Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:54:56.416008 lava-dispatcher, installed at version: 2024.01
2 01:54:56.416808 start: 0 validate
3 01:54:56.417286 Start time: 2024-11-09 01:54:56.417256+00:00 (UTC)
4 01:54:56.417836 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:54:56.418376 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 01:54:56.455813 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:54:56.456402 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-272-gda4373fbcf006%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 01:54:56.486485 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:54:56.487284 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-272-gda4373fbcf006%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:55:10.584123 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:55:10.584639 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-272-gda4373fbcf006%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 01:55:11.640805 validate duration: 15.22
14 01:55:11.641664 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:55:11.642014 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:55:11.642334 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:55:11.642931 Not decompressing ramdisk as can be used compressed.
18 01:55:11.643372 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 01:55:11.643621 saving as /var/lib/lava/dispatcher/tmp/964182/tftp-deploy-dclp5fw8/ramdisk/rootfs.cpio.gz
20 01:55:11.643880 total size: 8181887 (7 MB)
21 01:55:11.684253 progress 0 % (0 MB)
22 01:55:11.690092 progress 5 % (0 MB)
23 01:55:11.695433 progress 10 % (0 MB)
24 01:55:11.701106 progress 15 % (1 MB)
25 01:55:11.706396 progress 20 % (1 MB)
26 01:55:11.712124 progress 25 % (1 MB)
27 01:55:11.717342 progress 30 % (2 MB)
28 01:55:11.723007 progress 35 % (2 MB)
29 01:55:11.728282 progress 40 % (3 MB)
30 01:55:11.733949 progress 45 % (3 MB)
31 01:55:11.739103 progress 50 % (3 MB)
32 01:55:11.744772 progress 55 % (4 MB)
33 01:55:11.749858 progress 60 % (4 MB)
34 01:55:11.755214 progress 65 % (5 MB)
35 01:55:11.760233 progress 70 % (5 MB)
36 01:55:11.765619 progress 75 % (5 MB)
37 01:55:11.770591 progress 80 % (6 MB)
38 01:55:11.775934 progress 85 % (6 MB)
39 01:55:11.780728 progress 90 % (7 MB)
40 01:55:11.785842 progress 95 % (7 MB)
41 01:55:11.790734 progress 100 % (7 MB)
42 01:55:11.791386 7 MB downloaded in 0.15 s (52.91 MB/s)
43 01:55:11.791922 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:55:11.792842 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:55:11.793131 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:55:11.793399 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:55:11.793877 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-272-gda4373fbcf006/arm64/defconfig+debug/gcc-12/kernel/Image
49 01:55:11.794117 saving as /var/lib/lava/dispatcher/tmp/964182/tftp-deploy-dclp5fw8/kernel/Image
50 01:55:11.794326 total size: 169937408 (162 MB)
51 01:55:11.794536 No compression specified
52 01:55:11.828456 progress 0 % (0 MB)
53 01:55:11.930058 progress 5 % (8 MB)
54 01:55:12.030693 progress 10 % (16 MB)
55 01:55:12.129503 progress 15 % (24 MB)
56 01:55:12.229200 progress 20 % (32 MB)
57 01:55:12.328011 progress 25 % (40 MB)
58 01:55:12.427148 progress 30 % (48 MB)
59 01:55:12.526066 progress 35 % (56 MB)
60 01:55:12.646552 progress 40 % (64 MB)
61 01:55:12.765789 progress 45 % (72 MB)
62 01:55:12.869319 progress 50 % (81 MB)
63 01:55:12.966597 progress 55 % (89 MB)
64 01:55:13.065081 progress 60 % (97 MB)
65 01:55:13.164633 progress 65 % (105 MB)
66 01:55:13.264320 progress 70 % (113 MB)
67 01:55:13.362050 progress 75 % (121 MB)
68 01:55:13.459791 progress 80 % (129 MB)
69 01:55:13.558351 progress 85 % (137 MB)
70 01:55:13.656717 progress 90 % (145 MB)
71 01:55:13.754290 progress 95 % (153 MB)
72 01:55:13.851249 progress 100 % (162 MB)
73 01:55:13.851842 162 MB downloaded in 2.06 s (78.77 MB/s)
74 01:55:13.852374 end: 1.2.1 http-download (duration 00:00:02) [common]
76 01:55:13.853228 end: 1.2 download-retry (duration 00:00:02) [common]
77 01:55:13.853527 start: 1.3 download-retry (timeout 00:09:58) [common]
78 01:55:13.853808 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 01:55:13.854470 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-272-gda4373fbcf006/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 01:55:13.854781 saving as /var/lib/lava/dispatcher/tmp/964182/tftp-deploy-dclp5fw8/dtb/meson-g12b-a311d-libretech-cc.dtb
81 01:55:13.854999 total size: 54703 (0 MB)
82 01:55:13.855215 No compression specified
83 01:55:13.890283 progress 59 % (0 MB)
84 01:55:13.891356 progress 100 % (0 MB)
85 01:55:13.892104 0 MB downloaded in 0.04 s (1.41 MB/s)
86 01:55:13.892715 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:55:13.893766 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:55:13.894117 start: 1.4 download-retry (timeout 00:09:58) [common]
90 01:55:13.894456 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 01:55:13.895190 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-272-gda4373fbcf006/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 01:55:13.895541 saving as /var/lib/lava/dispatcher/tmp/964182/tftp-deploy-dclp5fw8/modules/modules.tar
93 01:55:13.895804 total size: 27651088 (26 MB)
94 01:55:13.896108 Using unxz to decompress xz
95 01:55:13.946409 progress 0 % (0 MB)
96 01:55:14.146673 progress 5 % (1 MB)
97 01:55:14.346245 progress 10 % (2 MB)
98 01:55:14.577872 progress 15 % (3 MB)
99 01:55:14.814797 progress 20 % (5 MB)
100 01:55:15.014373 progress 25 % (6 MB)
101 01:55:15.221070 progress 30 % (7 MB)
102 01:55:15.426805 progress 35 % (9 MB)
103 01:55:15.624451 progress 40 % (10 MB)
104 01:55:15.824431 progress 45 % (11 MB)
105 01:55:16.042206 progress 50 % (13 MB)
106 01:55:16.250438 progress 55 % (14 MB)
107 01:55:16.468572 progress 60 % (15 MB)
108 01:55:16.675835 progress 65 % (17 MB)
109 01:55:16.878635 progress 70 % (18 MB)
110 01:55:17.097448 progress 75 % (19 MB)
111 01:55:17.305341 progress 80 % (21 MB)
112 01:55:17.522845 progress 85 % (22 MB)
113 01:55:17.730524 progress 90 % (23 MB)
114 01:55:17.930354 progress 95 % (25 MB)
115 01:55:18.130561 progress 100 % (26 MB)
116 01:55:18.144886 26 MB downloaded in 4.25 s (6.21 MB/s)
117 01:55:18.145801 end: 1.4.1 http-download (duration 00:00:04) [common]
119 01:55:18.148914 end: 1.4 download-retry (duration 00:00:04) [common]
120 01:55:18.149629 start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
121 01:55:18.150789 start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
122 01:55:18.151090 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:55:18.151368 start: 1.5.2 lava-overlay (timeout 00:09:53) [common]
124 01:55:18.154642 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z
125 01:55:18.157148 makedir: /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin
126 01:55:18.157844 makedir: /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/tests
127 01:55:18.158873 makedir: /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/results
128 01:55:18.159594 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-add-keys
129 01:55:18.163066 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-add-sources
130 01:55:18.165559 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-background-process-start
131 01:55:18.167453 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-background-process-stop
132 01:55:18.169200 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-common-functions
133 01:55:18.170856 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-echo-ipv4
134 01:55:18.173073 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-install-packages
135 01:55:18.175683 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-installed-packages
136 01:55:18.177300 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-os-build
137 01:55:18.178857 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-probe-channel
138 01:55:18.180590 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-probe-ip
139 01:55:18.181536 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-target-ip
140 01:55:18.182431 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-target-mac
141 01:55:18.183066 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-target-storage
142 01:55:18.184440 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-test-case
143 01:55:18.186927 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-test-event
144 01:55:18.188591 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-test-feedback
145 01:55:18.189302 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-test-raise
146 01:55:18.189885 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-test-reference
147 01:55:18.190463 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-test-runner
148 01:55:18.191103 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-test-set
149 01:55:18.191700 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-test-shell
150 01:55:18.192324 Updating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-install-packages (oe)
151 01:55:18.193423 Updating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/bin/lava-installed-packages (oe)
152 01:55:18.194361 Creating /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/environment
153 01:55:18.194872 LAVA metadata
154 01:55:18.195183 - LAVA_JOB_ID=964182
155 01:55:18.195425 - LAVA_DISPATCHER_IP=192.168.6.2
156 01:55:18.195840 start: 1.5.2.1 ssh-authorize (timeout 00:09:53) [common]
157 01:55:18.197021 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 01:55:18.197386 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:53) [common]
159 01:55:18.197616 skipped lava-vland-overlay
160 01:55:18.197881 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 01:55:18.198163 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:53) [common]
162 01:55:18.198402 skipped lava-multinode-overlay
163 01:55:18.198666 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 01:55:18.198941 start: 1.5.2.4 test-definition (timeout 00:09:53) [common]
165 01:55:18.199222 Loading test definitions
166 01:55:18.199534 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:53) [common]
167 01:55:18.199775 Using /lava-964182 at stage 0
168 01:55:18.201235 uuid=964182_1.5.2.4.1 testdef=None
169 01:55:18.201613 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 01:55:18.201911 start: 1.5.2.4.2 test-overlay (timeout 00:09:53) [common]
171 01:55:18.203931 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 01:55:18.204885 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:53) [common]
174 01:55:18.207534 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 01:55:18.208499 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:53) [common]
177 01:55:18.211358 runner path: /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/0/tests/0_dmesg test_uuid 964182_1.5.2.4.1
178 01:55:18.212119 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 01:55:18.212975 Creating lava-test-runner.conf files
181 01:55:18.213197 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/964182/lava-overlay-1uoivj1z/lava-964182/0 for stage 0
182 01:55:18.213620 - 0_dmesg
183 01:55:18.214059 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 01:55:18.214373 start: 1.5.2.5 compress-overlay (timeout 00:09:53) [common]
185 01:55:18.243139 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 01:55:18.243622 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:53) [common]
187 01:55:18.243952 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 01:55:18.244334 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 01:55:18.244697 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
190 01:55:19.215381 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 01:55:19.215873 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
192 01:55:19.216184 extracting modules file /var/lib/lava/dispatcher/tmp/964182/tftp-deploy-dclp5fw8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964182/extract-overlay-ramdisk-5vo00aid/ramdisk
193 01:55:20.962572 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 01:55:20.963108 start: 1.5.5 apply-overlay-tftp (timeout 00:09:51) [common]
195 01:55:20.963433 [common] Applying overlay /var/lib/lava/dispatcher/tmp/964182/compress-overlay-23i6u__x/overlay-1.5.2.5.tar.gz to ramdisk
196 01:55:20.963695 [common] Applying overlay /var/lib/lava/dispatcher/tmp/964182/compress-overlay-23i6u__x/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/964182/extract-overlay-ramdisk-5vo00aid/ramdisk
197 01:55:20.994368 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 01:55:20.994811 start: 1.5.6 prepare-kernel (timeout 00:09:51) [common]
199 01:55:20.995083 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:51) [common]
200 01:55:20.995313 Converting downloaded kernel to a uImage
201 01:55:20.995623 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/964182/tftp-deploy-dclp5fw8/kernel/Image /var/lib/lava/dispatcher/tmp/964182/tftp-deploy-dclp5fw8/kernel/uImage
202 01:55:22.690208 output: Image Name:
203 01:55:22.690639 output: Created: Sat Nov 9 01:55:20 2024
204 01:55:22.690868 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 01:55:22.691087 output: Data Size: 169937408 Bytes = 165954.50 KiB = 162.06 MiB
206 01:55:22.691303 output: Load Address: 01080000
207 01:55:22.691535 output: Entry Point: 01080000
208 01:55:22.691753 output:
209 01:55:22.692155 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 01:55:22.692463 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 01:55:22.692749 start: 1.5.7 configure-preseed-file (timeout 00:09:49) [common]
212 01:55:22.693007 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 01:55:22.693400 start: 1.5.8 compress-ramdisk (timeout 00:09:49) [common]
214 01:55:22.693684 Building ramdisk /var/lib/lava/dispatcher/tmp/964182/extract-overlay-ramdisk-5vo00aid/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/964182/extract-overlay-ramdisk-5vo00aid/ramdisk
215 01:55:28.879603 >> 441555 blocks
216 01:55:47.286228 Adding RAMdisk u-boot header.
217 01:55:47.286824 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/964182/extract-overlay-ramdisk-5vo00aid/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/964182/extract-overlay-ramdisk-5vo00aid/ramdisk.cpio.gz.uboot
218 01:55:47.822121 output: Image Name:
219 01:55:47.822553 output: Created: Sat Nov 9 01:55:47 2024
220 01:55:47.823038 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 01:55:47.823454 output: Data Size: 53588562 Bytes = 52332.58 KiB = 51.11 MiB
222 01:55:47.823876 output: Load Address: 00000000
223 01:55:47.824343 output: Entry Point: 00000000
224 01:55:47.824746 output:
225 01:55:47.825848 rename /var/lib/lava/dispatcher/tmp/964182/extract-overlay-ramdisk-5vo00aid/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/964182/tftp-deploy-dclp5fw8/ramdisk/ramdisk.cpio.gz.uboot
226 01:55:47.826567 end: 1.5.8 compress-ramdisk (duration 00:00:25) [common]
227 01:55:47.827125 end: 1.5 prepare-tftp-overlay (duration 00:00:30) [common]
228 01:55:47.827658 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:24) [common]
229 01:55:47.828161 No LXC device requested
230 01:55:47.828676 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 01:55:47.829197 start: 1.7 deploy-device-env (timeout 00:09:24) [common]
232 01:55:47.829699 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 01:55:47.830114 Checking files for TFTP limit of 4294967296 bytes.
234 01:55:47.832809 end: 1 tftp-deploy (duration 00:00:36) [common]
235 01:55:47.833409 start: 2 uboot-action (timeout 00:05:00) [common]
236 01:55:47.833951 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 01:55:47.834456 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 01:55:47.834963 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 01:55:47.835506 Using kernel file from prepare-kernel: 964182/tftp-deploy-dclp5fw8/kernel/uImage
240 01:55:47.836168 substitutions:
241 01:55:47.836600 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 01:55:47.837010 - {DTB_ADDR}: 0x01070000
243 01:55:47.837413 - {DTB}: 964182/tftp-deploy-dclp5fw8/dtb/meson-g12b-a311d-libretech-cc.dtb
244 01:55:47.837814 - {INITRD}: 964182/tftp-deploy-dclp5fw8/ramdisk/ramdisk.cpio.gz.uboot
245 01:55:47.838211 - {KERNEL_ADDR}: 0x01080000
246 01:55:47.838606 - {KERNEL}: 964182/tftp-deploy-dclp5fw8/kernel/uImage
247 01:55:47.839005 - {LAVA_MAC}: None
248 01:55:47.839438 - {PRESEED_CONFIG}: None
249 01:55:47.839840 - {PRESEED_LOCAL}: None
250 01:55:47.840268 - {RAMDISK_ADDR}: 0x08000000
251 01:55:47.840661 - {RAMDISK}: 964182/tftp-deploy-dclp5fw8/ramdisk/ramdisk.cpio.gz.uboot
252 01:55:47.841060 - {ROOT_PART}: None
253 01:55:47.841454 - {ROOT}: None
254 01:55:47.841844 - {SERVER_IP}: 192.168.6.2
255 01:55:47.842238 - {TEE_ADDR}: 0x83000000
256 01:55:47.842629 - {TEE}: None
257 01:55:47.843019 Parsed boot commands:
258 01:55:47.843401 - setenv autoload no
259 01:55:47.843789 - setenv initrd_high 0xffffffff
260 01:55:47.844204 - setenv fdt_high 0xffffffff
261 01:55:47.844594 - dhcp
262 01:55:47.844986 - setenv serverip 192.168.6.2
263 01:55:47.845376 - tftpboot 0x01080000 964182/tftp-deploy-dclp5fw8/kernel/uImage
264 01:55:47.845769 - tftpboot 0x08000000 964182/tftp-deploy-dclp5fw8/ramdisk/ramdisk.cpio.gz.uboot
265 01:55:47.846156 - tftpboot 0x01070000 964182/tftp-deploy-dclp5fw8/dtb/meson-g12b-a311d-libretech-cc.dtb
266 01:55:47.846544 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 01:55:47.846942 - bootm 0x01080000 0x08000000 0x01070000
268 01:55:47.847451 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 01:55:47.849003 start: 2.3 connect-device (timeout 00:05:00) [common]
271 01:55:47.849465 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 01:55:47.864272 Setting prompt string to ['lava-test: # ']
273 01:55:47.865773 end: 2.3 connect-device (duration 00:00:00) [common]
274 01:55:47.866396 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 01:55:47.867210 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 01:55:47.867866 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 01:55:47.869095 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 01:55:47.908357 >> OK - accepted request
279 01:55:47.910279 Returned 0 in 0 seconds
280 01:55:48.011432 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 01:55:48.013190 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 01:55:48.013769 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 01:55:48.014475 Setting prompt string to ['Hit any key to stop autoboot']
285 01:55:48.014961 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 01:55:48.016600 Trying 192.168.56.21...
287 01:55:48.017094 Connected to conserv1.
288 01:55:48.017509 Escape character is '^]'.
289 01:55:48.017922
290 01:55:48.018348 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 01:55:48.018786
292 01:55:59.013844 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 01:55:59.014280 bl2_stage_init 0x01
294 01:55:59.014504 bl2_stage_init 0x81
295 01:55:59.019416 hw id: 0x0000 - pwm id 0x01
296 01:55:59.020046 bl2_stage_init 0xc1
297 01:55:59.020479 bl2_stage_init 0x02
298 01:55:59.020891
299 01:55:59.024891 L0:00000000
300 01:55:59.025234 L1:20000703
301 01:55:59.025482 L2:00008067
302 01:55:59.025712 L3:14000000
303 01:55:59.027846 B2:00402000
304 01:55:59.028223 B1:e0f83180
305 01:55:59.028444
306 01:55:59.028643 TE: 58124
307 01:55:59.028839
308 01:55:59.039081 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 01:55:59.039615
310 01:55:59.040159 Board ID = 1
311 01:55:59.040585 Set A53 clk to 24M
312 01:55:59.040975 Set A73 clk to 24M
313 01:55:59.044709 Set clk81 to 24M
314 01:55:59.045155 A53 clk: 1200 MHz
315 01:55:59.045544 A73 clk: 1200 MHz
316 01:55:59.048239 CLK81: 166.6M
317 01:55:59.048671 smccc: 00012a92
318 01:55:59.053697 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 01:55:59.059315 board id: 1
320 01:55:59.064588 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 01:55:59.074918 fw parse done
322 01:55:59.080954 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 01:55:59.123580 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 01:55:59.134441 PIEI prepare done
325 01:55:59.134888 fastboot data load
326 01:55:59.135282 fastboot data verify
327 01:55:59.140158 verify result: 266
328 01:55:59.145715 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 01:55:59.146161 LPDDR4 probe
330 01:55:59.146556 ddr clk to 1584MHz
331 01:55:59.153744 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 01:55:59.191051
333 01:55:59.191606 dmc_version 0001
334 01:55:59.197658 Check phy result
335 01:55:59.203513 INFO : End of CA training
336 01:55:59.203977 INFO : End of initialization
337 01:55:59.209104 INFO : Training has run successfully!
338 01:55:59.209536 Check phy result
339 01:55:59.214748 INFO : End of initialization
340 01:55:59.215274 INFO : End of read enable training
341 01:55:59.220331 INFO : End of fine write leveling
342 01:55:59.225942 INFO : End of Write leveling coarse delay
343 01:55:59.226390 INFO : Training has run successfully!
344 01:55:59.226789 Check phy result
345 01:55:59.231496 INFO : End of initialization
346 01:55:59.231927 INFO : End of read dq deskew training
347 01:55:59.237114 INFO : End of MPR read delay center optimization
348 01:55:59.242698 INFO : End of write delay center optimization
349 01:55:59.248345 INFO : End of read delay center optimization
350 01:55:59.248862 INFO : End of max read latency training
351 01:55:59.253884 INFO : Training has run successfully!
352 01:55:59.254335 1D training succeed
353 01:55:59.263102 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 01:55:59.310692 Check phy result
355 01:55:59.311256 INFO : End of initialization
356 01:55:59.333294 INFO : End of 2D read delay Voltage center optimization
357 01:55:59.353486 INFO : End of 2D read delay Voltage center optimization
358 01:55:59.405658 INFO : End of 2D write delay Voltage center optimization
359 01:55:59.454954 INFO : End of 2D write delay Voltage center optimization
360 01:55:59.460426 INFO : Training has run successfully!
361 01:55:59.460925
362 01:55:59.461348 channel==0
363 01:55:59.466017 RxClkDly_Margin_A0==88 ps 9
364 01:55:59.466478 TxDqDly_Margin_A0==98 ps 10
365 01:55:59.471623 RxClkDly_Margin_A1==88 ps 9
366 01:55:59.472123 TxDqDly_Margin_A1==98 ps 10
367 01:55:59.472546 TrainedVREFDQ_A0==74
368 01:55:59.477257 TrainedVREFDQ_A1==74
369 01:55:59.477793 VrefDac_Margin_A0==25
370 01:55:59.478218 DeviceVref_Margin_A0==40
371 01:55:59.482818 VrefDac_Margin_A1==25
372 01:55:59.483297 DeviceVref_Margin_A1==40
373 01:55:59.483713
374 01:55:59.484159
375 01:55:59.488426 channel==1
376 01:55:59.488888 RxClkDly_Margin_A0==98 ps 10
377 01:55:59.489296 TxDqDly_Margin_A0==88 ps 9
378 01:55:59.494059 RxClkDly_Margin_A1==98 ps 10
379 01:55:59.494519 TxDqDly_Margin_A1==88 ps 9
380 01:55:59.499610 TrainedVREFDQ_A0==75
381 01:55:59.499975 TrainedVREFDQ_A1==77
382 01:55:59.500256 VrefDac_Margin_A0==22
383 01:55:59.505257 DeviceVref_Margin_A0==38
384 01:55:59.505605 VrefDac_Margin_A1==23
385 01:55:59.510812 DeviceVref_Margin_A1==37
386 01:55:59.511132
387 01:55:59.511367 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 01:55:59.511587
389 01:55:59.544393 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 01:55:59.544854 2D training succeed
391 01:55:59.550012 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 01:55:59.555633 auto size-- 65535DDR cs0 size: 2048MB
393 01:55:59.555952 DDR cs1 size: 2048MB
394 01:55:59.561197 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 01:55:59.561509 cs0 DataBus test pass
396 01:55:59.566830 cs1 DataBus test pass
397 01:55:59.567209 cs0 AddrBus test pass
398 01:55:59.567523 cs1 AddrBus test pass
399 01:55:59.567767
400 01:55:59.572358 100bdlr_step_size ps== 420
401 01:55:59.572632 result report
402 01:55:59.577953 boot times 0Enable ddr reg access
403 01:55:59.583333 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 01:55:59.596791 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 01:56:00.170549 0.0;M3 CHK:0;cm4_sp_mode 0
406 01:56:00.171214 MVN_1=0x00000000
407 01:56:00.176074 MVN_2=0x00000000
408 01:56:00.181767 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 01:56:00.182218 OPS=0x10
410 01:56:00.182633 ring efuse init
411 01:56:00.183031 chipver efuse init
412 01:56:00.187366 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 01:56:00.193022 [0.018961 Inits done]
414 01:56:00.193482 secure task start!
415 01:56:00.193896 high task start!
416 01:56:00.196558 low task start!
417 01:56:00.197027 run into bl31
418 01:56:00.204268 NOTICE: BL31: v1.3(release):4fc40b1
419 01:56:00.211103 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 01:56:00.211597 NOTICE: BL31: G12A normal boot!
421 01:56:00.237454 NOTICE: BL31: BL33 decompress pass
422 01:56:00.243061 ERROR: Error initializing runtime service opteed_fast
423 01:56:01.475922
424 01:56:01.476376
425 01:56:01.484327 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 01:56:01.484766
427 01:56:01.485080 Model: Libre Computer AML-A311D-CC Alta
428 01:56:01.692898 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 01:56:01.716213 DRAM: 2 GiB (effective 3.8 GiB)
430 01:56:01.859279 Core: 408 devices, 31 uclasses, devicetree: separate
431 01:56:01.865112 WDT: Not starting watchdog@f0d0
432 01:56:01.897381 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 01:56:01.909792 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 01:56:01.914742 ** Bad device specification mmc 0 **
435 01:56:01.925108 Card did not respond to voltage select! : -110
436 01:56:01.932752 ** Bad device specification mmc 0 **
437 01:56:01.933195 Couldn't find partition mmc 0
438 01:56:01.941086 Card did not respond to voltage select! : -110
439 01:56:01.946577 ** Bad device specification mmc 0 **
440 01:56:01.947033 Couldn't find partition mmc 0
441 01:56:01.951682 Error: could not access storage.
442 01:56:03.264125 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 01:56:03.264533 bl2_stage_init 0x01
444 01:56:03.264760 bl2_stage_init 0x81
445 01:56:03.269701 hw id: 0x0000 - pwm id 0x01
446 01:56:03.270006 bl2_stage_init 0xc1
447 01:56:03.270222 bl2_stage_init 0x02
448 01:56:03.270428
449 01:56:03.275264 L0:00000000
450 01:56:03.275561 L1:20000703
451 01:56:03.275774 L2:00008067
452 01:56:03.276011 L3:14000000
453 01:56:03.280853 B2:00402000
454 01:56:03.281145 B1:e0f83180
455 01:56:03.281354
456 01:56:03.281566 TE: 58124
457 01:56:03.281770
458 01:56:03.286480 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 01:56:03.286783
460 01:56:03.286993 Board ID = 1
461 01:56:03.292016 Set A53 clk to 24M
462 01:56:03.292321 Set A73 clk to 24M
463 01:56:03.292526 Set clk81 to 24M
464 01:56:03.297699 A53 clk: 1200 MHz
465 01:56:03.298127 A73 clk: 1200 MHz
466 01:56:03.298445 CLK81: 166.6M
467 01:56:03.298749 smccc: 00012a92
468 01:56:03.303252 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 01:56:03.308859 board id: 1
470 01:56:03.314746 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 01:56:03.325430 fw parse done
472 01:56:03.331353 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 01:56:03.374008 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 01:56:03.384937 PIEI prepare done
475 01:56:03.385287 fastboot data load
476 01:56:03.385498 fastboot data verify
477 01:56:03.390560 verify result: 266
478 01:56:03.396151 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 01:56:03.396595 LPDDR4 probe
480 01:56:03.396923 ddr clk to 1584MHz
481 01:56:03.404118 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 01:56:03.441385
483 01:56:03.441778 dmc_version 0001
484 01:56:03.448077 Check phy result
485 01:56:03.453897 INFO : End of CA training
486 01:56:03.454343 INFO : End of initialization
487 01:56:03.459451 INFO : Training has run successfully!
488 01:56:03.459771 Check phy result
489 01:56:03.465117 INFO : End of initialization
490 01:56:03.465445 INFO : End of read enable training
491 01:56:03.470747 INFO : End of fine write leveling
492 01:56:03.476293 INFO : End of Write leveling coarse delay
493 01:56:03.476591 INFO : Training has run successfully!
494 01:56:03.476808 Check phy result
495 01:56:03.481831 INFO : End of initialization
496 01:56:03.482145 INFO : End of read dq deskew training
497 01:56:03.487491 INFO : End of MPR read delay center optimization
498 01:56:03.493116 INFO : End of write delay center optimization
499 01:56:03.498823 INFO : End of read delay center optimization
500 01:56:03.499147 INFO : End of max read latency training
501 01:56:03.504280 INFO : Training has run successfully!
502 01:56:03.504743 1D training succeed
503 01:56:03.512869 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 01:56:03.560427 Check phy result
505 01:56:03.560846 INFO : End of initialization
506 01:56:03.583386 INFO : End of 2D read delay Voltage center optimization
507 01:56:03.603196 INFO : End of 2D read delay Voltage center optimization
508 01:56:03.655100 INFO : End of 2D write delay Voltage center optimization
509 01:56:03.705390 INFO : End of 2D write delay Voltage center optimization
510 01:56:03.710907 INFO : Training has run successfully!
511 01:56:03.711209
512 01:56:03.711420 channel==0
513 01:56:03.716511 RxClkDly_Margin_A0==78 ps 8
514 01:56:03.716811 TxDqDly_Margin_A0==98 ps 10
515 01:56:03.722138 RxClkDly_Margin_A1==88 ps 9
516 01:56:03.722581 TxDqDly_Margin_A1==98 ps 10
517 01:56:03.722923 TrainedVREFDQ_A0==74
518 01:56:03.727771 TrainedVREFDQ_A1==74
519 01:56:03.728108 VrefDac_Margin_A0==26
520 01:56:03.728329 DeviceVref_Margin_A0==40
521 01:56:03.733328 VrefDac_Margin_A1==25
522 01:56:03.733624 DeviceVref_Margin_A1==40
523 01:56:03.733837
524 01:56:03.734053
525 01:56:03.738903 channel==1
526 01:56:03.739188 RxClkDly_Margin_A0==98 ps 10
527 01:56:03.739399 TxDqDly_Margin_A0==98 ps 10
528 01:56:03.744506 RxClkDly_Margin_A1==98 ps 10
529 01:56:03.744797 TxDqDly_Margin_A1==88 ps 9
530 01:56:03.750137 TrainedVREFDQ_A0==77
531 01:56:03.750439 TrainedVREFDQ_A1==77
532 01:56:03.750650 VrefDac_Margin_A0==22
533 01:56:03.755804 DeviceVref_Margin_A0==37
534 01:56:03.756140 VrefDac_Margin_A1==23
535 01:56:03.761277 DeviceVref_Margin_A1==37
536 01:56:03.761592
537 01:56:03.761810 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 01:56:03.767040
539 01:56:03.794901 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
540 01:56:03.795299 2D training succeed
541 01:56:03.800534 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 01:56:03.806117 auto size-- 65535DDR cs0 size: 2048MB
543 01:56:03.806479 DDR cs1 size: 2048MB
544 01:56:03.811796 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 01:56:03.812175 cs0 DataBus test pass
546 01:56:03.817306 cs1 DataBus test pass
547 01:56:03.817658 cs0 AddrBus test pass
548 01:56:03.817902 cs1 AddrBus test pass
549 01:56:03.818123
550 01:56:03.823063 100bdlr_step_size ps== 420
551 01:56:03.823439 result report
552 01:56:03.828614 boot times 0Enable ddr reg access
553 01:56:03.833678 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 01:56:03.846940 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 01:56:04.421274 0.0;M3 CHK:0;cm4_sp_mode 0
556 01:56:04.421719 MVN_1=0x00000000
557 01:56:04.426823 MVN_2=0x00000000
558 01:56:04.432587 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 01:56:04.432884 OPS=0x10
560 01:56:04.433118 ring efuse init
561 01:56:04.433318 chipver efuse init
562 01:56:04.440723 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 01:56:04.441001 [0.018960 Inits done]
564 01:56:04.441203 secure task start!
565 01:56:04.448248 high task start!
566 01:56:04.448540 low task start!
567 01:56:04.448746 run into bl31
568 01:56:04.454905 NOTICE: BL31: v1.3(release):4fc40b1
569 01:56:04.461879 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 01:56:04.462133 NOTICE: BL31: G12A normal boot!
571 01:56:04.488237 NOTICE: BL31: BL33 decompress pass
572 01:56:04.493406 ERROR: Error initializing runtime service opteed_fast
573 01:56:05.726618
574 01:56:05.727036
575 01:56:05.734361 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 01:56:05.734638
577 01:56:05.734847 Model: Libre Computer AML-A311D-CC Alta
578 01:56:05.942702 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 01:56:05.965929 DRAM: 2 GiB (effective 3.8 GiB)
580 01:56:06.109855 Core: 408 devices, 31 uclasses, devicetree: separate
581 01:56:06.114766 WDT: Not starting watchdog@f0d0
582 01:56:06.148029 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 01:56:06.160471 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 01:56:06.165056 ** Bad device specification mmc 0 **
585 01:56:06.175727 Card did not respond to voltage select! : -110
586 01:56:06.183193 ** Bad device specification mmc 0 **
587 01:56:06.183545 Couldn't find partition mmc 0
588 01:56:06.191666 Card did not respond to voltage select! : -110
589 01:56:06.197230 ** Bad device specification mmc 0 **
590 01:56:06.197552 Couldn't find partition mmc 0
591 01:56:06.201992 Error: could not access storage.
592 01:56:06.544251 Net: eth0: ethernet@ff3f0000
593 01:56:06.544707 starting USB...
594 01:56:06.796661 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 01:56:06.797116 Starting the controller
596 01:56:06.802880 USB XHCI 1.10
597 01:56:08.514336 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 01:56:08.514855 bl2_stage_init 0x01
599 01:56:08.515121 bl2_stage_init 0x81
600 01:56:08.519909 hw id: 0x0000 - pwm id 0x01
601 01:56:08.520568 bl2_stage_init 0xc1
602 01:56:08.521001 bl2_stage_init 0x02
603 01:56:08.521291
604 01:56:08.525484 L0:00000000
605 01:56:08.526066 L1:20000703
606 01:56:08.526470 L2:00008067
607 01:56:08.526776 L3:14000000
608 01:56:08.531100 B2:00402000
609 01:56:08.531690 B1:e0f83180
610 01:56:08.532125
611 01:56:08.532417 TE: 58159
612 01:56:08.532657
613 01:56:08.536572 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 01:56:08.536868
615 01:56:08.537085 Board ID = 1
616 01:56:08.542147 Set A53 clk to 24M
617 01:56:08.542411 Set A73 clk to 24M
618 01:56:08.542623 Set clk81 to 24M
619 01:56:08.547777 A53 clk: 1200 MHz
620 01:56:08.548131 A73 clk: 1200 MHz
621 01:56:08.548349 CLK81: 166.6M
622 01:56:08.548555 smccc: 00012ab5
623 01:56:08.553348 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 01:56:08.558952 board id: 1
625 01:56:08.564795 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 01:56:08.575515 fw parse done
627 01:56:08.581523 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 01:56:08.624119 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 01:56:08.635015 PIEI prepare done
630 01:56:08.635489 fastboot data load
631 01:56:08.635904 fastboot data verify
632 01:56:08.640738 verify result: 266
633 01:56:08.646327 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 01:56:08.646807 LPDDR4 probe
635 01:56:08.647214 ddr clk to 1584MHz
636 01:56:08.654323 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 01:56:08.691669
638 01:56:08.692239 dmc_version 0001
639 01:56:08.698221 Check phy result
640 01:56:08.704105 INFO : End of CA training
641 01:56:08.704582 INFO : End of initialization
642 01:56:08.709719 INFO : Training has run successfully!
643 01:56:08.710194 Check phy result
644 01:56:08.715309 INFO : End of initialization
645 01:56:08.715787 INFO : End of read enable training
646 01:56:08.720952 INFO : End of fine write leveling
647 01:56:08.726536 INFO : End of Write leveling coarse delay
648 01:56:08.727018 INFO : Training has run successfully!
649 01:56:08.727427 Check phy result
650 01:56:08.732118 INFO : End of initialization
651 01:56:08.732584 INFO : End of read dq deskew training
652 01:56:08.737732 INFO : End of MPR read delay center optimization
653 01:56:08.743307 INFO : End of write delay center optimization
654 01:56:08.748927 INFO : End of read delay center optimization
655 01:56:08.749405 INFO : End of max read latency training
656 01:56:08.754554 INFO : Training has run successfully!
657 01:56:08.755026 1D training succeed
658 01:56:08.762906 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 01:56:08.811339 Check phy result
660 01:56:08.811859 INFO : End of initialization
661 01:56:08.833948 INFO : End of 2D read delay Voltage center optimization
662 01:56:08.854077 INFO : End of 2D read delay Voltage center optimization
663 01:56:08.905983 INFO : End of 2D write delay Voltage center optimization
664 01:56:08.955404 INFO : End of 2D write delay Voltage center optimization
665 01:56:08.960965 INFO : Training has run successfully!
666 01:56:08.961273
667 01:56:08.961499 channel==0
668 01:56:08.966559 RxClkDly_Margin_A0==88 ps 9
669 01:56:08.967238 TxDqDly_Margin_A0==98 ps 10
670 01:56:08.972178 RxClkDly_Margin_A1==88 ps 9
671 01:56:08.972581 TxDqDly_Margin_A1==98 ps 10
672 01:56:08.972906 TrainedVREFDQ_A0==74
673 01:56:08.977768 TrainedVREFDQ_A1==74
674 01:56:08.978087 VrefDac_Margin_A0==25
675 01:56:08.978303 DeviceVref_Margin_A0==40
676 01:56:08.983341 VrefDac_Margin_A1==25
677 01:56:08.983745 DeviceVref_Margin_A1==40
678 01:56:08.984098
679 01:56:08.984418
680 01:56:08.989455 channel==1
681 01:56:08.989862 RxClkDly_Margin_A0==98 ps 10
682 01:56:08.990105 TxDqDly_Margin_A0==98 ps 10
683 01:56:08.994548 RxClkDly_Margin_A1==98 ps 10
684 01:56:08.994846 TxDqDly_Margin_A1==98 ps 10
685 01:56:09.000181 TrainedVREFDQ_A0==77
686 01:56:09.000489 TrainedVREFDQ_A1==77
687 01:56:09.000701 VrefDac_Margin_A0==22
688 01:56:09.005752 DeviceVref_Margin_A0==37
689 01:56:09.006160 VrefDac_Margin_A1==22
690 01:56:09.011336 DeviceVref_Margin_A1==37
691 01:56:09.011727
692 01:56:09.012077 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 01:56:09.016991
694 01:56:09.045211 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 01:56:09.045953 2D training succeed
696 01:56:09.050768 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 01:56:09.056345 auto size-- 65535DDR cs0 size: 2048MB
698 01:56:09.056973 DDR cs1 size: 2048MB
699 01:56:09.061893 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 01:56:09.062495 cs0 DataBus test pass
701 01:56:09.067525 cs1 DataBus test pass
702 01:56:09.068171 cs0 AddrBus test pass
703 01:56:09.068700 cs1 AddrBus test pass
704 01:56:09.069194
705 01:56:09.073167 100bdlr_step_size ps== 420
706 01:56:09.073811 result report
707 01:56:09.078698 boot times 0Enable ddr reg access
708 01:56:09.084280 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 01:56:09.096844 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 01:56:09.671517 0.0;M3 CHK:0;cm4_sp_mode 0
711 01:56:09.672369 MVN_1=0x00000000
712 01:56:09.678108 MVN_2=0x00000000
713 01:56:09.682918 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 01:56:09.683594 OPS=0x10
715 01:56:09.684159 ring efuse init
716 01:56:09.684671 chipver efuse init
717 01:56:09.688460 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 01:56:09.693955 [0.018960 Inits done]
719 01:56:09.694520 secure task start!
720 01:56:09.695027 high task start!
721 01:56:09.698281 low task start!
722 01:56:09.698836 run into bl31
723 01:56:09.705113 NOTICE: BL31: v1.3(release):4fc40b1
724 01:56:09.712901 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 01:56:09.713490 NOTICE: BL31: G12A normal boot!
726 01:56:09.738815 NOTICE: BL31: BL33 decompress pass
727 01:56:09.744495 ERROR: Error initializing runtime service opteed_fast
728 01:56:10.977480
729 01:56:10.978287
730 01:56:10.985819 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 01:56:10.986440
732 01:56:10.986973 Model: Libre Computer AML-A311D-CC Alta
733 01:56:11.194398 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 01:56:11.217711 DRAM: 2 GiB (effective 3.8 GiB)
735 01:56:11.360758 Core: 408 devices, 31 uclasses, devicetree: separate
736 01:56:11.366449 WDT: Not starting watchdog@f0d0
737 01:56:11.398897 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 01:56:11.411295 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 01:56:11.416268 ** Bad device specification mmc 0 **
740 01:56:11.426489 Card did not respond to voltage select! : -110
741 01:56:11.434213 ** Bad device specification mmc 0 **
742 01:56:11.434835 Couldn't find partition mmc 0
743 01:56:11.442481 Card did not respond to voltage select! : -110
744 01:56:11.447971 ** Bad device specification mmc 0 **
745 01:56:11.448620 Couldn't find partition mmc 0
746 01:56:11.453055 Error: could not access storage.
747 01:56:11.795341 Net: eth0: ethernet@ff3f0000
748 01:56:11.796049 starting USB...
749 01:56:12.047343 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 01:56:12.047770 Starting the controller
751 01:56:12.054443 USB XHCI 1.10
752 01:56:14.214827 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 01:56:14.215504 bl2_stage_init 0x01
754 01:56:14.215973 bl2_stage_init 0x81
755 01:56:14.220255 hw id: 0x0000 - pwm id 0x01
756 01:56:14.220794 bl2_stage_init 0xc1
757 01:56:14.221249 bl2_stage_init 0x02
758 01:56:14.221697
759 01:56:14.225845 L0:00000000
760 01:56:14.226382 L1:20000703
761 01:56:14.226862 L2:00008067
762 01:56:14.227311 L3:14000000
763 01:56:14.231430 B2:00402000
764 01:56:14.231944 B1:e0f83180
765 01:56:14.232435
766 01:56:14.232881 TE: 58159
767 01:56:14.233324
768 01:56:14.237080 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 01:56:14.237601
770 01:56:14.238054 Board ID = 1
771 01:56:14.242710 Set A53 clk to 24M
772 01:56:14.243255 Set A73 clk to 24M
773 01:56:14.243712 Set clk81 to 24M
774 01:56:14.248385 A53 clk: 1200 MHz
775 01:56:14.248928 A73 clk: 1200 MHz
776 01:56:14.249379 CLK81: 166.6M
777 01:56:14.249826 smccc: 00012ab5
778 01:56:14.253966 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 01:56:14.259570 board id: 1
780 01:56:14.265462 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 01:56:14.276127 fw parse done
782 01:56:14.282022 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 01:56:14.324500 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 01:56:14.335452 PIEI prepare done
785 01:56:14.336083 fastboot data load
786 01:56:14.336562 fastboot data verify
787 01:56:14.341071 verify result: 266
788 01:56:14.346727 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 01:56:14.347340 LPDDR4 probe
790 01:56:14.347798 ddr clk to 1584MHz
791 01:56:14.354658 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 01:56:14.391815
793 01:56:14.392282 dmc_version 0001
794 01:56:14.398447 Check phy result
795 01:56:14.404309 INFO : End of CA training
796 01:56:14.404656 INFO : End of initialization
797 01:56:14.410118 INFO : Training has run successfully!
798 01:56:14.410468 Check phy result
799 01:56:14.415459 INFO : End of initialization
800 01:56:14.415925 INFO : End of read enable training
801 01:56:14.421002 INFO : End of fine write leveling
802 01:56:14.426613 INFO : End of Write leveling coarse delay
803 01:56:14.426894 INFO : Training has run successfully!
804 01:56:14.427118 Check phy result
805 01:56:14.432241 INFO : End of initialization
806 01:56:14.432515 INFO : End of read dq deskew training
807 01:56:14.437800 INFO : End of MPR read delay center optimization
808 01:56:14.443434 INFO : End of write delay center optimization
809 01:56:14.449015 INFO : End of read delay center optimization
810 01:56:14.449288 INFO : End of max read latency training
811 01:56:14.454616 INFO : Training has run successfully!
812 01:56:14.454887 1D training succeed
813 01:56:14.463784 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 01:56:14.511608 Check phy result
815 01:56:14.512236 INFO : End of initialization
816 01:56:14.533432 INFO : End of 2D read delay Voltage center optimization
817 01:56:14.553584 INFO : End of 2D read delay Voltage center optimization
818 01:56:14.605486 INFO : End of 2D write delay Voltage center optimization
819 01:56:14.654396 INFO : End of 2D write delay Voltage center optimization
820 01:56:14.659897 INFO : Training has run successfully!
821 01:56:14.660432
822 01:56:14.660888 channel==0
823 01:56:14.665461 RxClkDly_Margin_A0==88 ps 9
824 01:56:14.665979 TxDqDly_Margin_A0==98 ps 10
825 01:56:14.671043 RxClkDly_Margin_A1==88 ps 9
826 01:56:14.671543 TxDqDly_Margin_A1==98 ps 10
827 01:56:14.672029 TrainedVREFDQ_A0==74
828 01:56:14.676674 TrainedVREFDQ_A1==74
829 01:56:14.677212 VrefDac_Margin_A0==25
830 01:56:14.677640 DeviceVref_Margin_A0==40
831 01:56:14.682285 VrefDac_Margin_A1==25
832 01:56:14.682799 DeviceVref_Margin_A1==40
833 01:56:14.683222
834 01:56:14.683640
835 01:56:14.687857 channel==1
836 01:56:14.688404 RxClkDly_Margin_A0==88 ps 9
837 01:56:14.688837 TxDqDly_Margin_A0==98 ps 10
838 01:56:14.693460 RxClkDly_Margin_A1==98 ps 10
839 01:56:14.693958 TxDqDly_Margin_A1==98 ps 10
840 01:56:14.699047 TrainedVREFDQ_A0==77
841 01:56:14.699527 TrainedVREFDQ_A1==78
842 01:56:14.699945 VrefDac_Margin_A0==22
843 01:56:14.704648 DeviceVref_Margin_A0==37
844 01:56:14.705114 VrefDac_Margin_A1==22
845 01:56:14.710265 DeviceVref_Margin_A1==36
846 01:56:14.710746
847 01:56:14.711160 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 01:56:14.715820
849 01:56:14.743855 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000019 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
850 01:56:14.744411 2D training succeed
851 01:56:14.749456 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 01:56:14.755042 auto size-- 65535DDR cs0 size: 2048MB
853 01:56:14.755514 DDR cs1 size: 2048MB
854 01:56:14.760690 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 01:56:14.761190 cs0 DataBus test pass
856 01:56:14.766302 cs1 DataBus test pass
857 01:56:14.766743 cs0 AddrBus test pass
858 01:56:14.767135 cs1 AddrBus test pass
859 01:56:14.767521
860 01:56:14.771918 100bdlr_step_size ps== 420
861 01:56:14.772288 result report
862 01:56:14.777463 boot times 0Enable ddr reg access
863 01:56:14.782849 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 01:56:14.796481 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 01:56:15.368372 0.0;M3 CHK:0;cm4_sp_mode 0
866 01:56:15.368807 MVN_1=0x00000000
867 01:56:15.373872 MVN_2=0x00000000
868 01:56:15.379614 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 01:56:15.379948 OPS=0x10
870 01:56:15.380292 ring efuse init
871 01:56:15.380505 chipver efuse init
872 01:56:15.387799 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 01:56:15.388124 [0.018961 Inits done]
874 01:56:15.394542 secure task start!
875 01:56:15.394844 high task start!
876 01:56:15.395054 low task start!
877 01:56:15.395256 run into bl31
878 01:56:15.402078 NOTICE: BL31: v1.3(release):4fc40b1
879 01:56:15.409855 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 01:56:15.410180 NOTICE: BL31: G12A normal boot!
881 01:56:15.435380 NOTICE: BL31: BL33 decompress pass
882 01:56:15.440940 ERROR: Error initializing runtime service opteed_fast
883 01:56:16.673870
884 01:56:16.674488
885 01:56:16.682249 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 01:56:16.682749
887 01:56:16.683165 Model: Libre Computer AML-A311D-CC Alta
888 01:56:16.890725 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 01:56:16.914029 DRAM: 2 GiB (effective 3.8 GiB)
890 01:56:17.057088 Core: 408 devices, 31 uclasses, devicetree: separate
891 01:56:17.062854 WDT: Not starting watchdog@f0d0
892 01:56:17.095146 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 01:56:17.107554 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 01:56:17.112576 ** Bad device specification mmc 0 **
895 01:56:17.122892 Card did not respond to voltage select! : -110
896 01:56:17.130638 ** Bad device specification mmc 0 **
897 01:56:17.131153 Couldn't find partition mmc 0
898 01:56:17.138895 Card did not respond to voltage select! : -110
899 01:56:17.144373 ** Bad device specification mmc 0 **
900 01:56:17.144842 Couldn't find partition mmc 0
901 01:56:17.149468 Error: could not access storage.
902 01:56:17.493109 Net: eth0: ethernet@ff3f0000
903 01:56:17.493709 starting USB...
904 01:56:17.744813 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 01:56:17.745281 Starting the controller
906 01:56:17.751807 USB XHCI 1.10
907 01:56:19.614314 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 01:56:19.614770 bl2_stage_init 0x01
909 01:56:19.615010 bl2_stage_init 0x81
910 01:56:19.620056 hw id: 0x0000 - pwm id 0x01
911 01:56:19.620479 bl2_stage_init 0xc1
912 01:56:19.620718 bl2_stage_init 0x02
913 01:56:19.620941
914 01:56:19.625497 L0:00000000
915 01:56:19.626047 L1:20000703
916 01:56:19.626316 L2:00008067
917 01:56:19.626530 L3:14000000
918 01:56:19.628529 B2:00402000
919 01:56:19.628890 B1:e0f83180
920 01:56:19.629104
921 01:56:19.629318 TE: 58124
922 01:56:19.629521
923 01:56:19.639584 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 01:56:19.640042
925 01:56:19.640287 Board ID = 1
926 01:56:19.640514 Set A53 clk to 24M
927 01:56:19.640727 Set A73 clk to 24M
928 01:56:19.645307 Set clk81 to 24M
929 01:56:19.645672 A53 clk: 1200 MHz
930 01:56:19.645888 A73 clk: 1200 MHz
931 01:56:19.648940 CLK81: 166.6M
932 01:56:19.649307 smccc: 00012a92
933 01:56:19.654528 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 01:56:19.660092 board id: 1
935 01:56:19.664944 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 01:56:19.675663 fw parse done
937 01:56:19.681401 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 01:56:19.723167 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 01:56:19.735091 PIEI prepare done
940 01:56:19.735503 fastboot data load
941 01:56:19.735721 fastboot data verify
942 01:56:19.740697 verify result: 266
943 01:56:19.746284 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 01:56:19.746641 LPDDR4 probe
945 01:56:19.746852 ddr clk to 1584MHz
946 01:56:19.754257 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 01:56:19.790632
948 01:56:19.791053 dmc_version 0001
949 01:56:19.797448 Check phy result
950 01:56:19.810865 INFO : End of CA training
951 01:56:19.811291 INFO : End of initialization
952 01:56:19.811515 INFO : Training has run successfully!
953 01:56:19.811724 Check phy result
954 01:56:19.815281 INFO : End of initialization
955 01:56:19.815638 INFO : End of read enable training
956 01:56:19.820896 INFO : End of fine write leveling
957 01:56:19.826467 INFO : End of Write leveling coarse delay
958 01:56:19.827052 INFO : Training has run successfully!
959 01:56:19.827333 Check phy result
960 01:56:19.832143 INFO : End of initialization
961 01:56:19.832666 INFO : End of read dq deskew training
962 01:56:19.837673 INFO : End of MPR read delay center optimization
963 01:56:19.843348 INFO : End of write delay center optimization
964 01:56:19.848930 INFO : End of read delay center optimization
965 01:56:19.849466 INFO : End of max read latency training
966 01:56:19.854523 INFO : Training has run successfully!
967 01:56:19.854896 1D training succeed
968 01:56:19.862710 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 01:56:19.910361 Check phy result
970 01:56:19.911094 INFO : End of initialization
971 01:56:19.932090 INFO : End of 2D read delay Voltage center optimization
972 01:56:19.952431 INFO : End of 2D read delay Voltage center optimization
973 01:56:20.004363 INFO : End of 2D write delay Voltage center optimization
974 01:56:20.054767 INFO : End of 2D write delay Voltage center optimization
975 01:56:20.060271 INFO : Training has run successfully!
976 01:56:20.060647
977 01:56:20.060878 channel==0
978 01:56:20.066165 RxClkDly_Margin_A0==88 ps 9
979 01:56:20.066838 TxDqDly_Margin_A0==98 ps 10
980 01:56:20.071459 RxClkDly_Margin_A1==88 ps 9
981 01:56:20.071844 TxDqDly_Margin_A1==98 ps 10
982 01:56:20.072152 TrainedVREFDQ_A0==74
983 01:56:20.077034 TrainedVREFDQ_A1==74
984 01:56:20.077432 VrefDac_Margin_A0==25
985 01:56:20.077690 DeviceVref_Margin_A0==40
986 01:56:20.082611 VrefDac_Margin_A1==25
987 01:56:20.083007 DeviceVref_Margin_A1==40
988 01:56:20.083272
989 01:56:20.083515
990 01:56:20.088275 channel==1
991 01:56:20.089039 RxClkDly_Margin_A0==98 ps 10
992 01:56:20.089506 TxDqDly_Margin_A0==98 ps 10
993 01:56:20.093840 RxClkDly_Margin_A1==98 ps 10
994 01:56:20.094240 TxDqDly_Margin_A1==98 ps 10
995 01:56:20.099389 TrainedVREFDQ_A0==77
996 01:56:20.099800 TrainedVREFDQ_A1==77
997 01:56:20.100092 VrefDac_Margin_A0==22
998 01:56:20.105312 DeviceVref_Margin_A0==37
999 01:56:20.105971 VrefDac_Margin_A1==23
1000 01:56:20.110798 DeviceVref_Margin_A1==37
1001 01:56:20.111757
1002 01:56:20.112036 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 01:56:20.116253
1004 01:56:20.144357 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1005 01:56:20.144867 2D training succeed
1006 01:56:20.149829 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 01:56:20.155394 auto size-- 65535DDR cs0 size: 2048MB
1008 01:56:20.155812 DDR cs1 size: 2048MB
1009 01:56:20.161034 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 01:56:20.161434 cs0 DataBus test pass
1011 01:56:20.166588 cs1 DataBus test pass
1012 01:56:20.167546 cs0 AddrBus test pass
1013 01:56:20.167864 cs1 AddrBus test pass
1014 01:56:20.168123
1015 01:56:20.172219 100bdlr_step_size ps== 420
1016 01:56:20.172641 result report
1017 01:56:20.177774 boot times 0Enable ddr reg access
1018 01:56:20.182466 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 01:56:20.196218 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 01:56:20.770406 0.0;M3 CHK:0;cm4_sp_mode 0
1021 01:56:20.771048 MVN_1=0x00000000
1022 01:56:20.775898 MVN_2=0x00000000
1023 01:56:20.781781 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 01:56:20.782239 OPS=0x10
1025 01:56:20.782783 ring efuse init
1026 01:56:20.783017 chipver efuse init
1027 01:56:20.789864 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 01:56:20.790297 [0.018961 Inits done]
1029 01:56:20.796551 secure task start!
1030 01:56:20.797115 high task start!
1031 01:56:20.797487 low task start!
1032 01:56:20.797744 run into bl31
1033 01:56:20.804068 NOTICE: BL31: v1.3(release):4fc40b1
1034 01:56:20.811703 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 01:56:20.812228 NOTICE: BL31: G12A normal boot!
1036 01:56:20.837368 NOTICE: BL31: BL33 decompress pass
1037 01:56:20.842551 ERROR: Error initializing runtime service opteed_fast
1038 01:56:22.075812
1039 01:56:22.076271
1040 01:56:22.083379 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 01:56:22.083697
1042 01:56:22.083919 Model: Libre Computer AML-A311D-CC Alta
1043 01:56:22.292049 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 01:56:22.315417 DRAM: 2 GiB (effective 3.8 GiB)
1045 01:56:22.459056 Core: 408 devices, 31 uclasses, devicetree: separate
1046 01:56:22.464756 WDT: Not starting watchdog@f0d0
1047 01:56:22.497310 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 01:56:22.509918 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 01:56:22.514018 ** Bad device specification mmc 0 **
1050 01:56:22.525012 Card did not respond to voltage select! : -110
1051 01:56:22.531736 ** Bad device specification mmc 0 **
1052 01:56:22.532314 Couldn't find partition mmc 0
1053 01:56:22.540998 Card did not respond to voltage select! : -110
1054 01:56:22.546518 ** Bad device specification mmc 0 **
1055 01:56:22.546901 Couldn't find partition mmc 0
1056 01:56:22.551095 Error: could not access storage.
1057 01:56:22.893665 Net: eth0: ethernet@ff3f0000
1058 01:56:22.894082 starting USB...
1059 01:56:23.145811 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 01:56:23.146231 Starting the controller
1061 01:56:23.151860 USB XHCI 1.10
1062 01:56:24.709884 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 01:56:24.715252 scanning usb for storage devices... 0 Storage Device(s) found
1065 01:56:24.766901 Hit any key to stop autoboot: 1
1066 01:56:24.767840 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 01:56:24.768462 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1068 01:56:24.768931 Setting prompt string to ['=>']
1069 01:56:24.769403 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1070 01:56:24.770159 0
1071 01:56:24.771001 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 01:56:24.771489 Sending with 10 millisecond of delay
1074 01:56:25.908841 => setenv autoload no
1075 01:56:25.919638 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1076 01:56:25.924531
1077 01:56:25.925022 => setenv autoload no
1078 01:56:25.925718 Sending with 10 millisecond of delay
1080 01:56:27.723248 => setenv initrd_high 0xffffffff
1081 01:56:27.734056 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1082 01:56:27.734848 Sending with 10 millisecond of delay
1084 01:56:29.355308 setenv fdt_high 0xffffffff
1085 01:56:29.366050 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 01:56:29.366660 setenv initrd_high 0xffffffff
1087 01:56:29.366902 => setenv fdt_high 0xffffffff
1088 01:56:29.367427 Sending with 10 millisecond of delay
1090 01:56:29.659439 => dhcp
1091 01:56:29.670729 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1092 01:56:29.671962 Sending with 10 millisecond of delay
1094 01:56:31.349762 setenv serverip 192.168.6.2
1095 01:56:31.360314 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1096 01:56:31.360851 dhcp
1097 01:56:31.361092 Speed: 1000, full duplex
1098 01:56:31.361299 BOOTP broadcast 1
1099 01:56:31.361499 DHCP client bound to address 192.168.6.27 (8 ms)
1100 01:56:31.361696 => setenv serverip 192.168.6.2
1101 01:56:31.362127 Sending with 10 millisecond of delay
1103 01:56:35.089572 => tftpboot 0x01080000 964182/tftp-deploy-dclp5fw8/kernel/uImage
1104 01:56:35.100622 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1105 01:56:35.101667 Sending with 10 millisecond of delay
1107 01:56:39.791082 tftpboot 0x08000000 964182/tftp-deploy-dclp5fw8/ramdisk/ramdisk.cpio.gz.uboot
1108 01:56:39.801923 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:08)
1109 01:56:39.802781 tftpboot 0x01080000 964182/tftp-deploy-dclp5fw8/kernel/uImage
1110 01:56:39.803274 Speed: 1000, full duplex
1111 01:56:39.803721 Using ethernet@ff3f0000 device
1112 01:56:39.804212 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1113 01:56:39.804654 Filename '964182/tftp-deploy-dclp5fw8/kernel/uImage'.
1114 01:56:39.805088 Load address: 0x1080000
1115 01:56:39.805518 Loading: *###################
1116 01:56:39.805945 TFTP error: trying to overwrite reserved memory...
1117 01:56:39.806374 => z.uboot
1118 01:56:39.806801 Unknown command 'z.uboot' - try 'help'
1120 01:56:39.808240 end: 2.4.3 bootloader-commands (duration 00:00:15) [common]
1123 01:56:39.810138 end: 2.4 uboot-commands (duration 00:00:52) [common]
1125 01:56:39.811568 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
1127 01:56:39.812695 end: 2 uboot-action (duration 00:00:52) [common]
1129 01:56:39.814324 Cleaning after the job
1130 01:56:39.814912 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964182/tftp-deploy-dclp5fw8/ramdisk
1131 01:56:39.844761 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964182/tftp-deploy-dclp5fw8/kernel
1132 01:56:39.869265 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964182/tftp-deploy-dclp5fw8/dtb
1133 01:56:39.870182 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964182/tftp-deploy-dclp5fw8/modules
1134 01:56:39.885580 start: 4.1 power-off (timeout 00:00:30) [common]
1135 01:56:39.886286 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1136 01:56:39.920902 >> OK - accepted request
1137 01:56:39.922990 Returned 0 in 0 seconds
1138 01:56:40.023781 end: 4.1 power-off (duration 00:00:00) [common]
1140 01:56:40.024837 start: 4.2 read-feedback (timeout 00:10:00) [common]
1141 01:56:40.025491 Listened to connection for namespace 'common' for up to 1s
1142 01:56:41.026486 Finalising connection for namespace 'common'
1143 01:56:41.027289 Disconnecting from shell: Finalise
1144 01:56:41.027838 =>
1145 01:56:41.129027 end: 4.2 read-feedback (duration 00:00:01) [common]
1146 01:56:41.129770 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/964182
1147 01:56:41.430747 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/964182
1148 01:56:41.431362 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.