Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:55:56.168717 lava-dispatcher, installed at version: 2024.01
2 01:55:56.169517 start: 0 validate
3 01:55:56.170002 Start time: 2024-11-09 01:55:56.169971+00:00 (UTC)
4 01:55:56.170564 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:55:56.171103 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 01:55:56.205395 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:55:56.205977 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-272-gda4373fbcf006%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 01:55:56.237110 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:55:56.237779 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-272-gda4373fbcf006%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 01:55:57.281607 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:55:57.282128 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-272-gda4373fbcf006%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 01:55:57.321272 validate duration: 1.15
14 01:55:57.322131 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:55:57.322465 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:55:57.322777 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:55:57.323360 Not decompressing ramdisk as can be used compressed.
18 01:55:57.323787 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 01:55:57.324084 saving as /var/lib/lava/dispatcher/tmp/964177/tftp-deploy-hz767y9x/ramdisk/rootfs.cpio.gz
20 01:55:57.324366 total size: 8181887 (7 MB)
21 01:55:57.358171 progress 0 % (0 MB)
22 01:55:57.369860 progress 5 % (0 MB)
23 01:55:57.380057 progress 10 % (0 MB)
24 01:55:57.391889 progress 15 % (1 MB)
25 01:55:57.401174 progress 20 % (1 MB)
26 01:55:57.406960 progress 25 % (1 MB)
27 01:55:57.412617 progress 30 % (2 MB)
28 01:55:57.418394 progress 35 % (2 MB)
29 01:55:57.423886 progress 40 % (3 MB)
30 01:55:57.429745 progress 45 % (3 MB)
31 01:55:57.434797 progress 50 % (3 MB)
32 01:55:57.440282 progress 55 % (4 MB)
33 01:55:57.445375 progress 60 % (4 MB)
34 01:55:57.450874 progress 65 % (5 MB)
35 01:55:57.455959 progress 70 % (5 MB)
36 01:55:57.461344 progress 75 % (5 MB)
37 01:55:57.466530 progress 80 % (6 MB)
38 01:55:57.471903 progress 85 % (6 MB)
39 01:55:57.476675 progress 90 % (7 MB)
40 01:55:57.481754 progress 95 % (7 MB)
41 01:55:57.486468 progress 100 % (7 MB)
42 01:55:57.487095 7 MB downloaded in 0.16 s (47.96 MB/s)
43 01:55:57.487636 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:55:57.488938 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:55:57.489245 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:55:57.489519 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:55:57.489994 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-272-gda4373fbcf006/arm64/defconfig+debug/gcc-12/kernel/Image
49 01:55:57.490236 saving as /var/lib/lava/dispatcher/tmp/964177/tftp-deploy-hz767y9x/kernel/Image
50 01:55:57.490445 total size: 169937408 (162 MB)
51 01:55:57.490658 No compression specified
52 01:55:57.522931 progress 0 % (0 MB)
53 01:55:57.635596 progress 5 % (8 MB)
54 01:55:57.756612 progress 10 % (16 MB)
55 01:55:57.877330 progress 15 % (24 MB)
56 01:55:57.998751 progress 20 % (32 MB)
57 01:55:58.120556 progress 25 % (40 MB)
58 01:55:58.240782 progress 30 % (48 MB)
59 01:55:58.361319 progress 35 % (56 MB)
60 01:55:58.481839 progress 40 % (64 MB)
61 01:55:58.603605 progress 45 % (72 MB)
62 01:55:58.724727 progress 50 % (81 MB)
63 01:55:58.847921 progress 55 % (89 MB)
64 01:55:58.967947 progress 60 % (97 MB)
65 01:55:59.089035 progress 65 % (105 MB)
66 01:55:59.210159 progress 70 % (113 MB)
67 01:55:59.330116 progress 75 % (121 MB)
68 01:55:59.453058 progress 80 % (129 MB)
69 01:55:59.575102 progress 85 % (137 MB)
70 01:55:59.696538 progress 90 % (145 MB)
71 01:55:59.808071 progress 95 % (153 MB)
72 01:55:59.908360 progress 100 % (162 MB)
73 01:55:59.908935 162 MB downloaded in 2.42 s (67.01 MB/s)
74 01:55:59.909432 end: 1.2.1 http-download (duration 00:00:02) [common]
76 01:55:59.910251 end: 1.2 download-retry (duration 00:00:02) [common]
77 01:55:59.910531 start: 1.3 download-retry (timeout 00:09:57) [common]
78 01:55:59.910798 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 01:55:59.911268 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-272-gda4373fbcf006/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 01:55:59.911543 saving as /var/lib/lava/dispatcher/tmp/964177/tftp-deploy-hz767y9x/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 01:55:59.911753 total size: 53209 (0 MB)
82 01:55:59.911964 No compression specified
83 01:55:59.952298 progress 61 % (0 MB)
84 01:55:59.953330 progress 100 % (0 MB)
85 01:55:59.953975 0 MB downloaded in 0.04 s (1.20 MB/s)
86 01:55:59.954567 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:55:59.955559 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:55:59.955880 start: 1.4 download-retry (timeout 00:09:57) [common]
90 01:55:59.956254 start: 1.4.1 http-download (timeout 00:09:57) [common]
91 01:55:59.956819 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-272-gda4373fbcf006/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 01:55:59.957116 saving as /var/lib/lava/dispatcher/tmp/964177/tftp-deploy-hz767y9x/modules/modules.tar
93 01:55:59.957375 total size: 27651088 (26 MB)
94 01:55:59.957631 Using unxz to decompress xz
95 01:55:59.990070 progress 0 % (0 MB)
96 01:56:00.224404 progress 5 % (1 MB)
97 01:56:00.437819 progress 10 % (2 MB)
98 01:56:00.671417 progress 15 % (3 MB)
99 01:56:00.904869 progress 20 % (5 MB)
100 01:56:01.103272 progress 25 % (6 MB)
101 01:56:01.308539 progress 30 % (7 MB)
102 01:56:01.509318 progress 35 % (9 MB)
103 01:56:01.703037 progress 40 % (10 MB)
104 01:56:01.894603 progress 45 % (11 MB)
105 01:56:02.104175 progress 50 % (13 MB)
106 01:56:02.310565 progress 55 % (14 MB)
107 01:56:02.525773 progress 60 % (15 MB)
108 01:56:02.739174 progress 65 % (17 MB)
109 01:56:02.939702 progress 70 % (18 MB)
110 01:56:03.150052 progress 75 % (19 MB)
111 01:56:03.356748 progress 80 % (21 MB)
112 01:56:03.569360 progress 85 % (22 MB)
113 01:56:03.780064 progress 90 % (23 MB)
114 01:56:03.982864 progress 95 % (25 MB)
115 01:56:04.192731 progress 100 % (26 MB)
116 01:56:04.207772 26 MB downloaded in 4.25 s (6.20 MB/s)
117 01:56:04.208716 end: 1.4.1 http-download (duration 00:00:04) [common]
119 01:56:04.210495 end: 1.4 download-retry (duration 00:00:04) [common]
120 01:56:04.211072 start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
121 01:56:04.211649 start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
122 01:56:04.212234 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:56:04.212795 start: 1.5.2 lava-overlay (timeout 00:09:53) [common]
124 01:56:04.213981 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq
125 01:56:04.214902 makedir: /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin
126 01:56:04.215580 makedir: /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/tests
127 01:56:04.216328 makedir: /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/results
128 01:56:04.217003 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-add-keys
129 01:56:04.218000 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-add-sources
130 01:56:04.218987 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-background-process-start
131 01:56:04.220026 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-background-process-stop
132 01:56:04.221100 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-common-functions
133 01:56:04.222072 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-echo-ipv4
134 01:56:04.223044 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-install-packages
135 01:56:04.224022 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-installed-packages
136 01:56:04.225161 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-os-build
137 01:56:04.226200 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-probe-channel
138 01:56:04.227172 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-probe-ip
139 01:56:04.228168 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-target-ip
140 01:56:04.229164 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-target-mac
141 01:56:04.230174 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-target-storage
142 01:56:04.231159 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-test-case
143 01:56:04.232224 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-test-event
144 01:56:04.233202 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-test-feedback
145 01:56:04.234159 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-test-raise
146 01:56:04.235107 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-test-reference
147 01:56:04.236099 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-test-runner
148 01:56:04.237095 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-test-set
149 01:56:04.238068 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-test-shell
150 01:56:04.239036 Updating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-install-packages (oe)
151 01:56:04.240111 Updating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/bin/lava-installed-packages (oe)
152 01:56:04.241011 Creating /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/environment
153 01:56:04.241759 LAVA metadata
154 01:56:04.242289 - LAVA_JOB_ID=964177
155 01:56:04.242761 - LAVA_DISPATCHER_IP=192.168.6.2
156 01:56:04.243482 start: 1.5.2.1 ssh-authorize (timeout 00:09:53) [common]
157 01:56:04.245431 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 01:56:04.246072 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:53) [common]
159 01:56:04.246707 skipped lava-vland-overlay
160 01:56:04.247269 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 01:56:04.247841 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:53) [common]
162 01:56:04.248374 skipped lava-multinode-overlay
163 01:56:04.248871 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 01:56:04.249392 start: 1.5.2.4 test-definition (timeout 00:09:53) [common]
165 01:56:04.249869 Loading test definitions
166 01:56:04.250411 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:53) [common]
167 01:56:04.250851 Using /lava-964177 at stage 0
168 01:56:04.252705 uuid=964177_1.5.2.4.1 testdef=None
169 01:56:04.253042 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 01:56:04.253319 start: 1.5.2.4.2 test-overlay (timeout 00:09:53) [common]
171 01:56:04.255115 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 01:56:04.255921 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:53) [common]
174 01:56:04.258190 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 01:56:04.259021 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:53) [common]
177 01:56:04.261212 runner path: /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/0/tests/0_dmesg test_uuid 964177_1.5.2.4.1
178 01:56:04.261767 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 01:56:04.262532 Creating lava-test-runner.conf files
181 01:56:04.262746 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/964177/lava-overlay-c3wlfrpq/lava-964177/0 for stage 0
182 01:56:04.263088 - 0_dmesg
183 01:56:04.263442 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 01:56:04.263722 start: 1.5.2.5 compress-overlay (timeout 00:09:53) [common]
185 01:56:04.287466 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 01:56:04.287865 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:53) [common]
187 01:56:04.288161 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 01:56:04.288435 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 01:56:04.288700 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
190 01:56:05.378669 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 01:56:05.379142 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
192 01:56:05.379392 extracting modules file /var/lib/lava/dispatcher/tmp/964177/tftp-deploy-hz767y9x/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964177/extract-overlay-ramdisk-aec593qa/ramdisk
193 01:56:07.139317 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 01:56:07.139807 start: 1.5.5 apply-overlay-tftp (timeout 00:09:50) [common]
195 01:56:07.140130 [common] Applying overlay /var/lib/lava/dispatcher/tmp/964177/compress-overlay-uiwkjju2/overlay-1.5.2.5.tar.gz to ramdisk
196 01:56:07.140383 [common] Applying overlay /var/lib/lava/dispatcher/tmp/964177/compress-overlay-uiwkjju2/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/964177/extract-overlay-ramdisk-aec593qa/ramdisk
197 01:56:07.170799 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 01:56:07.171254 start: 1.5.6 prepare-kernel (timeout 00:09:50) [common]
199 01:56:07.171533 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:50) [common]
200 01:56:07.171767 Converting downloaded kernel to a uImage
201 01:56:07.172107 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/964177/tftp-deploy-hz767y9x/kernel/Image /var/lib/lava/dispatcher/tmp/964177/tftp-deploy-hz767y9x/kernel/uImage
202 01:56:08.877196 output: Image Name:
203 01:56:08.877597 output: Created: Sat Nov 9 01:56:07 2024
204 01:56:08.877822 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 01:56:08.878038 output: Data Size: 169937408 Bytes = 165954.50 KiB = 162.06 MiB
206 01:56:08.878247 output: Load Address: 01080000
207 01:56:08.878453 output: Entry Point: 01080000
208 01:56:08.878656 output:
209 01:56:08.878993 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 01:56:08.879270 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 01:56:08.879552 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 01:56:08.879817 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 01:56:08.880134 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 01:56:08.880413 Building ramdisk /var/lib/lava/dispatcher/tmp/964177/extract-overlay-ramdisk-aec593qa/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/964177/extract-overlay-ramdisk-aec593qa/ramdisk
215 01:56:14.370169 >> 441555 blocks
216 01:56:33.066903 Adding RAMdisk u-boot header.
217 01:56:33.067362 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/964177/extract-overlay-ramdisk-aec593qa/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/964177/extract-overlay-ramdisk-aec593qa/ramdisk.cpio.gz.uboot
218 01:56:33.637076 output: Image Name:
219 01:56:33.637502 output: Created: Sat Nov 9 01:56:33 2024
220 01:56:33.637713 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 01:56:33.637920 output: Data Size: 53586979 Bytes = 52331.03 KiB = 51.10 MiB
222 01:56:33.638122 output: Load Address: 00000000
223 01:56:33.638322 output: Entry Point: 00000000
224 01:56:33.638520 output:
225 01:56:33.639119 rename /var/lib/lava/dispatcher/tmp/964177/extract-overlay-ramdisk-aec593qa/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/964177/tftp-deploy-hz767y9x/ramdisk/ramdisk.cpio.gz.uboot
226 01:56:33.639544 end: 1.5.8 compress-ramdisk (duration 00:00:25) [common]
227 01:56:33.639832 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
228 01:56:33.640306 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:24) [common]
229 01:56:33.640772 No LXC device requested
230 01:56:33.641271 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 01:56:33.641777 start: 1.7 deploy-device-env (timeout 00:09:24) [common]
232 01:56:33.642270 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 01:56:33.642681 Checking files for TFTP limit of 4294967296 bytes.
234 01:56:33.645393 end: 1 tftp-deploy (duration 00:00:36) [common]
235 01:56:33.645972 start: 2 uboot-action (timeout 00:05:00) [common]
236 01:56:33.646492 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 01:56:33.646985 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 01:56:33.647502 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 01:56:33.648052 Using kernel file from prepare-kernel: 964177/tftp-deploy-hz767y9x/kernel/uImage
240 01:56:33.648660 substitutions:
241 01:56:33.649068 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 01:56:33.649470 - {DTB_ADDR}: 0x01070000
243 01:56:33.649863 - {DTB}: 964177/tftp-deploy-hz767y9x/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 01:56:33.650261 - {INITRD}: 964177/tftp-deploy-hz767y9x/ramdisk/ramdisk.cpio.gz.uboot
245 01:56:33.650657 - {KERNEL_ADDR}: 0x01080000
246 01:56:33.651049 - {KERNEL}: 964177/tftp-deploy-hz767y9x/kernel/uImage
247 01:56:33.651441 - {LAVA_MAC}: None
248 01:56:33.651868 - {PRESEED_CONFIG}: None
249 01:56:33.652293 - {PRESEED_LOCAL}: None
250 01:56:33.652685 - {RAMDISK_ADDR}: 0x08000000
251 01:56:33.653074 - {RAMDISK}: 964177/tftp-deploy-hz767y9x/ramdisk/ramdisk.cpio.gz.uboot
252 01:56:33.653471 - {ROOT_PART}: None
253 01:56:33.653861 - {ROOT}: None
254 01:56:33.654251 - {SERVER_IP}: 192.168.6.2
255 01:56:33.654643 - {TEE_ADDR}: 0x83000000
256 01:56:33.655029 - {TEE}: None
257 01:56:33.655415 Parsed boot commands:
258 01:56:33.655792 - setenv autoload no
259 01:56:33.656205 - setenv initrd_high 0xffffffff
260 01:56:33.656594 - setenv fdt_high 0xffffffff
261 01:56:33.656977 - dhcp
262 01:56:33.657360 - setenv serverip 192.168.6.2
263 01:56:33.657743 - tftpboot 0x01080000 964177/tftp-deploy-hz767y9x/kernel/uImage
264 01:56:33.658130 - tftpboot 0x08000000 964177/tftp-deploy-hz767y9x/ramdisk/ramdisk.cpio.gz.uboot
265 01:56:33.658514 - tftpboot 0x01070000 964177/tftp-deploy-hz767y9x/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 01:56:33.658897 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 01:56:33.659286 - bootm 0x01080000 0x08000000 0x01070000
268 01:56:33.659778 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 01:56:33.661290 start: 2.3 connect-device (timeout 00:05:00) [common]
271 01:56:33.661732 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 01:56:33.676936 Setting prompt string to ['lava-test: # ']
273 01:56:33.678414 end: 2.3 connect-device (duration 00:00:00) [common]
274 01:56:33.679021 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 01:56:33.679549 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 01:56:33.680099 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 01:56:33.681257 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 01:56:33.718360 >> OK - accepted request
279 01:56:33.720713 Returned 0 in 0 seconds
280 01:56:33.821878 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 01:56:33.823460 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 01:56:33.824066 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 01:56:33.824589 Setting prompt string to ['Hit any key to stop autoboot']
285 01:56:33.825036 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 01:56:33.826598 Trying 192.168.56.21...
287 01:56:33.827070 Connected to conserv1.
288 01:56:33.827468 Escape character is '^]'.
289 01:56:33.827880
290 01:56:33.828337 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 01:56:33.828763
292 01:56:41.344677 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 01:56:41.345095 bl2_stage_init 0x01
294 01:56:41.345388 bl2_stage_init 0x81
295 01:56:41.348059 hw id: 0x0000 - pwm id 0x01
296 01:56:41.348725 bl2_stage_init 0xc1
297 01:56:41.349307 bl2_stage_init 0x02
298 01:56:41.349860
299 01:56:41.353597 L0:00000000
300 01:56:41.354232 L1:00000703
301 01:56:41.354782 L2:00008067
302 01:56:41.355310 L3:15000000
303 01:56:41.359246 S1:00000000
304 01:56:41.359854 B2:20282000
305 01:56:41.360447 B1:a0f83180
306 01:56:41.360990
307 01:56:41.361510 TE: 69346
308 01:56:41.362032
309 01:56:41.364891 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 01:56:41.365494
311 01:56:41.370287 Board ID = 1
312 01:56:41.370887 Set cpu clk to 24M
313 01:56:41.371417 Set clk81 to 24M
314 01:56:41.375843 Use GP1_pll as DSU clk.
315 01:56:41.376479 DSU clk: 1200 Mhz
316 01:56:41.377003 CPU clk: 1200 MHz
317 01:56:41.377523 Set clk81 to 166.6M
318 01:56:41.387040 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 01:56:41.387695 board id: 1
320 01:56:41.393708 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 01:56:41.404560 fw parse done
322 01:56:41.410423 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 01:56:41.453401 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 01:56:41.464811 PIEI prepare done
325 01:56:41.465419 fastboot data load
326 01:56:41.465960 fastboot data verify
327 01:56:41.470419 verify result: 266
328 01:56:41.475917 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 01:56:41.476571 LPDDR4 probe
330 01:56:41.477097 ddr clk to 1584MHz
331 01:56:41.483870 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 01:56:41.520819
333 01:56:41.521508 dmc_version 0001
334 01:56:41.528829 Check phy result
335 01:56:41.534728 INFO : End of CA training
336 01:56:41.535391 INFO : End of initialization
337 01:56:41.540367 INFO : Training has run successfully!
338 01:56:41.541018 Check phy result
339 01:56:41.545925 INFO : End of initialization
340 01:56:41.546578 INFO : End of read enable training
341 01:56:41.549223 INFO : End of fine write leveling
342 01:56:41.554753 INFO : End of Write leveling coarse delay
343 01:56:41.560422 INFO : Training has run successfully!
344 01:56:41.561140 Check phy result
345 01:56:41.561721 INFO : End of initialization
346 01:56:41.565944 INFO : End of read dq deskew training
347 01:56:41.569309 INFO : End of MPR read delay center optimization
348 01:56:41.574842 INFO : End of write delay center optimization
349 01:56:41.580459 INFO : End of read delay center optimization
350 01:56:41.581167 INFO : End of max read latency training
351 01:56:41.586046 INFO : Training has run successfully!
352 01:56:41.586755 1D training succeed
353 01:56:41.593390 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 01:56:41.642056 Check phy result
355 01:56:41.642754 INFO : End of initialization
356 01:56:41.669576 INFO : End of 2D read delay Voltage center optimization
357 01:56:41.693971 INFO : End of 2D read delay Voltage center optimization
358 01:56:41.750286 INFO : End of 2D write delay Voltage center optimization
359 01:56:41.804697 INFO : End of 2D write delay Voltage center optimization
360 01:56:41.810252 INFO : Training has run successfully!
361 01:56:41.810848
362 01:56:41.811392 channel==0
363 01:56:41.815889 RxClkDly_Margin_A0==78 ps 8
364 01:56:41.816570 TxDqDly_Margin_A0==98 ps 10
365 01:56:41.819311 RxClkDly_Margin_A1==88 ps 9
366 01:56:41.819907 TxDqDly_Margin_A1==98 ps 10
367 01:56:41.824823 TrainedVREFDQ_A0==74
368 01:56:41.825442 TrainedVREFDQ_A1==74
369 01:56:41.825968 VrefDac_Margin_A0==24
370 01:56:41.830568 DeviceVref_Margin_A0==40
371 01:56:41.831144 VrefDac_Margin_A1==23
372 01:56:41.836114 DeviceVref_Margin_A1==40
373 01:56:41.836734
374 01:56:41.837253
375 01:56:41.837760 channel==1
376 01:56:41.838299 RxClkDly_Margin_A0==78 ps 8
377 01:56:41.839622 TxDqDly_Margin_A0==78 ps 8
378 01:56:41.845119 RxClkDly_Margin_A1==78 ps 8
379 01:56:41.845723 TxDqDly_Margin_A1==88 ps 9
380 01:56:41.846266 TrainedVREFDQ_A0==75
381 01:56:41.850668 TrainedVREFDQ_A1==75
382 01:56:41.851265 VrefDac_Margin_A0==22
383 01:56:41.856306 DeviceVref_Margin_A0==39
384 01:56:41.856907 VrefDac_Margin_A1==22
385 01:56:41.857451 DeviceVref_Margin_A1==39
386 01:56:41.857952
387 01:56:41.865244 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 01:56:41.865845
389 01:56:41.893164 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000016 dram_vref_reg_value 0x 00000061
390 01:56:41.893875 2D training succeed
391 01:56:41.898785 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 01:56:41.904388 auto size-- 65535DDR cs0 size: 2048MB
393 01:56:41.904965 DDR cs1 size: 2048MB
394 01:56:41.910023 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 01:56:41.910615 cs0 DataBus test pass
396 01:56:41.915577 cs1 DataBus test pass
397 01:56:41.916232 cs0 AddrBus test pass
398 01:56:41.916778 cs1 AddrBus test pass
399 01:56:41.921196
400 01:56:41.921793 100bdlr_step_size ps== 471
401 01:56:41.922319 result report
402 01:56:41.926799 boot times 0Enable ddr reg access
403 01:56:41.932467 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 01:56:41.946549 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 01:56:42.604668 bl2z: ptr: 05129330, size: 00001e40
406 01:56:42.615551 0.0;M3 CHK:0;cm4_sp_mode 0
407 01:56:42.616201 MVN_1=0x00000000
408 01:56:42.616727 MVN_2=0x00000000
409 01:56:42.626811 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 01:56:42.627422 OPS=0x04
411 01:56:42.627936 ring efuse init
412 01:56:42.632487 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 01:56:42.633087 [0.017354 Inits done]
414 01:56:42.633594 secure task start!
415 01:56:42.639417 high task start!
416 01:56:42.640028 low task start!
417 01:56:42.640556 run into bl31
418 01:56:42.648945 NOTICE: BL31: v1.3(release):4fc40b1
419 01:56:42.656790 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 01:56:42.657404 NOTICE: BL31: G12A normal boot!
421 01:56:42.672481 NOTICE: BL31: BL33 decompress pass
422 01:56:42.677317 ERROR: Error initializing runtime service opteed_fast
423 01:56:45.387455 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 01:56:45.388325 bl2_stage_init 0x01
425 01:56:45.388913 bl2_stage_init 0x81
426 01:56:45.393190 hw id: 0x0000 - pwm id 0x01
427 01:56:45.393829 bl2_stage_init 0xc1
428 01:56:45.398720 bl2_stage_init 0x02
429 01:56:45.399588
430 01:56:45.400168 L0:00000000
431 01:56:45.400693 L1:00000703
432 01:56:45.401195 L2:00008067
433 01:56:45.401683 L3:15000000
434 01:56:45.402533 S1:00000000
435 01:56:45.404977 B2:20282000
436 01:56:45.405456 B1:a0f83180
437 01:56:45.405859
438 01:56:45.406253 TE: 66644
439 01:56:45.406644
440 01:56:45.410833 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 01:56:45.411501
442 01:56:45.416432 Board ID = 1
443 01:56:45.417146 Set cpu clk to 24M
444 01:56:45.417670 Set clk81 to 24M
445 01:56:45.421908 Use GP1_pll as DSU clk.
446 01:56:45.422502 DSU clk: 1200 Mhz
447 01:56:45.423010 CPU clk: 1200 MHz
448 01:56:45.423512 Set clk81 to 166.6M
449 01:56:45.433001 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 01:56:45.433627 board id: 1
451 01:56:45.439562 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 01:56:45.450145 fw parse done
453 01:56:45.455277 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 01:56:45.500721 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 01:56:45.509698 PIEI prepare done
456 01:56:45.510324 fastboot data load
457 01:56:45.510839 fastboot data verify
458 01:56:45.515257 verify result: 266
459 01:56:45.520941 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 01:56:45.521547 LPDDR4 probe
461 01:56:45.522056 ddr clk to 1584MHz
462 01:56:45.528549 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 01:56:45.565688
464 01:56:45.566358 dmc_version 0001
465 01:56:45.572119 Check phy result
466 01:56:45.578701 INFO : End of CA training
467 01:56:45.579323 INFO : End of initialization
468 01:56:45.584289 INFO : Training has run successfully!
469 01:56:45.584880 Check phy result
470 01:56:45.589933 INFO : End of initialization
471 01:56:45.590537 INFO : End of read enable training
472 01:56:45.595478 INFO : End of fine write leveling
473 01:56:45.601064 INFO : End of Write leveling coarse delay
474 01:56:45.601657 INFO : Training has run successfully!
475 01:56:45.602183 Check phy result
476 01:56:45.606672 INFO : End of initialization
477 01:56:45.607266 INFO : End of read dq deskew training
478 01:56:45.612310 INFO : End of MPR read delay center optimization
479 01:56:45.617928 INFO : End of write delay center optimization
480 01:56:45.623477 INFO : End of read delay center optimization
481 01:56:45.624125 INFO : End of max read latency training
482 01:56:45.629145 INFO : Training has run successfully!
483 01:56:45.629785 1D training succeed
484 01:56:45.637267 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 01:56:45.685798 Check phy result
486 01:56:45.686482 INFO : End of initialization
487 01:56:45.707852 INFO : End of 2D read delay Voltage center optimization
488 01:56:45.726445 INFO : End of 2D read delay Voltage center optimization
489 01:56:45.778824 INFO : End of 2D write delay Voltage center optimization
490 01:56:45.828501 INFO : End of 2D write delay Voltage center optimization
491 01:56:45.834004 INFO : Training has run successfully!
492 01:56:45.834495
493 01:56:45.834913 channel==0
494 01:56:45.839578 RxClkDly_Margin_A0==78 ps 8
495 01:56:45.840110 TxDqDly_Margin_A0==98 ps 10
496 01:56:45.845164 RxClkDly_Margin_A1==88 ps 9
497 01:56:45.845643 TxDqDly_Margin_A1==98 ps 10
498 01:56:45.846056 TrainedVREFDQ_A0==74
499 01:56:45.850762 TrainedVREFDQ_A1==75
500 01:56:45.851265 VrefDac_Margin_A0==24
501 01:56:45.851680 DeviceVref_Margin_A0==40
502 01:56:45.856347 VrefDac_Margin_A1==23
503 01:56:45.856881 DeviceVref_Margin_A1==39
504 01:56:45.857300
505 01:56:45.857710
506 01:56:45.862137 channel==1
507 01:56:45.862664 RxClkDly_Margin_A0==88 ps 9
508 01:56:45.863083 TxDqDly_Margin_A0==98 ps 10
509 01:56:45.867519 RxClkDly_Margin_A1==88 ps 9
510 01:56:45.868080 TxDqDly_Margin_A1==88 ps 9
511 01:56:45.873205 TrainedVREFDQ_A0==78
512 01:56:45.873735 TrainedVREFDQ_A1==75
513 01:56:45.874155 VrefDac_Margin_A0==22
514 01:56:45.878818 DeviceVref_Margin_A0==36
515 01:56:45.879342 VrefDac_Margin_A1==22
516 01:56:45.884405 DeviceVref_Margin_A1==39
517 01:56:45.884931
518 01:56:45.885350 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 01:56:45.885753
520 01:56:45.917992 soc_vref_reg_value 0x 0000001a 00000019 00000019 00000017 00000019 00000016 00000018 00000016 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
521 01:56:45.918588 2D training succeed
522 01:56:45.923607 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 01:56:45.929184 auto size-- 65535DDR cs0 size: 2048MB
524 01:56:45.929697 DDR cs1 size: 2048MB
525 01:56:45.934818 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 01:56:45.935318 cs0 DataBus test pass
527 01:56:45.940297 cs1 DataBus test pass
528 01:56:45.940808 cs0 AddrBus test pass
529 01:56:45.941215 cs1 AddrBus test pass
530 01:56:45.941610
531 01:56:45.946051 100bdlr_step_size ps== 478
532 01:56:45.946564 result report
533 01:56:45.951620 boot times 0Enable ddr reg access
534 01:56:45.955903 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 01:56:45.969772 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 01:56:46.625124 bl2z: ptr: 05129330, size: 00001e40
537 01:56:46.633330 0.0;M3 CHK:0;cm4_sp_mode 0
538 01:56:46.633880 MVN_1=0x00000000
539 01:56:46.634301 MVN_2=0x00000000
540 01:56:46.644771 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 01:56:46.645312 OPS=0x04
542 01:56:46.645737 ring efuse init
543 01:56:46.650406 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 01:56:46.650911 [0.017319 Inits done]
545 01:56:46.651327 secure task start!
546 01:56:46.657237 high task start!
547 01:56:46.657748 low task start!
548 01:56:46.658157 run into bl31
549 01:56:46.666421 NOTICE: BL31: v1.3(release):4fc40b1
550 01:56:46.673849 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 01:56:46.674338 NOTICE: BL31: G12A normal boot!
552 01:56:46.689638 NOTICE: BL31: BL33 decompress pass
553 01:56:46.694383 ERROR: Error initializing runtime service opteed_fast
554 01:56:48.090767 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 01:56:48.091372 bl2_stage_init 0x01
556 01:56:48.091797 bl2_stage_init 0x81
557 01:56:48.096477 hw id: 0x0000 - pwm id 0x01
558 01:56:48.096957 bl2_stage_init 0xc1
559 01:56:48.097370 bl2_stage_init 0x02
560 01:56:48.097768
561 01:56:48.101977 L0:00000000
562 01:56:48.102449 L1:00000703
563 01:56:48.102858 L2:00008067
564 01:56:48.103258 L3:15000000
565 01:56:48.103649 S1:00000000
566 01:56:48.104434 B2:20282000
567 01:56:48.109727 B1:a0f83180
568 01:56:48.110369
569 01:56:48.110938 TE: 68859
570 01:56:48.111474
571 01:56:48.115285 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 01:56:48.115909
573 01:56:48.116496 Board ID = 1
574 01:56:48.120824 Set cpu clk to 24M
575 01:56:48.121445 Set clk81 to 24M
576 01:56:48.121984 Use GP1_pll as DSU clk.
577 01:56:48.122499 DSU clk: 1200 Mhz
578 01:56:48.126426 CPU clk: 1200 MHz
579 01:56:48.127045 Set clk81 to 166.6M
580 01:56:48.132020 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 01:56:48.132638 board id: 1
582 01:56:48.141654 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 01:56:48.153182 fw parse done
584 01:56:48.158937 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 01:56:48.201170 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 01:56:48.213187 PIEI prepare done
587 01:56:48.213793 fastboot data load
588 01:56:48.214338 fastboot data verify
589 01:56:48.218741 verify result: 266
590 01:56:48.224407 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 01:56:48.225019 LPDDR4 probe
592 01:56:48.225544 ddr clk to 1584MHz
593 01:56:48.232064 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 01:56:48.269270
595 01:56:48.269910 dmc_version 0001
596 01:56:48.276227 Check phy result
597 01:56:48.283096 INFO : End of CA training
598 01:56:48.283710 INFO : End of initialization
599 01:56:48.288668 INFO : Training has run successfully!
600 01:56:48.289298 Check phy result
601 01:56:48.294213 INFO : End of initialization
602 01:56:48.294703 INFO : End of read enable training
603 01:56:48.299858 INFO : End of fine write leveling
604 01:56:48.305447 INFO : End of Write leveling coarse delay
605 01:56:48.305921 INFO : Training has run successfully!
606 01:56:48.306332 Check phy result
607 01:56:48.311044 INFO : End of initialization
608 01:56:48.311509 INFO : End of read dq deskew training
609 01:56:48.316644 INFO : End of MPR read delay center optimization
610 01:56:48.322287 INFO : End of write delay center optimization
611 01:56:48.327839 INFO : End of read delay center optimization
612 01:56:48.328352 INFO : End of max read latency training
613 01:56:48.333431 INFO : Training has run successfully!
614 01:56:48.333909 1D training succeed
615 01:56:48.341953 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 01:56:48.390520 Check phy result
617 01:56:48.391076 INFO : End of initialization
618 01:56:48.418211 INFO : End of 2D read delay Voltage center optimization
619 01:56:48.441953 INFO : End of 2D read delay Voltage center optimization
620 01:56:48.499247 INFO : End of 2D write delay Voltage center optimization
621 01:56:48.553357 INFO : End of 2D write delay Voltage center optimization
622 01:56:48.558849 INFO : Training has run successfully!
623 01:56:48.559467
624 01:56:48.560037 channel==0
625 01:56:48.564415 RxClkDly_Margin_A0==88 ps 9
626 01:56:48.564908 TxDqDly_Margin_A0==98 ps 10
627 01:56:48.569987 RxClkDly_Margin_A1==88 ps 9
628 01:56:48.570490 TxDqDly_Margin_A1==98 ps 10
629 01:56:48.570888 TrainedVREFDQ_A0==74
630 01:56:48.575535 TrainedVREFDQ_A1==75
631 01:56:48.576049 VrefDac_Margin_A0==24
632 01:56:48.576450 DeviceVref_Margin_A0==40
633 01:56:48.581280 VrefDac_Margin_A1==23
634 01:56:48.581751 DeviceVref_Margin_A1==39
635 01:56:48.582139
636 01:56:48.582541
637 01:56:48.586739 channel==1
638 01:56:48.587196 RxClkDly_Margin_A0==78 ps 8
639 01:56:48.587595 TxDqDly_Margin_A0==98 ps 10
640 01:56:48.592318 RxClkDly_Margin_A1==78 ps 8
641 01:56:48.592788 TxDqDly_Margin_A1==88 ps 9
642 01:56:48.597982 TrainedVREFDQ_A0==78
643 01:56:48.598452 TrainedVREFDQ_A1==75
644 01:56:48.598853 VrefDac_Margin_A0==22
645 01:56:48.603556 DeviceVref_Margin_A0==36
646 01:56:48.604056 VrefDac_Margin_A1==22
647 01:56:48.609170 DeviceVref_Margin_A1==39
648 01:56:48.609635
649 01:56:48.610033 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 01:56:48.610423
651 01:56:48.642755 soc_vref_reg_value 0x 0000001a 00000019 00000019 00000017 00000019 00000016 00000018 00000016 00000018 00000017 00000017 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
652 01:56:48.643300 2D training succeed
653 01:56:48.648363 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 01:56:48.653912 auto size-- 65535DDR cs0 size: 2048MB
655 01:56:48.654382 DDR cs1 size: 2048MB
656 01:56:48.659555 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 01:56:48.660048 cs0 DataBus test pass
658 01:56:48.665329 cs1 DataBus test pass
659 01:56:48.665798 cs0 AddrBus test pass
660 01:56:48.666202 cs1 AddrBus test pass
661 01:56:48.666598
662 01:56:48.670787 100bdlr_step_size ps== 485
663 01:56:48.671268 result report
664 01:56:48.676348 boot times 0Enable ddr reg access
665 01:56:48.680924 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 01:56:48.694948 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 01:56:49.356826 bl2z: ptr: 05129330, size: 00001e40
668 01:56:49.362527 0.0;M3 CHK:0;cm4_sp_mode 0
669 01:56:49.363033 MVN_1=0x00000000
670 01:56:49.363450 MVN_2=0x00000000
671 01:56:49.374048 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 01:56:49.374573 OPS=0x04
673 01:56:49.374993 ring efuse init
674 01:56:49.376989 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 01:56:49.382730 [0.017354 Inits done]
676 01:56:49.383221 secure task start!
677 01:56:49.383628 high task start!
678 01:56:49.384069 low task start!
679 01:56:49.386718 run into bl31
680 01:56:49.395659 NOTICE: BL31: v1.3(release):4fc40b1
681 01:56:49.403280 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 01:56:49.403766 NOTICE: BL31: G12A normal boot!
683 01:56:49.419140 NOTICE: BL31: BL33 decompress pass
684 01:56:49.424507 ERROR: Error initializing runtime service opteed_fast
685 01:56:50.220056
686 01:56:50.220671
687 01:56:50.225526 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 01:56:50.226007
689 01:56:50.229247 Model: Libre Computer AML-S905D3-CC Solitude
690 01:56:50.375453 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 01:56:50.390856 DRAM: 2 GiB (effective 3.8 GiB)
692 01:56:50.492522 Core: 406 devices, 33 uclasses, devicetree: separate
693 01:56:50.498314 WDT: Not starting watchdog@f0d0
694 01:56:50.523302 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 01:56:50.535534 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 01:56:50.540015 ** Bad device specification mmc 0 **
697 01:56:50.550642 Card did not respond to voltage select! : -110
698 01:56:50.557630 ** Bad device specification mmc 0 **
699 01:56:50.558118 Couldn't find partition mmc 0
700 01:56:50.566605 Card did not respond to voltage select! : -110
701 01:56:50.572162 ** Bad device specification mmc 0 **
702 01:56:50.572649 Couldn't find partition mmc 0
703 01:56:50.576827 Error: could not access storage.
704 01:56:50.873433 Net: eth0: ethernet@ff3f0000
705 01:56:50.874178 starting USB...
706 01:56:51.118538 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 01:56:51.119312 Starting the controller
708 01:56:51.125017 USB XHCI 1.10
709 01:56:52.681460 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 01:56:52.689735 scanning usb for storage devices... 0 Storage Device(s) found
712 01:56:52.741352 Hit any key to stop autoboot: 1
713 01:56:52.742079 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 01:56:52.742470 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 01:56:52.742771 Setting prompt string to ['=>']
716 01:56:52.743080 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 01:56:52.755273 0
718 01:56:52.756252 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 01:56:52.857325 => setenv autoload no
721 01:56:52.858082 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 01:56:52.862698 setenv autoload no
724 01:56:52.964130 => setenv initrd_high 0xffffffff
725 01:56:52.964907 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 01:56:52.969304 setenv initrd_high 0xffffffff
728 01:56:53.070805 => setenv fdt_high 0xffffffff
729 01:56:53.071573 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 01:56:53.075897 setenv fdt_high 0xffffffff
732 01:56:53.177356 => dhcp
733 01:56:53.177970 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 01:56:53.181999 dhcp
735 01:56:54.087947 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 01:56:54.088592 Speed: 1000, full duplex
737 01:56:54.089018 BOOTP broadcast 1
738 01:56:54.335157 BOOTP broadcast 2
739 01:56:54.346898 DHCP client bound to address 192.168.6.21 (259 ms)
741 01:56:54.448406 => setenv serverip 192.168.6.2
742 01:56:54.449119 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
743 01:56:54.453245 setenv serverip 192.168.6.2
745 01:56:54.554637 => tftpboot 0x01080000 964177/tftp-deploy-hz767y9x/kernel/uImage
746 01:56:54.555272 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
747 01:56:54.562217 tftpboot 0x01080000 964177/tftp-deploy-hz767y9x/kernel/uImage
748 01:56:54.562699 Speed: 1000, full duplex
749 01:56:54.563111 Using ethernet@ff3f0000 device
750 01:56:54.567486 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
751 01:56:54.573146 Filename '964177/tftp-deploy-hz767y9x/kernel/uImage'.
752 01:56:54.576532 Load address: 0x1080000
753 01:56:58.864532 Loading: *###################
754 01:56:58.865134 TFTP error: trying to overwrite reserved memory...
756 01:56:58.866531 end: 2.4.3 bootloader-commands (duration 00:00:06) [common]
759 01:56:58.868402 end: 2.4 uboot-commands (duration 00:00:25) [common]
761 01:56:58.869733 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
763 01:56:58.870720 end: 2 uboot-action (duration 00:00:25) [common]
765 01:56:58.872338 Cleaning after the job
766 01:56:58.872937 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964177/tftp-deploy-hz767y9x/ramdisk
767 01:56:58.901321 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964177/tftp-deploy-hz767y9x/kernel
768 01:56:58.953484 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964177/tftp-deploy-hz767y9x/dtb
769 01:56:58.954269 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964177/tftp-deploy-hz767y9x/modules
770 01:56:59.010326 start: 4.1 power-off (timeout 00:00:30) [common]
771 01:56:59.011009 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
772 01:56:59.043885 >> OK - accepted request
773 01:56:59.046409 Returned 0 in 0 seconds
774 01:56:59.147248 end: 4.1 power-off (duration 00:00:00) [common]
776 01:56:59.148265 start: 4.2 read-feedback (timeout 00:10:00) [common]
777 01:56:59.148935 Listened to connection for namespace 'common' for up to 1s
778 01:57:00.149871 Finalising connection for namespace 'common'
779 01:57:00.150358 Disconnecting from shell: Finalise
780 01:57:00.150644 =>
781 01:57:00.251427 end: 4.2 read-feedback (duration 00:00:01) [common]
782 01:57:00.252144 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/964177
783 01:57:00.615351 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/964177
784 01:57:00.616112 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.