Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 00:01:07.104633 lava-dispatcher, installed at version: 2024.01
2 00:01:07.105419 start: 0 validate
3 00:01:07.105891 Start time: 2024-11-10 00:01:07.105860+00:00 (UTC)
4 00:01:07.106417 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:01:07.106955 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 00:01:07.148945 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:01:07.149496 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 00:01:07.179756 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:01:07.180424 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 00:01:07.210810 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:01:07.211317 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 00:01:07.240118 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 00:01:07.240596 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 00:01:07.275257 validate duration: 0.17
16 00:01:07.276199 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:01:07.276549 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:01:07.276865 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:01:07.277471 Not decompressing ramdisk as can be used compressed.
20 00:01:07.277914 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 00:01:07.278190 saving as /var/lib/lava/dispatcher/tmp/968538/tftp-deploy-tfzyb6tt/ramdisk/initrd.cpio.gz
22 00:01:07.278468 total size: 4775763 (4 MB)
23 00:01:07.312608 progress 0 % (0 MB)
24 00:01:07.319740 progress 5 % (0 MB)
25 00:01:07.326461 progress 10 % (0 MB)
26 00:01:07.332604 progress 15 % (0 MB)
27 00:01:07.336519 progress 20 % (0 MB)
28 00:01:07.339946 progress 25 % (1 MB)
29 00:01:07.343379 progress 30 % (1 MB)
30 00:01:07.347211 progress 35 % (1 MB)
31 00:01:07.350538 progress 40 % (1 MB)
32 00:01:07.353797 progress 45 % (2 MB)
33 00:01:07.357017 progress 50 % (2 MB)
34 00:01:07.360603 progress 55 % (2 MB)
35 00:01:07.363808 progress 60 % (2 MB)
36 00:01:07.367025 progress 65 % (2 MB)
37 00:01:07.370608 progress 70 % (3 MB)
38 00:01:07.373763 progress 75 % (3 MB)
39 00:01:07.377042 progress 80 % (3 MB)
40 00:01:07.380243 progress 85 % (3 MB)
41 00:01:07.383796 progress 90 % (4 MB)
42 00:01:07.386923 progress 95 % (4 MB)
43 00:01:07.389855 progress 100 % (4 MB)
44 00:01:07.390510 4 MB downloaded in 0.11 s (40.66 MB/s)
45 00:01:07.391046 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:01:07.391933 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:01:07.392262 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:01:07.392536 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:01:07.393014 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 00:01:07.393272 saving as /var/lib/lava/dispatcher/tmp/968538/tftp-deploy-tfzyb6tt/kernel/zImage
52 00:01:07.393480 total size: 11444736 (10 MB)
53 00:01:07.393691 No compression specified
54 00:01:07.425946 progress 0 % (0 MB)
55 00:01:07.433487 progress 5 % (0 MB)
56 00:01:07.441128 progress 10 % (1 MB)
57 00:01:07.449024 progress 15 % (1 MB)
58 00:01:07.456491 progress 20 % (2 MB)
59 00:01:07.464278 progress 25 % (2 MB)
60 00:01:07.471668 progress 30 % (3 MB)
61 00:01:07.479348 progress 35 % (3 MB)
62 00:01:07.486591 progress 40 % (4 MB)
63 00:01:07.494223 progress 45 % (4 MB)
64 00:01:07.501551 progress 50 % (5 MB)
65 00:01:07.509153 progress 55 % (6 MB)
66 00:01:07.516342 progress 60 % (6 MB)
67 00:01:07.523867 progress 65 % (7 MB)
68 00:01:07.531001 progress 70 % (7 MB)
69 00:01:07.538172 progress 75 % (8 MB)
70 00:01:07.545801 progress 80 % (8 MB)
71 00:01:07.553105 progress 85 % (9 MB)
72 00:01:07.560696 progress 90 % (9 MB)
73 00:01:07.567880 progress 95 % (10 MB)
74 00:01:07.575137 progress 100 % (10 MB)
75 00:01:07.575671 10 MB downloaded in 0.18 s (59.91 MB/s)
76 00:01:07.576178 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:01:07.577011 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:01:07.577288 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:01:07.577555 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:01:07.578021 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 00:01:07.578297 saving as /var/lib/lava/dispatcher/tmp/968538/tftp-deploy-tfzyb6tt/dtb/am335x-boneblack.dtb
83 00:01:07.578509 total size: 70568 (0 MB)
84 00:01:07.578718 No compression specified
85 00:01:07.613910 progress 46 % (0 MB)
86 00:01:07.614757 progress 92 % (0 MB)
87 00:01:07.615430 progress 100 % (0 MB)
88 00:01:07.615820 0 MB downloaded in 0.04 s (1.80 MB/s)
89 00:01:07.616312 end: 1.3.1 http-download (duration 00:00:00) [common]
91 00:01:07.617128 end: 1.3 download-retry (duration 00:00:00) [common]
92 00:01:07.617394 start: 1.4 download-retry (timeout 00:10:00) [common]
93 00:01:07.617659 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 00:01:07.618106 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 00:01:07.618351 saving as /var/lib/lava/dispatcher/tmp/968538/tftp-deploy-tfzyb6tt/nfsrootfs/full.rootfs.tar
96 00:01:07.618556 total size: 117747780 (112 MB)
97 00:01:07.618763 Using unxz to decompress xz
98 00:01:07.650683 progress 0 % (0 MB)
99 00:01:08.361626 progress 5 % (5 MB)
100 00:01:09.094241 progress 10 % (11 MB)
101 00:01:09.856130 progress 15 % (16 MB)
102 00:01:10.723543 progress 20 % (22 MB)
103 00:01:11.436973 progress 25 % (28 MB)
104 00:01:12.475039 progress 30 % (33 MB)
105 00:01:13.279187 progress 35 % (39 MB)
106 00:01:13.631949 progress 40 % (44 MB)
107 00:01:13.986731 progress 45 % (50 MB)
108 00:01:14.635617 progress 50 % (56 MB)
109 00:01:15.434920 progress 55 % (61 MB)
110 00:01:16.156485 progress 60 % (67 MB)
111 00:01:16.863112 progress 65 % (73 MB)
112 00:01:17.626606 progress 70 % (78 MB)
113 00:01:18.373423 progress 75 % (84 MB)
114 00:01:19.095211 progress 80 % (89 MB)
115 00:01:19.806920 progress 85 % (95 MB)
116 00:01:20.587826 progress 90 % (101 MB)
117 00:01:21.347504 progress 95 % (106 MB)
118 00:01:22.159825 progress 100 % (112 MB)
119 00:01:22.172273 112 MB downloaded in 14.55 s (7.72 MB/s)
120 00:01:22.173233 end: 1.4.1 http-download (duration 00:00:15) [common]
122 00:01:22.174875 end: 1.4 download-retry (duration 00:00:15) [common]
123 00:01:22.175398 start: 1.5 download-retry (timeout 00:09:45) [common]
124 00:01:22.176059 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 00:01:22.176908 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 00:01:22.177372 saving as /var/lib/lava/dispatcher/tmp/968538/tftp-deploy-tfzyb6tt/modules/modules.tar
127 00:01:22.177790 total size: 6611468 (6 MB)
128 00:01:22.178209 Using unxz to decompress xz
129 00:01:22.219718 progress 0 % (0 MB)
130 00:01:22.254933 progress 5 % (0 MB)
131 00:01:22.298005 progress 10 % (0 MB)
132 00:01:22.341786 progress 15 % (0 MB)
133 00:01:22.385976 progress 20 % (1 MB)
134 00:01:22.432370 progress 25 % (1 MB)
135 00:01:22.475256 progress 30 % (1 MB)
136 00:01:22.517537 progress 35 % (2 MB)
137 00:01:22.561385 progress 40 % (2 MB)
138 00:01:22.604819 progress 45 % (2 MB)
139 00:01:22.648168 progress 50 % (3 MB)
140 00:01:22.690598 progress 55 % (3 MB)
141 00:01:22.740280 progress 60 % (3 MB)
142 00:01:22.782203 progress 65 % (4 MB)
143 00:01:22.825075 progress 70 % (4 MB)
144 00:01:22.870944 progress 75 % (4 MB)
145 00:01:22.914271 progress 80 % (5 MB)
146 00:01:22.956703 progress 85 % (5 MB)
147 00:01:22.999858 progress 90 % (5 MB)
148 00:01:23.043370 progress 95 % (6 MB)
149 00:01:23.087353 progress 100 % (6 MB)
150 00:01:23.100724 6 MB downloaded in 0.92 s (6.83 MB/s)
151 00:01:23.101332 end: 1.5.1 http-download (duration 00:00:01) [common]
153 00:01:23.102153 end: 1.5 download-retry (duration 00:00:01) [common]
154 00:01:23.102419 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 00:01:23.102687 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 00:01:38.936587 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/968538/extract-nfsrootfs-u1vb8hrg
157 00:01:38.937169 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 00:01:38.937452 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 00:01:38.938061 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i
160 00:01:38.938474 makedir: /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin
161 00:01:38.938787 makedir: /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/tests
162 00:01:38.939090 makedir: /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/results
163 00:01:38.939414 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-add-keys
164 00:01:38.939923 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-add-sources
165 00:01:38.940448 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-background-process-start
166 00:01:38.940927 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-background-process-stop
167 00:01:38.941469 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-common-functions
168 00:01:38.941997 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-echo-ipv4
169 00:01:38.942567 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-install-packages
170 00:01:38.943066 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-installed-packages
171 00:01:38.943603 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-os-build
172 00:01:38.944119 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-probe-channel
173 00:01:38.944606 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-probe-ip
174 00:01:38.945066 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-target-ip
175 00:01:38.945521 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-target-mac
176 00:01:38.945979 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-target-storage
177 00:01:38.946442 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-test-case
178 00:01:38.946904 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-test-event
179 00:01:38.947377 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-test-feedback
180 00:01:38.947854 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-test-raise
181 00:01:38.948367 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-test-reference
182 00:01:38.948834 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-test-runner
183 00:01:38.949305 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-test-set
184 00:01:38.949765 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-test-shell
185 00:01:38.950237 Updating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-add-keys (debian)
186 00:01:38.950748 Updating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-add-sources (debian)
187 00:01:38.951237 Updating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-install-packages (debian)
188 00:01:38.951717 Updating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-installed-packages (debian)
189 00:01:38.952214 Updating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/bin/lava-os-build (debian)
190 00:01:38.952643 Creating /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/environment
191 00:01:38.953002 LAVA metadata
192 00:01:38.953257 - LAVA_JOB_ID=968538
193 00:01:38.953470 - LAVA_DISPATCHER_IP=192.168.6.2
194 00:01:38.953817 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 00:01:38.954740 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 00:01:38.955038 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 00:01:38.955243 skipped lava-vland-overlay
198 00:01:38.955481 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 00:01:38.955732 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 00:01:38.955945 skipped lava-multinode-overlay
201 00:01:38.956229 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 00:01:38.956479 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 00:01:38.956722 Loading test definitions
204 00:01:38.956992 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 00:01:38.957208 Using /lava-968538 at stage 0
206 00:01:38.958281 uuid=968538_1.6.2.4.1 testdef=None
207 00:01:38.958585 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 00:01:38.958846 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 00:01:38.960378 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 00:01:38.961150 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 00:01:38.963010 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 00:01:38.963811 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 00:01:38.965606 runner path: /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/0/tests/0_timesync-off test_uuid 968538_1.6.2.4.1
216 00:01:38.966127 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 00:01:38.966925 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 00:01:38.967144 Using /lava-968538 at stage 0
220 00:01:38.967482 Fetching tests from https://github.com/kernelci/test-definitions.git
221 00:01:38.967764 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/0/tests/1_kselftest-dt'
222 00:01:42.312754 Running '/usr/bin/git checkout kernelci.org
223 00:01:42.594961 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 00:01:42.596395 uuid=968538_1.6.2.4.5 testdef=None
225 00:01:42.596742 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 00:01:42.597505 start: 1.6.2.4.6 test-overlay (timeout 00:09:25) [common]
228 00:01:42.600344 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 00:01:42.601163 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:25) [common]
231 00:01:42.604878 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 00:01:42.605734 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:25) [common]
234 00:01:42.609323 runner path: /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/0/tests/1_kselftest-dt test_uuid 968538_1.6.2.4.5
235 00:01:42.609604 BOARD='beaglebone-black'
236 00:01:42.609818 BRANCH='mainline'
237 00:01:42.610019 SKIPFILE='/dev/null'
238 00:01:42.610218 SKIP_INSTALL='True'
239 00:01:42.610416 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 00:01:42.610619 TST_CASENAME=''
241 00:01:42.610816 TST_CMDFILES='dt'
242 00:01:42.611371 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 00:01:42.612191 Creating lava-test-runner.conf files
245 00:01:42.612405 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/968538/lava-overlay-6hddth6i/lava-968538/0 for stage 0
246 00:01:42.612762 - 0_timesync-off
247 00:01:42.613006 - 1_kselftest-dt
248 00:01:42.613344 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 00:01:42.613632 start: 1.6.2.5 compress-overlay (timeout 00:09:25) [common]
250 00:02:05.726182 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 00:02:05.726623 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:02) [common]
252 00:02:05.726885 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 00:02:05.727152 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 00:02:05.727414 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:02) [common]
255 00:02:06.085058 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 00:02:06.085524 start: 1.6.4 extract-modules (timeout 00:09:01) [common]
257 00:02:06.085773 extracting modules file /var/lib/lava/dispatcher/tmp/968538/tftp-deploy-tfzyb6tt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/968538/extract-nfsrootfs-u1vb8hrg
258 00:02:06.948283 extracting modules file /var/lib/lava/dispatcher/tmp/968538/tftp-deploy-tfzyb6tt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/968538/extract-overlay-ramdisk-vg7n2eup/ramdisk
259 00:02:07.847223 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 00:02:07.847688 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 00:02:07.847970 [common] Applying overlay to NFS
262 00:02:07.848215 [common] Applying overlay /var/lib/lava/dispatcher/tmp/968538/compress-overlay-qnumjura/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/968538/extract-nfsrootfs-u1vb8hrg
263 00:02:10.626639 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 00:02:10.627122 start: 1.6.6 prepare-kernel (timeout 00:08:57) [common]
265 00:02:10.627402 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:57) [common]
266 00:02:10.627681 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 00:02:10.627934 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 00:02:10.628233 start: 1.6.7 configure-preseed-file (timeout 00:08:57) [common]
269 00:02:10.628486 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 00:02:10.628747 start: 1.6.8 compress-ramdisk (timeout 00:08:57) [common]
271 00:02:10.628998 Building ramdisk /var/lib/lava/dispatcher/tmp/968538/extract-overlay-ramdisk-vg7n2eup/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/968538/extract-overlay-ramdisk-vg7n2eup/ramdisk
272 00:02:11.626679 >> 74902 blocks
273 00:02:16.237776 Adding RAMdisk u-boot header.
274 00:02:16.238553 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/968538/extract-overlay-ramdisk-vg7n2eup/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/968538/extract-overlay-ramdisk-vg7n2eup/ramdisk.cpio.gz.uboot
275 00:02:16.403195 output: Image Name:
276 00:02:16.403668 output: Created: Sun Nov 10 00:02:16 2024
277 00:02:16.404156 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 00:02:16.404583 output: Data Size: 14790697 Bytes = 14444.04 KiB = 14.11 MiB
279 00:02:16.405018 output: Load Address: 00000000
280 00:02:16.405422 output: Entry Point: 00000000
281 00:02:16.405823 output:
282 00:02:16.406928 rename /var/lib/lava/dispatcher/tmp/968538/extract-overlay-ramdisk-vg7n2eup/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/968538/tftp-deploy-tfzyb6tt/ramdisk/ramdisk.cpio.gz.uboot
283 00:02:16.407648 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 00:02:16.408240 end: 1.6 prepare-tftp-overlay (duration 00:00:53) [common]
285 00:02:16.408788 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:51) [common]
286 00:02:16.409265 No LXC device requested
287 00:02:16.409775 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 00:02:16.410293 start: 1.8 deploy-device-env (timeout 00:08:51) [common]
289 00:02:16.410796 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 00:02:16.411213 Checking files for TFTP limit of 4294967296 bytes.
291 00:02:16.413980 end: 1 tftp-deploy (duration 00:01:09) [common]
292 00:02:16.414661 start: 2 uboot-action (timeout 00:05:00) [common]
293 00:02:16.415264 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 00:02:16.415844 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 00:02:16.416455 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 00:02:16.417241 substitutions:
297 00:02:16.417672 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 00:02:16.418087 - {DTB_ADDR}: 0x88000000
299 00:02:16.418490 - {DTB}: 968538/tftp-deploy-tfzyb6tt/dtb/am335x-boneblack.dtb
300 00:02:16.418893 - {INITRD}: 968538/tftp-deploy-tfzyb6tt/ramdisk/ramdisk.cpio.gz.uboot
301 00:02:16.419293 - {KERNEL_ADDR}: 0x82000000
302 00:02:16.419687 - {KERNEL}: 968538/tftp-deploy-tfzyb6tt/kernel/zImage
303 00:02:16.420138 - {LAVA_MAC}: None
304 00:02:16.420588 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/968538/extract-nfsrootfs-u1vb8hrg
305 00:02:16.420996 - {NFS_SERVER_IP}: 192.168.6.2
306 00:02:16.421391 - {PRESEED_CONFIG}: None
307 00:02:16.421783 - {PRESEED_LOCAL}: None
308 00:02:16.422173 - {RAMDISK_ADDR}: 0x83000000
309 00:02:16.422563 - {RAMDISK}: 968538/tftp-deploy-tfzyb6tt/ramdisk/ramdisk.cpio.gz.uboot
310 00:02:16.422960 - {ROOT_PART}: None
311 00:02:16.423350 - {ROOT}: None
312 00:02:16.423739 - {SERVER_IP}: 192.168.6.2
313 00:02:16.424170 - {TEE_ADDR}: 0x83000000
314 00:02:16.424574 - {TEE}: None
315 00:02:16.424972 Parsed boot commands:
316 00:02:16.425358 - setenv autoload no
317 00:02:16.425750 - setenv initrd_high 0xffffffff
318 00:02:16.426142 - setenv fdt_high 0xffffffff
319 00:02:16.426531 - dhcp
320 00:02:16.426920 - setenv serverip 192.168.6.2
321 00:02:16.427310 - tftp 0x82000000 968538/tftp-deploy-tfzyb6tt/kernel/zImage
322 00:02:16.427704 - tftp 0x83000000 968538/tftp-deploy-tfzyb6tt/ramdisk/ramdisk.cpio.gz.uboot
323 00:02:16.428122 - setenv initrd_size ${filesize}
324 00:02:16.428516 - tftp 0x88000000 968538/tftp-deploy-tfzyb6tt/dtb/am335x-boneblack.dtb
325 00:02:16.428907 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/968538/extract-nfsrootfs-u1vb8hrg,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 00:02:16.429311 - bootz 0x82000000 0x83000000 0x88000000
327 00:02:16.429816 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 00:02:16.431321 start: 2.3 connect-device (timeout 00:05:00) [common]
330 00:02:16.431751 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 00:02:16.445323 Setting prompt string to ['lava-test: # ']
332 00:02:16.446823 end: 2.3 connect-device (duration 00:00:00) [common]
333 00:02:16.447449 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 00:02:16.448065 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 00:02:16.448650 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 00:02:16.449860 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 00:02:16.488914 >> OK - accepted request
338 00:02:16.490791 Returned 0 in 0 seconds
339 00:02:16.591839 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 00:02:16.592906 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 00:02:16.593230 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 00:02:16.593524 Setting prompt string to ['Hit any key to stop autoboot']
344 00:02:16.593777 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 00:02:16.594692 Trying 192.168.56.21...
346 00:02:16.594974 Connected to conserv1.
347 00:02:16.595197 Escape character is '^]'.
348 00:02:16.595412
349 00:02:16.595632 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 00:02:16.595860
351 00:02:24.591147
352 00:02:24.591574 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 00:02:24.596075 Trying to boot from MMC1
354 00:02:25.171306
355 00:02:25.171890
356 00:02:25.172366 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 00:02:25.172775
358 00:02:25.176722 CPU : AM335X-GP rev 2.1
359 00:02:25.177184 Model: TI AM335x BeagleBone Black
360 00:02:25.180886 DRAM: 512 MiB
361 00:02:25.264116 Core: 160 devices, 18 uclasses, devicetree: separate
362 00:02:25.273727 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 00:02:28.638929 7[r[999;999H[6n8NAND:
364 00:02:28.639598 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 00:02:28.643952 Trying to boot from MMC1
366 00:02:29.216301
367 00:02:29.216813
368 00:02:29.217224 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 00:02:29.217626
370 00:02:29.221883 CPU : AM335X-GP rev 2.1
371 00:02:29.222338 Model: TI AM335x BeagleBone Black
372 00:02:29.225915 DRAM: 512 MiB
373 00:02:29.308746 Core: 160 devices, 18 uclasses, devicetree: separate
374 00:02:29.318406 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 00:02:31.410095 7[r[999;999H[6n8NAND:
376 00:02:31.410684 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 00:02:31.414487 Trying to boot from MMC1
378 00:02:31.987414
379 00:02:31.987909
380 00:02:31.988395 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 00:02:31.988810
382 00:02:31.992948 CPU : AM335X-GP rev 2.1
383 00:02:31.993409 Model: TI AM335x BeagleBone Black
384 00:02:31.997059 DRAM: 512 MiB
385 00:02:32.079841 Core: 160 devices, 18 uclasses, devicetree: separate
386 00:02:32.089429 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 00:02:32.594720 7[r[999;999H[6n8NAND: 0 MiB
388 00:02:32.604868 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 00:02:32.677645 Loading Environment from FAT... Unable to use mmc 0:1...
390 00:02:32.698971 <ethaddr> not set. Validating first E-fuse MAC
391 00:02:32.729375 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 00:02:32.788064 Hit any key to stop autoboot: 2
394 00:02:32.789059 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 00:02:32.789675 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
396 00:02:32.790163 Setting prompt string to ['=>']
397 00:02:32.790650 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
398 00:02:32.797920 0
399 00:02:32.798781 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 00:02:32.799276 Sending with 10 millisecond of delay
402 00:02:33.933806 => setenv autoload no
403 00:02:33.944571 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
404 00:02:33.949515 setenv autoload no
405 00:02:33.950232 Sending with 10 millisecond of delay
407 00:02:35.746730 => setenv initrd_high 0xffffffff
408 00:02:35.757472 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
409 00:02:35.758301 setenv initrd_high 0xffffffff
410 00:02:35.759011 Sending with 10 millisecond of delay
412 00:02:37.374878 => setenv fdt_high 0xffffffff
413 00:02:37.385610 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
414 00:02:37.386436 setenv fdt_high 0xffffffff
415 00:02:37.387147 Sending with 10 millisecond of delay
417 00:02:37.678941 => dhcp
418 00:02:37.689642 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 00:02:37.690455 dhcp
420 00:02:37.690887 link up on port 0, speed 100, full duplex
421 00:02:37.691301 BOOTP broadcast 1
422 00:02:37.717639 DHCP client bound to address 192.168.6.12 (22 ms)
423 00:02:37.718361 Sending with 10 millisecond of delay
425 00:02:39.394400 => setenv serverip 192.168.6.2
426 00:02:39.405141 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
427 00:02:39.406008 setenv serverip 192.168.6.2
428 00:02:39.406710 Sending with 10 millisecond of delay
430 00:02:42.890000 => tftp 0x82000000 968538/tftp-deploy-tfzyb6tt/kernel/zImage
431 00:02:42.900932 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
432 00:02:42.901960 tftp 0x82000000 968538/tftp-deploy-tfzyb6tt/kernel/zImage
433 00:02:42.902530 link up on port 0, speed 100, full duplex
434 00:02:42.905585 Using ethernet@4a100000 device
435 00:02:42.911212 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 00:02:42.918582 Filename '968538/tftp-deploy-tfzyb6tt/kernel/zImage'.
437 00:02:42.919165 Load address: 0x82000000
438 00:02:45.290879 Loading: *################################################## 10.9 MiB
439 00:02:45.291471 4.6 MiB/s
440 00:02:45.291904 done
441 00:02:45.295122 Bytes transferred = 11444736 (aea200 hex)
442 00:02:45.295889 Sending with 10 millisecond of delay
444 00:02:49.742762 => tftp 0x83000000 968538/tftp-deploy-tfzyb6tt/ramdisk/ramdisk.cpio.gz.uboot
445 00:02:49.753742 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
446 00:02:49.754879 tftp 0x83000000 968538/tftp-deploy-tfzyb6tt/ramdisk/ramdisk.cpio.gz.uboot
447 00:02:49.755352 link up on port 0, speed 100, full duplex
448 00:02:49.758937 Using ethernet@4a100000 device
449 00:02:49.764471 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 00:02:49.772235 Filename '968538/tftp-deploy-tfzyb6tt/ramdisk/ramdisk.cpio.gz.uboot'.
451 00:02:49.772763 Load address: 0x83000000
452 00:02:52.727409 Loading: *################################################## 14.1 MiB
453 00:02:52.728119 4.8 MiB/s
454 00:02:52.728580 done
455 00:02:52.731902 Bytes transferred = 14790761 (e1b069 hex)
456 00:02:52.732779 Sending with 10 millisecond of delay
458 00:02:54.590392 => setenv initrd_size ${filesize}
459 00:02:54.601232 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
460 00:02:54.602176 setenv initrd_size ${filesize}
461 00:02:54.602941 Sending with 10 millisecond of delay
463 00:02:58.748026 => tftp 0x88000000 968538/tftp-deploy-tfzyb6tt/dtb/am335x-boneblack.dtb
464 00:02:58.758861 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
465 00:02:58.759799 tftp 0x88000000 968538/tftp-deploy-tfzyb6tt/dtb/am335x-boneblack.dtb
466 00:02:58.760321 link up on port 0, speed 100, full duplex
467 00:02:58.763530 Using ethernet@4a100000 device
468 00:02:58.769055 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 00:02:58.776729 Filename '968538/tftp-deploy-tfzyb6tt/dtb/am335x-boneblack.dtb'.
470 00:02:58.777259 Load address: 0x88000000
471 00:02:58.790579 Loading: *################################################## 68.9 KiB
472 00:02:58.797029 4.2 MiB/s
473 00:02:58.797508 done
474 00:02:58.797945 Bytes transferred = 70568 (113a8 hex)
475 00:02:58.799557 Sending with 10 millisecond of delay
477 00:03:11.976612 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/968538/extract-nfsrootfs-u1vb8hrg,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 00:03:11.987606 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
479 00:03:11.988718 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/968538/extract-nfsrootfs-u1vb8hrg,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 00:03:11.989595 Sending with 10 millisecond of delay
482 00:03:14.328380 => bootz 0x82000000 0x83000000 0x88000000
483 00:03:14.339143 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 00:03:14.339653 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
485 00:03:14.340675 bootz 0x82000000 0x83000000 0x88000000
486 00:03:14.341122 Kernel image @ 0x82000000 [ 0x000000 - 0xaea200 ]
487 00:03:14.341615 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 00:03:14.346818 Image Name:
489 00:03:14.347259 Created: 2024-11-10 0:02:16 UTC
490 00:03:14.352313 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 00:03:14.357800 Data Size: 14790697 Bytes = 14.1 MiB
492 00:03:14.358235 Load Address: 00000000
493 00:03:14.364108 Entry Point: 00000000
494 00:03:14.532567 Verifying Checksum ... OK
495 00:03:14.533148 ## Flattened Device Tree blob at 88000000
496 00:03:14.538917 Booting using the fdt blob at 0x88000000
497 00:03:14.543965 Using Device Tree in place at 88000000, end 880143a7
498 00:03:14.557439
499 00:03:14.557950 Starting kernel ...
500 00:03:14.558372
501 00:03:14.559250 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 00:03:14.559879 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
503 00:03:14.560399 Setting prompt string to ['Linux version [0-9]']
504 00:03:14.560867 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 00:03:14.561360 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 00:03:15.398085 [ 0.000000] Booting Linux on physical CPU 0x0
507 00:03:15.404123 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
508 00:03:15.404674 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 00:03:15.405140 Setting prompt string to []
510 00:03:15.405629 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 00:03:15.406088 Using line separator: #'\n'#
512 00:03:15.406497 No login prompt set.
513 00:03:15.406925 Parsing kernel messages
514 00:03:15.407318 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 00:03:15.408137 [login-action] Waiting for messages, (timeout 00:04:01)
516 00:03:15.408593 Waiting using forced prompt support (timeout 00:02:01)
517 00:03:15.418048 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j371247-arm-gcc-12-multi-v7-defconfig-pbm25) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Sat Nov 9 23:01:50 UTC 2024
518 00:03:15.429461 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 00:03:15.432766 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 00:03:15.438361 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 00:03:15.444181 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 00:03:15.449883 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 00:03:15.455500 [ 0.000000] Memory policy: Data cache writeback
524 00:03:15.462175 [ 0.000000] efi: UEFI not found.
525 00:03:15.467113 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 00:03:15.472804 [ 0.000000] Zone ranges:
527 00:03:15.478572 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 00:03:15.484343 [ 0.000000] Normal empty
529 00:03:15.484777 [ 0.000000] HighMem empty
530 00:03:15.490071 [ 0.000000] Movable zone start for each node
531 00:03:15.490506 [ 0.000000] Early memory node ranges
532 00:03:15.501563 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 00:03:15.506901 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 00:03:15.532187 [ 0.000000] CPU: All CPU(s) started in SVC mode.
535 00:03:15.536959 [ 0.000000] AM335X ES2.1 (sgx neon)
536 00:03:15.549608 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
537 00:03:15.567117 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/968538/extract-nfsrootfs-u1vb8hrg,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
538 00:03:15.578704 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
539 00:03:15.584420 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
540 00:03:15.590167 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
541 00:03:15.600212 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
542 00:03:15.629284 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
543 00:03:15.635215 <6>[ 0.000000] trace event string verifier disabled
544 00:03:15.635657 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
545 00:03:15.640921 <6>[ 0.000000] rcu: RCU event tracing is enabled.
546 00:03:15.652378 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
547 00:03:15.658112 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
548 00:03:15.665379 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
549 00:03:15.680356 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
550 00:03:15.697580 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
551 00:03:15.704267 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
552 00:03:15.796877 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
553 00:03:15.808341 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
554 00:03:15.815104 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
555 00:03:15.827298 <6>[ 0.019142] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
556 00:03:15.835523 <6>[ 0.033955] Console: colour dummy device 80x30
557 00:03:15.841614 Matched prompt #6: WARNING:
558 00:03:15.842211 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
559 00:03:15.847036 <3>[ 0.038853] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
560 00:03:15.852725 <3>[ 0.045922] This ensures that you still see kernel messages. Please
561 00:03:15.855930 <3>[ 0.052647] update your kernel commandline.
562 00:03:15.896658 <6>[ 0.057262] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
563 00:03:15.902345 <6>[ 0.096149] CPU: Testing write buffer coherency: ok
564 00:03:15.908322 <6>[ 0.101514] CPU0: Spectre v2: using BPIALL workaround
565 00:03:15.908883 <6>[ 0.106979] pid_max: default: 32768 minimum: 301
566 00:03:15.919881 <6>[ 0.112174] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 00:03:15.926864 <6>[ 0.119995] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 00:03:15.933860 <6>[ 0.129357] CPU0: thread -1, cpu 0, socket -1, mpidr 0
569 00:03:15.942269 <6>[ 0.136364] Setting up static identity map for 0x80300000 - 0x803000ac
570 00:03:15.948068 <6>[ 0.145995] rcu: Hierarchical SRCU implementation.
571 00:03:15.955716 <6>[ 0.151277] rcu: Max phase no-delay instances is 1000.
572 00:03:15.964229 <6>[ 0.162396] EFI services will not be available.
573 00:03:15.970009 <6>[ 0.167673] smp: Bringing up secondary CPUs ...
574 00:03:15.975917 <6>[ 0.172718] smp: Brought up 1 node, 1 CPU
575 00:03:15.981556 <6>[ 0.177119] SMP: Total of 1 processors activated (996.14 BogoMIPS).
576 00:03:15.987447 <6>[ 0.183887] CPU: All CPU(s) started in SVC mode.
577 00:03:16.007923 <6>[ 0.189068] Memory: 405996K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
578 00:03:16.008622 <6>[ 0.205348] devtmpfs: initialized
579 00:03:16.030499 <6>[ 0.222258] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
580 00:03:16.042032 <6>[ 0.230833] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
581 00:03:16.047535 <6>[ 0.241293] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
582 00:03:16.058288 <6>[ 0.253637] pinctrl core: initialized pinctrl subsystem
583 00:03:16.067503 <6>[ 0.264246] DMI not present or invalid.
584 00:03:16.076270 <6>[ 0.270102] NET: Registered PF_NETLINK/PF_ROUTE protocol family
585 00:03:16.084318 <6>[ 0.279021] DMA: preallocated 256 KiB pool for atomic coherent allocations
586 00:03:16.100326 <6>[ 0.290580] thermal_sys: Registered thermal governor 'step_wise'
587 00:03:16.101045 <6>[ 0.290737] cpuidle: using governor menu
588 00:03:16.127807 <6>[ 0.326173] No ATAGs?
589 00:03:16.134195 <6>[ 0.328816] hw-breakpoint: debug architecture 0x4 unsupported.
590 00:03:16.144634 <6>[ 0.340820] Serial: AMBA PL011 UART driver
591 00:03:16.176710 <6>[ 0.374978] iommu: Default domain type: Translated
592 00:03:16.185872 <6>[ 0.380329] iommu: DMA domain TLB invalidation policy: strict mode
593 00:03:16.212776 <5>[ 0.410459] SCSI subsystem initialized
594 00:03:16.218481 <6>[ 0.415346] usbcore: registered new interface driver usbfs
595 00:03:16.224306 <6>[ 0.421373] usbcore: registered new interface driver hub
596 00:03:16.231078 <6>[ 0.427157] usbcore: registered new device driver usb
597 00:03:16.236818 <6>[ 0.433656] pps_core: LinuxPPS API ver. 1 registered
598 00:03:16.248318 <6>[ 0.439042] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
599 00:03:16.255491 <6>[ 0.448767] PTP clock support registered
600 00:03:16.256117 <6>[ 0.453227] EDAC MC: Ver: 3.0.0
601 00:03:16.303382 <6>[ 0.499266] scmi_core: SCMI protocol bus registered
602 00:03:16.318521 <6>[ 0.516662] vgaarb: loaded
603 00:03:16.340210 <6>[ 0.538746] clocksource: Switched to clocksource dmtimer
604 00:03:16.358415 <6>[ 0.556531] NET: Registered PF_INET protocol family
605 00:03:16.371006 <6>[ 0.562229] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
606 00:03:16.376780 <6>[ 0.571083] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
607 00:03:16.388229 <6>[ 0.580011] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
608 00:03:16.393998 <6>[ 0.588253] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
609 00:03:16.405576 <6>[ 0.596540] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
610 00:03:16.411396 <6>[ 0.604255] TCP: Hash tables configured (established 4096 bind 4096)
611 00:03:16.417205 <6>[ 0.611174] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
612 00:03:16.423231 <6>[ 0.618185] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
613 00:03:16.430635 <6>[ 0.625793] NET: Registered PF_UNIX/PF_LOCAL protocol family
614 00:03:16.516551 <6>[ 0.709364] RPC: Registered named UNIX socket transport module.
615 00:03:16.517195 <6>[ 0.715749] RPC: Registered udp transport module.
616 00:03:16.522310 <6>[ 0.720897] RPC: Registered tcp transport module.
617 00:03:16.528090 <6>[ 0.726003] RPC: Registered tcp-with-tls transport module.
618 00:03:16.541020 <6>[ 0.731933] RPC: Registered tcp NFSv4.1 backchannel transport module.
619 00:03:16.541542 <6>[ 0.738854] PCI: CLS 0 bytes, default 64
620 00:03:16.548286 <5>[ 0.744618] Initialise system trusted keyrings
621 00:03:16.569278 <6>[ 0.764679] Trying to unpack rootfs image as initramfs...
622 00:03:16.646736 <6>[ 0.838952] workingset: timestamp_bits=30 max_order=17 bucket_order=0
623 00:03:16.651479 <6>[ 0.846465] squashfs: version 4.0 (2009/01/31) Phillip Lougher
624 00:03:16.691009 <5>[ 0.889379] NFS: Registering the id_resolver key type
625 00:03:16.696748 <5>[ 0.894964] Key type id_resolver registered
626 00:03:16.702461 <5>[ 0.899616] Key type id_legacy registered
627 00:03:16.708253 <6>[ 0.904050] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
628 00:03:16.717610 <6>[ 0.911242] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
629 00:03:16.780684 <5>[ 0.979225] Key type asymmetric registered
630 00:03:16.786670 <5>[ 0.983747] Asymmetric key parser 'x509' registered
631 00:03:16.795040 <6>[ 0.989272] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
632 00:03:16.800761 <6>[ 0.997161] io scheduler mq-deadline registered
633 00:03:16.809525 <6>[ 1.002142] io scheduler kyber registered
634 00:03:16.809966 <6>[ 1.006593] io scheduler bfq registered
635 00:03:16.904362 <6>[ 1.099155] ledtrig-cpu: registered to indicate activity on CPUs
636 00:03:17.189526 <6>[ 1.384134] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 00:03:17.225231 <6>[ 1.423576] msm_serial: driver initialized
638 00:03:17.231313 <6>[ 1.428355] SuperH (H)SCI(F) driver initialized
639 00:03:17.237265 <6>[ 1.433677] STMicroelectronics ASC driver initialized
640 00:03:17.241571 <6>[ 1.439350] STM32 USART driver initialized
641 00:03:17.353541 <6>[ 1.551362] brd: module loaded
642 00:03:17.398901 <6>[ 1.597500] loop: module loaded
643 00:03:17.442111 <6>[ 1.639917] CAN device driver interface
644 00:03:17.448697 <6>[ 1.644881] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 00:03:17.454407 <6>[ 1.651921] e1000e: Intel(R) PRO/1000 Network Driver
646 00:03:17.460256 <6>[ 1.657308] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 00:03:17.466070 <6>[ 1.663772] igb: Intel(R) Gigabit Ethernet Network Driver
648 00:03:17.474299 <6>[ 1.669642] igb: Copyright (c) 2007-2014 Intel Corporation.
649 00:03:17.486068 <6>[ 1.678979] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 00:03:17.491916 <6>[ 1.685046] usbcore: registered new interface driver pegasus
651 00:03:17.494721 <6>[ 1.691218] usbcore: registered new interface driver asix
652 00:03:17.500432 <6>[ 1.697072] usbcore: registered new interface driver ax88179_178a
653 00:03:17.506218 <6>[ 1.703663] usbcore: registered new interface driver cdc_ether
654 00:03:17.512101 <6>[ 1.709983] usbcore: registered new interface driver smsc75xx
655 00:03:17.523482 <6>[ 1.716188] usbcore: registered new interface driver smsc95xx
656 00:03:17.529259 <6>[ 1.722431] usbcore: registered new interface driver net1080
657 00:03:17.535104 <6>[ 1.728552] usbcore: registered new interface driver cdc_subset
658 00:03:17.540856 <6>[ 1.734967] usbcore: registered new interface driver zaurus
659 00:03:17.545776 <6>[ 1.741032] usbcore: registered new interface driver cdc_ncm
660 00:03:17.555735 <6>[ 1.750639] usbcore: registered new interface driver usb-storage
661 00:03:17.565344 <6>[ 1.761867] i2c_dev: i2c /dev entries driver
662 00:03:17.590378 <5>[ 1.780831] cpuidle: enable-method property 'ti,am3352' found operations
663 00:03:17.596129 <6>[ 1.790424] sdhci: Secure Digital Host Controller Interface driver
664 00:03:17.603666 <6>[ 1.797078] sdhci: Copyright(c) Pierre Ossman
665 00:03:17.611103 <6>[ 1.803677] Synopsys Designware Multimedia Card Interface Driver
666 00:03:17.616502 <6>[ 1.811749] sdhci-pltfm: SDHCI platform and OF driver helper
667 00:03:17.630769 <6>[ 1.821872] usbcore: registered new interface driver usbhid
668 00:03:17.631245 <6>[ 1.827893] usbhid: USB HID core driver
669 00:03:17.644210 <6>[ 1.840016] NET: Registered PF_INET6 protocol family
670 00:03:18.092329 <6>[ 2.290666] Segment Routing with IPv6
671 00:03:18.098053 <6>[ 2.294811] In-situ OAM (IOAM) with IPv6
672 00:03:18.104691 <6>[ 2.299330] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
673 00:03:18.110510 <6>[ 2.306600] NET: Registered PF_PACKET protocol family
674 00:03:18.116321 <6>[ 2.312170] can: controller area network core
675 00:03:18.122144 <6>[ 2.316993] NET: Registered PF_CAN protocol family
676 00:03:18.122589 <6>[ 2.322217] can: raw protocol
677 00:03:18.127916 <6>[ 2.325541] can: broadcast manager protocol
678 00:03:18.134381 <6>[ 2.330147] can: netlink gateway - max_hops=1
679 00:03:18.140488 <5>[ 2.335678] Key type dns_resolver registered
680 00:03:18.146788 <6>[ 2.340736] ThumbEE CPU extension supported.
681 00:03:18.147236 <5>[ 2.345420] Registering SWP/SWPB emulation handler
682 00:03:18.156534 <3>[ 2.351108] omap_voltage_late_init: Voltage driver support not added
683 00:03:18.372695 <5>[ 2.568762] Loading compiled-in X.509 certificates
684 00:03:18.501978 <6>[ 2.687631] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
685 00:03:18.509271 <6>[ 2.704278] pinctrl-single 44e10800.pinmux: 142 pins, size 568
686 00:03:18.535309 <3>[ 2.727816] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
687 00:03:18.740065 <3>[ 2.932564] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
688 00:03:18.922458 <6>[ 3.119283] OMAP GPIO hardware version 0.1
689 00:03:18.942941 <6>[ 3.137830] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
690 00:03:19.047082 <4>[ 3.241703] at24 2-0054: supply vcc not found, using dummy regulator
691 00:03:19.092974 <4>[ 3.287609] at24 2-0055: supply vcc not found, using dummy regulator
692 00:03:19.128070 <4>[ 3.322626] at24 2-0056: supply vcc not found, using dummy regulator
693 00:03:19.179671 <4>[ 3.374258] at24 2-0057: supply vcc not found, using dummy regulator
694 00:03:19.217233 <6>[ 3.412622] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
695 00:03:19.293948 <3>[ 3.485304] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
696 00:03:19.318443 <6>[ 3.506017] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
697 00:03:19.340344 <4>[ 3.532054] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
698 00:03:19.347944 <4>[ 3.541282] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
699 00:03:19.494712 <6>[ 3.689459] omap_rng 48310000.rng: Random Number Generator ver. 20
700 00:03:19.517997 <5>[ 3.715596] random: crng init done
701 00:03:19.566301 <6>[ 3.759536] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
702 00:03:19.598898 <6>[ 3.795868] Freeing initrd memory: 14448K
703 00:03:19.648842 <6>[ 3.841206] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
704 00:03:19.654667 <6>[ 3.851523] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
705 00:03:19.666401 <6>[ 3.858870] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
706 00:03:19.672195 <6>[ 3.866308] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
707 00:03:19.683728 <6>[ 3.874442] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
708 00:03:19.691144 <6>[ 3.886072] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
709 00:03:19.704216 <5>[ 3.895093] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
710 00:03:19.731816 <3>[ 3.924704] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
711 00:03:19.737603 <6>[ 3.933298] edma 49000000.dma: TI EDMA DMA engine driver
712 00:03:19.808227 <3>[ 4.000362] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
713 00:03:19.822848 <6>[ 4.014687] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
714 00:03:19.835699 <3>[ 4.031728] l3-aon-clkctrl:0000:0: failed to disable
715 00:03:19.883654 <6>[ 4.076472] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
716 00:03:19.889415 <6>[ 4.085982] printk: legacy console [ttyS0] enabled
717 00:03:19.895059 <6>[ 4.085982] printk: legacy console [ttyS0] enabled
718 00:03:19.900715 <6>[ 4.096328] printk: legacy bootconsole [omap8250] disabled
719 00:03:19.906569 <6>[ 4.096328] printk: legacy bootconsole [omap8250] disabled
720 00:03:19.947613 <4>[ 4.139465] tps65217-pmic: Failed to locate of_node [id: -1]
721 00:03:19.951240 <4>[ 4.146862] tps65217-bl: Failed to locate of_node [id: -1]
722 00:03:19.967429 <6>[ 4.166268] tps65217 0-0024: TPS65217 ID 0xe version 1.2
723 00:03:19.987819 <6>[ 4.173195] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
724 00:03:19.999542 <6>[ 4.186884] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
725 00:03:20.002249 <6>[ 4.198792] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
726 00:03:20.025453 <6>[ 4.218437] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
727 00:03:20.031230 <6>[ 4.227683] sdhci-omap 48060000.mmc: Got CD GPIO
728 00:03:20.039317 <4>[ 4.232872] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
729 00:03:20.053956 <4>[ 4.246417] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
730 00:03:20.060454 <4>[ 4.255147] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
731 00:03:20.070176 <4>[ 4.263781] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
732 00:03:20.168824 <6>[ 4.363123] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
733 00:03:20.216562 <6>[ 4.409425] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
734 00:03:20.222926 <6>[ 4.417921] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
735 00:03:20.232085 <6>[ 4.426733] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
736 00:03:20.285344 <6>[ 4.480938] mmc0: new high speed SDHC card at address 1234
737 00:03:20.293810 <6>[ 4.490487] mmcblk0: mmc0:1234 SA32G 29.1 GiB
738 00:03:20.303001 <6>[ 4.501622] mmcblk0: p1
739 00:03:20.320051 <6>[ 4.510585] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
740 00:03:20.348503 <6>[ 4.537486] mmc1: new high speed MMC card at address 0001
741 00:03:20.348988 <6>[ 4.544472] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
742 00:03:20.353887 <6>[ 4.552189] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
743 00:03:20.362134 <6>[ 4.559361] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
744 00:03:20.371211 <6>[ 4.566220] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
745 00:03:22.416974 <6>[ 6.609809] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
746 00:03:22.490312 <5>[ 6.648791] Sending DHCP requests ., OK
747 00:03:22.501674 <6>[ 6.693297] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
748 00:03:22.502180 <6>[ 6.701439] IP-Config: Complete:
749 00:03:22.513006 <6>[ 6.704976] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
750 00:03:22.518880 <6>[ 6.715518] host=192.168.6.12, domain=, nis-domain=(none)
751 00:03:22.531132 <6>[ 6.721748] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
752 00:03:22.531633 <6>[ 6.721783] nameserver0=10.255.253.1
753 00:03:22.537267 <6>[ 6.734388] clk: Disabling unused clocks
754 00:03:22.543025 <6>[ 6.739104] PM: genpd: Disabling unused power domains
755 00:03:22.562375 <6>[ 6.757539] Freeing unused kernel image (initmem) memory: 2048K
756 00:03:22.569822 <6>[ 6.767272] Run /init as init process
757 00:03:22.592384 Loading, please wait...
758 00:03:22.668075 Starting systemd-udevd version 252.22-1~deb12u1
759 00:03:25.748428 <4>[ 9.940091] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 00:03:25.911658 <4>[ 10.103344] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 00:03:26.137573 <6>[ 10.336731] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
762 00:03:26.148440 <6>[ 10.342562] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
763 00:03:26.355602 <6>[ 10.552947] tda998x 0-0070: found TDA19988
764 00:03:26.372611 <6>[ 10.570652] hub 1-0:1.0: USB hub found
765 00:03:26.460492 <6>[ 10.657858] hub 1-0:1.0: 1 port detected
766 00:03:29.323896 Begin: Loading essential drivers ... done.
767 00:03:29.329337 Begin: Running /scripts/init-premount ... done.
768 00:03:29.334916 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
769 00:03:29.342813 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
770 00:03:29.348678 Device /sys/class/net/eth0 found
771 00:03:29.349124 done.
772 00:03:29.664129 Begin: Waiting up to 180 secs for any network device to become available ... done.
773 00:03:29.664766 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
774 00:03:29.665681 IP-Config: eth0 guessed broadcast address 192.168.6.255
775 00:03:29.666109 IP-Config: eth0 complete (dhcp from 192.168.6.1):
776 00:03:29.666525 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
777 00:03:29.666930 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
778 00:03:29.667886 rootserver: 192.168.6.1 rootpath:
779 00:03:29.668372 filename :
780 00:03:29.686937 done.
781 00:03:29.702580 Begin: Running /scripts/nfs-bottom ... done.
782 00:03:29.766098 Begin: Running /scripts/init-bottom ... done.
783 00:03:31.280736 <30>[ 15.475561] systemd[1]: System time before build time, advancing clock.
784 00:03:31.435736 <30>[ 15.604416] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 00:03:31.449949 <30>[ 15.646591] systemd[1]: Detected architecture arm.
786 00:03:31.463462
787 00:03:31.463925 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 00:03:31.464395
789 00:03:31.493574 <30>[ 15.689103] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 00:03:33.677627 <30>[ 17.871895] systemd[1]: Queued start job for default target graphical.target.
791 00:03:33.693987 <30>[ 17.886442] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 00:03:33.701639 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 00:03:33.730031 <30>[ 17.921553] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 00:03:33.737614 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 00:03:33.762275 <30>[ 17.955085] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 00:03:33.775245 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 00:03:33.797452 <30>[ 17.990602] systemd[1]: Created slice user.slice - User and Session Slice.
798 00:03:33.804212 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 00:03:33.833012 <30>[ 18.020195] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 00:03:33.839195 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 00:03:33.856892 <30>[ 18.049903] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 00:03:33.864866 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 00:03:33.897826 <30>[ 18.079813] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 00:03:33.904316 <30>[ 18.100326] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 00:03:33.912811 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 00:03:33.936033 <30>[ 18.129250] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 00:03:33.944331 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 00:03:33.967942 <30>[ 18.160707] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 00:03:33.980265 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 00:03:34.006449 <30>[ 18.199654] systemd[1]: Reached target paths.target - Path Units.
811 00:03:34.011624 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 00:03:34.036258 <30>[ 18.229383] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 00:03:34.043637 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 00:03:34.066222 <30>[ 18.259344] systemd[1]: Reached target slices.target - Slice Units.
815 00:03:34.071745 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 00:03:34.096480 <30>[ 18.289594] systemd[1]: Reached target swap.target - Swaps.
817 00:03:34.100605 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 00:03:34.126683 <30>[ 18.319534] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 00:03:34.134599 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 00:03:34.157508 <30>[ 18.350290] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 00:03:34.165756 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 00:03:34.253034 <30>[ 18.441118] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 00:03:34.265867 <30>[ 18.458547] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 00:03:34.274426 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 00:03:34.298218 <30>[ 18.490505] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 00:03:34.305705 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 00:03:34.329786 <30>[ 18.522417] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 00:03:34.338002 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 00:03:34.367455 <30>[ 18.559575] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 00:03:34.373037 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 00:03:34.397596 <30>[ 18.590427] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 00:03:34.406191 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 00:03:34.433746 <30>[ 18.620595] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 00:03:34.450339 <30>[ 18.637306] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 00:03:34.500374 <30>[ 18.694201] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 00:03:34.528148 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 00:03:34.589891 <30>[ 18.783395] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 00:03:34.603021 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 00:03:34.668419 <30>[ 18.862092] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 00:03:34.695331 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 00:03:34.747128 <30>[ 18.940548] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 00:03:34.766681 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 00:03:34.826159 <30>[ 19.019941] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 00:03:34.847729 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 00:03:34.886975 <30>[ 19.080060] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 00:03:34.893946 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 00:03:34.946971 <30>[ 19.140059] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 00:03:34.962974 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 00:03:35.026013 <30>[ 19.220100] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 00:03:35.037246 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 00:03:35.095787 <30>[ 19.289937] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 00:03:35.107078 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 00:03:35.134108 <28>[ 19.323027] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 00:03:35.149111 <28>[ 19.342206] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 00:03:35.197417 <30>[ 19.391990] systemd[1]: Starting systemd-journald.service - Journal Service...
856 00:03:35.215654 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 00:03:35.286160 <30>[ 19.480032] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 00:03:35.302095 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 00:03:35.347762 <30>[ 19.541866] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 00:03:35.395043 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 00:03:35.441865 <30>[ 19.634415] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 00:03:35.506553 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 00:03:35.577754 <30>[ 19.771014] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 00:03:35.633104 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 00:03:35.708729 <30>[ 19.902860] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 00:03:35.756101 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 00:03:35.787000 <30>[ 19.981095] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 00:03:35.813747 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 00:03:35.840322 <30>[ 20.033357] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 00:03:35.865545 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 00:03:35.976221 <30>[ 20.170980] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 00:03:36.006511 <30>[ 20.200165] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 00:03:36.035893 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 00:03:36.046767 <30>[ 20.241657] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
875 00:03:36.076595 <30>[ 20.270614] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
876 00:03:36.106016 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 00:03:36.116437 <30>[ 20.311668] systemd[1]: modprobe@drm.service: Deactivated successfully.
878 00:03:36.150330 <30>[ 20.344880] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
879 00:03:36.175534 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
880 00:03:36.197448 <30>[ 20.390644] systemd[1]: Started systemd-journald.service - Journal Service.
881 00:03:36.204334 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
882 00:03:36.235249 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
883 00:03:36.268248 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
884 00:03:36.291559 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
885 00:03:36.326078 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
886 00:03:36.356054 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
887 00:03:36.386008 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
888 00:03:36.411022 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
889 00:03:36.475586 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
890 00:03:36.524209 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
891 00:03:36.580944 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
892 00:03:36.659914 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
893 00:03:36.756236 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
894 00:03:36.901183 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
895 00:03:36.922950 <46>[ 21.117096] systemd-journald[163]: Received client request to flush runtime journal.
896 00:03:37.014582 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
897 00:03:37.346081 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
898 00:03:37.898210 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
899 00:03:37.954336 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
900 00:03:38.718638 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
901 00:03:38.838076 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
902 00:03:38.857904 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
903 00:03:38.875605 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
904 00:03:38.956186 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
905 00:03:39.016945 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
906 00:03:39.963112 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
907 00:03:40.035574 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
908 00:03:40.155892 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
909 00:03:40.286061 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
910 00:03:40.330952 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
911 00:03:42.113840 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
912 00:03:42.579892 <5>[ 26.774214] cfg80211: Loading compiled-in X.509 certificates for regulatory database
913 00:03:43.138272 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
914 00:03:44.067593 <5>[ 28.264123] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
915 00:03:44.098077 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
916 00:03:44.115190 <5>[ 28.310130] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
917 00:03:44.137114 <4>[ 28.331420] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
918 00:03:44.143101 <6>[ 28.340541] cfg80211: failed to load regulatory.db
919 00:03:44.746187 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
920 00:03:44.956957 <46>[ 29.141313] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
921 00:03:45.128405 <46>[ 29.315918] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
922 00:03:45.268384 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
923 00:03:54.259475 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
924 00:03:54.292082 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
925 00:03:54.317667 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
926 00:03:54.337816 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
927 00:03:54.405409 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
928 00:03:54.454187 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
929 00:03:54.526198 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
930 00:03:54.599351 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
931 00:03:54.655269 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
932 00:03:54.682546 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
933 00:03:54.711314 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
934 00:03:54.752745 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
935 00:03:54.779114 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
936 00:03:54.836907 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
937 00:03:54.868553 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
938 00:03:54.899636 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
939 00:03:54.931530 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
940 00:03:54.961278 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
941 00:03:54.992274 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
942 00:03:55.015916 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
943 00:03:55.043350 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
944 00:03:55.065858 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
945 00:03:55.092362 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
946 00:03:55.166238 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
947 00:03:55.236695 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
948 00:03:55.294802 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
949 00:03:55.382348 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
950 00:03:55.445095 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
951 00:03:55.496228 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
952 00:03:55.516671 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
953 00:03:55.706017 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
954 00:03:55.756363 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
955 00:03:55.797606 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
956 00:03:55.815608 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
957 00:03:55.888825 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
958 00:03:56.107489 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
959 00:03:56.459226 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
960 00:03:56.527096 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
961 00:03:56.549721 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
962 00:03:56.644315 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
963 00:03:56.811452 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
964 00:03:56.965489
965 00:03:56.968854 Debian GNU/Linux 12 worm-armhf login: root (automatic login)
966 00:03:56.969314
967 00:03:57.289744 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Sat Nov 9 23:01:50 UTC 2024 armv7l
968 00:03:57.290362
969 00:03:57.295104 The programs included with the Debian GNU/Linux system are free software;
970 00:03:57.298478 the exact distribution terms for each program are described in the
971 00:03:57.304042 individual files in /usr/share/doc/*/copyright.
972 00:03:57.304492
973 00:03:57.309808 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
974 00:03:57.314571 permitted by applicable law.
975 00:04:01.927595 Unable to match end of the kernel message
977 00:04:01.929190 Setting prompt string to ['/ #']
978 00:04:01.929766 end: 2.4.4.1 login-action (duration 00:00:47) [common]
980 00:04:01.931158 end: 2.4.4 auto-login-action (duration 00:00:47) [common]
981 00:04:01.931717 start: 2.4.5 expect-shell-connection (timeout 00:03:14) [common]
982 00:04:01.932239 Setting prompt string to ['/ #']
983 00:04:01.932686 Forcing a shell prompt, looking for ['/ #']
985 00:04:01.983727 / #
986 00:04:01.984604 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
987 00:04:01.985104 Waiting using forced prompt support (timeout 00:02:30)
988 00:04:01.988368
989 00:04:01.992616 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
990 00:04:01.993181 start: 2.4.6 export-device-env (timeout 00:03:14) [common]
991 00:04:01.993640 Sending with 10 millisecond of delay
993 00:04:06.982645 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/968538/extract-nfsrootfs-u1vb8hrg'
994 00:04:06.993607 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/968538/extract-nfsrootfs-u1vb8hrg'
995 00:04:06.994724 Sending with 10 millisecond of delay
997 00:04:09.093106 / # export NFS_SERVER_IP='192.168.6.2'
998 00:04:09.103919 export NFS_SERVER_IP='192.168.6.2'
999 00:04:09.104787 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1000 00:04:09.105135 end: 2.4 uboot-commands (duration 00:01:53) [common]
1001 00:04:09.105444 end: 2 uboot-action (duration 00:01:53) [common]
1002 00:04:09.105740 start: 3 lava-test-retry (timeout 00:06:58) [common]
1003 00:04:09.106044 start: 3.1 lava-test-shell (timeout 00:06:58) [common]
1004 00:04:09.106283 Using namespace: common
1006 00:04:09.207016 / # #
1007 00:04:09.207703 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1008 00:04:09.212241 #
1009 00:04:09.218770 Using /lava-968538
1011 00:04:09.319560 / # export SHELL=/bin/bash
1012 00:04:09.323880 export SHELL=/bin/bash
1014 00:04:09.432062 / # . /lava-968538/environment
1015 00:04:09.437679 . /lava-968538/environment
1017 00:04:09.551437 / # /lava-968538/bin/lava-test-runner /lava-968538/0
1018 00:04:09.552188 Test shell timeout: 10s (minimum of the action and connection timeout)
1019 00:04:09.556787 /lava-968538/bin/lava-test-runner /lava-968538/0
1020 00:04:09.991097 + export TESTRUN_ID=0_timesync-off
1021 00:04:09.999030 + TESTRUN_ID=0_timesync-off
1022 00:04:09.999550 + cd /lava-968538/0/tests/0_timesync-off
1023 00:04:09.999969 ++ cat uuid
1024 00:04:10.015173 + UUID=968538_1.6.2.4.1
1025 00:04:10.015689 + set +x
1026 00:04:10.023698 <LAVA_SIGNAL_STARTRUN 0_timesync-off 968538_1.6.2.4.1>
1027 00:04:10.024242 + systemctl stop systemd-timesyncd
1028 00:04:10.024950 Received signal: <STARTRUN> 0_timesync-off 968538_1.6.2.4.1
1029 00:04:10.025382 Starting test lava.0_timesync-off (968538_1.6.2.4.1)
1030 00:04:10.025886 Skipping test definition patterns.
1031 00:04:10.326940 + set +x
1032 00:04:10.327554 <LAVA_SIGNAL_ENDRUN 0_timesync-off 968538_1.6.2.4.1>
1033 00:04:10.328228 Received signal: <ENDRUN> 0_timesync-off 968538_1.6.2.4.1
1034 00:04:10.328729 Ending use of test pattern.
1035 00:04:10.329137 Ending test lava.0_timesync-off (968538_1.6.2.4.1), duration 0.30
1037 00:04:10.506080 + export TESTRUN_ID=1_kselftest-dt
1038 00:04:10.514011 + TESTRUN_ID=1_kselftest-dt
1039 00:04:10.514369 + cd /lava-968538/0/tests/1_kselftest-dt
1040 00:04:10.514613 ++ cat uuid
1041 00:04:10.530065 + UUID=968538_1.6.2.4.5
1042 00:04:10.530439 + set +x
1043 00:04:10.535691 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 968538_1.6.2.4.5>
1044 00:04:10.536081 + cd ./automated/linux/kselftest/
1045 00:04:10.536588 Received signal: <STARTRUN> 1_kselftest-dt 968538_1.6.2.4.5
1046 00:04:10.536872 Starting test lava.1_kselftest-dt (968538_1.6.2.4.5)
1047 00:04:10.537167 Skipping test definition patterns.
1048 00:04:10.563912 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1049 00:04:10.664274 INFO: install_deps skipped
1050 00:04:11.319535 --2024-11-10 00:04:11-- http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1051 00:04:11.342070 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1052 00:04:11.487693 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1053 00:04:11.631744 HTTP request sent, awaiting response... 200 OK
1054 00:04:11.632422 Length: 4106796 (3.9M) [application/octet-stream]
1055 00:04:11.637212 Saving to: 'kselftest_armhf.tar.gz'
1056 00:04:11.637724
1057 00:04:13.282977
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 174KB/s
kselftest_armhf.tar 5%[> ] 218.67K 382KB/s
kselftest_armhf.tar 22%[===> ] 892.70K 1.02MB/s
kselftest_armhf.tar 41%[=======> ] 1.64M 1.48MB/s
kselftest_armhf.tar 79%[==============> ] 3.11M 2.30MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 2.39MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 2.39MB/s in 1.6s
1058 00:04:13.283627
1059 00:04:13.932412 2024-11-10 00:04:13 (2.39 MB/s) - 'kselftest_armhf.tar.gz' saved [4106796/4106796]
1060 00:04:13.933051
1061 00:04:26.546593 skiplist:
1062 00:04:26.547132 ========================================
1063 00:04:26.552121 ========================================
1064 00:04:26.651495 dt:test_unprobed_devices.sh
1065 00:04:26.686329 ============== Tests to run ===============
1066 00:04:26.692959 dt:test_unprobed_devices.sh
1067 00:04:26.695785 ===========End Tests to run ===============
1068 00:04:26.704069 shardfile-dt pass
1069 00:04:26.931396 <12>[ 71.131497] kselftest: Running tests in dt
1070 00:04:26.959270 TAP version 13
1071 00:04:26.982291 1..1
1072 00:04:27.036144 # timeout set to 45
1073 00:04:27.036533 # selftests: dt: test_unprobed_devices.sh
1074 00:04:27.968183 # TAP version 13
1075 00:04:52.772281 # 1..257
1076 00:04:52.946431 # ok 1 / # SKIP
1077 00:04:52.972491 # ok 2 /clk_mcasp0
1078 00:04:53.039308 # ok 3 /clk_mcasp0_fixed # SKIP
1079 00:04:53.109763 # ok 4 /cpus/cpu@0 # SKIP
1080 00:04:53.184801 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1081 00:04:53.205354 # ok 6 /fixedregulator0
1082 00:04:53.224022 # ok 7 /leds
1083 00:04:53.243418 # ok 8 /ocp
1084 00:04:53.270987 # ok 9 /ocp/interconnect@44c00000
1085 00:04:53.290139 # ok 10 /ocp/interconnect@44c00000/segment@0
1086 00:04:53.317436 # ok 11 /ocp/interconnect@44c00000/segment@100000
1087 00:04:53.337027 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1088 00:04:53.409508 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1089 00:04:53.430091 # ok 14 /ocp/interconnect@44c00000/segment@200000
1090 00:04:53.458045 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1091 00:04:53.559510 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1092 00:04:53.629950 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1093 00:04:53.704555 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1094 00:04:53.777271 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1095 00:04:53.849256 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1096 00:04:53.921158 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1097 00:04:53.987917 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1098 00:04:54.061352 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1099 00:04:54.130554 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1100 00:04:54.206523 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1101 00:04:54.276879 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1102 00:04:54.348694 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1103 00:04:54.429920 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1104 00:04:54.500734 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1105 00:04:54.568754 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1106 00:04:54.644241 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1107 00:04:54.711509 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1108 00:04:54.783735 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1109 00:04:54.853669 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1110 00:04:54.924680 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1111 00:04:54.996735 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1112 00:04:55.068304 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1113 00:04:55.140500 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1114 00:04:55.212996 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1115 00:04:55.283681 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1116 00:04:55.359744 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1117 00:04:55.432145 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1118 00:04:55.502075 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1119 00:04:55.569401 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1120 00:04:55.641868 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1121 00:04:55.713467 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1122 00:04:55.784822 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1123 00:04:55.856483 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1124 00:04:55.928452 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1125 00:04:55.999874 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1126 00:04:56.071367 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1127 00:04:56.147104 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1128 00:04:56.214811 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1129 00:04:56.286416 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1130 00:04:56.357610 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1131 00:04:56.429274 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1132 00:04:56.500895 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1133 00:04:56.572662 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1134 00:04:56.644080 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1135 00:04:56.715973 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1136 00:04:56.786980 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1137 00:04:56.858228 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1138 00:04:56.929709 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1139 00:04:57.001351 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1140 00:04:57.076211 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1141 00:04:57.143084 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1142 00:04:57.214752 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1143 00:04:57.285078 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1144 00:04:57.355494 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1145 00:04:57.427764 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1146 00:04:57.500086 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1147 00:04:57.571952 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1148 00:04:57.652039 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1149 00:04:57.720080 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1150 00:04:57.791196 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1151 00:04:57.865141 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1152 00:04:57.938689 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1153 00:04:58.012103 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1154 00:04:58.088270 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1155 00:04:58.160979 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1156 00:04:58.231893 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1157 00:04:58.303247 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1158 00:04:58.373032 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1159 00:04:58.445156 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1160 00:04:58.516077 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1161 00:04:58.587412 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1162 00:04:58.659058 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1163 00:04:58.730077 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1164 00:04:58.848273 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1165 00:04:58.927861 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1166 00:04:58.998186 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1167 00:04:59.071310 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1168 00:04:59.142378 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1169 00:04:59.210473 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1170 00:04:59.231456 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1171 00:04:59.255319 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1172 00:04:59.278831 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1173 00:04:59.302822 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1174 00:04:59.329448 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1175 00:04:59.356320 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1176 00:04:59.373174 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1177 00:04:59.398548 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1178 00:04:59.507413 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1179 00:04:59.530206 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1180 00:04:59.552246 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1181 00:04:59.575678 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1182 00:04:59.680531 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1183 00:04:59.758051 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1184 00:04:59.829283 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1185 00:04:59.896659 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1186 00:04:59.968143 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1187 00:05:00.039427 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1188 00:05:00.111416 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1189 00:05:00.182481 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1190 00:05:00.252712 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1191 00:05:00.330879 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1192 00:05:00.398026 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1193 00:05:00.469470 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1194 00:05:00.540198 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1195 00:05:00.614292 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1196 00:05:00.686533 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1197 00:05:00.758569 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1198 00:05:00.779582 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1199 00:05:00.849616 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1200 00:05:00.921217 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1201 00:05:00.989042 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1202 00:05:01.012842 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1203 00:05:01.084120 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1204 00:05:01.106301 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1205 00:05:01.179449 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1206 00:05:01.199314 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1207 00:05:01.227838 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1208 00:05:01.248519 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1209 00:05:01.275765 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1210 00:05:01.297838 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1211 00:05:01.319118 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1212 00:05:01.344004 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1213 00:05:01.417174 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1214 00:05:01.438430 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1215 00:05:01.462126 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1216 00:05:01.533664 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1217 00:05:01.603718 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1218 00:05:01.624871 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1219 00:05:01.725949 # not ok 144 /ocp/interconnect@47c00000
1220 00:05:01.800705 # not ok 145 /ocp/interconnect@47c00000/segment@0
1221 00:05:01.818230 # ok 146 /ocp/interconnect@48000000
1222 00:05:01.845908 # ok 147 /ocp/interconnect@48000000/segment@0
1223 00:05:01.866216 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1224 00:05:01.889752 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1225 00:05:01.917124 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1226 00:05:01.938255 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1227 00:05:01.963616 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1228 00:05:01.988794 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1229 00:05:02.006458 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1230 00:05:02.078433 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1231 00:05:02.154605 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1232 00:05:02.176332 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1233 00:05:02.198899 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1234 00:05:02.225049 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1235 00:05:02.242163 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1236 00:05:02.264978 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1237 00:05:02.291565 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1238 00:05:02.315842 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1239 00:05:02.338844 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1240 00:05:02.364599 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1241 00:05:02.382154 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1242 00:05:02.405042 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1243 00:05:02.429364 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1244 00:05:02.451587 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1245 00:05:02.478569 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1246 00:05:02.503413 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1247 00:05:02.523115 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1248 00:05:02.544987 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1249 00:05:02.575576 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1250 00:05:02.595351 # ok 175 /ocp/interconnect@48000000/segment@100000
1251 00:05:02.618411 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1252 00:05:02.639945 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1253 00:05:02.714684 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1254 00:05:02.787737 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1255 00:05:02.857295 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1256 00:05:02.930204 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1257 00:05:03.000387 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1258 00:05:03.077545 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1259 00:05:03.142568 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1260 00:05:03.215668 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1261 00:05:03.235094 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1262 00:05:03.261965 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1263 00:05:03.281874 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1264 00:05:03.304952 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1265 00:05:03.330253 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1266 00:05:03.352041 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1267 00:05:03.375195 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1268 00:05:03.403338 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1269 00:05:03.422580 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1270 00:05:03.448688 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1271 00:05:03.476309 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1272 00:05:03.498370 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1273 00:05:03.514765 # ok 198 /ocp/interconnect@48000000/segment@200000
1274 00:05:03.540419 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1275 00:05:03.619613 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1276 00:05:03.643968 # ok 201 /ocp/interconnect@48000000/segment@300000
1277 00:05:03.676685 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1278 00:05:03.698488 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1279 00:05:03.719930 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1280 00:05:03.742591 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1281 00:05:03.765693 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1282 00:05:03.789290 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1283 00:05:03.865568 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1284 00:05:03.883920 # ok 209 /ocp/interconnect@4a000000
1285 00:05:03.906193 # ok 210 /ocp/interconnect@4a000000/segment@0
1286 00:05:03.932830 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1287 00:05:03.957229 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1288 00:05:03.979733 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1289 00:05:03.999926 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1290 00:05:04.075343 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1291 00:05:04.180352 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1292 00:05:04.246971 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1293 00:05:04.349695 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1294 00:05:04.419636 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1295 00:05:04.494238 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1296 00:05:04.587201 # not ok 221 /ocp/interconnect@4b140000
1297 00:05:04.663836 # not ok 222 /ocp/interconnect@4b140000/segment@0
1298 00:05:04.734888 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1299 00:05:04.755357 # ok 224 /ocp/target-module@40300000
1300 00:05:04.775163 # ok 225 /ocp/target-module@40300000/sram@0
1301 00:05:04.847897 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1302 00:05:04.920648 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1303 00:05:04.943899 # ok 228 /ocp/target-module@47400000
1304 00:05:04.967363 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1305 00:05:04.989050 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1306 00:05:05.013941 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1307 00:05:05.035659 # ok 232 /ocp/target-module@47400000/usb@1400
1308 00:05:05.053641 # ok 233 /ocp/target-module@47400000/usb@1800
1309 00:05:05.075258 # ok 234 /ocp/target-module@47810000
1310 00:05:05.101421 # ok 235 /ocp/target-module@49000000
1311 00:05:05.124034 # ok 236 /ocp/target-module@49000000/dma@0
1312 00:05:05.141534 # ok 237 /ocp/target-module@49800000
1313 00:05:05.165878 # ok 238 /ocp/target-module@49800000/dma@0
1314 00:05:05.186067 # ok 239 /ocp/target-module@49900000
1315 00:05:05.213075 # ok 240 /ocp/target-module@49900000/dma@0
1316 00:05:05.234757 # ok 241 /ocp/target-module@49a00000
1317 00:05:05.256103 # ok 242 /ocp/target-module@49a00000/dma@0
1318 00:05:05.275812 # ok 243 /ocp/target-module@4c000000
1319 00:05:05.348012 # not ok 244 /ocp/target-module@4c000000/emif@0
1320 00:05:05.368246 # ok 245 /ocp/target-module@50000000
1321 00:05:05.394160 # ok 246 /ocp/target-module@53100000
1322 00:05:05.465060 # not ok 247 /ocp/target-module@53100000/sham@0
1323 00:05:05.481970 # ok 248 /ocp/target-module@53500000
1324 00:05:05.556239 # not ok 249 /ocp/target-module@53500000/aes@0
1325 00:05:05.573852 # ok 250 /ocp/target-module@56000000
1326 00:05:05.681413 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1327 00:05:05.745830 # ok 252 /opp-table # SKIP
1328 00:05:05.814433 # ok 253 /soc # SKIP
1329 00:05:05.835592 # ok 254 /sound
1330 00:05:05.863205 # ok 255 /target-module@4b000000
1331 00:05:05.887098 # ok 256 /target-module@4b000000/target-module@140000
1332 00:05:05.904457 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1333 00:05:05.912775 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1334 00:05:05.921129 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1335 00:05:08.029565 dt_test_unprobed_devices_sh_ skip
1336 00:05:08.034866 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1337 00:05:08.040527 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1338 00:05:08.041033 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1339 00:05:08.049459 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1340 00:05:08.049907 dt_test_unprobed_devices_sh_fixedregulator0 pass
1341 00:05:08.055106 dt_test_unprobed_devices_sh_leds pass
1342 00:05:08.060653 dt_test_unprobed_devices_sh_ocp pass
1343 00:05:08.061085 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1344 00:05:08.069709 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1345 00:05:08.075375 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1346 00:05:08.084358 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1347 00:05:08.089859 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1348 00:05:08.101175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1349 00:05:08.104621 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1350 00:05:08.115844 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1351 00:05:08.124954 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1352 00:05:08.135965 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1353 00:05:08.147166 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1354 00:05:08.152738 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1355 00:05:08.163970 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1356 00:05:08.175199 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1357 00:05:08.186453 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1358 00:05:08.197677 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1359 00:05:08.203293 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1360 00:05:08.214453 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1361 00:05:08.225658 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1362 00:05:08.236836 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1363 00:05:08.248003 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1364 00:05:08.253605 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1365 00:05:08.264795 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1366 00:05:08.275967 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1367 00:05:08.287265 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1368 00:05:08.292800 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1369 00:05:08.303962 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1370 00:05:08.315143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1371 00:05:08.326272 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1372 00:05:08.331865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1373 00:05:08.343099 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1374 00:05:08.354296 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1375 00:05:08.365424 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1376 00:05:08.376652 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1377 00:05:08.387831 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1378 00:05:08.399031 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1379 00:05:08.410249 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1380 00:05:08.421436 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1381 00:05:08.432633 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1382 00:05:08.443809 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1383 00:05:08.455011 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1384 00:05:08.466288 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1385 00:05:08.477399 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1386 00:05:08.488572 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1387 00:05:08.499773 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1388 00:05:08.510955 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1389 00:05:08.522124 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1390 00:05:08.533337 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1391 00:05:08.544541 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1392 00:05:08.555722 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1393 00:05:08.566909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1394 00:05:08.578122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1395 00:05:08.589325 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1396 00:05:08.600497 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1397 00:05:08.611653 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1398 00:05:08.622850 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1399 00:05:08.628453 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1400 00:05:08.639664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1401 00:05:08.650840 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1402 00:05:08.662049 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1403 00:05:08.673299 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1404 00:05:08.684441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1405 00:05:08.695616 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1406 00:05:08.706783 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1407 00:05:08.717996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1408 00:05:08.729293 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1409 00:05:08.740392 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1410 00:05:08.751555 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1411 00:05:08.762753 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1412 00:05:08.773940 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1413 00:05:08.785186 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1414 00:05:08.796352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1415 00:05:08.807523 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1416 00:05:08.818731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1417 00:05:08.824378 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1418 00:05:08.835553 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1419 00:05:08.846726 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1420 00:05:08.857938 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1421 00:05:08.869187 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1422 00:05:08.874712 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1423 00:05:08.885850 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1424 00:05:08.902710 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1425 00:05:08.908325 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1426 00:05:08.925070 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1427 00:05:08.936356 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1428 00:05:08.947476 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1429 00:05:08.953053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1430 00:05:08.964337 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1431 00:05:08.975416 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1432 00:05:08.981009 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1433 00:05:08.992232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1434 00:05:09.003404 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1435 00:05:09.008996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1436 00:05:09.020237 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1437 00:05:09.025833 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1438 00:05:09.036970 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1439 00:05:09.048198 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1440 00:05:09.059392 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1441 00:05:09.070551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1442 00:05:09.081726 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1443 00:05:09.092928 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1444 00:05:09.104175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1445 00:05:09.115353 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1446 00:05:09.126505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1447 00:05:09.137689 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1448 00:05:09.148877 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1449 00:05:09.160062 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1450 00:05:09.176870 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1451 00:05:09.188070 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1452 00:05:09.199234 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1453 00:05:09.210415 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1454 00:05:09.221621 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1455 00:05:09.238421 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1456 00:05:09.249588 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1457 00:05:09.260779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1458 00:05:09.271957 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1459 00:05:09.277555 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1460 00:05:09.288744 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1461 00:05:09.294367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1462 00:05:09.305532 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1463 00:05:09.316729 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1464 00:05:09.322391 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1465 00:05:09.333519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1466 00:05:09.339121 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1467 00:05:09.350381 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1468 00:05:09.355891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1469 00:05:09.367097 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1470 00:05:09.372671 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1471 00:05:09.383909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1472 00:05:09.395152 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1473 00:05:09.406419 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1474 00:05:09.417549 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1475 00:05:09.423138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1476 00:05:09.434392 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1477 00:05:09.445542 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1478 00:05:09.451082 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1479 00:05:09.456696 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1480 00:05:09.462415 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1481 00:05:09.467914 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1482 00:05:09.473487 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1483 00:05:09.484693 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1484 00:05:09.490281 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1485 00:05:09.495910 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1486 00:05:09.507059 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1487 00:05:09.512670 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1488 00:05:09.523843 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1489 00:05:09.529460 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1490 00:05:09.540655 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1491 00:05:09.546305 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1492 00:05:09.557469 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1493 00:05:09.563069 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1494 00:05:09.574265 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1495 00:05:09.579799 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1496 00:05:09.591018 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1497 00:05:09.596598 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1498 00:05:09.602191 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1499 00:05:09.613446 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1500 00:05:09.618992 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1501 00:05:09.630184 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1502 00:05:09.635793 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1503 00:05:09.646951 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1504 00:05:09.652573 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1505 00:05:09.663733 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1506 00:05:09.669421 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1507 00:05:09.680559 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1508 00:05:09.686093 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1509 00:05:09.691678 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1510 00:05:09.702914 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1511 00:05:09.708483 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1512 00:05:09.719682 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1513 00:05:09.730882 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1514 00:05:09.742091 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1515 00:05:09.753299 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1516 00:05:09.764491 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1517 00:05:09.775712 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1518 00:05:09.786954 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1519 00:05:09.798175 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1520 00:05:09.803795 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1521 00:05:09.815018 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1522 00:05:09.820633 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1523 00:05:09.831842 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1524 00:05:09.837546 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1525 00:05:09.848765 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1526 00:05:09.854316 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1527 00:05:09.865508 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1528 00:05:09.871100 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1529 00:05:09.882309 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1530 00:05:09.887874 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1531 00:05:09.899137 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1532 00:05:09.904699 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1533 00:05:09.915885 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1534 00:05:09.921471 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1535 00:05:09.927094 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1536 00:05:09.938256 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1537 00:05:09.943850 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1538 00:05:09.955032 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1539 00:05:09.960654 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1540 00:05:09.971848 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1541 00:05:09.977504 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1542 00:05:09.988629 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1543 00:05:09.994237 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1544 00:05:09.999777 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1545 00:05:10.005534 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1546 00:05:10.016655 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1547 00:05:10.022263 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1548 00:05:10.033450 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1549 00:05:10.038951 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1550 00:05:10.050131 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1551 00:05:10.061366 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1552 00:05:10.072531 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1553 00:05:10.083724 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1554 00:05:10.089348 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1555 00:05:10.094968 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1556 00:05:10.100565 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1557 00:05:10.106194 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1558 00:05:10.111799 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1559 00:05:10.117493 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1560 00:05:10.128633 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1561 00:05:10.134240 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1562 00:05:10.139861 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1563 00:05:10.145481 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1564 00:05:10.151025 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1565 00:05:10.162235 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1566 00:05:10.167824 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1567 00:05:10.173509 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1568 00:05:10.179011 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1569 00:05:10.184617 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1570 00:05:10.190244 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1571 00:05:10.195802 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1572 00:05:10.201493 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1573 00:05:10.207014 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1574 00:05:10.212616 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1575 00:05:10.218236 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1576 00:05:10.223796 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1577 00:05:10.229509 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1578 00:05:10.235012 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1579 00:05:10.240640 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1580 00:05:10.246209 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1581 00:05:10.251817 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1582 00:05:10.257472 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1583 00:05:10.263019 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1584 00:05:10.268636 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1585 00:05:10.274220 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1586 00:05:10.274648 dt_test_unprobed_devices_sh_opp-table skip
1587 00:05:10.279813 dt_test_unprobed_devices_sh_soc skip
1588 00:05:10.285510 dt_test_unprobed_devices_sh_sound pass
1589 00:05:10.285944 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1590 00:05:10.296654 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1591 00:05:10.302269 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1592 00:05:10.307883 dt_test_unprobed_devices_sh fail
1593 00:05:10.308344 + ../../utils/send-to-lava.sh ./output/result.txt
1594 00:05:10.315578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1595 00:05:10.316489 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1597 00:05:10.329245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1598 00:05:10.329931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1600 00:05:10.422129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1601 00:05:10.422866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1603 00:05:10.511259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1604 00:05:10.512035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1606 00:05:10.595635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1607 00:05:10.596447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1609 00:05:10.681418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1610 00:05:10.682132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1612 00:05:10.771264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1613 00:05:10.771950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1615 00:05:10.861289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1616 00:05:10.861974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1618 00:05:10.945553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1619 00:05:10.946311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1621 00:05:11.037221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1622 00:05:11.037966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1624 00:05:11.124020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1625 00:05:11.124737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1627 00:05:11.213796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1628 00:05:11.214491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1630 00:05:11.300255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1631 00:05:11.301069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1633 00:05:11.386317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1634 00:05:11.387125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1636 00:05:11.475399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1637 00:05:11.476165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1639 00:05:11.566913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1640 00:05:11.567671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1642 00:05:11.651886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1643 00:05:11.652622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1645 00:05:11.746075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1646 00:05:11.746788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1648 00:05:11.837054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1649 00:05:11.837794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1651 00:05:11.928391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1652 00:05:11.929129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1654 00:05:12.013402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1655 00:05:12.014098 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1657 00:05:12.099492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1658 00:05:12.100273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1660 00:05:12.190470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1661 00:05:12.191162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1663 00:05:12.278382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1664 00:05:12.279069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1666 00:05:12.366452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1667 00:05:12.367164 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1669 00:05:12.460279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1670 00:05:12.461102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1672 00:05:12.544306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1673 00:05:12.545085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1675 00:05:12.635959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1676 00:05:12.636759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1678 00:05:12.728414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1679 00:05:12.729110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1681 00:05:12.817551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1682 00:05:12.818245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1684 00:05:12.902113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1685 00:05:12.902814 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1687 00:05:12.989081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1688 00:05:12.989808 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1690 00:05:13.078840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1691 00:05:13.079604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1693 00:05:13.165169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1694 00:05:13.165932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1696 00:05:13.256242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1697 00:05:13.256918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1699 00:05:13.349007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1700 00:05:13.349748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1702 00:05:13.434002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1703 00:05:13.434747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1705 00:05:13.526087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1706 00:05:13.526849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1708 00:05:13.618044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1709 00:05:13.618799 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1711 00:05:13.709726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1712 00:05:13.710435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1714 00:05:13.800213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1715 00:05:13.800917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1717 00:05:13.888531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1718 00:05:13.889221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1720 00:05:13.979331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1721 00:05:13.980061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1723 00:05:14.070503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1724 00:05:14.071231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1726 00:05:14.155460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1727 00:05:14.156215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1729 00:05:14.245816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1730 00:05:14.246518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1732 00:05:14.331401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1733 00:05:14.332105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1735 00:05:14.424433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1736 00:05:14.425166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1738 00:05:14.515250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1739 00:05:14.516050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1741 00:05:14.606995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1742 00:05:14.607771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1744 00:05:14.698381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1745 00:05:14.699088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1747 00:05:14.789115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1748 00:05:14.789802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1750 00:05:14.879132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1751 00:05:14.879813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1753 00:05:14.969261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1754 00:05:14.969993 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1756 00:05:15.054929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1757 00:05:15.055660 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1759 00:05:15.145347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1760 00:05:15.146053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1762 00:05:15.232195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1763 00:05:15.232889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1765 00:05:15.323320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1766 00:05:15.324062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1768 00:05:15.407855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1769 00:05:15.408607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1771 00:05:15.498473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1772 00:05:15.499208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1774 00:05:15.588106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1775 00:05:15.588940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1777 00:05:15.678186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1778 00:05:15.678936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1780 00:05:15.768481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1781 00:05:15.769265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1783 00:05:15.860723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1784 00:05:15.861496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1786 00:05:15.951694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1787 00:05:15.952521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1789 00:05:16.037500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1790 00:05:16.038367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1792 00:05:16.130101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1793 00:05:16.130918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1795 00:05:16.221968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1796 00:05:16.222790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1798 00:05:16.308242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1799 00:05:16.309028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1801 00:05:16.398675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1802 00:05:16.399453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1804 00:05:16.490170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1805 00:05:16.490909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1807 00:05:16.575613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1808 00:05:16.576428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1810 00:05:16.667122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1811 00:05:16.667846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1813 00:05:16.759518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1814 00:05:16.760214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1816 00:05:16.850237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1817 00:05:16.850944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1819 00:05:16.935645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1820 00:05:16.936401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1822 00:05:17.027820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1823 00:05:17.028588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1825 00:05:17.119029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1826 00:05:17.119751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1828 00:05:17.208784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1829 00:05:17.209481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1831 00:05:17.294229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1832 00:05:17.294916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1834 00:05:17.380156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1835 00:05:17.380877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1837 00:05:17.471696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1838 00:05:17.472504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1840 00:05:17.558424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1841 00:05:17.559179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1843 00:05:17.646785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1844 00:05:17.647518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1846 00:05:17.737362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1847 00:05:17.738059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1849 00:05:17.829277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1850 00:05:17.829966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1852 00:05:17.914361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1853 00:05:17.915086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1855 00:05:18.006146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1856 00:05:18.006845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1858 00:05:18.097564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1859 00:05:18.098306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1861 00:05:18.190997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1862 00:05:18.191757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1864 00:05:18.276188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1865 00:05:18.276866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1867 00:05:18.359920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1868 00:05:18.360698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1870 00:05:18.452849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1871 00:05:18.453589 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1873 00:05:18.538623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1874 00:05:18.539409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1876 00:05:18.629929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1877 00:05:18.630673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1879 00:05:18.713279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1880 00:05:18.713973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1882 00:05:18.805434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1883 00:05:18.806131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1885 00:05:18.897534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1886 00:05:18.898226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1888 00:05:18.988901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1889 00:05:18.989631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1891 00:05:19.074326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1892 00:05:19.075055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1894 00:05:19.166084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1895 00:05:19.166797 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1897 00:05:19.258377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1898 00:05:19.259074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1900 00:05:19.343446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1901 00:05:19.344160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1903 00:05:19.436248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1904 00:05:19.437006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1906 00:05:19.529118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1907 00:05:19.529881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1909 00:05:19.618309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1910 00:05:19.619061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1912 00:05:19.707939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1913 00:05:19.708680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1915 00:05:19.798852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1916 00:05:19.799547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1918 00:05:19.886033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1919 00:05:19.886720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1921 00:05:19.978870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1922 00:05:19.979597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1924 00:05:20.064923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1925 00:05:20.065658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1927 00:05:20.156074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1928 00:05:20.156783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1930 00:05:20.247847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1931 00:05:20.248594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1933 00:05:20.341210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1934 00:05:20.341907 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1936 00:05:20.433829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1937 00:05:20.434553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1939 00:05:20.519432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1940 00:05:20.520178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1942 00:05:20.610932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1943 00:05:20.611691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1945 00:05:20.696145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1946 00:05:20.696857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1948 00:05:20.786718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1949 00:05:20.787411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1951 00:05:20.871058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1952 00:05:20.871759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1954 00:05:20.956021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1956 00:05:20.959095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1957 00:05:21.048526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1959 00:05:21.051626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1960 00:05:21.140545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1962 00:05:21.143601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1963 00:05:21.228661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1964 00:05:21.229354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1966 00:05:21.317800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1967 00:05:21.318492 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1969 00:05:21.406255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1970 00:05:21.406971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1972 00:05:21.492928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1973 00:05:21.493664 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1975 00:05:21.583922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1976 00:05:21.584789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1978 00:05:21.675303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1979 00:05:21.676072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1981 00:05:21.766227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1982 00:05:21.766958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1984 00:05:21.852493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1985 00:05:21.853197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1987 00:05:21.938487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1988 00:05:21.939217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1990 00:05:22.030278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1991 00:05:22.031028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1993 00:05:22.115641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1994 00:05:22.116416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1996 00:05:22.207636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1997 00:05:22.208387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1999 00:05:22.298532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2000 00:05:22.299227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2002 00:05:22.386139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2003 00:05:22.386931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2005 00:05:22.479194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2006 00:05:22.479928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2008 00:05:22.572146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2009 00:05:22.572917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2011 00:05:22.657135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2012 00:05:22.657852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2014 00:05:22.747445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2015 00:05:22.748166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2017 00:05:22.839270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2018 00:05:22.839970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2020 00:05:22.927542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2021 00:05:22.928302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2023 00:05:23.016142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2024 00:05:23.016857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2026 00:05:23.105030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2027 00:05:23.105748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2029 00:05:23.193833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2030 00:05:23.194594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2032 00:05:23.282261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2033 00:05:23.282931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2035 00:05:23.374061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2036 00:05:23.374790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2038 00:05:23.461985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2039 00:05:23.462738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2041 00:05:23.553655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2042 00:05:23.554419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2044 00:05:23.645382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2045 00:05:23.646198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2047 00:05:23.737817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2048 00:05:23.738519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2050 00:05:23.829746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2051 00:05:23.830454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2053 00:05:23.917154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2054 00:05:23.917849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2056 00:05:24.001940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2057 00:05:24.002663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2059 00:05:24.094250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2060 00:05:24.094972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2062 00:05:24.186096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2063 00:05:24.186811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2065 00:05:24.271408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2066 00:05:24.272163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2068 00:05:24.358237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2069 00:05:24.358981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2071 00:05:24.444437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2072 00:05:24.445232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2074 00:05:24.536302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2075 00:05:24.537103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2077 00:05:24.626738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2078 00:05:24.627501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2080 00:05:24.712896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2081 00:05:24.713623 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2083 00:05:24.804200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2084 00:05:24.804900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2086 00:05:24.896063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2087 00:05:24.896775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2089 00:05:24.986542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2090 00:05:24.987282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2092 00:05:25.072918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2093 00:05:25.073739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2095 00:05:25.164776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2096 00:05:25.165518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2098 00:05:25.254828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2099 00:05:25.255547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2101 00:05:25.345373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2102 00:05:25.346112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2104 00:05:25.437010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2105 00:05:25.437782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2107 00:05:25.524512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2108 00:05:25.525296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2110 00:05:25.615852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2111 00:05:25.616697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2113 00:05:25.706339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2114 00:05:25.707071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2116 00:05:25.792984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2117 00:05:25.793716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2119 00:05:25.881641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2120 00:05:25.882356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2122 00:05:25.976290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2123 00:05:25.977018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2125 00:05:26.065622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2126 00:05:26.066461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2128 00:05:26.157759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2129 00:05:26.158511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2131 00:05:26.244091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2132 00:05:26.244897 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2134 00:05:26.333391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2135 00:05:26.334176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2137 00:05:26.419896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2138 00:05:26.420790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2140 00:05:26.503942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2141 00:05:26.504760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2143 00:05:26.591113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2144 00:05:26.591907 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2146 00:05:26.680475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2147 00:05:26.681214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2149 00:05:26.768171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2150 00:05:26.768886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2152 00:05:26.857063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2153 00:05:26.857827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2155 00:05:26.948375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2156 00:05:26.949104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2158 00:05:27.035677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2159 00:05:27.036539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2161 00:05:27.126765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2162 00:05:27.127510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2164 00:05:27.217946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2165 00:05:27.218666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2167 00:05:27.306525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2168 00:05:27.307249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2170 00:05:27.395877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2171 00:05:27.396648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2173 00:05:27.487977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2174 00:05:27.488763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2176 00:05:27.575477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2177 00:05:27.576300 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2179 00:05:27.665653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2180 00:05:27.666372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2182 00:05:27.756144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2183 00:05:27.756860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2185 00:05:27.841969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2186 00:05:27.842688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2188 00:05:27.932078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2189 00:05:27.932826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2191 00:05:28.025469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2192 00:05:28.026324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2194 00:05:28.117085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2195 00:05:28.117884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2197 00:05:28.201481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2198 00:05:28.202294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2200 00:05:28.295616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2201 00:05:28.296425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2203 00:05:28.385365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2204 00:05:28.386213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2206 00:05:28.477498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2207 00:05:28.478339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2209 00:05:28.561561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2210 00:05:28.562222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2212 00:05:28.653267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2213 00:05:28.654113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2215 00:05:28.744352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2216 00:05:28.745128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2218 00:05:28.837612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2219 00:05:28.838382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2221 00:05:28.938498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2222 00:05:28.939400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2224 00:05:29.035714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2225 00:05:29.037027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2227 00:05:29.128344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2228 00:05:29.129210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2230 00:05:29.219631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2231 00:05:29.220430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2233 00:05:29.305621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2234 00:05:29.306363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2236 00:05:29.394040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2237 00:05:29.394826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2239 00:05:29.484593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2240 00:05:29.485431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2242 00:05:29.576430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2243 00:05:29.577057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2245 00:05:29.669456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2246 00:05:29.670213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2248 00:05:29.753735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2249 00:05:29.754487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2251 00:05:29.845322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2252 00:05:29.846058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2254 00:05:29.936655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2255 00:05:29.937406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2257 00:05:30.023688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2258 00:05:30.024485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2260 00:05:30.115434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2261 00:05:30.116276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2263 00:05:30.200125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2264 00:05:30.200922 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2266 00:05:30.291102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2267 00:05:30.291848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2269 00:05:30.382545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2270 00:05:30.383444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2272 00:05:30.474597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2273 00:05:30.475416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2275 00:05:30.557136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2277 00:05:30.560166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2278 00:05:30.643882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2279 00:05:30.644755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2281 00:05:30.736629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2282 00:05:30.737377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2284 00:05:30.820638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2285 00:05:30.821365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2287 00:05:30.911295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2288 00:05:30.912059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2290 00:05:31.000952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2291 00:05:31.001704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2293 00:05:31.091659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2294 00:05:31.092472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2296 00:05:31.181361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2297 00:05:31.182102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2299 00:05:31.265772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2300 00:05:31.266502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2302 00:05:31.351499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2303 00:05:31.352259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2305 00:05:31.442764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2306 00:05:31.443707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2308 00:05:31.533963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2309 00:05:31.534619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2311 00:05:31.617625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2312 00:05:31.618471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2314 00:05:31.709684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2315 00:05:31.710432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2317 00:05:31.793795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2318 00:05:31.794523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2320 00:05:31.878769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2321 00:05:31.879494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2323 00:05:31.965296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2324 00:05:31.966047 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2326 00:05:32.058309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2327 00:05:32.059078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2329 00:05:32.149436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2330 00:05:32.150163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2332 00:05:32.239801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2333 00:05:32.240585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2335 00:05:32.331474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2336 00:05:32.332204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2338 00:05:32.422655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2339 00:05:32.423483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2341 00:05:32.514088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2342 00:05:32.514692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2344 00:05:32.598857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2345 00:05:32.599717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2347 00:05:32.690751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2348 00:05:32.691487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2350 00:05:32.779661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2351 00:05:32.780449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2353 00:05:32.869229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2354 00:05:32.869961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2356 00:05:32.960889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2357 00:05:32.961632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2359 00:05:33.052218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2360 00:05:33.052988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2362 00:05:33.144927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2363 00:05:33.145662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2365 00:05:33.230292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2366 00:05:33.231067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2368 00:05:33.317966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2369 00:05:33.318442 + set +x
2370 00:05:33.319085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2372 00:05:33.327535 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 968538_1.6.2.4.5>
2373 00:05:33.328024 <LAVA_TEST_RUNNER EXIT>
2374 00:05:33.328664 Received signal: <ENDRUN> 1_kselftest-dt 968538_1.6.2.4.5
2375 00:05:33.329097 Ending use of test pattern.
2376 00:05:33.329490 Ending test lava.1_kselftest-dt (968538_1.6.2.4.5), duration 82.79
2378 00:05:33.330966 ok: lava_test_shell seems to have completed
2379 00:05:33.343539 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2380 00:05:33.345420 end: 3.1 lava-test-shell (duration 00:01:24) [common]
2381 00:05:33.345952 end: 3 lava-test-retry (duration 00:01:24) [common]
2382 00:05:33.346491 start: 4 finalize (timeout 00:05:34) [common]
2383 00:05:33.347023 start: 4.1 power-off (timeout 00:00:30) [common]
2384 00:05:33.348009 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2385 00:05:33.384126 >> OK - accepted request
2386 00:05:33.386144 Returned 0 in 0 seconds
2387 00:05:33.487325 end: 4.1 power-off (duration 00:00:00) [common]
2389 00:05:33.489100 start: 4.2 read-feedback (timeout 00:05:34) [common]
2390 00:05:33.490197 Listened to connection for namespace 'common' for up to 1s
2391 00:05:33.491061 Listened to connection for namespace 'common' for up to 1s
2392 00:05:34.491032 Finalising connection for namespace 'common'
2393 00:05:34.491787 Disconnecting from shell: Finalise
2394 00:05:34.492364 / #
2395 00:05:34.593355 end: 4.2 read-feedback (duration 00:00:01) [common]
2396 00:05:34.593848 end: 4 finalize (duration 00:00:01) [common]
2397 00:05:34.594226 Cleaning after the job
2398 00:05:34.594582 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968538/tftp-deploy-tfzyb6tt/ramdisk
2399 00:05:34.599557 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968538/tftp-deploy-tfzyb6tt/kernel
2400 00:05:34.606647 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968538/tftp-deploy-tfzyb6tt/dtb
2401 00:05:34.607849 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968538/tftp-deploy-tfzyb6tt/nfsrootfs
2402 00:05:34.753171 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968538/tftp-deploy-tfzyb6tt/modules
2403 00:05:34.762355 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/968538
2404 00:05:37.651522 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/968538
2405 00:05:37.652186 Job finished correctly