Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 23:39:06.246096 lava-dispatcher, installed at version: 2024.01
2 23:39:06.246835 start: 0 validate
3 23:39:06.247291 Start time: 2024-11-09 23:39:06.247261+00:00 (UTC)
4 23:39:06.247846 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:39:06.248402 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 23:39:06.290117 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:39:06.290694 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 23:39:07.340392 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:39:07.341049 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 23:39:21.449953 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:39:21.450475 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 23:39:23.522133 validate duration: 17.27
14 23:39:23.523585 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:39:23.524237 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:39:23.524819 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:39:23.525886 Not decompressing ramdisk as can be used compressed.
18 23:39:23.526636 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 23:39:23.527093 saving as /var/lib/lava/dispatcher/tmp/968641/tftp-deploy-qf998odv/ramdisk/rootfs.cpio.gz
20 23:39:23.527571 total size: 8181887 (7 MB)
21 23:39:23.574237 progress 0 % (0 MB)
22 23:39:23.586088 progress 5 % (0 MB)
23 23:39:23.596202 progress 10 % (0 MB)
24 23:39:23.607777 progress 15 % (1 MB)
25 23:39:23.614504 progress 20 % (1 MB)
26 23:39:23.620097 progress 25 % (1 MB)
27 23:39:23.625252 progress 30 % (2 MB)
28 23:39:23.630821 progress 35 % (2 MB)
29 23:39:23.635927 progress 40 % (3 MB)
30 23:39:23.641439 progress 45 % (3 MB)
31 23:39:23.646593 progress 50 % (3 MB)
32 23:39:23.652106 progress 55 % (4 MB)
33 23:39:23.657313 progress 60 % (4 MB)
34 23:39:23.662847 progress 65 % (5 MB)
35 23:39:23.668018 progress 70 % (5 MB)
36 23:39:23.673516 progress 75 % (5 MB)
37 23:39:23.678646 progress 80 % (6 MB)
38 23:39:23.684179 progress 85 % (6 MB)
39 23:39:23.689050 progress 90 % (7 MB)
40 23:39:23.694170 progress 95 % (7 MB)
41 23:39:23.698926 progress 100 % (7 MB)
42 23:39:23.699604 7 MB downloaded in 0.17 s (45.36 MB/s)
43 23:39:23.700208 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:39:23.701142 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:39:23.701442 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:39:23.701718 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:39:23.702212 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig+debug/gcc-12/kernel/Image
49 23:39:23.702477 saving as /var/lib/lava/dispatcher/tmp/968641/tftp-deploy-qf998odv/kernel/Image
50 23:39:23.702687 total size: 169937408 (162 MB)
51 23:39:23.702901 No compression specified
52 23:39:23.750495 progress 0 % (0 MB)
53 23:39:23.852968 progress 5 % (8 MB)
54 23:39:23.952352 progress 10 % (16 MB)
55 23:39:24.051689 progress 15 % (24 MB)
56 23:39:24.152728 progress 20 % (32 MB)
57 23:39:24.252788 progress 25 % (40 MB)
58 23:39:24.352690 progress 30 % (48 MB)
59 23:39:24.452251 progress 35 % (56 MB)
60 23:39:24.550535 progress 40 % (64 MB)
61 23:39:24.650775 progress 45 % (72 MB)
62 23:39:24.750494 progress 50 % (81 MB)
63 23:39:24.849778 progress 55 % (89 MB)
64 23:39:24.950408 progress 60 % (97 MB)
65 23:39:25.051354 progress 65 % (105 MB)
66 23:39:25.152185 progress 70 % (113 MB)
67 23:39:25.260501 progress 75 % (121 MB)
68 23:39:25.360424 progress 80 % (129 MB)
69 23:39:25.462336 progress 85 % (137 MB)
70 23:39:25.564604 progress 90 % (145 MB)
71 23:39:25.665774 progress 95 % (153 MB)
72 23:39:25.767639 progress 100 % (162 MB)
73 23:39:25.768271 162 MB downloaded in 2.07 s (78.46 MB/s)
74 23:39:25.768782 end: 1.2.1 http-download (duration 00:00:02) [common]
76 23:39:25.769619 end: 1.2 download-retry (duration 00:00:02) [common]
77 23:39:25.769902 start: 1.3 download-retry (timeout 00:09:58) [common]
78 23:39:25.770172 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 23:39:25.770680 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 23:39:25.770982 saving as /var/lib/lava/dispatcher/tmp/968641/tftp-deploy-qf998odv/dtb/meson-g12b-a311d-libretech-cc.dtb
81 23:39:25.771193 total size: 54703 (0 MB)
82 23:39:25.771406 No compression specified
83 23:39:25.809463 progress 59 % (0 MB)
84 23:39:25.810315 progress 100 % (0 MB)
85 23:39:25.810861 0 MB downloaded in 0.04 s (1.32 MB/s)
86 23:39:25.811327 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:39:25.812182 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:39:25.812447 start: 1.4 download-retry (timeout 00:09:58) [common]
90 23:39:25.812708 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 23:39:25.813185 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 23:39:25.813429 saving as /var/lib/lava/dispatcher/tmp/968641/tftp-deploy-qf998odv/modules/modules.tar
93 23:39:25.813635 total size: 27648112 (26 MB)
94 23:39:25.813845 Using unxz to decompress xz
95 23:39:25.861968 progress 0 % (0 MB)
96 23:39:26.059919 progress 5 % (1 MB)
97 23:39:26.259105 progress 10 % (2 MB)
98 23:39:26.487826 progress 15 % (3 MB)
99 23:39:26.724205 progress 20 % (5 MB)
100 23:39:26.925570 progress 25 % (6 MB)
101 23:39:27.132335 progress 30 % (7 MB)
102 23:39:27.335355 progress 35 % (9 MB)
103 23:39:27.529943 progress 40 % (10 MB)
104 23:39:27.722235 progress 45 % (11 MB)
105 23:39:27.938300 progress 50 % (13 MB)
106 23:39:28.144720 progress 55 % (14 MB)
107 23:39:28.359527 progress 60 % (15 MB)
108 23:39:28.563628 progress 65 % (17 MB)
109 23:39:28.765608 progress 70 % (18 MB)
110 23:39:28.978261 progress 75 % (19 MB)
111 23:39:29.185969 progress 80 % (21 MB)
112 23:39:29.394025 progress 85 % (22 MB)
113 23:39:29.601249 progress 90 % (23 MB)
114 23:39:29.799345 progress 95 % (25 MB)
115 23:39:29.998938 progress 100 % (26 MB)
116 23:39:30.013601 26 MB downloaded in 4.20 s (6.28 MB/s)
117 23:39:30.014218 end: 1.4.1 http-download (duration 00:00:04) [common]
119 23:39:30.015063 end: 1.4 download-retry (duration 00:00:04) [common]
120 23:39:30.015334 start: 1.5 prepare-tftp-overlay (timeout 00:09:54) [common]
121 23:39:30.015602 start: 1.5.1 extract-nfsrootfs (timeout 00:09:54) [common]
122 23:39:30.015854 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:39:30.016281 start: 1.5.2 lava-overlay (timeout 00:09:54) [common]
124 23:39:30.017472 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut
125 23:39:30.018367 makedir: /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin
126 23:39:30.019017 makedir: /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/tests
127 23:39:30.019639 makedir: /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/results
128 23:39:30.020291 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-add-keys
129 23:39:30.021266 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-add-sources
130 23:39:30.022217 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-background-process-start
131 23:39:30.023181 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-background-process-stop
132 23:39:30.024217 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-common-functions
133 23:39:30.025181 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-echo-ipv4
134 23:39:30.026099 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-install-packages
135 23:39:30.026997 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-installed-packages
136 23:39:30.027892 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-os-build
137 23:39:30.028951 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-probe-channel
138 23:39:30.029885 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-probe-ip
139 23:39:30.030793 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-target-ip
140 23:39:30.031698 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-target-mac
141 23:39:30.032656 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-target-storage
142 23:39:30.033582 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-test-case
143 23:39:30.034488 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-test-event
144 23:39:30.035379 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-test-feedback
145 23:39:30.036305 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-test-raise
146 23:39:30.037212 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-test-reference
147 23:39:30.038107 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-test-runner
148 23:39:30.039009 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-test-set
149 23:39:30.039958 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-test-shell
150 23:39:30.040924 Updating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-install-packages (oe)
151 23:39:30.041915 Updating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/bin/lava-installed-packages (oe)
152 23:39:30.042739 Creating /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/environment
153 23:39:30.043492 LAVA metadata
154 23:39:30.044021 - LAVA_JOB_ID=968641
155 23:39:30.044461 - LAVA_DISPATCHER_IP=192.168.6.2
156 23:39:30.045128 start: 1.5.2.1 ssh-authorize (timeout 00:09:53) [common]
157 23:39:30.046922 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 23:39:30.047521 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:53) [common]
159 23:39:30.047936 skipped lava-vland-overlay
160 23:39:30.048460 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 23:39:30.048992 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:53) [common]
162 23:39:30.049418 skipped lava-multinode-overlay
163 23:39:30.049896 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 23:39:30.050392 start: 1.5.2.4 test-definition (timeout 00:09:53) [common]
165 23:39:30.050865 Loading test definitions
166 23:39:30.051405 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:53) [common]
167 23:39:30.051840 Using /lava-968641 at stage 0
168 23:39:30.054154 uuid=968641_1.5.2.4.1 testdef=None
169 23:39:30.054734 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 23:39:30.055250 start: 1.5.2.4.2 test-overlay (timeout 00:09:53) [common]
171 23:39:30.058666 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 23:39:30.060256 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:53) [common]
174 23:39:30.064657 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 23:39:30.066263 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:53) [common]
177 23:39:30.070467 runner path: /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/0/tests/0_dmesg test_uuid 968641_1.5.2.4.1
178 23:39:30.071460 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 23:39:30.073004 Creating lava-test-runner.conf files
181 23:39:30.073409 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/968641/lava-overlay-oquqagut/lava-968641/0 for stage 0
182 23:39:30.074135 - 0_dmesg
183 23:39:30.074805 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 23:39:30.075345 start: 1.5.2.5 compress-overlay (timeout 00:09:53) [common]
185 23:39:30.099532 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 23:39:30.099951 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:53) [common]
187 23:39:30.100253 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 23:39:30.100527 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 23:39:30.100796 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
190 23:39:31.037082 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 23:39:31.037561 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
192 23:39:31.037828 extracting modules file /var/lib/lava/dispatcher/tmp/968641/tftp-deploy-qf998odv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/968641/extract-overlay-ramdisk-zwnailbv/ramdisk
193 23:39:32.731942 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 23:39:32.732437 start: 1.5.5 apply-overlay-tftp (timeout 00:09:51) [common]
195 23:39:32.732735 [common] Applying overlay /var/lib/lava/dispatcher/tmp/968641/compress-overlay-juxx9zvl/overlay-1.5.2.5.tar.gz to ramdisk
196 23:39:32.732977 [common] Applying overlay /var/lib/lava/dispatcher/tmp/968641/compress-overlay-juxx9zvl/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/968641/extract-overlay-ramdisk-zwnailbv/ramdisk
197 23:39:32.763040 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 23:39:32.763432 start: 1.5.6 prepare-kernel (timeout 00:09:51) [common]
199 23:39:32.763703 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:51) [common]
200 23:39:32.763930 Converting downloaded kernel to a uImage
201 23:39:32.764272 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/968641/tftp-deploy-qf998odv/kernel/Image /var/lib/lava/dispatcher/tmp/968641/tftp-deploy-qf998odv/kernel/uImage
202 23:39:34.480263 output: Image Name:
203 23:39:34.480690 output: Created: Sat Nov 9 23:39:32 2024
204 23:39:34.480919 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 23:39:34.481140 output: Data Size: 169937408 Bytes = 165954.50 KiB = 162.06 MiB
206 23:39:34.481353 output: Load Address: 01080000
207 23:39:34.481562 output: Entry Point: 01080000
208 23:39:34.481770 output:
209 23:39:34.482116 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 23:39:34.482397 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 23:39:34.482681 start: 1.5.7 configure-preseed-file (timeout 00:09:49) [common]
212 23:39:34.482944 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 23:39:34.483212 start: 1.5.8 compress-ramdisk (timeout 00:09:49) [common]
214 23:39:34.483497 Building ramdisk /var/lib/lava/dispatcher/tmp/968641/extract-overlay-ramdisk-zwnailbv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/968641/extract-overlay-ramdisk-zwnailbv/ramdisk
215 23:39:39.975295 >> 441555 blocks
216 23:39:58.291042 Adding RAMdisk u-boot header.
217 23:39:58.291764 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/968641/extract-overlay-ramdisk-zwnailbv/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/968641/extract-overlay-ramdisk-zwnailbv/ramdisk.cpio.gz.uboot
218 23:39:58.844376 output: Image Name:
219 23:39:58.844792 output: Created: Sat Nov 9 23:39:58 2024
220 23:39:58.845001 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 23:39:58.845205 output: Data Size: 53579942 Bytes = 52324.16 KiB = 51.10 MiB
222 23:39:58.845406 output: Load Address: 00000000
223 23:39:58.845606 output: Entry Point: 00000000
224 23:39:58.845804 output:
225 23:39:58.846401 rename /var/lib/lava/dispatcher/tmp/968641/extract-overlay-ramdisk-zwnailbv/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/968641/tftp-deploy-qf998odv/ramdisk/ramdisk.cpio.gz.uboot
226 23:39:58.846817 end: 1.5.8 compress-ramdisk (duration 00:00:24) [common]
227 23:39:58.847107 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
228 23:39:58.847380 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:25) [common]
229 23:39:58.847623 No LXC device requested
230 23:39:58.847878 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 23:39:58.848356 start: 1.7 deploy-device-env (timeout 00:09:25) [common]
232 23:39:58.848863 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 23:39:58.849290 Checking files for TFTP limit of 4294967296 bytes.
234 23:39:58.851925 end: 1 tftp-deploy (duration 00:00:35) [common]
235 23:39:58.852536 start: 2 uboot-action (timeout 00:05:00) [common]
236 23:39:58.853064 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 23:39:58.853559 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 23:39:58.854058 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 23:39:58.854582 Using kernel file from prepare-kernel: 968641/tftp-deploy-qf998odv/kernel/uImage
240 23:39:58.855179 substitutions:
241 23:39:58.855583 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 23:39:58.856008 - {DTB_ADDR}: 0x01070000
243 23:39:58.856415 - {DTB}: 968641/tftp-deploy-qf998odv/dtb/meson-g12b-a311d-libretech-cc.dtb
244 23:39:58.856816 - {INITRD}: 968641/tftp-deploy-qf998odv/ramdisk/ramdisk.cpio.gz.uboot
245 23:39:58.857212 - {KERNEL_ADDR}: 0x01080000
246 23:39:58.857604 - {KERNEL}: 968641/tftp-deploy-qf998odv/kernel/uImage
247 23:39:58.857998 - {LAVA_MAC}: None
248 23:39:58.858428 - {PRESEED_CONFIG}: None
249 23:39:58.858820 - {PRESEED_LOCAL}: None
250 23:39:58.859211 - {RAMDISK_ADDR}: 0x08000000
251 23:39:58.859598 - {RAMDISK}: 968641/tftp-deploy-qf998odv/ramdisk/ramdisk.cpio.gz.uboot
252 23:39:58.860009 - {ROOT_PART}: None
253 23:39:58.860404 - {ROOT}: None
254 23:39:58.860792 - {SERVER_IP}: 192.168.6.2
255 23:39:58.861183 - {TEE_ADDR}: 0x83000000
256 23:39:58.861573 - {TEE}: None
257 23:39:58.861963 Parsed boot commands:
258 23:39:58.862343 - setenv autoload no
259 23:39:58.862731 - setenv initrd_high 0xffffffff
260 23:39:58.863117 - setenv fdt_high 0xffffffff
261 23:39:58.863501 - dhcp
262 23:39:58.863888 - setenv serverip 192.168.6.2
263 23:39:58.864297 - tftpboot 0x01080000 968641/tftp-deploy-qf998odv/kernel/uImage
264 23:39:58.864688 - tftpboot 0x08000000 968641/tftp-deploy-qf998odv/ramdisk/ramdisk.cpio.gz.uboot
265 23:39:58.865078 - tftpboot 0x01070000 968641/tftp-deploy-qf998odv/dtb/meson-g12b-a311d-libretech-cc.dtb
266 23:39:58.865463 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 23:39:58.865855 - bootm 0x01080000 0x08000000 0x01070000
268 23:39:58.866348 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 23:39:58.867885 start: 2.3 connect-device (timeout 00:05:00) [common]
271 23:39:58.868371 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 23:39:58.883558 Setting prompt string to ['lava-test: # ']
273 23:39:58.885091 end: 2.3 connect-device (duration 00:00:00) [common]
274 23:39:58.885687 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 23:39:58.886232 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 23:39:58.886760 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 23:39:58.888114 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 23:39:58.923838 >> OK - accepted request
279 23:39:58.926119 Returned 0 in 0 seconds
280 23:39:59.027307 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 23:39:59.029087 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 23:39:59.029653 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 23:39:59.030160 Setting prompt string to ['Hit any key to stop autoboot']
285 23:39:59.030614 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 23:39:59.032210 Trying 192.168.56.21...
287 23:39:59.032704 Connected to conserv1.
288 23:39:59.033123 Escape character is '^]'.
289 23:39:59.033540
290 23:39:59.033960 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 23:39:59.034386
292 23:40:10.911650 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 23:40:10.912340 bl2_stage_init 0x01
294 23:40:10.912762 bl2_stage_init 0x81
295 23:40:10.917177 hw id: 0x0000 - pwm id 0x01
296 23:40:10.917648 bl2_stage_init 0xc1
297 23:40:10.918068 bl2_stage_init 0x02
298 23:40:10.918457
299 23:40:10.922734 L0:00000000
300 23:40:10.923182 L1:20000703
301 23:40:10.923577 L2:00008067
302 23:40:10.923962 L3:14000000
303 23:40:10.925718 B2:00402000
304 23:40:10.926151 B1:e0f83180
305 23:40:10.926540
306 23:40:10.926927 TE: 58124
307 23:40:10.927313
308 23:40:10.936886 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 23:40:10.937333
310 23:40:10.937727 Board ID = 1
311 23:40:10.938115 Set A53 clk to 24M
312 23:40:10.938500 Set A73 clk to 24M
313 23:40:10.942510 Set clk81 to 24M
314 23:40:10.942938 A53 clk: 1200 MHz
315 23:40:10.943325 A73 clk: 1200 MHz
316 23:40:10.948103 CLK81: 166.6M
317 23:40:10.948549 smccc: 00012a92
318 23:40:10.953636 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 23:40:10.954074 board id: 1
320 23:40:10.962238 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 23:40:10.972879 fw parse done
322 23:40:10.978912 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 23:40:11.021388 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 23:40:11.032322 PIEI prepare done
325 23:40:11.032767 fastboot data load
326 23:40:11.033160 fastboot data verify
327 23:40:11.037987 verify result: 266
328 23:40:11.043584 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 23:40:11.044074 LPDDR4 probe
330 23:40:11.044468 ddr clk to 1584MHz
331 23:40:11.051571 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 23:40:11.088839
333 23:40:11.089335 dmc_version 0001
334 23:40:11.095510 Check phy result
335 23:40:11.101411 INFO : End of CA training
336 23:40:11.101876 INFO : End of initialization
337 23:40:11.106937 INFO : Training has run successfully!
338 23:40:11.107387 Check phy result
339 23:40:11.112530 INFO : End of initialization
340 23:40:11.112986 INFO : End of read enable training
341 23:40:11.115838 INFO : End of fine write leveling
342 23:40:11.121409 INFO : End of Write leveling coarse delay
343 23:40:11.127001 INFO : Training has run successfully!
344 23:40:11.127452 Check phy result
345 23:40:11.127848 INFO : End of initialization
346 23:40:11.132594 INFO : End of read dq deskew training
347 23:40:11.138193 INFO : End of MPR read delay center optimization
348 23:40:11.138656 INFO : End of write delay center optimization
349 23:40:11.143782 INFO : End of read delay center optimization
350 23:40:11.149522 INFO : End of max read latency training
351 23:40:11.149988 INFO : Training has run successfully!
352 23:40:11.155003 1D training succeed
353 23:40:11.161069 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 23:40:11.208552 Check phy result
355 23:40:11.209031 INFO : End of initialization
356 23:40:11.231127 INFO : End of 2D read delay Voltage center optimization
357 23:40:11.251333 INFO : End of 2D read delay Voltage center optimization
358 23:40:11.303416 INFO : End of 2D write delay Voltage center optimization
359 23:40:11.352857 INFO : End of 2D write delay Voltage center optimization
360 23:40:11.358300 INFO : Training has run successfully!
361 23:40:11.358774
362 23:40:11.359171 channel==0
363 23:40:11.364048 RxClkDly_Margin_A0==88 ps 9
364 23:40:11.364515 TxDqDly_Margin_A0==98 ps 10
365 23:40:11.369566 RxClkDly_Margin_A1==88 ps 9
366 23:40:11.370019 TxDqDly_Margin_A1==88 ps 9
367 23:40:11.370417 TrainedVREFDQ_A0==74
368 23:40:11.375206 TrainedVREFDQ_A1==74
369 23:40:11.375666 VrefDac_Margin_A0==24
370 23:40:11.376093 DeviceVref_Margin_A0==40
371 23:40:11.380775 VrefDac_Margin_A1==24
372 23:40:11.381234 DeviceVref_Margin_A1==40
373 23:40:11.381631
374 23:40:11.382019
375 23:40:11.382407 channel==1
376 23:40:11.386318 RxClkDly_Margin_A0==98 ps 10
377 23:40:11.386776 TxDqDly_Margin_A0==98 ps 10
378 23:40:11.391952 RxClkDly_Margin_A1==88 ps 9
379 23:40:11.392437 TxDqDly_Margin_A1==88 ps 9
380 23:40:11.397571 TrainedVREFDQ_A0==77
381 23:40:11.398022 TrainedVREFDQ_A1==77
382 23:40:11.398415 VrefDac_Margin_A0==22
383 23:40:11.403216 DeviceVref_Margin_A0==37
384 23:40:11.403680 VrefDac_Margin_A1==24
385 23:40:11.408823 DeviceVref_Margin_A1==37
386 23:40:11.409304
387 23:40:11.409716 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 23:40:11.410118
389 23:40:11.442376 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 23:40:11.443065 2D training succeed
391 23:40:11.448091 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 23:40:11.453418 auto size-- 65535DDR cs0 size: 2048MB
393 23:40:11.453965 DDR cs1 size: 2048MB
394 23:40:11.459062 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 23:40:11.459574 cs0 DataBus test pass
396 23:40:11.464632 cs1 DataBus test pass
397 23:40:11.465143 cs0 AddrBus test pass
398 23:40:11.465605 cs1 AddrBus test pass
399 23:40:11.466058
400 23:40:11.470220 100bdlr_step_size ps== 420
401 23:40:11.470742 result report
402 23:40:11.475815 boot times 0Enable ddr reg access
403 23:40:11.481103 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 23:40:11.494636 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 23:40:12.068301 0.0;M3 CHK:0;cm4_sp_mode 0
406 23:40:12.068933 MVN_1=0x00000000
407 23:40:12.073680 MVN_2=0x00000000
408 23:40:12.079530 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 23:40:12.080146 OPS=0x10
410 23:40:12.080657 ring efuse init
411 23:40:12.081236 chipver efuse init
412 23:40:12.085053 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 23:40:12.090645 [0.018961 Inits done]
414 23:40:12.091117 secure task start!
415 23:40:12.091531 high task start!
416 23:40:12.095200 low task start!
417 23:40:12.095657 run into bl31
418 23:40:12.101903 NOTICE: BL31: v1.3(release):4fc40b1
419 23:40:12.109689 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 23:40:12.110175 NOTICE: BL31: G12A normal boot!
421 23:40:12.135206 NOTICE: BL31: BL33 decompress pass
422 23:40:12.140816 ERROR: Error initializing runtime service opteed_fast
423 23:40:13.373700
424 23:40:13.374308
425 23:40:13.382068 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 23:40:13.382553
427 23:40:13.382971 Model: Libre Computer AML-A311D-CC Alta
428 23:40:13.590580 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 23:40:13.613917 DRAM: 2 GiB (effective 3.8 GiB)
430 23:40:13.756904 Core: 408 devices, 31 uclasses, devicetree: separate
431 23:40:13.761791 WDT: Not starting watchdog@f0d0
432 23:40:13.795015 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 23:40:13.807419 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 23:40:13.811626 ** Bad device specification mmc 0 **
435 23:40:13.822795 Card did not respond to voltage select! : -110
436 23:40:13.829527 ** Bad device specification mmc 0 **
437 23:40:13.830080 Couldn't find partition mmc 0
438 23:40:13.838770 Card did not respond to voltage select! : -110
439 23:40:13.844293 ** Bad device specification mmc 0 **
440 23:40:13.844822 Couldn't find partition mmc 0
441 23:40:13.848368 Error: could not access storage.
442 23:40:15.112101 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 23:40:15.112712 bl2_stage_init 0x01
444 23:40:15.113144 bl2_stage_init 0x81
445 23:40:15.117434 hw id: 0x0000 - pwm id 0x01
446 23:40:15.117880 bl2_stage_init 0xc1
447 23:40:15.118289 bl2_stage_init 0x02
448 23:40:15.118693
449 23:40:15.123017 L0:00000000
450 23:40:15.123465 L1:20000703
451 23:40:15.123872 L2:00008067
452 23:40:15.124314 L3:14000000
453 23:40:15.128595 B2:00402000
454 23:40:15.129029 B1:e0f83180
455 23:40:15.129431
456 23:40:15.129834 TE: 58150
457 23:40:15.130237
458 23:40:15.134221 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 23:40:15.134662
460 23:40:15.135067 Board ID = 1
461 23:40:15.139831 Set A53 clk to 24M
462 23:40:15.140327 Set A73 clk to 24M
463 23:40:15.140738 Set clk81 to 24M
464 23:40:15.145411 A53 clk: 1200 MHz
465 23:40:15.145847 A73 clk: 1200 MHz
466 23:40:15.146252 CLK81: 166.6M
467 23:40:15.146645 smccc: 00012aac
468 23:40:15.151033 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 23:40:15.156595 board id: 1
470 23:40:15.162481 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 23:40:15.173136 fw parse done
472 23:40:15.179150 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 23:40:15.221869 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 23:40:15.232638 PIEI prepare done
475 23:40:15.233106 fastboot data load
476 23:40:15.233531 fastboot data verify
477 23:40:15.238294 verify result: 266
478 23:40:15.243885 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 23:40:15.244381 LPDDR4 probe
480 23:40:15.244793 ddr clk to 1584MHz
481 23:40:15.251944 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 23:40:15.288340
483 23:40:15.288902 dmc_version 0001
484 23:40:15.295933 Check phy result
485 23:40:15.301650 INFO : End of CA training
486 23:40:15.302129 INFO : End of initialization
487 23:40:15.307266 INFO : Training has run successfully!
488 23:40:15.307585 Check phy result
489 23:40:15.312929 INFO : End of initialization
490 23:40:15.313239 INFO : End of read enable training
491 23:40:15.318495 INFO : End of fine write leveling
492 23:40:15.324212 INFO : End of Write leveling coarse delay
493 23:40:15.324802 INFO : Training has run successfully!
494 23:40:15.325335 Check phy result
495 23:40:15.329720 INFO : End of initialization
496 23:40:15.330266 INFO : End of read dq deskew training
497 23:40:15.335301 INFO : End of MPR read delay center optimization
498 23:40:15.340927 INFO : End of write delay center optimization
499 23:40:15.346509 INFO : End of read delay center optimization
500 23:40:15.347065 INFO : End of max read latency training
501 23:40:15.352108 INFO : Training has run successfully!
502 23:40:15.352674 1D training succeed
503 23:40:15.361314 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 23:40:15.412162 Check phy result
505 23:40:15.412810 INFO : End of initialization
506 23:40:15.432368 INFO : End of 2D read delay Voltage center optimization
507 23:40:15.451164 INFO : End of 2D read delay Voltage center optimization
508 23:40:15.504842 INFO : End of 2D write delay Voltage center optimization
509 23:40:15.552495 INFO : End of 2D write delay Voltage center optimization
510 23:40:15.560348 INFO : Training has run successfully!
511 23:40:15.560927
512 23:40:15.561369 channel==0
513 23:40:15.563726 RxClkDly_Margin_A0==88 ps 9
514 23:40:15.564307 TxDqDly_Margin_A0==98 ps 10
515 23:40:15.569263 RxClkDly_Margin_A1==88 ps 9
516 23:40:15.569821 TxDqDly_Margin_A1==98 ps 10
517 23:40:15.570262 TrainedVREFDQ_A0==74
518 23:40:15.574946 TrainedVREFDQ_A1==74
519 23:40:15.575518 VrefDac_Margin_A0==25
520 23:40:15.575957 DeviceVref_Margin_A0==40
521 23:40:15.580461 VrefDac_Margin_A1==24
522 23:40:15.581014 DeviceVref_Margin_A1==40
523 23:40:15.581422
524 23:40:15.581813
525 23:40:15.586051 channel==1
526 23:40:15.586583 RxClkDly_Margin_A0==98 ps 10
527 23:40:15.586981 TxDqDly_Margin_A0==98 ps 10
528 23:40:15.591628 RxClkDly_Margin_A1==98 ps 10
529 23:40:15.592264 TxDqDly_Margin_A1==88 ps 9
530 23:40:15.597206 TrainedVREFDQ_A0==77
531 23:40:15.597794 TrainedVREFDQ_A1==77
532 23:40:15.598238 VrefDac_Margin_A0==22
533 23:40:15.602819 DeviceVref_Margin_A0==37
534 23:40:15.603367 VrefDac_Margin_A1==24
535 23:40:15.608470 DeviceVref_Margin_A1==37
536 23:40:15.609032
537 23:40:15.609457 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 23:40:15.614200
539 23:40:15.642090 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000016 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
540 23:40:15.642693 2D training succeed
541 23:40:15.647608 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 23:40:15.653204 auto size-- 65535DDR cs0 size: 2048MB
543 23:40:15.653740 DDR cs1 size: 2048MB
544 23:40:15.658778 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 23:40:15.659299 cs0 DataBus test pass
546 23:40:15.664423 cs1 DataBus test pass
547 23:40:15.664940 cs0 AddrBus test pass
548 23:40:15.665341 cs1 AddrBus test pass
549 23:40:15.665751
550 23:40:15.670103 100bdlr_step_size ps== 420
551 23:40:15.670627 result report
552 23:40:15.675625 boot times 0Enable ddr reg access
553 23:40:15.681166 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 23:40:15.695122 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 23:40:16.268122 0.0;M3 CHK:0;cm4_sp_mode 0
556 23:40:16.268822 MVN_1=0x00000000
557 23:40:16.273592 MVN_2=0x00000000
558 23:40:16.279298 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 23:40:16.279628 OPS=0x10
560 23:40:16.279869 ring efuse init
561 23:40:16.280240 chipver efuse init
562 23:40:16.285024 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 23:40:16.290505 [0.018961 Inits done]
564 23:40:16.290832 secure task start!
565 23:40:16.291073 high task start!
566 23:40:16.295085 low task start!
567 23:40:16.295462 run into bl31
568 23:40:16.301709 NOTICE: BL31: v1.3(release):4fc40b1
569 23:40:16.309516 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 23:40:16.309955 NOTICE: BL31: G12A normal boot!
571 23:40:16.334856 NOTICE: BL31: BL33 decompress pass
572 23:40:16.340642 ERROR: Error initializing runtime service opteed_fast
573 23:40:17.573628
574 23:40:17.574263
575 23:40:17.581998 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 23:40:17.582516
577 23:40:17.582937 Model: Libre Computer AML-A311D-CC Alta
578 23:40:17.790452 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 23:40:17.813802 DRAM: 2 GiB (effective 3.8 GiB)
580 23:40:17.956774 Core: 408 devices, 31 uclasses, devicetree: separate
581 23:40:17.962655 WDT: Not starting watchdog@f0d0
582 23:40:17.994813 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 23:40:18.007500 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 23:40:18.011441 ** Bad device specification mmc 0 **
585 23:40:18.022680 Card did not respond to voltage select! : -110
586 23:40:18.030276 ** Bad device specification mmc 0 **
587 23:40:18.030782 Couldn't find partition mmc 0
588 23:40:18.038605 Card did not respond to voltage select! : -110
589 23:40:18.044187 ** Bad device specification mmc 0 **
590 23:40:18.044664 Couldn't find partition mmc 0
591 23:40:18.049249 Error: could not access storage.
592 23:40:18.391818 Net: eth0: ethernet@ff3f0000
593 23:40:18.392478 starting USB...
594 23:40:18.643630 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 23:40:18.644290 Starting the controller
596 23:40:18.650572 USB XHCI 1.10
597 23:40:20.362101 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 23:40:20.362738 bl2_stage_init 0x01
599 23:40:20.363166 bl2_stage_init 0x81
600 23:40:20.367713 hw id: 0x0000 - pwm id 0x01
601 23:40:20.368197 bl2_stage_init 0xc1
602 23:40:20.368612 bl2_stage_init 0x02
603 23:40:20.369016
604 23:40:20.373404 L0:00000000
605 23:40:20.373854 L1:20000703
606 23:40:20.374261 L2:00008067
607 23:40:20.374659 L3:14000000
608 23:40:20.379046 B2:00402000
609 23:40:20.379491 B1:e0f83180
610 23:40:20.379892
611 23:40:20.380333 TE: 58124
612 23:40:20.380737
613 23:40:20.384633 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 23:40:20.385075
615 23:40:20.385482 Board ID = 1
616 23:40:20.390161 Set A53 clk to 24M
617 23:40:20.390596 Set A73 clk to 24M
618 23:40:20.390996 Set clk81 to 24M
619 23:40:20.395703 A53 clk: 1200 MHz
620 23:40:20.396165 A73 clk: 1200 MHz
621 23:40:20.396567 CLK81: 166.6M
622 23:40:20.396959 smccc: 00012a92
623 23:40:20.401415 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 23:40:20.406855 board id: 1
625 23:40:20.413012 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 23:40:20.423379 fw parse done
627 23:40:20.429352 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 23:40:20.472001 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 23:40:20.482893 PIEI prepare done
630 23:40:20.483361 fastboot data load
631 23:40:20.483774 fastboot data verify
632 23:40:20.488512 verify result: 266
633 23:40:20.494076 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 23:40:20.494511 LPDDR4 probe
635 23:40:20.494913 ddr clk to 1584MHz
636 23:40:20.502061 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 23:40:20.539423
638 23:40:20.539961 dmc_version 0001
639 23:40:20.546065 Check phy result
640 23:40:20.551960 INFO : End of CA training
641 23:40:20.552437 INFO : End of initialization
642 23:40:20.557513 INFO : Training has run successfully!
643 23:40:20.557958 Check phy result
644 23:40:20.563136 INFO : End of initialization
645 23:40:20.563573 INFO : End of read enable training
646 23:40:20.568682 INFO : End of fine write leveling
647 23:40:20.574308 INFO : End of Write leveling coarse delay
648 23:40:20.574747 INFO : Training has run successfully!
649 23:40:20.575145 Check phy result
650 23:40:20.579946 INFO : End of initialization
651 23:40:20.580416 INFO : End of read dq deskew training
652 23:40:20.585662 INFO : End of MPR read delay center optimization
653 23:40:20.591119 INFO : End of write delay center optimization
654 23:40:20.596675 INFO : End of read delay center optimization
655 23:40:20.597123 INFO : End of max read latency training
656 23:40:20.602328 INFO : Training has run successfully!
657 23:40:20.602800 1D training succeed
658 23:40:20.611519 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 23:40:20.658995 Check phy result
660 23:40:20.659513 INFO : End of initialization
661 23:40:20.680737 INFO : End of 2D read delay Voltage center optimization
662 23:40:20.701065 INFO : End of 2D read delay Voltage center optimization
663 23:40:20.752044 INFO : End of 2D write delay Voltage center optimization
664 23:40:20.802478 INFO : End of 2D write delay Voltage center optimization
665 23:40:20.807915 INFO : Training has run successfully!
666 23:40:20.808394
667 23:40:20.808811 channel==0
668 23:40:20.813639 RxClkDly_Margin_A0==88 ps 9
669 23:40:20.814068 TxDqDly_Margin_A0==98 ps 10
670 23:40:20.819129 RxClkDly_Margin_A1==88 ps 9
671 23:40:20.819573 TxDqDly_Margin_A1==98 ps 10
672 23:40:20.820018 TrainedVREFDQ_A0==74
673 23:40:20.824740 TrainedVREFDQ_A1==74
674 23:40:20.825196 VrefDac_Margin_A0==25
675 23:40:20.825600 DeviceVref_Margin_A0==40
676 23:40:20.830391 VrefDac_Margin_A1==23
677 23:40:20.830820 DeviceVref_Margin_A1==40
678 23:40:20.831219
679 23:40:20.831617
680 23:40:20.835934 channel==1
681 23:40:20.836419 RxClkDly_Margin_A0==98 ps 10
682 23:40:20.836827 TxDqDly_Margin_A0==98 ps 10
683 23:40:20.841616 RxClkDly_Margin_A1==98 ps 10
684 23:40:20.842045 TxDqDly_Margin_A1==88 ps 9
685 23:40:20.847141 TrainedVREFDQ_A0==77
686 23:40:20.847581 TrainedVREFDQ_A1==77
687 23:40:20.848014 VrefDac_Margin_A0==22
688 23:40:20.852719 DeviceVref_Margin_A0==37
689 23:40:20.853146 VrefDac_Margin_A1==22
690 23:40:20.858393 DeviceVref_Margin_A1==37
691 23:40:20.858822
692 23:40:20.859236 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 23:40:20.863909
694 23:40:20.891896 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
695 23:40:20.892412 2D training succeed
696 23:40:20.897649 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 23:40:20.903133 auto size-- 65535DDR cs0 size: 2048MB
698 23:40:20.903572 DDR cs1 size: 2048MB
699 23:40:20.908715 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 23:40:20.909167 cs0 DataBus test pass
701 23:40:20.914400 cs1 DataBus test pass
702 23:40:20.914836 cs0 AddrBus test pass
703 23:40:20.915244 cs1 AddrBus test pass
704 23:40:20.915644
705 23:40:20.919925 100bdlr_step_size ps== 420
706 23:40:20.920397 result report
707 23:40:20.925526 boot times 0Enable ddr reg access
708 23:40:20.930948 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 23:40:20.944458 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 23:40:21.518257 0.0;M3 CHK:0;cm4_sp_mode 0
711 23:40:21.518939 MVN_1=0x00000000
712 23:40:21.523818 MVN_2=0x00000000
713 23:40:21.529518 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 23:40:21.530139 OPS=0x10
715 23:40:21.530545 ring efuse init
716 23:40:21.530937 chipver efuse init
717 23:40:21.534984 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 23:40:21.541307 [0.018961 Inits done]
719 23:40:21.541789 secure task start!
720 23:40:21.542189 high task start!
721 23:40:21.544451 low task start!
722 23:40:21.544909 run into bl31
723 23:40:21.551966 NOTICE: BL31: v1.3(release):4fc40b1
724 23:40:21.559819 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 23:40:21.560642 NOTICE: BL31: G12A normal boot!
726 23:40:21.585127 NOTICE: BL31: BL33 decompress pass
727 23:40:21.591040 ERROR: Error initializing runtime service opteed_fast
728 23:40:22.823691
729 23:40:22.824396
730 23:40:22.832107 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 23:40:22.832637
732 23:40:22.833072 Model: Libre Computer AML-A311D-CC Alta
733 23:40:23.040494 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 23:40:23.063770 DRAM: 2 GiB (effective 3.8 GiB)
735 23:40:23.206971 Core: 408 devices, 31 uclasses, devicetree: separate
736 23:40:23.212766 WDT: Not starting watchdog@f0d0
737 23:40:23.245157 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 23:40:23.257441 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 23:40:23.262431 ** Bad device specification mmc 0 **
740 23:40:23.272793 Card did not respond to voltage select! : -110
741 23:40:23.280348 ** Bad device specification mmc 0 **
742 23:40:23.280799 Couldn't find partition mmc 0
743 23:40:23.289544 Card did not respond to voltage select! : -110
744 23:40:23.294529 ** Bad device specification mmc 0 **
745 23:40:23.294983 Couldn't find partition mmc 0
746 23:40:23.299528 Error: could not access storage.
747 23:40:23.642925 Net: eth0: ethernet@ff3f0000
748 23:40:23.643553 starting USB...
749 23:40:23.894577 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 23:40:23.895141 Starting the controller
751 23:40:23.901926 USB XHCI 1.10
752 23:40:26.063654 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 23:40:26.064334 bl2_stage_init 0x01
754 23:40:26.064766 bl2_stage_init 0x81
755 23:40:26.069117 hw id: 0x0000 - pwm id 0x01
756 23:40:26.069655 bl2_stage_init 0xc1
757 23:40:26.070083 bl2_stage_init 0x02
758 23:40:26.070495
759 23:40:26.074741 L0:00000000
760 23:40:26.075199 L1:20000703
761 23:40:26.075607 L2:00008067
762 23:40:26.076031 L3:14000000
763 23:40:26.080198 B2:00402000
764 23:40:26.080647 B1:e0f83180
765 23:40:26.081055
766 23:40:26.081458 TE: 58124
767 23:40:26.081857
768 23:40:26.085851 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 23:40:26.086301
770 23:40:26.086707 Board ID = 1
771 23:40:26.091395 Set A53 clk to 24M
772 23:40:26.091836 Set A73 clk to 24M
773 23:40:26.092269 Set clk81 to 24M
774 23:40:26.097305 A53 clk: 1200 MHz
775 23:40:26.097748 A73 clk: 1200 MHz
776 23:40:26.098147 CLK81: 166.6M
777 23:40:26.098540 smccc: 00012a92
778 23:40:26.102758 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 23:40:26.108256 board id: 1
780 23:40:26.114232 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 23:40:26.124911 fw parse done
782 23:40:26.130886 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 23:40:26.175359 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 23:40:26.185765 PIEI prepare done
785 23:40:26.186259 fastboot data load
786 23:40:26.186677 fastboot data verify
787 23:40:26.191438 verify result: 266
788 23:40:26.196969 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 23:40:26.197446 LPDDR4 probe
790 23:40:26.197854 ddr clk to 1584MHz
791 23:40:26.204090 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 23:40:26.240819
793 23:40:26.241328 dmc_version 0001
794 23:40:26.248434 Check phy result
795 23:40:26.255811 INFO : End of CA training
796 23:40:26.256319 INFO : End of initialization
797 23:40:26.258909 INFO : Training has run successfully!
798 23:40:26.259356 Check phy result
799 23:40:26.264555 INFO : End of initialization
800 23:40:26.265021 INFO : End of read enable training
801 23:40:26.267768 INFO : End of fine write leveling
802 23:40:26.278155 INFO : End of Write leveling coarse delay
803 23:40:26.279079 INFO : Training has run successfully!
804 23:40:26.279520 Check phy result
805 23:40:26.279923 INFO : End of initialization
806 23:40:26.284549 INFO : End of read dq deskew training
807 23:40:26.293657 INFO : End of MPR read delay center optimization
808 23:40:26.294203 INFO : End of write delay center optimization
809 23:40:26.295732 INFO : End of read delay center optimization
810 23:40:26.301421 INFO : End of max read latency training
811 23:40:26.301895 INFO : Training has run successfully!
812 23:40:26.306919 1D training succeed
813 23:40:26.312821 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 23:40:26.359586 Check phy result
815 23:40:26.360290 INFO : End of initialization
816 23:40:26.381514 INFO : End of 2D read delay Voltage center optimization
817 23:40:26.405991 INFO : End of 2D read delay Voltage center optimization
818 23:40:26.454706 INFO : End of 2D write delay Voltage center optimization
819 23:40:26.504042 INFO : End of 2D write delay Voltage center optimization
820 23:40:26.509564 INFO : Training has run successfully!
821 23:40:26.510044
822 23:40:26.510469 channel==0
823 23:40:26.519367 RxClkDly_Margin_A0==88 ps 9
824 23:40:26.519904 TxDqDly_Margin_A0==98 ps 10
825 23:40:26.520760 RxClkDly_Margin_A1==88 ps 9
826 23:40:26.521252 TxDqDly_Margin_A1==98 ps 10
827 23:40:26.525251 TrainedVREFDQ_A0==74
828 23:40:26.525759 TrainedVREFDQ_A1==76
829 23:40:26.526221 VrefDac_Margin_A0==25
830 23:40:26.531520 DeviceVref_Margin_A0==40
831 23:40:26.532067 VrefDac_Margin_A1==25
832 23:40:26.536375 DeviceVref_Margin_A1==38
833 23:40:26.536829
834 23:40:26.537224
835 23:40:26.537681 channel==1
836 23:40:26.538143 RxClkDly_Margin_A0==98 ps 10
837 23:40:26.542831 TxDqDly_Margin_A0==88 ps 9
838 23:40:26.543363 RxClkDly_Margin_A1==88 ps 9
839 23:40:26.547662 TxDqDly_Margin_A1==88 ps 9
840 23:40:26.548154 TrainedVREFDQ_A0==76
841 23:40:26.548550 TrainedVREFDQ_A1==77
842 23:40:26.553441 VrefDac_Margin_A0==22
843 23:40:26.553882 DeviceVref_Margin_A0==38
844 23:40:26.559374 VrefDac_Margin_A1==24
845 23:40:26.559905 DeviceVref_Margin_A1==37
846 23:40:26.560366
847 23:40:26.565327 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 23:40:26.565845
849 23:40:26.593188 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
850 23:40:26.596704 2D training succeed
851 23:40:26.603307 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 23:40:26.603819 auto size-- 65535DDR cs0 size: 2048MB
853 23:40:26.610158 DDR cs1 size: 2048MB
854 23:40:26.610661 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 23:40:26.613513 cs0 DataBus test pass
856 23:40:26.613948 cs1 DataBus test pass
857 23:40:26.614337 cs0 AddrBus test pass
858 23:40:26.622359 cs1 AddrBus test pass
859 23:40:26.622794
860 23:40:26.623184 100bdlr_step_size ps== 420
861 23:40:26.623575 result report
862 23:40:26.624901 boot times 0Enable ddr reg access
863 23:40:26.632369 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 23:40:26.647354 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 23:40:27.218681 0.0;M3 CHK:0;cm4_sp_mode 0
866 23:40:27.219274 MVN_1=0x00000000
867 23:40:27.224290 MVN_2=0x00000000
868 23:40:27.229981 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 23:40:27.230492 OPS=0x10
870 23:40:27.230913 ring efuse init
871 23:40:27.231320 chipver efuse init
872 23:40:27.235522 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 23:40:27.241122 [0.018961 Inits done]
874 23:40:27.241570 secure task start!
875 23:40:27.241973 high task start!
876 23:40:27.245724 low task start!
877 23:40:27.246172 run into bl31
878 23:40:27.252537 NOTICE: BL31: v1.3(release):4fc40b1
879 23:40:27.260329 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 23:40:27.260858 NOTICE: BL31: G12A normal boot!
881 23:40:27.285729 NOTICE: BL31: BL33 decompress pass
882 23:40:27.291394 ERROR: Error initializing runtime service opteed_fast
883 23:40:28.524211
884 23:40:28.524909
885 23:40:28.532566 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 23:40:28.533065
887 23:40:28.533482 Model: Libre Computer AML-A311D-CC Alta
888 23:40:28.740992 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 23:40:28.764413 DRAM: 2 GiB (effective 3.8 GiB)
890 23:40:28.907344 Core: 408 devices, 31 uclasses, devicetree: separate
891 23:40:28.913193 WDT: Not starting watchdog@f0d0
892 23:40:28.945411 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 23:40:28.957986 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 23:40:28.961990 ** Bad device specification mmc 0 **
895 23:40:28.973243 Card did not respond to voltage select! : -110
896 23:40:28.980897 ** Bad device specification mmc 0 **
897 23:40:28.981339 Couldn't find partition mmc 0
898 23:40:28.989207 Card did not respond to voltage select! : -110
899 23:40:28.994744 ** Bad device specification mmc 0 **
900 23:40:28.995186 Couldn't find partition mmc 0
901 23:40:28.999819 Error: could not access storage.
902 23:40:29.342283 Net: eth0: ethernet@ff3f0000
903 23:40:29.342861 starting USB...
904 23:40:29.594102 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 23:40:29.594748 Starting the controller
906 23:40:29.601003 USB XHCI 1.10
907 23:40:31.463385 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 23:40:31.464022 bl2_stage_init 0x01
909 23:40:31.464463 bl2_stage_init 0x81
910 23:40:31.468949 hw id: 0x0000 - pwm id 0x01
911 23:40:31.469436 bl2_stage_init 0xc1
912 23:40:31.469847 bl2_stage_init 0x02
913 23:40:31.470250
914 23:40:31.474551 L0:00000000
915 23:40:31.475029 L1:20000703
916 23:40:31.475465 L2:00008067
917 23:40:31.475898 L3:14000000
918 23:40:31.480114 B2:00402000
919 23:40:31.480591 B1:e0f83180
920 23:40:31.481010
921 23:40:31.481439 TE: 58167
922 23:40:31.481859
923 23:40:31.485727 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 23:40:31.486197
925 23:40:31.486620 Board ID = 1
926 23:40:31.491340 Set A53 clk to 24M
927 23:40:31.491819 Set A73 clk to 24M
928 23:40:31.492266 Set clk81 to 24M
929 23:40:31.496922 A53 clk: 1200 MHz
930 23:40:31.497367 A73 clk: 1200 MHz
931 23:40:31.497776 CLK81: 166.6M
932 23:40:31.498183 smccc: 00012abe
933 23:40:31.502527 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 23:40:31.508148 board id: 1
935 23:40:31.514007 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 23:40:31.524678 fw parse done
937 23:40:31.530616 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 23:40:31.573334 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 23:40:31.584172 PIEI prepare done
940 23:40:31.584717 fastboot data load
941 23:40:31.585145 fastboot data verify
942 23:40:31.589980 verify result: 266
943 23:40:31.595674 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 23:40:31.596211 LPDDR4 probe
945 23:40:31.596616 ddr clk to 1584MHz
946 23:40:31.603635 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 23:40:31.640943
948 23:40:31.641492 dmc_version 0001
949 23:40:31.647811 Check phy result
950 23:40:31.653449 INFO : End of CA training
951 23:40:31.653949 INFO : End of initialization
952 23:40:31.659038 INFO : Training has run successfully!
953 23:40:31.659543 Check phy result
954 23:40:31.664670 INFO : End of initialization
955 23:40:31.665175 INFO : End of read enable training
956 23:40:31.670415 INFO : End of fine write leveling
957 23:40:31.675844 INFO : End of Write leveling coarse delay
958 23:40:31.676401 INFO : Training has run successfully!
959 23:40:31.676826 Check phy result
960 23:40:31.681385 INFO : End of initialization
961 23:40:31.681898 INFO : End of read dq deskew training
962 23:40:31.686988 INFO : End of MPR read delay center optimization
963 23:40:31.692521 INFO : End of write delay center optimization
964 23:40:31.698087 INFO : End of read delay center optimization
965 23:40:31.698598 INFO : End of max read latency training
966 23:40:31.703684 INFO : Training has run successfully!
967 23:40:31.704231 1D training succeed
968 23:40:31.712715 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 23:40:31.760425 Check phy result
970 23:40:31.760960 INFO : End of initialization
971 23:40:31.782184 INFO : End of 2D read delay Voltage center optimization
972 23:40:31.802448 INFO : End of 2D read delay Voltage center optimization
973 23:40:31.854506 INFO : End of 2D write delay Voltage center optimization
974 23:40:31.903868 INFO : End of 2D write delay Voltage center optimization
975 23:40:31.909468 INFO : Training has run successfully!
976 23:40:31.909979
977 23:40:31.910401 channel==0
978 23:40:31.915053 RxClkDly_Margin_A0==88 ps 9
979 23:40:31.915549 TxDqDly_Margin_A0==98 ps 10
980 23:40:31.920628 RxClkDly_Margin_A1==88 ps 9
981 23:40:31.921129 TxDqDly_Margin_A1==98 ps 10
982 23:40:31.921549 TrainedVREFDQ_A0==74
983 23:40:31.926296 TrainedVREFDQ_A1==74
984 23:40:31.926798 VrefDac_Margin_A0==25
985 23:40:31.927217 DeviceVref_Margin_A0==40
986 23:40:31.931867 VrefDac_Margin_A1==25
987 23:40:31.932408 DeviceVref_Margin_A1==40
988 23:40:31.932826
989 23:40:31.933236
990 23:40:31.937434 channel==1
991 23:40:31.937952 RxClkDly_Margin_A0==98 ps 10
992 23:40:31.938367 TxDqDly_Margin_A0==88 ps 9
993 23:40:31.943065 RxClkDly_Margin_A1==88 ps 9
994 23:40:31.943567 TxDqDly_Margin_A1==88 ps 9
995 23:40:31.948625 TrainedVREFDQ_A0==74
996 23:40:31.949129 TrainedVREFDQ_A1==77
997 23:40:31.949545 VrefDac_Margin_A0==22
998 23:40:31.954292 DeviceVref_Margin_A0==40
999 23:40:31.954786 VrefDac_Margin_A1==24
1000 23:40:31.959813 DeviceVref_Margin_A1==37
1001 23:40:31.960331
1002 23:40:31.960749 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 23:40:31.961154
1004 23:40:31.993386 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1005 23:40:31.993939 2D training succeed
1006 23:40:31.999033 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 23:40:32.004590 auto size-- 65535DDR cs0 size: 2048MB
1008 23:40:32.005096 DDR cs1 size: 2048MB
1009 23:40:32.010281 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 23:40:32.010772 cs0 DataBus test pass
1011 23:40:32.015852 cs1 DataBus test pass
1012 23:40:32.016392 cs0 AddrBus test pass
1013 23:40:32.016814 cs1 AddrBus test pass
1014 23:40:32.017221
1015 23:40:32.021466 100bdlr_step_size ps== 420
1016 23:40:32.021986 result report
1017 23:40:32.027062 boot times 0Enable ddr reg access
1018 23:40:32.032382 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 23:40:32.045476 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 23:40:32.619377 0.0;M3 CHK:0;cm4_sp_mode 0
1021 23:40:32.619976 MVN_1=0x00000000
1022 23:40:32.624835 MVN_2=0x00000000
1023 23:40:32.630624 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 23:40:32.631118 OPS=0x10
1025 23:40:32.631543 ring efuse init
1026 23:40:32.631952 chipver efuse init
1027 23:40:32.638778 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 23:40:32.639283 [0.018961 Inits done]
1029 23:40:32.646045 secure task start!
1030 23:40:32.646530 high task start!
1031 23:40:32.646948 low task start!
1032 23:40:32.647354 run into bl31
1033 23:40:32.653050 NOTICE: BL31: v1.3(release):4fc40b1
1034 23:40:32.660868 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 23:40:32.661360 NOTICE: BL31: G12A normal boot!
1036 23:40:32.686329 NOTICE: BL31: BL33 decompress pass
1037 23:40:32.691921 ERROR: Error initializing runtime service opteed_fast
1038 23:40:33.924723
1039 23:40:33.925351
1040 23:40:33.933178 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 23:40:33.933693
1042 23:40:33.934119 Model: Libre Computer AML-A311D-CC Alta
1043 23:40:34.141652 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 23:40:34.165022 DRAM: 2 GiB (effective 3.8 GiB)
1045 23:40:34.308031 Core: 408 devices, 31 uclasses, devicetree: separate
1046 23:40:34.313504 WDT: Not starting watchdog@f0d0
1047 23:40:34.346148 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 23:40:34.358565 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 23:40:34.363564 ** Bad device specification mmc 0 **
1050 23:40:34.373924 Card did not respond to voltage select! : -110
1051 23:40:34.380723 ** Bad device specification mmc 0 **
1052 23:40:34.381255 Couldn't find partition mmc 0
1053 23:40:34.389911 Card did not respond to voltage select! : -110
1054 23:40:34.395517 ** Bad device specification mmc 0 **
1055 23:40:34.396023 Couldn't find partition mmc 0
1056 23:40:34.400575 Error: could not access storage.
1057 23:40:34.743964 Net: eth0: ethernet@ff3f0000
1058 23:40:34.744587 starting USB...
1059 23:40:34.995802 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 23:40:34.996438 Starting the controller
1061 23:40:35.002780 USB XHCI 1.10
1062 23:40:36.556689 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 23:40:36.565083 scanning usb for storage devices... 0 Storage Device(s) found
1065 23:40:36.616668 Hit any key to stop autoboot: 1
1066 23:40:36.617621 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1067 23:40:36.618230 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1068 23:40:36.618690 Setting prompt string to ['=>']
1069 23:40:36.619160 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1070 23:40:36.632476 0
1071 23:40:36.633352 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 23:40:36.633837 Sending with 10 millisecond of delay
1074 23:40:37.768488 => setenv autoload no
1075 23:40:37.779272 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1076 23:40:37.784213 setenv autoload no
1077 23:40:37.784973 Sending with 10 millisecond of delay
1079 23:40:39.581699 => setenv initrd_high 0xffffffff
1080 23:40:39.592506 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1081 23:40:39.593393 setenv initrd_high 0xffffffff
1082 23:40:39.594100 Sending with 10 millisecond of delay
1084 23:40:41.210242 => setenv fdt_high 0xffffffff
1085 23:40:41.221036 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 23:40:41.221892 setenv fdt_high 0xffffffff
1087 23:40:41.222601 Sending with 10 millisecond of delay
1089 23:40:41.514403 => dhcp
1090 23:40:41.525161 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1091 23:40:41.525995 dhcp
1092 23:40:41.526433 Speed: 1000, full duplex
1093 23:40:41.526844 BOOTP broadcast 1
1094 23:40:41.536660 DHCP client bound to address 192.168.6.27 (12 ms)
1095 23:40:41.537423 Sending with 10 millisecond of delay
1097 23:40:43.213870 => setenv serverip 192.168.6.2
1098 23:40:43.224688 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 23:40:43.225604 setenv serverip 192.168.6.2
1100 23:40:43.226292 Sending with 10 millisecond of delay
1102 23:40:46.950460 => tftpboot 0x01080000 968641/tftp-deploy-qf998odv/kernel/uImage
1103 23:40:46.961255 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 23:40:46.962079 tftpboot 0x01080000 968641/tftp-deploy-qf998odv/kernel/uImage
1105 23:40:46.962537 Speed: 1000, full duplex
1106 23:40:46.962951 Using ethernet@ff3f0000 device
1107 23:40:46.964253 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 23:40:46.969656 Filename '968641/tftp-deploy-qf998odv/kernel/uImage'.
1109 23:40:46.973602 Load address: 0x1080000
1110 23:40:51.257635 Loading: *###################
1111 23:40:51.258215 TFTP error: trying to overwrite reserved memory...
1113 23:40:51.259605 end: 2.4.3 bootloader-commands (duration 00:00:15) [common]
1116 23:40:51.261479 end: 2.4 uboot-commands (duration 00:00:52) [common]
1118 23:40:51.262913 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
1120 23:40:51.263945 end: 2 uboot-action (duration 00:00:52) [common]
1122 23:40:51.265762 Cleaning after the job
1123 23:40:51.266324 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968641/tftp-deploy-qf998odv/ramdisk
1124 23:40:51.295727 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968641/tftp-deploy-qf998odv/kernel
1125 23:40:51.352075 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968641/tftp-deploy-qf998odv/dtb
1126 23:40:51.352941 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968641/tftp-deploy-qf998odv/modules
1127 23:40:51.411692 start: 4.1 power-off (timeout 00:00:30) [common]
1128 23:40:51.412577 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1129 23:40:51.443820 >> OK - accepted request
1130 23:40:51.445870 Returned 0 in 0 seconds
1131 23:40:51.546654 end: 4.1 power-off (duration 00:00:00) [common]
1133 23:40:51.547635 start: 4.2 read-feedback (timeout 00:10:00) [common]
1134 23:40:51.548328 Listened to connection for namespace 'common' for up to 1s
1135 23:40:52.549266 Finalising connection for namespace 'common'
1136 23:40:52.549768 Disconnecting from shell: Finalise
1137 23:40:52.550078 =>
1138 23:40:52.650797 end: 4.2 read-feedback (duration 00:00:01) [common]
1139 23:40:52.651224 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/968641
1140 23:40:52.962526 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/968641
1141 23:40:52.963114 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.