Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 23:40:06.290903 lava-dispatcher, installed at version: 2024.01
2 23:40:06.291688 start: 0 validate
3 23:40:06.292234 Start time: 2024-11-09 23:40:06.292204+00:00 (UTC)
4 23:40:06.292825 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:40:06.293363 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 23:40:06.335049 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:40:06.335638 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 23:40:06.377588 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:40:06.378227 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 23:40:07.430848 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:40:07.431354 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 23:40:07.476048 validate duration: 1.18
14 23:40:07.477190 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:40:07.477526 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:40:07.477846 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:40:07.478820 Not decompressing ramdisk as can be used compressed.
18 23:40:07.479546 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 23:40:07.480135 saving as /var/lib/lava/dispatcher/tmp/968619/tftp-deploy-dhz1y3w6/ramdisk/rootfs.cpio.gz
20 23:40:07.480439 total size: 8181887 (7 MB)
21 23:40:07.520624 progress 0 % (0 MB)
22 23:40:07.532621 progress 5 % (0 MB)
23 23:40:07.543919 progress 10 % (0 MB)
24 23:40:07.555800 progress 15 % (1 MB)
25 23:40:07.561206 progress 20 % (1 MB)
26 23:40:07.566926 progress 25 % (1 MB)
27 23:40:07.572134 progress 30 % (2 MB)
28 23:40:07.577689 progress 35 % (2 MB)
29 23:40:07.582925 progress 40 % (3 MB)
30 23:40:07.588422 progress 45 % (3 MB)
31 23:40:07.593678 progress 50 % (3 MB)
32 23:40:07.599154 progress 55 % (4 MB)
33 23:40:07.604311 progress 60 % (4 MB)
34 23:40:07.609773 progress 65 % (5 MB)
35 23:40:07.614748 progress 70 % (5 MB)
36 23:40:07.620268 progress 75 % (5 MB)
37 23:40:07.625344 progress 80 % (6 MB)
38 23:40:07.630657 progress 85 % (6 MB)
39 23:40:07.635454 progress 90 % (7 MB)
40 23:40:07.640507 progress 95 % (7 MB)
41 23:40:07.645426 progress 100 % (7 MB)
42 23:40:07.646062 7 MB downloaded in 0.17 s (47.12 MB/s)
43 23:40:07.646605 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:40:07.647491 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:40:07.647780 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:40:07.648077 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:40:07.648548 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig+debug/gcc-12/kernel/Image
49 23:40:07.648794 saving as /var/lib/lava/dispatcher/tmp/968619/tftp-deploy-dhz1y3w6/kernel/Image
50 23:40:07.649002 total size: 169937408 (162 MB)
51 23:40:07.649210 No compression specified
52 23:40:07.688313 progress 0 % (0 MB)
53 23:40:07.786695 progress 5 % (8 MB)
54 23:40:07.884020 progress 10 % (16 MB)
55 23:40:07.981223 progress 15 % (24 MB)
56 23:40:08.080099 progress 20 % (32 MB)
57 23:40:08.178076 progress 25 % (40 MB)
58 23:40:08.275612 progress 30 % (48 MB)
59 23:40:08.373273 progress 35 % (56 MB)
60 23:40:08.468964 progress 40 % (64 MB)
61 23:40:08.566937 progress 45 % (72 MB)
62 23:40:08.664126 progress 50 % (81 MB)
63 23:40:08.761344 progress 55 % (89 MB)
64 23:40:08.859525 progress 60 % (97 MB)
65 23:40:08.957754 progress 65 % (105 MB)
66 23:40:09.055626 progress 70 % (113 MB)
67 23:40:09.153111 progress 75 % (121 MB)
68 23:40:09.249919 progress 80 % (129 MB)
69 23:40:09.348652 progress 85 % (137 MB)
70 23:40:09.447461 progress 90 % (145 MB)
71 23:40:09.546400 progress 95 % (153 MB)
72 23:40:09.644239 progress 100 % (162 MB)
73 23:40:09.644804 162 MB downloaded in 2.00 s (81.20 MB/s)
74 23:40:09.645283 end: 1.2.1 http-download (duration 00:00:02) [common]
76 23:40:09.646185 end: 1.2 download-retry (duration 00:00:02) [common]
77 23:40:09.646461 start: 1.3 download-retry (timeout 00:09:58) [common]
78 23:40:09.646726 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 23:40:09.647184 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 23:40:09.647450 saving as /var/lib/lava/dispatcher/tmp/968619/tftp-deploy-dhz1y3w6/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 23:40:09.647659 total size: 53209 (0 MB)
82 23:40:09.647868 No compression specified
83 23:40:09.689362 progress 61 % (0 MB)
84 23:40:09.690196 progress 100 % (0 MB)
85 23:40:09.690714 0 MB downloaded in 0.04 s (1.18 MB/s)
86 23:40:09.691173 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:40:09.691976 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:40:09.692281 start: 1.4 download-retry (timeout 00:09:58) [common]
90 23:40:09.692545 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 23:40:09.693000 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 23:40:09.693238 saving as /var/lib/lava/dispatcher/tmp/968619/tftp-deploy-dhz1y3w6/modules/modules.tar
93 23:40:09.693444 total size: 27648112 (26 MB)
94 23:40:09.693654 Using unxz to decompress xz
95 23:40:09.734421 progress 0 % (0 MB)
96 23:40:09.926937 progress 5 % (1 MB)
97 23:40:10.126928 progress 10 % (2 MB)
98 23:40:10.357299 progress 15 % (3 MB)
99 23:40:10.597260 progress 20 % (5 MB)
100 23:40:10.794653 progress 25 % (6 MB)
101 23:40:11.000454 progress 30 % (7 MB)
102 23:40:11.203807 progress 35 % (9 MB)
103 23:40:11.398257 progress 40 % (10 MB)
104 23:40:11.592687 progress 45 % (11 MB)
105 23:40:11.801051 progress 50 % (13 MB)
106 23:40:12.004170 progress 55 % (14 MB)
107 23:40:12.219169 progress 60 % (15 MB)
108 23:40:12.421706 progress 65 % (17 MB)
109 23:40:12.622194 progress 70 % (18 MB)
110 23:40:12.833260 progress 75 % (19 MB)
111 23:40:13.040436 progress 80 % (21 MB)
112 23:40:13.299656 progress 85 % (22 MB)
113 23:40:13.523549 progress 90 % (23 MB)
114 23:40:13.734372 progress 95 % (25 MB)
115 23:40:13.938734 progress 100 % (26 MB)
116 23:40:13.952977 26 MB downloaded in 4.26 s (6.19 MB/s)
117 23:40:13.953937 end: 1.4.1 http-download (duration 00:00:04) [common]
119 23:40:13.955616 end: 1.4 download-retry (duration 00:00:04) [common]
120 23:40:13.956891 start: 1.5 prepare-tftp-overlay (timeout 00:09:54) [common]
121 23:40:13.957594 start: 1.5.1 extract-nfsrootfs (timeout 00:09:54) [common]
122 23:40:13.958157 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:40:13.958717 start: 1.5.2 lava-overlay (timeout 00:09:54) [common]
124 23:40:13.959794 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl
125 23:40:13.960743 makedir: /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin
126 23:40:13.961438 makedir: /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/tests
127 23:40:13.962114 makedir: /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/results
128 23:40:13.962815 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-add-keys
129 23:40:13.963839 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-add-sources
130 23:40:13.964903 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-background-process-start
131 23:40:13.965936 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-background-process-stop
132 23:40:13.966997 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-common-functions
133 23:40:13.968025 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-echo-ipv4
134 23:40:13.969047 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-install-packages
135 23:40:13.970034 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-installed-packages
136 23:40:13.971024 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-os-build
137 23:40:13.972057 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-probe-channel
138 23:40:13.973074 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-probe-ip
139 23:40:13.974068 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-target-ip
140 23:40:13.975088 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-target-mac
141 23:40:13.976095 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-target-storage
142 23:40:13.977098 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-test-case
143 23:40:13.978105 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-test-event
144 23:40:13.979124 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-test-feedback
145 23:40:13.980157 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-test-raise
146 23:40:13.981162 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-test-reference
147 23:40:13.982142 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-test-runner
148 23:40:13.983123 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-test-set
149 23:40:13.984120 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-test-shell
150 23:40:13.985134 Updating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-install-packages (oe)
151 23:40:13.986205 Updating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/bin/lava-installed-packages (oe)
152 23:40:13.987105 Creating /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/environment
153 23:40:13.987880 LAVA metadata
154 23:40:13.988474 - LAVA_JOB_ID=968619
155 23:40:13.988949 - LAVA_DISPATCHER_IP=192.168.6.2
156 23:40:13.989674 start: 1.5.2.1 ssh-authorize (timeout 00:09:53) [common]
157 23:40:13.991644 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 23:40:13.992353 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:53) [common]
159 23:40:13.992818 skipped lava-vland-overlay
160 23:40:13.993360 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 23:40:13.993920 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:53) [common]
162 23:40:13.994389 skipped lava-multinode-overlay
163 23:40:13.994925 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 23:40:13.995478 start: 1.5.2.4 test-definition (timeout 00:09:53) [common]
165 23:40:13.996069 Loading test definitions
166 23:40:13.996644 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:53) [common]
167 23:40:13.997101 Using /lava-968619 at stage 0
168 23:40:13.999274 uuid=968619_1.5.2.4.1 testdef=None
169 23:40:13.999866 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 23:40:14.000429 start: 1.5.2.4.2 test-overlay (timeout 00:09:53) [common]
171 23:40:14.003770 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 23:40:14.004788 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:53) [common]
174 23:40:14.007152 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 23:40:14.008050 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:53) [common]
177 23:40:14.010334 runner path: /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/0/tests/0_dmesg test_uuid 968619_1.5.2.4.1
178 23:40:14.010959 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 23:40:14.011765 Creating lava-test-runner.conf files
181 23:40:14.011969 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/968619/lava-overlay-f6588fbl/lava-968619/0 for stage 0
182 23:40:14.012437 - 0_dmesg
183 23:40:14.012844 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 23:40:14.013146 start: 1.5.2.5 compress-overlay (timeout 00:09:53) [common]
185 23:40:14.036713 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 23:40:14.037135 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:53) [common]
187 23:40:14.037409 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 23:40:14.037684 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 23:40:14.037952 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
190 23:40:15.065176 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 23:40:15.065621 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
192 23:40:15.065871 extracting modules file /var/lib/lava/dispatcher/tmp/968619/tftp-deploy-dhz1y3w6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/968619/extract-overlay-ramdisk-zdw3772a/ramdisk
193 23:40:16.870219 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 23:40:16.870678 start: 1.5.5 apply-overlay-tftp (timeout 00:09:51) [common]
195 23:40:16.870957 [common] Applying overlay /var/lib/lava/dispatcher/tmp/968619/compress-overlay-7qfb7wgy/overlay-1.5.2.5.tar.gz to ramdisk
196 23:40:16.871173 [common] Applying overlay /var/lib/lava/dispatcher/tmp/968619/compress-overlay-7qfb7wgy/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/968619/extract-overlay-ramdisk-zdw3772a/ramdisk
197 23:40:16.901278 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 23:40:16.901694 start: 1.5.6 prepare-kernel (timeout 00:09:51) [common]
199 23:40:16.901964 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:51) [common]
200 23:40:16.902191 Converting downloaded kernel to a uImage
201 23:40:16.902494 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/968619/tftp-deploy-dhz1y3w6/kernel/Image /var/lib/lava/dispatcher/tmp/968619/tftp-deploy-dhz1y3w6/kernel/uImage
202 23:40:18.589421 output: Image Name:
203 23:40:18.589815 output: Created: Sat Nov 9 23:40:16 2024
204 23:40:18.590051 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 23:40:18.590257 output: Data Size: 169937408 Bytes = 165954.50 KiB = 162.06 MiB
206 23:40:18.590465 output: Load Address: 01080000
207 23:40:18.590664 output: Entry Point: 01080000
208 23:40:18.590863 output:
209 23:40:18.591187 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 23:40:18.591453 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 23:40:18.591722 start: 1.5.7 configure-preseed-file (timeout 00:09:49) [common]
212 23:40:18.592007 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 23:40:18.592275 start: 1.5.8 compress-ramdisk (timeout 00:09:49) [common]
214 23:40:18.592547 Building ramdisk /var/lib/lava/dispatcher/tmp/968619/extract-overlay-ramdisk-zdw3772a/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/968619/extract-overlay-ramdisk-zdw3772a/ramdisk
215 23:40:24.225522 >> 441555 blocks
216 23:40:42.891500 Adding RAMdisk u-boot header.
217 23:40:42.891945 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/968619/extract-overlay-ramdisk-zdw3772a/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/968619/extract-overlay-ramdisk-zdw3772a/ramdisk.cpio.gz.uboot
218 23:40:43.442926 output: Image Name:
219 23:40:43.443600 output: Created: Sat Nov 9 23:40:42 2024
220 23:40:43.444112 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 23:40:43.444569 output: Data Size: 53585890 Bytes = 52329.97 KiB = 51.10 MiB
222 23:40:43.445012 output: Load Address: 00000000
223 23:40:43.445452 output: Entry Point: 00000000
224 23:40:43.445886 output:
225 23:40:43.446998 rename /var/lib/lava/dispatcher/tmp/968619/extract-overlay-ramdisk-zdw3772a/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/968619/tftp-deploy-dhz1y3w6/ramdisk/ramdisk.cpio.gz.uboot
226 23:40:43.447768 end: 1.5.8 compress-ramdisk (duration 00:00:25) [common]
227 23:40:43.448407 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
228 23:40:43.448992 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:24) [common]
229 23:40:43.449489 No LXC device requested
230 23:40:43.450039 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 23:40:43.450597 start: 1.7 deploy-device-env (timeout 00:09:24) [common]
232 23:40:43.451136 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 23:40:43.451589 Checking files for TFTP limit of 4294967296 bytes.
234 23:40:43.454512 end: 1 tftp-deploy (duration 00:00:36) [common]
235 23:40:43.455144 start: 2 uboot-action (timeout 00:05:00) [common]
236 23:40:43.455715 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 23:40:43.456298 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 23:40:43.456844 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 23:40:43.457423 Using kernel file from prepare-kernel: 968619/tftp-deploy-dhz1y3w6/kernel/uImage
240 23:40:43.458092 substitutions:
241 23:40:43.458538 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 23:40:43.458981 - {DTB_ADDR}: 0x01070000
243 23:40:43.459419 - {DTB}: 968619/tftp-deploy-dhz1y3w6/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 23:40:43.459860 - {INITRD}: 968619/tftp-deploy-dhz1y3w6/ramdisk/ramdisk.cpio.gz.uboot
245 23:40:43.460332 - {KERNEL_ADDR}: 0x01080000
246 23:40:43.460767 - {KERNEL}: 968619/tftp-deploy-dhz1y3w6/kernel/uImage
247 23:40:43.461203 - {LAVA_MAC}: None
248 23:40:43.461680 - {PRESEED_CONFIG}: None
249 23:40:43.462117 - {PRESEED_LOCAL}: None
250 23:40:43.462547 - {RAMDISK_ADDR}: 0x08000000
251 23:40:43.462982 - {RAMDISK}: 968619/tftp-deploy-dhz1y3w6/ramdisk/ramdisk.cpio.gz.uboot
252 23:40:43.463420 - {ROOT_PART}: None
253 23:40:43.463850 - {ROOT}: None
254 23:40:43.464308 - {SERVER_IP}: 192.168.6.2
255 23:40:43.464742 - {TEE_ADDR}: 0x83000000
256 23:40:43.465170 - {TEE}: None
257 23:40:43.465598 Parsed boot commands:
258 23:40:43.466013 - setenv autoload no
259 23:40:43.466437 - setenv initrd_high 0xffffffff
260 23:40:43.466863 - setenv fdt_high 0xffffffff
261 23:40:43.467285 - dhcp
262 23:40:43.467716 - setenv serverip 192.168.6.2
263 23:40:43.468200 - tftpboot 0x01080000 968619/tftp-deploy-dhz1y3w6/kernel/uImage
264 23:40:43.468635 - tftpboot 0x08000000 968619/tftp-deploy-dhz1y3w6/ramdisk/ramdisk.cpio.gz.uboot
265 23:40:43.469065 - tftpboot 0x01070000 968619/tftp-deploy-dhz1y3w6/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 23:40:43.469493 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 23:40:43.469926 - bootm 0x01080000 0x08000000 0x01070000
268 23:40:43.470480 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 23:40:43.472146 start: 2.3 connect-device (timeout 00:05:00) [common]
271 23:40:43.472639 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 23:40:43.487799 Setting prompt string to ['lava-test: # ']
273 23:40:43.489484 end: 2.3 connect-device (duration 00:00:00) [common]
274 23:40:43.490131 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 23:40:43.490716 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 23:40:43.491270 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 23:40:43.492530 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 23:40:43.531092 >> OK - accepted request
279 23:40:43.533265 Returned 0 in 0 seconds
280 23:40:43.634400 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 23:40:43.636141 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 23:40:43.636767 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 23:40:43.637323 Setting prompt string to ['Hit any key to stop autoboot']
285 23:40:43.637807 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 23:40:43.639508 Trying 192.168.56.21...
287 23:40:43.640107 Connected to conserv1.
288 23:40:43.640573 Escape character is '^]'.
289 23:40:43.641038
290 23:40:43.641500 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 23:40:43.641985
292 23:40:51.138821 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 23:40:51.139480 bl2_stage_init 0x01
294 23:40:51.139956 bl2_stage_init 0x81
295 23:40:51.144421 hw id: 0x0000 - pwm id 0x01
296 23:40:51.144906 bl2_stage_init 0xc1
297 23:40:51.145353 bl2_stage_init 0x02
298 23:40:51.145792
299 23:40:51.150028 L0:00000000
300 23:40:51.150493 L1:00000703
301 23:40:51.150924 L2:00008067
302 23:40:51.151352 L3:15000000
303 23:40:51.151785 S1:00000000
304 23:40:51.155525 B2:20282000
305 23:40:51.156008 B1:a0f83180
306 23:40:51.156442
307 23:40:51.156875 TE: 70699
308 23:40:51.157306
309 23:40:51.161190 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 23:40:51.161664
311 23:40:51.166770 Board ID = 1
312 23:40:51.167235 Set cpu clk to 24M
313 23:40:51.167664 Set clk81 to 24M
314 23:40:51.172286 Use GP1_pll as DSU clk.
315 23:40:51.172742 DSU clk: 1200 Mhz
316 23:40:51.173170 CPU clk: 1200 MHz
317 23:40:51.173598 Set clk81 to 166.6M
318 23:40:51.183462 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 23:40:51.183928 board id: 1
320 23:40:51.190057 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 23:40:51.200624 fw parse done
322 23:40:51.206675 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 23:40:51.249238 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 23:40:51.260070 PIEI prepare done
325 23:40:51.260542 fastboot data load
326 23:40:51.260976 fastboot data verify
327 23:40:51.265685 verify result: 266
328 23:40:51.271305 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 23:40:51.271775 LPDDR4 probe
330 23:40:51.272261 ddr clk to 1584MHz
331 23:40:51.279189 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 23:40:51.316497
333 23:40:51.317009 dmc_version 0001
334 23:40:51.323169 Check phy result
335 23:40:51.329082 INFO : End of CA training
336 23:40:51.329552 INFO : End of initialization
337 23:40:51.334692 INFO : Training has run successfully!
338 23:40:51.335154 Check phy result
339 23:40:51.340282 INFO : End of initialization
340 23:40:51.340742 INFO : End of read enable training
341 23:40:51.343617 INFO : End of fine write leveling
342 23:40:51.349190 INFO : End of Write leveling coarse delay
343 23:40:51.354788 INFO : Training has run successfully!
344 23:40:51.355245 Check phy result
345 23:40:51.355679 INFO : End of initialization
346 23:40:51.360438 INFO : End of read dq deskew training
347 23:40:51.366005 INFO : End of MPR read delay center optimization
348 23:40:51.366473 INFO : End of write delay center optimization
349 23:40:51.372378 INFO : End of read delay center optimization
350 23:40:51.377229 INFO : End of max read latency training
351 23:40:51.377686 INFO : Training has run successfully!
352 23:40:51.382841 1D training succeed
353 23:40:51.388210 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 23:40:51.435405 Check phy result
355 23:40:51.435887 INFO : End of initialization
356 23:40:51.458700 INFO : End of 2D read delay Voltage center optimization
357 23:40:51.477728 INFO : End of 2D read delay Voltage center optimization
358 23:40:51.529675 INFO : End of 2D write delay Voltage center optimization
359 23:40:51.578817 INFO : End of 2D write delay Voltage center optimization
360 23:40:51.584371 INFO : Training has run successfully!
361 23:40:51.584832
362 23:40:51.585265 channel==0
363 23:40:51.590062 RxClkDly_Margin_A0==88 ps 9
364 23:40:51.590525 TxDqDly_Margin_A0==98 ps 10
365 23:40:51.595571 RxClkDly_Margin_A1==88 ps 9
366 23:40:51.596070 TxDqDly_Margin_A1==98 ps 10
367 23:40:51.596512 TrainedVREFDQ_A0==74
368 23:40:51.601168 TrainedVREFDQ_A1==74
369 23:40:51.601636 VrefDac_Margin_A0==22
370 23:40:51.602068 DeviceVref_Margin_A0==40
371 23:40:51.606789 VrefDac_Margin_A1==23
372 23:40:51.607242 DeviceVref_Margin_A1==40
373 23:40:51.607674
374 23:40:51.608136
375 23:40:51.612410 channel==1
376 23:40:51.612866 RxClkDly_Margin_A0==78 ps 8
377 23:40:51.613299 TxDqDly_Margin_A0==98 ps 10
378 23:40:51.618004 RxClkDly_Margin_A1==78 ps 8
379 23:40:51.618458 TxDqDly_Margin_A1==88 ps 9
380 23:40:51.623731 TrainedVREFDQ_A0==78
381 23:40:51.624223 TrainedVREFDQ_A1==77
382 23:40:51.624654 VrefDac_Margin_A0==22
383 23:40:51.629256 DeviceVref_Margin_A0==36
384 23:40:51.629709 VrefDac_Margin_A1==22
385 23:40:51.634807 DeviceVref_Margin_A1==37
386 23:40:51.635257
387 23:40:51.635687 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 23:40:51.636144
389 23:40:51.668391 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000015 00000017 dram_vref_reg_value 0x 00000060
390 23:40:51.668910 2D training succeed
391 23:40:51.674023 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 23:40:51.679661 auto size-- 65535DDR cs0 size: 2048MB
393 23:40:51.680149 DDR cs1 size: 2048MB
394 23:40:51.685171 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 23:40:51.685624 cs0 DataBus test pass
396 23:40:51.690780 cs1 DataBus test pass
397 23:40:51.691230 cs0 AddrBus test pass
398 23:40:51.691652 cs1 AddrBus test pass
399 23:40:51.692111
400 23:40:51.696365 100bdlr_step_size ps== 478
401 23:40:51.696840 result report
402 23:40:51.702025 boot times 0Enable ddr reg access
403 23:40:51.707258 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 23:40:51.721097 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 23:40:52.377089 bl2z: ptr: 05129330, size: 00001e40
406 23:40:52.381718 0.0;M3 CHK:0;cm4_sp_mode 0
407 23:40:52.382211 MVN_1=0x00000000
408 23:40:52.382653 MVN_2=0x00000000
409 23:40:52.393178 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 23:40:52.393648 OPS=0x04
411 23:40:52.394087 ring efuse init
412 23:40:52.398823 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 23:40:52.399293 [0.017310 Inits done]
414 23:40:52.399720 secure task start!
415 23:40:52.406188 high task start!
416 23:40:52.406647 low task start!
417 23:40:52.407079 run into bl31
418 23:40:52.414857 NOTICE: BL31: v1.3(release):4fc40b1
419 23:40:52.422604 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 23:40:52.423077 NOTICE: BL31: G12A normal boot!
421 23:40:52.438157 NOTICE: BL31: BL33 decompress pass
422 23:40:52.443851 ERROR: Error initializing runtime service opteed_fast
423 23:40:55.186441 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 23:40:55.187090 bl2_stage_init 0x01
425 23:40:55.187567 bl2_stage_init 0x81
426 23:40:55.191854 hw id: 0x0000 - pwm id 0x01
427 23:40:55.192404 bl2_stage_init 0xc1
428 23:40:55.197182 bl2_stage_init 0x02
429 23:40:55.197714
430 23:40:55.198155 L0:00000000
431 23:40:55.198586 L1:00000703
432 23:40:55.199012 L2:00008067
433 23:40:55.199433 L3:15000000
434 23:40:55.202687 S1:00000000
435 23:40:55.203163 B2:20282000
436 23:40:55.203593 B1:a0f83180
437 23:40:55.204061
438 23:40:55.204494 TE: 69078
439 23:40:55.204921
440 23:40:55.208355 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 23:40:55.213880
442 23:40:55.214337 Board ID = 1
443 23:40:55.214765 Set cpu clk to 24M
444 23:40:55.215187 Set clk81 to 24M
445 23:40:55.217322 Use GP1_pll as DSU clk.
446 23:40:55.217776 DSU clk: 1200 Mhz
447 23:40:55.222840 CPU clk: 1200 MHz
448 23:40:55.223293 Set clk81 to 166.6M
449 23:40:55.228480 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 23:40:55.228937 board id: 1
451 23:40:55.238029 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 23:40:55.249152 fw parse done
453 23:40:55.254579 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 23:40:55.298374 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 23:40:55.309429 PIEI prepare done
456 23:40:55.309897 fastboot data load
457 23:40:55.310332 fastboot data verify
458 23:40:55.314987 verify result: 266
459 23:40:55.320572 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 23:40:55.321027 LPDDR4 probe
461 23:40:55.321448 ddr clk to 1584MHz
462 23:40:55.328057 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 23:40:55.365478
464 23:40:55.365932 dmc_version 0001
465 23:40:55.372764 Check phy result
466 23:40:55.379456 INFO : End of CA training
467 23:40:55.379965 INFO : End of initialization
468 23:40:55.384989 INFO : Training has run successfully!
469 23:40:55.385466 Check phy result
470 23:40:55.390538 INFO : End of initialization
471 23:40:55.391006 INFO : End of read enable training
472 23:40:55.396195 INFO : End of fine write leveling
473 23:40:55.401725 INFO : End of Write leveling coarse delay
474 23:40:55.402190 INFO : Training has run successfully!
475 23:40:55.402631 Check phy result
476 23:40:55.407433 INFO : End of initialization
477 23:40:55.407892 INFO : End of read dq deskew training
478 23:40:55.412939 INFO : End of MPR read delay center optimization
479 23:40:55.418533 INFO : End of write delay center optimization
480 23:40:55.424163 INFO : End of read delay center optimization
481 23:40:55.424621 INFO : End of max read latency training
482 23:40:55.429709 INFO : Training has run successfully!
483 23:40:55.430175 1D training succeed
484 23:40:55.438807 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 23:40:55.486300 Check phy result
486 23:40:55.486769 INFO : End of initialization
487 23:40:55.513743 INFO : End of 2D read delay Voltage center optimization
488 23:40:55.538293 INFO : End of 2D read delay Voltage center optimization
489 23:40:55.594662 INFO : End of 2D write delay Voltage center optimization
490 23:40:55.649488 INFO : End of 2D write delay Voltage center optimization
491 23:40:55.654992 INFO : Training has run successfully!
492 23:40:55.655454
493 23:40:55.655900 channel==0
494 23:40:55.660625 RxClkDly_Margin_A0==78 ps 8
495 23:40:55.661089 TxDqDly_Margin_A0==98 ps 10
496 23:40:55.666206 RxClkDly_Margin_A1==88 ps 9
497 23:40:55.666665 TxDqDly_Margin_A1==98 ps 10
498 23:40:55.667106 TrainedVREFDQ_A0==74
499 23:40:55.671781 TrainedVREFDQ_A1==75
500 23:40:55.672275 VrefDac_Margin_A0==22
501 23:40:55.672716 DeviceVref_Margin_A0==40
502 23:40:55.677464 VrefDac_Margin_A1==22
503 23:40:55.677941 DeviceVref_Margin_A1==39
504 23:40:55.678386
505 23:40:55.678821
506 23:40:55.682997 channel==1
507 23:40:55.683457 RxClkDly_Margin_A0==78 ps 8
508 23:40:55.683896 TxDqDly_Margin_A0==98 ps 10
509 23:40:55.688570 RxClkDly_Margin_A1==78 ps 8
510 23:40:55.689042 TxDqDly_Margin_A1==88 ps 9
511 23:40:55.694216 TrainedVREFDQ_A0==78
512 23:40:55.694682 TrainedVREFDQ_A1==75
513 23:40:55.695129 VrefDac_Margin_A0==22
514 23:40:55.699810 DeviceVref_Margin_A0==36
515 23:40:55.700298 VrefDac_Margin_A1==20
516 23:40:55.705456 DeviceVref_Margin_A1==39
517 23:40:55.705916
518 23:40:55.706359 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 23:40:55.706796
520 23:40:55.739014 soc_vref_reg_value 0x 00000019 00000018 00000017 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
521 23:40:55.739529 2D training succeed
522 23:40:55.744611 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 23:40:55.750224 auto size-- 65535DDR cs0 size: 2048MB
524 23:40:55.750690 DDR cs1 size: 2048MB
525 23:40:55.755806 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 23:40:55.756305 cs0 DataBus test pass
527 23:40:55.761483 cs1 DataBus test pass
528 23:40:55.761946 cs0 AddrBus test pass
529 23:40:55.762383 cs1 AddrBus test pass
530 23:40:55.762813
531 23:40:55.767026 100bdlr_step_size ps== 471
532 23:40:55.767496 result report
533 23:40:55.772598 boot times 0Enable ddr reg access
534 23:40:55.777176 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 23:40:55.791461 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 23:40:56.452066 bl2z: ptr: 05129330, size: 00001e40
537 23:40:56.460183 0.0;M3 CHK:0;cm4_sp_mode 0
538 23:40:56.460682 MVN_1=0x00000000
539 23:40:56.461129 MVN_2=0x00000000
540 23:40:56.471679 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 23:40:56.472195 OPS=0x04
542 23:40:56.472650 ring efuse init
543 23:40:56.474608 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 23:40:56.481073 [0.017354 Inits done]
545 23:40:56.481542 secure task start!
546 23:40:56.481984 high task start!
547 23:40:56.482421 low task start!
548 23:40:56.484834 run into bl31
549 23:40:56.493980 NOTICE: BL31: v1.3(release):4fc40b1
550 23:40:56.501465 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 23:40:56.501942 NOTICE: BL31: G12A normal boot!
552 23:40:56.517385 NOTICE: BL31: BL33 decompress pass
553 23:40:56.522521 ERROR: Error initializing runtime service opteed_fast
554 23:40:57.886506 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 23:40:57.887132 bl2_stage_init 0x01
556 23:40:57.887603 bl2_stage_init 0x81
557 23:40:57.892071 hw id: 0x0000 - pwm id 0x01
558 23:40:57.892556 bl2_stage_init 0xc1
559 23:40:57.893009 bl2_stage_init 0x02
560 23:40:57.893454
561 23:40:57.897695 L0:00000000
562 23:40:57.898168 L1:00000703
563 23:40:57.898612 L2:00008067
564 23:40:57.899052 L3:15000000
565 23:40:57.899484 S1:00000000
566 23:40:57.903252 B2:20282000
567 23:40:57.903731 B1:a0f83180
568 23:40:57.904212
569 23:40:57.904662 TE: 68059
570 23:40:57.905101
571 23:40:57.908839 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 23:40:57.909314
573 23:40:57.914459 Board ID = 1
574 23:40:57.914931 Set cpu clk to 24M
575 23:40:57.915375 Set clk81 to 24M
576 23:40:57.920092 Use GP1_pll as DSU clk.
577 23:40:57.920572 DSU clk: 1200 Mhz
578 23:40:57.921015 CPU clk: 1200 MHz
579 23:40:57.921450 Set clk81 to 166.6M
580 23:40:57.931206 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 23:40:57.931683 board id: 1
582 23:40:57.936727 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 23:40:57.948326 fw parse done
584 23:40:57.953293 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 23:40:57.995921 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 23:40:58.007902 PIEI prepare done
587 23:40:58.008402 fastboot data load
588 23:40:58.008855 fastboot data verify
589 23:40:58.013464 verify result: 266
590 23:40:58.019058 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 23:40:58.019542 LPDDR4 probe
592 23:40:58.020017 ddr clk to 1584MHz
593 23:40:58.026037 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 23:40:58.063479
595 23:40:58.064013 dmc_version 0001
596 23:40:58.070988 Check phy result
597 23:40:58.076849 INFO : End of CA training
598 23:40:58.077316 INFO : End of initialization
599 23:40:58.082532 INFO : Training has run successfully!
600 23:40:58.082999 Check phy result
601 23:40:58.088224 INFO : End of initialization
602 23:40:58.088701 INFO : End of read enable training
603 23:40:58.091454 INFO : End of fine write leveling
604 23:40:58.096928 INFO : End of Write leveling coarse delay
605 23:40:58.102612 INFO : Training has run successfully!
606 23:40:58.103122 Check phy result
607 23:40:58.103573 INFO : End of initialization
608 23:40:58.108144 INFO : End of read dq deskew training
609 23:40:58.111545 INFO : End of MPR read delay center optimization
610 23:40:58.117052 INFO : End of write delay center optimization
611 23:40:58.122659 INFO : End of read delay center optimization
612 23:40:58.123125 INFO : End of max read latency training
613 23:40:58.128228 INFO : Training has run successfully!
614 23:40:58.128697 1D training succeed
615 23:40:58.135577 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 23:40:58.183087 Check phy result
617 23:40:58.183610 INFO : End of initialization
618 23:40:58.205656 INFO : End of 2D read delay Voltage center optimization
619 23:40:58.225558 INFO : End of 2D read delay Voltage center optimization
620 23:40:58.276564 INFO : End of 2D write delay Voltage center optimization
621 23:40:58.326722 INFO : End of 2D write delay Voltage center optimization
622 23:40:58.332231 INFO : Training has run successfully!
623 23:40:58.332706
624 23:40:58.333158 channel==0
625 23:40:58.337838 RxClkDly_Margin_A0==78 ps 8
626 23:40:58.338305 TxDqDly_Margin_A0==98 ps 10
627 23:40:58.343369 RxClkDly_Margin_A1==88 ps 9
628 23:40:58.343835 TxDqDly_Margin_A1==98 ps 10
629 23:40:58.344328 TrainedVREFDQ_A0==74
630 23:40:58.348983 TrainedVREFDQ_A1==74
631 23:40:58.349450 VrefDac_Margin_A0==24
632 23:40:58.349893 DeviceVref_Margin_A0==40
633 23:40:58.354565 VrefDac_Margin_A1==23
634 23:40:58.355035 DeviceVref_Margin_A1==40
635 23:40:58.355472
636 23:40:58.355909
637 23:40:58.360184 channel==1
638 23:40:58.360647 RxClkDly_Margin_A0==88 ps 9
639 23:40:58.361096 TxDqDly_Margin_A0==98 ps 10
640 23:40:58.365831 RxClkDly_Margin_A1==88 ps 9
641 23:40:58.366295 TxDqDly_Margin_A1==88 ps 9
642 23:40:58.371433 TrainedVREFDQ_A0==78
643 23:40:58.371900 TrainedVREFDQ_A1==75
644 23:40:58.372391 VrefDac_Margin_A0==23
645 23:40:58.377042 DeviceVref_Margin_A0==36
646 23:40:58.377509 VrefDac_Margin_A1==20
647 23:40:58.382666 DeviceVref_Margin_A1==39
648 23:40:58.383131
649 23:40:58.383575 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 23:40:58.384048
651 23:40:58.416306 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
652 23:40:58.416861 2D training succeed
653 23:40:58.421860 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 23:40:58.427487 auto size-- 65535DDR cs0 size: 2048MB
655 23:40:58.427958 DDR cs1 size: 2048MB
656 23:40:58.433027 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 23:40:58.433497 cs0 DataBus test pass
658 23:40:58.438613 cs1 DataBus test pass
659 23:40:58.439077 cs0 AddrBus test pass
660 23:40:58.439518 cs1 AddrBus test pass
661 23:40:58.439951
662 23:40:58.444212 100bdlr_step_size ps== 478
663 23:40:58.444690 result report
664 23:40:58.449833 boot times 0Enable ddr reg access
665 23:40:58.454127 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 23:40:58.467948 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 23:40:59.124265 bl2z: ptr: 05129330, size: 00001e40
668 23:40:59.130761 0.0;M3 CHK:0;cm4_sp_mode 0
669 23:40:59.131291 MVN_1=0x00000000
670 23:40:59.131745 MVN_2=0x00000000
671 23:40:59.142222 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 23:40:59.142706 OPS=0x04
673 23:40:59.143156 ring efuse init
674 23:40:59.147904 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 23:40:59.148415 [0.017319 Inits done]
676 23:40:59.148859 secure task start!
677 23:40:59.155082 high task start!
678 23:40:59.155553 low task start!
679 23:40:59.156025 run into bl31
680 23:40:59.163705 NOTICE: BL31: v1.3(release):4fc40b1
681 23:40:59.171468 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 23:40:59.171943 NOTICE: BL31: G12A normal boot!
683 23:40:59.187041 NOTICE: BL31: BL33 decompress pass
684 23:40:59.192763 ERROR: Error initializing runtime service opteed_fast
685 23:40:59.988341
686 23:40:59.989005
687 23:40:59.993732 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 23:40:59.994267
689 23:40:59.997180 Model: Libre Computer AML-S905D3-CC Solitude
690 23:41:00.144451 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 23:41:00.159636 DRAM: 2 GiB (effective 3.8 GiB)
692 23:41:00.260648 Core: 406 devices, 33 uclasses, devicetree: separate
693 23:41:00.265512 WDT: Not starting watchdog@f0d0
694 23:41:00.291827 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 23:41:00.304795 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 23:41:00.309461 ** Bad device specification mmc 0 **
697 23:41:00.318738 Card did not respond to voltage select! : -110
698 23:41:00.326331 ** Bad device specification mmc 0 **
699 23:41:00.326906 Couldn't find partition mmc 0
700 23:41:00.334596 Card did not respond to voltage select! : -110
701 23:41:00.340105 ** Bad device specification mmc 0 **
702 23:41:00.340656 Couldn't find partition mmc 0
703 23:41:00.344606 Error: could not access storage.
704 23:41:00.641616 Net: eth0: ethernet@ff3f0000
705 23:41:00.642197 starting USB...
706 23:41:00.886194 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 23:41:00.886722 Starting the controller
708 23:41:00.893063 USB XHCI 1.10
709 23:41:02.446671 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 23:41:02.454893 scanning usb for storage devices... 0 Storage Device(s) found
712 23:41:02.506444 Hit any key to stop autoboot: 1
713 23:41:02.507534 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 23:41:02.508209 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 23:41:02.508698 Setting prompt string to ['=>']
716 23:41:02.509172 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 23:41:02.520892 0
718 23:41:02.521812 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 23:41:02.623086 => setenv autoload no
721 23:41:02.623835 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 23:41:02.628689 setenv autoload no
724 23:41:02.730153 => setenv initrd_high 0xffffffff
725 23:41:02.730771 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 23:41:02.735406 setenv initrd_high 0xffffffff
728 23:41:02.836797 => setenv fdt_high 0xffffffff
729 23:41:02.837427 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 23:41:02.842033 setenv fdt_high 0xffffffff
732 23:41:02.943425 => dhcp
733 23:41:02.944040 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 23:41:02.948298 dhcp
735 23:41:03.954257 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 23:41:03.954824 Speed: 1000, full duplex
737 23:41:03.955247 BOOTP broadcast 1
738 23:41:03.963850 DHCP client bound to address 192.168.6.21 (9 ms)
740 23:41:04.065317 => setenv serverip 192.168.6.2
741 23:41:04.066007 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
742 23:41:04.070599 setenv serverip 192.168.6.2
744 23:41:04.172030 => tftpboot 0x01080000 968619/tftp-deploy-dhz1y3w6/kernel/uImage
745 23:41:04.172689 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
746 23:41:04.179395 tftpboot 0x01080000 968619/tftp-deploy-dhz1y3w6/kernel/uImage
747 23:41:04.179860 Speed: 1000, full duplex
748 23:41:04.180302 Using ethernet@ff3f0000 device
749 23:41:04.184785 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 23:41:04.190467 Filename '968619/tftp-deploy-dhz1y3w6/kernel/uImage'.
751 23:41:04.194258 Load address: 0x1080000
752 23:41:08.002050 Loading: *################# UDP wrong checksum 00000005 00000b56
753 23:41:08.378224 ##
754 23:41:08.378818 TFTP error: trying to overwrite reserved memory...
756 23:41:08.380239 end: 2.4.3 bootloader-commands (duration 00:00:06) [common]
759 23:41:08.382358 end: 2.4 uboot-commands (duration 00:00:25) [common]
761 23:41:08.383801 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
763 23:41:08.384912 end: 2 uboot-action (duration 00:00:25) [common]
765 23:41:08.386433 Cleaning after the job
766 23:41:08.387271 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968619/tftp-deploy-dhz1y3w6/ramdisk
767 23:41:08.420776 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968619/tftp-deploy-dhz1y3w6/kernel
768 23:41:08.484826 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968619/tftp-deploy-dhz1y3w6/dtb
769 23:41:08.486192 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968619/tftp-deploy-dhz1y3w6/modules
770 23:41:08.546279 start: 4.1 power-off (timeout 00:00:30) [common]
771 23:41:08.546984 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
772 23:41:08.577966 >> OK - accepted request
773 23:41:08.580124 Returned 0 in 0 seconds
774 23:41:08.680830 end: 4.1 power-off (duration 00:00:00) [common]
776 23:41:08.681671 start: 4.2 read-feedback (timeout 00:10:00) [common]
777 23:41:08.682293 Listened to connection for namespace 'common' for up to 1s
778 23:41:09.683244 Finalising connection for namespace 'common'
779 23:41:09.683699 Disconnecting from shell: Finalise
780 23:41:09.683964 =>
781 23:41:09.784663 end: 4.2 read-feedback (duration 00:00:01) [common]
782 23:41:09.785007 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/968619
783 23:41:10.090869 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/968619
784 23:41:10.091462 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.