Boot log: meson-g12b-a311d-libretech-cc

    1 23:41:46.596625  lava-dispatcher, installed at version: 2024.01
    2 23:41:46.597408  start: 0 validate
    3 23:41:46.597900  Start time: 2024-11-09 23:41:46.597869+00:00 (UTC)
    4 23:41:46.598451  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
    5 23:41:46.598999  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
    6 23:41:46.641769  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
    7 23:41:46.642304  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
    8 23:41:46.675837  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
    9 23:41:46.676594  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
   10 23:41:46.712685  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
   11 23:41:46.713202  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
   12 23:41:46.748161  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
   13 23:41:46.748633  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
   14 23:41:46.793013  validate duration: 0.20
   16 23:41:46.794523  start: 1 tftp-deploy (timeout 00:10:00) [common]
   17 23:41:46.795134  start: 1.1 download-retry (timeout 00:10:00) [common]
   18 23:41:46.795736  start: 1.1.1 http-download (timeout 00:10:00) [common]
   19 23:41:46.796732  Not decompressing ramdisk as can be used compressed.
   20 23:41:46.797498  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
   21 23:41:46.798015  saving as /var/lib/lava/dispatcher/tmp/968618/tftp-deploy-tq0vpt0w/ramdisk/initrd.cpio.gz
   22 23:41:46.798523  total size: 5628182 (5 MB)
   23 23:41:46.841721  progress   0 % (0 MB)
   24 23:41:46.850302  progress   5 % (0 MB)
   25 23:41:46.859288  progress  10 % (0 MB)
   26 23:41:46.867415  progress  15 % (0 MB)
   27 23:41:46.873845  progress  20 % (1 MB)
   28 23:41:46.877580  progress  25 % (1 MB)
   29 23:41:46.881727  progress  30 % (1 MB)
   30 23:41:46.885953  progress  35 % (1 MB)
   31 23:41:46.889634  progress  40 % (2 MB)
   32 23:41:46.893774  progress  45 % (2 MB)
   33 23:41:46.897581  progress  50 % (2 MB)
   34 23:41:46.901763  progress  55 % (2 MB)
   35 23:41:46.905893  progress  60 % (3 MB)
   36 23:41:46.909583  progress  65 % (3 MB)
   37 23:41:46.913703  progress  70 % (3 MB)
   38 23:41:46.917469  progress  75 % (4 MB)
   39 23:41:46.921530  progress  80 % (4 MB)
   40 23:41:46.925374  progress  85 % (4 MB)
   41 23:41:46.929511  progress  90 % (4 MB)
   42 23:41:46.933418  progress  95 % (5 MB)
   43 23:41:46.936733  progress 100 % (5 MB)
   44 23:41:46.937384  5 MB downloaded in 0.14 s (38.66 MB/s)
   45 23:41:46.937951  end: 1.1.1 http-download (duration 00:00:00) [common]
   47 23:41:46.938890  end: 1.1 download-retry (duration 00:00:00) [common]
   48 23:41:46.939205  start: 1.2 download-retry (timeout 00:10:00) [common]
   49 23:41:46.939499  start: 1.2.1 http-download (timeout 00:10:00) [common]
   50 23:41:46.940018  downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig+debug/gcc-12/kernel/Image
   51 23:41:46.940294  saving as /var/lib/lava/dispatcher/tmp/968618/tftp-deploy-tq0vpt0w/kernel/Image
   52 23:41:46.940525  total size: 169937408 (162 MB)
   53 23:41:46.940754  No compression specified
   54 23:41:46.973725  progress   0 % (0 MB)
   55 23:41:47.077776  progress   5 % (8 MB)
   56 23:41:47.181162  progress  10 % (16 MB)
   57 23:41:47.284168  progress  15 % (24 MB)
   58 23:41:47.388454  progress  20 % (32 MB)
   59 23:41:47.491858  progress  25 % (40 MB)
   60 23:41:47.597021  progress  30 % (48 MB)
   61 23:41:47.701046  progress  35 % (56 MB)
   62 23:41:47.805086  progress  40 % (64 MB)
   63 23:41:47.908895  progress  45 % (72 MB)
   64 23:41:48.012212  progress  50 % (81 MB)
   65 23:41:48.115591  progress  55 % (89 MB)
   66 23:41:48.219447  progress  60 % (97 MB)
   67 23:41:48.323696  progress  65 % (105 MB)
   68 23:41:48.427812  progress  70 % (113 MB)
   69 23:41:48.531304  progress  75 % (121 MB)
   70 23:41:48.634340  progress  80 % (129 MB)
   71 23:41:48.738417  progress  85 % (137 MB)
   72 23:41:48.842453  progress  90 % (145 MB)
   73 23:41:48.946267  progress  95 % (153 MB)
   74 23:41:49.049640  progress 100 % (162 MB)
   75 23:41:49.050181  162 MB downloaded in 2.11 s (76.82 MB/s)
   76 23:41:49.050663  end: 1.2.1 http-download (duration 00:00:02) [common]
   78 23:41:49.051505  end: 1.2 download-retry (duration 00:00:02) [common]
   79 23:41:49.051787  start: 1.3 download-retry (timeout 00:09:58) [common]
   80 23:41:49.052085  start: 1.3.1 http-download (timeout 00:09:58) [common]
   81 23:41:49.052640  downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
   82 23:41:49.052926  saving as /var/lib/lava/dispatcher/tmp/968618/tftp-deploy-tq0vpt0w/dtb/meson-g12b-a311d-libretech-cc.dtb
   83 23:41:49.053140  total size: 54703 (0 MB)
   84 23:41:49.053354  No compression specified
   85 23:41:49.092615  progress  59 % (0 MB)
   86 23:41:49.093505  progress 100 % (0 MB)
   87 23:41:49.094065  0 MB downloaded in 0.04 s (1.28 MB/s)
   88 23:41:49.094533  end: 1.3.1 http-download (duration 00:00:00) [common]
   90 23:41:49.095366  end: 1.3 download-retry (duration 00:00:00) [common]
   91 23:41:49.095634  start: 1.4 download-retry (timeout 00:09:58) [common]
   92 23:41:49.095902  start: 1.4.1 http-download (timeout 00:09:58) [common]
   93 23:41:49.096401  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
   94 23:41:49.096648  saving as /var/lib/lava/dispatcher/tmp/968618/tftp-deploy-tq0vpt0w/nfsrootfs/full.rootfs.tar
   95 23:41:49.096857  total size: 107552908 (102 MB)
   96 23:41:49.097072  Using unxz to decompress xz
   97 23:41:49.135267  progress   0 % (0 MB)
   98 23:41:49.776100  progress   5 % (5 MB)
   99 23:41:50.496950  progress  10 % (10 MB)
  100 23:41:51.215235  progress  15 % (15 MB)
  101 23:41:51.969871  progress  20 % (20 MB)
  102 23:41:52.536974  progress  25 % (25 MB)
  103 23:41:53.154182  progress  30 % (30 MB)
  104 23:41:53.888673  progress  35 % (35 MB)
  105 23:41:54.233638  progress  40 % (41 MB)
  106 23:41:54.654757  progress  45 % (46 MB)
  107 23:41:55.343786  progress  50 % (51 MB)
  108 23:41:56.030597  progress  55 % (56 MB)
  109 23:41:56.787020  progress  60 % (61 MB)
  110 23:41:57.538946  progress  65 % (66 MB)
  111 23:41:58.268571  progress  70 % (71 MB)
  112 23:41:59.037855  progress  75 % (76 MB)
  113 23:41:59.710431  progress  80 % (82 MB)
  114 23:42:00.412591  progress  85 % (87 MB)
  115 23:42:01.169900  progress  90 % (92 MB)
  116 23:42:01.928321  progress  95 % (97 MB)
  117 23:42:02.761111  progress 100 % (102 MB)
  118 23:42:02.773383  102 MB downloaded in 13.68 s (7.50 MB/s)
  119 23:42:02.774305  end: 1.4.1 http-download (duration 00:00:14) [common]
  121 23:42:02.775924  end: 1.4 download-retry (duration 00:00:14) [common]
  122 23:42:02.776487  start: 1.5 download-retry (timeout 00:09:44) [common]
  123 23:42:02.777000  start: 1.5.1 http-download (timeout 00:09:44) [common]
  124 23:42:02.777810  downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig+debug/gcc-12/modules.tar.xz
  125 23:42:02.778257  saving as /var/lib/lava/dispatcher/tmp/968618/tftp-deploy-tq0vpt0w/modules/modules.tar
  126 23:42:02.778659  total size: 27648112 (26 MB)
  127 23:42:02.779074  Using unxz to decompress xz
  128 23:42:02.823368  progress   0 % (0 MB)
  129 23:42:03.009020  progress   5 % (1 MB)
  130 23:42:03.205559  progress  10 % (2 MB)
  131 23:42:03.431208  progress  15 % (3 MB)
  132 23:42:03.662702  progress  20 % (5 MB)
  133 23:42:03.860976  progress  25 % (6 MB)
  134 23:42:04.062404  progress  30 % (7 MB)
  135 23:42:04.261348  progress  35 % (9 MB)
  136 23:42:04.452069  progress  40 % (10 MB)
  137 23:42:04.641571  progress  45 % (11 MB)
  138 23:42:04.848031  progress  50 % (13 MB)
  139 23:42:05.051105  progress  55 % (14 MB)
  140 23:42:05.261245  progress  60 % (15 MB)
  141 23:42:05.461766  progress  65 % (17 MB)
  142 23:42:05.660407  progress  70 % (18 MB)
  143 23:42:05.870796  progress  75 % (19 MB)
  144 23:42:06.077389  progress  80 % (21 MB)
  145 23:42:06.284204  progress  85 % (22 MB)
  146 23:42:06.489162  progress  90 % (23 MB)
  147 23:42:06.688439  progress  95 % (25 MB)
  148 23:42:06.885777  progress 100 % (26 MB)
  149 23:42:06.899351  26 MB downloaded in 4.12 s (6.40 MB/s)
  150 23:42:06.899958  end: 1.5.1 http-download (duration 00:00:04) [common]
  152 23:42:06.901772  end: 1.5 download-retry (duration 00:00:04) [common]
  153 23:42:06.902358  start: 1.6 prepare-tftp-overlay (timeout 00:09:40) [common]
  154 23:42:06.902933  start: 1.6.1 extract-nfsrootfs (timeout 00:09:40) [common]
  155 23:42:16.761873  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/968618/extract-nfsrootfs-f273ay6n
  156 23:42:16.762516  end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
  157 23:42:16.763893  start: 1.6.2 lava-overlay (timeout 00:09:30) [common]
  158 23:42:16.764617  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9
  159 23:42:16.765094  makedir: /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin
  160 23:42:16.765438  makedir: /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/tests
  161 23:42:16.765761  makedir: /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/results
  162 23:42:16.766575  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-add-keys
  163 23:42:16.767170  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-add-sources
  164 23:42:16.767716  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-background-process-start
  165 23:42:16.768301  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-background-process-stop
  166 23:42:16.768880  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-common-functions
  167 23:42:16.770779  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-echo-ipv4
  168 23:42:16.771360  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-install-packages
  169 23:42:16.771918  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-installed-packages
  170 23:42:16.772530  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-os-build
  171 23:42:16.773147  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-probe-channel
  172 23:42:16.773696  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-probe-ip
  173 23:42:16.774237  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-target-ip
  174 23:42:16.774747  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-target-mac
  175 23:42:16.775264  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-target-storage
  176 23:42:16.775796  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-test-case
  177 23:42:16.776408  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-test-event
  178 23:42:16.776964  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-test-feedback
  179 23:42:16.777492  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-test-raise
  180 23:42:16.778003  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-test-reference
  181 23:42:16.778512  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-test-runner
  182 23:42:16.779038  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-test-set
  183 23:42:16.779553  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-test-shell
  184 23:42:16.780118  Updating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-install-packages (oe)
  185 23:42:16.780750  Updating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/bin/lava-installed-packages (oe)
  186 23:42:16.781244  Creating /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/environment
  187 23:42:16.781664  LAVA metadata
  188 23:42:16.781943  - LAVA_JOB_ID=968618
  189 23:42:16.782170  - LAVA_DISPATCHER_IP=192.168.6.2
  190 23:42:16.782576  start: 1.6.2.1 ssh-authorize (timeout 00:09:30) [common]
  191 23:42:16.783631  end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
  192 23:42:16.784020  start: 1.6.2.2 lava-vland-overlay (timeout 00:09:30) [common]
  193 23:42:16.784258  skipped lava-vland-overlay
  194 23:42:16.784511  end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
  195 23:42:16.784777  start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:30) [common]
  196 23:42:16.785009  skipped lava-multinode-overlay
  197 23:42:16.785260  end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
  198 23:42:16.785517  start: 1.6.2.4 test-definition (timeout 00:09:30) [common]
  199 23:42:16.785785  Loading test definitions
  200 23:42:16.786470  start: 1.6.2.4.1 inline-repo-action (timeout 00:09:30) [common]
  201 23:42:16.786707  Using /lava-968618 at stage 0
  202 23:42:16.789314  uuid=968618_1.6.2.4.1 testdef=None
  203 23:42:16.789706  end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
  204 23:42:16.789985  start: 1.6.2.4.2 test-overlay (timeout 00:09:30) [common]
  205 23:42:16.792443  end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
  207 23:42:16.793294  start: 1.6.2.4.3 test-install-overlay (timeout 00:09:30) [common]
  208 23:42:16.798054  end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
  210 23:42:16.798974  start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:30) [common]
  211 23:42:16.801421  runner path: /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/0/tests/0_dmesg test_uuid 968618_1.6.2.4.1
  212 23:42:16.802082  end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
  214 23:42:16.802885  Creating lava-test-runner.conf files
  215 23:42:16.803090  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/968618/lava-overlay-n4a2pkf9/lava-968618/0 for stage 0
  216 23:42:16.803456  - 0_dmesg
  217 23:42:16.803841  end: 1.6.2.4 test-definition (duration 00:00:00) [common]
  218 23:42:16.804169  start: 1.6.2.5 compress-overlay (timeout 00:09:30) [common]
  219 23:42:16.830229  end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
  220 23:42:16.830703  start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:30) [common]
  221 23:42:16.831018  end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
  222 23:42:16.831313  end: 1.6.2 lava-overlay (duration 00:00:00) [common]
  223 23:42:16.831595  start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:30) [common]
  224 23:42:17.453579  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
  225 23:42:17.454154  start: 1.6.4 extract-modules (timeout 00:09:29) [common]
  226 23:42:17.454457  extracting modules file /var/lib/lava/dispatcher/tmp/968618/tftp-deploy-tq0vpt0w/modules/modules.tar to /var/lib/lava/dispatcher/tmp/968618/extract-nfsrootfs-f273ay6n
  227 23:42:19.133708  extracting modules file /var/lib/lava/dispatcher/tmp/968618/tftp-deploy-tq0vpt0w/modules/modules.tar to /var/lib/lava/dispatcher/tmp/968618/extract-overlay-ramdisk-dbe5eys_/ramdisk
  228 23:42:20.841520  end: 1.6.4 extract-modules (duration 00:00:03) [common]
  229 23:42:20.842013  start: 1.6.5 apply-overlay-tftp (timeout 00:09:26) [common]
  230 23:42:20.842294  [common] Applying overlay to NFS
  231 23:42:20.842511  [common] Applying overlay /var/lib/lava/dispatcher/tmp/968618/compress-overlay-l2aey8s_/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/968618/extract-nfsrootfs-f273ay6n
  232 23:42:20.872417  end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
  233 23:42:20.872858  start: 1.6.6 prepare-kernel (timeout 00:09:26) [common]
  234 23:42:20.873137  start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:26) [common]
  235 23:42:20.873369  Converting downloaded kernel to a uImage
  236 23:42:20.873679  mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/968618/tftp-deploy-tq0vpt0w/kernel/Image /var/lib/lava/dispatcher/tmp/968618/tftp-deploy-tq0vpt0w/kernel/uImage
  237 23:42:22.536768  output: Image Name:   
  238 23:42:22.537193  output: Created:      Sat Nov  9 23:42:20 2024
  239 23:42:22.537420  output: Image Type:   AArch64 Linux Kernel Image (uncompressed)
  240 23:42:22.537624  output: Data Size:    169937408 Bytes = 165954.50 KiB = 162.06 MiB
  241 23:42:22.537826  output: Load Address: 01080000
  242 23:42:22.538024  output: Entry Point:  01080000
  243 23:42:22.538220  output: 
  244 23:42:22.538552  end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
  245 23:42:22.538819  end: 1.6.6 prepare-kernel (duration 00:00:02) [common]
  246 23:42:22.539096  start: 1.6.7 configure-preseed-file (timeout 00:09:24) [common]
  247 23:42:22.539352  end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
  248 23:42:22.539607  start: 1.6.8 compress-ramdisk (timeout 00:09:24) [common]
  249 23:42:22.539865  Building ramdisk /var/lib/lava/dispatcher/tmp/968618/extract-overlay-ramdisk-dbe5eys_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/968618/extract-overlay-ramdisk-dbe5eys_/ramdisk
  250 23:42:27.881138  >> 426772 blocks

  251 23:42:45.591479  Adding RAMdisk u-boot header.
  252 23:42:45.591938  mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/968618/extract-overlay-ramdisk-dbe5eys_/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/968618/extract-overlay-ramdisk-dbe5eys_/ramdisk.cpio.gz.uboot
  253 23:42:46.147572  output: Image Name:   
  254 23:42:46.148061  output: Created:      Sat Nov  9 23:42:45 2024
  255 23:42:46.148499  output: Image Type:   AArch64 Linux RAMDisk Image (uncompressed)
  256 23:42:46.148911  output: Data Size:    50965743 Bytes = 49771.23 KiB = 48.60 MiB
  257 23:42:46.149334  output: Load Address: 00000000
  258 23:42:46.149732  output: Entry Point:  00000000
  259 23:42:46.150126  output: 
  260 23:42:46.151260  rename /var/lib/lava/dispatcher/tmp/968618/extract-overlay-ramdisk-dbe5eys_/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/968618/tftp-deploy-tq0vpt0w/ramdisk/ramdisk.cpio.gz.uboot
  261 23:42:46.152028  end: 1.6.8 compress-ramdisk (duration 00:00:24) [common]
  262 23:42:46.152599  end: 1.6 prepare-tftp-overlay (duration 00:00:39) [common]
  263 23:42:46.153127  start: 1.7 lxc-create-udev-rule-action (timeout 00:09:01) [common]
  264 23:42:46.153583  No LXC device requested
  265 23:42:46.154084  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  266 23:42:46.154591  start: 1.8 deploy-device-env (timeout 00:09:01) [common]
  267 23:42:46.155079  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  268 23:42:46.155487  Checking files for TFTP limit of 4294967296 bytes.
  269 23:42:46.158147  end: 1 tftp-deploy (duration 00:00:59) [common]
  270 23:42:46.158727  start: 2 uboot-action (timeout 00:05:00) [common]
  271 23:42:46.159255  start: 2.1 uboot-from-media (timeout 00:05:00) [common]
  272 23:42:46.159753  end: 2.1 uboot-from-media (duration 00:00:00) [common]
  273 23:42:46.160301  start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
  274 23:42:46.160828  Using kernel file from prepare-kernel: 968618/tftp-deploy-tq0vpt0w/kernel/uImage
  275 23:42:46.161454  substitutions:
  276 23:42:46.161861  - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
  277 23:42:46.162262  - {DTB_ADDR}: 0x01070000
  278 23:42:46.162659  - {DTB}: 968618/tftp-deploy-tq0vpt0w/dtb/meson-g12b-a311d-libretech-cc.dtb
  279 23:42:46.163055  - {INITRD}: 968618/tftp-deploy-tq0vpt0w/ramdisk/ramdisk.cpio.gz.uboot
  280 23:42:46.163450  - {KERNEL_ADDR}: 0x01080000
  281 23:42:46.163842  - {KERNEL}: 968618/tftp-deploy-tq0vpt0w/kernel/uImage
  282 23:42:46.164264  - {LAVA_MAC}: None
  283 23:42:46.164697  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/968618/extract-nfsrootfs-f273ay6n
  284 23:42:46.165094  - {NFS_SERVER_IP}: 192.168.6.2
  285 23:42:46.165481  - {PRESEED_CONFIG}: None
  286 23:42:46.165870  - {PRESEED_LOCAL}: None
  287 23:42:46.166257  - {RAMDISK_ADDR}: 0x08000000
  288 23:42:46.166642  - {RAMDISK}: 968618/tftp-deploy-tq0vpt0w/ramdisk/ramdisk.cpio.gz.uboot
  289 23:42:46.167029  - {ROOT_PART}: None
  290 23:42:46.167415  - {ROOT}: None
  291 23:42:46.167799  - {SERVER_IP}: 192.168.6.2
  292 23:42:46.168212  - {TEE_ADDR}: 0x83000000
  293 23:42:46.168599  - {TEE}: None
  294 23:42:46.168985  Parsed boot commands:
  295 23:42:46.169361  - setenv autoload no
  296 23:42:46.169748  - setenv initrd_high 0xffffffff
  297 23:42:46.170130  - setenv fdt_high 0xffffffff
  298 23:42:46.170513  - dhcp
  299 23:42:46.170894  - setenv serverip 192.168.6.2
  300 23:42:46.171278  - tftpboot 0x01080000 968618/tftp-deploy-tq0vpt0w/kernel/uImage
  301 23:42:46.171663  - tftpboot 0x08000000 968618/tftp-deploy-tq0vpt0w/ramdisk/ramdisk.cpio.gz.uboot
  302 23:42:46.172071  - tftpboot 0x01070000 968618/tftp-deploy-tq0vpt0w/dtb/meson-g12b-a311d-libretech-cc.dtb
  303 23:42:46.172458  - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/968618/extract-nfsrootfs-f273ay6n,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  304 23:42:46.172855  - bootm 0x01080000 0x08000000 0x01070000
  305 23:42:46.173349  end: 2.2 bootloader-overlay (duration 00:00:00) [common]
  307 23:42:46.174829  start: 2.3 connect-device (timeout 00:05:00) [common]
  308 23:42:46.175246  [common] connect-device Connecting to device using 'telnet conserv1 3007'
  309 23:42:46.191115  Setting prompt string to ['lava-test: # ']
  310 23:42:46.192655  end: 2.3 connect-device (duration 00:00:00) [common]
  311 23:42:46.193252  start: 2.4 uboot-commands (timeout 00:05:00) [common]
  312 23:42:46.193795  start: 2.4.1 reset-device (timeout 00:05:00) [common]
  313 23:42:46.194314  start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
  314 23:42:46.195436  Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
  315 23:42:46.232345  >> OK - accepted request

  316 23:42:46.234700  Returned 0 in 0 seconds
  317 23:42:46.335803  end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
  319 23:42:46.337493  end: 2.4.1 reset-device (duration 00:00:00) [common]
  320 23:42:46.338077  start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
  321 23:42:46.338583  Setting prompt string to ['Hit any key to stop autoboot']
  322 23:42:46.339039  bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
  323 23:42:46.340616  Trying 192.168.56.21...
  324 23:42:46.341097  Connected to conserv1.
  325 23:42:46.341512  Escape character is '^]'.
  326 23:42:46.341927  
  327 23:42:46.342349  ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
  328 23:42:46.342764  
  329 23:42:57.752344  G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  330 23:42:57.752757  bl2_stage_init 0x01
  331 23:42:57.752974  bl2_stage_init 0x81
  332 23:42:57.757823  hw id: 0x0000 - pwm id 0x01
  333 23:42:57.758131  bl2_stage_init 0xc1
  334 23:42:57.758336  bl2_stage_init 0x02
  335 23:42:57.758534  
  336 23:42:57.763374  L0:00000000
  337 23:42:57.763654  L1:20000703
  338 23:42:57.763879  L2:00008067
  339 23:42:57.764120  L3:14000000
  340 23:42:57.766279  B2:00402000
  341 23:42:57.766537  B1:e0f83180
  342 23:42:57.766738  
  343 23:42:57.766943  TE: 58167
  344 23:42:57.767154  
  345 23:42:57.777519  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  346 23:42:57.777802  
  347 23:42:57.778010  Board ID = 1
  348 23:42:57.778211  Set A53 clk to 24M
  349 23:42:57.778408  Set A73 clk to 24M
  350 23:42:57.783147  Set clk81 to 24M
  351 23:42:57.783643  A53 clk: 1200 MHz
  352 23:42:57.784089  A73 clk: 1200 MHz
  353 23:42:57.788720  CLK81: 166.6M
  354 23:42:57.789193  smccc: 00012abe
  355 23:42:57.794238  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  356 23:42:57.794710  board id: 1
  357 23:42:57.802859  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  358 23:42:57.813468  fw parse done
  359 23:42:57.819541  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  360 23:42:57.862061  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
  361 23:42:57.872971  PIEI prepare done
  362 23:42:57.873484  fastboot data load
  363 23:42:57.873891  fastboot data verify
  364 23:42:57.878672  verify result: 266
  365 23:42:57.884271  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
  366 23:42:57.884784  LPDDR4 probe
  367 23:42:57.885189  ddr clk to 1584MHz
  368 23:42:57.892223  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
  369 23:42:57.929512  
  370 23:42:57.930049  dmc_version 0001
  371 23:42:57.936189  Check phy result
  372 23:42:57.942020  INFO : End of CA training
  373 23:42:57.942518  INFO : End of initialization
  374 23:42:57.947613  INFO : Training has run successfully!
  375 23:42:57.948151  Check phy result
  376 23:42:57.953252  INFO : End of initialization
  377 23:42:57.953747  INFO : End of read enable training
  378 23:42:57.956489  INFO : End of fine write leveling
  379 23:42:57.962024  INFO : End of Write leveling coarse delay
  380 23:42:57.967618  INFO : Training has run successfully!
  381 23:42:57.968135  Check phy result
  382 23:42:57.968541  INFO : End of initialization
  383 23:42:57.973230  INFO : End of read dq deskew training
  384 23:42:57.978885  INFO : End of MPR read delay center optimization
  385 23:42:57.979397  INFO : End of write delay center optimization
  386 23:42:57.984483  INFO : End of read delay center optimization
  387 23:42:57.990028  INFO : End of max read latency training
  388 23:42:57.990634  INFO : Training has run successfully!
  389 23:42:57.995626  1D training succeed
  390 23:42:58.001589  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
  391 23:42:58.049119  Check phy result
  392 23:42:58.049670  INFO : End of initialization
  393 23:42:58.070778  INFO : End of 2D read delay Voltage center optimization
  394 23:42:58.090872  INFO : End of 2D read delay Voltage center optimization
  395 23:42:58.142864  INFO : End of 2D write delay Voltage center optimization
  396 23:42:58.191974  INFO : End of 2D write delay Voltage center optimization
  397 23:42:58.197643  INFO : Training has run successfully!
  398 23:42:58.198135  
  399 23:42:58.198542  channel==0
  400 23:42:58.203213  RxClkDly_Margin_A0==88 ps 9
  401 23:42:58.203702  TxDqDly_Margin_A0==98 ps 10
  402 23:42:58.206515  RxClkDly_Margin_A1==88 ps 9
  403 23:42:58.207004  TxDqDly_Margin_A1==98 ps 10
  404 23:42:58.212075  TrainedVREFDQ_A0==74
  405 23:42:58.212586  TrainedVREFDQ_A1==74
  406 23:42:58.217670  VrefDac_Margin_A0==25
  407 23:42:58.218158  DeviceVref_Margin_A0==40
  408 23:42:58.218555  VrefDac_Margin_A1==25
  409 23:42:58.223349  DeviceVref_Margin_A1==40
  410 23:42:58.223836  
  411 23:42:58.224278  
  412 23:42:58.224677  channel==1
  413 23:42:58.225067  RxClkDly_Margin_A0==98 ps 10
  414 23:42:58.228968  TxDqDly_Margin_A0==98 ps 10
  415 23:42:58.229515  RxClkDly_Margin_A1==98 ps 10
  416 23:42:58.234553  TxDqDly_Margin_A1==88 ps 9
  417 23:42:58.235103  TrainedVREFDQ_A0==77
  418 23:42:58.235511  TrainedVREFDQ_A1==77
  419 23:42:58.240135  VrefDac_Margin_A0==22
  420 23:42:58.240692  DeviceVref_Margin_A0==37
  421 23:42:58.245851  VrefDac_Margin_A1==22
  422 23:42:58.246450  DeviceVref_Margin_A1==37
  423 23:42:58.246854  
  424 23:42:58.251456   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
  425 23:42:58.252033  
  426 23:42:58.279454  soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
  427 23:42:58.285062  2D training succeed
  428 23:42:58.290591  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  429 23:42:58.292248  auto size-- 65535DDR cs0 size: 2048MB
  430 23:42:58.296135  DDR cs1 size: 2048MB
  431 23:42:58.296705  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  432 23:42:58.301568  cs0 DataBus test pass
  433 23:42:58.302086  cs1 DataBus test pass
  434 23:42:58.302498  cs0 AddrBus test pass
  435 23:42:58.307125  cs1 AddrBus test pass
  436 23:42:58.307635  
  437 23:42:58.308141  100bdlr_step_size ps== 420
  438 23:42:58.308576  result report
  439 23:42:58.312761  boot times 0Enable ddr reg access
  440 23:42:58.320546  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
  441 23:42:58.334036  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
  442 23:42:58.905991  0.0;M3 CHK:0;cm4_sp_mode 0
  443 23:42:58.906622  MVN_1=0x00000000
  444 23:42:58.911417  MVN_2=0x00000000
  445 23:42:58.917222  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  446 23:42:58.917673  OPS=0x10
  447 23:42:58.918077  ring efuse init
  448 23:42:58.918469  chipver efuse init
  449 23:42:58.922758  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
  450 23:42:58.928344  [0.018961 Inits done]
  451 23:42:58.928786  secure task start!
  452 23:42:58.929184  high task start!
  453 23:42:58.932978  low task start!
  454 23:42:58.933479  run into bl31
  455 23:42:58.939612  NOTICE:  BL31: v1.3(release):4fc40b1
  456 23:42:58.947426  NOTICE:  BL31: Built : 15:58:17, May 22 2019
  457 23:42:58.947884  NOTICE:  BL31: G12A normal boot!
  458 23:42:58.972763  NOTICE:  BL31: BL33 decompress pass
  459 23:42:58.978436  ERROR:   Error initializing runtime service opteed_fast
  460 23:43:00.211325  
  461 23:43:00.211962  
  462 23:43:00.219685  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
  463 23:43:00.220186  
  464 23:43:00.220611  Model: Libre Computer AML-A311D-CC Alta
  465 23:43:00.428191  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
  466 23:43:00.451598  DRAM:  2 GiB (effective 3.8 GiB)
  467 23:43:00.594682  Core:  408 devices, 31 uclasses, devicetree: separate
  468 23:43:00.600555  WDT:   Not starting watchdog@f0d0
  469 23:43:00.632802  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
  470 23:43:00.645231  Loading Environment from FAT... Card did not respond to voltage select! : -110
  471 23:43:00.650248  ** Bad device specification mmc 0 **
  472 23:43:00.660596  Card did not respond to voltage select! : -110
  473 23:43:00.668226  ** Bad device specification mmc 0 **
  474 23:43:00.668703  Couldn't find partition mmc 0
  475 23:43:00.676595  Card did not respond to voltage select! : -110
  476 23:43:00.682094  ** Bad device specification mmc 0 **
  477 23:43:00.682571  Couldn't find partition mmc 0
  478 23:43:00.687138  Error: could not access storage.
  479 23:43:01.952732  G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  480 23:43:01.953363  bl2_stage_init 0x01
  481 23:43:01.953793  bl2_stage_init 0x81
  482 23:43:01.958296  hw id: 0x0000 - pwm id 0x01
  483 23:43:01.958768  bl2_stage_init 0xc1
  484 23:43:01.959182  bl2_stage_init 0x02
  485 23:43:01.959584  
  486 23:43:01.963878  L0:00000000
  487 23:43:01.964375  L1:20000703
  488 23:43:01.964789  L2:00008067
  489 23:43:01.965190  L3:14000000
  490 23:43:01.966774  B2:00402000
  491 23:43:01.967241  B1:e0f83180
  492 23:43:01.967646  
  493 23:43:01.968077  TE: 58159
  494 23:43:01.968484  
  495 23:43:01.977892  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  496 23:43:01.978383  
  497 23:43:01.978798  Board ID = 1
  498 23:43:01.979197  Set A53 clk to 24M
  499 23:43:01.979593  Set A73 clk to 24M
  500 23:43:01.983621  Set clk81 to 24M
  501 23:43:01.984109  A53 clk: 1200 MHz
  502 23:43:01.984522  A73 clk: 1200 MHz
  503 23:43:01.989146  CLK81: 166.6M
  504 23:43:01.989611  smccc: 00012ab5
  505 23:43:01.994739  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  506 23:43:01.995195  board id: 1
  507 23:43:02.003352  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  508 23:43:02.013998  fw parse done
  509 23:43:02.020008  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  510 23:43:02.062584  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
  511 23:43:02.073527  PIEI prepare done
  512 23:43:02.073991  fastboot data load
  513 23:43:02.074407  fastboot data verify
  514 23:43:02.079096  verify result: 266
  515 23:43:02.084761  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
  516 23:43:02.085222  LPDDR4 probe
  517 23:43:02.085630  ddr clk to 1584MHz
  518 23:43:02.092721  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
  519 23:43:02.129924  
  520 23:43:02.130389  dmc_version 0001
  521 23:43:02.136609  Check phy result
  522 23:43:02.142482  INFO : End of CA training
  523 23:43:02.142935  INFO : End of initialization
  524 23:43:02.148109  INFO : Training has run successfully!
  525 23:43:02.148572  Check phy result
  526 23:43:02.153800  INFO : End of initialization
  527 23:43:02.154268  INFO : End of read enable training
  528 23:43:02.159280  INFO : End of fine write leveling
  529 23:43:02.164901  INFO : End of Write leveling coarse delay
  530 23:43:02.165361  INFO : Training has run successfully!
  531 23:43:02.165769  Check phy result
  532 23:43:02.170495  INFO : End of initialization
  533 23:43:02.170949  INFO : End of read dq deskew training
  534 23:43:02.176110  INFO : End of MPR read delay center optimization
  535 23:43:02.181774  INFO : End of write delay center optimization
  536 23:43:02.187282  INFO : End of read delay center optimization
  537 23:43:02.187735  INFO : End of max read latency training
  538 23:43:02.192902  INFO : Training has run successfully!
  539 23:43:02.193356  1D training succeed
  540 23:43:02.202060  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
  541 23:43:02.249667  Check phy result
  542 23:43:02.250148  INFO : End of initialization
  543 23:43:02.271482  INFO : End of 2D read delay Voltage center optimization
  544 23:43:02.291662  INFO : End of 2D read delay Voltage center optimization
  545 23:43:02.343805  INFO : End of 2D write delay Voltage center optimization
  546 23:43:02.393153  INFO : End of 2D write delay Voltage center optimization
  547 23:43:02.398699  INFO : Training has run successfully!
  548 23:43:02.399171  
  549 23:43:02.399609  channel==0
  550 23:43:02.404286  RxClkDly_Margin_A0==78 ps 8
  551 23:43:02.404765  TxDqDly_Margin_A0==98 ps 10
  552 23:43:02.409895  RxClkDly_Margin_A1==88 ps 9
  553 23:43:02.410427  TxDqDly_Margin_A1==98 ps 10
  554 23:43:02.410860  TrainedVREFDQ_A0==74
  555 23:43:02.416444  TrainedVREFDQ_A1==74
  556 23:43:02.417014  VrefDac_Margin_A0==25
  557 23:43:02.417445  DeviceVref_Margin_A0==40
  558 23:43:02.421098  VrefDac_Margin_A1==25
  559 23:43:02.421574  DeviceVref_Margin_A1==40
  560 23:43:02.421994  
  561 23:43:02.422403  
  562 23:43:02.426721  channel==1
  563 23:43:02.427183  RxClkDly_Margin_A0==98 ps 10
  564 23:43:02.427594  TxDqDly_Margin_A0==98 ps 10
  565 23:43:02.432257  RxClkDly_Margin_A1==98 ps 10
  566 23:43:02.432723  TxDqDly_Margin_A1==88 ps 9
  567 23:43:02.437840  TrainedVREFDQ_A0==77
  568 23:43:02.438309  TrainedVREFDQ_A1==77
  569 23:43:02.438726  VrefDac_Margin_A0==22
  570 23:43:02.443446  DeviceVref_Margin_A0==37
  571 23:43:02.443911  VrefDac_Margin_A1==22
  572 23:43:02.449048  DeviceVref_Margin_A1==37
  573 23:43:02.449513  
  574 23:43:02.449927   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
  575 23:43:02.454703  
  576 23:43:02.482568  soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000017 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
  577 23:43:02.483079  2D training succeed
  578 23:43:02.488262  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  579 23:43:02.493826  auto size-- 65535DDR cs0 size: 2048MB
  580 23:43:02.494302  DDR cs1 size: 2048MB
  581 23:43:02.499401  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  582 23:43:02.499732  cs0 DataBus test pass
  583 23:43:02.505000  cs1 DataBus test pass
  584 23:43:02.505463  cs0 AddrBus test pass
  585 23:43:02.505839  cs1 AddrBus test pass
  586 23:43:02.506212  
  587 23:43:02.510589  100bdlr_step_size ps== 420
  588 23:43:02.510919  result report
  589 23:43:02.516213  boot times 0Enable ddr reg access
  590 23:43:02.521628  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
  591 23:43:02.535145  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
  592 23:43:03.108869  0.0;M3 CHK:0;cm4_sp_mode 0
  593 23:43:03.109501  MVN_1=0x00000000
  594 23:43:03.114293  MVN_2=0x00000000
  595 23:43:03.120110  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  596 23:43:03.120640  OPS=0x10
  597 23:43:03.121102  ring efuse init
  598 23:43:03.121507  chipver efuse init
  599 23:43:03.125714  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
  600 23:43:03.131208  [0.018961 Inits done]
  601 23:43:03.131673  secure task start!
  602 23:43:03.132105  high task start!
  603 23:43:03.135868  low task start!
  604 23:43:03.136363  run into bl31
  605 23:43:03.142482  NOTICE:  BL31: v1.3(release):4fc40b1
  606 23:43:03.150251  NOTICE:  BL31: Built : 15:58:17, May 22 2019
  607 23:43:03.150704  NOTICE:  BL31: G12A normal boot!
  608 23:43:03.175717  NOTICE:  BL31: BL33 decompress pass
  609 23:43:03.181327  ERROR:   Error initializing runtime service opteed_fast
  610 23:43:04.416248  
  611 23:43:04.416934  
  612 23:43:04.423018  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
  613 23:43:04.423498  
  614 23:43:04.423918  Model: Libre Computer AML-A311D-CC Alta
  615 23:43:04.631470  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
  616 23:43:04.654724  DRAM:  2 GiB (effective 3.8 GiB)
  617 23:43:04.797631  Core:  408 devices, 31 uclasses, devicetree: separate
  618 23:43:04.803557  WDT:   Not starting watchdog@f0d0
  619 23:43:04.835755  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
  620 23:43:04.848177  Loading Environment from FAT... Card did not respond to voltage select! : -110
  621 23:43:04.853295  ** Bad device specification mmc 0 **
  622 23:43:04.863518  Card did not respond to voltage select! : -110
  623 23:43:04.871330  ** Bad device specification mmc 0 **
  624 23:43:04.871777  Couldn't find partition mmc 0
  625 23:43:04.879469  Card did not respond to voltage select! : -110
  626 23:43:04.884990  ** Bad device specification mmc 0 **
  627 23:43:04.885435  Couldn't find partition mmc 0
  628 23:43:04.890191  Error: could not access storage.
  629 23:43:05.232677  Net:   eth0: ethernet@ff3f0000
  630 23:43:05.233196  starting USB...
  631 23:43:05.484694  Bus usb@ff500000: Register 3000140 NbrPorts 3
  632 23:43:05.485308  Starting the controller
  633 23:43:05.491467  USB XHCI 1.10
  634 23:43:07.202786  scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  635 23:43:07.203429  bl2_stage_init 0x01
  636 23:43:07.203865  bl2_stage_init 0x81
  637 23:43:07.208527  hw id: 0x0000 - pwm id 0x01
  638 23:43:07.208987  bl2_stage_init 0xc1
  639 23:43:07.209402  bl2_stage_init 0x02
  640 23:43:07.209805  
  641 23:43:07.213887  L0:00000000
  642 23:43:07.214329  L1:20000703
  643 23:43:07.214740  L2:00008067
  644 23:43:07.215142  L3:14000000
  645 23:43:07.219533  B2:00402000
  646 23:43:07.219970  B1:e0f83180
  647 23:43:07.220419  
  648 23:43:07.220823  TE: 58124
  649 23:43:07.221224  
  650 23:43:07.225072  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  651 23:43:07.225518  
  652 23:43:07.225926  Board ID = 1
  653 23:43:07.230838  Set A53 clk to 24M
  654 23:43:07.231270  Set A73 clk to 24M
  655 23:43:07.231675  Set clk81 to 24M
  656 23:43:07.236412  A53 clk: 1200 MHz
  657 23:43:07.236854  A73 clk: 1200 MHz
  658 23:43:07.237259  CLK81: 166.6M
  659 23:43:07.237658  smccc: 00012a91
  660 23:43:07.241853  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  661 23:43:07.247569  board id: 1
  662 23:43:07.253532  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  663 23:43:07.264093  fw parse done
  664 23:43:07.270048  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  665 23:43:07.313334  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
  666 23:43:07.323529  PIEI prepare done
  667 23:43:07.323973  fastboot data load
  668 23:43:07.324458  fastboot data verify
  669 23:43:07.329306  verify result: 266
  670 23:43:07.334860  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
  671 23:43:07.335583  LPDDR4 probe
  672 23:43:07.336204  ddr clk to 1584MHz
  673 23:43:07.342860  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
  674 23:43:07.380290  
  675 23:43:07.380869  dmc_version 0001
  676 23:43:07.386732  Check phy result
  677 23:43:07.392648  INFO : End of CA training
  678 23:43:07.393322  INFO : End of initialization
  679 23:43:07.398226  INFO : Training has run successfully!
  680 23:43:07.398908  Check phy result
  681 23:43:07.403846  INFO : End of initialization
  682 23:43:07.404557  INFO : End of read enable training
  683 23:43:07.409506  INFO : End of fine write leveling
  684 23:43:07.415089  INFO : End of Write leveling coarse delay
  685 23:43:07.415704  INFO : Training has run successfully!
  686 23:43:07.416248  Check phy result
  687 23:43:07.420631  INFO : End of initialization
  688 23:43:07.421165  INFO : End of read dq deskew training
  689 23:43:07.426204  INFO : End of MPR read delay center optimization
  690 23:43:07.431836  INFO : End of write delay center optimization
  691 23:43:07.437429  INFO : End of read delay center optimization
  692 23:43:07.437954  INFO : End of max read latency training
  693 23:43:07.443001  INFO : Training has run successfully!
  694 23:43:07.443515  1D training succeed
  695 23:43:07.452140  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
  696 23:43:07.499815  Check phy result
  697 23:43:07.500394  INFO : End of initialization
  698 23:43:07.521404  INFO : End of 2D read delay Voltage center optimization
  699 23:43:07.541565  INFO : End of 2D read delay Voltage center optimization
  700 23:43:07.593460  INFO : End of 2D write delay Voltage center optimization
  701 23:43:07.642642  INFO : End of 2D write delay Voltage center optimization
  702 23:43:07.648233  INFO : Training has run successfully!
  703 23:43:07.648756  
  704 23:43:07.649188  channel==0
  705 23:43:07.653770  RxClkDly_Margin_A0==88 ps 9
  706 23:43:07.654301  TxDqDly_Margin_A0==98 ps 10
  707 23:43:07.657093  RxClkDly_Margin_A1==88 ps 9
  708 23:43:07.657604  TxDqDly_Margin_A1==98 ps 10
  709 23:43:07.662736  TrainedVREFDQ_A0==74
  710 23:43:07.663250  TrainedVREFDQ_A1==74
  711 23:43:07.663674  VrefDac_Margin_A0==25
  712 23:43:07.668398  DeviceVref_Margin_A0==40
  713 23:43:07.668901  VrefDac_Margin_A1==24
  714 23:43:07.673897  DeviceVref_Margin_A1==40
  715 23:43:07.674390  
  716 23:43:07.674811  
  717 23:43:07.675218  channel==1
  718 23:43:07.675620  RxClkDly_Margin_A0==98 ps 10
  719 23:43:07.679680  TxDqDly_Margin_A0==98 ps 10
  720 23:43:07.680342  RxClkDly_Margin_A1==98 ps 10
  721 23:43:07.685039  TxDqDly_Margin_A1==88 ps 9
  722 23:43:07.685568  TrainedVREFDQ_A0==77
  723 23:43:07.686044  TrainedVREFDQ_A1==77
  724 23:43:07.690651  VrefDac_Margin_A0==23
  725 23:43:07.691165  DeviceVref_Margin_A0==37
  726 23:43:07.696240  VrefDac_Margin_A1==22
  727 23:43:07.696750  DeviceVref_Margin_A1==37
  728 23:43:07.697218  
  729 23:43:07.701822   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
  730 23:43:07.702333  
  731 23:43:07.729809  soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
  732 23:43:07.735516  2D training succeed
  733 23:43:07.741024  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  734 23:43:07.741558  auto size-- 65535DDR cs0 size: 2048MB
  735 23:43:07.746633  DDR cs1 size: 2048MB
  736 23:43:07.747155  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  737 23:43:07.752250  cs0 DataBus test pass
  738 23:43:07.752773  cs1 DataBus test pass
  739 23:43:07.753234  cs0 AddrBus test pass
  740 23:43:07.757809  cs1 AddrBus test pass
  741 23:43:07.758321  
  742 23:43:07.758790  100bdlr_step_size ps== 420
  743 23:43:07.759252  result report
  744 23:43:07.763534  boot times 0Enable ddr reg access
  745 23:43:07.771195  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
  746 23:43:07.784589  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
  747 23:43:08.356731  0.0;M3 CHK:0;cm4_sp_mode 0
  748 23:43:08.357373  MVN_1=0x00000000
  749 23:43:08.362084  MVN_2=0x00000000
  750 23:43:08.367862  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  751 23:43:08.368536  OPS=0x10
  752 23:43:08.368985  ring efuse init
  753 23:43:08.369414  chipver efuse init
  754 23:43:08.373445  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
  755 23:43:08.379024  [0.018961 Inits done]
  756 23:43:08.379528  secure task start!
  757 23:43:08.379966  high task start!
  758 23:43:08.383582  low task start!
  759 23:43:08.384100  run into bl31
  760 23:43:08.390286  NOTICE:  BL31: v1.3(release):4fc40b1
  761 23:43:08.398041  NOTICE:  BL31: Built : 15:58:17, May 22 2019
  762 23:43:08.398534  NOTICE:  BL31: G12A normal boot!
  763 23:43:08.423657  NOTICE:  BL31: BL33 decompress pass
  764 23:43:08.429239  ERROR:   Error initializing runtime service opteed_fast
  765 23:43:09.662271  
  766 23:43:09.663079  
  767 23:43:09.670607  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
  768 23:43:09.671272  
  769 23:43:09.671822  Model: Libre Computer AML-A311D-CC Alta
  770 23:43:09.879153  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
  771 23:43:09.902476  DRAM:  2 GiB (effective 3.8 GiB)
  772 23:43:10.045475  Core:  408 devices, 31 uclasses, devicetree: separate
  773 23:43:10.051271  WDT:   Not starting watchdog@f0d0
  774 23:43:10.083580  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
  775 23:43:10.095975  Loading Environment from FAT... Card did not respond to voltage select! : -110
  776 23:43:10.100992  ** Bad device specification mmc 0 **
  777 23:43:10.111323  Card did not respond to voltage select! : -110
  778 23:43:10.118997  ** Bad device specification mmc 0 **
  779 23:43:10.119627  Couldn't find partition mmc 0
  780 23:43:10.127314  Card did not respond to voltage select! : -110
  781 23:43:10.132860  ** Bad device specification mmc 0 **
  782 23:43:10.133488  Couldn't find partition mmc 0
  783 23:43:10.137964  Error: could not access storage.
  784 23:43:10.480380  Net:   eth0: ethernet@ff3f0000
  785 23:43:10.481157  starting USB...
  786 23:43:10.732222  Bus usb@ff500000: Register 3000140 NbrPorts 3
  787 23:43:10.733007  Starting the controller
  788 23:43:10.739120  USB XHCI 1.10
  789 23:43:12.904692  scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
  790 23:43:12.905543  bl2_stage_init 0x81
  791 23:43:12.910052  hw id: 0x0000 - pwm id 0x01
  792 23:43:12.910685  bl2_stage_init 0xc1
  793 23:43:12.911238  bl2_stage_init 0x02
  794 23:43:12.911778  
  795 23:43:12.915618  L0:00000000
  796 23:43:12.916257  L1:20000703
  797 23:43:12.916791  L2:00008067
  798 23:43:12.917321  L3:14000000
  799 23:43:12.917837  B2:00402000
  800 23:43:12.918766  B1:e0f83180
  801 23:43:12.919235  
  802 23:43:12.919656  TE: 58150
  803 23:43:12.920103  
  804 23:43:12.929642  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  805 23:43:12.930147  
  806 23:43:12.930565  Board ID = 1
  807 23:43:12.930966  Set A53 clk to 24M
  808 23:43:12.931369  Set A73 clk to 24M
  809 23:43:12.935368  Set clk81 to 24M
  810 23:43:12.935841  A53 clk: 1200 MHz
  811 23:43:12.936287  A73 clk: 1200 MHz
  812 23:43:12.938777  CLK81: 166.6M
  813 23:43:12.939237  smccc: 00012aac
  814 23:43:12.944412  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  815 23:43:12.949961  board id: 1
  816 23:43:12.955182  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  817 23:43:12.965668  fw parse done
  818 23:43:12.971625  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  819 23:43:13.014289  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
  820 23:43:13.025191  PIEI prepare done
  821 23:43:13.025705  fastboot data load
  822 23:43:13.026123  fastboot data verify
  823 23:43:13.030740  verify result: 266
  824 23:43:13.036408  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
  825 23:43:13.036892  LPDDR4 probe
  826 23:43:13.037307  ddr clk to 1584MHz
  827 23:43:13.044378  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
  828 23:43:13.081599  
  829 23:43:13.082111  dmc_version 0001
  830 23:43:13.088271  Check phy result
  831 23:43:13.094106  INFO : End of CA training
  832 23:43:13.094571  INFO : End of initialization
  833 23:43:13.099623  INFO : Training has run successfully!
  834 23:43:13.100121  Check phy result
  835 23:43:13.105331  INFO : End of initialization
  836 23:43:13.105791  INFO : End of read enable training
  837 23:43:13.108592  INFO : End of fine write leveling
  838 23:43:13.114121  INFO : End of Write leveling coarse delay
  839 23:43:13.119742  INFO : Training has run successfully!
  840 23:43:13.120244  Check phy result
  841 23:43:13.120658  INFO : End of initialization
  842 23:43:13.125352  INFO : End of read dq deskew training
  843 23:43:13.128782  INFO : End of MPR read delay center optimization
  844 23:43:13.134398  INFO : End of write delay center optimization
  845 23:43:13.139999  INFO : End of read delay center optimization
  846 23:43:13.140470  INFO : End of max read latency training
  847 23:43:13.145588  INFO : Training has run successfully!
  848 23:43:13.146055  1D training succeed
  849 23:43:13.153769  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
  850 23:43:13.201255  Check phy result
  851 23:43:13.201773  INFO : End of initialization
  852 23:43:13.223023  INFO : End of 2D read delay Voltage center optimization
  853 23:43:13.243319  INFO : End of 2D read delay Voltage center optimization
  854 23:43:13.295373  INFO : End of 2D write delay Voltage center optimization
  855 23:43:13.344803  INFO : End of 2D write delay Voltage center optimization
  856 23:43:13.350485  INFO : Training has run successfully!
  857 23:43:13.351052  
  858 23:43:13.351486  channel==0
  859 23:43:13.356067  RxClkDly_Margin_A0==88 ps 9
  860 23:43:13.356662  TxDqDly_Margin_A0==98 ps 10
  861 23:43:13.361543  RxClkDly_Margin_A1==88 ps 9
  862 23:43:13.362074  TxDqDly_Margin_A1==98 ps 10
  863 23:43:13.362511  TrainedVREFDQ_A0==74
  864 23:43:13.367193  TrainedVREFDQ_A1==74
  865 23:43:13.367764  VrefDac_Margin_A0==25
  866 23:43:13.368212  DeviceVref_Margin_A0==40
  867 23:43:13.372777  VrefDac_Margin_A1==25
  868 23:43:13.373335  DeviceVref_Margin_A1==40
  869 23:43:13.373725  
  870 23:43:13.374113  
  871 23:43:13.378471  channel==1
  872 23:43:13.378969  RxClkDly_Margin_A0==98 ps 10
  873 23:43:13.379365  TxDqDly_Margin_A0==88 ps 9
  874 23:43:13.383966  RxClkDly_Margin_A1==98 ps 10
  875 23:43:13.384472  TxDqDly_Margin_A1==88 ps 9
  876 23:43:13.389494  TrainedVREFDQ_A0==76
  877 23:43:13.389953  TrainedVREFDQ_A1==77
  878 23:43:13.390348  VrefDac_Margin_A0==22
  879 23:43:13.395091  DeviceVref_Margin_A0==38
  880 23:43:13.395537  VrefDac_Margin_A1==22
  881 23:43:13.400609  DeviceVref_Margin_A1==37
  882 23:43:13.401060  
  883 23:43:13.401455   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
  884 23:43:13.401844  
  885 23:43:13.434207  soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
  886 23:43:13.434761  2D training succeed
  887 23:43:13.439871  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  888 23:43:13.445419  auto size-- 65535DDR cs0 size: 2048MB
  889 23:43:13.445875  DDR cs1 size: 2048MB
  890 23:43:13.451022  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  891 23:43:13.451468  cs0 DataBus test pass
  892 23:43:13.456655  cs1 DataBus test pass
  893 23:43:13.457115  cs0 AddrBus test pass
  894 23:43:13.457510  cs1 AddrBus test pass
  895 23:43:13.457896  
  896 23:43:13.462222  100bdlr_step_size ps== 420
  897 23:43:13.462679  result report
  898 23:43:13.467831  boot times 0Enable ddr reg access
  899 23:43:13.473194  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
  900 23:43:13.486621  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
  901 23:43:14.059753  0.0;M3 CHK:0;cm4_sp_mode 0
  902 23:43:14.060422  MVN_1=0x00000000
  903 23:43:14.065201  MVN_2=0x00000000
  904 23:43:14.071067  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  905 23:43:14.071542  OPS=0x10
  906 23:43:14.071957  ring efuse init
  907 23:43:14.072397  chipver efuse init
  908 23:43:14.079257  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
  909 23:43:14.079740  [0.018961 Inits done]
  910 23:43:14.085967  secure task start!
  911 23:43:14.086430  high task start!
  912 23:43:14.086835  low task start!
  913 23:43:14.087233  run into bl31
  914 23:43:14.093394  NOTICE:  BL31: v1.3(release):4fc40b1
  915 23:43:14.100405  NOTICE:  BL31: Built : 15:58:17, May 22 2019
  916 23:43:14.100893  NOTICE:  BL31: G12A normal boot!
  917 23:43:14.126715  NOTICE:  BL31: BL33 decompress pass
  918 23:43:14.131326  ERROR:   Error initializing runtime service opteed_fast
  919 23:43:15.365045  
  920 23:43:15.365673  
  921 23:43:15.373519  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
  922 23:43:15.374008  
  923 23:43:15.374424  Model: Libre Computer AML-A311D-CC Alta
  924 23:43:15.581909  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
  925 23:43:15.605248  DRAM:  2 GiB (effective 3.8 GiB)
  926 23:43:15.748327  Core:  408 devices, 31 uclasses, devicetree: separate
  927 23:43:15.754119  WDT:   Not starting watchdog@f0d0
  928 23:43:15.786506  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
  929 23:43:15.798915  Loading Environment from FAT... Card did not respond to voltage select! : -110
  930 23:43:15.803903  ** Bad device specification mmc 0 **
  931 23:43:15.814215  Card did not respond to voltage select! : -110
  932 23:43:15.821910  ** Bad device specification mmc 0 **
  933 23:43:15.822414  Couldn't find partition mmc 0
  934 23:43:15.830219  Card did not respond to voltage select! : -110
  935 23:43:15.835754  ** Bad device specification mmc 0 **
  936 23:43:15.836277  Couldn't find partition mmc 0
  937 23:43:15.840865  Error: could not access storage.
  938 23:43:16.183244  Net:   eth0: ethernet@ff3f0000
  939 23:43:16.183848  starting USB...
  940 23:43:16.435083  Bus usb@ff500000: Register 3000140 NbrPorts 3
  941 23:43:16.435676  Starting the controller
  942 23:43:16.442026  USB XHCI 1.10
  943 23:43:17.998022  scanning bus usb@ff500000 for devices... 3 USB Device(s) found
  944 23:43:18.006368         scanning usb for storage devices... 0 Storage Device(s) found
  946 23:43:18.057951  Hit any key to stop autoboot:  1 
  947 23:43:18.058843  end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
  948 23:43:18.059579  start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
  949 23:43:18.060115  Setting prompt string to ['=>']
  950 23:43:18.060615  bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
  951 23:43:18.073035   0 
  952 23:43:18.074238  Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
  953 23:43:18.074902  Sending with 10 millisecond of delay
  955 23:43:19.210327  => setenv autoload no
  956 23:43:19.221331  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
  957 23:43:19.227628  setenv autoload no
  958 23:43:19.228543  Sending with 10 millisecond of delay
  960 23:43:21.026114  => setenv initrd_high 0xffffffff
  961 23:43:21.036887  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
  962 23:43:21.037735  setenv initrd_high 0xffffffff
  963 23:43:21.038442  Sending with 10 millisecond of delay
  965 23:43:22.654418  => setenv fdt_high 0xffffffff
  966 23:43:22.665168  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
  967 23:43:22.665973  setenv fdt_high 0xffffffff
  968 23:43:22.666671  Sending with 10 millisecond of delay
  970 23:43:22.958406  => dhcp
  971 23:43:22.969068  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
  972 23:43:22.969846  dhcp
  973 23:43:22.970279  Speed: 1000, full duplex
  974 23:43:22.970686  BOOTP broadcast 1
  975 23:43:22.978741  DHCP client bound to address 192.168.6.27 (10 ms)
  976 23:43:22.979463  Sending with 10 millisecond of delay
  978 23:43:24.655724  => setenv serverip 192.168.6.2
  979 23:43:24.666551  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
  980 23:43:24.667439  setenv serverip 192.168.6.2
  981 23:43:24.668121  Sending with 10 millisecond of delay
  983 23:43:28.392572  => tftpboot 0x01080000 968618/tftp-deploy-tq0vpt0w/kernel/uImage
  984 23:43:28.403605  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
  985 23:43:28.404828  tftpboot 0x01080000 968618/tftp-deploy-tq0vpt0w/kernel/uImage
  986 23:43:28.405427  Speed: 1000, full duplex
  987 23:43:28.405974  Using ethernet@ff3f0000 device
  988 23:43:28.406881  TFTP from server 192.168.6.2; our IP address is 192.168.6.27
  989 23:43:28.412069  Filename '968618/tftp-deploy-tq0vpt0w/kernel/uImage'.
  990 23:43:28.416087  Load address: 0x1080000
  991 23:43:32.736724  Loading: *###################
  992 23:43:32.737315  TFTP error: trying to overwrite reserved memory...
  994 23:43:32.738718  end: 2.4.3 bootloader-commands (duration 00:00:15) [common]
  997 23:43:32.740604  end: 2.4 uboot-commands (duration 00:00:47) [common]
  999 23:43:32.742007  uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
 1001 23:43:32.743098  end: 2 uboot-action (duration 00:00:47) [common]
 1003 23:43:32.744680  Cleaning after the job
 1004 23:43:32.745253  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968618/tftp-deploy-tq0vpt0w/ramdisk
 1005 23:43:32.773421  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968618/tftp-deploy-tq0vpt0w/kernel
 1006 23:43:32.799035  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968618/tftp-deploy-tq0vpt0w/dtb
 1007 23:43:32.799823  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968618/tftp-deploy-tq0vpt0w/nfsrootfs
 1008 23:43:32.895197  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968618/tftp-deploy-tq0vpt0w/modules
 1009 23:43:32.911666  start: 4.1 power-off (timeout 00:00:30) [common]
 1010 23:43:32.912324  Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
 1011 23:43:32.946443  >> OK - accepted request

 1012 23:43:32.948719  Returned 0 in 0 seconds
 1013 23:43:33.049488  end: 4.1 power-off (duration 00:00:00) [common]
 1015 23:43:33.050504  start: 4.2 read-feedback (timeout 00:10:00) [common]
 1016 23:43:33.051162  Listened to connection for namespace 'common' for up to 1s
 1017 23:43:34.051418  Finalising connection for namespace 'common'
 1018 23:43:34.051901  Disconnecting from shell: Finalise
 1019 23:43:34.052223  => 
 1020 23:43:34.152910  end: 4.2 read-feedback (duration 00:00:01) [common]
 1021 23:43:34.153386  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/968618
 1022 23:43:36.067049  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/968618
 1023 23:43:36.067726  InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.