Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 00:06:27.290529 lava-dispatcher, installed at version: 2024.01
2 00:06:27.291334 start: 0 validate
3 00:06:27.291821 Start time: 2024-11-10 00:06:27.291790+00:00 (UTC)
4 00:06:27.292386 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:06:27.292933 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:06:27.333411 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:06:27.333958 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Fclang-15%2Fkernel%2FImage exists
8 00:06:27.364015 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:06:27.364657 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 00:06:27.395169 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:06:27.395681 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:06:27.429893 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 00:06:27.430406 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Fclang-15%2Fmodules.tar.xz exists
14 00:06:27.464119 validate duration: 0.17
16 00:06:27.465003 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:06:27.465341 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:06:27.465665 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:06:27.466257 Not decompressing ramdisk as can be used compressed.
20 00:06:27.466721 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 00:06:27.467009 saving as /var/lib/lava/dispatcher/tmp/968427/tftp-deploy-oyj0498l/ramdisk/initrd.cpio.gz
22 00:06:27.467289 total size: 5628140 (5 MB)
23 00:06:27.504380 progress 0 % (0 MB)
24 00:06:27.509670 progress 5 % (0 MB)
25 00:06:27.514699 progress 10 % (0 MB)
26 00:06:27.519148 progress 15 % (0 MB)
27 00:06:27.524246 progress 20 % (1 MB)
28 00:06:27.528884 progress 25 % (1 MB)
29 00:06:27.533836 progress 30 % (1 MB)
30 00:06:27.538936 progress 35 % (1 MB)
31 00:06:27.543446 progress 40 % (2 MB)
32 00:06:27.548439 progress 45 % (2 MB)
33 00:06:27.553002 progress 50 % (2 MB)
34 00:06:27.557993 progress 55 % (2 MB)
35 00:06:27.562991 progress 60 % (3 MB)
36 00:06:27.567548 progress 65 % (3 MB)
37 00:06:27.572559 progress 70 % (3 MB)
38 00:06:27.577028 progress 75 % (4 MB)
39 00:06:27.581926 progress 80 % (4 MB)
40 00:06:27.586320 progress 85 % (4 MB)
41 00:06:27.591220 progress 90 % (4 MB)
42 00:06:27.596031 progress 95 % (5 MB)
43 00:06:27.600191 progress 100 % (5 MB)
44 00:06:27.601000 5 MB downloaded in 0.13 s (40.15 MB/s)
45 00:06:27.601708 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:06:27.602835 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:06:27.603220 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:06:27.603577 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:06:27.604201 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig/clang-15/kernel/Image
51 00:06:27.604537 saving as /var/lib/lava/dispatcher/tmp/968427/tftp-deploy-oyj0498l/kernel/Image
52 00:06:27.604806 total size: 37878272 (36 MB)
53 00:06:27.605068 No compression specified
54 00:06:27.646455 progress 0 % (0 MB)
55 00:06:27.670445 progress 5 % (1 MB)
56 00:06:27.694119 progress 10 % (3 MB)
57 00:06:27.718157 progress 15 % (5 MB)
58 00:06:27.742569 progress 20 % (7 MB)
59 00:06:27.766349 progress 25 % (9 MB)
60 00:06:27.790547 progress 30 % (10 MB)
61 00:06:27.814476 progress 35 % (12 MB)
62 00:06:27.838597 progress 40 % (14 MB)
63 00:06:27.862507 progress 45 % (16 MB)
64 00:06:27.886354 progress 50 % (18 MB)
65 00:06:27.910613 progress 55 % (19 MB)
66 00:06:27.934652 progress 60 % (21 MB)
67 00:06:27.959176 progress 65 % (23 MB)
68 00:06:27.983290 progress 70 % (25 MB)
69 00:06:28.007033 progress 75 % (27 MB)
70 00:06:28.031214 progress 80 % (28 MB)
71 00:06:28.055125 progress 85 % (30 MB)
72 00:06:28.079413 progress 90 % (32 MB)
73 00:06:28.103581 progress 95 % (34 MB)
74 00:06:28.126929 progress 100 % (36 MB)
75 00:06:28.127678 36 MB downloaded in 0.52 s (69.09 MB/s)
76 00:06:28.128188 end: 1.2.1 http-download (duration 00:00:01) [common]
78 00:06:28.129017 end: 1.2 download-retry (duration 00:00:01) [common]
79 00:06:28.129296 start: 1.3 download-retry (timeout 00:09:59) [common]
80 00:06:28.129562 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 00:06:28.130023 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 00:06:28.130292 saving as /var/lib/lava/dispatcher/tmp/968427/tftp-deploy-oyj0498l/dtb/meson-g12b-a311d-libretech-cc.dtb
83 00:06:28.130499 total size: 54703 (0 MB)
84 00:06:28.130703 No compression specified
85 00:06:28.170206 progress 59 % (0 MB)
86 00:06:28.171059 progress 100 % (0 MB)
87 00:06:28.171605 0 MB downloaded in 0.04 s (1.27 MB/s)
88 00:06:28.172102 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:06:28.172920 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:06:28.173183 start: 1.4 download-retry (timeout 00:09:59) [common]
92 00:06:28.173447 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 00:06:28.173895 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 00:06:28.174134 saving as /var/lib/lava/dispatcher/tmp/968427/tftp-deploy-oyj0498l/nfsrootfs/full.rootfs.tar
95 00:06:28.174336 total size: 474398908 (452 MB)
96 00:06:28.174542 Using unxz to decompress xz
97 00:06:28.213692 progress 0 % (0 MB)
98 00:06:29.384943 progress 5 % (22 MB)
99 00:06:30.859590 progress 10 % (45 MB)
100 00:06:31.300950 progress 15 % (67 MB)
101 00:06:32.128942 progress 20 % (90 MB)
102 00:06:32.707610 progress 25 % (113 MB)
103 00:06:33.086299 progress 30 % (135 MB)
104 00:06:33.695031 progress 35 % (158 MB)
105 00:06:34.526094 progress 40 % (181 MB)
106 00:06:35.262359 progress 45 % (203 MB)
107 00:06:35.833173 progress 50 % (226 MB)
108 00:06:36.493337 progress 55 % (248 MB)
109 00:06:37.716222 progress 60 % (271 MB)
110 00:06:39.204696 progress 65 % (294 MB)
111 00:06:40.846608 progress 70 % (316 MB)
112 00:06:43.929218 progress 75 % (339 MB)
113 00:06:46.342458 progress 80 % (361 MB)
114 00:06:49.232901 progress 85 % (384 MB)
115 00:06:52.426853 progress 90 % (407 MB)
116 00:06:55.625812 progress 95 % (429 MB)
117 00:06:58.892172 progress 100 % (452 MB)
118 00:06:58.905724 452 MB downloaded in 30.73 s (14.72 MB/s)
119 00:06:58.906418 end: 1.4.1 http-download (duration 00:00:31) [common]
121 00:06:58.907268 end: 1.4 download-retry (duration 00:00:31) [common]
122 00:06:58.907541 start: 1.5 download-retry (timeout 00:09:29) [common]
123 00:06:58.907808 start: 1.5.1 http-download (timeout 00:09:29) [common]
124 00:06:58.908521 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig/clang-15/modules.tar.xz
125 00:06:58.909016 saving as /var/lib/lava/dispatcher/tmp/968427/tftp-deploy-oyj0498l/modules/modules.tar
126 00:06:58.909419 total size: 11775236 (11 MB)
127 00:06:58.909834 Using unxz to decompress xz
128 00:06:58.960123 progress 0 % (0 MB)
129 00:06:59.028435 progress 5 % (0 MB)
130 00:06:59.106984 progress 10 % (1 MB)
131 00:06:59.205419 progress 15 % (1 MB)
132 00:06:59.308349 progress 20 % (2 MB)
133 00:06:59.388532 progress 25 % (2 MB)
134 00:06:59.466288 progress 30 % (3 MB)
135 00:06:59.547862 progress 35 % (3 MB)
136 00:06:59.628384 progress 40 % (4 MB)
137 00:06:59.705366 progress 45 % (5 MB)
138 00:06:59.791488 progress 50 % (5 MB)
139 00:06:59.876656 progress 55 % (6 MB)
140 00:06:59.962901 progress 60 % (6 MB)
141 00:07:00.051155 progress 65 % (7 MB)
142 00:07:00.134388 progress 70 % (7 MB)
143 00:07:00.218349 progress 75 % (8 MB)
144 00:07:00.302609 progress 80 % (9 MB)
145 00:07:00.384406 progress 85 % (9 MB)
146 00:07:00.470214 progress 90 % (10 MB)
147 00:07:00.553430 progress 95 % (10 MB)
148 00:07:00.632793 progress 100 % (11 MB)
149 00:07:00.644950 11 MB downloaded in 1.74 s (6.47 MB/s)
150 00:07:00.645548 end: 1.5.1 http-download (duration 00:00:02) [common]
152 00:07:00.646359 end: 1.5 download-retry (duration 00:00:02) [common]
153 00:07:00.646625 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 00:07:00.646890 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 00:07:16.041418 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/968427/extract-nfsrootfs-a3id5l46
156 00:07:16.042013 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 00:07:16.042300 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 00:07:16.043008 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4
159 00:07:16.043505 makedir: /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin
160 00:07:16.043839 makedir: /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/tests
161 00:07:16.044188 makedir: /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/results
162 00:07:16.044515 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-add-keys
163 00:07:16.045029 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-add-sources
164 00:07:16.045580 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-background-process-start
165 00:07:16.046094 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-background-process-stop
166 00:07:16.046623 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-common-functions
167 00:07:16.047128 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-echo-ipv4
168 00:07:16.047607 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-install-packages
169 00:07:16.048130 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-installed-packages
170 00:07:16.048636 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-os-build
171 00:07:16.049119 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-probe-channel
172 00:07:16.049602 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-probe-ip
173 00:07:16.050116 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-target-ip
174 00:07:16.050598 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-target-mac
175 00:07:16.051076 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-target-storage
176 00:07:16.051559 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-test-case
177 00:07:16.052057 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-test-event
178 00:07:16.052555 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-test-feedback
179 00:07:16.053106 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-test-raise
180 00:07:16.053653 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-test-reference
181 00:07:16.054203 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-test-runner
182 00:07:16.054772 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-test-set
183 00:07:16.055310 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-test-shell
184 00:07:16.055873 Updating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-install-packages (oe)
185 00:07:16.056548 Updating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/bin/lava-installed-packages (oe)
186 00:07:16.057074 Creating /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/environment
187 00:07:16.057506 LAVA metadata
188 00:07:16.057792 - LAVA_JOB_ID=968427
189 00:07:16.058020 - LAVA_DISPATCHER_IP=192.168.6.2
190 00:07:16.058420 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 00:07:16.059501 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 00:07:16.059855 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 00:07:16.060113 skipped lava-vland-overlay
194 00:07:16.060380 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 00:07:16.060660 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 00:07:16.060898 skipped lava-multinode-overlay
197 00:07:16.061161 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 00:07:16.061436 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 00:07:16.061714 Loading test definitions
200 00:07:16.062026 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 00:07:16.062267 Using /lava-968427 at stage 0
202 00:07:16.063553 uuid=968427_1.6.2.4.1 testdef=None
203 00:07:16.063900 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 00:07:16.064215 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 00:07:16.066160 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 00:07:16.067017 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 00:07:16.069622 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 00:07:16.070573 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 00:07:16.073231 runner path: /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 968427_1.6.2.4.1
212 00:07:16.073878 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 00:07:16.074642 Creating lava-test-runner.conf files
215 00:07:16.074844 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/968427/lava-overlay-kfljq1v4/lava-968427/0 for stage 0
216 00:07:16.075191 - 0_v4l2-decoder-conformance-vp9
217 00:07:16.075541 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 00:07:16.075819 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 00:07:16.097852 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 00:07:16.098286 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 00:07:16.098547 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 00:07:16.098816 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 00:07:16.099077 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 00:07:16.720148 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 00:07:16.720623 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 00:07:16.720887 extracting modules file /var/lib/lava/dispatcher/tmp/968427/tftp-deploy-oyj0498l/modules/modules.tar to /var/lib/lava/dispatcher/tmp/968427/extract-nfsrootfs-a3id5l46
227 00:07:18.129893 extracting modules file /var/lib/lava/dispatcher/tmp/968427/tftp-deploy-oyj0498l/modules/modules.tar to /var/lib/lava/dispatcher/tmp/968427/extract-overlay-ramdisk-stl1surz/ramdisk
228 00:07:19.593899 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 00:07:19.594398 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 00:07:19.594693 [common] Applying overlay to NFS
231 00:07:19.594924 [common] Applying overlay /var/lib/lava/dispatcher/tmp/968427/compress-overlay-zgqjkdla/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/968427/extract-nfsrootfs-a3id5l46
232 00:07:19.623899 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 00:07:19.624375 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 00:07:19.624670 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 00:07:19.624909 Converting downloaded kernel to a uImage
236 00:07:19.625235 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/968427/tftp-deploy-oyj0498l/kernel/Image /var/lib/lava/dispatcher/tmp/968427/tftp-deploy-oyj0498l/kernel/uImage
237 00:07:20.001181 output: Image Name:
238 00:07:20.001605 output: Created: Sun Nov 10 00:07:19 2024
239 00:07:20.001815 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 00:07:20.002020 output: Data Size: 37878272 Bytes = 36990.50 KiB = 36.12 MiB
241 00:07:20.002222 output: Load Address: 01080000
242 00:07:20.002421 output: Entry Point: 01080000
243 00:07:20.002618 output:
244 00:07:20.002951 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 00:07:20.003216 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 00:07:20.003487 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 00:07:20.003741 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 00:07:20.004033 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 00:07:20.004307 Building ramdisk /var/lib/lava/dispatcher/tmp/968427/extract-overlay-ramdisk-stl1surz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/968427/extract-overlay-ramdisk-stl1surz/ramdisk
250 00:07:22.652274 >> 173438 blocks
251 00:07:30.304105 Adding RAMdisk u-boot header.
252 00:07:30.304825 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/968427/extract-overlay-ramdisk-stl1surz/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/968427/extract-overlay-ramdisk-stl1surz/ramdisk.cpio.gz.uboot
253 00:07:30.557332 output: Image Name:
254 00:07:30.557903 output: Created: Sun Nov 10 00:07:30 2024
255 00:07:30.558501 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 00:07:30.559074 output: Data Size: 24147865 Bytes = 23581.90 KiB = 23.03 MiB
257 00:07:30.559627 output: Load Address: 00000000
258 00:07:30.560226 output: Entry Point: 00000000
259 00:07:30.560774 output:
260 00:07:30.562204 rename /var/lib/lava/dispatcher/tmp/968427/extract-overlay-ramdisk-stl1surz/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/968427/tftp-deploy-oyj0498l/ramdisk/ramdisk.cpio.gz.uboot
261 00:07:30.563228 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 00:07:30.564023 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 00:07:30.564775 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 00:07:30.565411 No LXC device requested
265 00:07:30.566103 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 00:07:30.566810 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 00:07:30.567487 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 00:07:30.568099 Checking files for TFTP limit of 4294967296 bytes.
269 00:07:30.571687 end: 1 tftp-deploy (duration 00:01:03) [common]
270 00:07:30.572519 start: 2 uboot-action (timeout 00:05:00) [common]
271 00:07:30.573230 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 00:07:30.573901 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 00:07:30.574578 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 00:07:30.575279 Using kernel file from prepare-kernel: 968427/tftp-deploy-oyj0498l/kernel/uImage
275 00:07:30.576135 substitutions:
276 00:07:30.576685 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 00:07:30.577205 - {DTB_ADDR}: 0x01070000
278 00:07:30.577721 - {DTB}: 968427/tftp-deploy-oyj0498l/dtb/meson-g12b-a311d-libretech-cc.dtb
279 00:07:30.578236 - {INITRD}: 968427/tftp-deploy-oyj0498l/ramdisk/ramdisk.cpio.gz.uboot
280 00:07:30.578757 - {KERNEL_ADDR}: 0x01080000
281 00:07:30.579267 - {KERNEL}: 968427/tftp-deploy-oyj0498l/kernel/uImage
282 00:07:30.579777 - {LAVA_MAC}: None
283 00:07:30.580378 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/968427/extract-nfsrootfs-a3id5l46
284 00:07:30.580912 - {NFS_SERVER_IP}: 192.168.6.2
285 00:07:30.581422 - {PRESEED_CONFIG}: None
286 00:07:30.581930 - {PRESEED_LOCAL}: None
287 00:07:30.582440 - {RAMDISK_ADDR}: 0x08000000
288 00:07:30.582943 - {RAMDISK}: 968427/tftp-deploy-oyj0498l/ramdisk/ramdisk.cpio.gz.uboot
289 00:07:30.583452 - {ROOT_PART}: None
290 00:07:30.583958 - {ROOT}: None
291 00:07:30.584495 - {SERVER_IP}: 192.168.6.2
292 00:07:30.585004 - {TEE_ADDR}: 0x83000000
293 00:07:30.585511 - {TEE}: None
294 00:07:30.586031 Parsed boot commands:
295 00:07:30.586518 - setenv autoload no
296 00:07:30.587025 - setenv initrd_high 0xffffffff
297 00:07:30.587529 - setenv fdt_high 0xffffffff
298 00:07:30.588074 - dhcp
299 00:07:30.588584 - setenv serverip 192.168.6.2
300 00:07:30.589085 - tftpboot 0x01080000 968427/tftp-deploy-oyj0498l/kernel/uImage
301 00:07:30.589591 - tftpboot 0x08000000 968427/tftp-deploy-oyj0498l/ramdisk/ramdisk.cpio.gz.uboot
302 00:07:30.590095 - tftpboot 0x01070000 968427/tftp-deploy-oyj0498l/dtb/meson-g12b-a311d-libretech-cc.dtb
303 00:07:30.590597 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/968427/extract-nfsrootfs-a3id5l46,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 00:07:30.591113 - bootm 0x01080000 0x08000000 0x01070000
305 00:07:30.591761 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 00:07:30.593791 start: 2.3 connect-device (timeout 00:05:00) [common]
308 00:07:30.594361 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 00:07:30.610332 Setting prompt string to ['lava-test: # ']
310 00:07:30.612243 end: 2.3 connect-device (duration 00:00:00) [common]
311 00:07:30.613086 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 00:07:30.614011 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 00:07:30.614440 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 00:07:30.615704 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 00:07:30.654284 >> OK - accepted request
316 00:07:30.656434 Returned 0 in 0 seconds
317 00:07:30.757869 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 00:07:30.760039 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 00:07:30.760828 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 00:07:30.761512 Setting prompt string to ['Hit any key to stop autoboot']
322 00:07:30.762138 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 00:07:30.764192 Trying 192.168.56.21...
324 00:07:30.764834 Connected to conserv1.
325 00:07:30.765406 Escape character is '^]'.
326 00:07:30.765954
327 00:07:30.766512 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 00:07:30.767069
329 00:07:41.621871 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 00:07:41.622662 bl2_stage_init 0x01
331 00:07:41.623205 bl2_stage_init 0x81
332 00:07:41.627338 hw id: 0x0000 - pwm id 0x01
333 00:07:41.627910 bl2_stage_init 0xc1
334 00:07:41.628464 bl2_stage_init 0x02
335 00:07:41.628992
336 00:07:41.632900 L0:00000000
337 00:07:41.633455 L1:20000703
338 00:07:41.633963 L2:00008067
339 00:07:41.634458 L3:14000000
340 00:07:41.635837 B2:00402000
341 00:07:41.636397 B1:e0f83180
342 00:07:41.636900
343 00:07:41.637400 TE: 58124
344 00:07:41.637893
345 00:07:41.647027 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 00:07:41.647577
347 00:07:41.648121 Board ID = 1
348 00:07:41.648626 Set A53 clk to 24M
349 00:07:41.649128 Set A73 clk to 24M
350 00:07:41.652660 Set clk81 to 24M
351 00:07:41.653206 A53 clk: 1200 MHz
352 00:07:41.653718 A73 clk: 1200 MHz
353 00:07:41.656155 CLK81: 166.6M
354 00:07:41.656676 smccc: 00012a92
355 00:07:41.661816 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 00:07:41.667386 board id: 1
357 00:07:41.672446 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 00:07:41.682856 fw parse done
359 00:07:41.688804 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 00:07:41.731547 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 00:07:41.742355 PIEI prepare done
362 00:07:41.742897 fastboot data load
363 00:07:41.743405 fastboot data verify
364 00:07:41.747920 verify result: 266
365 00:07:41.753530 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 00:07:41.754060 LPDDR4 probe
367 00:07:41.754566 ddr clk to 1584MHz
368 00:07:41.761547 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 00:07:41.798774
370 00:07:41.799365 dmc_version 0001
371 00:07:41.805601 Check phy result
372 00:07:41.811311 INFO : End of CA training
373 00:07:41.811867 INFO : End of initialization
374 00:07:41.816924 INFO : Training has run successfully!
375 00:07:41.817465 Check phy result
376 00:07:41.822537 INFO : End of initialization
377 00:07:41.823078 INFO : End of read enable training
378 00:07:41.828132 INFO : End of fine write leveling
379 00:07:41.833682 INFO : End of Write leveling coarse delay
380 00:07:41.834207 INFO : Training has run successfully!
381 00:07:41.834710 Check phy result
382 00:07:41.839301 INFO : End of initialization
383 00:07:41.839832 INFO : End of read dq deskew training
384 00:07:41.844898 INFO : End of MPR read delay center optimization
385 00:07:41.850559 INFO : End of write delay center optimization
386 00:07:41.856151 INFO : End of read delay center optimization
387 00:07:41.856709 INFO : End of max read latency training
388 00:07:41.861726 INFO : Training has run successfully!
389 00:07:41.862298 1D training succeed
390 00:07:41.870916 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 00:07:41.918641 Check phy result
392 00:07:41.919276 INFO : End of initialization
393 00:07:41.940231 INFO : End of 2D read delay Voltage center optimization
394 00:07:41.960584 INFO : End of 2D read delay Voltage center optimization
395 00:07:42.012634 INFO : End of 2D write delay Voltage center optimization
396 00:07:42.062066 INFO : End of 2D write delay Voltage center optimization
397 00:07:42.067570 INFO : Training has run successfully!
398 00:07:42.068178
399 00:07:42.068730 channel==0
400 00:07:42.073068 RxClkDly_Margin_A0==88 ps 9
401 00:07:42.073611 TxDqDly_Margin_A0==98 ps 10
402 00:07:42.078700 RxClkDly_Margin_A1==88 ps 9
403 00:07:42.079228 TxDqDly_Margin_A1==98 ps 10
404 00:07:42.079746 TrainedVREFDQ_A0==74
405 00:07:42.084270 TrainedVREFDQ_A1==74
406 00:07:42.084812 VrefDac_Margin_A0==25
407 00:07:42.085315 DeviceVref_Margin_A0==40
408 00:07:42.089884 VrefDac_Margin_A1==25
409 00:07:42.090419 DeviceVref_Margin_A1==40
410 00:07:42.090908
411 00:07:42.091408
412 00:07:42.095530 channel==1
413 00:07:42.096087 RxClkDly_Margin_A0==98 ps 10
414 00:07:42.096593 TxDqDly_Margin_A0==88 ps 9
415 00:07:42.101059 RxClkDly_Margin_A1==98 ps 10
416 00:07:42.101595 TxDqDly_Margin_A1==98 ps 10
417 00:07:42.106669 TrainedVREFDQ_A0==77
418 00:07:42.107205 TrainedVREFDQ_A1==78
419 00:07:42.107712 VrefDac_Margin_A0==22
420 00:07:42.112283 DeviceVref_Margin_A0==37
421 00:07:42.112804 VrefDac_Margin_A1==22
422 00:07:42.117862 DeviceVref_Margin_A1==36
423 00:07:42.118420
424 00:07:42.118934 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 00:07:42.123554
426 00:07:42.151566 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 00:07:42.152269 2D training succeed
428 00:07:42.157071 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 00:07:42.162666 auto size-- 65535DDR cs0 size: 2048MB
430 00:07:42.163205 DDR cs1 size: 2048MB
431 00:07:42.168283 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 00:07:42.168830 cs0 DataBus test pass
433 00:07:42.173867 cs1 DataBus test pass
434 00:07:42.174394 cs0 AddrBus test pass
435 00:07:42.174899 cs1 AddrBus test pass
436 00:07:42.175399
437 00:07:42.179539 100bdlr_step_size ps== 420
438 00:07:42.180122 result report
439 00:07:42.185060 boot times 0Enable ddr reg access
440 00:07:42.190606 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 00:07:42.204116 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 00:07:42.777857 0.0;M3 CHK:0;cm4_sp_mode 0
443 00:07:42.778643 MVN_1=0x00000000
444 00:07:42.783150 MVN_2=0x00000000
445 00:07:42.788936 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 00:07:42.789547 OPS=0x10
447 00:07:42.790062 ring efuse init
448 00:07:42.790564 chipver efuse init
449 00:07:42.797213 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 00:07:42.797768 [0.018960 Inits done]
451 00:07:42.798268 secure task start!
452 00:07:42.804709 high task start!
453 00:07:42.805239 low task start!
454 00:07:42.805743 run into bl31
455 00:07:42.811364 NOTICE: BL31: v1.3(release):4fc40b1
456 00:07:42.819135 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 00:07:42.819677 NOTICE: BL31: G12A normal boot!
458 00:07:42.844491 NOTICE: BL31: BL33 decompress pass
459 00:07:42.850175 ERROR: Error initializing runtime service opteed_fast
460 00:07:44.083188
461 00:07:44.084031
462 00:07:44.090918 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 00:07:44.091513
464 00:07:44.092091 Model: Libre Computer AML-A311D-CC Alta
465 00:07:44.300123 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 00:07:44.322278 DRAM: 2 GiB (effective 3.8 GiB)
467 00:07:44.466392 Core: 408 devices, 31 uclasses, devicetree: separate
468 00:07:44.472154 WDT: Not starting watchdog@f0d0
469 00:07:44.504384 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 00:07:44.516862 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 00:07:44.521931 ** Bad device specification mmc 0 **
472 00:07:44.532171 Card did not respond to voltage select! : -110
473 00:07:44.539778 ** Bad device specification mmc 0 **
474 00:07:44.540411 Couldn't find partition mmc 0
475 00:07:44.548157 Card did not respond to voltage select! : -110
476 00:07:44.553653 ** Bad device specification mmc 0 **
477 00:07:44.554230 Couldn't find partition mmc 0
478 00:07:44.558282 Error: could not access storage.
479 00:07:45.822217 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 00:07:45.822984 bl2_stage_init 0x01
481 00:07:45.823537 bl2_stage_init 0x81
482 00:07:45.827612 hw id: 0x0000 - pwm id 0x01
483 00:07:45.828215 bl2_stage_init 0xc1
484 00:07:45.828750 bl2_stage_init 0x02
485 00:07:45.829276
486 00:07:45.833191 L0:00000000
487 00:07:45.833735 L1:20000703
488 00:07:45.834249 L2:00008067
489 00:07:45.834757 L3:14000000
490 00:07:45.838861 B2:00402000
491 00:07:45.839406 B1:e0f83180
492 00:07:45.839931
493 00:07:45.840489 TE: 58124
494 00:07:45.841002
495 00:07:45.844406 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 00:07:45.844956
497 00:07:45.845474 Board ID = 1
498 00:07:45.850059 Set A53 clk to 24M
499 00:07:45.850615 Set A73 clk to 24M
500 00:07:45.851148 Set clk81 to 24M
501 00:07:45.855588 A53 clk: 1200 MHz
502 00:07:45.856174 A73 clk: 1200 MHz
503 00:07:45.856712 CLK81: 166.6M
504 00:07:45.857242 smccc: 00012a91
505 00:07:45.861198 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 00:07:45.866770 board id: 1
507 00:07:45.871754 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 00:07:45.883333 fw parse done
509 00:07:45.889305 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 00:07:45.930990 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 00:07:45.942837 PIEI prepare done
512 00:07:45.943403 fastboot data load
513 00:07:45.943940 fastboot data verify
514 00:07:45.948439 verify result: 266
515 00:07:45.954051 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 00:07:45.954602 LPDDR4 probe
517 00:07:45.955132 ddr clk to 1584MHz
518 00:07:45.962131 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 00:07:45.999262
520 00:07:45.999817 dmc_version 0001
521 00:07:46.005957 Check phy result
522 00:07:46.011856 INFO : End of CA training
523 00:07:46.012567 INFO : End of initialization
524 00:07:46.017422 INFO : Training has run successfully!
525 00:07:46.018036 Check phy result
526 00:07:46.023120 INFO : End of initialization
527 00:07:46.023716 INFO : End of read enable training
528 00:07:46.028606 INFO : End of fine write leveling
529 00:07:46.034207 INFO : End of Write leveling coarse delay
530 00:07:46.034775 INFO : Training has run successfully!
531 00:07:46.035303 Check phy result
532 00:07:46.039806 INFO : End of initialization
533 00:07:46.040429 INFO : End of read dq deskew training
534 00:07:46.045407 INFO : End of MPR read delay center optimization
535 00:07:46.051066 INFO : End of write delay center optimization
536 00:07:46.056623 INFO : End of read delay center optimization
537 00:07:46.057199 INFO : End of max read latency training
538 00:07:46.062218 INFO : Training has run successfully!
539 00:07:46.062800 1D training succeed
540 00:07:46.071397 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 00:07:46.118992 Check phy result
542 00:07:46.119547 INFO : End of initialization
543 00:07:46.140698 INFO : End of 2D read delay Voltage center optimization
544 00:07:46.160960 INFO : End of 2D read delay Voltage center optimization
545 00:07:46.213015 INFO : End of 2D write delay Voltage center optimization
546 00:07:46.262335 INFO : End of 2D write delay Voltage center optimization
547 00:07:46.267896 INFO : Training has run successfully!
548 00:07:46.268482
549 00:07:46.269002 channel==0
550 00:07:46.273502 RxClkDly_Margin_A0==88 ps 9
551 00:07:46.274060 TxDqDly_Margin_A0==98 ps 10
552 00:07:46.276861 RxClkDly_Margin_A1==88 ps 9
553 00:07:46.277407 TxDqDly_Margin_A1==98 ps 10
554 00:07:46.282433 TrainedVREFDQ_A0==74
555 00:07:46.282987 TrainedVREFDQ_A1==74
556 00:07:46.283508 VrefDac_Margin_A0==25
557 00:07:46.288178 DeviceVref_Margin_A0==40
558 00:07:46.288736 VrefDac_Margin_A1==25
559 00:07:46.293637 DeviceVref_Margin_A1==40
560 00:07:46.294187
561 00:07:46.294715
562 00:07:46.295235 channel==1
563 00:07:46.295744 RxClkDly_Margin_A0==98 ps 10
564 00:07:46.299218 TxDqDly_Margin_A0==98 ps 10
565 00:07:46.299748 RxClkDly_Margin_A1==98 ps 10
566 00:07:46.304865 TxDqDly_Margin_A1==88 ps 9
567 00:07:46.305413 TrainedVREFDQ_A0==77
568 00:07:46.305926 TrainedVREFDQ_A1==77
569 00:07:46.310420 VrefDac_Margin_A0==22
570 00:07:46.310945 DeviceVref_Margin_A0==37
571 00:07:46.316106 VrefDac_Margin_A1==22
572 00:07:46.316668 DeviceVref_Margin_A1==37
573 00:07:46.317181
574 00:07:46.321625 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 00:07:46.322172
576 00:07:46.349636 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000018 dram_vref_reg_value 0x 00000060
577 00:07:46.355192 2D training succeed
578 00:07:46.360847 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 00:07:46.361401 auto size-- 65535DDR cs0 size: 2048MB
580 00:07:46.366424 DDR cs1 size: 2048MB
581 00:07:46.366966 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 00:07:46.372249 cs0 DataBus test pass
583 00:07:46.372802 cs1 DataBus test pass
584 00:07:46.373319 cs0 AddrBus test pass
585 00:07:46.377709 cs1 AddrBus test pass
586 00:07:46.378291
587 00:07:46.378827 100bdlr_step_size ps== 420
588 00:07:46.379351 result report
589 00:07:46.383343 boot times 0Enable ddr reg access
590 00:07:46.390964 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 00:07:46.404447 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 00:07:46.978217 0.0;M3 CHK:0;cm4_sp_mode 0
593 00:07:46.978970 MVN_1=0x00000000
594 00:07:46.983771 MVN_2=0x00000000
595 00:07:46.989548 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 00:07:46.990167 OPS=0x10
597 00:07:46.990724 ring efuse init
598 00:07:46.991244 chipver efuse init
599 00:07:46.995093 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 00:07:47.000706 [0.018961 Inits done]
601 00:07:47.001249 secure task start!
602 00:07:47.001753 high task start!
603 00:07:47.005416 low task start!
604 00:07:47.005948 run into bl31
605 00:07:47.011940 NOTICE: BL31: v1.3(release):4fc40b1
606 00:07:47.019883 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 00:07:47.020572 NOTICE: BL31: G12A normal boot!
608 00:07:47.045140 NOTICE: BL31: BL33 decompress pass
609 00:07:47.050843 ERROR: Error initializing runtime service opteed_fast
610 00:07:48.283716
611 00:07:48.284406
612 00:07:48.292235 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 00:07:48.292766
614 00:07:48.293193 Model: Libre Computer AML-A311D-CC Alta
615 00:07:48.500630 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 00:07:48.524009 DRAM: 2 GiB (effective 3.8 GiB)
617 00:07:48.667119 Core: 408 devices, 31 uclasses, devicetree: separate
618 00:07:48.672861 WDT: Not starting watchdog@f0d0
619 00:07:48.705116 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 00:07:48.717624 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 00:07:48.722521 ** Bad device specification mmc 0 **
622 00:07:48.732914 Card did not respond to voltage select! : -110
623 00:07:48.740542 ** Bad device specification mmc 0 **
624 00:07:48.741063 Couldn't find partition mmc 0
625 00:07:48.748912 Card did not respond to voltage select! : -110
626 00:07:48.754416 ** Bad device specification mmc 0 **
627 00:07:48.754931 Couldn't find partition mmc 0
628 00:07:48.758640 Error: could not access storage.
629 00:07:49.101843 Net: eth0: ethernet@ff3f0000
630 00:07:49.102430 starting USB...
631 00:07:49.353888 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 00:07:49.354539 Starting the controller
633 00:07:49.360841 USB XHCI 1.10
634 00:07:51.073870 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 00:07:51.074501 bl2_stage_init 0x01
636 00:07:51.074925 bl2_stage_init 0x81
637 00:07:51.079446 hw id: 0x0000 - pwm id 0x01
638 00:07:51.079926 bl2_stage_init 0xc1
639 00:07:51.080376 bl2_stage_init 0x02
640 00:07:51.080778
641 00:07:51.085059 L0:00000000
642 00:07:51.085538 L1:20000703
643 00:07:51.085946 L2:00008067
644 00:07:51.086343 L3:14000000
645 00:07:51.088020 B2:00402000
646 00:07:51.088486 B1:e0f83180
647 00:07:51.088892
648 00:07:51.089290 TE: 58124
649 00:07:51.089684
650 00:07:51.099101 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 00:07:51.099607
652 00:07:51.100049 Board ID = 1
653 00:07:51.100452 Set A53 clk to 24M
654 00:07:51.100843 Set A73 clk to 24M
655 00:07:51.104756 Set clk81 to 24M
656 00:07:51.105250 A53 clk: 1200 MHz
657 00:07:51.105654 A73 clk: 1200 MHz
658 00:07:51.110321 CLK81: 166.6M
659 00:07:51.110798 smccc: 00012a91
660 00:07:51.116027 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 00:07:51.116549 board id: 1
662 00:07:51.124530 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 00:07:51.135154 fw parse done
664 00:07:51.141077 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 00:07:51.183663 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 00:07:51.194565 PIEI prepare done
667 00:07:51.195042 fastboot data load
668 00:07:51.195452 fastboot data verify
669 00:07:51.200185 verify result: 266
670 00:07:51.205761 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 00:07:51.206231 LPDDR4 probe
672 00:07:51.206642 ddr clk to 1584MHz
673 00:07:51.213766 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 00:07:51.251115
675 00:07:51.251628 dmc_version 0001
676 00:07:51.257829 Check phy result
677 00:07:51.263616 INFO : End of CA training
678 00:07:51.264124 INFO : End of initialization
679 00:07:51.269247 INFO : Training has run successfully!
680 00:07:51.269715 Check phy result
681 00:07:51.274752 INFO : End of initialization
682 00:07:51.275212 INFO : End of read enable training
683 00:07:51.280444 INFO : End of fine write leveling
684 00:07:51.285959 INFO : End of Write leveling coarse delay
685 00:07:51.286422 INFO : Training has run successfully!
686 00:07:51.286825 Check phy result
687 00:07:51.291624 INFO : End of initialization
688 00:07:51.292126 INFO : End of read dq deskew training
689 00:07:51.297232 INFO : End of MPR read delay center optimization
690 00:07:51.302723 INFO : End of write delay center optimization
691 00:07:51.308440 INFO : End of read delay center optimization
692 00:07:51.308901 INFO : End of max read latency training
693 00:07:51.313966 INFO : Training has run successfully!
694 00:07:51.314429 1D training succeed
695 00:07:51.323171 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 00:07:51.370891 Check phy result
697 00:07:51.371466 INFO : End of initialization
698 00:07:51.392444 INFO : End of 2D read delay Voltage center optimization
699 00:07:51.412558 INFO : End of 2D read delay Voltage center optimization
700 00:07:51.464518 INFO : End of 2D write delay Voltage center optimization
701 00:07:51.513639 INFO : End of 2D write delay Voltage center optimization
702 00:07:51.519221 INFO : Training has run successfully!
703 00:07:51.519686
704 00:07:51.520092 channel==0
705 00:07:51.524744 RxClkDly_Margin_A0==88 ps 9
706 00:07:51.525149 TxDqDly_Margin_A0==98 ps 10
707 00:07:51.530355 RxClkDly_Margin_A1==88 ps 9
708 00:07:51.530803 TxDqDly_Margin_A1==98 ps 10
709 00:07:51.531176 TrainedVREFDQ_A0==74
710 00:07:51.536028 TrainedVREFDQ_A1==74
711 00:07:51.536499 VrefDac_Margin_A0==25
712 00:07:51.536854 DeviceVref_Margin_A0==40
713 00:07:51.541507 VrefDac_Margin_A1==25
714 00:07:51.541995 DeviceVref_Margin_A1==40
715 00:07:51.542572
716 00:07:51.543302
717 00:07:51.547153 channel==1
718 00:07:51.547782 RxClkDly_Margin_A0==98 ps 10
719 00:07:51.548256 TxDqDly_Margin_A0==98 ps 10
720 00:07:51.552805 RxClkDly_Margin_A1==98 ps 10
721 00:07:51.553359 TxDqDly_Margin_A1==88 ps 9
722 00:07:51.558437 TrainedVREFDQ_A0==77
723 00:07:51.558853 TrainedVREFDQ_A1==77
724 00:07:51.559107 VrefDac_Margin_A0==22
725 00:07:51.563959 DeviceVref_Margin_A0==37
726 00:07:51.564379 VrefDac_Margin_A1==22
727 00:07:51.569566 DeviceVref_Margin_A1==37
728 00:07:51.569956
729 00:07:51.570200 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 00:07:51.575318
731 00:07:51.603048 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
732 00:07:51.603784 2D training succeed
733 00:07:51.608600 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 00:07:51.614307 auto size-- 65535DDR cs0 size: 2048MB
735 00:07:51.614923 DDR cs1 size: 2048MB
736 00:07:51.619926 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 00:07:51.620578 cs0 DataBus test pass
738 00:07:51.625526 cs1 DataBus test pass
739 00:07:51.626119 cs0 AddrBus test pass
740 00:07:51.626606 cs1 AddrBus test pass
741 00:07:51.627076
742 00:07:51.631073 100bdlr_step_size ps== 420
743 00:07:51.631652 result report
744 00:07:51.636733 boot times 0Enable ddr reg access
745 00:07:51.642156 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 00:07:51.655612 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 00:07:52.227726 0.0;M3 CHK:0;cm4_sp_mode 0
748 00:07:52.228447 MVN_1=0x00000000
749 00:07:52.233044 MVN_2=0x00000000
750 00:07:52.238900 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 00:07:52.239378 OPS=0x10
752 00:07:52.239818 ring efuse init
753 00:07:52.240284 chipver efuse init
754 00:07:52.244424 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 00:07:52.249958 [0.018961 Inits done]
756 00:07:52.250436 secure task start!
757 00:07:52.250870 high task start!
758 00:07:52.254574 low task start!
759 00:07:52.255046 run into bl31
760 00:07:52.261183 NOTICE: BL31: v1.3(release):4fc40b1
761 00:07:52.269054 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 00:07:52.269652 NOTICE: BL31: G12A normal boot!
763 00:07:52.294398 NOTICE: BL31: BL33 decompress pass
764 00:07:52.300074 ERROR: Error initializing runtime service opteed_fast
765 00:07:53.532998
766 00:07:53.533669
767 00:07:53.541400 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 00:07:53.541917
769 00:07:53.542372 Model: Libre Computer AML-A311D-CC Alta
770 00:07:53.749908 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 00:07:53.773209 DRAM: 2 GiB (effective 3.8 GiB)
772 00:07:53.916248 Core: 408 devices, 31 uclasses, devicetree: separate
773 00:07:53.922034 WDT: Not starting watchdog@f0d0
774 00:07:53.954420 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 00:07:53.966788 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 00:07:53.971717 ** Bad device specification mmc 0 **
777 00:07:53.982157 Card did not respond to voltage select! : -110
778 00:07:53.989713 ** Bad device specification mmc 0 **
779 00:07:53.990278 Couldn't find partition mmc 0
780 00:07:53.998162 Card did not respond to voltage select! : -110
781 00:07:54.003558 ** Bad device specification mmc 0 **
782 00:07:54.004139 Couldn't find partition mmc 0
783 00:07:54.008625 Error: could not access storage.
784 00:07:54.352306 Net: eth0: ethernet@ff3f0000
785 00:07:54.352961 starting USB...
786 00:07:54.604060 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 00:07:54.604720 Starting the controller
788 00:07:54.610987 USB XHCI 1.10
789 00:07:56.772379 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 00:07:56.773005 bl2_stage_init 0x01
791 00:07:56.773433 bl2_stage_init 0x81
792 00:07:56.778002 hw id: 0x0000 - pwm id 0x01
793 00:07:56.778481 bl2_stage_init 0xc1
794 00:07:56.778892 bl2_stage_init 0x02
795 00:07:56.779295
796 00:07:56.783645 L0:00000000
797 00:07:56.784154 L1:20000703
798 00:07:56.784570 L2:00008067
799 00:07:56.784971 L3:14000000
800 00:07:56.789044 B2:00402000
801 00:07:56.789508 B1:e0f83180
802 00:07:56.789912
803 00:07:56.790311 TE: 58167
804 00:07:56.790707
805 00:07:56.794685 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 00:07:56.795164
807 00:07:56.795574 Board ID = 1
808 00:07:56.800267 Set A53 clk to 24M
809 00:07:56.800739 Set A73 clk to 24M
810 00:07:56.801148 Set clk81 to 24M
811 00:07:56.805746 A53 clk: 1200 MHz
812 00:07:56.806042 A73 clk: 1200 MHz
813 00:07:56.806285 CLK81: 166.6M
814 00:07:56.806528 smccc: 00012abe
815 00:07:56.811414 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 00:07:56.816999 board id: 1
817 00:07:56.822958 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 00:07:56.833646 fw parse done
819 00:07:56.839787 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 00:07:56.882192 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 00:07:56.893087 PIEI prepare done
822 00:07:56.893569 fastboot data load
823 00:07:56.893985 fastboot data verify
824 00:07:56.898804 verify result: 266
825 00:07:56.904372 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 00:07:56.904850 LPDDR4 probe
827 00:07:56.905259 ddr clk to 1584MHz
828 00:07:56.912283 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 00:07:56.949594
830 00:07:56.950066 dmc_version 0001
831 00:07:56.955444 Check phy result
832 00:07:56.962140 INFO : End of CA training
833 00:07:56.962606 INFO : End of initialization
834 00:07:56.967748 INFO : Training has run successfully!
835 00:07:56.968234 Check phy result
836 00:07:56.973368 INFO : End of initialization
837 00:07:56.973821 INFO : End of read enable training
838 00:07:56.978943 INFO : End of fine write leveling
839 00:07:56.984555 INFO : End of Write leveling coarse delay
840 00:07:56.985018 INFO : Training has run successfully!
841 00:07:56.985422 Check phy result
842 00:07:56.990147 INFO : End of initialization
843 00:07:56.990600 INFO : End of read dq deskew training
844 00:07:56.995697 INFO : End of MPR read delay center optimization
845 00:07:57.001354 INFO : End of write delay center optimization
846 00:07:57.006962 INFO : End of read delay center optimization
847 00:07:57.007425 INFO : End of max read latency training
848 00:07:57.012607 INFO : Training has run successfully!
849 00:07:57.013080 1D training succeed
850 00:07:57.021773 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 00:07:57.069374 Check phy result
852 00:07:57.069857 INFO : End of initialization
853 00:07:57.091117 INFO : End of 2D read delay Voltage center optimization
854 00:07:57.111342 INFO : End of 2D read delay Voltage center optimization
855 00:07:57.163364 INFO : End of 2D write delay Voltage center optimization
856 00:07:57.212950 INFO : End of 2D write delay Voltage center optimization
857 00:07:57.218402 INFO : Training has run successfully!
858 00:07:57.218868
859 00:07:57.219298 channel==0
860 00:07:57.223974 RxClkDly_Margin_A0==88 ps 9
861 00:07:57.224456 TxDqDly_Margin_A0==98 ps 10
862 00:07:57.227265 RxClkDly_Margin_A1==88 ps 9
863 00:07:57.227721 TxDqDly_Margin_A1==98 ps 10
864 00:07:57.232793 TrainedVREFDQ_A0==74
865 00:07:57.233251 TrainedVREFDQ_A1==74
866 00:07:57.239096 VrefDac_Margin_A0==25
867 00:07:57.239571 DeviceVref_Margin_A0==40
868 00:07:57.240026 VrefDac_Margin_A1==25
869 00:07:57.244033 DeviceVref_Margin_A1==40
870 00:07:57.244488
871 00:07:57.244876
872 00:07:57.245258 channel==1
873 00:07:57.245636 RxClkDly_Margin_A0==98 ps 10
874 00:07:57.249573 TxDqDly_Margin_A0==98 ps 10
875 00:07:57.250026 RxClkDly_Margin_A1==98 ps 10
876 00:07:57.255205 TxDqDly_Margin_A1==88 ps 9
877 00:07:57.255654 TrainedVREFDQ_A0==77
878 00:07:57.256079 TrainedVREFDQ_A1==77
879 00:07:57.260781 VrefDac_Margin_A0==22
880 00:07:57.261226 DeviceVref_Margin_A0==37
881 00:07:57.266287 VrefDac_Margin_A1==24
882 00:07:57.266728 DeviceVref_Margin_A1==37
883 00:07:57.267114
884 00:07:57.271964 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 00:07:57.272433
886 00:07:57.299903 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
887 00:07:57.305529 2D training succeed
888 00:07:57.311110 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 00:07:57.311584 auto size-- 65535DDR cs0 size: 2048MB
890 00:07:57.316702 DDR cs1 size: 2048MB
891 00:07:57.317148 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 00:07:57.322265 cs0 DataBus test pass
893 00:07:57.322702 cs1 DataBus test pass
894 00:07:57.323087 cs0 AddrBus test pass
895 00:07:57.327854 cs1 AddrBus test pass
896 00:07:57.328334
897 00:07:57.328719 100bdlr_step_size ps== 420
898 00:07:57.329109 result report
899 00:07:57.333499 boot times 0Enable ddr reg access
900 00:07:57.341273 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 00:07:57.354732 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 00:07:57.928357 0.0;M3 CHK:0;cm4_sp_mode 0
903 00:07:57.928984 MVN_1=0x00000000
904 00:07:57.933804 MVN_2=0x00000000
905 00:07:57.939684 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 00:07:57.940192 OPS=0x10
907 00:07:57.940595 ring efuse init
908 00:07:57.940987 chipver efuse init
909 00:07:57.945164 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 00:07:57.950734 [0.018961 Inits done]
911 00:07:57.951196 secure task start!
912 00:07:57.951587 high task start!
913 00:07:57.955337 low task start!
914 00:07:57.955791 run into bl31
915 00:07:57.961979 NOTICE: BL31: v1.3(release):4fc40b1
916 00:07:57.969797 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 00:07:57.970274 NOTICE: BL31: G12A normal boot!
918 00:07:57.995726 NOTICE: BL31: BL33 decompress pass
919 00:07:58.001376 ERROR: Error initializing runtime service opteed_fast
920 00:07:59.234296
921 00:07:59.234919
922 00:07:59.242769 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 00:07:59.243259
924 00:07:59.243681 Model: Libre Computer AML-A311D-CC Alta
925 00:07:59.451160 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 00:07:59.473632 DRAM: 2 GiB (effective 3.8 GiB)
927 00:07:59.617598 Core: 408 devices, 31 uclasses, devicetree: separate
928 00:07:59.623431 WDT: Not starting watchdog@f0d0
929 00:07:59.655625 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 00:07:59.668017 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 00:07:59.673004 ** Bad device specification mmc 0 **
932 00:07:59.683315 Card did not respond to voltage select! : -110
933 00:07:59.690983 ** Bad device specification mmc 0 **
934 00:07:59.691520 Couldn't find partition mmc 0
935 00:07:59.699281 Card did not respond to voltage select! : -110
936 00:07:59.704920 ** Bad device specification mmc 0 **
937 00:07:59.705449 Couldn't find partition mmc 0
938 00:07:59.709994 Error: could not access storage.
939 00:08:00.053357 Net: eth0: ethernet@ff3f0000
940 00:08:00.053911 starting USB...
941 00:08:00.305162 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 00:08:00.305735 Starting the controller
943 00:08:00.312142 USB XHCI 1.10
944 00:08:02.172182 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 00:08:02.172850 bl2_stage_init 0x01
946 00:08:02.173325 bl2_stage_init 0x81
947 00:08:02.177584 hw id: 0x0000 - pwm id 0x01
948 00:08:02.178079 bl2_stage_init 0xc1
949 00:08:02.178535 bl2_stage_init 0x02
950 00:08:02.178983
951 00:08:02.183242 L0:00000000
952 00:08:02.183730 L1:20000703
953 00:08:02.184232 L2:00008067
954 00:08:02.184683 L3:14000000
955 00:08:02.188772 B2:00402000
956 00:08:02.189252 B1:e0f83180
957 00:08:02.189695
958 00:08:02.190139 TE: 58159
959 00:08:02.190586
960 00:08:02.194277 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 00:08:02.194773
962 00:08:02.195228 Board ID = 1
963 00:08:02.199865 Set A53 clk to 24M
964 00:08:02.200378 Set A73 clk to 24M
965 00:08:02.200831 Set clk81 to 24M
966 00:08:02.205487 A53 clk: 1200 MHz
967 00:08:02.205962 A73 clk: 1200 MHz
968 00:08:02.206410 CLK81: 166.6M
969 00:08:02.206847 smccc: 00012ab5
970 00:08:02.211247 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 00:08:02.216719 board id: 1
972 00:08:02.222557 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 00:08:02.233229 fw parse done
974 00:08:02.239337 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 00:08:02.282073 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 00:08:02.293278 PIEI prepare done
977 00:08:02.293853 fastboot data load
978 00:08:02.294293 fastboot data verify
979 00:08:02.300431 verify result: 266
980 00:08:02.305439 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 00:08:02.305949 LPDDR4 probe
982 00:08:02.306381 ddr clk to 1584MHz
983 00:08:02.312417 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 00:08:02.349633
985 00:08:02.350278 dmc_version 0001
986 00:08:02.356250 Check phy result
987 00:08:02.362699 INFO : End of CA training
988 00:08:02.363183 INFO : End of initialization
989 00:08:02.369819 INFO : Training has run successfully!
990 00:08:02.370421 Check phy result
991 00:08:02.373795 INFO : End of initialization
992 00:08:02.374300 INFO : End of read enable training
993 00:08:02.378705 INFO : End of fine write leveling
994 00:08:02.384337 INFO : End of Write leveling coarse delay
995 00:08:02.384841 INFO : Training has run successfully!
996 00:08:02.385292 Check phy result
997 00:08:02.389945 INFO : End of initialization
998 00:08:02.390456 INFO : End of read dq deskew training
999 00:08:02.395481 INFO : End of MPR read delay center optimization
1000 00:08:02.401161 INFO : End of write delay center optimization
1001 00:08:02.406757 INFO : End of read delay center optimization
1002 00:08:02.407242 INFO : End of max read latency training
1003 00:08:02.413729 INFO : Training has run successfully!
1004 00:08:02.414236 1D training succeed
1005 00:08:02.421155 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 00:08:02.469025 Check phy result
1007 00:08:02.469550 INFO : End of initialization
1008 00:08:02.490648 INFO : End of 2D read delay Voltage center optimization
1009 00:08:02.510777 INFO : End of 2D read delay Voltage center optimization
1010 00:08:02.562657 INFO : End of 2D write delay Voltage center optimization
1011 00:08:02.611913 INFO : End of 2D write delay Voltage center optimization
1012 00:08:02.617504 INFO : Training has run successfully!
1013 00:08:02.617989
1014 00:08:02.618452 channel==0
1015 00:08:02.623141 RxClkDly_Margin_A0==88 ps 9
1016 00:08:02.623621 TxDqDly_Margin_A0==98 ps 10
1017 00:08:02.626580 RxClkDly_Margin_A1==88 ps 9
1018 00:08:02.627052 TxDqDly_Margin_A1==98 ps 10
1019 00:08:02.632188 TrainedVREFDQ_A0==76
1020 00:08:02.632661 TrainedVREFDQ_A1==74
1021 00:08:02.633137 VrefDac_Margin_A0==24
1022 00:08:02.637907 DeviceVref_Margin_A0==38
1023 00:08:02.638406 VrefDac_Margin_A1==25
1024 00:08:02.643259 DeviceVref_Margin_A1==40
1025 00:08:02.643738
1026 00:08:02.644227
1027 00:08:02.644671 channel==1
1028 00:08:02.645108 RxClkDly_Margin_A0==98 ps 10
1029 00:08:02.648975 TxDqDly_Margin_A0==98 ps 10
1030 00:08:02.649456 RxClkDly_Margin_A1==98 ps 10
1031 00:08:02.654525 TxDqDly_Margin_A1==88 ps 9
1032 00:08:02.655003 TrainedVREFDQ_A0==77
1033 00:08:02.655449 TrainedVREFDQ_A1==77
1034 00:08:02.660198 VrefDac_Margin_A0==22
1035 00:08:02.660676 DeviceVref_Margin_A0==37
1036 00:08:02.665779 VrefDac_Margin_A1==22
1037 00:08:02.666255 DeviceVref_Margin_A1==37
1038 00:08:02.666693
1039 00:08:02.671350 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 00:08:02.671826
1041 00:08:02.699180 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1042 00:08:02.704785 2D training succeed
1043 00:08:02.710422 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 00:08:02.710899 auto size-- 65535DDR cs0 size: 2048MB
1045 00:08:02.716035 DDR cs1 size: 2048MB
1046 00:08:02.716512 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 00:08:02.721618 cs0 DataBus test pass
1048 00:08:02.722091 cs1 DataBus test pass
1049 00:08:02.722540 cs0 AddrBus test pass
1050 00:08:02.727201 cs1 AddrBus test pass
1051 00:08:02.727668
1052 00:08:02.728145 100bdlr_step_size ps== 415
1053 00:08:02.728596 result report
1054 00:08:02.732783 boot times 0Enable ddr reg access
1055 00:08:02.740429 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 00:08:02.753907 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 00:08:03.325904 0.0;M3 CHK:0;cm4_sp_mode 0
1058 00:08:03.326568 MVN_1=0x00000000
1059 00:08:03.331417 MVN_2=0x00000000
1060 00:08:03.337175 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 00:08:03.337717 OPS=0x10
1062 00:08:03.338185 ring efuse init
1063 00:08:03.338640 chipver efuse init
1064 00:08:03.342715 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 00:08:03.348412 [0.018960 Inits done]
1066 00:08:03.348885 secure task start!
1067 00:08:03.349332 high task start!
1068 00:08:03.352895 low task start!
1069 00:08:03.353364 run into bl31
1070 00:08:03.359578 NOTICE: BL31: v1.3(release):4fc40b1
1071 00:08:03.367470 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 00:08:03.367962 NOTICE: BL31: G12A normal boot!
1073 00:08:03.392797 NOTICE: BL31: BL33 decompress pass
1074 00:08:03.398468 ERROR: Error initializing runtime service opteed_fast
1075 00:08:04.631445
1076 00:08:04.632148
1077 00:08:04.639747 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 00:08:04.640271
1079 00:08:04.640727 Model: Libre Computer AML-A311D-CC Alta
1080 00:08:04.848107 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 00:08:04.871516 DRAM: 2 GiB (effective 3.8 GiB)
1082 00:08:05.014461 Core: 408 devices, 31 uclasses, devicetree: separate
1083 00:08:05.020370 WDT: Not starting watchdog@f0d0
1084 00:08:05.052754 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 00:08:05.065112 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 00:08:05.069595 ** Bad device specification mmc 0 **
1087 00:08:05.080401 Card did not respond to voltage select! : -110
1088 00:08:05.088094 ** Bad device specification mmc 0 **
1089 00:08:05.088587 Couldn't find partition mmc 0
1090 00:08:05.096405 Card did not respond to voltage select! : -110
1091 00:08:05.101903 ** Bad device specification mmc 0 **
1092 00:08:05.102381 Couldn't find partition mmc 0
1093 00:08:05.106964 Error: could not access storage.
1094 00:08:05.450625 Net: eth0: ethernet@ff3f0000
1095 00:08:05.451185 starting USB...
1096 00:08:05.702303 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 00:08:05.702843 Starting the controller
1098 00:08:05.709256 USB XHCI 1.10
1099 00:08:07.266706 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 00:08:07.274934 scanning usb for storage devices... 0 Storage Device(s) found
1102 00:08:07.326666 Hit any key to stop autoboot: 1
1103 00:08:07.327496 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 00:08:07.328144 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 00:08:07.328645 Setting prompt string to ['=>']
1106 00:08:07.329157 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 00:08:07.342329 0
1108 00:08:07.343232 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 00:08:07.343743 Sending with 10 millisecond of delay
1111 00:08:08.478659 => setenv autoload no
1112 00:08:08.489518 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 00:08:08.494866 setenv autoload no
1114 00:08:08.495650 Sending with 10 millisecond of delay
1116 00:08:10.292628 => setenv initrd_high 0xffffffff
1117 00:08:10.303468 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 00:08:10.304424 setenv initrd_high 0xffffffff
1119 00:08:10.305196 Sending with 10 millisecond of delay
1121 00:08:11.921767 => setenv fdt_high 0xffffffff
1122 00:08:11.932573 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1123 00:08:11.933414 setenv fdt_high 0xffffffff
1124 00:08:11.934119 Sending with 10 millisecond of delay
1126 00:08:12.225941 => dhcp
1127 00:08:12.236718 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 00:08:12.237578 dhcp
1129 00:08:12.238015 Speed: 1000, full duplex
1130 00:08:12.238424 BOOTP broadcast 1
1131 00:08:12.249437 DHCP client bound to address 192.168.6.27 (13 ms)
1132 00:08:12.250186 Sending with 10 millisecond of delay
1134 00:08:13.926393 => setenv serverip 192.168.6.2
1135 00:08:13.937152 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1136 00:08:13.938037 setenv serverip 192.168.6.2
1137 00:08:13.938720 Sending with 10 millisecond of delay
1139 00:08:17.661817 => tftpboot 0x01080000 968427/tftp-deploy-oyj0498l/kernel/uImage
1140 00:08:17.672604 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1141 00:08:17.673411 tftpboot 0x01080000 968427/tftp-deploy-oyj0498l/kernel/uImage
1142 00:08:17.673850 Speed: 1000, full duplex
1143 00:08:17.674253 Using ethernet@ff3f0000 device
1144 00:08:17.675152 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 00:08:17.680700 Filename '968427/tftp-deploy-oyj0498l/kernel/uImage'.
1146 00:08:17.684533 Load address: 0x1080000
1147 00:08:20.072641 Loading: *################################################## 36.1 MiB
1148 00:08:20.073260 15.1 MiB/s
1149 00:08:20.073692 done
1150 00:08:20.077063 Bytes transferred = 37878336 (241fa40 hex)
1151 00:08:20.077845 Sending with 10 millisecond of delay
1153 00:08:24.764709 => tftpboot 0x08000000 968427/tftp-deploy-oyj0498l/ramdisk/ramdisk.cpio.gz.uboot
1154 00:08:24.775651 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:06)
1155 00:08:24.776700 tftpboot 0x08000000 968427/tftp-deploy-oyj0498l/ramdisk/ramdisk.cpio.gz.uboot
1156 00:08:24.777278 Speed: 1000, full duplex
1157 00:08:24.777806 Using ethernet@ff3f0000 device
1158 00:08:24.778430 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 00:08:24.789922 Filename '968427/tftp-deploy-oyj0498l/ramdisk/ramdisk.cpio.gz.uboot'.
1160 00:08:24.790555 Load address: 0x8000000
1161 00:08:29.002290 Loading: *################################# UDP wrong checksum 000000ff 00007d95
1162 00:08:29.047889 UDP wrong checksum 000000ff 00000988
1163 00:08:31.430550 T ################ UDP wrong checksum 00000005 0000bc35
1164 00:08:36.432418 T UDP wrong checksum 00000005 0000bc35
1165 00:08:44.812516 T UDP wrong checksum 000000ff 0000ac19
1166 00:08:44.841872 UDP wrong checksum 000000ff 0000430c
1167 00:08:46.434593 T UDP wrong checksum 00000005 0000bc35
1168 00:09:06.437071 T T T UDP wrong checksum 00000005 0000bc35
1169 00:09:06.449734 T UDP wrong checksum 000000ff 00002b36
1170 00:09:06.490717 UDP wrong checksum 000000ff 0000c628
1171 00:09:21.442752 T T
1172 00:09:21.443381 Retry count exceeded; starting again
1174 00:09:21.444866 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1177 00:09:21.446715 end: 2.4 uboot-commands (duration 00:01:51) [common]
1179 00:09:21.448195 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1181 00:09:21.449212 end: 2 uboot-action (duration 00:01:51) [common]
1183 00:09:21.450790 Cleaning after the job
1184 00:09:21.451330 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968427/tftp-deploy-oyj0498l/ramdisk
1185 00:09:21.452594 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968427/tftp-deploy-oyj0498l/kernel
1186 00:09:21.475171 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968427/tftp-deploy-oyj0498l/dtb
1187 00:09:21.476309 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968427/tftp-deploy-oyj0498l/nfsrootfs
1188 00:09:21.607885 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968427/tftp-deploy-oyj0498l/modules
1189 00:09:21.629297 start: 4.1 power-off (timeout 00:00:30) [common]
1190 00:09:21.629926 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1191 00:09:21.662473 >> OK - accepted request
1192 00:09:21.664580 Returned 0 in 0 seconds
1193 00:09:21.765302 end: 4.1 power-off (duration 00:00:00) [common]
1195 00:09:21.766205 start: 4.2 read-feedback (timeout 00:10:00) [common]
1196 00:09:21.766836 Listened to connection for namespace 'common' for up to 1s
1197 00:09:22.767827 Finalising connection for namespace 'common'
1198 00:09:22.768407 Disconnecting from shell: Finalise
1199 00:09:22.768694 =>
1200 00:09:22.869351 end: 4.2 read-feedback (duration 00:00:01) [common]
1201 00:09:22.869692 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/968427
1202 00:09:25.526997 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/968427
1203 00:09:25.527615 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.