Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 23:52:26.749536 lava-dispatcher, installed at version: 2024.01
2 23:52:26.750582 start: 0 validate
3 23:52:26.751075 Start time: 2024-11-09 23:52:26.751046+00:00 (UTC)
4 23:52:26.751621 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:52:26.752192 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:52:26.795287 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:52:26.795829 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 23:52:26.830815 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:52:26.831436 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 23:52:26.862699 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:52:26.863191 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 23:52:26.901247 validate duration: 0.15
14 23:52:26.902062 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:52:26.902397 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:52:26.902701 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:52:26.903277 Not decompressing ramdisk as can be used compressed.
18 23:52:26.903691 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 23:52:26.903932 saving as /var/lib/lava/dispatcher/tmp/968285/tftp-deploy-beb998v9/ramdisk/rootfs.cpio.gz
20 23:52:26.904211 total size: 47897469 (45 MB)
21 23:52:26.939045 progress 0 % (0 MB)
22 23:52:26.970889 progress 5 % (2 MB)
23 23:52:27.002061 progress 10 % (4 MB)
24 23:52:27.033082 progress 15 % (6 MB)
25 23:52:27.064337 progress 20 % (9 MB)
26 23:52:27.095045 progress 25 % (11 MB)
27 23:52:27.125810 progress 30 % (13 MB)
28 23:52:27.156899 progress 35 % (16 MB)
29 23:52:27.187472 progress 40 % (18 MB)
30 23:52:27.217401 progress 45 % (20 MB)
31 23:52:27.247287 progress 50 % (22 MB)
32 23:52:27.277965 progress 55 % (25 MB)
33 23:52:27.308371 progress 60 % (27 MB)
34 23:52:27.340967 progress 65 % (29 MB)
35 23:52:27.376136 progress 70 % (32 MB)
36 23:52:27.406753 progress 75 % (34 MB)
37 23:52:27.442488 progress 80 % (36 MB)
38 23:52:27.473072 progress 85 % (38 MB)
39 23:52:27.503766 progress 90 % (41 MB)
40 23:52:27.533930 progress 95 % (43 MB)
41 23:52:27.563256 progress 100 % (45 MB)
42 23:52:27.564033 45 MB downloaded in 0.66 s (69.23 MB/s)
43 23:52:27.564615 end: 1.1.1 http-download (duration 00:00:01) [common]
45 23:52:27.565505 end: 1.1 download-retry (duration 00:00:01) [common]
46 23:52:27.565799 start: 1.2 download-retry (timeout 00:09:59) [common]
47 23:52:27.566072 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 23:52:27.566579 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig/gcc-12/kernel/Image
49 23:52:27.566855 saving as /var/lib/lava/dispatcher/tmp/968285/tftp-deploy-beb998v9/kernel/Image
50 23:52:27.567064 total size: 45713920 (43 MB)
51 23:52:27.567277 No compression specified
52 23:52:27.598602 progress 0 % (0 MB)
53 23:52:27.626821 progress 5 % (2 MB)
54 23:52:27.656650 progress 10 % (4 MB)
55 23:52:27.685398 progress 15 % (6 MB)
56 23:52:27.714194 progress 20 % (8 MB)
57 23:52:27.743539 progress 25 % (10 MB)
58 23:52:27.771758 progress 30 % (13 MB)
59 23:52:27.800915 progress 35 % (15 MB)
60 23:52:27.830698 progress 40 % (17 MB)
61 23:52:27.859847 progress 45 % (19 MB)
62 23:52:27.888732 progress 50 % (21 MB)
63 23:52:27.917510 progress 55 % (24 MB)
64 23:52:27.946441 progress 60 % (26 MB)
65 23:52:27.974647 progress 65 % (28 MB)
66 23:52:28.003357 progress 70 % (30 MB)
67 23:52:28.032517 progress 75 % (32 MB)
68 23:52:28.060632 progress 80 % (34 MB)
69 23:52:28.089136 progress 85 % (37 MB)
70 23:52:28.118085 progress 90 % (39 MB)
71 23:52:28.146364 progress 95 % (41 MB)
72 23:52:28.174636 progress 100 % (43 MB)
73 23:52:28.175141 43 MB downloaded in 0.61 s (71.70 MB/s)
74 23:52:28.175611 end: 1.2.1 http-download (duration 00:00:01) [common]
76 23:52:28.176456 end: 1.2 download-retry (duration 00:00:01) [common]
77 23:52:28.176731 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:52:28.176992 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:52:28.177465 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 23:52:28.177750 saving as /var/lib/lava/dispatcher/tmp/968285/tftp-deploy-beb998v9/dtb/meson-g12b-a311d-libretech-cc.dtb
81 23:52:28.177961 total size: 54703 (0 MB)
82 23:52:28.178170 No compression specified
83 23:52:28.221309 progress 59 % (0 MB)
84 23:52:28.222224 progress 100 % (0 MB)
85 23:52:28.222852 0 MB downloaded in 0.04 s (1.16 MB/s)
86 23:52:28.223391 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:52:28.224350 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:52:28.224648 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:52:28.224931 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:52:28.225444 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig/gcc-12/modules.tar.xz
92 23:52:28.225711 saving as /var/lib/lava/dispatcher/tmp/968285/tftp-deploy-beb998v9/modules/modules.tar
93 23:52:28.225925 total size: 11611856 (11 MB)
94 23:52:28.226145 Using unxz to decompress xz
95 23:52:28.267037 progress 0 % (0 MB)
96 23:52:28.342954 progress 5 % (0 MB)
97 23:52:28.430116 progress 10 % (1 MB)
98 23:52:28.541068 progress 15 % (1 MB)
99 23:52:28.644293 progress 20 % (2 MB)
100 23:52:28.732068 progress 25 % (2 MB)
101 23:52:28.815365 progress 30 % (3 MB)
102 23:52:28.901737 progress 35 % (3 MB)
103 23:52:28.981799 progress 40 % (4 MB)
104 23:52:29.067539 progress 45 % (5 MB)
105 23:52:29.160800 progress 50 % (5 MB)
106 23:52:29.245760 progress 55 % (6 MB)
107 23:52:29.339478 progress 60 % (6 MB)
108 23:52:29.427375 progress 65 % (7 MB)
109 23:52:29.507297 progress 70 % (7 MB)
110 23:52:29.587378 progress 75 % (8 MB)
111 23:52:29.671113 progress 80 % (8 MB)
112 23:52:29.750227 progress 85 % (9 MB)
113 23:52:29.827914 progress 90 % (9 MB)
114 23:52:29.904693 progress 95 % (10 MB)
115 23:52:29.980706 progress 100 % (11 MB)
116 23:52:29.993261 11 MB downloaded in 1.77 s (6.27 MB/s)
117 23:52:29.994115 end: 1.4.1 http-download (duration 00:00:02) [common]
119 23:52:29.995706 end: 1.4 download-retry (duration 00:00:02) [common]
120 23:52:29.996282 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 23:52:29.996805 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 23:52:29.997291 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:52:29.997791 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 23:52:29.998777 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3
125 23:52:29.999602 makedir: /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin
126 23:52:30.000268 makedir: /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/tests
127 23:52:30.000876 makedir: /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/results
128 23:52:30.001483 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-add-keys
129 23:52:30.002396 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-add-sources
130 23:52:30.003303 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-background-process-start
131 23:52:30.004257 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-background-process-stop
132 23:52:30.005237 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-common-functions
133 23:52:30.006132 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-echo-ipv4
134 23:52:30.007013 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-install-packages
135 23:52:30.007920 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-installed-packages
136 23:52:30.008837 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-os-build
137 23:52:30.009731 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-probe-channel
138 23:52:30.010641 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-probe-ip
139 23:52:30.011504 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-target-ip
140 23:52:30.012420 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-target-mac
141 23:52:30.013317 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-target-storage
142 23:52:30.014319 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-test-case
143 23:52:30.015217 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-test-event
144 23:52:30.016188 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-test-feedback
145 23:52:30.017139 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-test-raise
146 23:52:30.018053 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-test-reference
147 23:52:30.018939 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-test-runner
148 23:52:30.019821 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-test-set
149 23:52:30.020746 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-test-shell
150 23:52:30.021636 Updating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-install-packages (oe)
151 23:52:30.022581 Updating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/bin/lava-installed-packages (oe)
152 23:52:30.023385 Creating /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/environment
153 23:52:30.024119 LAVA metadata
154 23:52:30.024618 - LAVA_JOB_ID=968285
155 23:52:30.025041 - LAVA_DISPATCHER_IP=192.168.6.2
156 23:52:30.025701 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 23:52:30.027488 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 23:52:30.028109 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 23:52:30.028526 skipped lava-vland-overlay
160 23:52:30.029011 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 23:52:30.029510 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 23:52:30.029933 skipped lava-multinode-overlay
163 23:52:30.030410 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 23:52:30.030904 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 23:52:30.031376 Loading test definitions
166 23:52:30.031910 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 23:52:30.032377 Using /lava-968285 at stage 0
168 23:52:30.034494 uuid=968285_1.5.2.4.1 testdef=None
169 23:52:30.035057 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 23:52:30.035568 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 23:52:30.037578 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 23:52:30.038381 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 23:52:30.040538 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 23:52:30.041368 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 23:52:30.043430 runner path: /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/0/tests/0_igt-gpu-panfrost test_uuid 968285_1.5.2.4.1
178 23:52:30.044014 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 23:52:30.044820 Creating lava-test-runner.conf files
181 23:52:30.045025 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/968285/lava-overlay-wx7x74l3/lava-968285/0 for stage 0
182 23:52:30.045361 - 0_igt-gpu-panfrost
183 23:52:30.045702 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 23:52:30.045977 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 23:52:30.069485 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 23:52:30.069859 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 23:52:30.070121 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 23:52:30.070385 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 23:52:30.070647 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 23:52:37.267143 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 23:52:37.267619 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 23:52:37.267877 extracting modules file /var/lib/lava/dispatcher/tmp/968285/tftp-deploy-beb998v9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/968285/extract-overlay-ramdisk-3gt55lyx/ramdisk
193 23:52:38.927940 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 23:52:38.928550 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 23:52:38.928889 [common] Applying overlay /var/lib/lava/dispatcher/tmp/968285/compress-overlay-_remiu3n/overlay-1.5.2.5.tar.gz to ramdisk
196 23:52:38.929151 [common] Applying overlay /var/lib/lava/dispatcher/tmp/968285/compress-overlay-_remiu3n/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/968285/extract-overlay-ramdisk-3gt55lyx/ramdisk
197 23:52:38.966619 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 23:52:38.967165 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 23:52:38.967498 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 23:52:38.967780 Converting downloaded kernel to a uImage
201 23:52:38.968207 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/968285/tftp-deploy-beb998v9/kernel/Image /var/lib/lava/dispatcher/tmp/968285/tftp-deploy-beb998v9/kernel/uImage
202 23:52:39.438462 output: Image Name:
203 23:52:39.438879 output: Created: Sat Nov 9 23:52:38 2024
204 23:52:39.439089 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 23:52:39.439294 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 23:52:39.439495 output: Load Address: 01080000
207 23:52:39.439695 output: Entry Point: 01080000
208 23:52:39.439896 output:
209 23:52:39.440270 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 23:52:39.440537 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 23:52:39.440806 start: 1.5.7 configure-preseed-file (timeout 00:09:47) [common]
212 23:52:39.441059 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 23:52:39.441312 start: 1.5.8 compress-ramdisk (timeout 00:09:47) [common]
214 23:52:39.441574 Building ramdisk /var/lib/lava/dispatcher/tmp/968285/extract-overlay-ramdisk-3gt55lyx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/968285/extract-overlay-ramdisk-3gt55lyx/ramdisk
215 23:52:46.197469 >> 502414 blocks
216 23:53:08.061943 Adding RAMdisk u-boot header.
217 23:53:08.062403 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/968285/extract-overlay-ramdisk-3gt55lyx/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/968285/extract-overlay-ramdisk-3gt55lyx/ramdisk.cpio.gz.uboot
218 23:53:08.736793 output: Image Name:
219 23:53:08.737419 output: Created: Sat Nov 9 23:53:08 2024
220 23:53:08.737848 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 23:53:08.738263 output: Data Size: 65716133 Bytes = 64175.91 KiB = 62.67 MiB
222 23:53:08.738672 output: Load Address: 00000000
223 23:53:08.739078 output: Entry Point: 00000000
224 23:53:08.739476 output:
225 23:53:08.740498 rename /var/lib/lava/dispatcher/tmp/968285/extract-overlay-ramdisk-3gt55lyx/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/968285/tftp-deploy-beb998v9/ramdisk/ramdisk.cpio.gz.uboot
226 23:53:08.741229 end: 1.5.8 compress-ramdisk (duration 00:00:29) [common]
227 23:53:08.741784 end: 1.5 prepare-tftp-overlay (duration 00:00:39) [common]
228 23:53:08.742362 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:18) [common]
229 23:53:08.742827 No LXC device requested
230 23:53:08.743338 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 23:53:08.743851 start: 1.7 deploy-device-env (timeout 00:09:18) [common]
232 23:53:08.744390 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 23:53:08.744811 Checking files for TFTP limit of 4294967296 bytes.
234 23:53:08.747473 end: 1 tftp-deploy (duration 00:00:42) [common]
235 23:53:08.748076 start: 2 uboot-action (timeout 00:05:00) [common]
236 23:53:08.748621 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 23:53:08.749128 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 23:53:08.749633 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 23:53:08.750167 Using kernel file from prepare-kernel: 968285/tftp-deploy-beb998v9/kernel/uImage
240 23:53:08.750779 substitutions:
241 23:53:08.751193 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 23:53:08.751599 - {DTB_ADDR}: 0x01070000
243 23:53:08.752024 - {DTB}: 968285/tftp-deploy-beb998v9/dtb/meson-g12b-a311d-libretech-cc.dtb
244 23:53:08.752436 - {INITRD}: 968285/tftp-deploy-beb998v9/ramdisk/ramdisk.cpio.gz.uboot
245 23:53:08.752838 - {KERNEL_ADDR}: 0x01080000
246 23:53:08.753234 - {KERNEL}: 968285/tftp-deploy-beb998v9/kernel/uImage
247 23:53:08.753630 - {LAVA_MAC}: None
248 23:53:08.754067 - {PRESEED_CONFIG}: None
249 23:53:08.754468 - {PRESEED_LOCAL}: None
250 23:53:08.754859 - {RAMDISK_ADDR}: 0x08000000
251 23:53:08.755250 - {RAMDISK}: 968285/tftp-deploy-beb998v9/ramdisk/ramdisk.cpio.gz.uboot
252 23:53:08.755646 - {ROOT_PART}: None
253 23:53:08.756062 - {ROOT}: None
254 23:53:08.756462 - {SERVER_IP}: 192.168.6.2
255 23:53:08.756860 - {TEE_ADDR}: 0x83000000
256 23:53:08.757253 - {TEE}: None
257 23:53:08.757645 Parsed boot commands:
258 23:53:08.758025 - setenv autoload no
259 23:53:08.758412 - setenv initrd_high 0xffffffff
260 23:53:08.758801 - setenv fdt_high 0xffffffff
261 23:53:08.759186 - dhcp
262 23:53:08.759573 - setenv serverip 192.168.6.2
263 23:53:08.759961 - tftpboot 0x01080000 968285/tftp-deploy-beb998v9/kernel/uImage
264 23:53:08.760377 - tftpboot 0x08000000 968285/tftp-deploy-beb998v9/ramdisk/ramdisk.cpio.gz.uboot
265 23:53:08.760771 - tftpboot 0x01070000 968285/tftp-deploy-beb998v9/dtb/meson-g12b-a311d-libretech-cc.dtb
266 23:53:08.761162 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 23:53:08.761556 - bootm 0x01080000 0x08000000 0x01070000
268 23:53:08.762061 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 23:53:08.763553 start: 2.3 connect-device (timeout 00:05:00) [common]
271 23:53:08.764024 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 23:53:08.778109 Setting prompt string to ['lava-test: # ']
273 23:53:08.779595 end: 2.3 connect-device (duration 00:00:00) [common]
274 23:53:08.780269 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 23:53:08.780848 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 23:53:08.781425 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 23:53:08.782642 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 23:53:08.819113 >> OK - accepted request
279 23:53:08.820995 Returned 0 in 0 seconds
280 23:53:08.922078 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 23:53:08.923672 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 23:53:08.924291 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 23:53:08.924820 Setting prompt string to ['Hit any key to stop autoboot']
285 23:53:08.925277 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 23:53:08.926851 Trying 192.168.56.21...
287 23:53:08.927325 Connected to conserv1.
288 23:53:08.927749 Escape character is '^]'.
289 23:53:08.928197
290 23:53:08.928634 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 23:53:08.929070
292 23:53:20.076208 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 23:53:20.076871 bl2_stage_init 0x01
294 23:53:20.077318 bl2_stage_init 0x81
295 23:53:20.081897 hw id: 0x0000 - pwm id 0x01
296 23:53:20.082459 bl2_stage_init 0xc1
297 23:53:20.082879 bl2_stage_init 0x02
298 23:53:20.083281
299 23:53:20.087285 L0:00000000
300 23:53:20.087735 L1:20000703
301 23:53:20.088169 L2:00008067
302 23:53:20.088557 L3:14000000
303 23:53:20.090252 B2:00402000
304 23:53:20.090670 B1:e0f83180
305 23:53:20.091066
306 23:53:20.091452 TE: 58159
307 23:53:20.091833
308 23:53:20.101296 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 23:53:20.101732
310 23:53:20.102119 Board ID = 1
311 23:53:20.102498 Set A53 clk to 24M
312 23:53:20.102876 Set A73 clk to 24M
313 23:53:20.106996 Set clk81 to 24M
314 23:53:20.107414 A53 clk: 1200 MHz
315 23:53:20.107797 A73 clk: 1200 MHz
316 23:53:20.110449 CLK81: 166.6M
317 23:53:20.110861 smccc: 00012ab5
318 23:53:20.116038 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 23:53:20.121623 board id: 1
320 23:53:20.126885 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 23:53:20.137463 fw parse done
322 23:53:20.143480 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 23:53:20.186002 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 23:53:20.196971 PIEI prepare done
325 23:53:20.197458 fastboot data load
326 23:53:20.197851 fastboot data verify
327 23:53:20.202536 verify result: 266
328 23:53:20.208167 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 23:53:20.208655 LPDDR4 probe
330 23:53:20.209080 ddr clk to 1584MHz
331 23:53:20.216178 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 23:53:20.253388
333 23:53:20.253849 dmc_version 0001
334 23:53:20.260068 Check phy result
335 23:53:20.265889 INFO : End of CA training
336 23:53:20.266323 INFO : End of initialization
337 23:53:20.271512 INFO : Training has run successfully!
338 23:53:20.271947 Check phy result
339 23:53:20.277094 INFO : End of initialization
340 23:53:20.277527 INFO : End of read enable training
341 23:53:20.282802 INFO : End of fine write leveling
342 23:53:20.288382 INFO : End of Write leveling coarse delay
343 23:53:20.288811 INFO : Training has run successfully!
344 23:53:20.289214 Check phy result
345 23:53:20.293959 INFO : End of initialization
346 23:53:20.294389 INFO : End of read dq deskew training
347 23:53:20.299556 INFO : End of MPR read delay center optimization
348 23:53:20.305129 INFO : End of write delay center optimization
349 23:53:20.310829 INFO : End of read delay center optimization
350 23:53:20.311264 INFO : End of max read latency training
351 23:53:20.316375 INFO : Training has run successfully!
352 23:53:20.316816 1D training succeed
353 23:53:20.325577 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 23:53:20.373196 Check phy result
355 23:53:20.373681 INFO : End of initialization
356 23:53:20.394772 INFO : End of 2D read delay Voltage center optimization
357 23:53:20.414835 INFO : End of 2D read delay Voltage center optimization
358 23:53:20.466760 INFO : End of 2D write delay Voltage center optimization
359 23:53:20.516112 INFO : End of 2D write delay Voltage center optimization
360 23:53:20.521568 INFO : Training has run successfully!
361 23:53:20.521888
362 23:53:20.522115 channel==0
363 23:53:20.527137 RxClkDly_Margin_A0==88 ps 9
364 23:53:20.527644 TxDqDly_Margin_A0==98 ps 10
365 23:53:20.530379 RxClkDly_Margin_A1==88 ps 9
366 23:53:20.530623 TxDqDly_Margin_A1==98 ps 10
367 23:53:20.536026 TrainedVREFDQ_A0==74
368 23:53:20.536476 TrainedVREFDQ_A1==74
369 23:53:20.541629 VrefDac_Margin_A0==25
370 23:53:20.541888 DeviceVref_Margin_A0==40
371 23:53:20.542316 VrefDac_Margin_A1==25
372 23:53:20.547247 DeviceVref_Margin_A1==40
373 23:53:20.547575
374 23:53:20.547793
375 23:53:20.548052 channel==1
376 23:53:20.548290 RxClkDly_Margin_A0==98 ps 10
377 23:53:20.550691 TxDqDly_Margin_A0==88 ps 9
378 23:53:20.556167 RxClkDly_Margin_A1==98 ps 10
379 23:53:20.556436 TxDqDly_Margin_A1==88 ps 9
380 23:53:20.556841 TrainedVREFDQ_A0==76
381 23:53:20.561761 TrainedVREFDQ_A1==77
382 23:53:20.562211 VrefDac_Margin_A0==22
383 23:53:20.567498 DeviceVref_Margin_A0==38
384 23:53:20.568042 VrefDac_Margin_A1==22
385 23:53:20.568468 DeviceVref_Margin_A1==37
386 23:53:20.568880
387 23:53:20.573067 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 23:53:20.573530
389 23:53:20.606769 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 23:53:20.607325 2D training succeed
391 23:53:20.612101 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 23:53:20.617765 auto size-- 65535DDR cs0 size: 2048MB
393 23:53:20.618207 DDR cs1 size: 2048MB
394 23:53:20.623311 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 23:53:20.623748 cs0 DataBus test pass
396 23:53:20.624166 cs1 DataBus test pass
397 23:53:20.628901 cs0 AddrBus test pass
398 23:53:20.629203 cs1 AddrBus test pass
399 23:53:20.629612
400 23:53:20.634550 100bdlr_step_size ps== 420
401 23:53:20.635092 result report
402 23:53:20.635509 boot times 0Enable ddr reg access
403 23:53:20.644375 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 23:53:20.657870 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 23:53:21.229785 0.0;M3 CHK:0;cm4_sp_mode 0
406 23:53:21.230212 MVN_1=0x00000000
407 23:53:21.235259 MVN_2=0x00000000
408 23:53:21.241029 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 23:53:21.241326 OPS=0x10
410 23:53:21.241551 ring efuse init
411 23:53:21.241765 chipver efuse init
412 23:53:21.249323 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 23:53:21.249639 [0.018961 Inits done]
414 23:53:21.249859 secure task start!
415 23:53:21.256875 high task start!
416 23:53:21.257157 low task start!
417 23:53:21.257373 run into bl31
418 23:53:21.263581 NOTICE: BL31: v1.3(release):4fc40b1
419 23:53:21.270463 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 23:53:21.270772 NOTICE: BL31: G12A normal boot!
421 23:53:21.296867 NOTICE: BL31: BL33 decompress pass
422 23:53:21.302483 ERROR: Error initializing runtime service opteed_fast
423 23:53:22.535253
424 23:53:22.535713
425 23:53:22.543685 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 23:53:22.544114
427 23:53:22.544342 Model: Libre Computer AML-A311D-CC Alta
428 23:53:22.752264 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 23:53:22.775476 DRAM: 2 GiB (effective 3.8 GiB)
430 23:53:22.918592 Core: 408 devices, 31 uclasses, devicetree: separate
431 23:53:22.924384 WDT: Not starting watchdog@f0d0
432 23:53:22.956626 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 23:53:22.969105 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 23:53:22.974148 ** Bad device specification mmc 0 **
435 23:53:22.984433 Card did not respond to voltage select! : -110
436 23:53:22.992150 ** Bad device specification mmc 0 **
437 23:53:22.992589 Couldn't find partition mmc 0
438 23:53:23.000358 Card did not respond to voltage select! : -110
439 23:53:23.005943 ** Bad device specification mmc 0 **
440 23:53:23.006407 Couldn't find partition mmc 0
441 23:53:23.011016 Error: could not access storage.
442 23:53:24.276577 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 23:53:24.277220 bl2_stage_init 0x81
444 23:53:24.282176 hw id: 0x0000 - pwm id 0x01
445 23:53:24.282666 bl2_stage_init 0xc1
446 23:53:24.283077 bl2_stage_init 0x02
447 23:53:24.283478
448 23:53:24.287845 L0:00000000
449 23:53:24.288382 L1:20000703
450 23:53:24.288798 L2:00008067
451 23:53:24.289200 L3:14000000
452 23:53:24.289597 B2:00402000
453 23:53:24.293420 B1:e0f83180
454 23:53:24.293878
455 23:53:24.294285 TE: 58150
456 23:53:24.294685
457 23:53:24.298955 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 23:53:24.299422
459 23:53:24.299829 Board ID = 1
460 23:53:24.304580 Set A53 clk to 24M
461 23:53:24.305038 Set A73 clk to 24M
462 23:53:24.305441 Set clk81 to 24M
463 23:53:24.310152 A53 clk: 1200 MHz
464 23:53:24.310609 A73 clk: 1200 MHz
465 23:53:24.311012 CLK81: 166.6M
466 23:53:24.311405 smccc: 00012aab
467 23:53:24.315751 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 23:53:24.321380 board id: 1
469 23:53:24.327185 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 23:53:24.337830 fw parse done
471 23:53:24.343806 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 23:53:24.386535 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 23:53:24.397436 PIEI prepare done
474 23:53:24.397921 fastboot data load
475 23:53:24.398327 fastboot data verify
476 23:53:24.402941 verify result: 266
477 23:53:24.408544 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 23:53:24.409016 LPDDR4 probe
479 23:53:24.409422 ddr clk to 1584MHz
480 23:53:24.416571 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 23:53:24.453836
482 23:53:24.454349 dmc_version 0001
483 23:53:24.460518 Check phy result
484 23:53:24.466314 INFO : End of CA training
485 23:53:24.466783 INFO : End of initialization
486 23:53:24.471918 INFO : Training has run successfully!
487 23:53:24.472437 Check phy result
488 23:53:24.477526 INFO : End of initialization
489 23:53:24.478012 INFO : End of read enable training
490 23:53:24.483115 INFO : End of fine write leveling
491 23:53:24.488786 INFO : End of Write leveling coarse delay
492 23:53:24.489288 INFO : Training has run successfully!
493 23:53:24.489692 Check phy result
494 23:53:24.494329 INFO : End of initialization
495 23:53:24.494802 INFO : End of read dq deskew training
496 23:53:24.500001 INFO : End of MPR read delay center optimization
497 23:53:24.505558 INFO : End of write delay center optimization
498 23:53:24.511162 INFO : End of read delay center optimization
499 23:53:24.511645 INFO : End of max read latency training
500 23:53:24.516764 INFO : Training has run successfully!
501 23:53:24.517245 1D training succeed
502 23:53:24.525890 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 23:53:24.573603 Check phy result
504 23:53:24.574158 INFO : End of initialization
505 23:53:24.596150 INFO : End of 2D read delay Voltage center optimization
506 23:53:24.616373 INFO : End of 2D read delay Voltage center optimization
507 23:53:24.668359 INFO : End of 2D write delay Voltage center optimization
508 23:53:24.717756 INFO : End of 2D write delay Voltage center optimization
509 23:53:24.723365 INFO : Training has run successfully!
510 23:53:24.724067
511 23:53:24.724641 channel==0
512 23:53:24.728883 RxClkDly_Margin_A0==88 ps 9
513 23:53:24.729347 TxDqDly_Margin_A0==98 ps 10
514 23:53:24.734490 RxClkDly_Margin_A1==78 ps 8
515 23:53:24.734942 TxDqDly_Margin_A1==98 ps 10
516 23:53:24.735349 TrainedVREFDQ_A0==74
517 23:53:24.740122 TrainedVREFDQ_A1==74
518 23:53:24.740741 VrefDac_Margin_A0==24
519 23:53:24.741287 DeviceVref_Margin_A0==40
520 23:53:24.745665 VrefDac_Margin_A1==25
521 23:53:24.746123 DeviceVref_Margin_A1==40
522 23:53:24.746530
523 23:53:24.746932
524 23:53:24.751367 channel==1
525 23:53:24.751838 RxClkDly_Margin_A0==98 ps 10
526 23:53:24.752282 TxDqDly_Margin_A0==98 ps 10
527 23:53:24.756870 RxClkDly_Margin_A1==98 ps 10
528 23:53:24.757324 TxDqDly_Margin_A1==88 ps 9
529 23:53:24.762454 TrainedVREFDQ_A0==77
530 23:53:24.762914 TrainedVREFDQ_A1==77
531 23:53:24.763319 VrefDac_Margin_A0==22
532 23:53:24.768072 DeviceVref_Margin_A0==37
533 23:53:24.768525 VrefDac_Margin_A1==22
534 23:53:24.773659 DeviceVref_Margin_A1==37
535 23:53:24.774110
536 23:53:24.774517 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 23:53:24.779340
538 23:53:24.807317 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000016 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
539 23:53:24.807847 2D training succeed
540 23:53:24.812866 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 23:53:24.818480 auto size-- 65535DDR cs0 size: 2048MB
542 23:53:24.818943 DDR cs1 size: 2048MB
543 23:53:24.824161 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 23:53:24.824731 cs0 DataBus test pass
545 23:53:24.829606 cs1 DataBus test pass
546 23:53:24.830101 cs0 AddrBus test pass
547 23:53:24.830561 cs1 AddrBus test pass
548 23:53:24.831008
549 23:53:24.835184 100bdlr_step_size ps== 420
550 23:53:24.835684 result report
551 23:53:24.840783 boot times 0Enable ddr reg access
552 23:53:24.846236 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 23:53:24.859724 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 23:53:25.433639 0.0;M3 CHK:0;cm4_sp_mode 0
555 23:53:25.434324 MVN_1=0x00000000
556 23:53:25.438954 MVN_2=0x00000000
557 23:53:25.444716 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 23:53:25.445283 OPS=0x10
559 23:53:25.445759 ring efuse init
560 23:53:25.446252 chipver efuse init
561 23:53:25.450369 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 23:53:25.455903 [0.018961 Inits done]
563 23:53:25.456444 secure task start!
564 23:53:25.456878 high task start!
565 23:53:25.460551 low task start!
566 23:53:25.461033 run into bl31
567 23:53:25.467144 NOTICE: BL31: v1.3(release):4fc40b1
568 23:53:25.474940 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 23:53:25.475424 NOTICE: BL31: G12A normal boot!
570 23:53:25.500421 NOTICE: BL31: BL33 decompress pass
571 23:53:25.506067 ERROR: Error initializing runtime service opteed_fast
572 23:53:26.739199
573 23:53:26.739874
574 23:53:26.747572 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 23:53:26.748208
576 23:53:26.748697 Model: Libre Computer AML-A311D-CC Alta
577 23:53:26.956318 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 23:53:26.979456 DRAM: 2 GiB (effective 3.8 GiB)
579 23:53:27.122417 Core: 408 devices, 31 uclasses, devicetree: separate
580 23:53:27.128227 WDT: Not starting watchdog@f0d0
581 23:53:27.160475 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 23:53:27.172872 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 23:53:27.178034 ** Bad device specification mmc 0 **
584 23:53:27.188248 Card did not respond to voltage select! : -110
585 23:53:27.195933 ** Bad device specification mmc 0 **
586 23:53:27.196439 Couldn't find partition mmc 0
587 23:53:27.204265 Card did not respond to voltage select! : -110
588 23:53:27.209733 ** Bad device specification mmc 0 **
589 23:53:27.210212 Couldn't find partition mmc 0
590 23:53:27.214754 Error: could not access storage.
591 23:53:27.557349 Net: eth0: ethernet@ff3f0000
592 23:53:27.557959 starting USB...
593 23:53:27.809234 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 23:53:27.809837 Starting the controller
595 23:53:27.816210 USB XHCI 1.10
596 23:53:29.526946 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
597 23:53:29.527592 bl2_stage_init 0x81
598 23:53:29.532445 hw id: 0x0000 - pwm id 0x01
599 23:53:29.532935 bl2_stage_init 0xc1
600 23:53:29.533349 bl2_stage_init 0x02
601 23:53:29.533753
602 23:53:29.538247 L0:00000000
603 23:53:29.538731 L1:20000703
604 23:53:29.539138 L2:00008067
605 23:53:29.539536 L3:14000000
606 23:53:29.539931 B2:00402000
607 23:53:29.543742 B1:e0f83180
608 23:53:29.544252
609 23:53:29.544663 TE: 58150
610 23:53:29.545063
611 23:53:29.549257 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
612 23:53:29.549742
613 23:53:29.550152 Board ID = 1
614 23:53:29.554928 Set A53 clk to 24M
615 23:53:29.555406 Set A73 clk to 24M
616 23:53:29.555811 Set clk81 to 24M
617 23:53:29.560496 A53 clk: 1200 MHz
618 23:53:29.560972 A73 clk: 1200 MHz
619 23:53:29.561376 CLK81: 166.6M
620 23:53:29.561774 smccc: 00012aab
621 23:53:29.566162 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
622 23:53:29.571627 board id: 1
623 23:53:29.577691 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
624 23:53:29.588040 fw parse done
625 23:53:29.593992 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
626 23:53:29.636643 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
627 23:53:29.647609 PIEI prepare done
628 23:53:29.648355 fastboot data load
629 23:53:29.648921 fastboot data verify
630 23:53:29.653295 verify result: 266
631 23:53:29.658833 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
632 23:53:29.659456 LPDDR4 probe
633 23:53:29.660030 ddr clk to 1584MHz
634 23:53:29.666723 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
635 23:53:29.704119
636 23:53:29.704765 dmc_version 0001
637 23:53:29.710855 Check phy result
638 23:53:29.716637 INFO : End of CA training
639 23:53:29.717254 INFO : End of initialization
640 23:53:29.722337 INFO : Training has run successfully!
641 23:53:29.722952 Check phy result
642 23:53:29.727828 INFO : End of initialization
643 23:53:29.728338 INFO : End of read enable training
644 23:53:29.731136 INFO : End of fine write leveling
645 23:53:29.736679 INFO : End of Write leveling coarse delay
646 23:53:29.742325 INFO : Training has run successfully!
647 23:53:29.742935 Check phy result
648 23:53:29.743461 INFO : End of initialization
649 23:53:29.747937 INFO : End of read dq deskew training
650 23:53:29.753554 INFO : End of MPR read delay center optimization
651 23:53:29.754169 INFO : End of write delay center optimization
652 23:53:29.759143 INFO : End of read delay center optimization
653 23:53:29.764748 INFO : End of max read latency training
654 23:53:29.765344 INFO : Training has run successfully!
655 23:53:29.770257 1D training succeed
656 23:53:29.776301 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
657 23:53:29.823830 Check phy result
658 23:53:29.824548 INFO : End of initialization
659 23:53:29.845572 INFO : End of 2D read delay Voltage center optimization
660 23:53:29.865790 INFO : End of 2D read delay Voltage center optimization
661 23:53:29.917953 INFO : End of 2D write delay Voltage center optimization
662 23:53:29.967268 INFO : End of 2D write delay Voltage center optimization
663 23:53:29.972866 INFO : Training has run successfully!
664 23:53:29.973482
665 23:53:29.974020 channel==0
666 23:53:29.978355 RxClkDly_Margin_A0==88 ps 9
667 23:53:29.978952 TxDqDly_Margin_A0==98 ps 10
668 23:53:29.984102 RxClkDly_Margin_A1==88 ps 9
669 23:53:29.984713 TxDqDly_Margin_A1==98 ps 10
670 23:53:29.985254 TrainedVREFDQ_A0==74
671 23:53:29.989658 TrainedVREFDQ_A1==74
672 23:53:29.990269 VrefDac_Margin_A0==25
673 23:53:29.990798 DeviceVref_Margin_A0==40
674 23:53:29.995348 VrefDac_Margin_A1==25
675 23:53:29.995959 DeviceVref_Margin_A1==40
676 23:53:29.996521
677 23:53:29.997037
678 23:53:30.000861 channel==1
679 23:53:30.001455 RxClkDly_Margin_A0==98 ps 10
680 23:53:30.001983 TxDqDly_Margin_A0==98 ps 10
681 23:53:30.006418 RxClkDly_Margin_A1==98 ps 10
682 23:53:30.007028 TxDqDly_Margin_A1==88 ps 9
683 23:53:30.012128 TrainedVREFDQ_A0==77
684 23:53:30.012659 TrainedVREFDQ_A1==77
685 23:53:30.013099 VrefDac_Margin_A0==23
686 23:53:30.017553 DeviceVref_Margin_A0==37
687 23:53:30.018059 VrefDac_Margin_A1==22
688 23:53:30.023143 DeviceVref_Margin_A1==37
689 23:53:30.023636
690 23:53:30.024088 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
691 23:53:30.028721
692 23:53:30.056704 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
693 23:53:30.057392 2D training succeed
694 23:53:30.062350 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
695 23:53:30.067911 auto size-- 65535DDR cs0 size: 2048MB
696 23:53:30.068418 DDR cs1 size: 2048MB
697 23:53:30.073525 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
698 23:53:30.073999 cs0 DataBus test pass
699 23:53:30.079172 cs1 DataBus test pass
700 23:53:30.079644 cs0 AddrBus test pass
701 23:53:30.080084 cs1 AddrBus test pass
702 23:53:30.080488
703 23:53:30.084735 100bdlr_step_size ps== 420
704 23:53:30.085213 result report
705 23:53:30.090424 boot times 0Enable ddr reg access
706 23:53:30.094940 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
707 23:53:30.108381 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
708 23:53:30.682835 0.0;M3 CHK:0;cm4_sp_mode 0
709 23:53:30.683431 MVN_1=0x00000000
710 23:53:30.688382 MVN_2=0x00000000
711 23:53:30.694176 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
712 23:53:30.694675 OPS=0x10
713 23:53:30.695071 ring efuse init
714 23:53:30.695455 chipver efuse init
715 23:53:30.699710 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
716 23:53:30.705267 [0.018961 Inits done]
717 23:53:30.705720 secure task start!
718 23:53:30.706108 high task start!
719 23:53:30.709840 low task start!
720 23:53:30.710285 run into bl31
721 23:53:30.716573 NOTICE: BL31: v1.3(release):4fc40b1
722 23:53:30.724369 NOTICE: BL31: Built : 15:58:17, May 22 2019
723 23:53:30.724835 NOTICE: BL31: G12A normal boot!
724 23:53:30.749703 NOTICE: BL31: BL33 decompress pass
725 23:53:30.755359 ERROR: Error initializing runtime service opteed_fast
726 23:53:31.988159
727 23:53:31.988790
728 23:53:31.996558 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
729 23:53:31.997052
730 23:53:31.997465 Model: Libre Computer AML-A311D-CC Alta
731 23:53:32.205011 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
732 23:53:32.228363 DRAM: 2 GiB (effective 3.8 GiB)
733 23:53:32.371346 Core: 408 devices, 31 uclasses, devicetree: separate
734 23:53:32.377230 WDT: Not starting watchdog@f0d0
735 23:53:32.409566 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
736 23:53:32.421929 Loading Environment from FAT... Card did not respond to voltage select! : -110
737 23:53:32.426938 ** Bad device specification mmc 0 **
738 23:53:32.437276 Card did not respond to voltage select! : -110
739 23:53:32.444901 ** Bad device specification mmc 0 **
740 23:53:32.445374 Couldn't find partition mmc 0
741 23:53:32.453229 Card did not respond to voltage select! : -110
742 23:53:32.458771 ** Bad device specification mmc 0 **
743 23:53:32.459241 Couldn't find partition mmc 0
744 23:53:32.463775 Error: could not access storage.
745 23:53:32.806376 Net: eth0: ethernet@ff3f0000
746 23:53:32.806948 starting USB...
747 23:53:33.058097 Bus usb@ff500000: Register 3000140 NbrPorts 3
748 23:53:33.058666 Starting the controller
749 23:53:33.065073 USB XHCI 1.10
750 23:53:35.148463 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
751 23:53:35.149042 bl2_stage_init 0x01
752 23:53:35.149457 bl2_stage_init 0x81
753 23:53:35.154111 hw id: 0x0000 - pwm id 0x01
754 23:53:35.154732 bl2_stage_init 0xc1
755 23:53:35.155271 bl2_stage_init 0x02
756 23:53:35.155803
757 23:53:35.159540 L0:00000000
758 23:53:35.160171 L1:20000703
759 23:53:35.160718 L2:00008067
760 23:53:35.161246 L3:14000000
761 23:53:35.164957 B2:00402000
762 23:53:35.165547 B1:e0f83180
763 23:53:35.166089
764 23:53:35.166618 TE: 58159
765 23:53:35.167139
766 23:53:35.170717 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
767 23:53:35.171306
768 23:53:35.171844 Board ID = 1
769 23:53:35.176264 Set A53 clk to 24M
770 23:53:35.176849 Set A73 clk to 24M
771 23:53:35.177393 Set clk81 to 24M
772 23:53:35.181899 A53 clk: 1200 MHz
773 23:53:35.182487 A73 clk: 1200 MHz
774 23:53:35.183033 CLK81: 166.6M
775 23:53:35.183560 smccc: 00012ab5
776 23:53:35.187354 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
777 23:53:35.193067 board id: 1
778 23:53:35.199137 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
779 23:53:35.209494 fw parse done
780 23:53:35.214728 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
781 23:53:35.258029 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
782 23:53:35.268975 PIEI prepare done
783 23:53:35.269586 fastboot data load
784 23:53:35.270133 fastboot data verify
785 23:53:35.274641 verify result: 266
786 23:53:35.280238 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
787 23:53:35.280808 LPDDR4 probe
788 23:53:35.281334 ddr clk to 1584MHz
789 23:53:35.288178 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
790 23:53:35.325507
791 23:53:35.326098 dmc_version 0001
792 23:53:35.332138 Check phy result
793 23:53:35.338008 INFO : End of CA training
794 23:53:35.338589 INFO : End of initialization
795 23:53:35.343636 INFO : Training has run successfully!
796 23:53:35.344259 Check phy result
797 23:53:35.349275 INFO : End of initialization
798 23:53:35.349839 INFO : End of read enable training
799 23:53:35.354956 INFO : End of fine write leveling
800 23:53:35.360418 INFO : End of Write leveling coarse delay
801 23:53:35.360992 INFO : Training has run successfully!
802 23:53:35.361516 Check phy result
803 23:53:35.366054 INFO : End of initialization
804 23:53:35.366618 INFO : End of read dq deskew training
805 23:53:35.371634 INFO : End of MPR read delay center optimization
806 23:53:35.377200 INFO : End of write delay center optimization
807 23:53:35.382934 INFO : End of read delay center optimization
808 23:53:35.383548 INFO : End of max read latency training
809 23:53:35.388438 INFO : Training has run successfully!
810 23:53:35.389023 1D training succeed
811 23:53:35.397538 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
812 23:53:35.445294 Check phy result
813 23:53:35.445963 INFO : End of initialization
814 23:53:35.467610 INFO : End of 2D read delay Voltage center optimization
815 23:53:35.487701 INFO : End of 2D read delay Voltage center optimization
816 23:53:35.539706 INFO : End of 2D write delay Voltage center optimization
817 23:53:35.588882 INFO : End of 2D write delay Voltage center optimization
818 23:53:35.594434 INFO : Training has run successfully!
819 23:53:35.595052
820 23:53:35.595605 channel==0
821 23:53:35.600059 RxClkDly_Margin_A0==88 ps 9
822 23:53:35.600673 TxDqDly_Margin_A0==98 ps 10
823 23:53:35.605616 RxClkDly_Margin_A1==88 ps 9
824 23:53:35.606205 TxDqDly_Margin_A1==98 ps 10
825 23:53:35.606748 TrainedVREFDQ_A0==74
826 23:53:35.611237 TrainedVREFDQ_A1==74
827 23:53:35.611803 VrefDac_Margin_A0==24
828 23:53:35.612364 DeviceVref_Margin_A0==40
829 23:53:35.616816 VrefDac_Margin_A1==25
830 23:53:35.617398 DeviceVref_Margin_A1==40
831 23:53:35.617923
832 23:53:35.618438
833 23:53:35.622449 channel==1
834 23:53:35.623032 RxClkDly_Margin_A0==98 ps 10
835 23:53:35.623564 TxDqDly_Margin_A0==98 ps 10
836 23:53:35.628006 RxClkDly_Margin_A1==98 ps 10
837 23:53:35.628594 TxDqDly_Margin_A1==88 ps 9
838 23:53:35.633606 TrainedVREFDQ_A0==77
839 23:53:35.634193 TrainedVREFDQ_A1==77
840 23:53:35.634741 VrefDac_Margin_A0==22
841 23:53:35.639202 DeviceVref_Margin_A0==37
842 23:53:35.639778 VrefDac_Margin_A1==22
843 23:53:35.644857 DeviceVref_Margin_A1==37
844 23:53:35.645426
845 23:53:35.645963 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
846 23:53:35.650462
847 23:53:35.678415 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
848 23:53:35.679056 2D training succeed
849 23:53:35.684042 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
850 23:53:35.689808 auto size-- 65535DDR cs0 size: 2048MB
851 23:53:35.690441 DDR cs1 size: 2048MB
852 23:53:35.695291 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
853 23:53:35.695890 cs0 DataBus test pass
854 23:53:35.700897 cs1 DataBus test pass
855 23:53:35.701465 cs0 AddrBus test pass
856 23:53:35.701972 cs1 AddrBus test pass
857 23:53:35.702480
858 23:53:35.706536 100bdlr_step_size ps== 420
859 23:53:35.707128 result report
860 23:53:35.712103 boot times 0Enable ddr reg access
861 23:53:35.717529 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
862 23:53:35.731056 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
863 23:53:36.303057 0.0;M3 CHK:0;cm4_sp_mode 0
864 23:53:36.303860 MVN_1=0x00000000
865 23:53:36.308463 MVN_2=0x00000000
866 23:53:36.314187 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
867 23:53:36.314807 OPS=0x10
868 23:53:36.315359 ring efuse init
869 23:53:36.315892 chipver efuse init
870 23:53:36.319775 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
871 23:53:36.325373 [0.018961 Inits done]
872 23:53:36.325962 secure task start!
873 23:53:36.326486 high task start!
874 23:53:36.330078 low task start!
875 23:53:36.330656 run into bl31
876 23:53:36.336618 NOTICE: BL31: v1.3(release):4fc40b1
877 23:53:36.344456 NOTICE: BL31: Built : 15:58:17, May 22 2019
878 23:53:36.345064 NOTICE: BL31: G12A normal boot!
879 23:53:36.369758 NOTICE: BL31: BL33 decompress pass
880 23:53:36.375442 ERROR: Error initializing runtime service opteed_fast
881 23:53:37.608344
882 23:53:37.609110
883 23:53:37.616761 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
884 23:53:37.617374
885 23:53:37.617915 Model: Libre Computer AML-A311D-CC Alta
886 23:53:37.825154 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
887 23:53:37.848528 DRAM: 2 GiB (effective 3.8 GiB)
888 23:53:37.991524 Core: 408 devices, 31 uclasses, devicetree: separate
889 23:53:37.997392 WDT: Not starting watchdog@f0d0
890 23:53:38.029633 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
891 23:53:38.042090 Loading Environment from FAT... Card did not respond to voltage select! : -110
892 23:53:38.047059 ** Bad device specification mmc 0 **
893 23:53:38.057406 Card did not respond to voltage select! : -110
894 23:53:38.065048 ** Bad device specification mmc 0 **
895 23:53:38.065655 Couldn't find partition mmc 0
896 23:53:38.073399 Card did not respond to voltage select! : -110
897 23:53:38.078885 ** Bad device specification mmc 0 **
898 23:53:38.079489 Couldn't find partition mmc 0
899 23:53:38.083962 Error: could not access storage.
900 23:53:38.426470 Net: eth0: ethernet@ff3f0000
901 23:53:38.427185 starting USB...
902 23:53:38.678343 Bus usb@ff500000: Register 3000140 NbrPorts 3
903 23:53:38.679111 Starting the controller
904 23:53:38.685208 USB XHCI 1.10
905 23:53:40.548303 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
906 23:53:40.549111 bl2_stage_init 0x01
907 23:53:40.549679 bl2_stage_init 0x81
908 23:53:40.553899 hw id: 0x0000 - pwm id 0x01
909 23:53:40.554207 bl2_stage_init 0xc1
910 23:53:40.554431 bl2_stage_init 0x02
911 23:53:40.554643
912 23:53:40.559413 L0:00000000
913 23:53:40.559796 L1:20000703
914 23:53:40.560185 L2:00008067
915 23:53:40.560519 L3:14000000
916 23:53:40.564942 B2:00402000
917 23:53:40.565320 B1:e0f83180
918 23:53:40.565648
919 23:53:40.565968 TE: 58167
920 23:53:40.566287
921 23:53:40.570708 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
922 23:53:40.571000
923 23:53:40.571226 Board ID = 1
924 23:53:40.576293 Set A53 clk to 24M
925 23:53:40.576638 Set A73 clk to 24M
926 23:53:40.576854 Set clk81 to 24M
927 23:53:40.581804 A53 clk: 1200 MHz
928 23:53:40.582059 A73 clk: 1200 MHz
929 23:53:40.582270 CLK81: 166.6M
930 23:53:40.582475 smccc: 00012abd
931 23:53:40.587453 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
932 23:53:40.592849 board id: 1
933 23:53:40.598877 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
934 23:53:40.609597 fw parse done
935 23:53:40.615650 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
936 23:53:40.658050 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
937 23:53:40.668991 PIEI prepare done
938 23:53:40.669448 fastboot data load
939 23:53:40.669860 fastboot data verify
940 23:53:40.674676 verify result: 266
941 23:53:40.680231 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
942 23:53:40.680689 LPDDR4 probe
943 23:53:40.681096 ddr clk to 1584MHz
944 23:53:40.688139 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
945 23:53:40.725419
946 23:53:40.725913 dmc_version 0001
947 23:53:40.732098 Check phy result
948 23:53:40.737954 INFO : End of CA training
949 23:53:40.738396 INFO : End of initialization
950 23:53:40.743628 INFO : Training has run successfully!
951 23:53:40.744117 Check phy result
952 23:53:40.749174 INFO : End of initialization
953 23:53:40.749620 INFO : End of read enable training
954 23:53:40.752534 INFO : End of fine write leveling
955 23:53:40.758100 INFO : End of Write leveling coarse delay
956 23:53:40.763709 INFO : Training has run successfully!
957 23:53:40.764186 Check phy result
958 23:53:40.764574 INFO : End of initialization
959 23:53:40.769292 INFO : End of read dq deskew training
960 23:53:40.774899 INFO : End of MPR read delay center optimization
961 23:53:40.775339 INFO : End of write delay center optimization
962 23:53:40.780516 INFO : End of read delay center optimization
963 23:53:40.786086 INFO : End of max read latency training
964 23:53:40.786530 INFO : Training has run successfully!
965 23:53:40.791716 1D training succeed
966 23:53:40.797601 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
967 23:53:40.845186 Check phy result
968 23:53:40.845680 INFO : End of initialization
969 23:53:40.866828 INFO : End of 2D read delay Voltage center optimization
970 23:53:40.887131 INFO : End of 2D read delay Voltage center optimization
971 23:53:40.939120 INFO : End of 2D write delay Voltage center optimization
972 23:53:40.988477 INFO : End of 2D write delay Voltage center optimization
973 23:53:40.994074 INFO : Training has run successfully!
974 23:53:40.994531
975 23:53:40.994946 channel==0
976 23:53:40.999732 RxClkDly_Margin_A0==88 ps 9
977 23:53:41.000232 TxDqDly_Margin_A0==98 ps 10
978 23:53:41.005295 RxClkDly_Margin_A1==88 ps 9
979 23:53:41.005749 TxDqDly_Margin_A1==98 ps 10
980 23:53:41.006156 TrainedVREFDQ_A0==74
981 23:53:41.010867 TrainedVREFDQ_A1==74
982 23:53:41.011320 VrefDac_Margin_A0==25
983 23:53:41.011724 DeviceVref_Margin_A0==40
984 23:53:41.016484 VrefDac_Margin_A1==25
985 23:53:41.016957 DeviceVref_Margin_A1==40
986 23:53:41.017361
987 23:53:41.017766
988 23:53:41.022134 channel==1
989 23:53:41.022611 RxClkDly_Margin_A0==98 ps 10
990 23:53:41.023023 TxDqDly_Margin_A0==88 ps 9
991 23:53:41.027743 RxClkDly_Margin_A1==98 ps 10
992 23:53:41.028236 TxDqDly_Margin_A1==88 ps 9
993 23:53:41.033283 TrainedVREFDQ_A0==76
994 23:53:41.033743 TrainedVREFDQ_A1==77
995 23:53:41.034149 VrefDac_Margin_A0==22
996 23:53:41.038863 DeviceVref_Margin_A0==38
997 23:53:41.039314 VrefDac_Margin_A1==22
998 23:53:41.044469 DeviceVref_Margin_A1==37
999 23:53:41.044924
1000 23:53:41.045329 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1001 23:53:41.045721
1002 23:53:41.078029 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1003 23:53:41.078536 2D training succeed
1004 23:53:41.083751 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1005 23:53:41.089269 auto size-- 65535DDR cs0 size: 2048MB
1006 23:53:41.089727 DDR cs1 size: 2048MB
1007 23:53:41.094850 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1008 23:53:41.095305 cs0 DataBus test pass
1009 23:53:41.100456 cs1 DataBus test pass
1010 23:53:41.100904 cs0 AddrBus test pass
1011 23:53:41.101305 cs1 AddrBus test pass
1012 23:53:41.101700
1013 23:53:41.106046 100bdlr_step_size ps== 420
1014 23:53:41.106509 result report
1015 23:53:41.111735 boot times 0Enable ddr reg access
1016 23:53:41.116993 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1017 23:53:41.130459 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1018 23:53:41.704273 0.0;M3 CHK:0;cm4_sp_mode 0
1019 23:53:41.704875 MVN_1=0x00000000
1020 23:53:41.709832 MVN_2=0x00000000
1021 23:53:41.715455 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1022 23:53:41.715924 OPS=0x10
1023 23:53:41.716441 ring efuse init
1024 23:53:41.716867 chipver efuse init
1025 23:53:41.721086 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1026 23:53:41.726683 [0.018961 Inits done]
1027 23:53:41.727148 secure task start!
1028 23:53:41.727551 high task start!
1029 23:53:41.731262 low task start!
1030 23:53:41.731718 run into bl31
1031 23:53:41.737925 NOTICE: BL31: v1.3(release):4fc40b1
1032 23:53:41.745748 NOTICE: BL31: Built : 15:58:17, May 22 2019
1033 23:53:41.746216 NOTICE: BL31: G12A normal boot!
1034 23:53:41.771088 NOTICE: BL31: BL33 decompress pass
1035 23:53:41.776756 ERROR: Error initializing runtime service opteed_fast
1036 23:53:43.009574
1037 23:53:43.010173
1038 23:53:43.018117 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1039 23:53:43.018627
1040 23:53:43.019045 Model: Libre Computer AML-A311D-CC Alta
1041 23:53:43.226406 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1042 23:53:43.249809 DRAM: 2 GiB (effective 3.8 GiB)
1043 23:53:43.392818 Core: 408 devices, 31 uclasses, devicetree: separate
1044 23:53:43.398698 WDT: Not starting watchdog@f0d0
1045 23:53:43.430922 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1046 23:53:43.443350 Loading Environment from FAT... Card did not respond to voltage select! : -110
1047 23:53:43.448362 ** Bad device specification mmc 0 **
1048 23:53:43.458707 Card did not respond to voltage select! : -110
1049 23:53:43.466360 ** Bad device specification mmc 0 **
1050 23:53:43.466825 Couldn't find partition mmc 0
1051 23:53:43.474682 Card did not respond to voltage select! : -110
1052 23:53:43.480209 ** Bad device specification mmc 0 **
1053 23:53:43.480686 Couldn't find partition mmc 0
1054 23:53:43.485252 Error: could not access storage.
1055 23:53:43.828791 Net: eth0: ethernet@ff3f0000
1056 23:53:43.829379 starting USB...
1057 23:53:44.080594 Bus usb@ff500000: Register 3000140 NbrPorts 3
1058 23:53:44.081172 Starting the controller
1059 23:53:44.087566 USB XHCI 1.10
1060 23:53:45.641692 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1061 23:53:45.650013 scanning usb for storage devices... 0 Storage Device(s) found
1063 23:53:45.701634 Hit any key to stop autoboot: 1
1064 23:53:45.702865 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1065 23:53:45.703496 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1066 23:53:45.704034 Setting prompt string to ['=>']
1067 23:53:45.704540 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1068 23:53:45.717688 0
1069 23:53:45.718599 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1070 23:53:45.719106 Sending with 10 millisecond of delay
1072 23:53:46.854765 => setenv autoload no
1073 23:53:46.865576 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1074 23:53:46.870495 setenv autoload no
1075 23:53:46.871244 Sending with 10 millisecond of delay
1077 23:53:48.669072 => setenv initrd_high 0xffffffff
1078 23:53:48.679818 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1079 23:53:48.680736 setenv initrd_high 0xffffffff
1080 23:53:48.681456 Sending with 10 millisecond of delay
1082 23:53:50.298385 => setenv fdt_high 0xffffffff
1083 23:53:50.309168 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1084 23:53:50.310062 setenv fdt_high 0xffffffff
1085 23:53:50.310775 Sending with 10 millisecond of delay
1087 23:53:50.602738 => dhcp
1088 23:53:50.613289 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1089 23:53:50.613823 dhcp
1090 23:53:50.614070 Speed: 1000, full duplex
1091 23:53:50.614300 BOOTP broadcast 1
1092 23:53:50.634915 DHCP client bound to address 192.168.6.27 (22 ms)
1093 23:53:50.635722 Sending with 10 millisecond of delay
1095 23:53:52.313517 => setenv serverip 192.168.6.2
1096 23:53:52.324339 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1097 23:53:52.325283 setenv serverip 192.168.6.2
1098 23:53:52.325992 Sending with 10 millisecond of delay
1100 23:53:56.050737 => tftpboot 0x01080000 968285/tftp-deploy-beb998v9/kernel/uImage
1101 23:53:56.061888 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1102 23:53:56.062567 tftpboot 0x01080000 968285/tftp-deploy-beb998v9/kernel/uImage
1103 23:53:56.062860 Speed: 1000, full duplex
1104 23:53:56.063135 Using ethernet@ff3f0000 device
1105 23:53:56.064290 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1106 23:53:56.069864 Filename '968285/tftp-deploy-beb998v9/kernel/uImage'.
1107 23:53:56.073919 Load address: 0x1080000
1108 23:53:59.010400 Loading: *################################################## 43.6 MiB
1109 23:53:59.011022 14.8 MiB/s
1110 23:53:59.011491 done
1111 23:53:59.014722 Bytes transferred = 45713984 (2b98a40 hex)
1112 23:53:59.015558 Sending with 10 millisecond of delay
1114 23:54:03.706390 => tftpboot 0x08000000 968285/tftp-deploy-beb998v9/ramdisk/ramdisk.cpio.gz.uboot
1115 23:54:03.717094 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1116 23:54:03.717607 tftpboot 0x08000000 968285/tftp-deploy-beb998v9/ramdisk/ramdisk.cpio.gz.uboot
1117 23:54:03.717859 Speed: 1000, full duplex
1118 23:54:03.718091 Using ethernet@ff3f0000 device
1119 23:54:03.719324 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1120 23:54:03.730176 Filename '968285/tftp-deploy-beb998v9/ramdisk/ramdisk.cpio.gz.uboot'.
1121 23:54:03.730503 Load address: 0x8000000
1122 23:54:12.996760 Loading: *#######T ########################################## UDP wrong checksum 0000000f 000073dd
1123 23:54:17.996632 T UDP wrong checksum 0000000f 000073dd
1124 23:54:24.997064 T UDP wrong checksum 000000ff 0000ee85
1125 23:54:25.159433 UDP wrong checksum 000000ff 00008978
1126 23:54:27.999788 T UDP wrong checksum 0000000f 000073dd
1127 23:54:32.684244 UDP wrong checksum 000000ff 0000e348
1128 23:54:32.694508 UDP wrong checksum 000000ff 0000773b
1129 23:54:36.363642 T UDP wrong checksum 000000ff 0000ad2e
1130 23:54:36.367797 UDP wrong checksum 000000ff 00003a21
1131 23:54:44.178641 T T UDP wrong checksum 000000ff 00004a11
1132 23:54:44.230103 UDP wrong checksum 000000ff 0000db03
1133 23:54:48.004705 T UDP wrong checksum 0000000f 000073dd
1134 23:54:52.159077 UDP wrong checksum 000000ff 0000d299
1135 23:54:52.171679 UDP wrong checksum 000000ff 0000688c
1136 23:55:03.008744 T T
1137 23:55:03.009579 Retry count exceeded; starting again
1139 23:55:03.011389 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
1142 23:55:03.013922 end: 2.4 uboot-commands (duration 00:01:54) [common]
1144 23:55:03.015711 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1146 23:55:03.017124 end: 2 uboot-action (duration 00:01:54) [common]
1148 23:55:03.019068 Cleaning after the job
1149 23:55:03.019768 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968285/tftp-deploy-beb998v9/ramdisk
1150 23:55:03.021265 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968285/tftp-deploy-beb998v9/kernel
1151 23:55:03.054856 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968285/tftp-deploy-beb998v9/dtb
1152 23:55:03.056752 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968285/tftp-deploy-beb998v9/modules
1153 23:55:03.062506 start: 4.1 power-off (timeout 00:00:30) [common]
1154 23:55:03.063223 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1155 23:55:03.099024 >> OK - accepted request
1156 23:55:03.101011 Returned 0 in 0 seconds
1157 23:55:03.202497 end: 4.1 power-off (duration 00:00:00) [common]
1159 23:55:03.204963 start: 4.2 read-feedback (timeout 00:10:00) [common]
1160 23:55:03.206494 Listened to connection for namespace 'common' for up to 1s
1161 23:55:04.207255 Finalising connection for namespace 'common'
1162 23:55:04.208257 Disconnecting from shell: Finalise
1163 23:55:04.208950 =>
1164 23:55:04.310313 end: 4.2 read-feedback (duration 00:00:01) [common]
1165 23:55:04.311222 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/968285
1166 23:55:04.961934 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/968285
1167 23:55:04.962556 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.