Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 23:44:26.464674 lava-dispatcher, installed at version: 2024.01
2 23:44:26.465468 start: 0 validate
3 23:44:26.465950 Start time: 2024-11-09 23:44:26.465920+00:00 (UTC)
4 23:44:26.466484 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:44:26.467014 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:44:26.515033 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:44:26.515706 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 23:44:26.545787 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:44:26.546447 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 23:44:26.575697 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:44:26.576253 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:44:26.608103 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 23:44:26.608610 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-279-gde2f378f2b77%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 23:44:26.645510 validate duration: 0.18
16 23:44:26.646381 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:44:26.646719 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:44:26.647045 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:44:26.647635 Not decompressing ramdisk as can be used compressed.
20 23:44:26.648118 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 23:44:26.648418 saving as /var/lib/lava/dispatcher/tmp/968274/tftp-deploy-mbxzk2wt/ramdisk/initrd.cpio.gz
22 23:44:26.648694 total size: 5628140 (5 MB)
23 23:44:26.683385 progress 0 % (0 MB)
24 23:44:26.687363 progress 5 % (0 MB)
25 23:44:26.691463 progress 10 % (0 MB)
26 23:44:26.695059 progress 15 % (0 MB)
27 23:44:26.699090 progress 20 % (1 MB)
28 23:44:26.702642 progress 25 % (1 MB)
29 23:44:26.706577 progress 30 % (1 MB)
30 23:44:26.710641 progress 35 % (1 MB)
31 23:44:26.714163 progress 40 % (2 MB)
32 23:44:26.718128 progress 45 % (2 MB)
33 23:44:26.721655 progress 50 % (2 MB)
34 23:44:26.725616 progress 55 % (2 MB)
35 23:44:26.729547 progress 60 % (3 MB)
36 23:44:26.733165 progress 65 % (3 MB)
37 23:44:26.737120 progress 70 % (3 MB)
38 23:44:26.740773 progress 75 % (4 MB)
39 23:44:26.744701 progress 80 % (4 MB)
40 23:44:26.748118 progress 85 % (4 MB)
41 23:44:26.751711 progress 90 % (4 MB)
42 23:44:26.755264 progress 95 % (5 MB)
43 23:44:26.758497 progress 100 % (5 MB)
44 23:44:26.759160 5 MB downloaded in 0.11 s (48.60 MB/s)
45 23:44:26.759725 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:44:26.760641 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:44:26.760938 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:44:26.761212 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:44:26.761689 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig/gcc-12/kernel/Image
51 23:44:26.761945 saving as /var/lib/lava/dispatcher/tmp/968274/tftp-deploy-mbxzk2wt/kernel/Image
52 23:44:26.762156 total size: 45713920 (43 MB)
53 23:44:26.762369 No compression specified
54 23:44:26.795594 progress 0 % (0 MB)
55 23:44:26.823619 progress 5 % (2 MB)
56 23:44:26.852179 progress 10 % (4 MB)
57 23:44:26.880770 progress 15 % (6 MB)
58 23:44:26.909145 progress 20 % (8 MB)
59 23:44:26.937571 progress 25 % (10 MB)
60 23:44:26.965731 progress 30 % (13 MB)
61 23:44:26.993891 progress 35 % (15 MB)
62 23:44:27.022832 progress 40 % (17 MB)
63 23:44:27.051294 progress 45 % (19 MB)
64 23:44:27.079931 progress 50 % (21 MB)
65 23:44:27.108512 progress 55 % (24 MB)
66 23:44:27.137378 progress 60 % (26 MB)
67 23:44:27.165424 progress 65 % (28 MB)
68 23:44:27.193683 progress 70 % (30 MB)
69 23:44:27.222156 progress 75 % (32 MB)
70 23:44:27.250547 progress 80 % (34 MB)
71 23:44:27.278587 progress 85 % (37 MB)
72 23:44:27.307025 progress 90 % (39 MB)
73 23:44:27.335220 progress 95 % (41 MB)
74 23:44:27.362453 progress 100 % (43 MB)
75 23:44:27.363000 43 MB downloaded in 0.60 s (72.56 MB/s)
76 23:44:27.363486 end: 1.2.1 http-download (duration 00:00:01) [common]
78 23:44:27.364342 end: 1.2 download-retry (duration 00:00:01) [common]
79 23:44:27.364621 start: 1.3 download-retry (timeout 00:09:59) [common]
80 23:44:27.364889 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 23:44:27.365364 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 23:44:27.365615 saving as /var/lib/lava/dispatcher/tmp/968274/tftp-deploy-mbxzk2wt/dtb/meson-g12b-a311d-libretech-cc.dtb
83 23:44:27.365824 total size: 54703 (0 MB)
84 23:44:27.366034 No compression specified
85 23:44:27.401490 progress 59 % (0 MB)
86 23:44:27.402389 progress 100 % (0 MB)
87 23:44:27.402941 0 MB downloaded in 0.04 s (1.41 MB/s)
88 23:44:27.403422 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:44:27.404279 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:44:27.404545 start: 1.4 download-retry (timeout 00:09:59) [common]
92 23:44:27.404807 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 23:44:27.405270 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 23:44:27.405514 saving as /var/lib/lava/dispatcher/tmp/968274/tftp-deploy-mbxzk2wt/nfsrootfs/full.rootfs.tar
95 23:44:27.405720 total size: 474398908 (452 MB)
96 23:44:27.405929 Using unxz to decompress xz
97 23:44:27.442230 progress 0 % (0 MB)
98 23:44:28.540461 progress 5 % (22 MB)
99 23:44:29.974819 progress 10 % (45 MB)
100 23:44:30.402324 progress 15 % (67 MB)
101 23:44:31.191844 progress 20 % (90 MB)
102 23:44:31.742901 progress 25 % (113 MB)
103 23:44:32.109672 progress 30 % (135 MB)
104 23:44:32.720679 progress 35 % (158 MB)
105 23:44:33.662504 progress 40 % (181 MB)
106 23:44:34.469157 progress 45 % (203 MB)
107 23:44:35.032524 progress 50 % (226 MB)
108 23:44:35.686235 progress 55 % (248 MB)
109 23:44:36.912897 progress 60 % (271 MB)
110 23:44:38.380605 progress 65 % (294 MB)
111 23:44:40.029767 progress 70 % (316 MB)
112 23:44:43.103300 progress 75 % (339 MB)
113 23:44:45.529457 progress 80 % (361 MB)
114 23:44:48.469241 progress 85 % (384 MB)
115 23:44:51.643004 progress 90 % (407 MB)
116 23:44:54.848568 progress 95 % (429 MB)
117 23:44:58.027158 progress 100 % (452 MB)
118 23:44:58.040269 452 MB downloaded in 30.63 s (14.77 MB/s)
119 23:44:58.040899 end: 1.4.1 http-download (duration 00:00:31) [common]
121 23:44:58.041816 end: 1.4 download-retry (duration 00:00:31) [common]
122 23:44:58.042124 start: 1.5 download-retry (timeout 00:09:29) [common]
123 23:44:58.042426 start: 1.5.1 http-download (timeout 00:09:29) [common]
124 23:44:58.042939 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-279-gde2f378f2b77/arm64/defconfig/gcc-12/modules.tar.xz
125 23:44:58.043216 saving as /var/lib/lava/dispatcher/tmp/968274/tftp-deploy-mbxzk2wt/modules/modules.tar
126 23:44:58.043451 total size: 11611856 (11 MB)
127 23:44:58.043688 Using unxz to decompress xz
128 23:44:58.086306 progress 0 % (0 MB)
129 23:44:58.168162 progress 5 % (0 MB)
130 23:44:58.259459 progress 10 % (1 MB)
131 23:44:58.378835 progress 15 % (1 MB)
132 23:44:58.493985 progress 20 % (2 MB)
133 23:44:58.592117 progress 25 % (2 MB)
134 23:44:58.684858 progress 30 % (3 MB)
135 23:44:58.783053 progress 35 % (3 MB)
136 23:44:58.872596 progress 40 % (4 MB)
137 23:44:58.965808 progress 45 % (5 MB)
138 23:44:59.064225 progress 50 % (5 MB)
139 23:44:59.141701 progress 55 % (6 MB)
140 23:44:59.228185 progress 60 % (6 MB)
141 23:44:59.308677 progress 65 % (7 MB)
142 23:44:59.388805 progress 70 % (7 MB)
143 23:44:59.466673 progress 75 % (8 MB)
144 23:44:59.549885 progress 80 % (8 MB)
145 23:44:59.629506 progress 85 % (9 MB)
146 23:44:59.707340 progress 90 % (9 MB)
147 23:44:59.785540 progress 95 % (10 MB)
148 23:44:59.862264 progress 100 % (11 MB)
149 23:44:59.873813 11 MB downloaded in 1.83 s (6.05 MB/s)
150 23:44:59.874672 end: 1.5.1 http-download (duration 00:00:02) [common]
152 23:44:59.876292 end: 1.5 download-retry (duration 00:00:02) [common]
153 23:44:59.876804 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 23:44:59.877311 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 23:45:15.936180 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/968274/extract-nfsrootfs-k68_a_hf
156 23:45:15.936812 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 23:45:15.937105 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 23:45:15.938145 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h
159 23:45:15.938788 makedir: /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin
160 23:45:15.939466 makedir: /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/tests
161 23:45:15.939964 makedir: /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/results
162 23:45:15.940436 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-add-keys
163 23:45:15.941097 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-add-sources
164 23:45:15.942170 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-background-process-start
165 23:45:15.943054 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-background-process-stop
166 23:45:15.943822 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-common-functions
167 23:45:15.944513 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-echo-ipv4
168 23:45:15.945491 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-install-packages
169 23:45:15.946202 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-installed-packages
170 23:45:15.946871 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-os-build
171 23:45:15.947540 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-probe-channel
172 23:45:15.948273 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-probe-ip
173 23:45:15.948980 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-target-ip
174 23:45:15.949653 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-target-mac
175 23:45:15.950352 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-target-storage
176 23:45:15.951140 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-test-case
177 23:45:15.951821 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-test-event
178 23:45:15.952710 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-test-feedback
179 23:45:15.953405 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-test-raise
180 23:45:15.953973 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-test-reference
181 23:45:15.954504 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-test-runner
182 23:45:15.955027 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-test-set
183 23:45:15.955553 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-test-shell
184 23:45:15.956132 Updating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-install-packages (oe)
185 23:45:15.956770 Updating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/bin/lava-installed-packages (oe)
186 23:45:15.957251 Creating /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/environment
187 23:45:15.957664 LAVA metadata
188 23:45:15.957949 - LAVA_JOB_ID=968274
189 23:45:15.958184 - LAVA_DISPATCHER_IP=192.168.6.2
190 23:45:15.958658 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 23:45:15.959910 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 23:45:15.960363 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 23:45:15.960597 skipped lava-vland-overlay
194 23:45:15.960865 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 23:45:15.961146 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 23:45:15.961393 skipped lava-multinode-overlay
197 23:45:15.961662 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 23:45:15.961947 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 23:45:15.962249 Loading test definitions
200 23:45:15.962568 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 23:45:15.962814 Using /lava-968274 at stage 0
202 23:45:15.964342 uuid=968274_1.6.2.4.1 testdef=None
203 23:45:15.964745 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 23:45:15.965040 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 23:45:15.967495 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 23:45:15.968433 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 23:45:15.971584 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 23:45:15.972582 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 23:45:15.975830 runner path: /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 968274_1.6.2.4.1
212 23:45:15.976642 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 23:45:15.977503 Creating lava-test-runner.conf files
215 23:45:15.977716 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/968274/lava-overlay-dysuc18h/lava-968274/0 for stage 0
216 23:45:15.978124 - 0_v4l2-decoder-conformance-vp9
217 23:45:15.978526 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 23:45:15.978818 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 23:45:16.006689 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 23:45:16.007173 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 23:45:16.007442 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 23:45:16.007714 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 23:45:16.008002 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 23:45:16.640768 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 23:45:16.641243 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 23:45:16.641493 extracting modules file /var/lib/lava/dispatcher/tmp/968274/tftp-deploy-mbxzk2wt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/968274/extract-nfsrootfs-k68_a_hf
227 23:45:18.007931 extracting modules file /var/lib/lava/dispatcher/tmp/968274/tftp-deploy-mbxzk2wt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/968274/extract-overlay-ramdisk-pkfh35vv/ramdisk
228 23:45:19.404150 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 23:45:19.404645 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 23:45:19.404926 [common] Applying overlay to NFS
231 23:45:19.405142 [common] Applying overlay /var/lib/lava/dispatcher/tmp/968274/compress-overlay-fmriv16s/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/968274/extract-nfsrootfs-k68_a_hf
232 23:45:19.435108 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 23:45:19.435567 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 23:45:19.435839 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 23:45:19.436105 Converting downloaded kernel to a uImage
236 23:45:19.436429 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/968274/tftp-deploy-mbxzk2wt/kernel/Image /var/lib/lava/dispatcher/tmp/968274/tftp-deploy-mbxzk2wt/kernel/uImage
237 23:45:19.977508 output: Image Name:
238 23:45:19.977940 output: Created: Sat Nov 9 23:45:19 2024
239 23:45:19.978151 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 23:45:19.978358 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 23:45:19.978560 output: Load Address: 01080000
242 23:45:19.978760 output: Entry Point: 01080000
243 23:45:19.978957 output:
244 23:45:19.979295 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 23:45:19.979562 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 23:45:19.979832 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 23:45:19.980143 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 23:45:19.980410 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 23:45:19.980679 Building ramdisk /var/lib/lava/dispatcher/tmp/968274/extract-overlay-ramdisk-pkfh35vv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/968274/extract-overlay-ramdisk-pkfh35vv/ramdisk
250 23:45:22.188670 >> 166827 blocks
251 23:45:31.323794 Adding RAMdisk u-boot header.
252 23:45:31.324521 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/968274/extract-overlay-ramdisk-pkfh35vv/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/968274/extract-overlay-ramdisk-pkfh35vv/ramdisk.cpio.gz.uboot
253 23:45:31.593683 output: Image Name:
254 23:45:31.594111 output: Created: Sat Nov 9 23:45:31 2024
255 23:45:31.594326 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 23:45:31.594532 output: Data Size: 23435685 Bytes = 22886.41 KiB = 22.35 MiB
257 23:45:31.594736 output: Load Address: 00000000
258 23:45:31.594935 output: Entry Point: 00000000
259 23:45:31.595132 output:
260 23:45:31.595820 rename /var/lib/lava/dispatcher/tmp/968274/extract-overlay-ramdisk-pkfh35vv/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/968274/tftp-deploy-mbxzk2wt/ramdisk/ramdisk.cpio.gz.uboot
261 23:45:31.596444 end: 1.6.8 compress-ramdisk (duration 00:00:12) [common]
262 23:45:31.596997 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
263 23:45:31.597523 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:55) [common]
264 23:45:31.597989 No LXC device requested
265 23:45:31.598486 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 23:45:31.598989 start: 1.8 deploy-device-env (timeout 00:08:55) [common]
267 23:45:31.599480 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 23:45:31.599885 Checking files for TFTP limit of 4294967296 bytes.
269 23:45:31.602558 end: 1 tftp-deploy (duration 00:01:05) [common]
270 23:45:31.603120 start: 2 uboot-action (timeout 00:05:00) [common]
271 23:45:31.603638 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 23:45:31.604163 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 23:45:31.604665 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 23:45:31.605185 Using kernel file from prepare-kernel: 968274/tftp-deploy-mbxzk2wt/kernel/uImage
275 23:45:31.605806 substitutions:
276 23:45:31.606212 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 23:45:31.606607 - {DTB_ADDR}: 0x01070000
278 23:45:31.607002 - {DTB}: 968274/tftp-deploy-mbxzk2wt/dtb/meson-g12b-a311d-libretech-cc.dtb
279 23:45:31.607394 - {INITRD}: 968274/tftp-deploy-mbxzk2wt/ramdisk/ramdisk.cpio.gz.uboot
280 23:45:31.607785 - {KERNEL_ADDR}: 0x01080000
281 23:45:31.608206 - {KERNEL}: 968274/tftp-deploy-mbxzk2wt/kernel/uImage
282 23:45:31.608598 - {LAVA_MAC}: None
283 23:45:31.609023 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/968274/extract-nfsrootfs-k68_a_hf
284 23:45:31.609415 - {NFS_SERVER_IP}: 192.168.6.2
285 23:45:31.609798 - {PRESEED_CONFIG}: None
286 23:45:31.610186 - {PRESEED_LOCAL}: None
287 23:45:31.610571 - {RAMDISK_ADDR}: 0x08000000
288 23:45:31.610953 - {RAMDISK}: 968274/tftp-deploy-mbxzk2wt/ramdisk/ramdisk.cpio.gz.uboot
289 23:45:31.611337 - {ROOT_PART}: None
290 23:45:31.611722 - {ROOT}: None
291 23:45:31.612133 - {SERVER_IP}: 192.168.6.2
292 23:45:31.612521 - {TEE_ADDR}: 0x83000000
293 23:45:31.612902 - {TEE}: None
294 23:45:31.613287 Parsed boot commands:
295 23:45:31.613662 - setenv autoload no
296 23:45:31.614043 - setenv initrd_high 0xffffffff
297 23:45:31.614425 - setenv fdt_high 0xffffffff
298 23:45:31.614807 - dhcp
299 23:45:31.615188 - setenv serverip 192.168.6.2
300 23:45:31.615567 - tftpboot 0x01080000 968274/tftp-deploy-mbxzk2wt/kernel/uImage
301 23:45:31.615948 - tftpboot 0x08000000 968274/tftp-deploy-mbxzk2wt/ramdisk/ramdisk.cpio.gz.uboot
302 23:45:31.616357 - tftpboot 0x01070000 968274/tftp-deploy-mbxzk2wt/dtb/meson-g12b-a311d-libretech-cc.dtb
303 23:45:31.616743 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/968274/extract-nfsrootfs-k68_a_hf,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 23:45:31.617137 - bootm 0x01080000 0x08000000 0x01070000
305 23:45:31.617623 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 23:45:31.619083 start: 2.3 connect-device (timeout 00:05:00) [common]
308 23:45:31.619497 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 23:45:31.634146 Setting prompt string to ['lava-test: # ']
310 23:45:31.635649 end: 2.3 connect-device (duration 00:00:00) [common]
311 23:45:31.636286 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 23:45:31.636838 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 23:45:31.637355 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 23:45:31.638482 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 23:45:31.676459 >> OK - accepted request
316 23:45:31.678285 Returned 0 in 0 seconds
317 23:45:31.779353 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 23:45:31.781001 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 23:45:31.781569 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 23:45:31.782093 Setting prompt string to ['Hit any key to stop autoboot']
322 23:45:31.782552 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 23:45:31.784136 Trying 192.168.56.21...
324 23:45:31.784614 Connected to conserv1.
325 23:45:31.785038 Escape character is '^]'.
326 23:45:31.785454
327 23:45:31.785872 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 23:45:31.786290
329 23:45:42.784537 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 23:45:42.785181 bl2_stage_init 0x01
331 23:45:42.785595 bl2_stage_init 0x81
332 23:45:42.789865 hw id: 0x0000 - pwm id 0x01
333 23:45:42.790312 bl2_stage_init 0xc1
334 23:45:42.790723 bl2_stage_init 0x02
335 23:45:42.791116
336 23:45:42.795476 L0:00000000
337 23:45:42.795914 L1:20000703
338 23:45:42.796404 L2:00008067
339 23:45:42.796808 L3:14000000
340 23:45:42.798583 B2:00402000
341 23:45:42.799020 B1:e0f83180
342 23:45:42.799413
343 23:45:42.799805 TE: 58124
344 23:45:42.800234
345 23:45:42.809563 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 23:45:42.809999
347 23:45:42.810398 Board ID = 1
348 23:45:42.810787 Set A53 clk to 24M
349 23:45:42.811176 Set A73 clk to 24M
350 23:45:42.815448 Set clk81 to 24M
351 23:45:42.815865 A53 clk: 1200 MHz
352 23:45:42.816289 A73 clk: 1200 MHz
353 23:45:42.820955 CLK81: 166.6M
354 23:45:42.821373 smccc: 00012a91
355 23:45:42.826410 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 23:45:42.826824 board id: 1
357 23:45:42.834993 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 23:45:42.845729 fw parse done
359 23:45:42.851613 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 23:45:42.894060 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 23:45:42.904933 PIEI prepare done
362 23:45:42.905347 fastboot data load
363 23:45:42.905740 fastboot data verify
364 23:45:42.910570 verify result: 266
365 23:45:42.916196 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 23:45:42.916621 LPDDR4 probe
367 23:45:42.917036 ddr clk to 1584MHz
368 23:45:42.924177 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 23:45:42.961389
370 23:45:42.961828 dmc_version 0001
371 23:45:42.968085 Check phy result
372 23:45:42.973954 INFO : End of CA training
373 23:45:42.974382 INFO : End of initialization
374 23:45:42.979520 INFO : Training has run successfully!
375 23:45:42.979945 Check phy result
376 23:45:42.985132 INFO : End of initialization
377 23:45:42.985565 INFO : End of read enable training
378 23:45:42.990751 INFO : End of fine write leveling
379 23:45:42.996326 INFO : End of Write leveling coarse delay
380 23:45:42.996749 INFO : Training has run successfully!
381 23:45:42.997155 Check phy result
382 23:45:43.001954 INFO : End of initialization
383 23:45:43.002380 INFO : End of read dq deskew training
384 23:45:43.007535 INFO : End of MPR read delay center optimization
385 23:45:43.013118 INFO : End of write delay center optimization
386 23:45:43.018757 INFO : End of read delay center optimization
387 23:45:43.019194 INFO : End of max read latency training
388 23:45:43.024334 INFO : Training has run successfully!
389 23:45:43.024774 1D training succeed
390 23:45:43.033533 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 23:45:43.081167 Check phy result
392 23:45:43.081620 INFO : End of initialization
393 23:45:43.102852 INFO : End of 2D read delay Voltage center optimization
394 23:45:43.123114 INFO : End of 2D read delay Voltage center optimization
395 23:45:43.175162 INFO : End of 2D write delay Voltage center optimization
396 23:45:43.224554 INFO : End of 2D write delay Voltage center optimization
397 23:45:43.230126 INFO : Training has run successfully!
398 23:45:43.230565
399 23:45:43.230990 channel==0
400 23:45:43.235755 RxClkDly_Margin_A0==88 ps 9
401 23:45:43.236231 TxDqDly_Margin_A0==98 ps 10
402 23:45:43.241311 RxClkDly_Margin_A1==88 ps 9
403 23:45:43.241742 TxDqDly_Margin_A1==98 ps 10
404 23:45:43.242152 TrainedVREFDQ_A0==74
405 23:45:43.246992 TrainedVREFDQ_A1==74
406 23:45:43.247417 VrefDac_Margin_A0==25
407 23:45:43.247821 DeviceVref_Margin_A0==40
408 23:45:43.252496 VrefDac_Margin_A1==25
409 23:45:43.252926 DeviceVref_Margin_A1==40
410 23:45:43.253332
411 23:45:43.253732
412 23:45:43.258125 channel==1
413 23:45:43.258554 RxClkDly_Margin_A0==98 ps 10
414 23:45:43.258958 TxDqDly_Margin_A0==98 ps 10
415 23:45:43.263745 RxClkDly_Margin_A1==88 ps 9
416 23:45:43.264196 TxDqDly_Margin_A1==98 ps 10
417 23:45:43.269292 TrainedVREFDQ_A0==77
418 23:45:43.269723 TrainedVREFDQ_A1==77
419 23:45:43.270128 VrefDac_Margin_A0==23
420 23:45:43.274994 DeviceVref_Margin_A0==37
421 23:45:43.275423 VrefDac_Margin_A1==24
422 23:45:43.280504 DeviceVref_Margin_A1==37
423 23:45:43.280927
424 23:45:43.281334 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 23:45:43.286114
426 23:45:43.314160 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
427 23:45:43.314694 2D training succeed
428 23:45:43.319755 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 23:45:43.325303 auto size-- 65535DDR cs0 size: 2048MB
430 23:45:43.325735 DDR cs1 size: 2048MB
431 23:45:43.330998 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 23:45:43.331426 cs0 DataBus test pass
433 23:45:43.336497 cs1 DataBus test pass
434 23:45:43.336923 cs0 AddrBus test pass
435 23:45:43.337327 cs1 AddrBus test pass
436 23:45:43.337729
437 23:45:43.342073 100bdlr_step_size ps== 420
438 23:45:43.342506 result report
439 23:45:43.347742 boot times 0Enable ddr reg access
440 23:45:43.353145 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 23:45:43.366629 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 23:45:43.940284 0.0;M3 CHK:0;cm4_sp_mode 0
443 23:45:43.940811 MVN_1=0x00000000
444 23:45:43.945738 MVN_2=0x00000000
445 23:45:43.951472 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 23:45:43.951902 OPS=0x10
447 23:45:43.952365 ring efuse init
448 23:45:43.952768 chipver efuse init
449 23:45:43.957084 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 23:45:43.962713 [0.018961 Inits done]
451 23:45:43.963137 secure task start!
452 23:45:43.963543 high task start!
453 23:45:43.967276 low task start!
454 23:45:43.967704 run into bl31
455 23:45:43.973921 NOTICE: BL31: v1.3(release):4fc40b1
456 23:45:43.981721 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 23:45:43.982153 NOTICE: BL31: G12A normal boot!
458 23:45:44.007091 NOTICE: BL31: BL33 decompress pass
459 23:45:44.012786 ERROR: Error initializing runtime service opteed_fast
460 23:45:45.245776
461 23:45:45.246417
462 23:45:45.255259 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 23:45:45.255725
464 23:45:45.256199 Model: Libre Computer AML-A311D-CC Alta
465 23:45:45.462588 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 23:45:45.485925 DRAM: 2 GiB (effective 3.8 GiB)
467 23:45:45.629093 Core: 408 devices, 31 uclasses, devicetree: separate
468 23:45:45.634786 WDT: Not starting watchdog@f0d0
469 23:45:45.667070 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 23:45:45.679538 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 23:45:45.684476 ** Bad device specification mmc 0 **
472 23:45:45.694802 Card did not respond to voltage select! : -110
473 23:45:45.702439 ** Bad device specification mmc 0 **
474 23:45:45.702909 Couldn't find partition mmc 0
475 23:45:45.710789 Card did not respond to voltage select! : -110
476 23:45:45.716328 ** Bad device specification mmc 0 **
477 23:45:45.716781 Couldn't find partition mmc 0
478 23:45:45.721413 Error: could not access storage.
479 23:45:46.984670 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 23:45:46.985252 bl2_stage_init 0x01
481 23:45:46.985690 bl2_stage_init 0x81
482 23:45:46.990200 hw id: 0x0000 - pwm id 0x01
483 23:45:46.990653 bl2_stage_init 0xc1
484 23:45:46.991066 bl2_stage_init 0x02
485 23:45:46.991476
486 23:45:46.995792 L0:00000000
487 23:45:46.996280 L1:20000703
488 23:45:46.996694 L2:00008067
489 23:45:46.997101 L3:14000000
490 23:45:47.001566 B2:00402000
491 23:45:47.002009 B1:e0f83180
492 23:45:47.002415
493 23:45:47.002818 TE: 58167
494 23:45:47.003219
495 23:45:47.007037 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 23:45:47.007482
497 23:45:47.007893 Board ID = 1
498 23:45:47.012562 Set A53 clk to 24M
499 23:45:47.013008 Set A73 clk to 24M
500 23:45:47.013416 Set clk81 to 24M
501 23:45:47.018296 A53 clk: 1200 MHz
502 23:45:47.018745 A73 clk: 1200 MHz
503 23:45:47.019160 CLK81: 166.6M
504 23:45:47.019569 smccc: 00012abe
505 23:45:47.023827 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 23:45:47.029597 board id: 1
507 23:45:47.035367 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 23:45:47.045976 fw parse done
509 23:45:47.051878 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 23:45:47.094640 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 23:45:47.105600 PIEI prepare done
512 23:45:47.106052 fastboot data load
513 23:45:47.106470 fastboot data verify
514 23:45:47.111082 verify result: 266
515 23:45:47.116609 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 23:45:47.117059 LPDDR4 probe
517 23:45:47.117475 ddr clk to 1584MHz
518 23:45:47.124634 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 23:45:47.161909
520 23:45:47.162363 dmc_version 0001
521 23:45:47.168642 Check phy result
522 23:45:47.174552 INFO : End of CA training
523 23:45:47.174981 INFO : End of initialization
524 23:45:47.180055 INFO : Training has run successfully!
525 23:45:47.180502 Check phy result
526 23:45:47.185670 INFO : End of initialization
527 23:45:47.186100 INFO : End of read enable training
528 23:45:47.191233 INFO : End of fine write leveling
529 23:45:47.196840 INFO : End of Write leveling coarse delay
530 23:45:47.197292 INFO : Training has run successfully!
531 23:45:47.197701 Check phy result
532 23:45:47.202641 INFO : End of initialization
533 23:45:47.203090 INFO : End of read dq deskew training
534 23:45:47.208046 INFO : End of MPR read delay center optimization
535 23:45:47.213619 INFO : End of write delay center optimization
536 23:45:47.219205 INFO : End of read delay center optimization
537 23:45:47.219649 INFO : End of max read latency training
538 23:45:47.224921 INFO : Training has run successfully!
539 23:45:47.225366 1D training succeed
540 23:45:47.234026 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 23:45:47.281818 Check phy result
542 23:45:47.282387 INFO : End of initialization
543 23:45:47.303429 INFO : End of 2D read delay Voltage center optimization
544 23:45:47.323671 INFO : End of 2D read delay Voltage center optimization
545 23:45:47.375790 INFO : End of 2D write delay Voltage center optimization
546 23:45:47.425072 INFO : End of 2D write delay Voltage center optimization
547 23:45:47.430606 INFO : Training has run successfully!
548 23:45:47.431056
549 23:45:47.431481 channel==0
550 23:45:47.436106 RxClkDly_Margin_A0==88 ps 9
551 23:45:47.436562 TxDqDly_Margin_A0==98 ps 10
552 23:45:47.441813 RxClkDly_Margin_A1==88 ps 9
553 23:45:47.442357 TxDqDly_Margin_A1==98 ps 10
554 23:45:47.442796 TrainedVREFDQ_A0==74
555 23:45:47.447450 TrainedVREFDQ_A1==74
556 23:45:47.447977 VrefDac_Margin_A0==25
557 23:45:47.448461 DeviceVref_Margin_A0==40
558 23:45:47.453009 VrefDac_Margin_A1==25
559 23:45:47.453493 DeviceVref_Margin_A1==40
560 23:45:47.453910
561 23:45:47.454324
562 23:45:47.458688 channel==1
563 23:45:47.459176 RxClkDly_Margin_A0==98 ps 10
564 23:45:47.459589 TxDqDly_Margin_A0==98 ps 10
565 23:45:47.464313 RxClkDly_Margin_A1==88 ps 9
566 23:45:47.464811 TxDqDly_Margin_A1==88 ps 9
567 23:45:47.469824 TrainedVREFDQ_A0==77
568 23:45:47.470316 TrainedVREFDQ_A1==77
569 23:45:47.470734 VrefDac_Margin_A0==22
570 23:45:47.475413 DeviceVref_Margin_A0==37
571 23:45:47.475903 VrefDac_Margin_A1==24
572 23:45:47.481020 DeviceVref_Margin_A1==37
573 23:45:47.481510
574 23:45:47.481933 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 23:45:47.482346
576 23:45:47.514676 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
577 23:45:47.515261 2D training succeed
578 23:45:47.520256 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 23:45:47.525825 auto size-- 65535DDR cs0 size: 2048MB
580 23:45:47.526344 DDR cs1 size: 2048MB
581 23:45:47.531485 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 23:45:47.532036 cs0 DataBus test pass
583 23:45:47.537072 cs1 DataBus test pass
584 23:45:47.537600 cs0 AddrBus test pass
585 23:45:47.538026 cs1 AddrBus test pass
586 23:45:47.538435
587 23:45:47.542736 100bdlr_step_size ps== 420
588 23:45:47.543271 result report
589 23:45:47.548271 boot times 0Enable ddr reg access
590 23:45:47.553577 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 23:45:47.567026 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 23:45:48.141229 0.0;M3 CHK:0;cm4_sp_mode 0
593 23:45:48.141822 MVN_1=0x00000000
594 23:45:48.146531 MVN_2=0x00000000
595 23:45:48.152300 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 23:45:48.152841 OPS=0x10
597 23:45:48.153312 ring efuse init
598 23:45:48.153783 chipver efuse init
599 23:45:48.160502 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 23:45:48.161017 [0.018961 Inits done]
601 23:45:48.161416 secure task start!
602 23:45:48.167940 high task start!
603 23:45:48.168455 low task start!
604 23:45:48.168853 run into bl31
605 23:45:48.174568 NOTICE: BL31: v1.3(release):4fc40b1
606 23:45:48.182291 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 23:45:48.182770 NOTICE: BL31: G12A normal boot!
608 23:45:48.207812 NOTICE: BL31: BL33 decompress pass
609 23:45:48.213446 ERROR: Error initializing runtime service opteed_fast
610 23:45:49.446447
611 23:45:49.447084
612 23:45:49.454753 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 23:45:49.455256
614 23:45:49.455681 Model: Libre Computer AML-A311D-CC Alta
615 23:45:49.662974 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 23:45:49.686409 DRAM: 2 GiB (effective 3.8 GiB)
617 23:45:49.829576 Core: 408 devices, 31 uclasses, devicetree: separate
618 23:45:49.835350 WDT: Not starting watchdog@f0d0
619 23:45:49.867630 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 23:45:49.880246 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 23:45:49.885073 ** Bad device specification mmc 0 **
622 23:45:49.895537 Card did not respond to voltage select! : -110
623 23:45:49.903082 ** Bad device specification mmc 0 **
624 23:45:49.903588 Couldn't find partition mmc 0
625 23:45:49.911483 Card did not respond to voltage select! : -110
626 23:45:49.916994 ** Bad device specification mmc 0 **
627 23:45:49.917498 Couldn't find partition mmc 0
628 23:45:49.921988 Error: could not access storage.
629 23:45:50.264555 Net: eth0: ethernet@ff3f0000
630 23:45:50.265175 starting USB...
631 23:45:50.516563 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 23:45:50.517213 Starting the controller
633 23:45:50.523293 USB XHCI 1.10
634 23:45:52.233559 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 23:45:52.234095 bl2_stage_init 0x01
636 23:45:52.234334 bl2_stage_init 0x81
637 23:45:52.239009 hw id: 0x0000 - pwm id 0x01
638 23:45:52.239331 bl2_stage_init 0xc1
639 23:45:52.239570 bl2_stage_init 0x02
640 23:45:52.239789
641 23:45:52.244740 L0:00000000
642 23:45:52.245056 L1:20000703
643 23:45:52.245277 L2:00008067
644 23:45:52.245501 L3:14000000
645 23:45:52.247591 B2:00402000
646 23:45:52.248034 B1:e0f83180
647 23:45:52.248397
648 23:45:52.248740 TE: 58124
649 23:45:52.248983
650 23:45:52.258727 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 23:45:52.259204
652 23:45:52.259456 Board ID = 1
653 23:45:52.259678 Set A53 clk to 24M
654 23:45:52.259889 Set A73 clk to 24M
655 23:45:52.264438 Set clk81 to 24M
656 23:45:52.264751 A53 clk: 1200 MHz
657 23:45:52.264971 A73 clk: 1200 MHz
658 23:45:52.269951 CLK81: 166.6M
659 23:45:52.270269 smccc: 00012a92
660 23:45:52.275486 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 23:45:52.275800 board id: 1
662 23:45:52.284075 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 23:45:52.294773 fw parse done
664 23:45:52.300933 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 23:45:52.343239 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 23:45:52.354032 PIEI prepare done
667 23:45:52.354362 fastboot data load
668 23:45:52.354572 fastboot data verify
669 23:45:52.359724 verify result: 266
670 23:45:52.365270 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 23:45:52.365719 LPDDR4 probe
672 23:45:52.366060 ddr clk to 1584MHz
673 23:45:52.373333 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 23:45:52.410601
675 23:45:52.410998 dmc_version 0001
676 23:45:52.417392 Check phy result
677 23:45:52.423091 INFO : End of CA training
678 23:45:52.423532 INFO : End of initialization
679 23:45:52.428695 INFO : Training has run successfully!
680 23:45:52.429012 Check phy result
681 23:45:52.434323 INFO : End of initialization
682 23:45:52.434636 INFO : End of read enable training
683 23:45:52.439883 INFO : End of fine write leveling
684 23:45:52.445530 INFO : End of Write leveling coarse delay
685 23:45:52.445964 INFO : Training has run successfully!
686 23:45:52.446199 Check phy result
687 23:45:52.451086 INFO : End of initialization
688 23:45:52.451398 INFO : End of read dq deskew training
689 23:45:52.456697 INFO : End of MPR read delay center optimization
690 23:45:52.462331 INFO : End of write delay center optimization
691 23:45:52.467887 INFO : End of read delay center optimization
692 23:45:52.468216 INFO : End of max read latency training
693 23:45:52.473484 INFO : Training has run successfully!
694 23:45:52.473915 1D training succeed
695 23:45:52.482629 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 23:45:52.530463 Check phy result
697 23:45:52.530885 INFO : End of initialization
698 23:45:52.552902 INFO : End of 2D read delay Voltage center optimization
699 23:45:52.573200 INFO : End of 2D read delay Voltage center optimization
700 23:45:52.625207 INFO : End of 2D write delay Voltage center optimization
701 23:45:52.674540 INFO : End of 2D write delay Voltage center optimization
702 23:45:52.680182 INFO : Training has run successfully!
703 23:45:52.680713
704 23:45:52.681149 channel==0
705 23:45:52.685634 RxClkDly_Margin_A0==88 ps 9
706 23:45:52.686113 TxDqDly_Margin_A0==98 ps 10
707 23:45:52.691275 RxClkDly_Margin_A1==88 ps 9
708 23:45:52.691750 TxDqDly_Margin_A1==88 ps 9
709 23:45:52.692230 TrainedVREFDQ_A0==74
710 23:45:52.696868 TrainedVREFDQ_A1==74
711 23:45:52.697327 VrefDac_Margin_A0==25
712 23:45:52.697746 DeviceVref_Margin_A0==40
713 23:45:52.702441 VrefDac_Margin_A1==25
714 23:45:52.702895 DeviceVref_Margin_A1==40
715 23:45:52.703309
716 23:45:52.703719
717 23:45:52.704166 channel==1
718 23:45:52.708025 RxClkDly_Margin_A0==98 ps 10
719 23:45:52.708485 TxDqDly_Margin_A0==98 ps 10
720 23:45:52.713635 RxClkDly_Margin_A1==88 ps 9
721 23:45:52.714099 TxDqDly_Margin_A1==98 ps 10
722 23:45:52.719270 TrainedVREFDQ_A0==77
723 23:45:52.719727 TrainedVREFDQ_A1==78
724 23:45:52.720183 VrefDac_Margin_A0==23
725 23:45:52.724814 DeviceVref_Margin_A0==37
726 23:45:52.725268 VrefDac_Margin_A1==24
727 23:45:52.730396 DeviceVref_Margin_A1==36
728 23:45:52.730851
729 23:45:52.731269 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 23:45:52.731680
731 23:45:52.764044 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
732 23:45:52.764607 2D training succeed
733 23:45:52.769636 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 23:45:52.775283 auto size-- 65535DDR cs0 size: 2048MB
735 23:45:52.775747 DDR cs1 size: 2048MB
736 23:45:52.780837 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 23:45:52.781306 cs0 DataBus test pass
738 23:45:52.786422 cs1 DataBus test pass
739 23:45:52.786884 cs0 AddrBus test pass
740 23:45:52.787303 cs1 AddrBus test pass
741 23:45:52.787710
742 23:45:52.792032 100bdlr_step_size ps== 420
743 23:45:52.792515 result report
744 23:45:52.797656 boot times 0Enable ddr reg access
745 23:45:52.803045 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 23:45:52.816466 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 23:45:53.390125 0.0;M3 CHK:0;cm4_sp_mode 0
748 23:45:53.390804 MVN_1=0x00000000
749 23:45:53.395583 MVN_2=0x00000000
750 23:45:53.401381 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 23:45:53.401924 OPS=0x10
752 23:45:53.402335 ring efuse init
753 23:45:53.402735 chipver efuse init
754 23:45:53.406861 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 23:45:53.412486 [0.018961 Inits done]
756 23:45:53.412990 secure task start!
757 23:45:53.413445 high task start!
758 23:45:53.417095 low task start!
759 23:45:53.417621 run into bl31
760 23:45:53.423760 NOTICE: BL31: v1.3(release):4fc40b1
761 23:45:53.431557 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 23:45:53.432042 NOTICE: BL31: G12A normal boot!
763 23:45:53.457001 NOTICE: BL31: BL33 decompress pass
764 23:45:53.462690 ERROR: Error initializing runtime service opteed_fast
765 23:45:54.695550
766 23:45:54.696219
767 23:45:54.703895 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 23:45:54.704412
769 23:45:54.704853 Model: Libre Computer AML-A311D-CC Alta
770 23:45:54.912428 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 23:45:54.935770 DRAM: 2 GiB (effective 3.8 GiB)
772 23:45:55.078803 Core: 408 devices, 31 uclasses, devicetree: separate
773 23:45:55.084678 WDT: Not starting watchdog@f0d0
774 23:45:55.116879 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 23:45:55.129345 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 23:45:55.134280 ** Bad device specification mmc 0 **
777 23:45:55.144651 Card did not respond to voltage select! : -110
778 23:45:55.152250 ** Bad device specification mmc 0 **
779 23:45:55.152708 Couldn't find partition mmc 0
780 23:45:55.160573 Card did not respond to voltage select! : -110
781 23:45:55.166093 ** Bad device specification mmc 0 **
782 23:45:55.166545 Couldn't find partition mmc 0
783 23:45:55.171165 Error: could not access storage.
784 23:45:55.513819 Net: eth0: ethernet@ff3f0000
785 23:45:55.514443 starting USB...
786 23:45:55.765615 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 23:45:55.766224 Starting the controller
788 23:45:55.772399 USB XHCI 1.10
789 23:45:57.933641 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 23:45:57.934266 bl2_stage_init 0x01
791 23:45:57.934701 bl2_stage_init 0x81
792 23:45:57.939252 hw id: 0x0000 - pwm id 0x01
793 23:45:57.939701 bl2_stage_init 0xc1
794 23:45:57.940168 bl2_stage_init 0x02
795 23:45:57.940583
796 23:45:57.944855 L0:00000000
797 23:45:57.945295 L1:20000703
798 23:45:57.945705 L2:00008067
799 23:45:57.946106 L3:14000000
800 23:45:57.950478 B2:00402000
801 23:45:57.950910 B1:e0f83180
802 23:45:57.951316
803 23:45:57.951720 TE: 58124
804 23:45:57.952158
805 23:45:57.956224 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 23:45:57.956666
807 23:45:57.957076 Board ID = 1
808 23:45:57.961647 Set A53 clk to 24M
809 23:45:57.962086 Set A73 clk to 24M
810 23:45:57.962494 Set clk81 to 24M
811 23:45:57.967212 A53 clk: 1200 MHz
812 23:45:57.967646 A73 clk: 1200 MHz
813 23:45:57.968081 CLK81: 166.6M
814 23:45:57.968486 smccc: 00012a91
815 23:45:57.972864 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 23:45:57.978348 board id: 1
817 23:45:57.984248 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 23:45:57.994869 fw parse done
819 23:45:58.000945 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 23:45:58.043411 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 23:45:58.054275 PIEI prepare done
822 23:45:58.054737 fastboot data load
823 23:45:58.055153 fastboot data verify
824 23:45:58.060145 verify result: 266
825 23:45:58.065546 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 23:45:58.065992 LPDDR4 probe
827 23:45:58.066403 ddr clk to 1584MHz
828 23:45:58.073594 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 23:45:58.110812
830 23:45:58.111334 dmc_version 0001
831 23:45:58.117476 Check phy result
832 23:45:58.123356 INFO : End of CA training
833 23:45:58.123805 INFO : End of initialization
834 23:45:58.128921 INFO : Training has run successfully!
835 23:45:58.129355 Check phy result
836 23:45:58.134543 INFO : End of initialization
837 23:45:58.134977 INFO : End of read enable training
838 23:45:58.140197 INFO : End of fine write leveling
839 23:45:58.145742 INFO : End of Write leveling coarse delay
840 23:45:58.146176 INFO : Training has run successfully!
841 23:45:58.146581 Check phy result
842 23:45:58.151363 INFO : End of initialization
843 23:45:58.151794 INFO : End of read dq deskew training
844 23:45:58.156950 INFO : End of MPR read delay center optimization
845 23:45:58.162565 INFO : End of write delay center optimization
846 23:45:58.168167 INFO : End of read delay center optimization
847 23:45:58.168609 INFO : End of max read latency training
848 23:45:58.173745 INFO : Training has run successfully!
849 23:45:58.174177 1D training succeed
850 23:45:58.182951 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 23:45:58.230600 Check phy result
852 23:45:58.231136 INFO : End of initialization
853 23:45:58.252332 INFO : End of 2D read delay Voltage center optimization
854 23:45:58.272713 INFO : End of 2D read delay Voltage center optimization
855 23:45:58.324647 INFO : End of 2D write delay Voltage center optimization
856 23:45:58.374022 INFO : End of 2D write delay Voltage center optimization
857 23:45:58.379565 INFO : Training has run successfully!
858 23:45:58.380089
859 23:45:58.380517 channel==0
860 23:45:58.385285 RxClkDly_Margin_A0==88 ps 9
861 23:45:58.385735 TxDqDly_Margin_A0==98 ps 10
862 23:45:58.390879 RxClkDly_Margin_A1==88 ps 9
863 23:45:58.391316 TxDqDly_Margin_A1==98 ps 10
864 23:45:58.391740 TrainedVREFDQ_A0==74
865 23:45:58.396439 TrainedVREFDQ_A1==74
866 23:45:58.396919 VrefDac_Margin_A0==25
867 23:45:58.397328 DeviceVref_Margin_A0==40
868 23:45:58.402014 VrefDac_Margin_A1==26
869 23:45:58.402480 DeviceVref_Margin_A1==40
870 23:45:58.402869
871 23:45:58.403258
872 23:45:58.407543 channel==1
873 23:45:58.407964 RxClkDly_Margin_A0==98 ps 10
874 23:45:58.408384 TxDqDly_Margin_A0==98 ps 10
875 23:45:58.413303 RxClkDly_Margin_A1==88 ps 9
876 23:45:58.413791 TxDqDly_Margin_A1==88 ps 9
877 23:45:58.418862 TrainedVREFDQ_A0==77
878 23:45:58.419375 TrainedVREFDQ_A1==77
879 23:45:58.419773 VrefDac_Margin_A0==22
880 23:45:58.424392 DeviceVref_Margin_A0==37
881 23:45:58.424821 VrefDac_Margin_A1==24
882 23:45:58.430007 DeviceVref_Margin_A1==37
883 23:45:58.430429
884 23:45:58.430823 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 23:45:58.431213
886 23:45:58.463548 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
887 23:45:58.464088 2D training succeed
888 23:45:58.469252 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 23:45:58.474638 auto size-- 65535DDR cs0 size: 2048MB
890 23:45:58.475058 DDR cs1 size: 2048MB
891 23:45:58.480261 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 23:45:58.480689 cs0 DataBus test pass
893 23:45:58.485875 cs1 DataBus test pass
894 23:45:58.486290 cs0 AddrBus test pass
895 23:45:58.486679 cs1 AddrBus test pass
896 23:45:58.487064
897 23:45:58.491456 100bdlr_step_size ps== 420
898 23:45:58.491887 result report
899 23:45:58.497182 boot times 0Enable ddr reg access
900 23:45:58.502417 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 23:45:58.515917 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 23:45:59.089234 0.0;M3 CHK:0;cm4_sp_mode 0
903 23:45:59.089884 MVN_1=0x00000000
904 23:45:59.094556 MVN_2=0x00000000
905 23:45:59.100336 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 23:45:59.100811 OPS=0x10
907 23:45:59.101233 ring efuse init
908 23:45:59.101643 chipver efuse init
909 23:45:59.105883 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 23:45:59.111533 [0.018961 Inits done]
911 23:45:59.112040 secure task start!
912 23:45:59.112466 high task start!
913 23:45:59.116111 low task start!
914 23:45:59.116571 run into bl31
915 23:45:59.122743 NOTICE: BL31: v1.3(release):4fc40b1
916 23:45:59.130548 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 23:45:59.131021 NOTICE: BL31: G12A normal boot!
918 23:45:59.155915 NOTICE: BL31: BL33 decompress pass
919 23:45:59.161621 ERROR: Error initializing runtime service opteed_fast
920 23:46:00.394661
921 23:46:00.395285
922 23:46:00.403021 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 23:46:00.403517
924 23:46:00.403945 Model: Libre Computer AML-A311D-CC Alta
925 23:46:00.611450 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 23:46:00.634810 DRAM: 2 GiB (effective 3.8 GiB)
927 23:46:00.777818 Core: 408 devices, 31 uclasses, devicetree: separate
928 23:46:00.783701 WDT: Not starting watchdog@f0d0
929 23:46:00.815934 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 23:46:00.828437 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 23:46:00.833322 ** Bad device specification mmc 0 **
932 23:46:00.843647 Card did not respond to voltage select! : -110
933 23:46:00.851307 ** Bad device specification mmc 0 **
934 23:46:00.851783 Couldn't find partition mmc 0
935 23:46:00.859633 Card did not respond to voltage select! : -110
936 23:46:00.865197 ** Bad device specification mmc 0 **
937 23:46:00.865673 Couldn't find partition mmc 0
938 23:46:00.870252 Error: could not access storage.
939 23:46:01.212633 Net: eth0: ethernet@ff3f0000
940 23:46:01.213234 starting USB...
941 23:46:01.464614 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 23:46:01.465042 Starting the controller
943 23:46:01.471404 USB XHCI 1.10
944 23:46:03.334369 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 23:46:03.334999 bl2_stage_init 0x01
946 23:46:03.335429 bl2_stage_init 0x81
947 23:46:03.339943 hw id: 0x0000 - pwm id 0x01
948 23:46:03.340458 bl2_stage_init 0xc1
949 23:46:03.340878 bl2_stage_init 0x02
950 23:46:03.341287
951 23:46:03.345562 L0:00000000
952 23:46:03.346034 L1:20000703
953 23:46:03.346451 L2:00008067
954 23:46:03.346854 L3:14000000
955 23:46:03.351158 B2:00402000
956 23:46:03.351628 B1:e0f83180
957 23:46:03.352079
958 23:46:03.352496 TE: 58159
959 23:46:03.352906
960 23:46:03.356766 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 23:46:03.357242
962 23:46:03.357652 Board ID = 1
963 23:46:03.362315 Set A53 clk to 24M
964 23:46:03.362783 Set A73 clk to 24M
965 23:46:03.363190 Set clk81 to 24M
966 23:46:03.367893 A53 clk: 1200 MHz
967 23:46:03.368387 A73 clk: 1200 MHz
968 23:46:03.368797 CLK81: 166.6M
969 23:46:03.369198 smccc: 00012ab5
970 23:46:03.373547 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 23:46:03.379108 board id: 1
972 23:46:03.384987 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 23:46:03.395660 fw parse done
974 23:46:03.401767 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 23:46:03.444196 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 23:46:03.455055 PIEI prepare done
977 23:46:03.455551 fastboot data load
978 23:46:03.455959 fastboot data verify
979 23:46:03.460892 verify result: 266
980 23:46:03.466357 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 23:46:03.466820 LPDDR4 probe
982 23:46:03.467218 ddr clk to 1584MHz
983 23:46:03.474639 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 23:46:03.511739
985 23:46:03.512290 dmc_version 0001
986 23:46:03.518485 Check phy result
987 23:46:03.524404 INFO : End of CA training
988 23:46:03.524867 INFO : End of initialization
989 23:46:03.529923 INFO : Training has run successfully!
990 23:46:03.530431 Check phy result
991 23:46:03.535627 INFO : End of initialization
992 23:46:03.536157 INFO : End of read enable training
993 23:46:03.541100 INFO : End of fine write leveling
994 23:46:03.546738 INFO : End of Write leveling coarse delay
995 23:46:03.547225 INFO : Training has run successfully!
996 23:46:03.547636 Check phy result
997 23:46:03.552420 INFO : End of initialization
998 23:46:03.552900 INFO : End of read dq deskew training
999 23:46:03.557944 INFO : End of MPR read delay center optimization
1000 23:46:03.563487 INFO : End of write delay center optimization
1001 23:46:03.569018 INFO : End of read delay center optimization
1002 23:46:03.569538 INFO : End of max read latency training
1003 23:46:03.574612 INFO : Training has run successfully!
1004 23:46:03.575098 1D training succeed
1005 23:46:03.583697 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 23:46:03.631329 Check phy result
1007 23:46:03.631814 INFO : End of initialization
1008 23:46:03.653048 INFO : End of 2D read delay Voltage center optimization
1009 23:46:03.672297 INFO : End of 2D read delay Voltage center optimization
1010 23:46:03.725320 INFO : End of 2D write delay Voltage center optimization
1011 23:46:03.774686 INFO : End of 2D write delay Voltage center optimization
1012 23:46:03.780289 INFO : Training has run successfully!
1013 23:46:03.780783
1014 23:46:03.781219 channel==0
1015 23:46:03.785938 RxClkDly_Margin_A0==88 ps 9
1016 23:46:03.786407 TxDqDly_Margin_A0==98 ps 10
1017 23:46:03.791484 RxClkDly_Margin_A1==88 ps 9
1018 23:46:03.791958 TxDqDly_Margin_A1==98 ps 10
1019 23:46:03.792424 TrainedVREFDQ_A0==74
1020 23:46:03.797083 TrainedVREFDQ_A1==74
1021 23:46:03.797558 VrefDac_Margin_A0==25
1022 23:46:03.797975 DeviceVref_Margin_A0==40
1023 23:46:03.802646 VrefDac_Margin_A1==25
1024 23:46:03.803109 DeviceVref_Margin_A1==40
1025 23:46:03.803520
1026 23:46:03.803924
1027 23:46:03.808273 channel==1
1028 23:46:03.808733 RxClkDly_Margin_A0==98 ps 10
1029 23:46:03.809145 TxDqDly_Margin_A0==88 ps 9
1030 23:46:03.813963 RxClkDly_Margin_A1==98 ps 10
1031 23:46:03.814457 TxDqDly_Margin_A1==88 ps 9
1032 23:46:03.819479 TrainedVREFDQ_A0==77
1033 23:46:03.819948 TrainedVREFDQ_A1==77
1034 23:46:03.820399 VrefDac_Margin_A0==22
1035 23:46:03.825107 DeviceVref_Margin_A0==37
1036 23:46:03.825582 VrefDac_Margin_A1==23
1037 23:46:03.830663 DeviceVref_Margin_A1==37
1038 23:46:03.831121
1039 23:46:03.831532 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 23:46:03.831933
1041 23:46:03.864282 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1042 23:46:03.864820 2D training succeed
1043 23:46:03.869937 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 23:46:03.875503 auto size-- 65535DDR cs0 size: 2048MB
1045 23:46:03.876058 DDR cs1 size: 2048MB
1046 23:46:03.881068 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 23:46:03.881541 cs0 DataBus test pass
1048 23:46:03.886671 cs1 DataBus test pass
1049 23:46:03.887135 cs0 AddrBus test pass
1050 23:46:03.887550 cs1 AddrBus test pass
1051 23:46:03.887961
1052 23:46:03.892264 100bdlr_step_size ps== 420
1053 23:46:03.892748 result report
1054 23:46:03.897936 boot times 0Enable ddr reg access
1055 23:46:03.903203 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 23:46:03.916705 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 23:46:04.490383 0.0;M3 CHK:0;cm4_sp_mode 0
1058 23:46:04.491020 MVN_1=0x00000000
1059 23:46:04.495815 MVN_2=0x00000000
1060 23:46:04.501583 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 23:46:04.502085 OPS=0x10
1062 23:46:04.502503 ring efuse init
1063 23:46:04.502910 chipver efuse init
1064 23:46:04.509983 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 23:46:04.510500 [0.018960 Inits done]
1066 23:46:04.510919 secure task start!
1067 23:46:04.517375 high task start!
1068 23:46:04.517858 low task start!
1069 23:46:04.518273 run into bl31
1070 23:46:04.524044 NOTICE: BL31: v1.3(release):4fc40b1
1071 23:46:04.531853 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 23:46:04.532372 NOTICE: BL31: G12A normal boot!
1073 23:46:04.557144 NOTICE: BL31: BL33 decompress pass
1074 23:46:04.562848 ERROR: Error initializing runtime service opteed_fast
1075 23:46:05.795647
1076 23:46:05.796138
1077 23:46:05.804008 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 23:46:05.804399
1079 23:46:05.804657 Model: Libre Computer AML-A311D-CC Alta
1080 23:46:06.012432 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 23:46:06.035839 DRAM: 2 GiB (effective 3.8 GiB)
1082 23:46:06.178994 Core: 408 devices, 31 uclasses, devicetree: separate
1083 23:46:06.184736 WDT: Not starting watchdog@f0d0
1084 23:46:06.217061 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 23:46:06.229473 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 23:46:06.234495 ** Bad device specification mmc 0 **
1087 23:46:06.244887 Card did not respond to voltage select! : -110
1088 23:46:06.252505 ** Bad device specification mmc 0 **
1089 23:46:06.253019 Couldn't find partition mmc 0
1090 23:46:06.260838 Card did not respond to voltage select! : -110
1091 23:46:06.266315 ** Bad device specification mmc 0 **
1092 23:46:06.266806 Couldn't find partition mmc 0
1093 23:46:06.271383 Error: could not access storage.
1094 23:46:06.614872 Net: eth0: ethernet@ff3f0000
1095 23:46:06.615499 starting USB...
1096 23:46:06.866489 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 23:46:06.866893 Starting the controller
1098 23:46:06.873518 USB XHCI 1.10
1099 23:46:08.427646 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 23:46:08.435923 scanning usb for storage devices... 0 Storage Device(s) found
1102 23:46:08.487168 Hit any key to stop autoboot: 1
1103 23:46:08.488193 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 23:46:08.488871 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 23:46:08.489412 Setting prompt string to ['=>']
1106 23:46:08.489964 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 23:46:08.503513 0
1108 23:46:08.504574 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 23:46:08.505145 Sending with 10 millisecond of delay
1111 23:46:09.640752 => setenv autoload no
1112 23:46:09.651639 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 23:46:09.657215 setenv autoload no
1114 23:46:09.658039 Sending with 10 millisecond of delay
1116 23:46:11.455749 => setenv initrd_high 0xffffffff
1117 23:46:11.466540 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 23:46:11.491518 setenv initrd_high 0xffffffff
1119 23:46:11.492161 Sending with 10 millisecond of delay
1121 23:46:13.108696 => setenv fdt_high 0xffffffff
1122 23:46:13.119456 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 23:46:13.120047 setenv fdt_high 0xffffffff
1124 23:46:13.120524 Sending with 10 millisecond of delay
1126 23:46:13.412043 => dhcp
1127 23:46:13.422656 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 23:46:13.423252 dhcp
1129 23:46:13.423483 Speed: 1000, full duplex
1130 23:46:13.423693 BOOTP broadcast 1
1131 23:46:13.431953 DHCP client bound to address 192.168.6.27 (9 ms)
1132 23:46:13.432501 Sending with 10 millisecond of delay
1134 23:46:15.110256 => setenv serverip 192.168.6.2
1135 23:46:15.121110 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 23:46:15.122062 setenv serverip 192.168.6.2
1137 23:46:15.122822 Sending with 10 millisecond of delay
1139 23:46:18.847752 => tftpboot 0x01080000 968274/tftp-deploy-mbxzk2wt/kernel/uImage
1140 23:46:18.858604 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1141 23:46:18.859507 tftpboot 0x01080000 968274/tftp-deploy-mbxzk2wt/kernel/uImage
1142 23:46:18.859937 Speed: 1000, full duplex
1143 23:46:18.860396 Using ethernet@ff3f0000 device
1144 23:46:18.861378 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 23:46:18.866899 Filename '968274/tftp-deploy-mbxzk2wt/kernel/uImage'.
1146 23:46:18.870981 Load address: 0x1080000
1147 23:46:21.915224 Loading: *################################################## 43.6 MiB
1148 23:46:21.915854 14.3 MiB/s
1149 23:46:21.916337 done
1150 23:46:21.919788 Bytes transferred = 45713984 (2b98a40 hex)
1151 23:46:21.920582 Sending with 10 millisecond of delay
1153 23:46:26.612793 => tftpboot 0x08000000 968274/tftp-deploy-mbxzk2wt/ramdisk/ramdisk.cpio.gz.uboot
1154 23:46:26.623659 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1155 23:46:26.624597 tftpboot 0x08000000 968274/tftp-deploy-mbxzk2wt/ramdisk/ramdisk.cpio.gz.uboot
1156 23:46:26.625029 Speed: 1000, full duplex
1157 23:46:26.625431 Using ethernet@ff3f0000 device
1158 23:46:26.626548 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 23:46:26.635053 Filename '968274/tftp-deploy-mbxzk2wt/ramdisk/ramdisk.cpio.gz.uboot'.
1160 23:46:26.635487 Load address: 0x8000000
1161 23:46:30.528874 Loading: *################ UDP wrong checksum 000000ff 0000b12f
1162 23:46:30.593803 UDP wrong checksum 000000ff 00003d22
1163 23:46:33.344437 T ################################# UDP wrong checksum 00000005 00006bae
1164 23:46:38.346825 T UDP wrong checksum 00000005 00006bae
1165 23:46:48.348705 T T UDP wrong checksum 00000005 00006bae
1166 23:47:04.000801 T T T UDP wrong checksum 000000ff 0000bf02
1167 23:47:04.048158 UDP wrong checksum 000000ff 000057f5
1168 23:47:08.354818 T UDP wrong checksum 00000005 00006bae
1169 23:47:12.586720 UDP wrong checksum 000000ff 0000ec54
1170 23:47:12.626860 UDP wrong checksum 000000ff 00007147
1171 23:47:20.626879 T T UDP wrong checksum 000000ff 0000ffd5
1172 23:47:20.642789 UDP wrong checksum 000000ff 000094c8
1173 23:47:23.356760
1174 23:47:23.357399 Retry count exceeded; starting again
1176 23:47:23.358845 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1179 23:47:23.360774 end: 2.4 uboot-commands (duration 00:01:52) [common]
1181 23:47:23.362160 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1183 23:47:23.363180 end: 2 uboot-action (duration 00:01:52) [common]
1185 23:47:23.364730 Cleaning after the job
1186 23:47:23.365276 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968274/tftp-deploy-mbxzk2wt/ramdisk
1187 23:47:23.366515 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968274/tftp-deploy-mbxzk2wt/kernel
1188 23:47:23.394415 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968274/tftp-deploy-mbxzk2wt/dtb
1189 23:47:23.395678 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968274/tftp-deploy-mbxzk2wt/nfsrootfs
1190 23:47:23.455012 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/968274/tftp-deploy-mbxzk2wt/modules
1191 23:47:23.470284 start: 4.1 power-off (timeout 00:00:30) [common]
1192 23:47:23.470954 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1193 23:47:23.506208 >> OK - accepted request
1194 23:47:23.508304 Returned 0 in 0 seconds
1195 23:47:23.609424 end: 4.1 power-off (duration 00:00:00) [common]
1197 23:47:23.610534 start: 4.2 read-feedback (timeout 00:10:00) [common]
1198 23:47:23.611243 Listened to connection for namespace 'common' for up to 1s
1199 23:47:24.612189 Finalising connection for namespace 'common'
1200 23:47:24.612690 Disconnecting from shell: Finalise
1201 23:47:24.612985 =>
1202 23:47:24.713742 end: 4.2 read-feedback (duration 00:00:01) [common]
1203 23:47:24.714201 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/968274
1204 23:47:27.863133 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/968274
1205 23:47:27.863748 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.