Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 19:17:31.654824 lava-dispatcher, installed at version: 2024.01
2 19:17:31.655779 start: 0 validate
3 19:17:31.656407 Start time: 2024-11-10 19:17:31.656370+00:00 (UTC)
4 19:17:31.657072 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 19:17:31.657730 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 19:17:31.700815 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 19:17:31.701407 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-318-ga9cda7c0ffed%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 19:17:31.731344 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 19:17:31.732019 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-318-ga9cda7c0ffed%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 19:17:31.760465 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 19:17:31.761001 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 19:17:31.793693 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 19:17:31.794218 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-318-ga9cda7c0ffed%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 19:17:31.840283 validate duration: 0.18
16 19:17:31.841643 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:17:31.842206 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:17:31.842771 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:17:31.843737 Not decompressing ramdisk as can be used compressed.
20 19:17:31.844496 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 19:17:31.844892 saving as /var/lib/lava/dispatcher/tmp/972062/tftp-deploy-1bslt6of/ramdisk/initrd.cpio.gz
22 19:17:31.845548 total size: 4775763 (4 MB)
23 19:17:31.884309 progress 0 % (0 MB)
24 19:17:31.888378 progress 5 % (0 MB)
25 19:17:31.891831 progress 10 % (0 MB)
26 19:17:31.895408 progress 15 % (0 MB)
27 19:17:31.899348 progress 20 % (0 MB)
28 19:17:31.902748 progress 25 % (1 MB)
29 19:17:31.906159 progress 30 % (1 MB)
30 19:17:31.909954 progress 35 % (1 MB)
31 19:17:31.913398 progress 40 % (1 MB)
32 19:17:31.916840 progress 45 % (2 MB)
33 19:17:31.920153 progress 50 % (2 MB)
34 19:17:31.923938 progress 55 % (2 MB)
35 19:17:31.927306 progress 60 % (2 MB)
36 19:17:31.930641 progress 65 % (2 MB)
37 19:17:31.934442 progress 70 % (3 MB)
38 19:17:31.937862 progress 75 % (3 MB)
39 19:17:31.941195 progress 80 % (3 MB)
40 19:17:31.944691 progress 85 % (3 MB)
41 19:17:31.948512 progress 90 % (4 MB)
42 19:17:31.951690 progress 95 % (4 MB)
43 19:17:31.954715 progress 100 % (4 MB)
44 19:17:31.955377 4 MB downloaded in 0.11 s (41.47 MB/s)
45 19:17:31.955909 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:17:31.956862 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:17:31.957167 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:17:31.957448 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:17:31.957930 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-318-ga9cda7c0ffed/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 19:17:31.958211 saving as /var/lib/lava/dispatcher/tmp/972062/tftp-deploy-1bslt6of/kernel/zImage
52 19:17:31.958426 total size: 11444736 (10 MB)
53 19:17:31.958642 No compression specified
54 19:17:31.996275 progress 0 % (0 MB)
55 19:17:32.004312 progress 5 % (0 MB)
56 19:17:32.012188 progress 10 % (1 MB)
57 19:17:32.020445 progress 15 % (1 MB)
58 19:17:32.027921 progress 20 % (2 MB)
59 19:17:32.036031 progress 25 % (2 MB)
60 19:17:32.043400 progress 30 % (3 MB)
61 19:17:32.051184 progress 35 % (3 MB)
62 19:17:32.058430 progress 40 % (4 MB)
63 19:17:32.066072 progress 45 % (4 MB)
64 19:17:32.073384 progress 50 % (5 MB)
65 19:17:32.081153 progress 55 % (6 MB)
66 19:17:32.088524 progress 60 % (6 MB)
67 19:17:32.096543 progress 65 % (7 MB)
68 19:17:32.104167 progress 70 % (7 MB)
69 19:17:32.111855 progress 75 % (8 MB)
70 19:17:32.120202 progress 80 % (8 MB)
71 19:17:32.127495 progress 85 % (9 MB)
72 19:17:32.135049 progress 90 % (9 MB)
73 19:17:32.142275 progress 95 % (10 MB)
74 19:17:32.149561 progress 100 % (10 MB)
75 19:17:32.150107 10 MB downloaded in 0.19 s (56.94 MB/s)
76 19:17:32.150579 end: 1.2.1 http-download (duration 00:00:00) [common]
78 19:17:32.151399 end: 1.2 download-retry (duration 00:00:00) [common]
79 19:17:32.151675 start: 1.3 download-retry (timeout 00:10:00) [common]
80 19:17:32.151937 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 19:17:32.152445 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-318-ga9cda7c0ffed/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 19:17:32.152718 saving as /var/lib/lava/dispatcher/tmp/972062/tftp-deploy-1bslt6of/dtb/am335x-boneblack.dtb
83 19:17:32.152923 total size: 70568 (0 MB)
84 19:17:32.153132 No compression specified
85 19:17:32.195811 progress 46 % (0 MB)
86 19:17:32.196921 progress 92 % (0 MB)
87 19:17:32.197837 progress 100 % (0 MB)
88 19:17:32.198487 0 MB downloaded in 0.05 s (1.48 MB/s)
89 19:17:32.199134 end: 1.3.1 http-download (duration 00:00:00) [common]
91 19:17:32.200379 end: 1.3 download-retry (duration 00:00:00) [common]
92 19:17:32.200847 start: 1.4 download-retry (timeout 00:10:00) [common]
93 19:17:32.201447 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 19:17:32.202029 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 19:17:32.202442 saving as /var/lib/lava/dispatcher/tmp/972062/tftp-deploy-1bslt6of/nfsrootfs/full.rootfs.tar
96 19:17:32.202750 total size: 117747780 (112 MB)
97 19:17:32.203055 Using unxz to decompress xz
98 19:17:32.238565 progress 0 % (0 MB)
99 19:17:32.971913 progress 5 % (5 MB)
100 19:17:33.727280 progress 10 % (11 MB)
101 19:17:34.493079 progress 15 % (16 MB)
102 19:17:35.208365 progress 20 % (22 MB)
103 19:17:35.797456 progress 25 % (28 MB)
104 19:17:36.605231 progress 30 % (33 MB)
105 19:17:37.405971 progress 35 % (39 MB)
106 19:17:37.733857 progress 40 % (44 MB)
107 19:17:38.081508 progress 45 % (50 MB)
108 19:17:38.760725 progress 50 % (56 MB)
109 19:17:39.565186 progress 55 % (61 MB)
110 19:17:40.290983 progress 60 % (67 MB)
111 19:17:41.018397 progress 65 % (73 MB)
112 19:17:41.778937 progress 70 % (78 MB)
113 19:17:42.533692 progress 75 % (84 MB)
114 19:17:43.262839 progress 80 % (89 MB)
115 19:17:43.964028 progress 85 % (95 MB)
116 19:17:44.762875 progress 90 % (101 MB)
117 19:17:45.529766 progress 95 % (106 MB)
118 19:17:46.371774 progress 100 % (112 MB)
119 19:17:46.384649 112 MB downloaded in 14.18 s (7.92 MB/s)
120 19:17:46.385427 end: 1.4.1 http-download (duration 00:00:14) [common]
122 19:17:46.387090 end: 1.4 download-retry (duration 00:00:14) [common]
123 19:17:46.387623 start: 1.5 download-retry (timeout 00:09:45) [common]
124 19:17:46.388207 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 19:17:46.389112 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-318-ga9cda7c0ffed/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 19:17:46.389615 saving as /var/lib/lava/dispatcher/tmp/972062/tftp-deploy-1bslt6of/modules/modules.tar
127 19:17:46.390115 total size: 6611772 (6 MB)
128 19:17:46.390407 Using unxz to decompress xz
129 19:17:46.427416 progress 0 % (0 MB)
130 19:17:46.464376 progress 5 % (0 MB)
131 19:17:46.511491 progress 10 % (0 MB)
132 19:17:46.561805 progress 15 % (0 MB)
133 19:17:46.612511 progress 20 % (1 MB)
134 19:17:46.679965 progress 25 % (1 MB)
135 19:17:46.728561 progress 30 % (1 MB)
136 19:17:46.775498 progress 35 % (2 MB)
137 19:17:46.823795 progress 40 % (2 MB)
138 19:17:46.872341 progress 45 % (2 MB)
139 19:17:46.920344 progress 50 % (3 MB)
140 19:17:46.965856 progress 55 % (3 MB)
141 19:17:47.017092 progress 60 % (3 MB)
142 19:17:47.061382 progress 65 % (4 MB)
143 19:17:47.106480 progress 70 % (4 MB)
144 19:17:47.154019 progress 75 % (4 MB)
145 19:17:47.198424 progress 80 % (5 MB)
146 19:17:47.251266 progress 85 % (5 MB)
147 19:17:47.306003 progress 90 % (5 MB)
148 19:17:47.360888 progress 95 % (6 MB)
149 19:17:47.419450 progress 100 % (6 MB)
150 19:17:47.436346 6 MB downloaded in 1.05 s (6.03 MB/s)
151 19:17:47.436964 end: 1.5.1 http-download (duration 00:00:01) [common]
153 19:17:47.437795 end: 1.5 download-retry (duration 00:00:01) [common]
154 19:17:47.438065 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 19:17:47.438331 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 19:18:03.706716 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/972062/extract-nfsrootfs-u060o51f
157 19:18:03.707332 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 19:18:03.707653 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 19:18:03.708333 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc
160 19:18:03.708823 makedir: /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin
161 19:18:03.709222 makedir: /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/tests
162 19:18:03.709601 makedir: /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/results
163 19:18:03.709978 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-add-keys
164 19:18:03.710539 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-add-sources
165 19:18:03.711084 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-background-process-start
166 19:18:03.711670 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-background-process-stop
167 19:18:03.712229 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-common-functions
168 19:18:03.712730 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-echo-ipv4
169 19:18:03.713203 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-install-packages
170 19:18:03.713673 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-installed-packages
171 19:18:03.714155 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-os-build
172 19:18:03.714647 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-probe-channel
173 19:18:03.715116 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-probe-ip
174 19:18:03.715576 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-target-ip
175 19:18:03.716078 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-target-mac
176 19:18:03.716572 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-target-storage
177 19:18:03.717050 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-test-case
178 19:18:03.717543 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-test-event
179 19:18:03.718025 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-test-feedback
180 19:18:03.718496 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-test-raise
181 19:18:03.718963 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-test-reference
182 19:18:03.719429 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-test-runner
183 19:18:03.719902 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-test-set
184 19:18:03.720434 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-test-shell
185 19:18:03.720928 Updating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-add-keys (debian)
186 19:18:03.721456 Updating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-add-sources (debian)
187 19:18:03.721952 Updating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-install-packages (debian)
188 19:18:03.722438 Updating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-installed-packages (debian)
189 19:18:03.722919 Updating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/bin/lava-os-build (debian)
190 19:18:03.723350 Creating /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/environment
191 19:18:03.723736 LAVA metadata
192 19:18:03.724021 - LAVA_JOB_ID=972062
193 19:18:03.724242 - LAVA_DISPATCHER_IP=192.168.6.2
194 19:18:03.724602 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 19:18:03.725573 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 19:18:03.725882 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 19:18:03.726089 skipped lava-vland-overlay
198 19:18:03.726329 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 19:18:03.726580 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 19:18:03.726795 skipped lava-multinode-overlay
201 19:18:03.727035 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 19:18:03.727284 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 19:18:03.727525 Loading test definitions
204 19:18:03.727796 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 19:18:03.728042 Using /lava-972062 at stage 0
206 19:18:03.729140 uuid=972062_1.6.2.4.1 testdef=None
207 19:18:03.729441 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 19:18:03.729700 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 19:18:03.731228 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 19:18:03.732027 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 19:18:03.733957 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 19:18:03.734779 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 19:18:03.736622 runner path: /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/0/tests/0_timesync-off test_uuid 972062_1.6.2.4.1
216 19:18:03.737164 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 19:18:03.737971 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 19:18:03.738193 Using /lava-972062 at stage 0
220 19:18:03.738539 Fetching tests from https://github.com/kernelci/test-definitions.git
221 19:18:03.738823 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/0/tests/1_kselftest-dt'
222 19:18:07.404863 Running '/usr/bin/git checkout kernelci.org
223 19:18:07.734953 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 19:18:07.737185 uuid=972062_1.6.2.4.5 testdef=None
225 19:18:07.737884 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 19:18:07.738694 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 19:18:07.741767 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 19:18:07.742702 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 19:18:07.746832 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 19:18:07.747844 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 19:18:07.751836 runner path: /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/0/tests/1_kselftest-dt test_uuid 972062_1.6.2.4.5
235 19:18:07.752214 BOARD='beaglebone-black'
236 19:18:07.752455 BRANCH='mainline'
237 19:18:07.752671 SKIPFILE='/dev/null'
238 19:18:07.752886 SKIP_INSTALL='True'
239 19:18:07.753096 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-318-ga9cda7c0ffed/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 19:18:07.753313 TST_CASENAME=''
241 19:18:07.753529 TST_CMDFILES='dt'
242 19:18:07.754252 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 19:18:07.755159 Creating lava-test-runner.conf files
245 19:18:07.755396 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/972062/lava-overlay-n09ao9gc/lava-972062/0 for stage 0
246 19:18:07.755863 - 0_timesync-off
247 19:18:07.756216 - 1_kselftest-dt
248 19:18:07.756643 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 19:18:07.756991 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 19:18:30.929442 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 19:18:30.929888 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 19:18:30.930178 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 19:18:30.930484 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 19:18:30.930778 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 19:18:31.287359 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 19:18:31.287831 start: 1.6.4 extract-modules (timeout 00:09:01) [common]
257 19:18:31.288129 extracting modules file /var/lib/lava/dispatcher/tmp/972062/tftp-deploy-1bslt6of/modules/modules.tar to /var/lib/lava/dispatcher/tmp/972062/extract-nfsrootfs-u060o51f
258 19:18:32.170197 extracting modules file /var/lib/lava/dispatcher/tmp/972062/tftp-deploy-1bslt6of/modules/modules.tar to /var/lib/lava/dispatcher/tmp/972062/extract-overlay-ramdisk-0t8n8ycg/ramdisk
259 19:18:33.069152 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 19:18:33.069602 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 19:18:33.069887 [common] Applying overlay to NFS
262 19:18:33.070105 [common] Applying overlay /var/lib/lava/dispatcher/tmp/972062/compress-overlay-wz4q31ho/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/972062/extract-nfsrootfs-u060o51f
263 19:18:35.979958 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 19:18:35.980479 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 19:18:35.980784 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 19:18:35.981101 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 19:18:35.981386 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 19:18:35.981666 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 19:18:35.981929 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 19:18:35.982202 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 19:18:35.982465 Building ramdisk /var/lib/lava/dispatcher/tmp/972062/extract-overlay-ramdisk-0t8n8ycg/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/972062/extract-overlay-ramdisk-0t8n8ycg/ramdisk
272 19:18:36.993652 >> 74902 blocks
273 19:18:41.590068 Adding RAMdisk u-boot header.
274 19:18:41.590536 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/972062/extract-overlay-ramdisk-0t8n8ycg/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/972062/extract-overlay-ramdisk-0t8n8ycg/ramdisk.cpio.gz.uboot
275 19:18:41.755072 output: Image Name:
276 19:18:41.755467 output: Created: Sun Nov 10 19:18:41 2024
277 19:18:41.755678 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 19:18:41.755885 output: Data Size: 14790584 Bytes = 14443.93 KiB = 14.11 MiB
279 19:18:41.756449 output: Load Address: 00000000
280 19:18:41.756912 output: Entry Point: 00000000
281 19:18:41.757321 output:
282 19:18:41.758385 rename /var/lib/lava/dispatcher/tmp/972062/extract-overlay-ramdisk-0t8n8ycg/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/972062/tftp-deploy-1bslt6of/ramdisk/ramdisk.cpio.gz.uboot
283 19:18:41.759115 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 19:18:41.759663 end: 1.6 prepare-tftp-overlay (duration 00:00:54) [common]
285 19:18:41.760236 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
286 19:18:41.760708 No LXC device requested
287 19:18:41.761206 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 19:18:41.761713 start: 1.8 deploy-device-env (timeout 00:08:50) [common]
289 19:18:41.762206 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 19:18:41.762620 Checking files for TFTP limit of 4294967296 bytes.
291 19:18:41.765297 end: 1 tftp-deploy (duration 00:01:10) [common]
292 19:18:41.765904 start: 2 uboot-action (timeout 00:05:00) [common]
293 19:18:41.766432 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 19:18:41.766934 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 19:18:41.767435 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 19:18:41.768210 substitutions:
297 19:18:41.768641 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 19:18:41.769051 - {DTB_ADDR}: 0x88000000
299 19:18:41.769451 - {DTB}: 972062/tftp-deploy-1bslt6of/dtb/am335x-boneblack.dtb
300 19:18:41.769846 - {INITRD}: 972062/tftp-deploy-1bslt6of/ramdisk/ramdisk.cpio.gz.uboot
301 19:18:41.770241 - {KERNEL_ADDR}: 0x82000000
302 19:18:41.770635 - {KERNEL}: 972062/tftp-deploy-1bslt6of/kernel/zImage
303 19:18:41.771029 - {LAVA_MAC}: None
304 19:18:41.771459 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/972062/extract-nfsrootfs-u060o51f
305 19:18:41.771859 - {NFS_SERVER_IP}: 192.168.6.2
306 19:18:41.772291 - {PRESEED_CONFIG}: None
307 19:18:41.772685 - {PRESEED_LOCAL}: None
308 19:18:41.773078 - {RAMDISK_ADDR}: 0x83000000
309 19:18:41.773470 - {RAMDISK}: 972062/tftp-deploy-1bslt6of/ramdisk/ramdisk.cpio.gz.uboot
310 19:18:41.773867 - {ROOT_PART}: None
311 19:18:41.774258 - {ROOT}: None
312 19:18:41.774647 - {SERVER_IP}: 192.168.6.2
313 19:18:41.775037 - {TEE_ADDR}: 0x83000000
314 19:18:41.775424 - {TEE}: None
315 19:18:41.775809 Parsed boot commands:
316 19:18:41.776221 - setenv autoload no
317 19:18:41.776614 - setenv initrd_high 0xffffffff
318 19:18:41.777002 - setenv fdt_high 0xffffffff
319 19:18:41.777387 - dhcp
320 19:18:41.777770 - setenv serverip 192.168.6.2
321 19:18:41.778156 - tftp 0x82000000 972062/tftp-deploy-1bslt6of/kernel/zImage
322 19:18:41.778542 - tftp 0x83000000 972062/tftp-deploy-1bslt6of/ramdisk/ramdisk.cpio.gz.uboot
323 19:18:41.778927 - setenv initrd_size ${filesize}
324 19:18:41.779315 - tftp 0x88000000 972062/tftp-deploy-1bslt6of/dtb/am335x-boneblack.dtb
325 19:18:41.779702 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/972062/extract-nfsrootfs-u060o51f,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 19:18:41.780120 - bootz 0x82000000 0x83000000 0x88000000
327 19:18:41.780625 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 19:18:41.782110 start: 2.3 connect-device (timeout 00:05:00) [common]
330 19:18:41.782530 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 19:18:41.799543 Setting prompt string to ['lava-test: # ']
332 19:18:41.801218 end: 2.3 connect-device (duration 00:00:00) [common]
333 19:18:41.801859 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 19:18:41.802552 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 19:18:41.803279 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 19:18:41.804575 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 19:18:41.840317 >> OK - accepted request
338 19:18:41.843032 Returned 0 in 0 seconds
339 19:18:41.944326 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 19:18:41.946084 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 19:18:41.946686 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 19:18:41.947223 Setting prompt string to ['Hit any key to stop autoboot']
344 19:18:41.947712 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 19:18:41.949383 Trying 192.168.56.21...
346 19:18:41.949913 Connected to conserv1.
347 19:18:41.950349 Escape character is '^]'.
348 19:18:41.950777
349 19:18:41.951200 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 19:18:41.951625
351 19:18:49.180361
352 19:18:49.180784 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 19:18:49.185115 Trying to boot from MMC1
354 19:18:49.757510
355 19:18:49.758262
356 19:18:49.758767 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 19:18:49.759184
358 19:18:49.762634 CPU : AM335X-GP rev 2.1
359 19:18:49.763106 Model: TI AM335x BeagleBone Black
360 19:18:49.766935 DRAM: 512 MiB
361 19:18:49.849647 Core: 160 devices, 18 uclasses, devicetree: separate
362 19:18:49.859267 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 19:18:53.232084 7[r[999;999H[6n8NAND:
364 19:18:53.232777 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 19:18:53.237313 Trying to boot from MMC1
366 19:18:53.809637
367 19:18:53.810069
368 19:18:53.810282 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 19:18:53.810494
370 19:18:53.815145 CPU : AM335X-GP rev 2.1
371 19:18:53.815496 Model: TI AM335x BeagleBone Black
372 19:18:53.819175 DRAM: 512 MiB
373 19:18:53.900981 Core: 160 devices, 18 uclasses, devicetree: separate
374 19:18:53.911695 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 19:18:55.931186 7[r[999;999H[6n8NAND:
376 19:18:55.931828 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 19:18:55.936255 Trying to boot from MMC1
378 19:18:56.509146
379 19:18:56.509571
380 19:18:56.509803 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 19:18:56.510036
382 19:18:56.514583 CPU : AM335X-GP rev 2.1
383 19:18:56.514934 Model: TI AM335x BeagleBone Black
384 19:18:56.518680 DRAM: 512 MiB
385 19:18:56.601551 Core: 160 devices, 18 uclasses, devicetree: separate
386 19:18:56.611162 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 19:18:57.116580 7[r[999;999H[6n8NAND: 0 MiB
388 19:18:57.126564 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 19:18:57.198573 Loading Environment from FAT... Unable to use mmc 0:1...
390 19:18:57.221072 <ethaddr> not set. Validating first E-fuse MAC
391 19:18:57.252154 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 19:18:57.309988 Hit any key to stop autoboot: 2
394 19:18:57.311113 end: 2.4.2 bootloader-interrupt (duration 00:00:15) [common]
395 19:18:57.311922 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
396 19:18:57.312756 Setting prompt string to ['=>']
397 19:18:57.313461 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
398 19:18:57.319441 0
399 19:18:57.320542 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 19:18:57.321195 Sending with 10 millisecond of delay
402 19:18:58.456784 => setenv autoload no
403 19:18:58.467628 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
404 19:18:58.472634 setenv autoload no
405 19:18:58.473364 Sending with 10 millisecond of delay
407 19:19:00.272181 => setenv initrd_high 0xffffffff
408 19:19:00.282969 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
409 19:19:00.283890 setenv initrd_high 0xffffffff
410 19:19:00.284694 Sending with 10 millisecond of delay
412 19:19:01.901548 => setenv fdt_high 0xffffffff
413 19:19:01.912033 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
414 19:19:01.912535 setenv fdt_high 0xffffffff
415 19:19:01.913000 Sending with 10 millisecond of delay
417 19:19:02.204402 => dhcp
418 19:19:02.214945 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
419 19:19:02.215509 dhcp
420 19:19:02.216191 link up on port 0, speed 100, full duplex
421 19:19:02.216439 BOOTP broadcast 1
422 19:19:02.236936 DHCP client bound to address 192.168.6.12 (17 ms)
423 19:19:02.237490 Sending with 10 millisecond of delay
425 19:19:03.916125 => setenv serverip 192.168.6.2
426 19:19:03.927029 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
427 19:19:03.928033 setenv serverip 192.168.6.2
428 19:19:03.928820 Sending with 10 millisecond of delay
430 19:19:07.412439 => tftp 0x82000000 972062/tftp-deploy-1bslt6of/kernel/zImage
431 19:19:07.423359 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
432 19:19:07.424396 tftp 0x82000000 972062/tftp-deploy-1bslt6of/kernel/zImage
433 19:19:07.424906 link up on port 0, speed 100, full duplex
434 19:19:07.427921 Using ethernet@4a100000 device
435 19:19:07.433585 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 19:19:07.440899 Filename '972062/tftp-deploy-1bslt6of/kernel/zImage'.
437 19:19:07.441542 Load address: 0x82000000
438 19:19:09.652849 Loading: *################################################## 10.9 MiB
439 19:19:09.653648 4.9 MiB/s
440 19:19:09.654218 done
441 19:19:09.657129 Bytes transferred = 11444736 (aea200 hex)
442 19:19:09.658121 Sending with 10 millisecond of delay
444 19:19:14.105914 => tftp 0x83000000 972062/tftp-deploy-1bslt6of/ramdisk/ramdisk.cpio.gz.uboot
445 19:19:14.116772 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:28)
446 19:19:14.117645 tftp 0x83000000 972062/tftp-deploy-1bslt6of/ramdisk/ramdisk.cpio.gz.uboot
447 19:19:14.118139 link up on port 0, speed 100, full duplex
448 19:19:14.121595 Using ethernet@4a100000 device
449 19:19:14.127069 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 19:19:14.135831 Filename '972062/tftp-deploy-1bslt6of/ramdisk/ramdisk.cpio.gz.uboot'.
451 19:19:14.136445 Load address: 0x83000000
452 19:19:17.068234 Loading: *################################################## 14.1 MiB
453 19:19:17.068908 4.8 MiB/s
454 19:19:17.069395 done
455 19:19:17.072506 Bytes transferred = 14790648 (e1aff8 hex)
456 19:19:17.073386 Sending with 10 millisecond of delay
458 19:19:18.930506 => setenv initrd_size ${filesize}
459 19:19:18.941335 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
460 19:19:18.942174 setenv initrd_size ${filesize}
461 19:19:18.942919 Sending with 10 millisecond of delay
463 19:19:23.087777 => tftp 0x88000000 972062/tftp-deploy-1bslt6of/dtb/am335x-boneblack.dtb
464 19:19:23.098617 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
465 19:19:23.099540 tftp 0x88000000 972062/tftp-deploy-1bslt6of/dtb/am335x-boneblack.dtb
466 19:19:23.100046 link up on port 0, speed 100, full duplex
467 19:19:23.103386 Using ethernet@4a100000 device
468 19:19:23.109036 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 19:19:23.121767 Filename '972062/tftp-deploy-1bslt6of/dtb/am335x-boneblack.dtb'.
470 19:19:23.122310 Load address: 0x88000000
471 19:19:23.133007 Loading: *################################################## 68.9 KiB
472 19:19:23.133477 4.5 MiB/s
473 19:19:23.133910 done
474 19:19:23.139577 Bytes transferred = 70568 (113a8 hex)
475 19:19:23.140347 Sending with 10 millisecond of delay
477 19:19:36.316871 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/972062/extract-nfsrootfs-u060o51f,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 19:19:36.328018 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
479 19:19:36.328943 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/972062/extract-nfsrootfs-u060o51f,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 19:19:36.329658 Sending with 10 millisecond of delay
482 19:19:38.668900 => bootz 0x82000000 0x83000000 0x88000000
483 19:19:38.679702 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 19:19:38.680302 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
485 19:19:38.681296 bootz 0x82000000 0x83000000 0x88000000
486 19:19:38.681745 Kernel image @ 0x82000000 [ 0x000000 - 0xaea200 ]
487 19:19:38.682238 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 19:19:38.687375 Image Name:
489 19:19:38.687819 Created: 2024-11-10 19:18:41 UTC
490 19:19:38.696315 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 19:19:38.696760 Data Size: 14790584 Bytes = 14.1 MiB
492 19:19:38.704707 Load Address: 00000000
493 19:19:38.705214 Entry Point: 00000000
494 19:19:38.873025 Verifying Checksum ... OK
495 19:19:38.873643 ## Flattened Device Tree blob at 88000000
496 19:19:38.879493 Booting using the fdt blob at 0x88000000
497 19:19:38.884384 Using Device Tree in place at 88000000, end 880143a7
498 19:19:38.898197
499 19:19:38.898725 Starting kernel ...
500 19:19:38.899146
501 19:19:38.900049 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 19:19:38.900653 start: 2.4.4 auto-login-action (timeout 00:04:03) [common]
503 19:19:38.901130 Setting prompt string to ['Linux version [0-9]']
504 19:19:38.901589 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 19:19:38.902053 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 19:19:39.739822 [ 0.000000] Booting Linux on physical CPU 0x0
507 19:19:39.745630 start: 2.4.4.1 login-action (timeout 00:04:02) [common]
508 19:19:39.746110 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 19:19:39.746390 Setting prompt string to []
510 19:19:39.746652 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 19:19:39.746895 Using line separator: #'\n'#
512 19:19:39.747104 No login prompt set.
513 19:19:39.747333 Parsing kernel messages
514 19:19:39.747532 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 19:19:39.747941 [login-action] Waiting for messages, (timeout 00:04:02)
516 19:19:39.748208 Waiting using forced prompt support (timeout 00:02:01)
517 19:19:39.759876 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j371937-arm-gcc-12-multi-v7-defconfig-vtbvv) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Sun Nov 10 18:55:38 UTC 2024
518 19:19:39.771278 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 19:19:39.777078 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 19:19:39.782824 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 19:19:39.788899 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 19:19:39.794177 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 19:19:39.801215 [ 0.000000] Memory policy: Data cache writeback
524 19:19:39.801867 [ 0.000000] efi: UEFI not found.
525 19:19:39.809325 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 19:19:39.815149 [ 0.000000] Zone ranges:
527 19:19:39.820997 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 19:19:39.821604 [ 0.000000] Normal empty
529 19:19:39.826631 [ 0.000000] HighMem empty
530 19:19:39.833154 [ 0.000000] Movable zone start for each node
531 19:19:39.833792 [ 0.000000] Early memory node ranges
532 19:19:39.843851 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 19:19:39.848463 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 19:19:39.873966 [ 0.000000] CPU: All CPU(s) started in SVC mode.
535 19:19:39.879603 [ 0.000000] AM335X ES2.1 (sgx neon)
536 19:19:39.891233 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
537 19:19:39.908876 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/972062/extract-nfsrootfs-u060o51f,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
538 19:19:39.923031 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
539 19:19:39.926219 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
540 19:19:39.931946 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
541 19:19:39.942150 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
542 19:19:39.970943 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
543 19:19:39.976866 <6>[ 0.000000] trace event string verifier disabled
544 19:19:39.977225 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
545 19:19:39.982605 <6>[ 0.000000] rcu: RCU event tracing is enabled.
546 19:19:39.994086 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
547 19:19:39.999883 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
548 19:19:40.006864 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
549 19:19:40.021098 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
550 19:19:40.039234 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
551 19:19:40.046022 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
552 19:19:40.138582 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
553 19:19:40.149924 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
554 19:19:40.156737 <6>[ 0.008332] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
555 19:19:40.169806 <6>[ 0.019136] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
556 19:19:40.177084 <6>[ 0.033962] Console: colour dummy device 80x30
557 19:19:40.183156 Matched prompt #6: WARNING:
558 19:19:40.183516 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
559 19:19:40.188630 <3>[ 0.038859] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
560 19:19:40.194393 <3>[ 0.045930] This ensures that you still see kernel messages. Please
561 19:19:40.197556 <3>[ 0.052657] update your kernel commandline.
562 19:19:40.238250 <6>[ 0.057270] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
563 19:19:40.244035 <6>[ 0.096147] CPU: Testing write buffer coherency: ok
564 19:19:40.246899 <6>[ 0.101518] CPU0: Spectre v2: using BPIALL workaround
565 19:19:40.252748 <6>[ 0.106979] pid_max: default: 32768 minimum: 301
566 19:19:40.258458 <6>[ 0.112167] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 19:19:40.271103 <6>[ 0.119983] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 19:19:40.275102 <6>[ 0.129342] CPU0: thread -1, cpu 0, socket -1, mpidr 0
569 19:19:40.341004 <6>[ 0.189527] Setting up static identity map for 0x80300000 - 0x803000ac
570 19:19:40.346791 <6>[ 0.199109] rcu: Hierarchical SRCU implementation.
571 19:19:40.350443 <6>[ 0.204391] rcu: Max phase no-delay instances is 1000.
572 19:19:40.358951 <6>[ 0.215418] EFI services will not be available.
573 19:19:40.364693 <6>[ 0.220767] smp: Bringing up secondary CPUs ...
574 19:19:40.370546 <6>[ 0.225738] smp: Brought up 1 node, 1 CPU
575 19:19:40.378593 <6>[ 0.230226] SMP: Total of 1 processors activated (996.14 BogoMIPS).
576 19:19:40.384463 <6>[ 0.236945] CPU: All CPU(s) started in SVC mode.
577 19:19:40.396674 <6>[ 0.242144] Memory: 406000K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49048K reserved, 65536K cma-reserved, 0K highmem)
578 19:19:40.402524 <6>[ 0.258415] devtmpfs: initialized
579 19:19:40.424563 <6>[ 0.275263] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
580 19:19:40.436080 <6>[ 0.283862] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
581 19:19:40.441063 <6>[ 0.294298] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
582 19:19:40.452700 <6>[ 0.306573] pinctrl core: initialized pinctrl subsystem
583 19:19:40.461975 <6>[ 0.317208] DMI not present or invalid.
584 19:19:40.470324 <6>[ 0.323050] NET: Registered PF_NETLINK/PF_ROUTE protocol family
585 19:19:40.479786 <6>[ 0.332026] DMA: preallocated 256 KiB pool for atomic coherent allocations
586 19:19:40.495013 <6>[ 0.343489] thermal_sys: Registered thermal governor 'step_wise'
587 19:19:40.495562 <6>[ 0.343657] cpuidle: using governor menu
588 19:19:40.522604 <6>[ 0.379288] No ATAGs?
589 19:19:40.528706 <6>[ 0.382025] hw-breakpoint: debug architecture 0x4 unsupported.
590 19:19:40.538816 <6>[ 0.393889] Serial: AMBA PL011 UART driver
591 19:19:40.568177 <6>[ 0.424852] iommu: Default domain type: Translated
592 19:19:40.577099 <6>[ 0.430195] iommu: DMA domain TLB invalidation policy: strict mode
593 19:19:40.604722 <5>[ 0.460876] SCSI subsystem initialized
594 19:19:40.610512 <6>[ 0.465767] usbcore: registered new interface driver usbfs
595 19:19:40.616273 <6>[ 0.471792] usbcore: registered new interface driver hub
596 19:19:40.623058 <6>[ 0.477575] usbcore: registered new device driver usb
597 19:19:40.629009 <6>[ 0.484080] pps_core: LinuxPPS API ver. 1 registered
598 19:19:40.640318 <6>[ 0.489512] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
599 19:19:40.647483 <6>[ 0.499197] PTP clock support registered
600 19:19:40.647976 <6>[ 0.503651] EDAC MC: Ver: 3.0.0
601 19:19:40.697534 <6>[ 0.552746] scmi_core: SCMI protocol bus registered
602 19:19:40.723269 <6>[ 0.579188] vgaarb: loaded
603 19:19:40.729172 <6>[ 0.583017] clocksource: Switched to clocksource dmtimer
604 19:19:40.753732 <6>[ 0.609982] NET: Registered PF_INET protocol family
605 19:19:40.766133 <6>[ 0.615704] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
606 19:19:40.772022 <6>[ 0.624543] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
607 19:19:40.783354 <6>[ 0.633466] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
608 19:19:40.789383 <6>[ 0.641707] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
609 19:19:40.800722 <6>[ 0.649995] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
610 19:19:40.806566 <6>[ 0.657716] TCP: Hash tables configured (established 4096 bind 4096)
611 19:19:40.812321 <6>[ 0.664636] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
612 19:19:40.818209 <6>[ 0.671650] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
613 19:19:40.825820 <6>[ 0.679261] NET: Registered PF_UNIX/PF_LOCAL protocol family
614 19:19:40.911798 <6>[ 0.762925] RPC: Registered named UNIX socket transport module.
615 19:19:40.912493 <6>[ 0.769356] RPC: Registered udp transport module.
616 19:19:40.917556 <6>[ 0.774478] RPC: Registered tcp transport module.
617 19:19:40.923301 <6>[ 0.779584] RPC: Registered tcp-with-tls transport module.
618 19:19:40.936302 <6>[ 0.785512] RPC: Registered tcp NFSv4.1 backchannel transport module.
619 19:19:40.936906 <6>[ 0.792419] PCI: CLS 0 bytes, default 64
620 19:19:40.943470 <5>[ 0.798215] Initialise system trusted keyrings
621 19:19:40.964513 <6>[ 0.818318] Trying to unpack rootfs image as initramfs...
622 19:19:41.042897 <6>[ 0.893450] workingset: timestamp_bits=30 max_order=17 bucket_order=0
623 19:19:41.047621 <6>[ 0.900955] squashfs: version 4.0 (2009/01/31) Phillip Lougher
624 19:19:41.087320 <5>[ 0.943769] NFS: Registering the id_resolver key type
625 19:19:41.092841 <5>[ 0.949380] Key type id_resolver registered
626 19:19:41.098602 <5>[ 0.954066] Key type id_legacy registered
627 19:19:41.104396 <6>[ 0.958508] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
628 19:19:41.113962 <6>[ 0.965707] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
629 19:19:41.186825 <5>[ 1.043598] Key type asymmetric registered
630 19:19:41.192640 <5>[ 1.048121] Asymmetric key parser 'x509' registered
631 19:19:41.200979 <6>[ 1.053598] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
632 19:19:41.207066 <6>[ 1.061482] io scheduler mq-deadline registered
633 19:19:41.215535 <6>[ 1.066462] io scheduler kyber registered
634 19:19:41.216058 <6>[ 1.070915] io scheduler bfq registered
635 19:19:41.320634 <6>[ 1.173782] ledtrig-cpu: registered to indicate activity on CPUs
636 19:19:41.622315 <6>[ 1.475299] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 19:19:41.660018 <6>[ 1.516666] msm_serial: driver initialized
638 19:19:41.666055 <6>[ 1.521438] SuperH (H)SCI(F) driver initialized
639 19:19:41.671893 <6>[ 1.526736] STMicroelectronics ASC driver initialized
640 19:19:41.674020 <6>[ 1.532339] STM32 USART driver initialized
641 19:19:41.793403 <6>[ 1.649541] brd: module loaded
642 19:19:41.828384 <6>[ 1.684501] loop: module loaded
643 19:19:41.868295 <6>[ 1.724507] CAN device driver interface
644 19:19:41.874988 <6>[ 1.729475] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 19:19:41.880694 <6>[ 1.736558] e1000e: Intel(R) PRO/1000 Network Driver
646 19:19:41.886534 <6>[ 1.741943] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 19:19:41.892295 <6>[ 1.748409] igb: Intel(R) Gigabit Ethernet Network Driver
648 19:19:41.900562 <6>[ 1.754258] igb: Copyright (c) 2007-2014 Intel Corporation.
649 19:19:41.912343 <6>[ 1.763603] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 19:19:41.918329 <6>[ 1.769671] usbcore: registered new interface driver pegasus
651 19:19:41.921094 <6>[ 1.775860] usbcore: registered new interface driver asix
652 19:19:41.926835 <6>[ 1.781713] usbcore: registered new interface driver ax88179_178a
653 19:19:41.932614 <6>[ 1.788307] usbcore: registered new interface driver cdc_ether
654 19:19:41.938363 <6>[ 1.794626] usbcore: registered new interface driver smsc75xx
655 19:19:41.949836 <6>[ 1.800845] usbcore: registered new interface driver smsc95xx
656 19:19:41.955658 <6>[ 1.807080] usbcore: registered new interface driver net1080
657 19:19:41.961419 <6>[ 1.813224] usbcore: registered new interface driver cdc_subset
658 19:19:41.967228 <6>[ 1.819613] usbcore: registered new interface driver zaurus
659 19:19:41.972229 <6>[ 1.825680] usbcore: registered new interface driver cdc_ncm
660 19:19:41.982245 <6>[ 1.835316] usbcore: registered new interface driver usb-storage
661 19:19:41.990702 <6>[ 1.846487] i2c_dev: i2c /dev entries driver
662 19:19:42.016253 <5>[ 1.865090] cpuidle: enable-method property 'ti,am3352' found operations
663 19:19:42.022019 <6>[ 1.874605] sdhci: Secure Digital Host Controller Interface driver
664 19:19:42.029622 <6>[ 1.881260] sdhci: Copyright(c) Pierre Ossman
665 19:19:42.036853 <6>[ 1.887833] Synopsys Designware Multimedia Card Interface Driver
666 19:19:42.042338 <6>[ 1.895844] sdhci-pltfm: SDHCI platform and OF driver helper
667 19:19:42.056507 <6>[ 1.905934] usbcore: registered new interface driver usbhid
668 19:19:42.057006 <6>[ 1.911959] usbhid: USB HID core driver
669 19:19:42.069629 <6>[ 1.923899] NET: Registered PF_INET6 protocol family
670 19:19:42.527726 <6>[ 2.384563] Segment Routing with IPv6
671 19:19:42.533568 <6>[ 2.388712] In-situ OAM (IOAM) with IPv6
672 19:19:42.540221 <6>[ 2.393239] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
673 19:19:42.546048 <6>[ 2.400473] NET: Registered PF_PACKET protocol family
674 19:19:42.551820 <6>[ 2.406055] can: controller area network core
675 19:19:42.557594 <6>[ 2.410880] NET: Registered PF_CAN protocol family
676 19:19:42.558051 <6>[ 2.416107] can: raw protocol
677 19:19:42.563340 <6>[ 2.419435] can: broadcast manager protocol
678 19:19:42.569835 <6>[ 2.424030] can: netlink gateway - max_hops=1
679 19:19:42.575942 <5>[ 2.429508] Key type dns_resolver registered
680 19:19:42.582232 <6>[ 2.434572] ThumbEE CPU extension supported.
681 19:19:42.582677 <5>[ 2.439260] Registering SWP/SWPB emulation handler
682 19:19:42.591966 <3>[ 2.444950] omap_voltage_late_init: Voltage driver support not added
683 19:19:42.799339 <5>[ 2.653697] Loading compiled-in X.509 certificates
684 19:19:42.951004 <6>[ 2.795043] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
685 19:19:42.958301 <6>[ 2.811678] pinctrl-single 44e10800.pinmux: 142 pins, size 568
686 19:19:42.983701 <3>[ 2.835542] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
687 19:19:43.162590 <3>[ 3.013517] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
688 19:19:43.360479 <6>[ 3.215577] OMAP GPIO hardware version 0.1
689 19:19:43.381243 <6>[ 3.234415] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
690 19:19:43.472055 <4>[ 3.325041] at24 2-0054: supply vcc not found, using dummy regulator
691 19:19:43.514592 <4>[ 3.367572] at24 2-0055: supply vcc not found, using dummy regulator
692 19:19:43.561307 <4>[ 3.414204] at24 2-0056: supply vcc not found, using dummy regulator
693 19:19:43.598910 <4>[ 3.451832] at24 2-0057: supply vcc not found, using dummy regulator
694 19:19:43.634947 <6>[ 3.488686] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
695 19:19:43.709491 <3>[ 3.559087] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
696 19:19:43.733972 <6>[ 3.579999] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
697 19:19:43.754507 <4>[ 3.606197] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
698 19:19:43.772459 <4>[ 3.624125] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
699 19:19:43.900796 <6>[ 3.753942] omap_rng 48310000.rng: Random Number Generator ver. 20
700 19:19:43.924394 <5>[ 3.780265] random: crng init done
701 19:19:43.983912 <6>[ 3.840564] Freeing initrd memory: 14444K
702 19:19:43.993567 <6>[ 3.845279] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
703 19:19:44.044660 <6>[ 3.895452] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
704 19:19:44.050459 <6>[ 3.905776] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
705 19:19:44.062221 <6>[ 3.913111] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
706 19:19:44.068070 <6>[ 3.920557] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
707 19:19:44.079572 <6>[ 3.928695] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
708 19:19:44.086902 <6>[ 3.940328] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
709 19:19:44.100096 <5>[ 3.949341] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
710 19:19:44.127814 <3>[ 3.979119] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
711 19:19:44.133599 <6>[ 3.987703] edma 49000000.dma: TI EDMA DMA engine driver
712 19:19:44.204975 <3>[ 4.055556] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
713 19:19:44.219675 <6>[ 4.069936] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
714 19:19:44.232557 <3>[ 4.086991] l3-aon-clkctrl:0000:0: failed to disable
715 19:19:44.282883 <6>[ 4.134154] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
716 19:19:44.288506 <6>[ 4.143617] printk: legacy console [ttyS0] enabled
717 19:19:44.294257 <6>[ 4.143617] printk: legacy console [ttyS0] enabled
718 19:19:44.299885 <6>[ 4.153938] printk: legacy bootconsole [omap8250] disabled
719 19:19:44.305758 <6>[ 4.153938] printk: legacy bootconsole [omap8250] disabled
720 19:19:44.343494 <4>[ 4.193769] tps65217-pmic: Failed to locate of_node [id: -1]
721 19:19:44.347045 <4>[ 4.201164] tps65217-bl: Failed to locate of_node [id: -1]
722 19:19:44.363543 <6>[ 4.220822] tps65217 0-0024: TPS65217 ID 0xe version 1.2
723 19:19:44.382002 <6>[ 4.227794] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
724 19:19:44.393697 <6>[ 4.241474] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
725 19:19:44.399492 <6>[ 4.253375] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
726 19:19:44.421532 <6>[ 4.273200] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
727 19:19:44.427423 <6>[ 4.282257] sdhci-omap 48060000.mmc: Got CD GPIO
728 19:19:44.435457 <4>[ 4.287437] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
729 19:19:44.450181 <4>[ 4.301110] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
730 19:19:44.456583 <4>[ 4.309763] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
731 19:19:44.466506 <4>[ 4.318422] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
732 19:19:44.564703 <6>[ 4.417342] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
733 19:19:44.612503 <6>[ 4.463268] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
734 19:19:44.619058 <6>[ 4.472266] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
735 19:19:44.628219 <6>[ 4.481252] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
736 19:19:44.681289 <6>[ 4.535335] mmc0: new high speed SDHC card at address 1234
737 19:19:44.689543 <6>[ 4.544689] mmcblk0: mmc0:1234 SA32G 29.1 GiB
738 19:19:44.698801 <6>[ 4.555783] mmcblk0: p1
739 19:19:44.715914 <6>[ 4.564860] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
740 19:19:44.743763 <6>[ 4.591901] mmc1: new high speed MMC card at address 0001
741 19:19:44.744122 <6>[ 4.598887] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
742 19:19:44.751327 <6>[ 4.606611] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
743 19:19:44.758614 <6>[ 4.613789] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
744 19:19:44.767259 <6>[ 4.620648] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
745 19:19:46.822997 <6>[ 6.674075] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
746 19:19:47.266359 <5>[ 6.703029] Sending DHCP requests ., OK
747 19:19:47.277467 <6>[ 7.127531] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
748 19:19:47.278011 <6>[ 7.135651] IP-Config: Complete:
749 19:19:47.288878 <6>[ 7.139189] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
750 19:19:47.294654 <6>[ 7.149728] host=192.168.6.12, domain=, nis-domain=(none)
751 19:19:47.307034 <6>[ 7.155965] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
752 19:19:47.307554 <6>[ 7.156001] nameserver0=10.255.253.1
753 19:19:47.313134 <6>[ 7.168610] clk: Disabling unused clocks
754 19:19:47.318985 <6>[ 7.173370] PM: genpd: Disabling unused power domains
755 19:19:47.338410 <6>[ 7.192086] Freeing unused kernel image (initmem) memory: 2048K
756 19:19:47.345839 <6>[ 7.201767] Run /init as init process
757 19:19:47.368370 Loading, please wait...
758 19:19:47.443824 Starting systemd-udevd version 252.22-1~deb12u1
759 19:19:50.656521 <4>[ 10.506243] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 19:19:50.814657 <4>[ 10.664547] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 19:19:50.985120 <6>[ 10.842417] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
762 19:19:50.996027 <6>[ 10.848274] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
763 19:19:51.070585 <6>[ 10.926026] tda998x 0-0070: found TDA19988
764 19:19:51.288149 <6>[ 11.143909] hub 1-0:1.0: USB hub found
765 19:19:51.337786 <6>[ 11.193399] hub 1-0:1.0: 1 port detected
766 19:19:54.033258 Begin: Loading essential drivers ... done.
767 19:19:54.038560 Begin: Running /scripts/init-premount ... done.
768 19:19:54.044109 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
769 19:19:54.058047 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
770 19:19:54.058616 Device /sys/class/net/eth0 found
771 19:19:54.059090 done.
772 19:19:54.152213 Begin: Waiting up to 180 secs for any network device to become available ... done.
773 19:19:54.218929 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
774 19:19:54.245794 IP-Config: eth0 guessed broadcast address 192.168.6.255
775 19:19:54.251365 IP-Config: eth0 complete (dhcp from 192.168.6.1):
776 19:19:54.257111 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
777 19:19:54.268091 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
778 19:19:54.268633 rootserver: 192.168.6.1 rootpath:
779 19:19:54.271654 filename :
780 19:19:54.390365 done.
781 19:19:54.398888 Begin: Running /scripts/nfs-bottom ... done.
782 19:19:54.464528 Begin: Running /scripts/init-bottom ... done.
783 19:19:55.970820 <30>[ 15.824591] systemd[1]: System time before build time, advancing clock.
784 19:19:56.176380 <30>[ 16.003357] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 19:19:56.185078 <30>[ 16.040074] systemd[1]: Detected architecture arm.
786 19:19:56.196899
787 19:19:56.197208 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 19:19:56.197435
789 19:19:56.218822 <30>[ 16.072617] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 19:19:58.359594 <30>[ 18.212276] systemd[1]: Queued start job for default target graphical.target.
791 19:19:58.376932 <30>[ 18.227345] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 19:19:58.384261 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 19:19:58.404692 <30>[ 18.255843] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 19:19:58.413113 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 19:19:58.435569 <30>[ 18.286434] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 19:19:58.443830 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 19:19:58.463810 <30>[ 18.315045] systemd[1]: Created slice user.slice - User and Session Slice.
798 19:19:58.470541 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 19:19:58.498948 <30>[ 18.344434] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 19:19:58.505034 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 19:19:58.523047 <30>[ 18.374201] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 19:19:58.534081 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 19:19:58.563817 <30>[ 18.404208] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 19:19:58.570321 <30>[ 18.424675] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 19:19:58.578799 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 19:19:58.601966 <30>[ 18.453528] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 19:19:58.610301 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 19:19:58.632556 <30>[ 18.483861] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 19:19:58.641001 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 19:19:58.662487 <30>[ 18.513995] systemd[1]: Reached target paths.target - Path Units.
811 19:19:58.667578 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 19:19:58.692147 <30>[ 18.543692] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 19:19:58.699579 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 19:19:58.721977 <30>[ 18.573535] systemd[1]: Reached target slices.target - Slice Units.
815 19:19:58.727438 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 19:19:58.752176 <30>[ 18.603705] systemd[1]: Reached target swap.target - Swaps.
817 19:19:58.756220 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 19:19:58.782468 <30>[ 18.633799] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 19:19:58.791310 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 19:19:58.813457 <30>[ 18.664646] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 19:19:58.821658 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 19:19:58.901137 <30>[ 18.747623] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 19:19:58.913646 <30>[ 18.765119] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 19:19:58.922126 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 19:19:58.945262 <30>[ 18.795758] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 19:19:58.952774 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 19:19:58.974826 <30>[ 18.826170] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 19:19:58.982985 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 19:19:59.007854 <30>[ 18.858038] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 19:19:59.013647 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 19:19:59.044723 <30>[ 18.894731] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 19:19:59.052255 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 19:19:59.079472 <30>[ 18.924820] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 19:19:59.098050 <30>[ 18.943373] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 19:19:59.145899 <30>[ 18.998715] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 19:19:59.172318 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 19:19:59.221729 <30>[ 19.073812] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 19:19:59.242260 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 19:19:59.283774 <30>[ 19.134844] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 19:19:59.299066 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 19:19:59.374708 <30>[ 19.226350] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 19:19:59.400352 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 19:19:59.452215 <30>[ 19.304271] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 19:19:59.468093 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 19:19:59.532639 <30>[ 19.384218] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 19:19:59.539608 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 19:19:59.604908 <30>[ 19.456329] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 19:19:59.630883 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 19:19:59.683232 <30>[ 19.535685] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 19:19:59.708943 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 19:19:59.762462 <30>[ 19.614931] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 19:19:59.781503 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 19:19:59.798177 <28>[ 19.645434] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 19:19:59.817914 <28>[ 19.669395] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 19:19:59.863461 <30>[ 19.716354] systemd[1]: Starting systemd-journald.service - Journal Service...
856 19:19:59.884475 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 19:19:59.952756 <30>[ 19.804933] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 19:19:59.966415 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 19:19:59.989278 <30>[ 19.841722] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 19:20:00.033445 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 19:20:00.117630 <30>[ 19.968483] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 19:20:00.162065 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 19:20:00.227211 <30>[ 20.078957] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 19:20:00.292093 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 19:20:00.380203 <30>[ 20.224790] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 19:20:00.411255 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 19:20:00.434261 <30>[ 20.286516] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 19:20:00.473217 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 19:20:00.499034 <30>[ 20.350276] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 19:20:00.530419 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 19:20:00.694678 <30>[ 20.547420] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 19:20:00.732936 <30>[ 20.584944] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 19:20:00.759270 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 19:20:00.773037 <30>[ 20.624810] systemd[1]: Started systemd-journald.service - Journal Service.
875 19:20:00.779942 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
876 19:20:00.821946 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 19:20:00.846372 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
878 19:20:00.884983 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
879 19:20:00.917206 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
880 19:20:00.953104 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
881 19:20:00.982259 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
882 19:20:01.004235 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
883 19:20:01.025313 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
884 19:20:01.061801 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
885 19:20:01.121531 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
886 19:20:01.172552 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
887 19:20:01.233198 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
888 19:20:01.292192 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
889 19:20:01.365839 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
890 19:20:01.572046 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
891 19:20:01.596943 <46>[ 21.449698] systemd-journald[163]: Received client request to flush runtime journal.
892 19:20:01.685150 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
893 19:20:02.264910 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
894 19:20:02.776850 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
895 19:20:02.848307 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
896 19:20:03.349027 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
897 19:20:03.492211 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
898 19:20:03.522319 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
899 19:20:03.540603 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
900 19:20:03.612642 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
901 19:20:03.659304 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
902 19:20:04.554814 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
903 19:20:04.633452 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
904 19:20:04.949255 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
905 19:20:05.070307 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
906 19:20:05.152819 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
907 19:20:07.106896 [[0m[0;31m* [0m] (1 of 5) Job systemd-udev-trigger.s…vice/start running (8s / no limit)
908 19:20:07.190782 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
909 19:20:07.235064 [K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
910 19:20:07.396053 <5>[ 27.249011] cfg80211: Loading compiled-in X.509 certificates for regulatory database
911 19:20:08.421063 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
912 19:20:08.722551 <5>[ 28.577484] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
913 19:20:08.781004 <5>[ 28.631220] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
914 19:20:08.786766 <4>[ 28.641299] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
915 19:20:08.794242 <6>[ 28.650466] cfg80211: failed to load regulatory.db
916 19:20:09.589728 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
917 19:20:09.941857 <46>[ 29.785918] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
918 19:20:10.147795 <46>[ 29.993817] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
919 19:20:10.164974 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
920 19:20:19.055297 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
921 19:20:19.081788 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
922 19:20:19.103602 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
923 19:20:19.126371 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
924 19:20:19.191527 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
925 19:20:19.234733 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
926 19:20:19.292996 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
927 19:20:19.364289 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
928 19:20:19.419222 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
929 19:20:19.446455 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
930 19:20:19.488631 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
931 19:20:19.514783 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
932 19:20:19.555555 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
933 19:20:19.601788 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
934 19:20:19.633590 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
935 19:20:19.653148 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
936 19:20:19.679613 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
937 19:20:19.706255 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
938 19:20:19.733023 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
939 19:20:19.754169 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
940 19:20:19.804603 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
941 19:20:19.830048 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
942 19:20:19.856961 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
943 19:20:19.946553 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
944 19:20:19.991011 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
945 19:20:20.065831 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
946 19:20:20.132918 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
947 19:20:20.205534 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
948 19:20:20.238402 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
949 19:20:20.251649 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
950 19:20:20.486929 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
951 19:20:20.561472 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
952 19:20:20.633100 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
953 19:20:20.651602 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
954 19:20:20.672720 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
955 19:20:20.871816 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
956 19:20:21.215235 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
957 19:20:21.273768 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
958 19:20:21.317885 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
959 19:20:21.404636 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
960 19:20:21.571418 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
961 19:20:21.733293
962 19:20:21.736836 Debian GNU/Linux 12 debian-bookworworm-armhf login: root (automatic login)
963 19:20:21.737362
964 19:20:22.057020 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Sun Nov 10 18:55:38 UTC 2024 armv7l
965 19:20:22.057643
966 19:20:22.062597 The programs included with the Debian GNU/Linux system are free software;
967 19:20:22.066080 the exact distribution terms for each program are described in the
968 19:20:22.071539 individual files in /usr/share/doc/*/copyright.
969 19:20:22.072121
970 19:20:22.077171 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
971 19:20:22.080876 permitted by applicable law.
972 19:20:26.644710 Unable to match end of the kernel message
974 19:20:26.646352 Setting prompt string to ['/ #']
975 19:20:26.646948 end: 2.4.4.1 login-action (duration 00:00:47) [common]
977 19:20:26.648473 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
978 19:20:26.649066 start: 2.4.5 expect-shell-connection (timeout 00:03:15) [common]
979 19:20:26.649539 Setting prompt string to ['/ #']
980 19:20:26.649983 Forcing a shell prompt, looking for ['/ #']
982 19:20:26.701049 / #
983 19:20:26.701859 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
984 19:20:26.702415 Waiting using forced prompt support (timeout 00:02:30)
985 19:20:26.705625
986 19:20:26.709489 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
987 19:20:26.710120 start: 2.4.6 export-device-env (timeout 00:03:15) [common]
988 19:20:26.710627 Sending with 10 millisecond of delay
990 19:20:31.700333 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/972062/extract-nfsrootfs-u060o51f'
991 19:20:31.711358 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/972062/extract-nfsrootfs-u060o51f'
992 19:20:31.712778 Sending with 10 millisecond of delay
994 19:20:33.811521 / # export NFS_SERVER_IP='192.168.6.2'
995 19:20:33.822540 export NFS_SERVER_IP='192.168.6.2'
996 19:20:33.823903 end: 2.4.6 export-device-env (duration 00:00:07) [common]
997 19:20:33.824611 end: 2.4 uboot-commands (duration 00:01:52) [common]
998 19:20:33.825254 end: 2 uboot-action (duration 00:01:52) [common]
999 19:20:33.825902 start: 3 lava-test-retry (timeout 00:06:58) [common]
1000 19:20:33.826593 start: 3.1 lava-test-shell (timeout 00:06:58) [common]
1001 19:20:33.827113 Using namespace: common
1003 19:20:33.928478 / # #
1004 19:20:33.929432 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1005 19:20:33.932848 #
1006 19:20:33.939632 Using /lava-972062
1008 19:20:34.041008 / # export SHELL=/bin/bash
1009 19:20:34.046498 export SHELL=/bin/bash
1011 19:20:34.153630 / # . /lava-972062/environment
1012 19:20:34.159357 . /lava-972062/environment
1014 19:20:34.272352 / # /lava-972062/bin/lava-test-runner /lava-972062/0
1015 19:20:34.273335 Test shell timeout: 10s (minimum of the action and connection timeout)
1016 19:20:34.277739 /lava-972062/bin/lava-test-runner /lava-972062/0
1017 19:20:34.711836 + export TESTRUN_ID=0_timesync-off
1018 19:20:34.719736 + TESTRUN_ID=0_timesync-off
1019 19:20:34.720307 + cd /lava-972062/0/tests/0_timesync-off
1020 19:20:34.720790 ++ cat uuid
1021 19:20:34.735859 + UUID=972062_1.6.2.4.1
1022 19:20:34.736427 + set +x
1023 19:20:34.744546 <LAVA_SIGNAL_STARTRUN 0_timesync-off 972062_1.6.2.4.1>
1024 19:20:34.745080 + systemctl stop systemd-timesyncd
1025 19:20:34.745870 Received signal: <STARTRUN> 0_timesync-off 972062_1.6.2.4.1
1026 19:20:34.746388 Starting test lava.0_timesync-off (972062_1.6.2.4.1)
1027 19:20:34.746972 Skipping test definition patterns.
1028 19:20:35.047108 + set +x
1029 19:20:35.047766 <LAVA_SIGNAL_ENDRUN 0_timesync-off 972062_1.6.2.4.1>
1030 19:20:35.048681 Received signal: <ENDRUN> 0_timesync-off 972062_1.6.2.4.1
1031 19:20:35.049286 Ending use of test pattern.
1032 19:20:35.049777 Ending test lava.0_timesync-off (972062_1.6.2.4.1), duration 0.30
1034 19:20:35.255934 + export TESTRUN_ID=1_kselftest-dt
1035 19:20:35.263823 + TESTRUN_ID=1_kselftest-dt
1036 19:20:35.264399 + cd /lava-972062/0/tests/1_kselftest-dt
1037 19:20:35.264881 ++ cat uuid
1038 19:20:35.279553 + UUID=972062_1.6.2.4.5
1039 19:20:35.280125 + set +x
1040 19:20:35.285045 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 972062_1.6.2.4.5>
1041 19:20:35.285565 + cd ./automated/linux/kselftest/
1042 19:20:35.286318 Received signal: <STARTRUN> 1_kselftest-dt 972062_1.6.2.4.5
1043 19:20:35.286798 Starting test lava.1_kselftest-dt (972062_1.6.2.4.5)
1044 19:20:35.287341 Skipping test definition patterns.
1045 19:20:35.313190 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-318-ga9cda7c0ffed/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1046 19:20:35.414167 INFO: install_deps skipped
1047 19:20:36.001655 --2024-11-10 19:20:35-- http://storage.kernelci.org/mainline/master/v6.12-rc6-318-ga9cda7c0ffed/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1048 19:20:36.015028 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1049 19:20:36.156918 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1050 19:20:36.297432 HTTP request sent, awaiting response... 200 OK
1051 19:20:36.298049 Length: 4108044 (3.9M) [application/octet-stream]
1052 19:20:36.302841 Saving to: 'kselftest_armhf.tar.gz'
1053 19:20:36.303360
1054 19:20:37.943291
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 180KB/s
kselftest_armhf.tar 5%[> ] 218.67K 394KB/s
kselftest_armhf.tar 22%[===> ] 892.70K 1.05MB/s
kselftest_armhf.tar 28%[====> ] 1.12M 1.05MB/s
kselftest_armhf.tar 62%[===========> ] 2.47M 1.84MB/s
kselftest_armhf.tar 92%[=================> ] 3.63M 2.36MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 2.39MB/s in 1.6s
1055 19:20:37.944031
1056 19:20:38.609323 2024-11-10 19:20:37 (2.39 MB/s) - 'kselftest_armhf.tar.gz' saved [4108044/4108044]
1057 19:20:38.610025
1058 19:20:51.161616 skiplist:
1059 19:20:51.162275 ========================================
1060 19:20:51.167283 ========================================
1061 19:20:51.280718 dt:test_unprobed_devices.sh
1062 19:20:51.311976 ============== Tests to run ===============
1063 19:20:51.320869 dt:test_unprobed_devices.sh
1064 19:20:51.324742 ===========End Tests to run ===============
1065 19:20:51.332882 shardfile-dt pass
1066 19:20:51.562152 <12>[ 71.420538] kselftest: Running tests in dt
1067 19:20:51.588664 TAP version 13
1068 19:20:51.613391 1..1
1069 19:20:51.667225 # timeout set to 45
1070 19:20:51.667871 # selftests: dt: test_unprobed_devices.sh
1071 19:20:52.467160 # TAP version 13
1072 19:21:17.169624 # 1..257
1073 19:21:17.367312 # ok 1 / # SKIP
1074 19:21:17.388698 # ok 2 /clk_mcasp0
1075 19:21:17.458352 # ok 3 /clk_mcasp0_fixed # SKIP
1076 19:21:17.531765 # ok 4 /cpus/cpu@0 # SKIP
1077 19:21:17.608256 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1078 19:21:17.623164 # ok 6 /fixedregulator0
1079 19:21:17.642946 # ok 7 /leds
1080 19:21:17.668606 # ok 8 /ocp
1081 19:21:17.691821 # ok 9 /ocp/interconnect@44c00000
1082 19:21:17.718875 # ok 10 /ocp/interconnect@44c00000/segment@0
1083 19:21:17.736320 # ok 11 /ocp/interconnect@44c00000/segment@100000
1084 19:21:17.760389 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1085 19:21:17.830230 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1086 19:21:17.853247 # ok 14 /ocp/interconnect@44c00000/segment@200000
1087 19:21:17.882672 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1088 19:21:17.980383 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1089 19:21:18.056410 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1090 19:21:18.123368 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1091 19:21:18.197374 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1092 19:21:18.266166 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1093 19:21:18.336869 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1094 19:21:18.410894 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1095 19:21:18.476809 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1096 19:21:18.553811 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1097 19:21:18.621061 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1098 19:21:18.691456 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1099 19:21:18.763094 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1100 19:21:18.834163 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1101 19:21:18.905343 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1102 19:21:18.975571 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1103 19:21:19.049162 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1104 19:21:19.117635 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1105 19:21:19.194931 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1106 19:21:19.260745 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1107 19:21:19.331906 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1108 19:21:19.401538 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1109 19:21:19.473375 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1110 19:21:19.544917 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1111 19:21:19.616369 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1112 19:21:19.690024 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1113 19:21:19.763388 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1114 19:21:19.836382 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1115 19:21:19.907676 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1116 19:21:19.978366 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1117 19:21:20.045139 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1118 19:21:20.116661 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1119 19:21:20.187589 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1120 19:21:20.262153 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1121 19:21:20.328287 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1122 19:21:20.405399 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1123 19:21:20.476511 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1124 19:21:20.548121 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1125 19:21:20.614157 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1126 19:21:20.687021 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1127 19:21:20.757630 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1128 19:21:20.829890 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1129 19:21:20.901156 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1130 19:21:20.971014 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1131 19:21:21.043516 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1132 19:21:21.114682 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1133 19:21:21.186003 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1134 19:21:21.257137 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1135 19:21:21.328865 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1136 19:21:21.400564 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1137 19:21:21.470203 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1138 19:21:21.542215 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1139 19:21:21.617557 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1140 19:21:21.685443 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1141 19:21:21.756555 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1142 19:21:21.833376 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1143 19:21:21.904898 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1144 19:21:21.976017 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1145 19:21:22.047955 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1146 19:21:22.115180 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1147 19:21:22.194383 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1148 19:21:22.265273 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1149 19:21:22.337394 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1150 19:21:22.412043 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1151 19:21:22.476998 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1152 19:21:22.554397 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1153 19:21:22.625995 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1154 19:21:22.696329 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1155 19:21:22.766874 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1156 19:21:22.833001 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1157 19:21:22.906907 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1158 19:21:22.974708 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1159 19:21:23.046000 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1160 19:21:23.121454 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1161 19:21:23.192367 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1162 19:21:23.271057 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1163 19:21:23.342771 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1164 19:21:23.417310 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1165 19:21:23.490842 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1166 19:21:23.562053 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1167 19:21:23.581545 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1168 19:21:23.605629 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1169 19:21:23.629112 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1170 19:21:23.655696 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1171 19:21:23.682904 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1172 19:21:23.699945 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1173 19:21:23.724325 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1174 19:21:23.745695 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1175 19:21:23.851101 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1176 19:21:23.875414 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1177 19:21:23.904602 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1178 19:21:23.926285 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1179 19:21:24.028599 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1180 19:21:24.102658 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1181 19:21:24.172604 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1182 19:21:24.244562 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1183 19:21:24.315632 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1184 19:21:24.386542 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1185 19:21:24.458184 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1186 19:21:24.533145 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1187 19:21:24.605249 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1188 19:21:24.678068 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1189 19:21:24.745763 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1190 19:21:24.817643 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1191 19:21:24.889458 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1192 19:21:24.964135 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1193 19:21:25.036665 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1194 19:21:25.108711 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1195 19:21:25.133159 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1196 19:21:25.201236 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1197 19:21:25.270686 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1198 19:21:25.346198 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1199 19:21:25.371299 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1200 19:21:25.438844 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1201 19:21:25.464100 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1202 19:21:25.530552 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1203 19:21:25.553952 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1204 19:21:25.577011 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1205 19:21:25.603436 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1206 19:21:25.625289 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1207 19:21:25.646221 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1208 19:21:25.669902 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1209 19:21:25.696617 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1210 19:21:25.770380 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1211 19:21:25.790572 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1212 19:21:25.813706 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1213 19:21:25.885154 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1214 19:21:25.955686 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1215 19:21:25.975930 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1216 19:21:26.075582 # not ok 144 /ocp/interconnect@47c00000
1217 19:21:26.150149 # not ok 145 /ocp/interconnect@47c00000/segment@0
1218 19:21:26.170803 # ok 146 /ocp/interconnect@48000000
1219 19:21:26.189692 # ok 147 /ocp/interconnect@48000000/segment@0
1220 19:21:26.218130 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1221 19:21:26.241898 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1222 19:21:26.264274 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1223 19:21:26.288119 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1224 19:21:26.306227 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1225 19:21:26.330743 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1226 19:21:26.352764 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1227 19:21:26.428524 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1228 19:21:26.495264 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1229 19:21:26.517967 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1230 19:21:26.541870 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1231 19:21:26.569047 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1232 19:21:26.593143 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1233 19:21:26.614204 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1234 19:21:26.635604 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1235 19:21:26.656930 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1236 19:21:26.681871 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1237 19:21:26.707832 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1238 19:21:26.732766 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1239 19:21:26.754283 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1240 19:21:26.775501 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1241 19:21:26.797692 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1242 19:21:26.820781 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1243 19:21:26.851584 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1244 19:21:26.874161 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1245 19:21:26.895747 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1246 19:21:26.916882 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1247 19:21:26.942331 # ok 175 /ocp/interconnect@48000000/segment@100000
1248 19:21:26.961908 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1249 19:21:26.991891 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1250 19:21:27.063905 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1251 19:21:27.137053 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1252 19:21:27.203547 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1253 19:21:27.278728 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1254 19:21:27.346342 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1255 19:21:27.421960 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1256 19:21:27.491786 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1257 19:21:27.564424 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1258 19:21:27.588493 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1259 19:21:27.607376 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1260 19:21:27.630327 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1261 19:21:27.657938 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1262 19:21:27.677232 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1263 19:21:27.701231 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1264 19:21:27.724354 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1265 19:21:27.748434 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1266 19:21:27.773383 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1267 19:21:27.794281 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1268 19:21:27.817421 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1269 19:21:27.841397 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1270 19:21:27.865963 # ok 198 /ocp/interconnect@48000000/segment@200000
1271 19:21:27.890915 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1272 19:21:27.963077 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1273 19:21:27.981659 # ok 201 /ocp/interconnect@48000000/segment@300000
1274 19:21:28.007817 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1275 19:21:28.031347 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1276 19:21:28.054034 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1277 19:21:28.078642 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1278 19:21:28.103191 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1279 19:21:28.121069 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1280 19:21:28.193724 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1281 19:21:28.216282 # ok 209 /ocp/interconnect@4a000000
1282 19:21:28.239033 # ok 210 /ocp/interconnect@4a000000/segment@0
1283 19:21:28.263000 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1284 19:21:28.286373 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1285 19:21:28.309120 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1286 19:21:28.330295 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1287 19:21:28.401295 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1288 19:21:28.507233 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1289 19:21:28.582885 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1290 19:21:28.686137 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1291 19:21:28.753115 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1292 19:21:28.822465 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1293 19:21:28.920183 # not ok 221 /ocp/interconnect@4b140000
1294 19:21:28.991587 # not ok 222 /ocp/interconnect@4b140000/segment@0
1295 19:21:29.062637 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1296 19:21:29.082930 # ok 224 /ocp/target-module@40300000
1297 19:21:29.109261 # ok 225 /ocp/target-module@40300000/sram@0
1298 19:21:29.180315 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1299 19:21:29.252050 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1300 19:21:29.271198 # ok 228 /ocp/target-module@47400000
1301 19:21:29.292445 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1302 19:21:29.314718 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1303 19:21:29.340697 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1304 19:21:29.362143 # ok 232 /ocp/target-module@47400000/usb@1400
1305 19:21:29.388584 # ok 233 /ocp/target-module@47400000/usb@1800
1306 19:21:29.403823 # ok 234 /ocp/target-module@47810000
1307 19:21:29.425472 # ok 235 /ocp/target-module@49000000
1308 19:21:29.451851 # ok 236 /ocp/target-module@49000000/dma@0
1309 19:21:29.477559 # ok 237 /ocp/target-module@49800000
1310 19:21:29.498642 # ok 238 /ocp/target-module@49800000/dma@0
1311 19:21:29.520119 # ok 239 /ocp/target-module@49900000
1312 19:21:29.538343 # ok 240 /ocp/target-module@49900000/dma@0
1313 19:21:29.561352 # ok 241 /ocp/target-module@49a00000
1314 19:21:29.582269 # ok 242 /ocp/target-module@49a00000/dma@0
1315 19:21:29.603560 # ok 243 /ocp/target-module@4c000000
1316 19:21:29.677964 # not ok 244 /ocp/target-module@4c000000/emif@0
1317 19:21:29.699353 # ok 245 /ocp/target-module@50000000
1318 19:21:29.721153 # ok 246 /ocp/target-module@53100000
1319 19:21:29.791469 # not ok 247 /ocp/target-module@53100000/sham@0
1320 19:21:29.810243 # ok 248 /ocp/target-module@53500000
1321 19:21:29.883394 # not ok 249 /ocp/target-module@53500000/aes@0
1322 19:21:29.907941 # ok 250 /ocp/target-module@56000000
1323 19:21:30.007040 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1324 19:21:30.079479 # ok 252 /opp-table # SKIP
1325 19:21:30.148526 # ok 253 /soc # SKIP
1326 19:21:30.164382 # ok 254 /sound
1327 19:21:30.188584 # ok 255 /target-module@4b000000
1328 19:21:30.217173 # ok 256 /target-module@4b000000/target-module@140000
1329 19:21:30.233664 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1330 19:21:30.241652 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1331 19:21:30.249534 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1332 19:21:32.339703 dt_test_unprobed_devices_sh_ skip
1333 19:21:32.345054 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1334 19:21:32.350596 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1335 19:21:32.350882 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1336 19:21:32.356223 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1337 19:21:32.361771 dt_test_unprobed_devices_sh_fixedregulator0 pass
1338 19:21:32.367379 dt_test_unprobed_devices_sh_leds pass
1339 19:21:32.367636 dt_test_unprobed_devices_sh_ocp pass
1340 19:21:32.372888 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1341 19:21:32.378692 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1342 19:21:32.384185 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1343 19:21:32.395398 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1344 19:21:32.400940 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1345 19:21:32.406512 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1346 19:21:32.417738 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1347 19:21:32.423293 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1348 19:21:32.434621 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1349 19:21:32.445916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1350 19:21:32.457073 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1351 19:21:32.462712 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1352 19:21:32.473909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1353 19:21:32.485114 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1354 19:21:32.496386 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1355 19:21:32.507525 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1356 19:21:32.513124 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1357 19:21:32.524374 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1358 19:21:32.535481 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1359 19:21:32.546703 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1360 19:21:32.557851 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1361 19:21:32.563462 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1362 19:21:32.574655 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1363 19:21:32.585824 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1364 19:21:32.596976 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1365 19:21:32.602611 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1366 19:21:32.613770 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1367 19:21:32.624982 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1368 19:21:32.636224 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1369 19:21:32.647337 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1370 19:21:32.652966 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1371 19:21:32.664198 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1372 19:21:32.675341 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1373 19:21:32.686488 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1374 19:21:32.697833 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1375 19:21:32.708921 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1376 19:21:32.720141 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1377 19:21:32.731382 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1378 19:21:32.742485 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1379 19:21:32.753680 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1380 19:21:32.764876 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1381 19:21:32.776116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1382 19:21:32.787291 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1383 19:21:32.798477 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1384 19:21:32.809725 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1385 19:21:32.820890 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1386 19:21:32.832077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1387 19:21:32.843321 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1388 19:21:32.854495 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1389 19:21:32.865740 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1390 19:21:32.876863 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1391 19:21:32.888303 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1392 19:21:32.899354 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1393 19:21:32.910542 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1394 19:21:32.921728 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1395 19:21:32.932932 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1396 19:21:32.938529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1397 19:21:32.949716 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1398 19:21:32.960916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1399 19:21:32.972111 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1400 19:21:32.983339 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1401 19:21:32.994684 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1402 19:21:33.005907 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1403 19:21:33.016877 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1404 19:21:33.028089 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1405 19:21:33.039290 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1406 19:21:33.050319 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1407 19:21:33.061514 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1408 19:21:33.072714 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1409 19:21:33.083896 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1410 19:21:33.095069 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1411 19:21:33.106305 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1412 19:21:33.117492 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1413 19:21:33.128663 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1414 19:21:33.134517 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1415 19:21:33.145555 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1416 19:21:33.156720 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1417 19:21:33.167943 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1418 19:21:33.179009 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1419 19:21:33.184615 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1420 19:21:33.201444 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1421 19:21:33.212609 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1422 19:21:33.218205 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1423 19:21:33.235006 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1424 19:21:33.246343 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1425 19:21:33.257549 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1426 19:21:33.263101 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1427 19:21:33.274232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1428 19:21:33.285498 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1429 19:21:33.291094 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1430 19:21:33.302236 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1431 19:21:33.313457 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1432 19:21:33.319099 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1433 19:21:33.330218 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1434 19:21:33.335855 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1435 19:21:33.347009 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1436 19:21:33.358326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1437 19:21:33.369494 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1438 19:21:33.380690 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1439 19:21:33.391822 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1440 19:21:33.403013 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1441 19:21:33.414200 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1442 19:21:33.425372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1443 19:21:33.436604 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1444 19:21:33.447834 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1445 19:21:33.458971 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1446 19:21:33.470150 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1447 19:21:33.486921 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1448 19:21:33.498040 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1449 19:21:33.509213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1450 19:21:33.520399 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1451 19:21:33.531589 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1452 19:21:33.548425 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1453 19:21:33.559579 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1454 19:21:33.570768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1455 19:21:33.582025 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1456 19:21:33.587585 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1457 19:21:33.598745 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1458 19:21:33.609972 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1459 19:21:33.615603 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1460 19:21:33.626734 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1461 19:21:33.632388 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1462 19:21:33.643539 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1463 19:21:33.649132 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1464 19:21:33.660353 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1465 19:21:33.666020 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1466 19:21:33.677225 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1467 19:21:33.682744 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1468 19:21:33.693974 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1469 19:21:33.705192 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1470 19:21:33.716391 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1471 19:21:33.727658 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1472 19:21:33.738772 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1473 19:21:33.744432 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1474 19:21:33.755643 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1475 19:21:33.761189 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1476 19:21:33.766782 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1477 19:21:33.772424 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1478 19:21:33.778005 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1479 19:21:33.783705 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1480 19:21:33.794776 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1481 19:21:33.800404 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1482 19:21:33.805981 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1483 19:21:33.817173 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1484 19:21:33.822773 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1485 19:21:33.833957 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1486 19:21:33.839650 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1487 19:21:33.850709 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1488 19:21:33.856351 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1489 19:21:33.867578 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1490 19:21:33.873103 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1491 19:21:33.884358 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1492 19:21:33.889924 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1493 19:21:33.901127 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1494 19:21:33.906764 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1495 19:21:33.917849 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1496 19:21:33.923540 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1497 19:21:33.929128 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1498 19:21:33.941054 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1499 19:21:33.947283 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1500 19:21:33.958028 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1501 19:21:33.963738 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1502 19:21:33.972538 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1503 19:21:33.978217 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1504 19:21:33.989352 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1505 19:21:33.998303 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1506 19:21:34.003914 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1507 19:21:34.302212 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1508 19:21:34.302741 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1509 19:21:34.303045 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1510 19:21:34.303333 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1511 19:21:34.303614 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1512 19:21:34.303889 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1513 19:21:34.304621 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1514 19:21:34.304950 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1515 19:21:34.305242 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1516 19:21:34.305524 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1517 19:21:34.305800 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1518 19:21:34.306078 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1519 19:21:34.306351 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1520 19:21:34.306617 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1521 19:21:34.306880 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1522 19:21:34.307146 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1523 19:21:34.307404 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1524 19:21:34.307663 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1525 19:21:34.307925 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1526 19:21:34.308243 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1527 19:21:34.308509 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1528 19:21:34.308776 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1529 19:21:34.309033 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1530 19:21:34.309291 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1531 19:21:34.309550 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1532 19:21:34.309813 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1533 19:21:34.310069 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1534 19:21:34.310322 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1535 19:21:34.310576 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1536 19:21:34.310832 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1537 19:21:34.311088 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1538 19:21:34.311350 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1539 19:21:34.311605 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1540 19:21:34.311862 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1541 19:21:34.312227 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1542 19:21:34.319216 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1543 19:21:34.324821 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1544 19:21:34.335976 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1545 19:21:34.341591 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1546 19:21:34.352776 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1547 19:21:34.358364 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1548 19:21:34.369594 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1549 19:21:34.380744 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1550 19:21:34.391951 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1551 19:21:34.403210 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1552 19:21:34.408855 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1553 19:21:34.414497 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1554 19:21:34.420093 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1555 19:21:34.425714 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1556 19:21:34.431260 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1557 19:21:34.436870 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1558 19:21:34.442468 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1559 19:21:34.448139 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1560 19:21:34.459226 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1561 19:21:34.464899 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1562 19:21:34.470467 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1563 19:21:34.476094 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1564 19:21:34.481701 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1565 19:21:34.487282 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1566 19:21:34.492925 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1567 19:21:34.498498 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1568 19:21:34.504102 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1569 19:21:34.509647 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1570 19:21:34.515201 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1571 19:21:34.520846 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1572 19:21:34.526480 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1573 19:21:34.532047 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1574 19:21:34.537597 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1575 19:21:34.543162 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1576 19:21:34.548794 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1577 19:21:34.554370 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1578 19:21:34.559970 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1579 19:21:34.565589 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1580 19:21:34.571226 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1581 19:21:34.576779 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1582 19:21:34.582460 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1583 19:21:34.588019 dt_test_unprobed_devices_sh_opp-table skip
1584 19:21:34.588273 dt_test_unprobed_devices_sh_soc skip
1585 19:21:34.593624 dt_test_unprobed_devices_sh_sound pass
1586 19:21:34.599184 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1587 19:21:34.604849 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1588 19:21:34.610401 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1589 19:21:34.616002 dt_test_unprobed_devices_sh fail
1590 19:21:34.621695 + ../../utils/send-to-lava.sh ./output/result.txt
1591 19:21:34.625508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1592 19:21:34.626593 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1594 19:21:34.656772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1595 19:21:34.657411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1597 19:21:34.747807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1598 19:21:34.748917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1600 19:21:34.831974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1601 19:21:34.832632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1603 19:21:34.921825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1604 19:21:34.922453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1606 19:21:35.009156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1607 19:21:35.010061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1609 19:21:35.096273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1610 19:21:35.096912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1612 19:21:35.184604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1613 19:21:35.185525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1615 19:21:35.268830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1616 19:21:35.269724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1618 19:21:35.359229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1619 19:21:35.360096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1621 19:21:35.444274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1622 19:21:35.445200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1624 19:21:35.535006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1625 19:21:35.535926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1627 19:21:35.622353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1628 19:21:35.623286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1630 19:21:35.712089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1631 19:21:35.713138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1633 19:21:35.799966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1634 19:21:35.801524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1636 19:21:35.891021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1637 19:21:35.891665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1639 19:21:35.975429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1640 19:21:35.976112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1642 19:21:36.060912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1643 19:21:36.061520 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1645 19:21:36.151080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1646 19:21:36.151795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1648 19:21:36.235440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1649 19:21:36.236124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1651 19:21:36.327273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1652 19:21:36.328212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1654 19:21:36.476568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1655 19:21:36.477489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1657 19:21:36.562195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1658 19:21:36.563333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1660 19:21:36.652786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1661 19:21:36.653691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1663 19:21:36.747332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1664 19:21:36.748297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1666 19:21:36.850576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1667 19:21:36.851470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1669 19:21:36.938980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1670 19:21:36.939968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1672 19:21:37.030680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1673 19:21:37.031607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1675 19:21:37.123827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1676 19:21:37.124772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1678 19:21:37.272752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1679 19:21:37.273672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1681 19:21:37.368253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1682 19:21:37.369199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1684 19:21:37.454717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1685 19:21:37.455622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1687 19:21:37.545165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1688 19:21:37.546075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1690 19:21:37.635134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1691 19:21:37.636086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1693 19:21:37.741498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1694 19:21:37.742382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1696 19:21:37.832947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1697 19:21:37.833846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1699 19:21:37.925946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1700 19:21:37.927376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1702 19:21:38.024339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1703 19:21:38.025255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1705 19:21:38.108225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1706 19:21:38.109094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1708 19:21:38.199143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1709 19:21:38.200057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1711 19:21:38.289676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1712 19:21:38.290550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1714 19:21:38.402165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1715 19:21:38.403263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1717 19:21:38.506372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1718 19:21:38.506966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1720 19:21:38.599365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1721 19:21:38.600342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1723 19:21:38.690930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1724 19:21:38.691838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1726 19:21:38.781229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1727 19:21:38.782132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1729 19:21:38.872974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1730 19:21:38.873636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1732 19:21:38.966574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1733 19:21:38.967227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1735 19:21:39.051023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1736 19:21:39.051656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1738 19:21:39.136607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1739 19:21:39.137222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1741 19:21:39.231261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1742 19:21:39.231894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1744 19:21:39.323015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1745 19:21:39.323652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1747 19:21:39.415001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1748 19:21:39.415679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1750 19:21:39.507571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1751 19:21:39.508257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1753 19:21:39.604516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1754 19:21:39.605171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1756 19:21:39.699681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1757 19:21:39.700352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1759 19:21:39.952035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1760 19:21:39.952681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1762 19:21:40.048090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1763 19:21:40.048814 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1765 19:21:40.138545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1766 19:21:40.139269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1768 19:21:40.234551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1769 19:21:40.235226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1771 19:21:40.344552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1772 19:21:40.345219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1774 19:21:40.436709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1775 19:21:40.437368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1777 19:21:40.526738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1778 19:21:40.527397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1780 19:21:40.612224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1781 19:21:40.612880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1783 19:21:40.698086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1784 19:21:40.698721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1786 19:21:40.787972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1787 19:21:40.788686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1789 19:21:40.874898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1790 19:21:40.875517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1792 19:21:40.962223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1793 19:21:40.962817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1795 19:21:41.046643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1796 19:21:41.047267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1798 19:21:41.133663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1799 19:21:41.134281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1801 19:21:41.226671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1802 19:21:41.227296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1804 19:21:41.312694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1805 19:21:41.313309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1807 19:21:41.405071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1808 19:21:41.405685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1810 19:21:41.490357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1811 19:21:41.490971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1813 19:21:41.581328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1814 19:21:41.581959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1816 19:21:41.667504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1817 19:21:41.668080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1819 19:21:41.757813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1820 19:21:41.758418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1822 19:21:41.849711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1823 19:21:41.850329 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1825 19:21:41.941434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1826 19:21:41.942033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1828 19:21:42.033993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1829 19:21:42.034630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1831 19:21:42.126136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1832 19:21:42.126735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1834 19:21:42.216459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1835 19:21:42.217093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1837 19:21:42.305617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1838 19:21:42.306253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1840 19:21:42.417959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1841 19:21:42.418811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1843 19:21:42.519540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1844 19:21:42.520242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1846 19:21:42.636429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1847 19:21:42.637337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1849 19:21:42.737616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1850 19:21:42.738459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1852 19:21:42.834150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1853 19:21:42.835048 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1855 19:21:42.923810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1856 19:21:42.924699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1858 19:21:43.011808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1859 19:21:43.012725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1861 19:21:43.105401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1862 19:21:43.106266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1864 19:21:43.198522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1865 19:21:43.199372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1867 19:21:43.294029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1868 19:21:43.295419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1870 19:21:43.407360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1871 19:21:43.412198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1873 19:21:43.500653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1874 19:21:43.501514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1876 19:21:43.591664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1877 19:21:43.592543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1879 19:21:43.687812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1880 19:21:43.688763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1882 19:21:43.781698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1883 19:21:43.782549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1885 19:21:43.877855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1886 19:21:43.878694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1888 19:21:44.286508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1889 19:21:44.287160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1891 19:21:44.287977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1892 19:21:44.288277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1893 19:21:44.288777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1895 19:21:44.289508 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1897 19:21:44.290261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1898 19:21:44.290735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1900 19:21:44.336443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1901 19:21:44.337071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1903 19:21:44.422320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1904 19:21:44.422973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1906 19:21:44.516478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1907 19:21:44.517127 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1909 19:21:44.605435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1910 19:21:44.606033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1912 19:21:44.696911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1913 19:21:44.697556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1915 19:21:44.786200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1916 19:21:44.786871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1918 19:21:44.874686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1919 19:21:44.875285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1921 19:21:44.963731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1922 19:21:44.964652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1924 19:21:45.046404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1925 19:21:45.047284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1927 19:21:45.130388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1928 19:21:45.131204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1930 19:21:45.217736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1931 19:21:45.218538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1933 19:21:45.307656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1934 19:21:45.308535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1936 19:21:45.391868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1937 19:21:45.392698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1939 19:21:45.489797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1940 19:21:45.490712 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1942 19:21:45.587388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1943 19:21:45.589998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1945 19:21:45.677998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1946 19:21:45.678856 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1948 19:21:45.767948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1949 19:21:45.768860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1951 19:21:45.863035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1953 19:21:45.866818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1954 19:21:45.953743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1956 19:21:45.956987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1957 19:21:46.039575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1959 19:21:46.042622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1960 19:21:46.125656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1961 19:21:46.126502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1963 19:21:46.212796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1964 19:21:46.213698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1966 19:21:46.325886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1967 19:21:46.329483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1969 19:21:46.440162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1970 19:21:46.443960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1972 19:21:46.531970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1973 19:21:46.533740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1975 19:21:46.624883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1976 19:21:46.626038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1978 19:21:46.714809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1979 19:21:46.715834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1981 19:21:46.813689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1982 19:21:46.814279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1984 19:21:46.904061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1985 19:21:46.904967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1987 19:21:46.995813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1988 19:21:46.996733 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1990 19:21:47.079644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1991 19:21:47.080538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1993 19:21:47.165233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1994 19:21:47.166124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1996 19:21:47.253749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1997 19:21:47.254374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1999 19:21:47.343645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2000 19:21:47.344286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2002 19:21:47.432857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2003 19:21:47.433452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2005 19:21:47.523632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2006 19:21:47.524396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2008 19:21:47.608114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2009 19:21:47.609012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2011 19:21:47.699805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2012 19:21:47.700760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2014 19:21:47.794281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2015 19:21:47.795100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2017 19:21:47.888163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2018 19:21:47.889010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2020 19:21:47.973122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2021 19:21:47.973965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2023 19:21:48.055897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2024 19:21:48.056758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2026 19:21:48.148909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2027 19:21:48.149834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2029 19:21:48.238436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2030 19:21:48.239032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2032 19:21:48.322577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2033 19:21:48.323191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2035 19:21:48.408217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2036 19:21:48.408833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2038 19:21:48.501221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2039 19:21:48.502111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2041 19:21:48.586867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2042 19:21:48.587759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2044 19:21:48.672853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2045 19:21:48.673769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2047 19:21:48.763082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2048 19:21:48.763709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2050 19:21:48.848769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2051 19:21:48.849391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2053 19:21:48.938220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2054 19:21:48.938844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2056 19:21:49.024015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2057 19:21:49.024657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2059 19:21:49.115773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2060 19:21:49.116416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2062 19:21:49.201728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2063 19:21:49.202339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2065 19:21:49.290482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2066 19:21:49.291107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2068 19:21:49.385937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2069 19:21:49.386558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2071 19:21:49.481017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2072 19:21:49.481663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2074 19:21:49.583278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2075 19:21:49.583921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2077 19:21:49.674299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2078 19:21:49.674943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2080 19:21:49.756841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2081 19:21:49.757487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2083 19:21:49.841365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2084 19:21:49.842023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2086 19:21:49.932190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2087 19:21:49.932836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2089 19:21:50.020247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2090 19:21:50.020923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2092 19:21:50.102585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2093 19:21:50.103424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2095 19:21:50.199500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2096 19:21:50.200337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2098 19:21:50.283808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2099 19:21:50.284599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2101 19:21:50.374929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2102 19:21:50.375729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2104 19:21:50.460794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2105 19:21:50.461588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2107 19:21:50.550961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2108 19:21:50.551803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2110 19:21:50.634839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2111 19:21:50.635579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2113 19:21:50.727173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2114 19:21:50.728040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2116 19:21:50.815438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2117 19:21:50.816311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2119 19:21:50.909587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2120 19:21:50.910575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2122 19:21:51.000805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2123 19:21:51.001625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2125 19:21:51.092467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2126 19:21:51.093297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2128 19:21:51.184132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2129 19:21:51.184898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2131 19:21:51.273132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2132 19:21:51.273973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2134 19:21:51.364832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2135 19:21:51.365436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2137 19:21:51.448819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2138 19:21:51.449407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2140 19:21:51.540916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2141 19:21:51.541524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2143 19:21:51.629936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2144 19:21:51.630569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2146 19:21:51.721229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2147 19:21:51.721846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2149 19:21:51.803544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2150 19:21:51.804211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2152 19:21:51.888397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2153 19:21:51.889020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2155 19:21:51.982031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2156 19:21:51.982668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2158 19:21:52.070990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2159 19:21:52.071613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2161 19:21:52.160276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2162 19:21:52.160882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2164 19:21:52.251563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2165 19:21:52.252232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2167 19:21:52.342991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2168 19:21:52.343629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2170 19:21:52.433497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2171 19:21:52.435018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2173 19:21:52.522109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2174 19:21:52.522722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2176 19:21:52.608409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2177 19:21:52.609030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2179 19:21:52.697036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2180 19:21:52.697679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2182 19:21:52.782324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2183 19:21:52.782961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2185 19:21:52.863732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2186 19:21:52.864433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2188 19:21:52.948826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2189 19:21:52.949473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2191 19:21:53.031705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2192 19:21:53.032361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2194 19:21:53.111266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2195 19:21:53.111882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2197 19:21:53.196285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2198 19:21:53.196913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2200 19:21:53.280545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2201 19:21:53.281163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2203 19:21:53.542710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2204 19:21:53.543348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2206 19:21:53.644068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2207 19:21:53.644686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2209 19:21:53.735041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2210 19:21:53.735641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2212 19:21:53.821814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2213 19:21:53.822404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2215 19:21:53.912392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2216 19:21:53.912954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2218 19:21:53.998663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2219 19:21:53.999242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2221 19:21:54.084578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2222 19:21:54.085183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2224 19:21:54.176315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2225 19:21:54.176881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2227 19:21:54.261780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2228 19:21:54.262345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2230 19:21:54.352414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2231 19:21:54.352998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2233 19:21:54.440705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2234 19:21:54.441319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2236 19:21:54.530662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2237 19:21:54.531276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2239 19:21:54.623029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2240 19:21:54.623659 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2242 19:21:54.712248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2243 19:21:54.712847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2245 19:21:54.792483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2246 19:21:54.793068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2248 19:21:54.874034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2249 19:21:54.874612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2251 19:21:54.956111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2252 19:21:54.956727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2254 19:21:55.034866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2255 19:21:55.035466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2257 19:21:55.123313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2258 19:21:55.123912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2260 19:21:55.204230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2261 19:21:55.204774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2263 19:21:55.285345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2264 19:21:55.285954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2266 19:21:55.368419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2267 19:21:55.369039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2269 19:21:55.451624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2270 19:21:55.452244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2272 19:21:55.530032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2274 19:21:55.533176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2275 19:21:55.612195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2276 19:21:55.612799 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2278 19:21:55.700298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2279 19:21:55.700928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2281 19:21:55.787098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2282 19:21:55.787665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2284 19:21:55.876020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2285 19:21:55.876678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2287 19:21:55.960056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2288 19:21:55.960676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2290 19:21:56.049894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2291 19:21:56.050494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2293 19:21:56.132705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2294 19:21:56.133284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2296 19:21:56.221762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2297 19:21:56.222383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2299 19:21:56.306650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2300 19:21:56.307288 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2302 19:21:56.396180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2303 19:21:56.396827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2305 19:21:56.481093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2306 19:21:56.481695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2308 19:21:56.571587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2309 19:21:56.572260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2311 19:21:56.657498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2312 19:21:56.658110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2314 19:21:56.747103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2315 19:21:56.747760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2317 19:21:56.839119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2318 19:21:56.839756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2320 19:21:56.926411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2321 19:21:56.927011 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2323 19:21:57.016538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2324 19:21:57.017162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2326 19:21:57.100626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2327 19:21:57.101538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2329 19:21:57.189152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2330 19:21:57.190049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2332 19:21:57.273857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2333 19:21:57.274762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2335 19:21:57.357564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2336 19:21:57.358448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2338 19:21:57.447371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2339 19:21:57.448291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2341 19:21:57.536784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2342 19:21:57.537648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2344 19:21:57.628182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2345 19:21:57.629061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2347 19:21:57.710479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2348 19:21:57.711287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2350 19:21:57.796449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2351 19:21:57.797224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2353 19:21:57.884247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2354 19:21:57.885103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2356 19:21:57.976701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2357 19:21:57.977544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2359 19:21:58.068504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2360 19:21:58.069389 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2362 19:21:58.159701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2363 19:21:58.160626 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2365 19:21:58.246649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2366 19:21:58.247275 + set +x
2367 19:21:58.248036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2369 19:21:58.255445 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 972062_1.6.2.4.5>
2370 19:21:58.255952 <LAVA_TEST_RUNNER EXIT>
2371 19:21:58.256678 Received signal: <ENDRUN> 1_kselftest-dt 972062_1.6.2.4.5
2372 19:21:58.257155 Ending use of test pattern.
2373 19:21:58.257590 Ending test lava.1_kselftest-dt (972062_1.6.2.4.5), duration 82.97
2375 19:21:58.259196 ok: lava_test_shell seems to have completed
2376 19:21:58.273085 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2377 19:21:58.275155 end: 3.1 lava-test-shell (duration 00:01:24) [common]
2378 19:21:58.275755 end: 3 lava-test-retry (duration 00:01:24) [common]
2379 19:21:58.276401 start: 4 finalize (timeout 00:05:34) [common]
2380 19:21:58.277013 start: 4.1 power-off (timeout 00:00:30) [common]
2381 19:21:58.278045 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2382 19:21:58.312783 >> OK - accepted request
2383 19:21:58.315477 Returned 0 in 0 seconds
2384 19:21:58.417141 end: 4.1 power-off (duration 00:00:00) [common]
2386 19:21:58.419146 start: 4.2 read-feedback (timeout 00:05:33) [common]
2387 19:21:58.420810 Listened to connection for namespace 'common' for up to 1s
2388 19:21:58.421819 Listened to connection for namespace 'common' for up to 1s
2389 19:21:59.421209 Finalising connection for namespace 'common'
2390 19:21:59.422020 Disconnecting from shell: Finalise
2391 19:21:59.422638 / #
2392 19:21:59.523773 end: 4.2 read-feedback (duration 00:00:01) [common]
2393 19:21:59.524686 end: 4 finalize (duration 00:00:01) [common]
2394 19:21:59.525566 Cleaning after the job
2395 19:21:59.526276 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972062/tftp-deploy-1bslt6of/ramdisk
2396 19:21:59.536158 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972062/tftp-deploy-1bslt6of/kernel
2397 19:21:59.539427 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972062/tftp-deploy-1bslt6of/dtb
2398 19:21:59.540803 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972062/tftp-deploy-1bslt6of/nfsrootfs
2399 19:21:59.692587 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972062/tftp-deploy-1bslt6of/modules
2400 19:21:59.704192 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/972062
2401 19:22:02.724323 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/972062
2402 19:22:02.724928 Job finished correctly