Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 19:32:32.154417 lava-dispatcher, installed at version: 2024.01
2 19:32:32.155185 start: 0 validate
3 19:32:32.155662 Start time: 2024-11-10 19:32:32.155632+00:00 (UTC)
4 19:32:32.156216 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 19:32:32.156766 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 19:32:32.196760 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 19:32:32.197283 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-318-ga9cda7c0ffed%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 19:32:32.229731 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 19:32:32.230334 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-318-ga9cda7c0ffed%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 19:32:32.261714 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 19:32:32.262200 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:32:32.294243 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 19:32:32.294710 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-318-ga9cda7c0ffed%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 19:32:32.334325 validate duration: 0.18
16 19:32:32.335264 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:32:32.335655 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:32:32.336061 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:32:32.336724 Not decompressing ramdisk as can be used compressed.
20 19:32:32.337232 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 19:32:32.337563 saving as /var/lib/lava/dispatcher/tmp/971984/tftp-deploy-ejjs2azl/ramdisk/initrd.cpio.gz
22 19:32:32.337890 total size: 5628169 (5 MB)
23 19:32:32.377239 progress 0 % (0 MB)
24 19:32:32.381559 progress 5 % (0 MB)
25 19:32:32.385993 progress 10 % (0 MB)
26 19:32:32.389886 progress 15 % (0 MB)
27 19:32:32.394098 progress 20 % (1 MB)
28 19:32:32.397911 progress 25 % (1 MB)
29 19:32:32.402111 progress 30 % (1 MB)
30 19:32:32.406356 progress 35 % (1 MB)
31 19:32:32.410217 progress 40 % (2 MB)
32 19:32:32.414819 progress 45 % (2 MB)
33 19:32:32.418787 progress 50 % (2 MB)
34 19:32:32.423022 progress 55 % (2 MB)
35 19:32:32.427243 progress 60 % (3 MB)
36 19:32:32.431057 progress 65 % (3 MB)
37 19:32:32.435303 progress 70 % (3 MB)
38 19:32:32.439199 progress 75 % (4 MB)
39 19:32:32.443500 progress 80 % (4 MB)
40 19:32:32.447347 progress 85 % (4 MB)
41 19:32:32.451593 progress 90 % (4 MB)
42 19:32:32.455699 progress 95 % (5 MB)
43 19:32:32.458999 progress 100 % (5 MB)
44 19:32:32.459638 5 MB downloaded in 0.12 s (44.09 MB/s)
45 19:32:32.460208 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:32:32.461112 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:32:32.461406 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:32:32.461681 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:32:32.462156 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-318-ga9cda7c0ffed/arm64/defconfig/gcc-12/kernel/Image
51 19:32:32.462405 saving as /var/lib/lava/dispatcher/tmp/971984/tftp-deploy-ejjs2azl/kernel/Image
52 19:32:32.462618 total size: 45713920 (43 MB)
53 19:32:32.462830 No compression specified
54 19:32:32.501040 progress 0 % (0 MB)
55 19:32:32.529476 progress 5 % (2 MB)
56 19:32:32.558130 progress 10 % (4 MB)
57 19:32:32.586762 progress 15 % (6 MB)
58 19:32:32.615427 progress 20 % (8 MB)
59 19:32:32.643489 progress 25 % (10 MB)
60 19:32:32.671948 progress 30 % (13 MB)
61 19:32:32.700384 progress 35 % (15 MB)
62 19:32:32.728947 progress 40 % (17 MB)
63 19:32:32.756911 progress 45 % (19 MB)
64 19:32:32.785310 progress 50 % (21 MB)
65 19:32:32.813880 progress 55 % (24 MB)
66 19:32:32.842747 progress 60 % (26 MB)
67 19:32:32.870414 progress 65 % (28 MB)
68 19:32:32.898681 progress 70 % (30 MB)
69 19:32:32.927148 progress 75 % (32 MB)
70 19:32:32.955442 progress 80 % (34 MB)
71 19:32:32.983061 progress 85 % (37 MB)
72 19:32:33.011193 progress 90 % (39 MB)
73 19:32:33.039869 progress 95 % (41 MB)
74 19:32:33.067514 progress 100 % (43 MB)
75 19:32:33.068052 43 MB downloaded in 0.61 s (72.01 MB/s)
76 19:32:33.068548 end: 1.2.1 http-download (duration 00:00:01) [common]
78 19:32:33.069386 end: 1.2 download-retry (duration 00:00:01) [common]
79 19:32:33.069663 start: 1.3 download-retry (timeout 00:09:59) [common]
80 19:32:33.069932 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 19:32:33.070405 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-318-ga9cda7c0ffed/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 19:32:33.070686 saving as /var/lib/lava/dispatcher/tmp/971984/tftp-deploy-ejjs2azl/dtb/meson-g12b-a311d-libretech-cc.dtb
83 19:32:33.070898 total size: 54703 (0 MB)
84 19:32:33.071111 No compression specified
85 19:32:33.114107 progress 59 % (0 MB)
86 19:32:33.114950 progress 100 % (0 MB)
87 19:32:33.115502 0 MB downloaded in 0.04 s (1.17 MB/s)
88 19:32:33.116029 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:32:33.116871 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:32:33.117140 start: 1.4 download-retry (timeout 00:09:59) [common]
92 19:32:33.117408 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 19:32:33.117868 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 19:32:33.118114 saving as /var/lib/lava/dispatcher/tmp/971984/tftp-deploy-ejjs2azl/nfsrootfs/full.rootfs.tar
95 19:32:33.118322 total size: 120894716 (115 MB)
96 19:32:33.118533 Using unxz to decompress xz
97 19:32:33.151269 progress 0 % (0 MB)
98 19:32:33.936093 progress 5 % (5 MB)
99 19:32:34.774085 progress 10 % (11 MB)
100 19:32:35.565196 progress 15 % (17 MB)
101 19:32:36.294355 progress 20 % (23 MB)
102 19:32:36.884396 progress 25 % (28 MB)
103 19:32:37.712402 progress 30 % (34 MB)
104 19:32:38.505445 progress 35 % (40 MB)
105 19:32:38.875848 progress 40 % (46 MB)
106 19:32:39.277886 progress 45 % (51 MB)
107 19:32:40.143591 progress 50 % (57 MB)
108 19:32:41.241709 progress 55 % (63 MB)
109 19:32:42.158472 progress 60 % (69 MB)
110 19:32:42.916529 progress 65 % (74 MB)
111 19:32:43.687538 progress 70 % (80 MB)
112 19:32:44.501630 progress 75 % (86 MB)
113 19:32:45.284846 progress 80 % (92 MB)
114 19:32:46.043064 progress 85 % (98 MB)
115 19:32:46.900253 progress 90 % (103 MB)
116 19:32:47.669959 progress 95 % (109 MB)
117 19:32:48.516705 progress 100 % (115 MB)
118 19:32:48.530508 115 MB downloaded in 15.41 s (7.48 MB/s)
119 19:32:48.531124 end: 1.4.1 http-download (duration 00:00:15) [common]
121 19:32:48.532060 end: 1.4 download-retry (duration 00:00:15) [common]
122 19:32:48.532381 start: 1.5 download-retry (timeout 00:09:44) [common]
123 19:32:48.532681 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 19:32:48.534217 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-318-ga9cda7c0ffed/arm64/defconfig/gcc-12/modules.tar.xz
125 19:32:48.534783 saving as /var/lib/lava/dispatcher/tmp/971984/tftp-deploy-ejjs2azl/modules/modules.tar
126 19:32:48.535251 total size: 11611460 (11 MB)
127 19:32:48.535715 Using unxz to decompress xz
128 19:32:48.587354 progress 0 % (0 MB)
129 19:32:48.653573 progress 5 % (0 MB)
130 19:32:48.726864 progress 10 % (1 MB)
131 19:32:48.822623 progress 15 % (1 MB)
132 19:32:48.915347 progress 20 % (2 MB)
133 19:32:48.994164 progress 25 % (2 MB)
134 19:32:49.070999 progress 30 % (3 MB)
135 19:32:49.149828 progress 35 % (3 MB)
136 19:32:49.221854 progress 40 % (4 MB)
137 19:32:49.297297 progress 45 % (5 MB)
138 19:32:49.382131 progress 50 % (5 MB)
139 19:32:49.459091 progress 55 % (6 MB)
140 19:32:49.545169 progress 60 % (6 MB)
141 19:32:49.628682 progress 65 % (7 MB)
142 19:32:49.711441 progress 70 % (7 MB)
143 19:32:49.788506 progress 75 % (8 MB)
144 19:32:49.871316 progress 80 % (8 MB)
145 19:32:49.950623 progress 85 % (9 MB)
146 19:32:50.028734 progress 90 % (9 MB)
147 19:32:50.106025 progress 95 % (10 MB)
148 19:32:50.184466 progress 100 % (11 MB)
149 19:32:50.195897 11 MB downloaded in 1.66 s (6.67 MB/s)
150 19:32:50.196799 end: 1.5.1 http-download (duration 00:00:02) [common]
152 19:32:50.198406 end: 1.5 download-retry (duration 00:00:02) [common]
153 19:32:50.198926 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 19:32:50.199437 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 19:33:06.857890 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/971984/extract-nfsrootfs-8vrs31uc
156 19:33:06.858490 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 19:33:06.858777 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 19:33:06.859459 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_
159 19:33:06.859909 makedir: /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin
160 19:33:06.860276 makedir: /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/tests
161 19:33:06.860596 makedir: /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/results
162 19:33:06.860928 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-add-keys
163 19:33:06.861479 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-add-sources
164 19:33:06.862011 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-background-process-start
165 19:33:06.862506 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-background-process-stop
166 19:33:06.863071 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-common-functions
167 19:33:06.863589 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-echo-ipv4
168 19:33:06.864116 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-install-packages
169 19:33:06.864696 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-installed-packages
170 19:33:06.865177 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-os-build
171 19:33:06.865677 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-probe-channel
172 19:33:06.866163 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-probe-ip
173 19:33:06.866639 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-target-ip
174 19:33:06.867103 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-target-mac
175 19:33:06.867618 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-target-storage
176 19:33:06.868150 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-test-case
177 19:33:06.868637 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-test-event
178 19:33:06.869105 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-test-feedback
179 19:33:06.869594 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-test-raise
180 19:33:06.870080 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-test-reference
181 19:33:06.870552 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-test-runner
182 19:33:06.871026 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-test-set
183 19:33:06.871535 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-test-shell
184 19:33:06.872047 Updating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-add-keys (debian)
185 19:33:06.872581 Updating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-add-sources (debian)
186 19:33:06.873079 Updating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-install-packages (debian)
187 19:33:06.873571 Updating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-installed-packages (debian)
188 19:33:06.874054 Updating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/bin/lava-os-build (debian)
189 19:33:06.874481 Creating /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/environment
190 19:33:06.874842 LAVA metadata
191 19:33:06.875102 - LAVA_JOB_ID=971984
192 19:33:06.875318 - LAVA_DISPATCHER_IP=192.168.6.2
193 19:33:06.875685 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 19:33:06.876706 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 19:33:06.877023 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 19:33:06.877233 skipped lava-vland-overlay
197 19:33:06.877475 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 19:33:06.877731 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 19:33:06.877950 skipped lava-multinode-overlay
200 19:33:06.878193 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 19:33:06.878443 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 19:33:06.878689 Loading test definitions
203 19:33:06.878966 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 19:33:06.879184 Using /lava-971984 at stage 0
205 19:33:06.880317 uuid=971984_1.6.2.4.1 testdef=None
206 19:33:06.880632 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 19:33:06.880899 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 19:33:06.882453 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 19:33:06.883239 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 19:33:06.885186 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 19:33:06.886024 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 19:33:06.887848 runner path: /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/0/tests/0_timesync-off test_uuid 971984_1.6.2.4.1
215 19:33:06.888458 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 19:33:06.889281 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 19:33:06.889505 Using /lava-971984 at stage 0
219 19:33:06.889864 Fetching tests from https://github.com/kernelci/test-definitions.git
220 19:33:06.890158 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/0/tests/1_kselftest-alsa'
221 19:33:10.731506 Running '/usr/bin/git checkout kernelci.org
222 19:33:11.187832 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 19:33:11.189321 uuid=971984_1.6.2.4.5 testdef=None
224 19:33:11.189687 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 19:33:11.190463 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 19:33:11.193444 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 19:33:11.194313 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 19:33:11.198282 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 19:33:11.199189 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 19:33:11.202911 runner path: /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/0/tests/1_kselftest-alsa test_uuid 971984_1.6.2.4.5
234 19:33:11.203217 BOARD='meson-g12b-a311d-libretech-cc'
235 19:33:11.203440 BRANCH='mainline'
236 19:33:11.203646 SKIPFILE='/dev/null'
237 19:33:11.203850 SKIP_INSTALL='True'
238 19:33:11.204077 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-318-ga9cda7c0ffed/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 19:33:11.204291 TST_CASENAME=''
240 19:33:11.204495 TST_CMDFILES='alsa'
241 19:33:11.205102 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 19:33:11.205927 Creating lava-test-runner.conf files
244 19:33:11.206145 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/971984/lava-overlay-_tlk_ru_/lava-971984/0 for stage 0
245 19:33:11.206519 - 0_timesync-off
246 19:33:11.206780 - 1_kselftest-alsa
247 19:33:11.207281 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 19:33:11.207643 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 19:33:34.634615 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 19:33:34.635086 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 19:33:34.635391 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 19:33:34.635710 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 19:33:34.636038 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 19:33:35.261479 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 19:33:35.261933 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 19:33:35.262205 extracting modules file /var/lib/lava/dispatcher/tmp/971984/tftp-deploy-ejjs2azl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/971984/extract-nfsrootfs-8vrs31uc
257 19:33:36.660482 extracting modules file /var/lib/lava/dispatcher/tmp/971984/tftp-deploy-ejjs2azl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/971984/extract-overlay-ramdisk-gk6iwop2/ramdisk
258 19:33:38.094114 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 19:33:38.094603 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 19:33:38.094881 [common] Applying overlay to NFS
261 19:33:38.095100 [common] Applying overlay /var/lib/lava/dispatcher/tmp/971984/compress-overlay-n_qz3b5m/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/971984/extract-nfsrootfs-8vrs31uc
262 19:33:40.859084 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 19:33:40.859584 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 19:33:40.859863 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 19:33:40.860133 Converting downloaded kernel to a uImage
266 19:33:40.860456 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/971984/tftp-deploy-ejjs2azl/kernel/Image /var/lib/lava/dispatcher/tmp/971984/tftp-deploy-ejjs2azl/kernel/uImage
267 19:33:41.330586 output: Image Name:
268 19:33:41.331022 output: Created: Sun Nov 10 19:33:40 2024
269 19:33:41.331237 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 19:33:41.331444 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 19:33:41.331648 output: Load Address: 01080000
272 19:33:41.331850 output: Entry Point: 01080000
273 19:33:41.332094 output:
274 19:33:41.332438 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 19:33:41.332711 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 19:33:41.332987 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 19:33:41.333245 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 19:33:41.333508 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 19:33:41.333769 Building ramdisk /var/lib/lava/dispatcher/tmp/971984/extract-overlay-ramdisk-gk6iwop2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/971984/extract-overlay-ramdisk-gk6iwop2/ramdisk
280 19:33:43.550547 >> 166829 blocks
281 19:33:51.305531 Adding RAMdisk u-boot header.
282 19:33:51.306198 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/971984/extract-overlay-ramdisk-gk6iwop2/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/971984/extract-overlay-ramdisk-gk6iwop2/ramdisk.cpio.gz.uboot
283 19:33:51.558261 output: Image Name:
284 19:33:51.558691 output: Created: Sun Nov 10 19:33:51 2024
285 19:33:51.558905 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 19:33:51.559113 output: Data Size: 23436227 Bytes = 22886.94 KiB = 22.35 MiB
287 19:33:51.559317 output: Load Address: 00000000
288 19:33:51.559518 output: Entry Point: 00000000
289 19:33:51.559719 output:
290 19:33:51.560596 rename /var/lib/lava/dispatcher/tmp/971984/extract-overlay-ramdisk-gk6iwop2/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/971984/tftp-deploy-ejjs2azl/ramdisk/ramdisk.cpio.gz.uboot
291 19:33:51.561329 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 19:33:51.561870 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 19:33:51.562395 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 19:33:51.562848 No LXC device requested
295 19:33:51.563346 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 19:33:51.563851 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 19:33:51.564388 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 19:33:51.564802 Checking files for TFTP limit of 4294967296 bytes.
299 19:33:51.567467 end: 1 tftp-deploy (duration 00:01:19) [common]
300 19:33:51.568088 start: 2 uboot-action (timeout 00:05:00) [common]
301 19:33:51.568620 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 19:33:51.569114 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 19:33:51.569613 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 19:33:51.570136 Using kernel file from prepare-kernel: 971984/tftp-deploy-ejjs2azl/kernel/uImage
305 19:33:51.570761 substitutions:
306 19:33:51.571168 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 19:33:51.571572 - {DTB_ADDR}: 0x01070000
308 19:33:51.571967 - {DTB}: 971984/tftp-deploy-ejjs2azl/dtb/meson-g12b-a311d-libretech-cc.dtb
309 19:33:51.572406 - {INITRD}: 971984/tftp-deploy-ejjs2azl/ramdisk/ramdisk.cpio.gz.uboot
310 19:33:51.572800 - {KERNEL_ADDR}: 0x01080000
311 19:33:51.573188 - {KERNEL}: 971984/tftp-deploy-ejjs2azl/kernel/uImage
312 19:33:51.573581 - {LAVA_MAC}: None
313 19:33:51.574006 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/971984/extract-nfsrootfs-8vrs31uc
314 19:33:51.574403 - {NFS_SERVER_IP}: 192.168.6.2
315 19:33:51.574788 - {PRESEED_CONFIG}: None
316 19:33:51.575173 - {PRESEED_LOCAL}: None
317 19:33:51.575559 - {RAMDISK_ADDR}: 0x08000000
318 19:33:51.575942 - {RAMDISK}: 971984/tftp-deploy-ejjs2azl/ramdisk/ramdisk.cpio.gz.uboot
319 19:33:51.576371 - {ROOT_PART}: None
320 19:33:51.576763 - {ROOT}: None
321 19:33:51.577147 - {SERVER_IP}: 192.168.6.2
322 19:33:51.577530 - {TEE_ADDR}: 0x83000000
323 19:33:51.577910 - {TEE}: None
324 19:33:51.578289 Parsed boot commands:
325 19:33:51.578657 - setenv autoload no
326 19:33:51.579037 - setenv initrd_high 0xffffffff
327 19:33:51.579417 - setenv fdt_high 0xffffffff
328 19:33:51.579794 - dhcp
329 19:33:51.580202 - setenv serverip 192.168.6.2
330 19:33:51.580585 - tftpboot 0x01080000 971984/tftp-deploy-ejjs2azl/kernel/uImage
331 19:33:51.580967 - tftpboot 0x08000000 971984/tftp-deploy-ejjs2azl/ramdisk/ramdisk.cpio.gz.uboot
332 19:33:51.581351 - tftpboot 0x01070000 971984/tftp-deploy-ejjs2azl/dtb/meson-g12b-a311d-libretech-cc.dtb
333 19:33:51.581732 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/971984/extract-nfsrootfs-8vrs31uc,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 19:33:51.582129 - bootm 0x01080000 0x08000000 0x01070000
335 19:33:51.582625 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 19:33:51.584134 start: 2.3 connect-device (timeout 00:05:00) [common]
338 19:33:51.584551 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 19:33:51.599614 Setting prompt string to ['lava-test: # ']
340 19:33:51.601226 end: 2.3 connect-device (duration 00:00:00) [common]
341 19:33:51.601852 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 19:33:51.602434 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 19:33:51.602979 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 19:33:51.604161 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 19:33:51.640675 >> OK - accepted request
346 19:33:51.643030 Returned 0 in 0 seconds
347 19:33:51.744193 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 19:33:51.745874 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 19:33:51.746442 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 19:33:51.746944 Setting prompt string to ['Hit any key to stop autoboot']
352 19:33:51.747387 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 19:33:51.749003 Trying 192.168.56.21...
354 19:33:51.749522 Connected to conserv1.
355 19:33:51.749940 Escape character is '^]'.
356 19:33:51.750344
357 19:33:51.750767 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 19:33:51.751191
359 19:34:02.656717 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 19:34:02.657207 bl2_stage_init 0x01
361 19:34:02.657488 bl2_stage_init 0x81
362 19:34:02.662290 hw id: 0x0000 - pwm id 0x01
363 19:34:02.663000 bl2_stage_init 0xc1
364 19:34:02.663454 bl2_stage_init 0x02
365 19:34:02.663891
366 19:34:02.676002 L0:00000000
367 19:34:02.676756 L1:20000703
368 19:34:02.677238 L2:00008067
369 19:34:02.677689 L3:14000000
370 19:34:02.678610 B2:00402000
371 19:34:02.679128 B1:e0f83180
372 19:34:02.679565
373 19:34:02.680029 TE: 58167
374 19:34:02.680511
375 19:34:02.682076 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 19:34:02.682441
377 19:34:02.682649 Board ID = 1
378 19:34:02.682847 Set A53 clk to 24M
379 19:34:02.683218 Set A73 clk to 24M
380 19:34:02.693975 Set clk81 to 24M
381 19:34:02.694386 A53 clk: 1200 MHz
382 19:34:02.694594 A73 clk: 1200 MHz
383 19:34:02.694841 CLK81: 166.6M
384 19:34:02.695051 smccc: 00012abd
385 19:34:02.696256 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 19:34:02.702058 board id: 1
387 19:34:02.706127 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 19:34:02.717611 fw parse done
389 19:34:02.723784 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 19:34:02.765367 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 19:34:02.777200 PIEI prepare done
392 19:34:02.777832 fastboot data load
393 19:34:02.778285 fastboot data verify
394 19:34:02.782663 verify result: 266
395 19:34:02.788482 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 19:34:02.789143 LPDDR4 probe
397 19:34:02.789601 ddr clk to 1584MHz
398 19:34:02.796439 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 19:34:02.832735
400 19:34:02.833396 dmc_version 0001
401 19:34:02.839293 Check phy result
402 19:34:02.846134 INFO : End of CA training
403 19:34:02.846682 INFO : End of initialization
404 19:34:02.851709 INFO : Training has run successfully!
405 19:34:02.852270 Check phy result
406 19:34:02.857318 INFO : End of initialization
407 19:34:02.857830 INFO : End of read enable training
408 19:34:02.860642 INFO : End of fine write leveling
409 19:34:02.866243 INFO : End of Write leveling coarse delay
410 19:34:02.871882 INFO : Training has run successfully!
411 19:34:02.872576 Check phy result
412 19:34:02.873236 INFO : End of initialization
413 19:34:02.877481 INFO : End of read dq deskew training
414 19:34:02.880777 INFO : End of MPR read delay center optimization
415 19:34:02.886341 INFO : End of write delay center optimization
416 19:34:02.892065 INFO : End of read delay center optimization
417 19:34:02.892669 INFO : End of max read latency training
418 19:34:02.897541 INFO : Training has run successfully!
419 19:34:02.898134 1D training succeed
420 19:34:02.905794 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 19:34:02.953404 Check phy result
422 19:34:02.954139 INFO : End of initialization
423 19:34:02.975273 INFO : End of 2D read delay Voltage center optimization
424 19:34:02.994447 INFO : End of 2D read delay Voltage center optimization
425 19:34:03.046637 INFO : End of 2D write delay Voltage center optimization
426 19:34:03.096839 INFO : End of 2D write delay Voltage center optimization
427 19:34:03.102414 INFO : Training has run successfully!
428 19:34:03.102978
429 19:34:03.103432 channel==0
430 19:34:03.108068 RxClkDly_Margin_A0==88 ps 9
431 19:34:03.108603 TxDqDly_Margin_A0==98 ps 10
432 19:34:03.113567 RxClkDly_Margin_A1==88 ps 9
433 19:34:03.114103 TxDqDly_Margin_A1==98 ps 10
434 19:34:03.114544 TrainedVREFDQ_A0==74
435 19:34:03.119238 TrainedVREFDQ_A1==74
436 19:34:03.119777 VrefDac_Margin_A0==25
437 19:34:03.120273 DeviceVref_Margin_A0==40
438 19:34:03.124805 VrefDac_Margin_A1==25
439 19:34:03.125392 DeviceVref_Margin_A1==40
440 19:34:03.125845
441 19:34:03.126298
442 19:34:03.130418 channel==1
443 19:34:03.131029 RxClkDly_Margin_A0==98 ps 10
444 19:34:03.131476 TxDqDly_Margin_A0==88 ps 9
445 19:34:03.136088 RxClkDly_Margin_A1==98 ps 10
446 19:34:03.136706 TxDqDly_Margin_A1==88 ps 9
447 19:34:03.142016 TrainedVREFDQ_A0==76
448 19:34:03.142642 TrainedVREFDQ_A1==77
449 19:34:03.142975 VrefDac_Margin_A0==22
450 19:34:03.147261 DeviceVref_Margin_A0==38
451 19:34:03.147873 VrefDac_Margin_A1==22
452 19:34:03.152846 DeviceVref_Margin_A1==37
453 19:34:03.153447
454 19:34:03.153902 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 19:34:03.154378
456 19:34:03.194232 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000018 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
457 19:34:03.194894 2D training succeed
458 19:34:03.195431 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 19:34:03.197721 auto size-- 65535DDR cs0 size: 2048MB
460 19:34:03.198337 DDR cs1 size: 2048MB
461 19:34:03.203404 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 19:34:03.204037 cs0 DataBus test pass
463 19:34:03.208947 cs1 DataBus test pass
464 19:34:03.209548 cs0 AddrBus test pass
465 19:34:03.209996 cs1 AddrBus test pass
466 19:34:03.210429
467 19:34:03.214514 100bdlr_step_size ps== 420
468 19:34:03.215141 result report
469 19:34:03.223507 boot times 0Enable ddr reg access
470 19:34:03.224717 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 19:34:03.237908 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 19:34:03.812367 0.0;M3 CHK:0;cm4_sp_mode 0
473 19:34:03.813057 MVN_1=0x00000000
474 19:34:03.817846 MVN_2=0x00000000
475 19:34:03.823540 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 19:34:03.824066 OPS=0x10
477 19:34:03.824516 ring efuse init
478 19:34:03.824950 chipver efuse init
479 19:34:03.829168 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 19:34:03.834765 [0.018961 Inits done]
481 19:34:03.835247 secure task start!
482 19:34:03.835681 high task start!
483 19:34:03.839321 low task start!
484 19:34:03.839824 run into bl31
485 19:34:03.845999 NOTICE: BL31: v1.3(release):4fc40b1
486 19:34:03.853816 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 19:34:03.854319 NOTICE: BL31: G12A normal boot!
488 19:34:03.879197 NOTICE: BL31: BL33 decompress pass
489 19:34:03.884947 ERROR: Error initializing runtime service opteed_fast
490 19:34:05.117744
491 19:34:05.118147
492 19:34:05.126182 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 19:34:05.126500
494 19:34:05.126717 Model: Libre Computer AML-A311D-CC Alta
495 19:34:05.334512 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 19:34:05.357922 DRAM: 2 GiB (effective 3.8 GiB)
497 19:34:05.500936 Core: 408 devices, 31 uclasses, devicetree: separate
498 19:34:05.506767 WDT: Not starting watchdog@f0d0
499 19:34:05.539094 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 19:34:05.551512 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 19:34:05.556457 ** Bad device specification mmc 0 **
502 19:34:05.566792 Card did not respond to voltage select! : -110
503 19:34:05.574471 ** Bad device specification mmc 0 **
504 19:34:05.574820 Couldn't find partition mmc 0
505 19:34:05.582824 Card did not respond to voltage select! : -110
506 19:34:05.588269 ** Bad device specification mmc 0 **
507 19:34:05.588570 Couldn't find partition mmc 0
508 19:34:05.593331 Error: could not access storage.
509 19:34:06.856435 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 19:34:06.856838 bl2_stage_init 0x01
511 19:34:06.857051 bl2_stage_init 0x81
512 19:34:06.861979 hw id: 0x0000 - pwm id 0x01
513 19:34:06.862258 bl2_stage_init 0xc1
514 19:34:06.862468 bl2_stage_init 0x02
515 19:34:06.862668
516 19:34:06.867570 L0:00000000
517 19:34:06.867848 L1:20000703
518 19:34:06.868089 L2:00008067
519 19:34:06.868306 L3:14000000
520 19:34:06.870437 B2:00402000
521 19:34:06.870710 B1:e0f83180
522 19:34:06.870914
523 19:34:06.871112 TE: 58167
524 19:34:06.871311
525 19:34:06.881590 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 19:34:06.881940
527 19:34:06.882151 Board ID = 1
528 19:34:06.882351 Set A53 clk to 24M
529 19:34:06.882548 Set A73 clk to 24M
530 19:34:06.887213 Set clk81 to 24M
531 19:34:06.887488 A53 clk: 1200 MHz
532 19:34:06.887691 A73 clk: 1200 MHz
533 19:34:06.890525 CLK81: 166.6M
534 19:34:06.890785 smccc: 00012abd
535 19:34:06.896077 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 19:34:06.901686 board id: 1
537 19:34:06.906119 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 19:34:06.917705 fw parse done
539 19:34:06.922734 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 19:34:06.966400 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 19:34:06.977330 PIEI prepare done
542 19:34:06.977634 fastboot data load
543 19:34:06.977848 fastboot data verify
544 19:34:06.982862 verify result: 266
545 19:34:06.988476 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 19:34:06.988753 LPDDR4 probe
547 19:34:06.988959 ddr clk to 1584MHz
548 19:34:06.996505 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 19:34:07.033785
550 19:34:07.034295 dmc_version 0001
551 19:34:07.039615 Check phy result
552 19:34:07.046311 INFO : End of CA training
553 19:34:07.046597 INFO : End of initialization
554 19:34:07.051871 INFO : Training has run successfully!
555 19:34:07.052300 Check phy result
556 19:34:07.057486 INFO : End of initialization
557 19:34:07.057882 INFO : End of read enable training
558 19:34:07.063058 INFO : End of fine write leveling
559 19:34:07.068664 INFO : End of Write leveling coarse delay
560 19:34:07.068951 INFO : Training has run successfully!
561 19:34:07.069158 Check phy result
562 19:34:07.074322 INFO : End of initialization
563 19:34:07.074612 INFO : End of read dq deskew training
564 19:34:07.079850 INFO : End of MPR read delay center optimization
565 19:34:07.085504 INFO : End of write delay center optimization
566 19:34:07.091075 INFO : End of read delay center optimization
567 19:34:07.091361 INFO : End of max read latency training
568 19:34:07.096682 INFO : Training has run successfully!
569 19:34:07.097083 1D training succeed
570 19:34:07.105812 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 19:34:07.152486 Check phy result
572 19:34:07.152826 INFO : End of initialization
573 19:34:07.174242 INFO : End of 2D read delay Voltage center optimization
574 19:34:07.194450 INFO : End of 2D read delay Voltage center optimization
575 19:34:07.246629 INFO : End of 2D write delay Voltage center optimization
576 19:34:07.296791 INFO : End of 2D write delay Voltage center optimization
577 19:34:07.302453 INFO : Training has run successfully!
578 19:34:07.302743
579 19:34:07.302961 channel==0
580 19:34:07.307968 RxClkDly_Margin_A0==88 ps 9
581 19:34:07.308296 TxDqDly_Margin_A0==98 ps 10
582 19:34:07.313555 RxClkDly_Margin_A1==88 ps 9
583 19:34:07.313961 TxDqDly_Margin_A1==98 ps 10
584 19:34:07.314303 TrainedVREFDQ_A0==74
585 19:34:07.319162 TrainedVREFDQ_A1==74
586 19:34:07.319435 VrefDac_Margin_A0==25
587 19:34:07.319648 DeviceVref_Margin_A0==40
588 19:34:07.324804 VrefDac_Margin_A1==25
589 19:34:07.325287 DeviceVref_Margin_A1==40
590 19:34:07.325704
591 19:34:07.326114
592 19:34:07.330458 channel==1
593 19:34:07.330892 RxClkDly_Margin_A0==98 ps 10
594 19:34:07.331297 TxDqDly_Margin_A0==88 ps 9
595 19:34:07.335931 RxClkDly_Margin_A1==98 ps 10
596 19:34:07.336380 TxDqDly_Margin_A1==88 ps 9
597 19:34:07.341526 TrainedVREFDQ_A0==77
598 19:34:07.341957 TrainedVREFDQ_A1==77
599 19:34:07.342365 VrefDac_Margin_A0==22
600 19:34:07.347115 DeviceVref_Margin_A0==37
601 19:34:07.347549 VrefDac_Margin_A1==22
602 19:34:07.352752 DeviceVref_Margin_A1==37
603 19:34:07.353211
604 19:34:07.353631 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 19:34:07.354046
606 19:34:07.386464 soc_vref_reg_value 0x 00000019 00000019 00000018 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
607 19:34:07.386980 2D training succeed
608 19:34:07.391956 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 19:34:07.397538 auto size-- 65535DDR cs0 size: 2048MB
610 19:34:07.398011 DDR cs1 size: 2048MB
611 19:34:07.403168 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 19:34:07.403623 cs0 DataBus test pass
613 19:34:07.408738 cs1 DataBus test pass
614 19:34:07.409197 cs0 AddrBus test pass
615 19:34:07.409607 cs1 AddrBus test pass
616 19:34:07.410004
617 19:34:07.414485 100bdlr_step_size ps== 420
618 19:34:07.414962 result report
619 19:34:07.419970 boot times 0Enable ddr reg access
620 19:34:07.425292 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 19:34:07.438780 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 19:34:08.012759 0.0;M3 CHK:0;cm4_sp_mode 0
623 19:34:08.013340 MVN_1=0x00000000
624 19:34:08.018286 MVN_2=0x00000000
625 19:34:08.024025 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 19:34:08.024593 OPS=0x10
627 19:34:08.025059 ring efuse init
628 19:34:08.025451 chipver efuse init
629 19:34:08.032371 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 19:34:08.032877 [0.018960 Inits done]
631 19:34:08.033264 secure task start!
632 19:34:08.039616 high task start!
633 19:34:08.040086 low task start!
634 19:34:08.040479 run into bl31
635 19:34:08.046155 NOTICE: BL31: v1.3(release):4fc40b1
636 19:34:08.053994 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 19:34:08.054440 NOTICE: BL31: G12A normal boot!
638 19:34:08.079406 NOTICE: BL31: BL33 decompress pass
639 19:34:08.085010 ERROR: Error initializing runtime service opteed_fast
640 19:34:09.317948
641 19:34:09.318542
642 19:34:09.326279 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 19:34:09.326726
644 19:34:09.327131 Model: Libre Computer AML-A311D-CC Alta
645 19:34:09.533991 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 19:34:09.558158 DRAM: 2 GiB (effective 3.8 GiB)
647 19:34:09.701269 Core: 408 devices, 31 uclasses, devicetree: separate
648 19:34:09.706089 WDT: Not starting watchdog@f0d0
649 19:34:09.739270 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 19:34:09.751734 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 19:34:09.756601 ** Bad device specification mmc 0 **
652 19:34:09.766951 Card did not respond to voltage select! : -110
653 19:34:09.774602 ** Bad device specification mmc 0 **
654 19:34:09.775036 Couldn't find partition mmc 0
655 19:34:09.782925 Card did not respond to voltage select! : -110
656 19:34:09.788455 ** Bad device specification mmc 0 **
657 19:34:09.788940 Couldn't find partition mmc 0
658 19:34:09.793507 Error: could not access storage.
659 19:34:10.136243 Net: eth0: ethernet@ff3f0000
660 19:34:10.136822 starting USB...
661 19:34:10.388047 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 19:34:10.388589 Starting the controller
663 19:34:10.394874 USB XHCI 1.10
664 19:34:12.107356 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 19:34:12.107780 bl2_stage_init 0x01
666 19:34:12.108051 bl2_stage_init 0x81
667 19:34:12.112900 hw id: 0x0000 - pwm id 0x01
668 19:34:12.113174 bl2_stage_init 0xc1
669 19:34:12.113392 bl2_stage_init 0x02
670 19:34:12.113596
671 19:34:12.118483 L0:00000000
672 19:34:12.118859 L1:20000703
673 19:34:12.119193 L2:00008067
674 19:34:12.119516 L3:14000000
675 19:34:12.124138 B2:00402000
676 19:34:12.124510 B1:e0f83180
677 19:34:12.124839
678 19:34:12.125167 TE: 58159
679 19:34:12.125404
680 19:34:12.129679 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 19:34:12.129952
682 19:34:12.130168 Board ID = 1
683 19:34:12.135309 Set A53 clk to 24M
684 19:34:12.135579 Set A73 clk to 24M
685 19:34:12.135790 Set clk81 to 24M
686 19:34:12.140891 A53 clk: 1200 MHz
687 19:34:12.141157 A73 clk: 1200 MHz
688 19:34:12.141369 CLK81: 166.6M
689 19:34:12.141571 smccc: 00012ab5
690 19:34:12.146516 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 19:34:12.152112 board id: 1
692 19:34:12.157987 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 19:34:12.168623 fw parse done
694 19:34:12.174590 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 19:34:12.217248 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 19:34:12.228126 PIEI prepare done
697 19:34:12.228411 fastboot data load
698 19:34:12.228627 fastboot data verify
699 19:34:12.233721 verify result: 266
700 19:34:12.239330 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 19:34:12.239601 LPDDR4 probe
702 19:34:12.239814 ddr clk to 1584MHz
703 19:34:12.247291 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 19:34:12.284599
705 19:34:12.284926 dmc_version 0001
706 19:34:12.291264 Check phy result
707 19:34:12.297144 INFO : End of CA training
708 19:34:12.297558 INFO : End of initialization
709 19:34:12.302713 INFO : Training has run successfully!
710 19:34:12.302985 Check phy result
711 19:34:12.308309 INFO : End of initialization
712 19:34:12.308700 INFO : End of read enable training
713 19:34:12.313918 INFO : End of fine write leveling
714 19:34:12.319513 INFO : End of Write leveling coarse delay
715 19:34:12.319780 INFO : Training has run successfully!
716 19:34:12.320021 Check phy result
717 19:34:12.325134 INFO : End of initialization
718 19:34:12.325399 INFO : End of read dq deskew training
719 19:34:12.330704 INFO : End of MPR read delay center optimization
720 19:34:12.336304 INFO : End of write delay center optimization
721 19:34:12.341899 INFO : End of read delay center optimization
722 19:34:12.342162 INFO : End of max read latency training
723 19:34:12.347487 INFO : Training has run successfully!
724 19:34:12.347879 1D training succeed
725 19:34:12.356696 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 19:34:12.404409 Check phy result
727 19:34:12.404739 INFO : End of initialization
728 19:34:12.426150 INFO : End of 2D read delay Voltage center optimization
729 19:34:12.446297 INFO : End of 2D read delay Voltage center optimization
730 19:34:12.498350 INFO : End of 2D write delay Voltage center optimization
731 19:34:12.547753 INFO : End of 2D write delay Voltage center optimization
732 19:34:12.553235 INFO : Training has run successfully!
733 19:34:12.553526
734 19:34:12.553743 channel==0
735 19:34:12.558832 RxClkDly_Margin_A0==88 ps 9
736 19:34:12.559239 TxDqDly_Margin_A0==108 ps 11
737 19:34:12.562139 RxClkDly_Margin_A1==88 ps 9
738 19:34:12.562533 TxDqDly_Margin_A1==98 ps 10
739 19:34:12.567874 TrainedVREFDQ_A0==74
740 19:34:12.568209 TrainedVREFDQ_A1==74
741 19:34:12.573351 VrefDac_Margin_A0==24
742 19:34:12.573623 DeviceVref_Margin_A0==40
743 19:34:12.573832 VrefDac_Margin_A1==24
744 19:34:12.578874 DeviceVref_Margin_A1==40
745 19:34:12.579140
746 19:34:12.579354
747 19:34:12.579560 channel==1
748 19:34:12.579760 RxClkDly_Margin_A0==98 ps 10
749 19:34:12.584490 TxDqDly_Margin_A0==98 ps 10
750 19:34:12.584960 RxClkDly_Margin_A1==98 ps 10
751 19:34:12.590099 TxDqDly_Margin_A1==98 ps 10
752 19:34:12.590530 TrainedVREFDQ_A0==78
753 19:34:12.590936 TrainedVREFDQ_A1==77
754 19:34:12.595708 VrefDac_Margin_A0==22
755 19:34:12.596146 DeviceVref_Margin_A0==36
756 19:34:12.601334 VrefDac_Margin_A1==22
757 19:34:12.601749 DeviceVref_Margin_A1==37
758 19:34:12.602144
759 19:34:12.607082 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 19:34:12.607526
761 19:34:12.635043 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
762 19:34:12.640625 2D training succeed
763 19:34:12.646238 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 19:34:12.646680 auto size-- 65535DDR cs0 size: 2048MB
765 19:34:12.651813 DDR cs1 size: 2048MB
766 19:34:12.652295 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 19:34:12.657423 cs0 DataBus test pass
768 19:34:12.657859 cs1 DataBus test pass
769 19:34:12.658258 cs0 AddrBus test pass
770 19:34:12.662992 cs1 AddrBus test pass
771 19:34:12.663424
772 19:34:12.663823 100bdlr_step_size ps== 415
773 19:34:12.664269 result report
774 19:34:12.668595 boot times 0Enable ddr reg access
775 19:34:12.676530 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 19:34:12.689997 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 19:34:13.263933 0.0;M3 CHK:0;cm4_sp_mode 0
778 19:34:13.264595 MVN_1=0x00000000
779 19:34:13.269239 MVN_2=0x00000000
780 19:34:13.275041 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 19:34:13.275558 OPS=0x10
782 19:34:13.275948 ring efuse init
783 19:34:13.276373 chipver efuse init
784 19:34:13.283400 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 19:34:13.283845 [0.018961 Inits done]
786 19:34:13.284267 secure task start!
787 19:34:13.290840 high task start!
788 19:34:13.291266 low task start!
789 19:34:13.291647 run into bl31
790 19:34:13.297420 NOTICE: BL31: v1.3(release):4fc40b1
791 19:34:13.305339 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 19:34:13.305764 NOTICE: BL31: G12A normal boot!
793 19:34:13.330608 NOTICE: BL31: BL33 decompress pass
794 19:34:13.336401 ERROR: Error initializing runtime service opteed_fast
795 19:34:14.569173
796 19:34:14.569795
797 19:34:14.577547 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 19:34:14.578010
799 19:34:14.578421 Model: Libre Computer AML-A311D-CC Alta
800 19:34:14.786104 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 19:34:14.809426 DRAM: 2 GiB (effective 3.8 GiB)
802 19:34:14.952270 Core: 408 devices, 31 uclasses, devicetree: separate
803 19:34:14.958212 WDT: Not starting watchdog@f0d0
804 19:34:14.990535 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 19:34:15.002884 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 19:34:15.007957 ** Bad device specification mmc 0 **
807 19:34:15.018295 Card did not respond to voltage select! : -110
808 19:34:15.025967 ** Bad device specification mmc 0 **
809 19:34:15.026413 Couldn't find partition mmc 0
810 19:34:15.034262 Card did not respond to voltage select! : -110
811 19:34:15.039769 ** Bad device specification mmc 0 **
812 19:34:15.040235 Couldn't find partition mmc 0
813 19:34:15.044865 Error: could not access storage.
814 19:34:15.387392 Net: eth0: ethernet@ff3f0000
815 19:34:15.387919 starting USB...
816 19:34:15.639141 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 19:34:15.639720 Starting the controller
818 19:34:15.646140 USB XHCI 1.10
819 19:34:17.807166 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
820 19:34:17.807780 bl2_stage_init 0x81
821 19:34:17.812545 hw id: 0x0000 - pwm id 0x01
822 19:34:17.812995 bl2_stage_init 0xc1
823 19:34:17.813403 bl2_stage_init 0x02
824 19:34:17.813803
825 19:34:17.818147 L0:00000000
826 19:34:17.818578 L1:20000703
827 19:34:17.818973 L2:00008067
828 19:34:17.819367 L3:14000000
829 19:34:17.819761 B2:00402000
830 19:34:17.821052 B1:e0f83180
831 19:34:17.821486
832 19:34:17.821890 TE: 58150
833 19:34:17.822286
834 19:34:17.832207 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 19:34:17.832654
836 19:34:17.833057 Board ID = 1
837 19:34:17.833447 Set A53 clk to 24M
838 19:34:17.833837 Set A73 clk to 24M
839 19:34:17.837823 Set clk81 to 24M
840 19:34:17.838249 A53 clk: 1200 MHz
841 19:34:17.838645 A73 clk: 1200 MHz
842 19:34:17.841244 CLK81: 166.6M
843 19:34:17.841675 smccc: 00012aac
844 19:34:17.846874 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 19:34:17.852427 board id: 1
846 19:34:17.857528 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 19:34:17.868175 fw parse done
848 19:34:17.874125 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 19:34:17.916686 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 19:34:17.927638 PIEI prepare done
851 19:34:17.928141 fastboot data load
852 19:34:17.928553 fastboot data verify
853 19:34:17.933188 verify result: 266
854 19:34:17.938743 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 19:34:17.939179 LPDDR4 probe
856 19:34:17.939578 ddr clk to 1584MHz
857 19:34:17.946881 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 19:34:17.984174
859 19:34:17.984782 dmc_version 0001
860 19:34:17.990049 Check phy result
861 19:34:17.996756 INFO : End of CA training
862 19:34:17.997290 INFO : End of initialization
863 19:34:18.002340 INFO : Training has run successfully!
864 19:34:18.002878 Check phy result
865 19:34:18.008033 INFO : End of initialization
866 19:34:18.008585 INFO : End of read enable training
867 19:34:18.013622 INFO : End of fine write leveling
868 19:34:18.019178 INFO : End of Write leveling coarse delay
869 19:34:18.019741 INFO : Training has run successfully!
870 19:34:18.020253 Check phy result
871 19:34:18.024780 INFO : End of initialization
872 19:34:18.025328 INFO : End of read dq deskew training
873 19:34:18.030366 INFO : End of MPR read delay center optimization
874 19:34:18.035966 INFO : End of write delay center optimization
875 19:34:18.041601 INFO : End of read delay center optimization
876 19:34:18.042142 INFO : End of max read latency training
877 19:34:18.047133 INFO : Training has run successfully!
878 19:34:18.047674 1D training succeed
879 19:34:18.056311 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 19:34:18.103105 Check phy result
881 19:34:18.103742 INFO : End of initialization
882 19:34:18.125678 INFO : End of 2D read delay Voltage center optimization
883 19:34:18.146010 INFO : End of 2D read delay Voltage center optimization
884 19:34:18.198016 INFO : End of 2D write delay Voltage center optimization
885 19:34:18.247392 INFO : End of 2D write delay Voltage center optimization
886 19:34:18.253037 INFO : Training has run successfully!
887 19:34:18.253584
888 19:34:18.254045 channel==0
889 19:34:18.258584 RxClkDly_Margin_A0==88 ps 9
890 19:34:18.259115 TxDqDly_Margin_A0==98 ps 10
891 19:34:18.264277 RxClkDly_Margin_A1==88 ps 9
892 19:34:18.264841 TxDqDly_Margin_A1==98 ps 10
893 19:34:18.265337 TrainedVREFDQ_A0==74
894 19:34:18.269762 TrainedVREFDQ_A1==74
895 19:34:18.270329 VrefDac_Margin_A0==25
896 19:34:18.270790 DeviceVref_Margin_A0==40
897 19:34:18.275387 VrefDac_Margin_A1==25
898 19:34:18.275935 DeviceVref_Margin_A1==40
899 19:34:18.276413
900 19:34:18.276842
901 19:34:18.280960 channel==1
902 19:34:18.281481 RxClkDly_Margin_A0==98 ps 10
903 19:34:18.281914 TxDqDly_Margin_A0==98 ps 10
904 19:34:18.286493 RxClkDly_Margin_A1==88 ps 9
905 19:34:18.287009 TxDqDly_Margin_A1==88 ps 9
906 19:34:18.292274 TrainedVREFDQ_A0==77
907 19:34:18.292797 TrainedVREFDQ_A1==77
908 19:34:18.293226 VrefDac_Margin_A0==22
909 19:34:18.297766 DeviceVref_Margin_A0==37
910 19:34:18.298281 VrefDac_Margin_A1==24
911 19:34:18.303379 DeviceVref_Margin_A1==37
912 19:34:18.303893
913 19:34:18.304370 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 19:34:18.304794
915 19:34:18.336786 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
916 19:34:18.337371 2D training succeed
917 19:34:18.342458 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 19:34:18.348125 auto size-- 65535DDR cs0 size: 2048MB
919 19:34:18.348649 DDR cs1 size: 2048MB
920 19:34:18.353649 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 19:34:18.354165 cs0 DataBus test pass
922 19:34:18.359262 cs1 DataBus test pass
923 19:34:18.359781 cs0 AddrBus test pass
924 19:34:18.360263 cs1 AddrBus test pass
925 19:34:18.360688
926 19:34:18.364831 100bdlr_step_size ps== 420
927 19:34:18.365359 result report
928 19:34:18.370411 boot times 0Enable ddr reg access
929 19:34:18.375764 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 19:34:18.388332 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 19:34:18.962273 0.0;M3 CHK:0;cm4_sp_mode 0
932 19:34:18.962936 MVN_1=0x00000000
933 19:34:18.968107 MVN_2=0x00000000
934 19:34:18.973523 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 19:34:18.974084 OPS=0x10
936 19:34:18.974550 ring efuse init
937 19:34:18.974993 chipver efuse init
938 19:34:18.979184 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 19:34:18.984718 [0.018961 Inits done]
940 19:34:18.985294 secure task start!
941 19:34:18.985763 high task start!
942 19:34:18.989290 low task start!
943 19:34:18.989830 run into bl31
944 19:34:18.997916 NOTICE: BL31: v1.3(release):4fc40b1
945 19:34:19.003729 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 19:34:19.004324 NOTICE: BL31: G12A normal boot!
947 19:34:19.029151 NOTICE: BL31: BL33 decompress pass
948 19:34:19.034767 ERROR: Error initializing runtime service opteed_fast
949 19:34:20.267462
950 19:34:20.267871
951 19:34:20.276101 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 19:34:20.276657
953 19:34:20.277124 Model: Libre Computer AML-A311D-CC Alta
954 19:34:20.483649 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 19:34:20.507904 DRAM: 2 GiB (effective 3.8 GiB)
956 19:34:20.651019 Core: 408 devices, 31 uclasses, devicetree: separate
957 19:34:20.656848 WDT: Not starting watchdog@f0d0
958 19:34:20.689060 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 19:34:20.701455 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 19:34:20.706505 ** Bad device specification mmc 0 **
961 19:34:20.716815 Card did not respond to voltage select! : -110
962 19:34:20.724493 ** Bad device specification mmc 0 **
963 19:34:20.725013 Couldn't find partition mmc 0
964 19:34:20.732814 Card did not respond to voltage select! : -110
965 19:34:20.738418 ** Bad device specification mmc 0 **
966 19:34:20.738925 Couldn't find partition mmc 0
967 19:34:20.743515 Error: could not access storage.
968 19:34:21.084904 Net: eth0: ethernet@ff3f0000
969 19:34:21.085528 starting USB...
970 19:34:21.337676 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 19:34:21.338270 Starting the controller
972 19:34:21.344659 USB XHCI 1.10
973 19:34:23.206419 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
974 19:34:23.206823 bl2_stage_init 0x01
975 19:34:23.207063 bl2_stage_init 0x81
976 19:34:23.211959 hw id: 0x0000 - pwm id 0x01
977 19:34:23.212402 bl2_stage_init 0xc1
978 19:34:23.212754 bl2_stage_init 0x02
979 19:34:23.213100
980 19:34:23.217581 L0:00000000
981 19:34:23.217971 L1:20000703
982 19:34:23.218229 L2:00008067
983 19:34:23.218455 L3:14000000
984 19:34:23.220511 B2:00402000
985 19:34:23.220904 B1:e0f83180
986 19:34:23.221257
987 19:34:23.221603 TE: 58167
988 19:34:23.221943
989 19:34:23.231778 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
990 19:34:23.232159
991 19:34:23.232637 Board ID = 1
992 19:34:23.233076 Set A53 clk to 24M
993 19:34:23.233513 Set A73 clk to 24M
994 19:34:23.237401 Set clk81 to 24M
995 19:34:23.237938 A53 clk: 1200 MHz
996 19:34:23.238401 A73 clk: 1200 MHz
997 19:34:23.240754 CLK81: 166.6M
998 19:34:23.241259 smccc: 00012abd
999 19:34:23.246311 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1000 19:34:23.251873 board id: 1
1001 19:34:23.256172 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1002 19:34:23.267773 fw parse done
1003 19:34:23.272935 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 19:34:23.315424 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1005 19:34:23.327500 PIEI prepare done
1006 19:34:23.328045 fastboot data load
1007 19:34:23.328482 fastboot data verify
1008 19:34:23.333314 verify result: 266
1009 19:34:23.338705 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1010 19:34:23.339203 LPDDR4 probe
1011 19:34:23.339635 ddr clk to 1584MHz
1012 19:34:23.346628 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1013 19:34:23.383904
1014 19:34:23.384462 dmc_version 0001
1015 19:34:23.390626 Check phy result
1016 19:34:23.396476 INFO : End of CA training
1017 19:34:23.396981 INFO : End of initialization
1018 19:34:23.402257 INFO : Training has run successfully!
1019 19:34:23.402803 Check phy result
1020 19:34:23.407680 INFO : End of initialization
1021 19:34:23.408279 INFO : End of read enable training
1022 19:34:23.413183 INFO : End of fine write leveling
1023 19:34:23.418987 INFO : End of Write leveling coarse delay
1024 19:34:23.419574 INFO : Training has run successfully!
1025 19:34:23.420086 Check phy result
1026 19:34:23.424374 INFO : End of initialization
1027 19:34:23.424889 INFO : End of read dq deskew training
1028 19:34:23.429957 INFO : End of MPR read delay center optimization
1029 19:34:23.435576 INFO : End of write delay center optimization
1030 19:34:23.441147 INFO : End of read delay center optimization
1031 19:34:23.441668 INFO : End of max read latency training
1032 19:34:23.446856 INFO : Training has run successfully!
1033 19:34:23.447380 1D training succeed
1034 19:34:23.455877 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1035 19:34:23.503423 Check phy result
1036 19:34:23.503794 INFO : End of initialization
1037 19:34:23.525251 INFO : End of 2D read delay Voltage center optimization
1038 19:34:23.544552 INFO : End of 2D read delay Voltage center optimization
1039 19:34:23.597530 INFO : End of 2D write delay Voltage center optimization
1040 19:34:23.646959 INFO : End of 2D write delay Voltage center optimization
1041 19:34:23.652525 INFO : Training has run successfully!
1042 19:34:23.653036
1043 19:34:23.653477 channel==0
1044 19:34:23.658125 RxClkDly_Margin_A0==88 ps 9
1045 19:34:23.658629 TxDqDly_Margin_A0==98 ps 10
1046 19:34:23.663742 RxClkDly_Margin_A1==88 ps 9
1047 19:34:23.664297 TxDqDly_Margin_A1==98 ps 10
1048 19:34:23.664740 TrainedVREFDQ_A0==74
1049 19:34:23.669318 TrainedVREFDQ_A1==74
1050 19:34:23.669819 VrefDac_Margin_A0==25
1051 19:34:23.670251 DeviceVref_Margin_A0==40
1052 19:34:23.674911 VrefDac_Margin_A1==25
1053 19:34:23.675417 DeviceVref_Margin_A1==40
1054 19:34:23.675849
1055 19:34:23.676320
1056 19:34:23.680486 channel==1
1057 19:34:23.680989 RxClkDly_Margin_A0==98 ps 10
1058 19:34:23.681420 TxDqDly_Margin_A0==98 ps 10
1059 19:34:23.686125 RxClkDly_Margin_A1==88 ps 9
1060 19:34:23.686627 TxDqDly_Margin_A1==88 ps 9
1061 19:34:23.691713 TrainedVREFDQ_A0==77
1062 19:34:23.692258 TrainedVREFDQ_A1==77
1063 19:34:23.692691 VrefDac_Margin_A0==22
1064 19:34:23.697320 DeviceVref_Margin_A0==37
1065 19:34:23.697824 VrefDac_Margin_A1==24
1066 19:34:23.702926 DeviceVref_Margin_A1==37
1067 19:34:23.703421
1068 19:34:23.703856 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1069 19:34:23.704325
1070 19:34:23.736494 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1071 19:34:23.737070 2D training succeed
1072 19:34:23.742110 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1073 19:34:23.747739 auto size-- 65535DDR cs0 size: 2048MB
1074 19:34:23.748288 DDR cs1 size: 2048MB
1075 19:34:23.753306 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1076 19:34:23.753813 cs0 DataBus test pass
1077 19:34:23.758930 cs1 DataBus test pass
1078 19:34:23.759425 cs0 AddrBus test pass
1079 19:34:23.759858 cs1 AddrBus test pass
1080 19:34:23.760323
1081 19:34:23.764497 100bdlr_step_size ps== 420
1082 19:34:23.765012 result report
1083 19:34:23.770118 boot times 0Enable ddr reg access
1084 19:34:23.775468 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1085 19:34:23.788915 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1086 19:34:24.362133 0.0;M3 CHK:0;cm4_sp_mode 0
1087 19:34:24.362781 MVN_1=0x00000000
1088 19:34:24.367535 MVN_2=0x00000000
1089 19:34:24.373293 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1090 19:34:24.373820 OPS=0x10
1091 19:34:24.374276 ring efuse init
1092 19:34:24.374718 chipver efuse init
1093 19:34:24.378963 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1094 19:34:24.384478 [0.018961 Inits done]
1095 19:34:24.384996 secure task start!
1096 19:34:24.385445 high task start!
1097 19:34:24.389072 low task start!
1098 19:34:24.389576 run into bl31
1099 19:34:24.395800 NOTICE: BL31: v1.3(release):4fc40b1
1100 19:34:24.403579 NOTICE: BL31: Built : 15:58:17, May 22 2019
1101 19:34:24.404155 NOTICE: BL31: G12A normal boot!
1102 19:34:24.429036 NOTICE: BL31: BL33 decompress pass
1103 19:34:24.434609 ERROR: Error initializing runtime service opteed_fast
1104 19:34:25.667570
1105 19:34:25.668293
1106 19:34:25.675886 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1107 19:34:25.676459
1108 19:34:25.676920 Model: Libre Computer AML-A311D-CC Alta
1109 19:34:25.884360 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1110 19:34:25.907697 DRAM: 2 GiB (effective 3.8 GiB)
1111 19:34:26.050704 Core: 408 devices, 31 uclasses, devicetree: separate
1112 19:34:26.056584 WDT: Not starting watchdog@f0d0
1113 19:34:26.088865 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1114 19:34:26.101252 Loading Environment from FAT... Card did not respond to voltage select! : -110
1115 19:34:26.106331 ** Bad device specification mmc 0 **
1116 19:34:26.116683 Card did not respond to voltage select! : -110
1117 19:34:26.124341 ** Bad device specification mmc 0 **
1118 19:34:26.124931 Couldn't find partition mmc 0
1119 19:34:26.132634 Card did not respond to voltage select! : -110
1120 19:34:26.138219 ** Bad device specification mmc 0 **
1121 19:34:26.138788 Couldn't find partition mmc 0
1122 19:34:26.143298 Error: could not access storage.
1123 19:34:26.486694 Net: eth0: ethernet@ff3f0000
1124 19:34:26.487339 starting USB...
1125 19:34:26.738515 Bus usb@ff500000: Register 3000140 NbrPorts 3
1126 19:34:26.739157 Starting the controller
1127 19:34:26.745409 USB XHCI 1.10
1128 19:34:28.299468 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1129 19:34:28.307752 scanning usb for storage devices... 0 Storage Device(s) found
1131 19:34:28.359668 Hit any key to stop autoboot: 1
1132 19:34:28.360631 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1133 19:34:28.361010 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1134 19:34:28.361271 Setting prompt string to ['=>']
1135 19:34:28.361545 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1136 19:34:28.375788 0
1137 19:34:28.376785 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1138 19:34:28.377278 Sending with 10 millisecond of delay
1140 19:34:29.513243 => setenv autoload no
1141 19:34:29.525144 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1142 19:34:29.528542 setenv autoload no
1143 19:34:29.529940 Sending with 10 millisecond of delay
1145 19:34:31.337522 => setenv initrd_high 0xffffffff
1146 19:34:31.348473 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1147 19:34:31.349467 setenv initrd_high 0xffffffff
1148 19:34:31.350296 Sending with 10 millisecond of delay
1150 19:34:32.966890 => setenv fdt_high 0xffffffff
1151 19:34:32.977884 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1152 19:34:32.978882 setenv fdt_high 0xffffffff
1153 19:34:32.979742 Sending with 10 millisecond of delay
1155 19:34:33.271854 => dhcp
1156 19:34:33.282796 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1157 19:34:33.283793 dhcp
1158 19:34:33.284375 Speed: 1000, full duplex
1159 19:34:33.284909 BOOTP broadcast 1
1160 19:34:33.295923 DHCP client bound to address 192.168.6.27 (12 ms)
1161 19:34:33.296791 Sending with 10 millisecond of delay
1163 19:34:34.973479 => setenv serverip 192.168.6.2
1164 19:34:34.984461 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1165 19:34:34.985581 setenv serverip 192.168.6.2
1166 19:34:34.986407 Sending with 10 millisecond of delay
1168 19:34:38.712708 => tftpboot 0x01080000 971984/tftp-deploy-ejjs2azl/kernel/uImage
1169 19:34:38.723498 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1170 19:34:38.724332 tftpboot 0x01080000 971984/tftp-deploy-ejjs2azl/kernel/uImage
1171 19:34:38.724780 Speed: 1000, full duplex
1172 19:34:38.725194 Using ethernet@ff3f0000 device
1173 19:34:38.725910 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1174 19:34:38.731380 Filename '971984/tftp-deploy-ejjs2azl/kernel/uImage'.
1175 19:34:38.735239 Load address: 0x1080000
1176 19:34:41.629785 Loading: *################################################## 43.6 MiB
1177 19:34:41.630373 15 MiB/s
1178 19:34:41.630800 done
1179 19:34:41.633974 Bytes transferred = 45713984 (2b98a40 hex)
1180 19:34:41.634750 Sending with 10 millisecond of delay
1182 19:34:46.321511 => tftpboot 0x08000000 971984/tftp-deploy-ejjs2azl/ramdisk/ramdisk.cpio.gz.uboot
1183 19:34:46.332252 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1184 19:34:46.333054 tftpboot 0x08000000 971984/tftp-deploy-ejjs2azl/ramdisk/ramdisk.cpio.gz.uboot
1185 19:34:46.333486 Speed: 1000, full duplex
1186 19:34:46.333903 Using ethernet@ff3f0000 device
1187 19:34:46.334967 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1188 19:34:46.346676 Filename '971984/tftp-deploy-ejjs2azl/ramdisk/ramdisk.cpio.gz.uboot'.
1189 19:34:46.347188 Load address: 0x8000000
1190 19:34:52.931684 Loading: *#####################T ############################ UDP wrong checksum 00000005 00000e2b
1191 19:34:57.932329 T UDP wrong checksum 00000005 00000e2b
1192 19:35:07.935440 T T UDP wrong checksum 00000005 00000e2b
1193 19:35:09.109518 UDP wrong checksum 000000ff 000070bc
1194 19:35:09.147349 UDP wrong checksum 000000ff 000009af
1195 19:35:11.589579 UDP wrong checksum 000000ff 00000fca
1196 19:35:11.627125 UDP wrong checksum 000000ff 00009abc
1197 19:35:24.930625 T T T UDP wrong checksum 000000ff 0000546a
1198 19:35:25.100628 UDP wrong checksum 000000ff 0000f05c
1199 19:35:27.939345 T UDP wrong checksum 00000005 00000e2b
1200 19:35:42.943461 T T
1201 19:35:42.943871 Retry count exceeded; starting again
1203 19:35:42.944774 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1206 19:35:42.945742 end: 2.4 uboot-commands (duration 00:01:51) [common]
1208 19:35:42.946448 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1210 19:35:42.946957 end: 2 uboot-action (duration 00:01:51) [common]
1212 19:35:42.947769 Cleaning after the job
1213 19:35:42.948113 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/971984/tftp-deploy-ejjs2azl/ramdisk
1214 19:35:42.948917 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/971984/tftp-deploy-ejjs2azl/kernel
1215 19:35:42.974323 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/971984/tftp-deploy-ejjs2azl/dtb
1216 19:35:42.975160 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/971984/tftp-deploy-ejjs2azl/nfsrootfs
1217 19:35:43.152846 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/971984/tftp-deploy-ejjs2azl/modules
1218 19:35:43.177164 start: 4.1 power-off (timeout 00:00:30) [common]
1219 19:35:43.177841 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1220 19:35:43.211478 >> OK - accepted request
1221 19:35:43.213585 Returned 0 in 0 seconds
1222 19:35:43.314356 end: 4.1 power-off (duration 00:00:00) [common]
1224 19:35:43.315364 start: 4.2 read-feedback (timeout 00:10:00) [common]
1225 19:35:43.316151 Listened to connection for namespace 'common' for up to 1s
1226 19:35:44.316945 Finalising connection for namespace 'common'
1227 19:35:44.317413 Disconnecting from shell: Finalise
1228 19:35:44.317707 =>
1229 19:35:44.418430 end: 4.2 read-feedback (duration 00:00:01) [common]
1230 19:35:44.418877 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/971984
1231 19:35:47.386144 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/971984
1232 19:35:47.386804 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.