Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 19:49:12.676150 lava-dispatcher, installed at version: 2024.01
2 19:49:12.676927 start: 0 validate
3 19:49:12.677406 Start time: 2024-11-10 19:49:12.677376+00:00 (UTC)
4 19:49:12.677949 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 19:49:12.678488 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 19:49:12.721599 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 19:49:12.722158 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-318-ga9cda7c0ffed%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 19:49:12.755220 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 19:49:12.755869 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-318-ga9cda7c0ffed%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 19:49:12.789177 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 19:49:12.789715 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:49:12.824257 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 19:49:12.824773 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-318-ga9cda7c0ffed%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 19:49:12.870044 validate duration: 0.19
16 19:49:12.871605 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:49:12.872025 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:49:12.872632 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:49:12.873859 Not decompressing ramdisk as can be used compressed.
20 19:49:12.874698 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 19:49:12.875244 saving as /var/lib/lava/dispatcher/tmp/972027/tftp-deploy-j_b2qfj0/ramdisk/initrd.cpio.gz
22 19:49:12.875938 total size: 5628169 (5 MB)
23 19:49:12.919884 progress 0 % (0 MB)
24 19:49:12.928036 progress 5 % (0 MB)
25 19:49:12.935830 progress 10 % (0 MB)
26 19:49:12.942829 progress 15 % (0 MB)
27 19:49:12.950599 progress 20 % (1 MB)
28 19:49:12.954941 progress 25 % (1 MB)
29 19:49:12.959060 progress 30 % (1 MB)
30 19:49:12.963150 progress 35 % (1 MB)
31 19:49:12.966702 progress 40 % (2 MB)
32 19:49:12.970727 progress 45 % (2 MB)
33 19:49:12.974560 progress 50 % (2 MB)
34 19:49:12.978809 progress 55 % (2 MB)
35 19:49:12.983056 progress 60 % (3 MB)
36 19:49:12.986873 progress 65 % (3 MB)
37 19:49:12.991231 progress 70 % (3 MB)
38 19:49:12.995082 progress 75 % (4 MB)
39 19:49:12.999290 progress 80 % (4 MB)
40 19:49:13.003094 progress 85 % (4 MB)
41 19:49:13.007172 progress 90 % (4 MB)
42 19:49:13.010875 progress 95 % (5 MB)
43 19:49:13.014154 progress 100 % (5 MB)
44 19:49:13.014808 5 MB downloaded in 0.14 s (38.65 MB/s)
45 19:49:13.015348 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:49:13.016262 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:49:13.016561 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:49:13.016832 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:49:13.017301 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-318-ga9cda7c0ffed/arm64/defconfig/gcc-12/kernel/Image
51 19:49:13.017555 saving as /var/lib/lava/dispatcher/tmp/972027/tftp-deploy-j_b2qfj0/kernel/Image
52 19:49:13.017767 total size: 45713920 (43 MB)
53 19:49:13.017977 No compression specified
54 19:49:13.056826 progress 0 % (0 MB)
55 19:49:13.092643 progress 5 % (2 MB)
56 19:49:13.128385 progress 10 % (4 MB)
57 19:49:13.162549 progress 15 % (6 MB)
58 19:49:13.197799 progress 20 % (8 MB)
59 19:49:13.230284 progress 25 % (10 MB)
60 19:49:13.262057 progress 30 % (13 MB)
61 19:49:13.293456 progress 35 % (15 MB)
62 19:49:13.324825 progress 40 % (17 MB)
63 19:49:13.356371 progress 45 % (19 MB)
64 19:49:13.388365 progress 50 % (21 MB)
65 19:49:13.420872 progress 55 % (24 MB)
66 19:49:13.449110 progress 60 % (26 MB)
67 19:49:13.476651 progress 65 % (28 MB)
68 19:49:13.504929 progress 70 % (30 MB)
69 19:49:13.533117 progress 75 % (32 MB)
70 19:49:13.561628 progress 80 % (34 MB)
71 19:49:13.589255 progress 85 % (37 MB)
72 19:49:13.617368 progress 90 % (39 MB)
73 19:49:13.645903 progress 95 % (41 MB)
74 19:49:13.673494 progress 100 % (43 MB)
75 19:49:13.674017 43 MB downloaded in 0.66 s (66.43 MB/s)
76 19:49:13.674484 end: 1.2.1 http-download (duration 00:00:01) [common]
78 19:49:13.675299 end: 1.2 download-retry (duration 00:00:01) [common]
79 19:49:13.675570 start: 1.3 download-retry (timeout 00:09:59) [common]
80 19:49:13.675834 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 19:49:13.676325 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-318-ga9cda7c0ffed/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 19:49:13.676589 saving as /var/lib/lava/dispatcher/tmp/972027/tftp-deploy-j_b2qfj0/dtb/meson-g12b-a311d-libretech-cc.dtb
83 19:49:13.676795 total size: 54703 (0 MB)
84 19:49:13.677002 No compression specified
85 19:49:13.720846 progress 59 % (0 MB)
86 19:49:13.721690 progress 100 % (0 MB)
87 19:49:13.722227 0 MB downloaded in 0.05 s (1.15 MB/s)
88 19:49:13.722699 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:49:13.723502 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:49:13.723759 start: 1.4 download-retry (timeout 00:09:59) [common]
92 19:49:13.724043 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 19:49:13.724508 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 19:49:13.724754 saving as /var/lib/lava/dispatcher/tmp/972027/tftp-deploy-j_b2qfj0/nfsrootfs/full.rootfs.tar
95 19:49:13.724960 total size: 120894716 (115 MB)
96 19:49:13.725167 Using unxz to decompress xz
97 19:49:13.764900 progress 0 % (0 MB)
98 19:49:14.561167 progress 5 % (5 MB)
99 19:49:15.406420 progress 10 % (11 MB)
100 19:49:16.202309 progress 15 % (17 MB)
101 19:49:16.954129 progress 20 % (23 MB)
102 19:49:17.561895 progress 25 % (28 MB)
103 19:49:18.399332 progress 30 % (34 MB)
104 19:49:19.225111 progress 35 % (40 MB)
105 19:49:19.583910 progress 40 % (46 MB)
106 19:49:19.956591 progress 45 % (51 MB)
107 19:49:20.693874 progress 50 % (57 MB)
108 19:49:21.593813 progress 55 % (63 MB)
109 19:49:22.381357 progress 60 % (69 MB)
110 19:49:23.145594 progress 65 % (74 MB)
111 19:49:23.934081 progress 70 % (80 MB)
112 19:49:24.766629 progress 75 % (86 MB)
113 19:49:25.564396 progress 80 % (92 MB)
114 19:49:26.339267 progress 85 % (98 MB)
115 19:49:27.211465 progress 90 % (103 MB)
116 19:49:28.001277 progress 95 % (109 MB)
117 19:49:28.834123 progress 100 % (115 MB)
118 19:49:28.847490 115 MB downloaded in 15.12 s (7.62 MB/s)
119 19:49:28.848470 end: 1.4.1 http-download (duration 00:00:15) [common]
121 19:49:28.850249 end: 1.4 download-retry (duration 00:00:15) [common]
122 19:49:28.850833 start: 1.5 download-retry (timeout 00:09:44) [common]
123 19:49:28.851406 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 19:49:28.852377 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-318-ga9cda7c0ffed/arm64/defconfig/gcc-12/modules.tar.xz
125 19:49:28.852898 saving as /var/lib/lava/dispatcher/tmp/972027/tftp-deploy-j_b2qfj0/modules/modules.tar
126 19:49:28.853357 total size: 11611460 (11 MB)
127 19:49:28.853827 Using unxz to decompress xz
128 19:49:28.895003 progress 0 % (0 MB)
129 19:49:28.963105 progress 5 % (0 MB)
130 19:49:29.038924 progress 10 % (1 MB)
131 19:49:29.137682 progress 15 % (1 MB)
132 19:49:29.230725 progress 20 % (2 MB)
133 19:49:29.313270 progress 25 % (2 MB)
134 19:49:29.389199 progress 30 % (3 MB)
135 19:49:29.467974 progress 35 % (3 MB)
136 19:49:29.540880 progress 40 % (4 MB)
137 19:49:29.617247 progress 45 % (5 MB)
138 19:49:29.701363 progress 50 % (5 MB)
139 19:49:29.778061 progress 55 % (6 MB)
140 19:49:29.862669 progress 60 % (6 MB)
141 19:49:29.943349 progress 65 % (7 MB)
142 19:49:30.027245 progress 70 % (7 MB)
143 19:49:30.105790 progress 75 % (8 MB)
144 19:49:30.189207 progress 80 % (8 MB)
145 19:49:30.268866 progress 85 % (9 MB)
146 19:49:30.347266 progress 90 % (9 MB)
147 19:49:30.424972 progress 95 % (10 MB)
148 19:49:30.501965 progress 100 % (11 MB)
149 19:49:30.514390 11 MB downloaded in 1.66 s (6.67 MB/s)
150 19:49:30.515264 end: 1.5.1 http-download (duration 00:00:02) [common]
152 19:49:30.516940 end: 1.5 download-retry (duration 00:00:02) [common]
153 19:49:30.517460 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 19:49:30.517974 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 19:49:47.885598 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/972027/extract-nfsrootfs-d1utwvpn
156 19:49:47.886209 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 19:49:47.886496 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 19:49:47.887198 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10
159 19:49:47.887643 makedir: /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin
160 19:49:47.887966 makedir: /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/tests
161 19:49:47.888345 makedir: /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/results
162 19:49:47.888681 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-add-keys
163 19:49:47.889209 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-add-sources
164 19:49:47.889709 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-background-process-start
165 19:49:47.890201 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-background-process-stop
166 19:49:47.890877 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-common-functions
167 19:49:47.891429 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-echo-ipv4
168 19:49:47.891923 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-install-packages
169 19:49:47.892453 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-installed-packages
170 19:49:47.892943 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-os-build
171 19:49:47.893419 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-probe-channel
172 19:49:47.893900 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-probe-ip
173 19:49:47.894376 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-target-ip
174 19:49:47.894888 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-target-mac
175 19:49:47.895397 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-target-storage
176 19:49:47.895884 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-test-case
177 19:49:47.896403 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-test-event
178 19:49:47.896876 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-test-feedback
179 19:49:47.897348 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-test-raise
180 19:49:47.897817 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-test-reference
181 19:49:47.898286 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-test-runner
182 19:49:47.898791 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-test-set
183 19:49:47.899290 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-test-shell
184 19:49:47.899774 Updating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-add-keys (debian)
185 19:49:47.900337 Updating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-add-sources (debian)
186 19:49:47.900845 Updating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-install-packages (debian)
187 19:49:47.901339 Updating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-installed-packages (debian)
188 19:49:47.901830 Updating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/bin/lava-os-build (debian)
189 19:49:47.902321 Creating /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/environment
190 19:49:47.902704 LAVA metadata
191 19:49:47.902966 - LAVA_JOB_ID=972027
192 19:49:47.903180 - LAVA_DISPATCHER_IP=192.168.6.2
193 19:49:47.903545 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 19:49:47.904513 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 19:49:47.904827 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 19:49:47.905033 skipped lava-vland-overlay
197 19:49:47.905271 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 19:49:47.905520 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 19:49:47.905736 skipped lava-multinode-overlay
200 19:49:47.905976 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 19:49:47.906224 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 19:49:47.906468 Loading test definitions
203 19:49:47.906739 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 19:49:47.906955 Using /lava-972027 at stage 0
205 19:49:47.908060 uuid=972027_1.6.2.4.1 testdef=None
206 19:49:47.908372 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 19:49:47.908635 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 19:49:47.910206 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 19:49:47.910991 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 19:49:47.912966 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 19:49:47.913808 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 19:49:47.915656 runner path: /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/0/tests/0_timesync-off test_uuid 972027_1.6.2.4.1
215 19:49:47.916299 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 19:49:47.917124 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 19:49:47.917346 Using /lava-972027 at stage 0
219 19:49:47.917709 Fetching tests from https://github.com/kernelci/test-definitions.git
220 19:49:47.918003 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/0/tests/1_kselftest-rtc'
221 19:49:51.247252 Running '/usr/bin/git checkout kernelci.org
222 19:49:51.483087 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
223 19:49:51.486343 uuid=972027_1.6.2.4.5 testdef=None
224 19:49:51.487213 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 19:49:51.489403 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 19:49:51.497167 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 19:49:51.499404 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 19:49:51.510117 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 19:49:51.512626 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 19:49:51.522808 runner path: /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/0/tests/1_kselftest-rtc test_uuid 972027_1.6.2.4.5
234 19:49:51.523547 BOARD='meson-g12b-a311d-libretech-cc'
235 19:49:51.524242 BRANCH='mainline'
236 19:49:51.524851 SKIPFILE='/dev/null'
237 19:49:51.525425 SKIP_INSTALL='True'
238 19:49:51.525998 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-318-ga9cda7c0ffed/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 19:49:51.526580 TST_CASENAME=''
240 19:49:51.527218 TST_CMDFILES='rtc'
241 19:49:51.528822 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 19:49:51.531110 Creating lava-test-runner.conf files
244 19:49:51.531703 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/972027/lava-overlay-c8hiqp10/lava-972027/0 for stage 0
245 19:49:51.532745 - 0_timesync-off
246 19:49:51.533366 - 1_kselftest-rtc
247 19:49:51.534239 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 19:49:51.534978 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 19:50:16.378193 end: 1.6.2.5 compress-overlay (duration 00:00:25) [common]
250 19:50:16.378731 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:56) [common]
251 19:50:16.379053 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 19:50:16.379384 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 19:50:16.379707 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:56) [common]
254 19:50:17.010041 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 19:50:17.010517 start: 1.6.4 extract-modules (timeout 00:08:56) [common]
256 19:50:17.010768 extracting modules file /var/lib/lava/dispatcher/tmp/972027/tftp-deploy-j_b2qfj0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/972027/extract-nfsrootfs-d1utwvpn
257 19:50:18.369310 extracting modules file /var/lib/lava/dispatcher/tmp/972027/tftp-deploy-j_b2qfj0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/972027/extract-overlay-ramdisk-ycjdxcal/ramdisk
258 19:50:19.803353 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 19:50:19.803833 start: 1.6.5 apply-overlay-tftp (timeout 00:08:53) [common]
260 19:50:19.804143 [common] Applying overlay to NFS
261 19:50:19.804361 [common] Applying overlay /var/lib/lava/dispatcher/tmp/972027/compress-overlay-hicc8o_e/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/972027/extract-nfsrootfs-d1utwvpn
262 19:50:22.597199 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 19:50:22.597699 start: 1.6.6 prepare-kernel (timeout 00:08:50) [common]
264 19:50:22.597972 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:50) [common]
265 19:50:22.598204 Converting downloaded kernel to a uImage
266 19:50:22.598549 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/972027/tftp-deploy-j_b2qfj0/kernel/Image /var/lib/lava/dispatcher/tmp/972027/tftp-deploy-j_b2qfj0/kernel/uImage
267 19:50:23.071689 output: Image Name:
268 19:50:23.072121 output: Created: Sun Nov 10 19:50:22 2024
269 19:50:23.072352 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 19:50:23.072568 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 19:50:23.072779 output: Load Address: 01080000
272 19:50:23.072985 output: Entry Point: 01080000
273 19:50:23.073187 output:
274 19:50:23.073526 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 19:50:23.073801 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 19:50:23.074079 start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
277 19:50:23.074340 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 19:50:23.074608 start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
279 19:50:23.074869 Building ramdisk /var/lib/lava/dispatcher/tmp/972027/extract-overlay-ramdisk-ycjdxcal/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/972027/extract-overlay-ramdisk-ycjdxcal/ramdisk
280 19:50:25.282014 >> 166829 blocks
281 19:50:33.394425 Adding RAMdisk u-boot header.
282 19:50:33.395113 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/972027/extract-overlay-ramdisk-ycjdxcal/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/972027/extract-overlay-ramdisk-ycjdxcal/ramdisk.cpio.gz.uboot
283 19:50:33.640475 output: Image Name:
284 19:50:33.641090 output: Created: Sun Nov 10 19:50:33 2024
285 19:50:33.641519 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 19:50:33.641939 output: Data Size: 23435549 Bytes = 22886.28 KiB = 22.35 MiB
287 19:50:33.642352 output: Load Address: 00000000
288 19:50:33.642767 output: Entry Point: 00000000
289 19:50:33.643173 output:
290 19:50:33.644395 rename /var/lib/lava/dispatcher/tmp/972027/extract-overlay-ramdisk-ycjdxcal/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/972027/tftp-deploy-j_b2qfj0/ramdisk/ramdisk.cpio.gz.uboot
291 19:50:33.645134 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 19:50:33.645687 end: 1.6 prepare-tftp-overlay (duration 00:01:03) [common]
293 19:50:33.646230 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:39) [common]
294 19:50:33.646710 No LXC device requested
295 19:50:33.647297 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 19:50:33.647856 start: 1.8 deploy-device-env (timeout 00:08:39) [common]
297 19:50:33.648433 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 19:50:33.648883 Checking files for TFTP limit of 4294967296 bytes.
299 19:50:33.651644 end: 1 tftp-deploy (duration 00:01:21) [common]
300 19:50:33.652362 start: 2 uboot-action (timeout 00:05:00) [common]
301 19:50:33.652980 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 19:50:33.653557 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 19:50:33.654156 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 19:50:33.654748 Using kernel file from prepare-kernel: 972027/tftp-deploy-j_b2qfj0/kernel/uImage
305 19:50:33.655439 substitutions:
306 19:50:33.655900 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 19:50:33.656394 - {DTB_ADDR}: 0x01070000
308 19:50:33.656830 - {DTB}: 972027/tftp-deploy-j_b2qfj0/dtb/meson-g12b-a311d-libretech-cc.dtb
309 19:50:33.657256 - {INITRD}: 972027/tftp-deploy-j_b2qfj0/ramdisk/ramdisk.cpio.gz.uboot
310 19:50:33.657669 - {KERNEL_ADDR}: 0x01080000
311 19:50:33.658083 - {KERNEL}: 972027/tftp-deploy-j_b2qfj0/kernel/uImage
312 19:50:33.658496 - {LAVA_MAC}: None
313 19:50:33.658954 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/972027/extract-nfsrootfs-d1utwvpn
314 19:50:33.659384 - {NFS_SERVER_IP}: 192.168.6.2
315 19:50:33.659864 - {PRESEED_CONFIG}: None
316 19:50:33.660337 - {PRESEED_LOCAL}: None
317 19:50:33.660753 - {RAMDISK_ADDR}: 0x08000000
318 19:50:33.661171 - {RAMDISK}: 972027/tftp-deploy-j_b2qfj0/ramdisk/ramdisk.cpio.gz.uboot
319 19:50:33.661576 - {ROOT_PART}: None
320 19:50:33.661993 - {ROOT}: None
321 19:50:33.662390 - {SERVER_IP}: 192.168.6.2
322 19:50:33.662801 - {TEE_ADDR}: 0x83000000
323 19:50:33.663196 - {TEE}: None
324 19:50:33.663599 Parsed boot commands:
325 19:50:33.664011 - setenv autoload no
326 19:50:33.664430 - setenv initrd_high 0xffffffff
327 19:50:33.664827 - setenv fdt_high 0xffffffff
328 19:50:33.665239 - dhcp
329 19:50:33.665639 - setenv serverip 192.168.6.2
330 19:50:33.666032 - tftpboot 0x01080000 972027/tftp-deploy-j_b2qfj0/kernel/uImage
331 19:50:33.666421 - tftpboot 0x08000000 972027/tftp-deploy-j_b2qfj0/ramdisk/ramdisk.cpio.gz.uboot
332 19:50:33.666809 - tftpboot 0x01070000 972027/tftp-deploy-j_b2qfj0/dtb/meson-g12b-a311d-libretech-cc.dtb
333 19:50:33.667197 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/972027/extract-nfsrootfs-d1utwvpn,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 19:50:33.667598 - bootm 0x01080000 0x08000000 0x01070000
335 19:50:33.668153 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 19:50:33.669704 start: 2.3 connect-device (timeout 00:05:00) [common]
338 19:50:33.670151 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 19:50:33.685551 Setting prompt string to ['lava-test: # ']
340 19:50:33.687086 end: 2.3 connect-device (duration 00:00:00) [common]
341 19:50:33.687759 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 19:50:33.688460 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 19:50:33.689102 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 19:50:33.690383 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 19:50:33.730905 >> OK - accepted request
346 19:50:33.733198 Returned 0 in 0 seconds
347 19:50:33.834317 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 19:50:33.836250 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 19:50:33.836885 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 19:50:33.837465 Setting prompt string to ['Hit any key to stop autoboot']
352 19:50:33.837983 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 19:50:33.839732 Trying 192.168.56.21...
354 19:50:33.840310 Connected to conserv1.
355 19:50:33.840730 Escape character is '^]'.
356 19:50:33.841217
357 19:50:33.841697 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 19:50:33.842194
359 19:50:44.643738 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 19:50:44.644482 bl2_stage_init 0x01
361 19:50:44.644968 bl2_stage_init 0x81
362 19:50:44.649319 hw id: 0x0000 - pwm id 0x01
363 19:50:44.649822 bl2_stage_init 0xc1
364 19:50:44.650333 bl2_stage_init 0x02
365 19:50:44.650767
366 19:50:44.654930 L0:00000000
367 19:50:44.655442 L1:20000703
368 19:50:44.655911 L2:00008067
369 19:50:44.656405 L3:14000000
370 19:50:44.660430 B2:00402000
371 19:50:44.660892 B1:e0f83180
372 19:50:44.661364
373 19:50:44.661808 TE: 58159
374 19:50:44.662210
375 19:50:44.666070 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 19:50:44.666603
377 19:50:44.667063 Board ID = 1
378 19:50:44.671692 Set A53 clk to 24M
379 19:50:44.672212 Set A73 clk to 24M
380 19:50:44.672702 Set clk81 to 24M
381 19:50:44.677344 A53 clk: 1200 MHz
382 19:50:44.677846 A73 clk: 1200 MHz
383 19:50:44.678296 CLK81: 166.6M
384 19:50:44.678733 smccc: 00012ab5
385 19:50:44.682883 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 19:50:44.688487 board id: 1
387 19:50:44.693397 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 19:50:44.705033 fw parse done
389 19:50:44.710956 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 19:50:44.753663 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 19:50:44.764534 PIEI prepare done
392 19:50:44.765048 fastboot data load
393 19:50:44.765451 fastboot data verify
394 19:50:44.770154 verify result: 266
395 19:50:44.775773 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 19:50:44.776318 LPDDR4 probe
397 19:50:44.776775 ddr clk to 1584MHz
398 19:50:44.783786 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 19:50:44.820361
400 19:50:44.820870 dmc_version 0001
401 19:50:44.827652 Check phy result
402 19:50:44.833546 INFO : End of CA training
403 19:50:44.834036 INFO : End of initialization
404 19:50:44.839124 INFO : Training has run successfully!
405 19:50:44.839610 Check phy result
406 19:50:44.844788 INFO : End of initialization
407 19:50:44.845268 INFO : End of read enable training
408 19:50:44.848061 INFO : End of fine write leveling
409 19:50:44.853545 INFO : End of Write leveling coarse delay
410 19:50:44.859220 INFO : Training has run successfully!
411 19:50:44.859689 Check phy result
412 19:50:44.860182 INFO : End of initialization
413 19:50:44.864807 INFO : End of read dq deskew training
414 19:50:44.868202 INFO : End of MPR read delay center optimization
415 19:50:44.873759 INFO : End of write delay center optimization
416 19:50:44.879354 INFO : End of read delay center optimization
417 19:50:44.879876 INFO : End of max read latency training
418 19:50:44.884949 INFO : Training has run successfully!
419 19:50:44.885432 1D training succeed
420 19:50:44.893147 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 19:50:44.940726 Check phy result
422 19:50:44.941269 INFO : End of initialization
423 19:50:44.963256 INFO : End of 2D read delay Voltage center optimization
424 19:50:44.982387 INFO : End of 2D read delay Voltage center optimization
425 19:50:45.034368 INFO : End of 2D write delay Voltage center optimization
426 19:50:45.084483 INFO : End of 2D write delay Voltage center optimization
427 19:50:45.090079 INFO : Training has run successfully!
428 19:50:45.090577
429 19:50:45.091044 channel==0
430 19:50:45.095641 RxClkDly_Margin_A0==88 ps 9
431 19:50:45.096212 TxDqDly_Margin_A0==98 ps 10
432 19:50:45.098974 RxClkDly_Margin_A1==88 ps 9
433 19:50:45.099445 TxDqDly_Margin_A1==98 ps 10
434 19:50:45.104389 TrainedVREFDQ_A0==74
435 19:50:45.104876 TrainedVREFDQ_A1==74
436 19:50:45.109998 VrefDac_Margin_A0==24
437 19:50:45.110482 DeviceVref_Margin_A0==40
438 19:50:45.110971 VrefDac_Margin_A1==26
439 19:50:45.115563 DeviceVref_Margin_A1==40
440 19:50:45.116069
441 19:50:45.116476
442 19:50:45.116935 channel==1
443 19:50:45.117380 RxClkDly_Margin_A0==98 ps 10
444 19:50:45.121152 TxDqDly_Margin_A0==88 ps 9
445 19:50:45.121641 RxClkDly_Margin_A1==88 ps 9
446 19:50:45.126758 TxDqDly_Margin_A1==88 ps 9
447 19:50:45.127251 TrainedVREFDQ_A0==76
448 19:50:45.127701 TrainedVREFDQ_A1==77
449 19:50:45.132388 VrefDac_Margin_A0==22
450 19:50:45.132876 DeviceVref_Margin_A0==38
451 19:50:45.138043 VrefDac_Margin_A1==24
452 19:50:45.138567 DeviceVref_Margin_A1==37
453 19:50:45.138974
454 19:50:45.143640 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 19:50:45.144166
456 19:50:45.171557 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000016 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 19:50:45.177223 2D training succeed
458 19:50:45.182866 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 19:50:45.183598 auto size-- 65535DDR cs0 size: 2048MB
460 19:50:45.188434 DDR cs1 size: 2048MB
461 19:50:45.189183 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 19:50:45.194007 cs0 DataBus test pass
463 19:50:45.194829 cs1 DataBus test pass
464 19:50:45.195449 cs0 AddrBus test pass
465 19:50:45.199596 cs1 AddrBus test pass
466 19:50:45.200346
467 19:50:45.200991 100bdlr_step_size ps== 420
468 19:50:45.201712 result report
469 19:50:45.205186 boot times 0Enable ddr reg access
470 19:50:45.211932 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 19:50:45.225435 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 19:50:45.798449 0.0;M3 CHK:0;cm4_sp_mode 0
473 19:50:45.799537 MVN_1=0x00000000
474 19:50:45.803811 MVN_2=0x00000000
475 19:50:45.809615 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 19:50:45.810387 OPS=0x10
477 19:50:45.811077 ring efuse init
478 19:50:45.811694 chipver efuse init
479 19:50:45.815191 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 19:50:45.820801 [0.018960 Inits done]
481 19:50:45.821519 secure task start!
482 19:50:45.822209 high task start!
483 19:50:45.825390 low task start!
484 19:50:45.826233 run into bl31
485 19:50:45.832132 NOTICE: BL31: v1.3(release):4fc40b1
486 19:50:45.839886 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 19:50:45.840655 NOTICE: BL31: G12A normal boot!
488 19:50:45.865267 NOTICE: BL31: BL33 decompress pass
489 19:50:45.870873 ERROR: Error initializing runtime service opteed_fast
490 19:50:47.103821
491 19:50:47.104864
492 19:50:47.112231 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 19:50:47.112977
494 19:50:47.113633 Model: Libre Computer AML-A311D-CC Alta
495 19:50:47.319705 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 19:50:47.344076 DRAM: 2 GiB (effective 3.8 GiB)
497 19:50:47.486902 Core: 408 devices, 31 uclasses, devicetree: separate
498 19:50:47.492813 WDT: Not starting watchdog@f0d0
499 19:50:47.525089 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 19:50:47.537601 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 19:50:47.542502 ** Bad device specification mmc 0 **
502 19:50:47.552837 Card did not respond to voltage select! : -110
503 19:50:47.560502 ** Bad device specification mmc 0 **
504 19:50:47.560850 Couldn't find partition mmc 0
505 19:50:47.568831 Card did not respond to voltage select! : -110
506 19:50:47.574802 ** Bad device specification mmc 0 **
507 19:50:47.575252 Couldn't find partition mmc 0
508 19:50:47.578682 Error: could not access storage.
509 19:50:48.844487 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 19:50:48.844897 bl2_stage_init 0x01
511 19:50:48.845120 bl2_stage_init 0x81
512 19:50:48.849920 hw id: 0x0000 - pwm id 0x01
513 19:50:48.850211 bl2_stage_init 0xc1
514 19:50:48.850437 bl2_stage_init 0x02
515 19:50:48.850648
516 19:50:48.855539 L0:00000000
517 19:50:48.855822 L1:20000703
518 19:50:48.856077 L2:00008067
519 19:50:48.856294 L3:14000000
520 19:50:48.858409 B2:00402000
521 19:50:48.858678 B1:e0f83180
522 19:50:48.858887
523 19:50:48.859094 TE: 58167
524 19:50:48.859298
525 19:50:48.869599 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 19:50:48.869910
527 19:50:48.870125 Board ID = 1
528 19:50:48.870327 Set A53 clk to 24M
529 19:50:48.870530 Set A73 clk to 24M
530 19:50:48.875213 Set clk81 to 24M
531 19:50:48.875502 A53 clk: 1200 MHz
532 19:50:48.875718 A73 clk: 1200 MHz
533 19:50:48.880801 CLK81: 166.6M
534 19:50:48.881087 smccc: 00012abd
535 19:50:48.886396 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 19:50:48.886686 board id: 1
537 19:50:48.895015 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 19:50:48.905678 fw parse done
539 19:50:48.910701 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 19:50:48.954312 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 19:50:48.965180 PIEI prepare done
542 19:50:48.965495 fastboot data load
543 19:50:48.965712 fastboot data verify
544 19:50:48.970844 verify result: 266
545 19:50:48.976508 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 19:50:48.976801 LPDDR4 probe
547 19:50:48.977013 ddr clk to 1584MHz
548 19:50:48.984410 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 19:50:49.021682
550 19:50:49.022059 dmc_version 0001
551 19:50:49.028340 Check phy result
552 19:50:49.034242 INFO : End of CA training
553 19:50:49.034561 INFO : End of initialization
554 19:50:49.039793 INFO : Training has run successfully!
555 19:50:49.040127 Check phy result
556 19:50:49.045496 INFO : End of initialization
557 19:50:49.045790 INFO : End of read enable training
558 19:50:49.050993 INFO : End of fine write leveling
559 19:50:49.056617 INFO : End of Write leveling coarse delay
560 19:50:49.056919 INFO : Training has run successfully!
561 19:50:49.057129 Check phy result
562 19:50:49.062297 INFO : End of initialization
563 19:50:49.062592 INFO : End of read dq deskew training
564 19:50:49.067895 INFO : End of MPR read delay center optimization
565 19:50:49.073616 INFO : End of write delay center optimization
566 19:50:49.079072 INFO : End of read delay center optimization
567 19:50:49.079536 INFO : End of max read latency training
568 19:50:49.084696 INFO : Training has run successfully!
569 19:50:49.084995 1D training succeed
570 19:50:49.093829 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 19:50:49.141454 Check phy result
572 19:50:49.141836 INFO : End of initialization
573 19:50:49.163950 INFO : End of 2D read delay Voltage center optimization
574 19:50:49.184214 INFO : End of 2D read delay Voltage center optimization
575 19:50:49.236312 INFO : End of 2D write delay Voltage center optimization
576 19:50:49.285693 INFO : End of 2D write delay Voltage center optimization
577 19:50:49.291268 INFO : Training has run successfully!
578 19:50:49.291751
579 19:50:49.292208 channel==0
580 19:50:49.296909 RxClkDly_Margin_A0==88 ps 9
581 19:50:49.297360 TxDqDly_Margin_A0==98 ps 10
582 19:50:49.302628 RxClkDly_Margin_A1==88 ps 9
583 19:50:49.303079 TxDqDly_Margin_A1==98 ps 10
584 19:50:49.303476 TrainedVREFDQ_A0==74
585 19:50:49.308114 TrainedVREFDQ_A1==74
586 19:50:49.308588 VrefDac_Margin_A0==25
587 19:50:49.308980 DeviceVref_Margin_A0==40
588 19:50:49.313672 VrefDac_Margin_A1==25
589 19:50:49.314126 DeviceVref_Margin_A1==40
590 19:50:49.314516
591 19:50:49.314909
592 19:50:49.319260 channel==1
593 19:50:49.319725 RxClkDly_Margin_A0==98 ps 10
594 19:50:49.320155 TxDqDly_Margin_A0==98 ps 10
595 19:50:49.324875 RxClkDly_Margin_A1==88 ps 9
596 19:50:49.325344 TxDqDly_Margin_A1==88 ps 9
597 19:50:49.330430 TrainedVREFDQ_A0==77
598 19:50:49.330729 TrainedVREFDQ_A1==77
599 19:50:49.330974 VrefDac_Margin_A0==22
600 19:50:49.336091 DeviceVref_Margin_A0==37
601 19:50:49.336439 VrefDac_Margin_A1==24
602 19:50:49.341754 DeviceVref_Margin_A1==37
603 19:50:49.342161
604 19:50:49.342452 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 19:50:49.342738
606 19:50:49.375328 soc_vref_reg_value 0x 00000019 00000019 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 19:50:49.375791 2D training succeed
608 19:50:49.380953 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 19:50:49.387028 auto size-- 65535DDR cs0 size: 2048MB
610 19:50:49.387451 DDR cs1 size: 2048MB
611 19:50:49.392285 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 19:50:49.392872 cs0 DataBus test pass
613 19:50:49.397704 cs1 DataBus test pass
614 19:50:49.398279 cs0 AddrBus test pass
615 19:50:49.398732 cs1 AddrBus test pass
616 19:50:49.399173
617 19:50:49.403381 100bdlr_step_size ps== 420
618 19:50:49.403896 result report
619 19:50:49.409011 boot times 0Enable ddr reg access
620 19:50:49.414392 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 19:50:49.427879 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 19:50:50.001485 0.0;M3 CHK:0;cm4_sp_mode 0
623 19:50:50.002154 MVN_1=0x00000000
624 19:50:50.006997 MVN_2=0x00000000
625 19:50:50.012739 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 19:50:50.013225 OPS=0x10
627 19:50:50.013673 ring efuse init
628 19:50:50.014103 chipver efuse init
629 19:50:50.021054 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 19:50:50.021595 [0.018960 Inits done]
631 19:50:50.028772 secure task start!
632 19:50:50.029269 high task start!
633 19:50:50.029673 low task start!
634 19:50:50.030061 run into bl31
635 19:50:50.035249 NOTICE: BL31: v1.3(release):4fc40b1
636 19:50:50.043102 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 19:50:50.043600 NOTICE: BL31: G12A normal boot!
638 19:50:50.068346 NOTICE: BL31: BL33 decompress pass
639 19:50:50.074136 ERROR: Error initializing runtime service opteed_fast
640 19:50:51.306974
641 19:50:51.307588
642 19:50:51.315381 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 19:50:51.315888
644 19:50:51.316363 Model: Libre Computer AML-A311D-CC Alta
645 19:50:51.774401 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 19:50:51.775023 DRAM: 2 GiB (effective 3.8 GiB)
647 19:50:51.775468 Core: 408 devices, 31 uclasses, devicetree: separate
648 19:50:51.775881 WDT: Not starting watchdog@f0d0
649 19:50:51.776727 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 19:50:51.777209 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 19:50:51.777636 ** Bad device specification mmc 0 **
652 19:50:51.778048 Card did not respond to voltage select! : -110
653 19:50:51.778451 ** Bad device specification mmc 0 **
654 19:50:51.778853 Couldn't find partition mmc 0
655 19:50:51.779251 Card did not respond to voltage select! : -110
656 19:50:51.779737 ** Bad device specification mmc 0 **
657 19:50:51.780197 Couldn't find partition mmc 0
658 19:50:51.782647 Error: could not access storage.
659 19:50:52.125181 Net: eth0: ethernet@ff3f0000
660 19:50:52.125801 starting USB...
661 19:50:52.376975 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 19:50:52.377576 Starting the controller
663 19:50:52.384015 USB XHCI 1.10
664 19:50:54.093293 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 19:50:54.093948 bl2_stage_init 0x01
666 19:50:54.094386 bl2_stage_init 0x81
667 19:50:54.098685 hw id: 0x0000 - pwm id 0x01
668 19:50:54.099178 bl2_stage_init 0xc1
669 19:50:54.099592 bl2_stage_init 0x02
670 19:50:54.100040
671 19:50:54.104391 L0:00000000
672 19:50:54.104872 L1:20000703
673 19:50:54.105284 L2:00008067
674 19:50:54.105683 L3:14000000
675 19:50:54.109949 B2:00402000
676 19:50:54.110428 B1:e0f83180
677 19:50:54.110842
678 19:50:54.111243 TE: 58124
679 19:50:54.111641
680 19:50:54.115492 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 19:50:54.115969
682 19:50:54.116415 Board ID = 1
683 19:50:54.121071 Set A53 clk to 24M
684 19:50:54.121544 Set A73 clk to 24M
685 19:50:54.121950 Set clk81 to 24M
686 19:50:54.126649 A53 clk: 1200 MHz
687 19:50:54.127152 A73 clk: 1200 MHz
688 19:50:54.127566 CLK81: 166.6M
689 19:50:54.127971 smccc: 00012a92
690 19:50:54.132307 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 19:50:54.137869 board id: 1
692 19:50:54.143821 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 19:50:54.154469 fw parse done
694 19:50:54.160450 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 19:50:54.203021 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 19:50:54.213920 PIEI prepare done
697 19:50:54.214428 fastboot data load
698 19:50:54.214851 fastboot data verify
699 19:50:54.219564 verify result: 266
700 19:50:54.225108 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 19:50:54.225581 LPDDR4 probe
702 19:50:54.225992 ddr clk to 1584MHz
703 19:50:54.233095 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 19:50:54.270398
705 19:50:54.270896 dmc_version 0001
706 19:50:54.277097 Check phy result
707 19:50:54.282881 INFO : End of CA training
708 19:50:54.283347 INFO : End of initialization
709 19:50:54.288527 INFO : Training has run successfully!
710 19:50:54.288995 Check phy result
711 19:50:54.294103 INFO : End of initialization
712 19:50:54.294567 INFO : End of read enable training
713 19:50:54.297389 INFO : End of fine write leveling
714 19:50:54.302909 INFO : End of Write leveling coarse delay
715 19:50:54.308582 INFO : Training has run successfully!
716 19:50:54.309043 Check phy result
717 19:50:54.309454 INFO : End of initialization
718 19:50:54.314097 INFO : End of read dq deskew training
719 19:50:54.319713 INFO : End of MPR read delay center optimization
720 19:50:54.320221 INFO : End of write delay center optimization
721 19:50:54.325302 INFO : End of read delay center optimization
722 19:50:54.330910 INFO : End of max read latency training
723 19:50:54.331374 INFO : Training has run successfully!
724 19:50:54.336497 1D training succeed
725 19:50:54.342484 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 19:50:54.390124 Check phy result
727 19:50:54.390660 INFO : End of initialization
728 19:50:54.412796 INFO : End of 2D read delay Voltage center optimization
729 19:50:54.433163 INFO : End of 2D read delay Voltage center optimization
730 19:50:54.485118 INFO : End of 2D write delay Voltage center optimization
731 19:50:54.534378 INFO : End of 2D write delay Voltage center optimization
732 19:50:54.539871 INFO : Training has run successfully!
733 19:50:54.540608
734 19:50:54.541163 channel==0
735 19:50:54.545560 RxClkDly_Margin_A0==88 ps 9
736 19:50:54.546228 TxDqDly_Margin_A0==98 ps 10
737 19:50:54.550985 RxClkDly_Margin_A1==88 ps 9
738 19:50:54.551519 TxDqDly_Margin_A1==98 ps 10
739 19:50:54.552005 TrainedVREFDQ_A0==74
740 19:50:54.556660 TrainedVREFDQ_A1==74
741 19:50:54.557165 VrefDac_Margin_A0==24
742 19:50:54.557588 DeviceVref_Margin_A0==40
743 19:50:54.562229 VrefDac_Margin_A1==25
744 19:50:54.562721 DeviceVref_Margin_A1==40
745 19:50:54.563155
746 19:50:54.563598
747 19:50:54.567818 channel==1
748 19:50:54.568332 RxClkDly_Margin_A0==98 ps 10
749 19:50:54.568782 TxDqDly_Margin_A0==98 ps 10
750 19:50:54.573499 RxClkDly_Margin_A1==98 ps 10
751 19:50:54.574014 TxDqDly_Margin_A1==88 ps 9
752 19:50:54.579088 TrainedVREFDQ_A0==77
753 19:50:54.579602 TrainedVREFDQ_A1==77
754 19:50:54.580105 VrefDac_Margin_A0==22
755 19:50:54.584670 DeviceVref_Margin_A0==37
756 19:50:54.585162 VrefDac_Margin_A1==22
757 19:50:54.590272 DeviceVref_Margin_A1==37
758 19:50:54.590762
759 19:50:54.591191 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 19:50:54.595753
761 19:50:54.623860 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
762 19:50:54.624435 2D training succeed
763 19:50:54.629285 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 19:50:54.634906 auto size-- 65535DDR cs0 size: 2048MB
765 19:50:54.635387 DDR cs1 size: 2048MB
766 19:50:54.640538 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 19:50:54.641041 cs0 DataBus test pass
768 19:50:54.646178 cs1 DataBus test pass
769 19:50:54.646673 cs0 AddrBus test pass
770 19:50:54.647107 cs1 AddrBus test pass
771 19:50:54.647549
772 19:50:54.651702 100bdlr_step_size ps== 420
773 19:50:54.652245 result report
774 19:50:54.657316 boot times 0Enable ddr reg access
775 19:50:54.662764 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 19:50:54.676262 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 19:50:55.249337 0.0;M3 CHK:0;cm4_sp_mode 0
778 19:50:55.249967 MVN_1=0x00000000
779 19:50:55.254810 MVN_2=0x00000000
780 19:50:55.260614 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 19:50:55.261136 OPS=0x10
782 19:50:55.261544 ring efuse init
783 19:50:55.261935 chipver efuse init
784 19:50:55.268815 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 19:50:55.269311 [0.018961 Inits done]
786 19:50:55.276461 secure task start!
787 19:50:55.276934 high task start!
788 19:50:55.277331 low task start!
789 19:50:55.277717 run into bl31
790 19:50:55.283055 NOTICE: BL31: v1.3(release):4fc40b1
791 19:50:55.290927 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 19:50:55.291464 NOTICE: BL31: G12A normal boot!
793 19:50:55.316294 NOTICE: BL31: BL33 decompress pass
794 19:50:55.321949 ERROR: Error initializing runtime service opteed_fast
795 19:50:56.554932
796 19:50:56.555569
797 19:50:56.563343 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 19:50:56.563976
799 19:50:56.564496 Model: Libre Computer AML-A311D-CC Alta
800 19:50:56.771688 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 19:50:56.795073 DRAM: 2 GiB (effective 3.8 GiB)
802 19:50:56.938122 Core: 408 devices, 31 uclasses, devicetree: separate
803 19:50:56.943961 WDT: Not starting watchdog@f0d0
804 19:50:56.976225 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 19:50:56.988596 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 19:50:56.993625 ** Bad device specification mmc 0 **
807 19:50:57.003941 Card did not respond to voltage select! : -110
808 19:50:57.011618 ** Bad device specification mmc 0 **
809 19:50:57.012200 Couldn't find partition mmc 0
810 19:50:57.019952 Card did not respond to voltage select! : -110
811 19:50:57.025538 ** Bad device specification mmc 0 **
812 19:50:57.026088 Couldn't find partition mmc 0
813 19:50:57.030590 Error: could not access storage.
814 19:50:57.372885 Net: eth0: ethernet@ff3f0000
815 19:50:57.373450 starting USB...
816 19:50:57.624756 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 19:50:57.625354 Starting the controller
818 19:50:57.631704 USB XHCI 1.10
819 19:50:59.794191 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 19:50:59.794786 bl2_stage_init 0x01
821 19:50:59.795252 bl2_stage_init 0x81
822 19:50:59.799752 hw id: 0x0000 - pwm id 0x01
823 19:50:59.800336 bl2_stage_init 0xc1
824 19:50:59.800799 bl2_stage_init 0x02
825 19:50:59.801220
826 19:50:59.805333 L0:00000000
827 19:50:59.805950 L1:20000703
828 19:50:59.806539 L2:00008067
829 19:50:59.807064 L3:14000000
830 19:50:59.808523 B2:00402000
831 19:50:59.809085 B1:e0f83180
832 19:50:59.809686
833 19:50:59.810276 TE: 58124
834 19:50:59.810806
835 19:50:59.819652 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 19:50:59.820311
837 19:50:59.820911 Board ID = 1
838 19:50:59.821476 Set A53 clk to 24M
839 19:50:59.821996 Set A73 clk to 24M
840 19:50:59.825240 Set clk81 to 24M
841 19:50:59.825847 A53 clk: 1200 MHz
842 19:50:59.826435 A73 clk: 1200 MHz
843 19:50:59.828716 CLK81: 166.6M
844 19:50:59.829319 smccc: 00012a92
845 19:50:59.834272 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 19:50:59.839785 board id: 1
847 19:50:59.845045 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 19:50:59.855339 fw parse done
849 19:50:59.861377 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 19:50:59.904047 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 19:50:59.914972 PIEI prepare done
852 19:50:59.915524 fastboot data load
853 19:50:59.915977 fastboot data verify
854 19:50:59.920532 verify result: 266
855 19:50:59.926150 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 19:50:59.926665 LPDDR4 probe
857 19:50:59.927115 ddr clk to 1584MHz
858 19:50:59.934105 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 19:50:59.971380
860 19:50:59.971961 dmc_version 0001
861 19:50:59.978096 Check phy result
862 19:50:59.984006 INFO : End of CA training
863 19:50:59.984494 INFO : End of initialization
864 19:50:59.989494 INFO : Training has run successfully!
865 19:50:59.989956 Check phy result
866 19:50:59.995103 INFO : End of initialization
867 19:50:59.995572 INFO : End of read enable training
868 19:51:00.000714 INFO : End of fine write leveling
869 19:51:00.006293 INFO : End of Write leveling coarse delay
870 19:51:00.006764 INFO : Training has run successfully!
871 19:51:00.007166 Check phy result
872 19:51:00.011951 INFO : End of initialization
873 19:51:00.012466 INFO : End of read dq deskew training
874 19:51:00.017492 INFO : End of MPR read delay center optimization
875 19:51:00.023105 INFO : End of write delay center optimization
876 19:51:00.028725 INFO : End of read delay center optimization
877 19:51:00.029215 INFO : End of max read latency training
878 19:51:00.034326 INFO : Training has run successfully!
879 19:51:00.034823 1D training succeed
880 19:51:00.043440 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 19:51:00.090144 Check phy result
882 19:51:00.090651 INFO : End of initialization
883 19:51:00.112837 INFO : End of 2D read delay Voltage center optimization
884 19:51:00.132145 INFO : End of 2D read delay Voltage center optimization
885 19:51:00.184250 INFO : End of 2D write delay Voltage center optimization
886 19:51:00.234517 INFO : End of 2D write delay Voltage center optimization
887 19:51:00.240104 INFO : Training has run successfully!
888 19:51:00.240601
889 19:51:00.241003 channel==0
890 19:51:00.245682 RxClkDly_Margin_A0==88 ps 9
891 19:51:00.246175 TxDqDly_Margin_A0==98 ps 10
892 19:51:00.249073 RxClkDly_Margin_A1==88 ps 9
893 19:51:00.249553 TxDqDly_Margin_A1==98 ps 10
894 19:51:00.254616 TrainedVREFDQ_A0==74
895 19:51:00.255104 TrainedVREFDQ_A1==74
896 19:51:00.255499 VrefDac_Margin_A0==25
897 19:51:00.260280 DeviceVref_Margin_A0==40
898 19:51:00.260773 VrefDac_Margin_A1==25
899 19:51:00.265825 DeviceVref_Margin_A1==40
900 19:51:00.266313
901 19:51:00.266707
902 19:51:00.267093 channel==1
903 19:51:00.267476 RxClkDly_Margin_A0==98 ps 10
904 19:51:00.271412 TxDqDly_Margin_A0==98 ps 10
905 19:51:00.271893 RxClkDly_Margin_A1==98 ps 10
906 19:51:00.277193 TxDqDly_Margin_A1==88 ps 9
907 19:51:00.277724 TrainedVREFDQ_A0==77
908 19:51:00.278117 TrainedVREFDQ_A1==77
909 19:51:00.282607 VrefDac_Margin_A0==22
910 19:51:00.283097 DeviceVref_Margin_A0==37
911 19:51:00.288226 VrefDac_Margin_A1==22
912 19:51:00.288704 DeviceVref_Margin_A1==37
913 19:51:00.289095
914 19:51:00.293804 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 19:51:00.294283
916 19:51:00.321756 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
917 19:51:00.327386 2D training succeed
918 19:51:00.333050 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 19:51:00.333535 auto size-- 65535DDR cs0 size: 2048MB
920 19:51:00.338593 DDR cs1 size: 2048MB
921 19:51:00.339085 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 19:51:00.344221 cs0 DataBus test pass
923 19:51:00.344707 cs1 DataBus test pass
924 19:51:00.345096 cs0 AddrBus test pass
925 19:51:00.349810 cs1 AddrBus test pass
926 19:51:00.350276
927 19:51:00.350671 100bdlr_step_size ps== 420
928 19:51:00.351068 result report
929 19:51:00.355356 boot times 0Enable ddr reg access
930 19:51:00.363115 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 19:51:00.376603 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 19:51:00.950263 0.0;M3 CHK:0;cm4_sp_mode 0
933 19:51:00.950897 MVN_1=0x00000000
934 19:51:00.955827 MVN_2=0x00000000
935 19:51:00.961554 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 19:51:00.962038 OPS=0x10
937 19:51:00.962440 ring efuse init
938 19:51:00.962830 chipver efuse init
939 19:51:00.967169 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 19:51:00.972768 [0.018961 Inits done]
941 19:51:00.973248 secure task start!
942 19:51:00.973648 high task start!
943 19:51:00.977343 low task start!
944 19:51:00.977811 run into bl31
945 19:51:00.984142 NOTICE: BL31: v1.3(release):4fc40b1
946 19:51:00.991833 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 19:51:00.992373 NOTICE: BL31: G12A normal boot!
948 19:51:01.017232 NOTICE: BL31: BL33 decompress pass
949 19:51:01.022911 ERROR: Error initializing runtime service opteed_fast
950 19:51:02.255866
951 19:51:02.256526
952 19:51:02.264213 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 19:51:02.264703
954 19:51:02.265101 Model: Libre Computer AML-A311D-CC Alta
955 19:51:02.472704 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 19:51:02.496130 DRAM: 2 GiB (effective 3.8 GiB)
957 19:51:02.639020 Core: 408 devices, 31 uclasses, devicetree: separate
958 19:51:02.644868 WDT: Not starting watchdog@f0d0
959 19:51:02.677136 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 19:51:02.689577 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 19:51:02.694606 ** Bad device specification mmc 0 **
962 19:51:02.704934 Card did not respond to voltage select! : -110
963 19:51:02.712602 ** Bad device specification mmc 0 **
964 19:51:02.713098 Couldn't find partition mmc 0
965 19:51:02.720940 Card did not respond to voltage select! : -110
966 19:51:02.726427 ** Bad device specification mmc 0 **
967 19:51:02.726902 Couldn't find partition mmc 0
968 19:51:02.731487 Error: could not access storage.
969 19:51:03.073976 Net: eth0: ethernet@ff3f0000
970 19:51:03.074585 starting USB...
971 19:51:03.325774 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 19:51:03.326355 Starting the controller
973 19:51:03.332768 USB XHCI 1.10
974 19:51:05.193074 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 19:51:05.193693 bl2_stage_init 0x01
976 19:51:05.194120 bl2_stage_init 0x81
977 19:51:05.198899 hw id: 0x0000 - pwm id 0x01
978 19:51:05.199398 bl2_stage_init 0xc1
979 19:51:05.199814 bl2_stage_init 0x02
980 19:51:05.200274
981 19:51:05.204381 L0:00000000
982 19:51:05.204877 L1:20000703
983 19:51:05.205305 L2:00008067
984 19:51:05.205715 L3:14000000
985 19:51:05.207226 B2:00402000
986 19:51:05.207690 B1:e0f83180
987 19:51:05.208141
988 19:51:05.208559 TE: 58124
989 19:51:05.208965
990 19:51:05.218237 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 19:51:05.218757
992 19:51:05.219176 Board ID = 1
993 19:51:05.219575 Set A53 clk to 24M
994 19:51:05.219972 Set A73 clk to 24M
995 19:51:05.223950 Set clk81 to 24M
996 19:51:05.224455 A53 clk: 1200 MHz
997 19:51:05.224867 A73 clk: 1200 MHz
998 19:51:05.227434 CLK81: 166.6M
999 19:51:05.227894 smccc: 00012a91
1000 19:51:05.232975 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 19:51:05.238609 board id: 1
1002 19:51:05.243854 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 19:51:05.254418 fw parse done
1004 19:51:05.260370 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 19:51:05.302991 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 19:51:05.313914 PIEI prepare done
1007 19:51:05.314382 fastboot data load
1008 19:51:05.314784 fastboot data verify
1009 19:51:05.319545 verify result: 266
1010 19:51:05.325200 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 19:51:05.325699 LPDDR4 probe
1012 19:51:05.326100 ddr clk to 1584MHz
1013 19:51:05.333119 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 19:51:05.370325
1015 19:51:05.370840 dmc_version 0001
1016 19:51:05.377046 Check phy result
1017 19:51:05.382939 INFO : End of CA training
1018 19:51:05.383413 INFO : End of initialization
1019 19:51:05.388508 INFO : Training has run successfully!
1020 19:51:05.388812 Check phy result
1021 19:51:05.394013 INFO : End of initialization
1022 19:51:05.394332 INFO : End of read enable training
1023 19:51:05.399697 INFO : End of fine write leveling
1024 19:51:05.405337 INFO : End of Write leveling coarse delay
1025 19:51:05.405659 INFO : Training has run successfully!
1026 19:51:05.405885 Check phy result
1027 19:51:05.410861 INFO : End of initialization
1028 19:51:05.411188 INFO : End of read dq deskew training
1029 19:51:05.416477 INFO : End of MPR read delay center optimization
1030 19:51:05.421999 INFO : End of write delay center optimization
1031 19:51:05.427925 INFO : End of read delay center optimization
1032 19:51:05.428294 INFO : End of max read latency training
1033 19:51:05.433238 INFO : Training has run successfully!
1034 19:51:05.433551 1D training succeed
1035 19:51:05.442397 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 19:51:05.490029 Check phy result
1037 19:51:05.490461 INFO : End of initialization
1038 19:51:05.511876 INFO : End of 2D read delay Voltage center optimization
1039 19:51:05.532198 INFO : End of 2D read delay Voltage center optimization
1040 19:51:05.584309 INFO : End of 2D write delay Voltage center optimization
1041 19:51:05.633501 INFO : End of 2D write delay Voltage center optimization
1042 19:51:05.638966 INFO : Training has run successfully!
1043 19:51:05.639424
1044 19:51:05.639681 channel==0
1045 19:51:05.644659 RxClkDly_Margin_A0==88 ps 9
1046 19:51:05.645093 TxDqDly_Margin_A0==98 ps 10
1047 19:51:05.647880 RxClkDly_Margin_A1==88 ps 9
1048 19:51:05.648202 TxDqDly_Margin_A1==98 ps 10
1049 19:51:05.653493 TrainedVREFDQ_A0==74
1050 19:51:05.653815 TrainedVREFDQ_A1==74
1051 19:51:05.659102 VrefDac_Margin_A0==24
1052 19:51:05.659430 DeviceVref_Margin_A0==40
1053 19:51:05.659651 VrefDac_Margin_A1==24
1054 19:51:05.664783 DeviceVref_Margin_A1==40
1055 19:51:05.665136
1056 19:51:05.665361
1057 19:51:05.665565 channel==1
1058 19:51:05.665765 RxClkDly_Margin_A0==98 ps 10
1059 19:51:05.668269 TxDqDly_Margin_A0==98 ps 10
1060 19:51:05.673736 RxClkDly_Margin_A1==88 ps 9
1061 19:51:05.674305 TxDqDly_Margin_A1==88 ps 9
1062 19:51:05.674812 TrainedVREFDQ_A0==77
1063 19:51:05.679293 TrainedVREFDQ_A1==77
1064 19:51:05.679869 VrefDac_Margin_A0==22
1065 19:51:05.684835 DeviceVref_Margin_A0==37
1066 19:51:05.685401 VrefDac_Margin_A1==24
1067 19:51:05.685910 DeviceVref_Margin_A1==37
1068 19:51:05.686425
1069 19:51:05.690436 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 19:51:05.691031
1071 19:51:05.724065 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1072 19:51:05.724738 2D training succeed
1073 19:51:05.729722 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 19:51:05.735065 auto size-- 65535DDR cs0 size: 2048MB
1075 19:51:05.735615 DDR cs1 size: 2048MB
1076 19:51:05.740661 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 19:51:05.741196 cs0 DataBus test pass
1078 19:51:05.741664 cs1 DataBus test pass
1079 19:51:05.746275 cs0 AddrBus test pass
1080 19:51:05.746776 cs1 AddrBus test pass
1081 19:51:05.747232
1082 19:51:05.751876 100bdlr_step_size ps== 420
1083 19:51:05.752418 result report
1084 19:51:05.752874 boot times 0Enable ddr reg access
1085 19:51:05.761784 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 19:51:05.775315 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 19:51:06.349164 0.0;M3 CHK:0;cm4_sp_mode 0
1088 19:51:06.350011 MVN_1=0x00000000
1089 19:51:06.354602 MVN_2=0x00000000
1090 19:51:06.360307 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 19:51:06.360860 OPS=0x10
1092 19:51:06.361347 ring efuse init
1093 19:51:06.361820 chipver efuse init
1094 19:51:06.365908 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 19:51:06.371501 [0.018961 Inits done]
1096 19:51:06.372077 secure task start!
1097 19:51:06.372540 high task start!
1098 19:51:06.376093 low task start!
1099 19:51:06.376583 run into bl31
1100 19:51:06.382783 NOTICE: BL31: v1.3(release):4fc40b1
1101 19:51:06.390599 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 19:51:06.391157 NOTICE: BL31: G12A normal boot!
1103 19:51:06.416066 NOTICE: BL31: BL33 decompress pass
1104 19:51:06.421620 ERROR: Error initializing runtime service opteed_fast
1105 19:51:07.654751
1106 19:51:07.655400
1107 19:51:07.662987 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 19:51:07.663494
1109 19:51:07.663916 Model: Libre Computer AML-A311D-CC Alta
1110 19:51:07.871869 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 19:51:07.894748 DRAM: 2 GiB (effective 3.8 GiB)
1112 19:51:08.037718 Core: 408 devices, 31 uclasses, devicetree: separate
1113 19:51:08.043431 WDT: Not starting watchdog@f0d0
1114 19:51:08.075762 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 19:51:08.088286 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 19:51:08.093218 ** Bad device specification mmc 0 **
1117 19:51:08.103532 Card did not respond to voltage select! : -110
1118 19:51:08.111179 ** Bad device specification mmc 0 **
1119 19:51:08.111653 Couldn't find partition mmc 0
1120 19:51:08.119512 Card did not respond to voltage select! : -110
1121 19:51:08.125027 ** Bad device specification mmc 0 **
1122 19:51:08.125479 Couldn't find partition mmc 0
1123 19:51:08.130099 Error: could not access storage.
1124 19:51:08.473672 Net: eth0: ethernet@ff3f0000
1125 19:51:08.474282 starting USB...
1126 19:51:08.725412 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 19:51:08.726022 Starting the controller
1128 19:51:08.732321 USB XHCI 1.10
1129 19:51:10.290609 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 19:51:10.297780 scanning usb for storage devices... 0 Storage Device(s) found
1132 19:51:10.349117 Hit any key to stop autoboot: 1
1133 19:51:10.349749 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 19:51:10.350114 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 19:51:10.350388 Setting prompt string to ['=>']
1136 19:51:10.350665 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 19:51:10.365254 0
1138 19:51:10.366706 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 19:51:10.367286 Sending with 10 millisecond of delay
1141 19:51:11.510078 => setenv autoload no
1142 19:51:11.521141 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 19:51:11.526278 setenv autoload no
1144 19:51:11.527155 Sending with 10 millisecond of delay
1146 19:51:13.329457 => setenv initrd_high 0xffffffff
1147 19:51:13.340456 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 19:51:13.341624 setenv initrd_high 0xffffffff
1149 19:51:13.342484 Sending with 10 millisecond of delay
1151 19:51:14.964790 => setenv fdt_high 0xffffffff
1152 19:51:14.975382 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1153 19:51:14.976066 setenv fdt_high 0xffffffff
1154 19:51:14.976573 Sending with 10 millisecond of delay
1156 19:51:15.268196 => dhcp
1157 19:51:15.278743 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 19:51:15.279304 dhcp
1159 19:51:15.279543 Speed: 1000, full duplex
1160 19:51:15.279775 BOOTP broadcast 1
1161 19:51:15.509163 DHCP client bound to address 192.168.6.27 (230 ms)
1162 19:51:15.510516 Sending with 10 millisecond of delay
1164 19:51:17.187945 => setenv serverip 192.168.6.2
1165 19:51:17.198754 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 19:51:17.199684 setenv serverip 192.168.6.2
1167 19:51:17.200445 Sending with 10 millisecond of delay
1169 19:51:20.929397 => tftpboot 0x01080000 972027/tftp-deploy-j_b2qfj0/kernel/uImage
1170 19:51:20.940015 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1171 19:51:20.940638 tftpboot 0x01080000 972027/tftp-deploy-j_b2qfj0/kernel/uImage
1172 19:51:20.940891 Speed: 1000, full duplex
1173 19:51:20.941109 Using ethernet@ff3f0000 device
1174 19:51:20.942754 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 19:51:20.948305 Filename '972027/tftp-deploy-j_b2qfj0/kernel/uImage'.
1176 19:51:20.952138 Load address: 0x1080000
1177 19:51:23.882584 Loading: *################################################## 43.6 MiB
1178 19:51:23.883197 14.9 MiB/s
1179 19:51:23.883601 done
1180 19:51:23.887185 Bytes transferred = 45713984 (2b98a40 hex)
1181 19:51:23.887937 Sending with 10 millisecond of delay
1183 19:51:28.575807 => tftpboot 0x08000000 972027/tftp-deploy-j_b2qfj0/ramdisk/ramdisk.cpio.gz.uboot
1184 19:51:28.586651 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1185 19:51:28.587511 tftpboot 0x08000000 972027/tftp-deploy-j_b2qfj0/ramdisk/ramdisk.cpio.gz.uboot
1186 19:51:28.587929 Speed: 1000, full duplex
1187 19:51:28.588374 Using ethernet@ff3f0000 device
1188 19:51:28.589413 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 19:51:28.601391 Filename '972027/tftp-deploy-j_b2qfj0/ramdisk/ramdisk.cpio.gz.uboot'.
1190 19:51:28.601896 Load address: 0x8000000
1191 19:51:35.209057 Loading: *###################T ############################## UDP wrong checksum 00000005 00005770
1192 19:51:40.209411 T UDP wrong checksum 00000005 00005770
1193 19:51:50.212545 T T UDP wrong checksum 00000005 00005770
1194 19:52:10.216279 T T T T UDP wrong checksum 00000005 00005770
1195 19:52:25.089298 T T UDP wrong checksum 000000ff 0000f86a
1196 19:52:25.139528 UDP wrong checksum 000000ff 00008b5d
1197 19:52:25.220185
1198 19:52:25.220573 Retry count exceeded; starting again
1200 19:52:25.221482 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1203 19:52:25.222632 end: 2.4 uboot-commands (duration 00:01:52) [common]
1205 19:52:25.223462 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1207 19:52:25.224103 end: 2 uboot-action (duration 00:01:52) [common]
1209 19:52:25.225008 Cleaning after the job
1210 19:52:25.225395 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972027/tftp-deploy-j_b2qfj0/ramdisk
1211 19:52:25.226154 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972027/tftp-deploy-j_b2qfj0/kernel
1212 19:52:25.237400 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972027/tftp-deploy-j_b2qfj0/dtb
1213 19:52:25.238553 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972027/tftp-deploy-j_b2qfj0/nfsrootfs
1214 19:52:25.268089 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972027/tftp-deploy-j_b2qfj0/modules
1215 19:52:25.275478 start: 4.1 power-off (timeout 00:00:30) [common]
1216 19:52:25.276224 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1217 19:52:25.309624 >> OK - accepted request
1218 19:52:25.311500 Returned 0 in 0 seconds
1219 19:52:25.412627 end: 4.1 power-off (duration 00:00:00) [common]
1221 19:52:25.414161 start: 4.2 read-feedback (timeout 00:10:00) [common]
1222 19:52:25.415504 Listened to connection for namespace 'common' for up to 1s
1223 19:52:26.416129 Finalising connection for namespace 'common'
1224 19:52:26.416689 Disconnecting from shell: Finalise
1225 19:52:26.417044 =>
1226 19:52:26.517890 end: 4.2 read-feedback (duration 00:00:01) [common]
1227 19:52:26.518513 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/972027
1228 19:52:30.564131 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/972027
1229 19:52:30.564771 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.