Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 19:52:16.092873 lava-dispatcher, installed at version: 2024.01
2 19:52:16.093680 start: 0 validate
3 19:52:16.094178 Start time: 2024-11-04 19:52:16.094147+00:00 (UTC)
4 19:52:16.094737 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 19:52:16.095299 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 19:52:16.136848 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 19:52:16.137614 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-5-g557329bcecc2%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 19:52:16.175951 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 19:52:16.176598 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-5-g557329bcecc2%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 19:52:17.233265 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 19:52:17.233789 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-5-g557329bcecc2%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 19:52:17.282227 validate duration: 1.19
14 19:52:17.284178 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:52:17.285021 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:52:17.285770 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:52:17.287023 Not decompressing ramdisk as can be used compressed.
18 19:52:17.287977 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 19:52:17.288620 saving as /var/lib/lava/dispatcher/tmp/936392/tftp-deploy-edgplj6a/ramdisk/rootfs.cpio.gz
20 19:52:17.289246 total size: 8181887 (7 MB)
21 19:52:17.333564 progress 0 % (0 MB)
22 19:52:17.339742 progress 5 % (0 MB)
23 19:52:17.345356 progress 10 % (0 MB)
24 19:52:17.351388 progress 15 % (1 MB)
25 19:52:17.356997 progress 20 % (1 MB)
26 19:52:17.363002 progress 25 % (1 MB)
27 19:52:17.368561 progress 30 % (2 MB)
28 19:52:17.374255 progress 35 % (2 MB)
29 19:52:17.379536 progress 40 % (3 MB)
30 19:52:17.385210 progress 45 % (3 MB)
31 19:52:17.390431 progress 50 % (3 MB)
32 19:52:17.396053 progress 55 % (4 MB)
33 19:52:17.401279 progress 60 % (4 MB)
34 19:52:17.406908 progress 65 % (5 MB)
35 19:52:17.412328 progress 70 % (5 MB)
36 19:52:17.418046 progress 75 % (5 MB)
37 19:52:17.423303 progress 80 % (6 MB)
38 19:52:17.428983 progress 85 % (6 MB)
39 19:52:17.434230 progress 90 % (7 MB)
40 19:52:17.439601 progress 95 % (7 MB)
41 19:52:17.444417 progress 100 % (7 MB)
42 19:52:17.445083 7 MB downloaded in 0.16 s (50.07 MB/s)
43 19:52:17.445636 end: 1.1.1 http-download (duration 00:00:00) [common]
45 19:52:17.446520 end: 1.1 download-retry (duration 00:00:00) [common]
46 19:52:17.446812 start: 1.2 download-retry (timeout 00:10:00) [common]
47 19:52:17.447082 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 19:52:17.447572 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-5-g557329bcecc2/arm64/defconfig/gcc-12/kernel/Image
49 19:52:17.447824 saving as /var/lib/lava/dispatcher/tmp/936392/tftp-deploy-edgplj6a/kernel/Image
50 19:52:17.448056 total size: 45713920 (43 MB)
51 19:52:17.448272 No compression specified
52 19:52:17.487801 progress 0 % (0 MB)
53 19:52:17.516592 progress 5 % (2 MB)
54 19:52:17.545499 progress 10 % (4 MB)
55 19:52:17.574427 progress 15 % (6 MB)
56 19:52:17.603000 progress 20 % (8 MB)
57 19:52:17.631866 progress 25 % (10 MB)
58 19:52:17.660462 progress 30 % (13 MB)
59 19:52:17.689198 progress 35 % (15 MB)
60 19:52:17.718435 progress 40 % (17 MB)
61 19:52:17.746972 progress 45 % (19 MB)
62 19:52:17.775838 progress 50 % (21 MB)
63 19:52:17.804620 progress 55 % (24 MB)
64 19:52:17.833403 progress 60 % (26 MB)
65 19:52:17.861831 progress 65 % (28 MB)
66 19:52:17.890263 progress 70 % (30 MB)
67 19:52:17.919082 progress 75 % (32 MB)
68 19:52:17.947996 progress 80 % (34 MB)
69 19:52:17.976213 progress 85 % (37 MB)
70 19:52:18.004912 progress 90 % (39 MB)
71 19:52:18.033823 progress 95 % (41 MB)
72 19:52:18.062330 progress 100 % (43 MB)
73 19:52:18.062924 43 MB downloaded in 0.61 s (70.90 MB/s)
74 19:52:18.063421 end: 1.2.1 http-download (duration 00:00:01) [common]
76 19:52:18.064294 end: 1.2 download-retry (duration 00:00:01) [common]
77 19:52:18.064582 start: 1.3 download-retry (timeout 00:09:59) [common]
78 19:52:18.064851 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 19:52:18.065338 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-5-g557329bcecc2/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 19:52:18.065630 saving as /var/lib/lava/dispatcher/tmp/936392/tftp-deploy-edgplj6a/dtb/meson-g12b-a311d-libretech-cc.dtb
81 19:52:18.065842 total size: 54703 (0 MB)
82 19:52:18.066054 No compression specified
83 19:52:18.108060 progress 59 % (0 MB)
84 19:52:18.109124 progress 100 % (0 MB)
85 19:52:18.109827 0 MB downloaded in 0.04 s (1.19 MB/s)
86 19:52:18.110451 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:52:18.111474 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:52:18.111804 start: 1.4 download-retry (timeout 00:09:59) [common]
90 19:52:18.112192 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 19:52:18.112797 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-5-g557329bcecc2/arm64/defconfig/gcc-12/modules.tar.xz
92 19:52:18.113109 saving as /var/lib/lava/dispatcher/tmp/936392/tftp-deploy-edgplj6a/modules/modules.tar
93 19:52:18.113360 total size: 11612232 (11 MB)
94 19:52:18.113626 Using unxz to decompress xz
95 19:52:18.149270 progress 0 % (0 MB)
96 19:52:18.215144 progress 5 % (0 MB)
97 19:52:18.289084 progress 10 % (1 MB)
98 19:52:18.385397 progress 15 % (1 MB)
99 19:52:18.477749 progress 20 % (2 MB)
100 19:52:18.558268 progress 25 % (2 MB)
101 19:52:18.634870 progress 30 % (3 MB)
102 19:52:18.713384 progress 35 % (3 MB)
103 19:52:18.787004 progress 40 % (4 MB)
104 19:52:18.864534 progress 45 % (5 MB)
105 19:52:18.949916 progress 50 % (5 MB)
106 19:52:19.026831 progress 55 % (6 MB)
107 19:52:19.112016 progress 60 % (6 MB)
108 19:52:19.193433 progress 65 % (7 MB)
109 19:52:19.275302 progress 70 % (7 MB)
110 19:52:19.352677 progress 75 % (8 MB)
111 19:52:19.435834 progress 80 % (8 MB)
112 19:52:19.515730 progress 85 % (9 MB)
113 19:52:19.594195 progress 90 % (9 MB)
114 19:52:19.671650 progress 95 % (10 MB)
115 19:52:19.748508 progress 100 % (11 MB)
116 19:52:19.760168 11 MB downloaded in 1.65 s (6.72 MB/s)
117 19:52:19.760776 end: 1.4.1 http-download (duration 00:00:02) [common]
119 19:52:19.761619 end: 1.4 download-retry (duration 00:00:02) [common]
120 19:52:19.761896 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 19:52:19.762169 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 19:52:19.762423 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:52:19.762683 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 19:52:19.763286 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso
125 19:52:19.763767 makedir: /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin
126 19:52:19.764300 makedir: /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/tests
127 19:52:19.764945 makedir: /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/results
128 19:52:19.765573 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-add-keys
129 19:52:19.766520 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-add-sources
130 19:52:19.767475 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-background-process-start
131 19:52:19.768461 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-background-process-stop
132 19:52:19.769460 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-common-functions
133 19:52:19.770373 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-echo-ipv4
134 19:52:19.771272 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-install-packages
135 19:52:19.772188 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-installed-packages
136 19:52:19.773084 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-os-build
137 19:52:19.773974 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-probe-channel
138 19:52:19.774861 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-probe-ip
139 19:52:19.775753 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-target-ip
140 19:52:19.776697 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-target-mac
141 19:52:19.777591 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-target-storage
142 19:52:19.778499 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-test-case
143 19:52:19.779385 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-test-event
144 19:52:19.780310 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-test-feedback
145 19:52:19.781205 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-test-raise
146 19:52:19.782083 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-test-reference
147 19:52:19.782967 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-test-runner
148 19:52:19.783851 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-test-set
149 19:52:19.784803 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-test-shell
150 19:52:19.785713 Updating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-install-packages (oe)
151 19:52:19.786686 Updating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/bin/lava-installed-packages (oe)
152 19:52:19.787523 Creating /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/environment
153 19:52:19.788268 LAVA metadata
154 19:52:19.788770 - LAVA_JOB_ID=936392
155 19:52:19.789196 - LAVA_DISPATCHER_IP=192.168.6.2
156 19:52:19.789844 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 19:52:19.791753 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 19:52:19.792410 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 19:52:19.792825 skipped lava-vland-overlay
160 19:52:19.793310 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 19:52:19.793820 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 19:52:19.794247 skipped lava-multinode-overlay
163 19:52:19.794729 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 19:52:19.795231 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 19:52:19.795699 Loading test definitions
166 19:52:19.796210 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 19:52:19.796455 Using /lava-936392 at stage 0
168 19:52:19.797660 uuid=936392_1.5.2.4.1 testdef=None
169 19:52:19.797998 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 19:52:19.798273 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 19:52:19.800098 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 19:52:19.800940 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 19:52:19.803202 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 19:52:19.804119 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 19:52:19.806316 runner path: /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/0/tests/0_dmesg test_uuid 936392_1.5.2.4.1
178 19:52:19.806898 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 19:52:19.807696 Creating lava-test-runner.conf files
181 19:52:19.807904 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/936392/lava-overlay-cr9xugso/lava-936392/0 for stage 0
182 19:52:19.808269 - 0_dmesg
183 19:52:19.808630 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 19:52:19.808923 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 19:52:19.832358 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 19:52:19.832783 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 19:52:19.833053 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 19:52:19.833328 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 19:52:19.833593 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 19:52:20.748700 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 19:52:20.749169 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 19:52:20.749420 extracting modules file /var/lib/lava/dispatcher/tmp/936392/tftp-deploy-edgplj6a/modules/modules.tar to /var/lib/lava/dispatcher/tmp/936392/extract-overlay-ramdisk-pypyhrku/ramdisk
193 19:52:22.104533 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 19:52:22.105061 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 19:52:22.105331 [common] Applying overlay /var/lib/lava/dispatcher/tmp/936392/compress-overlay-kb2qto8r/overlay-1.5.2.5.tar.gz to ramdisk
196 19:52:22.105548 [common] Applying overlay /var/lib/lava/dispatcher/tmp/936392/compress-overlay-kb2qto8r/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/936392/extract-overlay-ramdisk-pypyhrku/ramdisk
197 19:52:22.135840 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 19:52:22.136287 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 19:52:22.136567 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 19:52:22.136797 Converting downloaded kernel to a uImage
201 19:52:22.137105 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/936392/tftp-deploy-edgplj6a/kernel/Image /var/lib/lava/dispatcher/tmp/936392/tftp-deploy-edgplj6a/kernel/uImage
202 19:52:22.617386 output: Image Name:
203 19:52:22.617795 output: Created: Mon Nov 4 19:52:22 2024
204 19:52:22.618007 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 19:52:22.618214 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 19:52:22.618416 output: Load Address: 01080000
207 19:52:22.618614 output: Entry Point: 01080000
208 19:52:22.618812 output:
209 19:52:22.619146 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 19:52:22.619417 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 19:52:22.619692 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 19:52:22.619949 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 19:52:22.620256 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 19:52:22.620514 Building ramdisk /var/lib/lava/dispatcher/tmp/936392/extract-overlay-ramdisk-pypyhrku/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/936392/extract-overlay-ramdisk-pypyhrku/ramdisk
215 19:52:25.003911 >> 181607 blocks
216 19:52:33.570514 Adding RAMdisk u-boot header.
217 19:52:33.571181 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/936392/extract-overlay-ramdisk-pypyhrku/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/936392/extract-overlay-ramdisk-pypyhrku/ramdisk.cpio.gz.uboot
218 19:52:33.855296 output: Image Name:
219 19:52:33.855728 output: Created: Mon Nov 4 19:52:33 2024
220 19:52:33.855937 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 19:52:33.856336 output: Data Size: 26062453 Bytes = 25451.61 KiB = 24.86 MiB
222 19:52:33.856739 output: Load Address: 00000000
223 19:52:33.857138 output: Entry Point: 00000000
224 19:52:33.857528 output:
225 19:52:33.861867 rename /var/lib/lava/dispatcher/tmp/936392/extract-overlay-ramdisk-pypyhrku/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/936392/tftp-deploy-edgplj6a/ramdisk/ramdisk.cpio.gz.uboot
226 19:52:33.862415 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 19:52:33.863115 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 19:52:33.863698 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 19:52:33.864071 No LXC device requested
230 19:52:33.864387 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 19:52:33.864686 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 19:52:33.865070 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 19:52:33.865529 Checking files for TFTP limit of 4294967296 bytes.
234 19:52:33.868671 end: 1 tftp-deploy (duration 00:00:17) [common]
235 19:52:33.869311 start: 2 uboot-action (timeout 00:05:00) [common]
236 19:52:33.869847 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 19:52:33.870352 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 19:52:33.870862 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 19:52:33.871398 Using kernel file from prepare-kernel: 936392/tftp-deploy-edgplj6a/kernel/uImage
240 19:52:33.872062 substitutions:
241 19:52:33.872494 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 19:52:33.872901 - {DTB_ADDR}: 0x01070000
243 19:52:33.873300 - {DTB}: 936392/tftp-deploy-edgplj6a/dtb/meson-g12b-a311d-libretech-cc.dtb
244 19:52:33.873704 - {INITRD}: 936392/tftp-deploy-edgplj6a/ramdisk/ramdisk.cpio.gz.uboot
245 19:52:33.874104 - {KERNEL_ADDR}: 0x01080000
246 19:52:33.874499 - {KERNEL}: 936392/tftp-deploy-edgplj6a/kernel/uImage
247 19:52:33.874894 - {LAVA_MAC}: None
248 19:52:33.875328 - {PRESEED_CONFIG}: None
249 19:52:33.875726 - {PRESEED_LOCAL}: None
250 19:52:33.876098 - {RAMDISK_ADDR}: 0x08000000
251 19:52:33.876303 - {RAMDISK}: 936392/tftp-deploy-edgplj6a/ramdisk/ramdisk.cpio.gz.uboot
252 19:52:33.876505 - {ROOT_PART}: None
253 19:52:33.876704 - {ROOT}: None
254 19:52:33.876901 - {SERVER_IP}: 192.168.6.2
255 19:52:33.877102 - {TEE_ADDR}: 0x83000000
256 19:52:33.877301 - {TEE}: None
257 19:52:33.877498 Parsed boot commands:
258 19:52:33.877690 - setenv autoload no
259 19:52:33.877888 - setenv initrd_high 0xffffffff
260 19:52:33.878085 - setenv fdt_high 0xffffffff
261 19:52:33.878279 - dhcp
262 19:52:33.878475 - setenv serverip 192.168.6.2
263 19:52:33.878669 - tftpboot 0x01080000 936392/tftp-deploy-edgplj6a/kernel/uImage
264 19:52:33.878866 - tftpboot 0x08000000 936392/tftp-deploy-edgplj6a/ramdisk/ramdisk.cpio.gz.uboot
265 19:52:33.879061 - tftpboot 0x01070000 936392/tftp-deploy-edgplj6a/dtb/meson-g12b-a311d-libretech-cc.dtb
266 19:52:33.879257 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 19:52:33.879456 - bootm 0x01080000 0x08000000 0x01070000
268 19:52:33.879714 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 19:52:33.880505 start: 2.3 connect-device (timeout 00:05:00) [common]
271 19:52:33.880745 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 19:52:33.892860 Setting prompt string to ['lava-test: # ']
273 19:52:33.893760 end: 2.3 connect-device (duration 00:00:00) [common]
274 19:52:33.894092 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 19:52:33.894380 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 19:52:33.894661 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 19:52:33.895304 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 19:52:33.928619 >> OK - accepted request
279 19:52:33.930747 Returned 0 in 0 seconds
280 19:52:34.031840 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 19:52:34.033507 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 19:52:34.034084 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 19:52:34.034598 Setting prompt string to ['Hit any key to stop autoboot']
285 19:52:34.035060 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 19:52:34.036695 Trying 192.168.56.21...
287 19:52:34.037178 Connected to conserv1.
288 19:52:34.037593 Escape character is '^]'.
289 19:52:34.038012
290 19:52:34.038431 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 19:52:34.038859
292 19:52:44.919092 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
293 19:52:44.919515 bl2_stage_init 0x81
294 19:52:44.924718 hw id: 0x0000 - pwm id 0x01
295 19:52:44.925026 bl2_stage_init 0xc1
296 19:52:44.925258 bl2_stage_init 0x02
297 19:52:44.925478
298 19:52:44.930336 L0:00000000
299 19:52:44.930605 L1:20000703
300 19:52:44.930830 L2:00008067
301 19:52:44.931052 L3:14000000
302 19:52:44.931260 B2:00402000
303 19:52:44.935809 B1:e0f83180
304 19:52:44.936079
305 19:52:44.936298 TE: 58150
306 19:52:44.936508
307 19:52:44.941532 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
308 19:52:44.941792
309 19:52:44.942005 Board ID = 1
310 19:52:44.947047 Set A53 clk to 24M
311 19:52:44.947298 Set A73 clk to 24M
312 19:52:44.947512 Set clk81 to 24M
313 19:52:44.952666 A53 clk: 1200 MHz
314 19:52:44.952916 A73 clk: 1200 MHz
315 19:52:44.953128 CLK81: 166.6M
316 19:52:44.953330 smccc: 00012aab
317 19:52:44.958318 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
318 19:52:44.963788 board id: 1
319 19:52:44.969724 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
320 19:52:44.980196 fw parse done
321 19:52:44.986045 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
322 19:52:45.028731 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
323 19:52:45.039593 PIEI prepare done
324 19:52:45.039858 fastboot data load
325 19:52:45.040113 fastboot data verify
326 19:52:45.045286 verify result: 266
327 19:52:45.050897 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
328 19:52:45.051155 LPDDR4 probe
329 19:52:45.051368 ddr clk to 1584MHz
330 19:52:45.058802 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
331 19:52:45.096229
332 19:52:45.096536 dmc_version 0001
333 19:52:45.102799 Check phy result
334 19:52:45.108668 INFO : End of CA training
335 19:52:45.109086 INFO : End of initialization
336 19:52:45.114321 INFO : Training has run successfully!
337 19:52:45.114737 Check phy result
338 19:52:45.119884 INFO : End of initialization
339 19:52:45.120321 INFO : End of read enable training
340 19:52:45.123283 INFO : End of fine write leveling
341 19:52:45.128806 INFO : End of Write leveling coarse delay
342 19:52:45.134405 INFO : Training has run successfully!
343 19:52:45.134812 Check phy result
344 19:52:45.135199 INFO : End of initialization
345 19:52:45.140030 INFO : End of read dq deskew training
346 19:52:45.145607 INFO : End of MPR read delay center optimization
347 19:52:45.146021 INFO : End of write delay center optimization
348 19:52:45.151286 INFO : End of read delay center optimization
349 19:52:45.156807 INFO : End of max read latency training
350 19:52:45.157219 INFO : Training has run successfully!
351 19:52:45.162350 1D training succeed
352 19:52:45.168346 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
353 19:52:45.215891 Check phy result
354 19:52:45.216347 INFO : End of initialization
355 19:52:45.237575 INFO : End of 2D read delay Voltage center optimization
356 19:52:45.257801 INFO : End of 2D read delay Voltage center optimization
357 19:52:45.309860 INFO : End of 2D write delay Voltage center optimization
358 19:52:45.359291 INFO : End of 2D write delay Voltage center optimization
359 19:52:45.364783 INFO : Training has run successfully!
360 19:52:45.365209
361 19:52:45.365604 channel==0
362 19:52:45.370350 RxClkDly_Margin_A0==88 ps 9
363 19:52:45.370762 TxDqDly_Margin_A0==98 ps 10
364 19:52:45.376155 RxClkDly_Margin_A1==88 ps 9
365 19:52:45.376568 TxDqDly_Margin_A1==98 ps 10
366 19:52:45.376957 TrainedVREFDQ_A0==74
367 19:52:45.381573 TrainedVREFDQ_A1==76
368 19:52:45.381987 VrefDac_Margin_A0==25
369 19:52:45.382369 DeviceVref_Margin_A0==40
370 19:52:45.387287 VrefDac_Margin_A1==25
371 19:52:45.387695 DeviceVref_Margin_A1==38
372 19:52:45.388109
373 19:52:45.388504
374 19:52:45.392773 channel==1
375 19:52:45.393186 RxClkDly_Margin_A0==98 ps 10
376 19:52:45.393575 TxDqDly_Margin_A0==98 ps 10
377 19:52:45.398370 RxClkDly_Margin_A1==98 ps 10
378 19:52:45.398780 TxDqDly_Margin_A1==98 ps 10
379 19:52:45.404045 TrainedVREFDQ_A0==77
380 19:52:45.404463 TrainedVREFDQ_A1==78
381 19:52:45.404850 VrefDac_Margin_A0==22
382 19:52:45.409574 DeviceVref_Margin_A0==37
383 19:52:45.409983 VrefDac_Margin_A1==22
384 19:52:45.415316 DeviceVref_Margin_A1==36
385 19:52:45.415727
386 19:52:45.416138 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
387 19:52:45.420777
388 19:52:45.448779 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
389 19:52:45.449274 2D training succeed
390 19:52:45.454369 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
391 19:52:45.460069 auto size-- 65535DDR cs0 size: 2048MB
392 19:52:45.460489 DDR cs1 size: 2048MB
393 19:52:45.465572 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
394 19:52:45.465982 cs0 DataBus test pass
395 19:52:45.471279 cs1 DataBus test pass
396 19:52:45.471697 cs0 AddrBus test pass
397 19:52:45.472108 cs1 AddrBus test pass
398 19:52:45.472491
399 19:52:45.476798 100bdlr_step_size ps== 420
400 19:52:45.477218 result report
401 19:52:45.482305 boot times 0Enable ddr reg access
402 19:52:45.487828 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
403 19:52:45.501328 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
404 19:52:46.075161 0.0;M3 CHK:0;cm4_sp_mode 0
405 19:52:46.075796 MVN_1=0x00000000
406 19:52:46.080644 MVN_2=0x00000000
407 19:52:46.086509 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
408 19:52:46.086988 OPS=0x10
409 19:52:46.087408 ring efuse init
410 19:52:46.087813 chipver efuse init
411 19:52:46.092040 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
412 19:52:46.097612 [0.018961 Inits done]
413 19:52:46.098077 secure task start!
414 19:52:46.098485 high task start!
415 19:52:46.102209 low task start!
416 19:52:46.102668 run into bl31
417 19:52:46.108820 NOTICE: BL31: v1.3(release):4fc40b1
418 19:52:46.116612 NOTICE: BL31: Built : 15:58:17, May 22 2019
419 19:52:46.117078 NOTICE: BL31: G12A normal boot!
420 19:52:46.141964 NOTICE: BL31: BL33 decompress pass
421 19:52:46.147664 ERROR: Error initializing runtime service opteed_fast
422 19:52:47.380646
423 19:52:47.381252
424 19:52:47.388957 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
425 19:52:47.389444
426 19:52:47.389863 Model: Libre Computer AML-A311D-CC Alta
427 19:52:47.597429 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
428 19:52:47.620849 DRAM: 2 GiB (effective 3.8 GiB)
429 19:52:47.763781 Core: 408 devices, 31 uclasses, devicetree: separate
430 19:52:47.769613 WDT: Not starting watchdog@f0d0
431 19:52:47.801846 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
432 19:52:47.814278 Loading Environment from FAT... Card did not respond to voltage select! : -110
433 19:52:47.819299 ** Bad device specification mmc 0 **
434 19:52:47.829742 Card did not respond to voltage select! : -110
435 19:52:47.837295 ** Bad device specification mmc 0 **
436 19:52:47.837766 Couldn't find partition mmc 0
437 19:52:47.845720 Card did not respond to voltage select! : -110
438 19:52:47.851145 ** Bad device specification mmc 0 **
439 19:52:47.851610 Couldn't find partition mmc 0
440 19:52:47.856196 Error: could not access storage.
441 19:52:49.119707 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
442 19:52:49.120178 bl2_stage_init 0x01
443 19:52:49.120407 bl2_stage_init 0x81
444 19:52:49.124930 hw id: 0x0000 - pwm id 0x01
445 19:52:49.125289 bl2_stage_init 0xc1
446 19:52:49.125507 bl2_stage_init 0x02
447 19:52:49.125713
448 19:52:49.130644 L0:00000000
449 19:52:49.131133 L1:20000703
450 19:52:49.131467 L2:00008067
451 19:52:49.131784 L3:14000000
452 19:52:49.136171 B2:00402000
453 19:52:49.136639 B1:e0f83180
454 19:52:49.136967
455 19:52:49.137287 TE: 58124
456 19:52:49.137610
457 19:52:49.141862 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 19:52:49.142325
459 19:52:49.142655 Board ID = 1
460 19:52:49.147335 Set A53 clk to 24M
461 19:52:49.147662 Set A73 clk to 24M
462 19:52:49.147874 Set clk81 to 24M
463 19:52:49.152954 A53 clk: 1200 MHz
464 19:52:49.153309 A73 clk: 1200 MHz
465 19:52:49.153526 CLK81: 166.6M
466 19:52:49.153732 smccc: 00012a92
467 19:52:49.158623 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 19:52:49.164148 board id: 1
469 19:52:49.170000 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 19:52:49.180697 fw parse done
471 19:52:49.186673 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 19:52:49.229275 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 19:52:49.240212 PIEI prepare done
474 19:52:49.240598 fastboot data load
475 19:52:49.240810 fastboot data verify
476 19:52:49.245866 verify result: 266
477 19:52:49.251380 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 19:52:49.251863 LPDDR4 probe
479 19:52:49.252258 ddr clk to 1584MHz
480 19:52:49.259404 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 19:52:49.296653
482 19:52:49.297068 dmc_version 0001
483 19:52:49.303264 Check phy result
484 19:52:49.309158 INFO : End of CA training
485 19:52:49.309481 INFO : End of initialization
486 19:52:49.314856 INFO : Training has run successfully!
487 19:52:49.315176 Check phy result
488 19:52:49.320345 INFO : End of initialization
489 19:52:49.320821 INFO : End of read enable training
490 19:52:49.323624 INFO : End of fine write leveling
491 19:52:49.329189 INFO : End of Write leveling coarse delay
492 19:52:49.337822 INFO : Training has run successfully!
493 19:52:49.338261 Check phy result
494 19:52:49.338683 INFO : End of initialization
495 19:52:49.340378 INFO : End of read dq deskew training
496 19:52:49.347688 INFO : End of MPR read delay center optimization
497 19:52:49.350207 INFO : End of write delay center optimization
498 19:52:49.352059 INFO : End of read delay center optimization
499 19:52:49.357780 INFO : End of max read latency training
500 19:52:49.358368 INFO : Training has run successfully!
501 19:52:49.363774 1D training succeed
502 19:52:49.368790 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 19:52:49.416525 Check phy result
504 19:52:49.416962 INFO : End of initialization
505 19:52:49.438430 INFO : End of 2D read delay Voltage center optimization
506 19:52:49.458101 INFO : End of 2D read delay Voltage center optimization
507 19:52:49.510188 INFO : End of 2D write delay Voltage center optimization
508 19:52:49.559481 INFO : End of 2D write delay Voltage center optimization
509 19:52:49.565493 INFO : Training has run successfully!
510 19:52:49.565946
511 19:52:49.566185 channel==0
512 19:52:49.570414 RxClkDly_Margin_A0==88 ps 9
513 19:52:49.570835 TxDqDly_Margin_A0==98 ps 10
514 19:52:49.573626 RxClkDly_Margin_A1==88 ps 9
515 19:52:49.574166 TxDqDly_Margin_A1==98 ps 10
516 19:52:49.580887 TrainedVREFDQ_A0==74
517 19:52:49.581336 TrainedVREFDQ_A1==74
518 19:52:49.586001 VrefDac_Margin_A0==25
519 19:52:49.586613 DeviceVref_Margin_A0==40
520 19:52:49.586991 VrefDac_Margin_A1==25
521 19:52:49.590859 DeviceVref_Margin_A1==40
522 19:52:49.591263
523 19:52:49.591487
524 19:52:49.591694 channel==1
525 19:52:49.591902 RxClkDly_Margin_A0==98 ps 10
526 19:52:49.596159 TxDqDly_Margin_A0==98 ps 10
527 19:52:49.596584 RxClkDly_Margin_A1==88 ps 9
528 19:52:49.601665 TxDqDly_Margin_A1==88 ps 9
529 19:52:49.602257 TrainedVREFDQ_A0==77
530 19:52:49.602644 TrainedVREFDQ_A1==77
531 19:52:49.607141 VrefDac_Margin_A0==22
532 19:52:49.607575 DeviceVref_Margin_A0==37
533 19:52:49.612940 VrefDac_Margin_A1==24
534 19:52:49.613386 DeviceVref_Margin_A1==37
535 19:52:49.613676
536 19:52:49.618433 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 19:52:49.618894
538 19:52:49.646407 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
539 19:52:49.652010 2D training succeed
540 19:52:49.657859 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 19:52:49.658298 auto size-- 65535DDR cs0 size: 2048MB
542 19:52:49.663250 DDR cs1 size: 2048MB
543 19:52:49.663669 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 19:52:49.668912 cs0 DataBus test pass
545 19:52:49.669423 cs1 DataBus test pass
546 19:52:49.669855 cs0 AddrBus test pass
547 19:52:49.674371 cs1 AddrBus test pass
548 19:52:49.674795
549 19:52:49.675066 100bdlr_step_size ps== 420
550 19:52:49.675328 result report
551 19:52:49.679997 boot times 0Enable ddr reg access
552 19:52:49.687770 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 19:52:49.701169 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 19:52:50.273474 0.0;M3 CHK:0;cm4_sp_mode 0
555 19:52:50.274103 MVN_1=0x00000000
556 19:52:50.278874 MVN_2=0x00000000
557 19:52:50.284533 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 19:52:50.285054 OPS=0x10
559 19:52:50.285503 ring efuse init
560 19:52:50.285930 chipver efuse init
561 19:52:50.292644 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 19:52:50.293157 [0.018961 Inits done]
563 19:52:50.300389 secure task start!
564 19:52:50.300826 high task start!
565 19:52:50.301212 low task start!
566 19:52:50.301593 run into bl31
567 19:52:50.307034 NOTICE: BL31: v1.3(release):4fc40b1
568 19:52:50.314848 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 19:52:50.315284 NOTICE: BL31: G12A normal boot!
570 19:52:50.340186 NOTICE: BL31: BL33 decompress pass
571 19:52:50.345890 ERROR: Error initializing runtime service opteed_fast
572 19:52:51.578782
573 19:52:51.579368
574 19:52:51.587195 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 19:52:51.587660
576 19:52:51.588111 Model: Libre Computer AML-A311D-CC Alta
577 19:52:51.795516 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 19:52:51.819010 DRAM: 2 GiB (effective 3.8 GiB)
579 19:52:51.961848 Core: 408 devices, 31 uclasses, devicetree: separate
580 19:52:51.967782 WDT: Not starting watchdog@f0d0
581 19:52:52.000083 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 19:52:52.012439 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 19:52:52.017492 ** Bad device specification mmc 0 **
584 19:52:52.027695 Card did not respond to voltage select! : -110
585 19:52:52.035365 ** Bad device specification mmc 0 **
586 19:52:52.035818 Couldn't find partition mmc 0
587 19:52:52.043732 Card did not respond to voltage select! : -110
588 19:52:52.049222 ** Bad device specification mmc 0 **
589 19:52:52.049667 Couldn't find partition mmc 0
590 19:52:52.054337 Error: could not access storage.
591 19:52:52.396921 Net: eth0: ethernet@ff3f0000
592 19:52:52.397513 starting USB...
593 19:52:52.648738 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 19:52:52.649328 Starting the controller
595 19:52:52.655644 USB XHCI 1.10
596 19:52:54.369728 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 19:52:54.370150 bl2_stage_init 0x01
598 19:52:54.370381 bl2_stage_init 0x81
599 19:52:54.375324 hw id: 0x0000 - pwm id 0x01
600 19:52:54.375736 bl2_stage_init 0xc1
601 19:52:54.376107 bl2_stage_init 0x02
602 19:52:54.376631
603 19:52:54.380995 L0:00000000
604 19:52:54.381450 L1:20000703
605 19:52:54.381865 L2:00008067
606 19:52:54.382273 L3:14000000
607 19:52:54.383699 B2:00402000
608 19:52:54.384224 B1:e0f83180
609 19:52:54.384641
610 19:52:54.385051 TE: 58167
611 19:52:54.385458
612 19:52:54.394807 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 19:52:54.395275
614 19:52:54.395692 Board ID = 1
615 19:52:54.396134 Set A53 clk to 24M
616 19:52:54.396543 Set A73 clk to 24M
617 19:52:54.400361 Set clk81 to 24M
618 19:52:54.400809 A53 clk: 1200 MHz
619 19:52:54.401217 A73 clk: 1200 MHz
620 19:52:54.403959 CLK81: 166.6M
621 19:52:54.404434 smccc: 00012abd
622 19:52:54.409651 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 19:52:54.415189 board id: 1
624 19:52:54.420501 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 19:52:54.430882 fw parse done
626 19:52:54.436847 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 19:52:54.479635 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 19:52:54.490374 PIEI prepare done
629 19:52:54.490855 fastboot data load
630 19:52:54.491279 fastboot data verify
631 19:52:54.495920 verify result: 266
632 19:52:54.501565 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 19:52:54.502041 LPDDR4 probe
634 19:52:54.502452 ddr clk to 1584MHz
635 19:52:54.509633 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 19:52:54.546872
637 19:52:54.547349 dmc_version 0001
638 19:52:54.553583 Check phy result
639 19:52:54.559383 INFO : End of CA training
640 19:52:54.559857 INFO : End of initialization
641 19:52:54.565008 INFO : Training has run successfully!
642 19:52:54.565470 Check phy result
643 19:52:54.570549 INFO : End of initialization
644 19:52:54.571003 INFO : End of read enable training
645 19:52:54.573869 INFO : End of fine write leveling
646 19:52:54.579541 INFO : End of Write leveling coarse delay
647 19:52:54.585108 INFO : Training has run successfully!
648 19:52:54.585567 Check phy result
649 19:52:54.585979 INFO : End of initialization
650 19:52:54.590683 INFO : End of read dq deskew training
651 19:52:54.596321 INFO : End of MPR read delay center optimization
652 19:52:54.596779 INFO : End of write delay center optimization
653 19:52:54.601917 INFO : End of read delay center optimization
654 19:52:54.607556 INFO : End of max read latency training
655 19:52:54.608045 INFO : Training has run successfully!
656 19:52:54.613160 1D training succeed
657 19:52:54.619074 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 19:52:54.666682 Check phy result
659 19:52:54.667142 INFO : End of initialization
660 19:52:54.688991 INFO : End of 2D read delay Voltage center optimization
661 19:52:54.709088 INFO : End of 2D read delay Voltage center optimization
662 19:52:54.761052 INFO : End of 2D write delay Voltage center optimization
663 19:52:54.810270 INFO : End of 2D write delay Voltage center optimization
664 19:52:54.815713 INFO : Training has run successfully!
665 19:52:54.816219
666 19:52:54.816648 channel==0
667 19:52:54.821373 RxClkDly_Margin_A0==88 ps 9
668 19:52:54.821834 TxDqDly_Margin_A0==98 ps 10
669 19:52:54.824667 RxClkDly_Margin_A1==88 ps 9
670 19:52:54.825119 TxDqDly_Margin_A1==88 ps 9
671 19:52:54.830276 TrainedVREFDQ_A0==74
672 19:52:54.830732 TrainedVREFDQ_A1==74
673 19:52:54.831150 VrefDac_Margin_A0==25
674 19:52:54.835853 DeviceVref_Margin_A0==40
675 19:52:54.836357 VrefDac_Margin_A1==24
676 19:52:54.841405 DeviceVref_Margin_A1==40
677 19:52:54.841858
678 19:52:54.842274
679 19:52:54.842681 channel==1
680 19:52:54.843076 RxClkDly_Margin_A0==98 ps 10
681 19:52:54.846945 TxDqDly_Margin_A0==88 ps 9
682 19:52:54.847415 RxClkDly_Margin_A1==88 ps 9
683 19:52:54.852654 TxDqDly_Margin_A1==88 ps 9
684 19:52:54.853129 TrainedVREFDQ_A0==77
685 19:52:54.853550 TrainedVREFDQ_A1==77
686 19:52:54.858189 VrefDac_Margin_A0==22
687 19:52:54.858647 DeviceVref_Margin_A0==37
688 19:52:54.863782 VrefDac_Margin_A1==24
689 19:52:54.864273 DeviceVref_Margin_A1==37
690 19:52:54.864686
691 19:52:54.869385 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 19:52:54.869841
693 19:52:54.897507 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
694 19:52:54.903167 2D training succeed
695 19:52:54.908779 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 19:52:54.909333 auto size-- 65535DDR cs0 size: 2048MB
697 19:52:54.914373 DDR cs1 size: 2048MB
698 19:52:54.914911 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 19:52:54.919962 cs0 DataBus test pass
700 19:52:54.920537 cs1 DataBus test pass
701 19:52:54.920963 cs0 AddrBus test pass
702 19:52:54.925551 cs1 AddrBus test pass
703 19:52:54.926086
704 19:52:54.926513 100bdlr_step_size ps== 420
705 19:52:54.926936 result report
706 19:52:54.931135 boot times 0Enable ddr reg access
707 19:52:54.938740 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 19:52:54.952144 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 19:52:55.524293 0.0;M3 CHK:0;cm4_sp_mode 0
710 19:52:55.524923 MVN_1=0x00000000
711 19:52:55.529805 MVN_2=0x00000000
712 19:52:55.535488 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 19:52:55.536070 OPS=0x10
714 19:52:55.536488 ring efuse init
715 19:52:55.536879 chipver efuse init
716 19:52:55.543675 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 19:52:55.544210 [0.018961 Inits done]
718 19:52:55.551356 secure task start!
719 19:52:55.551828 high task start!
720 19:52:55.552264 low task start!
721 19:52:55.552653 run into bl31
722 19:52:55.557880 NOTICE: BL31: v1.3(release):4fc40b1
723 19:52:55.565796 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 19:52:55.566276 NOTICE: BL31: G12A normal boot!
725 19:52:55.591099 NOTICE: BL31: BL33 decompress pass
726 19:52:55.596945 ERROR: Error initializing runtime service opteed_fast
727 19:52:56.829760
728 19:52:56.830386
729 19:52:56.838241 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 19:52:56.838790
731 19:52:56.839221 Model: Libre Computer AML-A311D-CC Alta
732 19:52:57.046733 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 19:52:57.070070 DRAM: 2 GiB (effective 3.8 GiB)
734 19:52:57.212962 Core: 408 devices, 31 uclasses, devicetree: separate
735 19:52:57.218897 WDT: Not starting watchdog@f0d0
736 19:52:57.251182 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 19:52:57.263489 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 19:52:57.268579 ** Bad device specification mmc 0 **
739 19:52:57.278938 Card did not respond to voltage select! : -110
740 19:52:57.286522 ** Bad device specification mmc 0 **
741 19:52:57.287007 Couldn't find partition mmc 0
742 19:52:57.294939 Card did not respond to voltage select! : -110
743 19:52:57.300374 ** Bad device specification mmc 0 **
744 19:52:57.300851 Couldn't find partition mmc 0
745 19:52:57.305491 Error: could not access storage.
746 19:52:57.647843 Net: eth0: ethernet@ff3f0000
747 19:52:57.648466 starting USB...
748 19:52:57.899799 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 19:52:57.900456 Starting the controller
750 19:52:57.906738 USB XHCI 1.10
751 19:53:00.071253 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
752 19:53:00.071697 bl2_stage_init 0x81
753 19:53:00.076665 hw id: 0x0000 - pwm id 0x01
754 19:53:00.077138 bl2_stage_init 0xc1
755 19:53:00.077474 bl2_stage_init 0x02
756 19:53:00.077720
757 19:53:00.082604 L0:00000000
758 19:53:00.082963 L1:20000703
759 19:53:00.083179 L2:00008067
760 19:53:00.083382 L3:14000000
761 19:53:00.083582 B2:00402000
762 19:53:00.088035 B1:e0f83180
763 19:53:00.088547
764 19:53:00.088890 TE: 58150
765 19:53:00.089220
766 19:53:00.093502 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
767 19:53:00.094036
768 19:53:00.094396 Board ID = 1
769 19:53:00.098986 Set A53 clk to 24M
770 19:53:00.099528 Set A73 clk to 24M
771 19:53:00.099782 Set clk81 to 24M
772 19:53:00.104698 A53 clk: 1200 MHz
773 19:53:00.105245 A73 clk: 1200 MHz
774 19:53:00.105503 CLK81: 166.6M
775 19:53:00.105711 smccc: 00012aac
776 19:53:00.110304 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
777 19:53:00.115866 board id: 1
778 19:53:00.121825 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
779 19:53:00.132371 fw parse done
780 19:53:00.138259 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
781 19:53:00.180786 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
782 19:53:00.192023 PIEI prepare done
783 19:53:00.192734 fastboot data load
784 19:53:00.193287 fastboot data verify
785 19:53:00.197593 verify result: 266
786 19:53:00.203137 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
787 19:53:00.203766 LPDDR4 probe
788 19:53:00.204355 ddr clk to 1584MHz
789 19:53:00.210882 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
790 19:53:00.248294
791 19:53:00.249044 dmc_version 0001
792 19:53:00.254908 Check phy result
793 19:53:00.260749 INFO : End of CA training
794 19:53:00.261371 INFO : End of initialization
795 19:53:00.266463 INFO : Training has run successfully!
796 19:53:00.267088 Check phy result
797 19:53:00.271917 INFO : End of initialization
798 19:53:00.272553 INFO : End of read enable training
799 19:53:00.275239 INFO : End of fine write leveling
800 19:53:00.280755 INFO : End of Write leveling coarse delay
801 19:53:00.286801 INFO : Training has run successfully!
802 19:53:00.287419 Check phy result
803 19:53:00.287947 INFO : End of initialization
804 19:53:00.292040 INFO : End of read dq deskew training
805 19:53:00.297624 INFO : End of MPR read delay center optimization
806 19:53:00.298227 INFO : End of write delay center optimization
807 19:53:00.303184 INFO : End of read delay center optimization
808 19:53:00.308825 INFO : End of max read latency training
809 19:53:00.309415 INFO : Training has run successfully!
810 19:53:00.314447 1D training succeed
811 19:53:00.320308 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
812 19:53:00.367935 Check phy result
813 19:53:00.368691 INFO : End of initialization
814 19:53:00.389698 INFO : End of 2D read delay Voltage center optimization
815 19:53:00.409970 INFO : End of 2D read delay Voltage center optimization
816 19:53:00.462366 INFO : End of 2D write delay Voltage center optimization
817 19:53:00.511310 INFO : End of 2D write delay Voltage center optimization
818 19:53:00.516893 INFO : Training has run successfully!
819 19:53:00.517526
820 19:53:00.518075 channel==0
821 19:53:00.522573 RxClkDly_Margin_A0==88 ps 9
822 19:53:00.523176 TxDqDly_Margin_A0==98 ps 10
823 19:53:00.528185 RxClkDly_Margin_A1==88 ps 9
824 19:53:00.528803 TxDqDly_Margin_A1==98 ps 10
825 19:53:00.529379 TrainedVREFDQ_A0==74
826 19:53:00.533661 TrainedVREFDQ_A1==76
827 19:53:00.534360 VrefDac_Margin_A0==25
828 19:53:00.534913 DeviceVref_Margin_A0==40
829 19:53:00.539834 VrefDac_Margin_A1==25
830 19:53:00.540519 DeviceVref_Margin_A1==38
831 19:53:00.541027
832 19:53:00.541532
833 19:53:00.544939 channel==1
834 19:53:00.545583 RxClkDly_Margin_A0==98 ps 10
835 19:53:00.546209 TxDqDly_Margin_A0==98 ps 10
836 19:53:00.550578 RxClkDly_Margin_A1==98 ps 10
837 19:53:00.551271 TxDqDly_Margin_A1==88 ps 9
838 19:53:00.556098 TrainedVREFDQ_A0==77
839 19:53:00.556694 TrainedVREFDQ_A1==77
840 19:53:00.557222 VrefDac_Margin_A0==22
841 19:53:00.561693 DeviceVref_Margin_A0==37
842 19:53:00.562260 VrefDac_Margin_A1==22
843 19:53:00.567616 DeviceVref_Margin_A1==37
844 19:53:00.568237
845 19:53:00.568754 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
846 19:53:00.572803
847 19:53:00.601008 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
848 19:53:00.601772 2D training succeed
849 19:53:00.606463 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
850 19:53:00.612089 auto size-- 65535DDR cs0 size: 2048MB
851 19:53:00.612664 DDR cs1 size: 2048MB
852 19:53:00.617697 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
853 19:53:00.618266 cs0 DataBus test pass
854 19:53:00.623204 cs1 DataBus test pass
855 19:53:00.623763 cs0 AddrBus test pass
856 19:53:00.624303 cs1 AddrBus test pass
857 19:53:00.624804
858 19:53:00.629287 100bdlr_step_size ps== 420
859 19:53:00.629879 result report
860 19:53:00.634470 boot times 0Enable ddr reg access
861 19:53:00.639878 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
862 19:53:00.653382 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
863 19:53:01.227206 0.0;M3 CHK:0;cm4_sp_mode 0
864 19:53:01.228043 MVN_1=0x00000000
865 19:53:01.232657 MVN_2=0x00000000
866 19:53:01.238373 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
867 19:53:01.238968 OPS=0x10
868 19:53:01.239514 ring efuse init
869 19:53:01.240080 chipver efuse init
870 19:53:01.246606 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
871 19:53:01.247225 [0.018961 Inits done]
872 19:53:01.254296 secure task start!
873 19:53:01.254941 high task start!
874 19:53:01.255478 low task start!
875 19:53:01.256026 run into bl31
876 19:53:01.261114 NOTICE: BL31: v1.3(release):4fc40b1
877 19:53:01.268779 NOTICE: BL31: Built : 15:58:17, May 22 2019
878 19:53:01.269385 NOTICE: BL31: G12A normal boot!
879 19:53:01.294076 NOTICE: BL31: BL33 decompress pass
880 19:53:01.299768 ERROR: Error initializing runtime service opteed_fast
881 19:53:02.532730
882 19:53:02.533549
883 19:53:02.541007 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
884 19:53:02.541623
885 19:53:02.542175 Model: Libre Computer AML-A311D-CC Alta
886 19:53:02.750461 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
887 19:53:02.772874 DRAM: 2 GiB (effective 3.8 GiB)
888 19:53:02.915955 Core: 408 devices, 31 uclasses, devicetree: separate
889 19:53:02.921817 WDT: Not starting watchdog@f0d0
890 19:53:02.953913 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
891 19:53:02.966403 Loading Environment from FAT... Card did not respond to voltage select! : -110
892 19:53:02.971339 ** Bad device specification mmc 0 **
893 19:53:02.981641 Card did not respond to voltage select! : -110
894 19:53:02.989289 ** Bad device specification mmc 0 **
895 19:53:02.989748 Couldn't find partition mmc 0
896 19:53:02.997551 Card did not respond to voltage select! : -110
897 19:53:03.003061 ** Bad device specification mmc 0 **
898 19:53:03.003514 Couldn't find partition mmc 0
899 19:53:03.008142 Error: could not access storage.
900 19:53:03.350919 Net: eth0: ethernet@ff3f0000
901 19:53:03.351527 starting USB...
902 19:53:03.602625 Bus usb@ff500000: Register 3000140 NbrPorts 3
903 19:53:03.603230 Starting the controller
904 19:53:03.609521 USB XHCI 1.10
905 19:53:05.163668 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
906 19:53:05.171733 scanning usb for storage devices... 0 Storage Device(s) found
908 19:53:05.223323 Hit any key to stop autoboot: 1
909 19:53:05.224181 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
910 19:53:05.224774 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
911 19:53:05.225246 Setting prompt string to ['=>']
912 19:53:05.225726 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
913 19:53:05.239362 0
914 19:53:05.240310 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
915 19:53:05.240821 Sending with 10 millisecond of delay
917 19:53:06.377299 => setenv autoload no
918 19:53:06.387913 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
919 19:53:06.390766 setenv autoload no
920 19:53:06.391348 Sending with 10 millisecond of delay
922 19:53:08.189800 => setenv initrd_high 0xffffffff
923 19:53:08.200648 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
924 19:53:08.201538 setenv initrd_high 0xffffffff
925 19:53:08.202284 Sending with 10 millisecond of delay
927 19:53:09.819651 => setenv fdt_high 0xffffffff
928 19:53:09.830541 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
929 19:53:09.831514 setenv fdt_high 0xffffffff
930 19:53:09.832310 Sending with 10 millisecond of delay
932 19:53:10.124344 => dhcp
933 19:53:10.134915 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
934 19:53:10.135640 dhcp
935 19:53:10.136172 Speed: 1000, full duplex
936 19:53:10.136659 BOOTP broadcast 1
937 19:53:10.256375 DHCP client bound to address 192.168.6.27 (120 ms)
938 19:53:10.257077 Sending with 10 millisecond of delay
940 19:53:11.934974 => setenv serverip 192.168.6.2
941 19:53:11.945545 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
942 19:53:11.946070 setenv serverip 192.168.6.2
943 19:53:11.946528 Sending with 10 millisecond of delay
945 19:53:15.669774 => tftpboot 0x01080000 936392/tftp-deploy-edgplj6a/kernel/uImage
946 19:53:15.680345 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
947 19:53:15.680873 tftpboot 0x01080000 936392/tftp-deploy-edgplj6a/kernel/uImage
948 19:53:15.681113 Speed: 1000, full duplex
949 19:53:15.681323 Using ethernet@ff3f0000 device
950 19:53:15.683152 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
951 19:53:15.688789 Filename '936392/tftp-deploy-edgplj6a/kernel/uImage'.
952 19:53:15.692724 Load address: 0x1080000
953 19:53:18.581019 Loading: *################################################## 43.6 MiB
954 19:53:18.582004 15.1 MiB/s
955 19:53:18.582307 done
956 19:53:18.585493 Bytes transferred = 45713984 (2b98a40 hex)
957 19:53:18.586094 Sending with 10 millisecond of delay
959 19:53:23.278348 => tftpboot 0x08000000 936392/tftp-deploy-edgplj6a/ramdisk/ramdisk.cpio.gz.uboot
960 19:53:23.289274 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
961 19:53:23.289978 tftpboot 0x08000000 936392/tftp-deploy-edgplj6a/ramdisk/ramdisk.cpio.gz.uboot
962 19:53:23.290296 Speed: 1000, full duplex
963 19:53:23.290561 Using ethernet@ff3f0000 device
964 19:53:23.291676 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
965 19:53:23.303504 Filename '936392/tftp-deploy-edgplj6a/ramdisk/ramdisk.cpio.gz.uboot'.
966 19:53:23.303908 Load address: 0x8000000
967 19:53:30.588444 Loading: *#################T ################################ UDP wrong checksum 00000005 00001cfd
968 19:53:35.588345 T UDP wrong checksum 00000005 00001cfd
969 19:53:45.592485 T T UDP wrong checksum 00000005 00001cfd
970 19:54:05.596685 T T T T UDP wrong checksum 00000005 00001cfd
971 19:54:11.272390 T UDP wrong checksum 000000ff 00000053
972 19:54:11.312971 UDP wrong checksum 000000ff 00009945
973 19:54:20.600465 T
974 19:54:20.600868 Retry count exceeded; starting again
976 19:54:20.601876 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
979 19:54:20.603041 end: 2.4 uboot-commands (duration 00:01:47) [common]
981 19:54:20.603738 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
983 19:54:20.604362 end: 2 uboot-action (duration 00:01:47) [common]
985 19:54:20.605168 Cleaning after the job
986 19:54:20.605482 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936392/tftp-deploy-edgplj6a/ramdisk
987 19:54:20.606493 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936392/tftp-deploy-edgplj6a/kernel
988 19:54:20.613393 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936392/tftp-deploy-edgplj6a/dtb
989 19:54:20.614299 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936392/tftp-deploy-edgplj6a/modules
990 19:54:20.617911 start: 4.1 power-off (timeout 00:00:30) [common]
991 19:54:20.618620 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
992 19:54:20.653497 >> OK - accepted request
993 19:54:20.655567 Returned 0 in 0 seconds
994 19:54:20.756512 end: 4.1 power-off (duration 00:00:00) [common]
996 19:54:20.757781 start: 4.2 read-feedback (timeout 00:10:00) [common]
997 19:54:20.758562 Listened to connection for namespace 'common' for up to 1s
998 19:54:21.759675 Finalising connection for namespace 'common'
999 19:54:21.761464 Disconnecting from shell: Finalise
1000 19:54:21.761828 =>
1001 19:54:21.862619 end: 4.2 read-feedback (duration 00:00:01) [common]
1002 19:54:21.863367 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/936392
1003 19:54:22.143515 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/936392
1004 19:54:22.144165 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.