Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:11:56.624531 lava-dispatcher, installed at version: 2024.01
2 20:11:56.625337 start: 0 validate
3 20:11:56.625808 Start time: 2024-11-04 20:11:56.625777+00:00 (UTC)
4 20:11:56.626354 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:11:56.626883 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 20:11:56.666493 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:11:56.667065 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-5-g557329bcecc2%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 20:11:56.694834 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:11:56.695499 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-5-g557329bcecc2%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 20:11:57.741344 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:11:57.741851 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-5-g557329bcecc2%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 20:11:57.776127 validate duration: 1.15
14 20:11:57.776971 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:11:57.777290 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:11:57.777583 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:11:57.778162 Not decompressing ramdisk as can be used compressed.
18 20:11:57.778582 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 20:11:57.778844 saving as /var/lib/lava/dispatcher/tmp/936439/tftp-deploy-mxtyl1th/ramdisk/rootfs.cpio.gz
20 20:11:57.779111 total size: 8181887 (7 MB)
21 20:11:57.813077 progress 0 % (0 MB)
22 20:11:57.824188 progress 5 % (0 MB)
23 20:11:57.835494 progress 10 % (0 MB)
24 20:11:57.844641 progress 15 % (1 MB)
25 20:11:57.850278 progress 20 % (1 MB)
26 20:11:57.856573 progress 25 % (1 MB)
27 20:11:57.862060 progress 30 % (2 MB)
28 20:11:57.868022 progress 35 % (2 MB)
29 20:11:57.873436 progress 40 % (3 MB)
30 20:11:57.879181 progress 45 % (3 MB)
31 20:11:57.884711 progress 50 % (3 MB)
32 20:11:57.890540 progress 55 % (4 MB)
33 20:11:57.895930 progress 60 % (4 MB)
34 20:11:57.901722 progress 65 % (5 MB)
35 20:11:57.907146 progress 70 % (5 MB)
36 20:11:57.913018 progress 75 % (5 MB)
37 20:11:57.918305 progress 80 % (6 MB)
38 20:11:57.924110 progress 85 % (6 MB)
39 20:11:57.929596 progress 90 % (7 MB)
40 20:11:57.935208 progress 95 % (7 MB)
41 20:11:57.940515 progress 100 % (7 MB)
42 20:11:57.941166 7 MB downloaded in 0.16 s (48.16 MB/s)
43 20:11:57.941712 end: 1.1.1 http-download (duration 00:00:00) [common]
45 20:11:57.942588 end: 1.1 download-retry (duration 00:00:00) [common]
46 20:11:57.942876 start: 1.2 download-retry (timeout 00:10:00) [common]
47 20:11:57.943145 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 20:11:57.943608 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-5-g557329bcecc2/arm64/defconfig/gcc-12/kernel/Image
49 20:11:57.943854 saving as /var/lib/lava/dispatcher/tmp/936439/tftp-deploy-mxtyl1th/kernel/Image
50 20:11:57.944097 total size: 45713920 (43 MB)
51 20:11:57.944308 No compression specified
52 20:11:57.983414 progress 0 % (0 MB)
53 20:11:58.012439 progress 5 % (2 MB)
54 20:11:58.041618 progress 10 % (4 MB)
55 20:11:58.071042 progress 15 % (6 MB)
56 20:11:58.100598 progress 20 % (8 MB)
57 20:11:58.129465 progress 25 % (10 MB)
58 20:11:58.158690 progress 30 % (13 MB)
59 20:11:58.188409 progress 35 % (15 MB)
60 20:11:58.217776 progress 40 % (17 MB)
61 20:11:58.246925 progress 45 % (19 MB)
62 20:11:58.276522 progress 50 % (21 MB)
63 20:11:58.305883 progress 55 % (24 MB)
64 20:11:58.334797 progress 60 % (26 MB)
65 20:11:58.363264 progress 65 % (28 MB)
66 20:11:58.392572 progress 70 % (30 MB)
67 20:11:58.423219 progress 75 % (32 MB)
68 20:11:58.452637 progress 80 % (34 MB)
69 20:11:58.481548 progress 85 % (37 MB)
70 20:11:58.510928 progress 90 % (39 MB)
71 20:11:58.540521 progress 95 % (41 MB)
72 20:11:58.570642 progress 100 % (43 MB)
73 20:11:58.571240 43 MB downloaded in 0.63 s (69.52 MB/s)
74 20:11:58.571730 end: 1.2.1 http-download (duration 00:00:01) [common]
76 20:11:58.572595 end: 1.2 download-retry (duration 00:00:01) [common]
77 20:11:58.572876 start: 1.3 download-retry (timeout 00:09:59) [common]
78 20:11:58.573140 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 20:11:58.573621 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-5-g557329bcecc2/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 20:11:58.573904 saving as /var/lib/lava/dispatcher/tmp/936439/tftp-deploy-mxtyl1th/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 20:11:58.574110 total size: 53209 (0 MB)
82 20:11:58.574320 No compression specified
83 20:11:58.613738 progress 61 % (0 MB)
84 20:11:58.614659 progress 100 % (0 MB)
85 20:11:58.615225 0 MB downloaded in 0.04 s (1.23 MB/s)
86 20:11:58.615747 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:11:58.616663 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:11:58.616929 start: 1.4 download-retry (timeout 00:09:59) [common]
90 20:11:58.617195 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 20:11:58.617687 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-5-g557329bcecc2/arm64/defconfig/gcc-12/modules.tar.xz
92 20:11:58.617965 saving as /var/lib/lava/dispatcher/tmp/936439/tftp-deploy-mxtyl1th/modules/modules.tar
93 20:11:58.618170 total size: 11612232 (11 MB)
94 20:11:58.618381 Using unxz to decompress xz
95 20:11:58.657553 progress 0 % (0 MB)
96 20:11:58.723309 progress 5 % (0 MB)
97 20:11:58.797694 progress 10 % (1 MB)
98 20:11:58.895619 progress 15 % (1 MB)
99 20:11:58.988654 progress 20 % (2 MB)
100 20:11:59.068046 progress 25 % (2 MB)
101 20:11:59.144341 progress 30 % (3 MB)
102 20:11:59.223500 progress 35 % (3 MB)
103 20:11:59.295659 progress 40 % (4 MB)
104 20:11:59.371308 progress 45 % (5 MB)
105 20:11:59.455015 progress 50 % (5 MB)
106 20:11:59.531889 progress 55 % (6 MB)
107 20:11:59.617103 progress 60 % (6 MB)
108 20:11:59.697285 progress 65 % (7 MB)
109 20:11:59.777710 progress 70 % (7 MB)
110 20:11:59.854819 progress 75 % (8 MB)
111 20:11:59.938252 progress 80 % (8 MB)
112 20:12:00.018454 progress 85 % (9 MB)
113 20:12:00.096814 progress 90 % (9 MB)
114 20:12:00.174533 progress 95 % (10 MB)
115 20:12:00.251465 progress 100 % (11 MB)
116 20:12:00.263329 11 MB downloaded in 1.65 s (6.73 MB/s)
117 20:12:00.263901 end: 1.4.1 http-download (duration 00:00:02) [common]
119 20:12:00.265527 end: 1.4 download-retry (duration 00:00:02) [common]
120 20:12:00.266050 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 20:12:00.266561 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 20:12:00.267044 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:12:00.267536 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 20:12:00.268513 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__
125 20:12:00.269342 makedir: /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin
126 20:12:00.269971 makedir: /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/tests
127 20:12:00.270577 makedir: /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/results
128 20:12:00.271181 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-add-keys
129 20:12:00.272151 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-add-sources
130 20:12:00.273082 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-background-process-start
131 20:12:00.274001 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-background-process-stop
132 20:12:00.274989 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-common-functions
133 20:12:00.275894 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-echo-ipv4
134 20:12:00.276848 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-install-packages
135 20:12:00.277724 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-installed-packages
136 20:12:00.278589 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-os-build
137 20:12:00.279457 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-probe-channel
138 20:12:00.280363 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-probe-ip
139 20:12:00.281249 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-target-ip
140 20:12:00.282133 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-target-mac
141 20:12:00.283014 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-target-storage
142 20:12:00.283944 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-test-case
143 20:12:00.284874 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-test-event
144 20:12:00.285747 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-test-feedback
145 20:12:00.286610 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-test-raise
146 20:12:00.287493 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-test-reference
147 20:12:00.288441 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-test-runner
148 20:12:00.289349 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-test-set
149 20:12:00.290234 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-test-shell
150 20:12:00.291117 Updating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-install-packages (oe)
151 20:12:00.292071 Updating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/bin/lava-installed-packages (oe)
152 20:12:00.292882 Creating /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/environment
153 20:12:00.293582 LAVA metadata
154 20:12:00.294055 - LAVA_JOB_ID=936439
155 20:12:00.294477 - LAVA_DISPATCHER_IP=192.168.6.2
156 20:12:00.295122 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 20:12:00.296903 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 20:12:00.297480 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 20:12:00.297887 skipped lava-vland-overlay
160 20:12:00.298370 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 20:12:00.298872 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 20:12:00.299291 skipped lava-multinode-overlay
163 20:12:00.299769 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 20:12:00.300304 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 20:12:00.300772 Loading test definitions
166 20:12:00.301308 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 20:12:00.301738 Using /lava-936439 at stage 0
168 20:12:00.303574 uuid=936439_1.5.2.4.1 testdef=None
169 20:12:00.303891 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 20:12:00.304196 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 20:12:00.305993 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 20:12:00.306815 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 20:12:00.309164 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 20:12:00.310017 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 20:12:00.312211 runner path: /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/0/tests/0_dmesg test_uuid 936439_1.5.2.4.1
178 20:12:00.312848 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 20:12:00.313619 Creating lava-test-runner.conf files
181 20:12:00.313822 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/936439/lava-overlay-r66fqc__/lava-936439/0 for stage 0
182 20:12:00.314161 - 0_dmesg
183 20:12:00.314508 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 20:12:00.314786 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 20:12:00.338432 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 20:12:00.338813 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 20:12:00.339073 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 20:12:00.339337 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 20:12:00.339598 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 20:12:01.360789 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 20:12:01.361263 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 20:12:01.361510 extracting modules file /var/lib/lava/dispatcher/tmp/936439/tftp-deploy-mxtyl1th/modules/modules.tar to /var/lib/lava/dispatcher/tmp/936439/extract-overlay-ramdisk-_o149f6r/ramdisk
193 20:12:02.740161 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 20:12:02.740631 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 20:12:02.740906 [common] Applying overlay /var/lib/lava/dispatcher/tmp/936439/compress-overlay-eqmr7vxa/overlay-1.5.2.5.tar.gz to ramdisk
196 20:12:02.741116 [common] Applying overlay /var/lib/lava/dispatcher/tmp/936439/compress-overlay-eqmr7vxa/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/936439/extract-overlay-ramdisk-_o149f6r/ramdisk
197 20:12:02.772138 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 20:12:02.772560 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 20:12:02.772826 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 20:12:02.773052 Converting downloaded kernel to a uImage
201 20:12:02.773351 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/936439/tftp-deploy-mxtyl1th/kernel/Image /var/lib/lava/dispatcher/tmp/936439/tftp-deploy-mxtyl1th/kernel/uImage
202 20:12:03.255068 output: Image Name:
203 20:12:03.255500 output: Created: Mon Nov 4 20:12:02 2024
204 20:12:03.255724 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 20:12:03.255941 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 20:12:03.256201 output: Load Address: 01080000
207 20:12:03.256411 output: Entry Point: 01080000
208 20:12:03.256619 output:
209 20:12:03.256964 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 20:12:03.257265 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 20:12:03.257558 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 20:12:03.257828 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 20:12:03.258099 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 20:12:03.258372 Building ramdisk /var/lib/lava/dispatcher/tmp/936439/extract-overlay-ramdisk-_o149f6r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/936439/extract-overlay-ramdisk-_o149f6r/ramdisk
215 20:12:06.122602 >> 181607 blocks
216 20:12:14.644170 Adding RAMdisk u-boot header.
217 20:12:14.644880 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/936439/extract-overlay-ramdisk-_o149f6r/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/936439/extract-overlay-ramdisk-_o149f6r/ramdisk.cpio.gz.uboot
218 20:12:14.940263 output: Image Name:
219 20:12:14.940689 output: Created: Mon Nov 4 20:12:14 2024
220 20:12:14.940896 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 20:12:14.941097 output: Data Size: 26061877 Bytes = 25451.05 KiB = 24.85 MiB
222 20:12:14.941294 output: Load Address: 00000000
223 20:12:14.941490 output: Entry Point: 00000000
224 20:12:14.941683 output:
225 20:12:14.942330 rename /var/lib/lava/dispatcher/tmp/936439/extract-overlay-ramdisk-_o149f6r/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/936439/tftp-deploy-mxtyl1th/ramdisk/ramdisk.cpio.gz.uboot
226 20:12:14.942742 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 20:12:14.943022 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 20:12:14.943293 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 20:12:14.943541 No LXC device requested
230 20:12:14.943791 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 20:12:14.944208 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 20:12:14.944766 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 20:12:14.945243 Checking files for TFTP limit of 4294967296 bytes.
234 20:12:14.948155 end: 1 tftp-deploy (duration 00:00:17) [common]
235 20:12:14.948777 start: 2 uboot-action (timeout 00:05:00) [common]
236 20:12:14.949344 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 20:12:14.949876 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 20:12:14.950415 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 20:12:14.950982 Using kernel file from prepare-kernel: 936439/tftp-deploy-mxtyl1th/kernel/uImage
240 20:12:14.951653 substitutions:
241 20:12:14.952127 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 20:12:14.952569 - {DTB_ADDR}: 0x01070000
243 20:12:14.953003 - {DTB}: 936439/tftp-deploy-mxtyl1th/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 20:12:14.953436 - {INITRD}: 936439/tftp-deploy-mxtyl1th/ramdisk/ramdisk.cpio.gz.uboot
245 20:12:14.953869 - {KERNEL_ADDR}: 0x01080000
246 20:12:14.954295 - {KERNEL}: 936439/tftp-deploy-mxtyl1th/kernel/uImage
247 20:12:14.954724 - {LAVA_MAC}: None
248 20:12:14.955190 - {PRESEED_CONFIG}: None
249 20:12:14.955621 - {PRESEED_LOCAL}: None
250 20:12:14.956068 - {RAMDISK_ADDR}: 0x08000000
251 20:12:14.956494 - {RAMDISK}: 936439/tftp-deploy-mxtyl1th/ramdisk/ramdisk.cpio.gz.uboot
252 20:12:14.956926 - {ROOT_PART}: None
253 20:12:14.957354 - {ROOT}: None
254 20:12:14.957780 - {SERVER_IP}: 192.168.6.2
255 20:12:14.958210 - {TEE_ADDR}: 0x83000000
256 20:12:14.958636 - {TEE}: None
257 20:12:14.959060 Parsed boot commands:
258 20:12:14.959472 - setenv autoload no
259 20:12:14.959894 - setenv initrd_high 0xffffffff
260 20:12:14.960347 - setenv fdt_high 0xffffffff
261 20:12:14.960770 - dhcp
262 20:12:14.961191 - setenv serverip 192.168.6.2
263 20:12:14.961613 - tftpboot 0x01080000 936439/tftp-deploy-mxtyl1th/kernel/uImage
264 20:12:14.962037 - tftpboot 0x08000000 936439/tftp-deploy-mxtyl1th/ramdisk/ramdisk.cpio.gz.uboot
265 20:12:14.962459 - tftpboot 0x01070000 936439/tftp-deploy-mxtyl1th/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 20:12:14.962881 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 20:12:14.963308 - bootm 0x01080000 0x08000000 0x01070000
268 20:12:14.963835 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 20:12:14.965456 start: 2.3 connect-device (timeout 00:05:00) [common]
271 20:12:14.965931 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 20:12:14.980466 Setting prompt string to ['lava-test: # ']
273 20:12:14.982035 end: 2.3 connect-device (duration 00:00:00) [common]
274 20:12:14.982676 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 20:12:14.983294 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 20:12:14.984074 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 20:12:14.985461 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 20:12:15.022352 >> OK - accepted request
279 20:12:15.024244 Returned 0 in 0 seconds
280 20:12:15.125418 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 20:12:15.127098 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 20:12:15.127704 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 20:12:15.128297 Setting prompt string to ['Hit any key to stop autoboot']
285 20:12:15.128793 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 20:12:15.130514 Trying 192.168.56.21...
287 20:12:15.131016 Connected to conserv1.
288 20:12:15.131473 Escape character is '^]'.
289 20:12:15.131933
290 20:12:15.132435 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 20:12:15.132898
292 20:12:22.641552 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 20:12:22.642205 bl2_stage_init 0x01
294 20:12:22.642659 bl2_stage_init 0x81
295 20:12:22.647182 hw id: 0x0000 - pwm id 0x01
296 20:12:22.647676 bl2_stage_init 0xc1
297 20:12:22.652774 bl2_stage_init 0x02
298 20:12:22.653313
299 20:12:22.653729 L0:00000000
300 20:12:22.654134 L1:00000703
301 20:12:22.654531 L2:00008067
302 20:12:22.654919 L3:15000000
303 20:12:22.658209 S1:00000000
304 20:12:22.658695 B2:20282000
305 20:12:22.659092 B1:a0f83180
306 20:12:22.659478
307 20:12:22.659867 TE: 68769
308 20:12:22.660305
309 20:12:22.663845 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 20:12:22.664342
311 20:12:22.669508 Board ID = 1
312 20:12:22.669970 Set cpu clk to 24M
313 20:12:22.670362 Set clk81 to 24M
314 20:12:22.674987 Use GP1_pll as DSU clk.
315 20:12:22.675440 DSU clk: 1200 Mhz
316 20:12:22.675833 CPU clk: 1200 MHz
317 20:12:22.680621 Set clk81 to 166.6M
318 20:12:22.686227 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 20:12:22.686692 board id: 1
320 20:12:22.693402 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 20:12:22.704254 fw parse done
322 20:12:22.710299 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 20:12:22.753302 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 20:12:22.764464 PIEI prepare done
325 20:12:22.764938 fastboot data load
326 20:12:22.765337 fastboot data verify
327 20:12:22.770027 verify result: 266
328 20:12:22.775680 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 20:12:22.776223 LPDDR4 probe
330 20:12:22.776619 ddr clk to 1584MHz
331 20:12:22.783727 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 20:12:22.821428
333 20:12:22.821967 dmc_version 0001
334 20:12:22.828441 Check phy result
335 20:12:22.834420 INFO : End of CA training
336 20:12:22.834886 INFO : End of initialization
337 20:12:22.840052 INFO : Training has run successfully!
338 20:12:22.840517 Check phy result
339 20:12:22.845649 INFO : End of initialization
340 20:12:22.846116 INFO : End of read enable training
341 20:12:22.848937 INFO : End of fine write leveling
342 20:12:22.854457 INFO : End of Write leveling coarse delay
343 20:12:22.860081 INFO : Training has run successfully!
344 20:12:22.860546 Check phy result
345 20:12:22.860942 INFO : End of initialization
346 20:12:22.865711 INFO : End of read dq deskew training
347 20:12:22.871309 INFO : End of MPR read delay center optimization
348 20:12:22.871779 INFO : End of write delay center optimization
349 20:12:22.876910 INFO : End of read delay center optimization
350 20:12:22.882438 INFO : End of max read latency training
351 20:12:22.882919 INFO : Training has run successfully!
352 20:12:22.888091 1D training succeed
353 20:12:22.894068 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 20:12:22.942482 Check phy result
355 20:12:22.942982 INFO : End of initialization
356 20:12:22.969713 INFO : End of 2D read delay Voltage center optimization
357 20:12:22.993858 INFO : End of 2D read delay Voltage center optimization
358 20:12:23.050611 INFO : End of 2D write delay Voltage center optimization
359 20:12:23.104442 INFO : End of 2D write delay Voltage center optimization
360 20:12:23.110098 INFO : Training has run successfully!
361 20:12:23.110560
362 20:12:23.110958 channel==0
363 20:12:23.115606 RxClkDly_Margin_A0==78 ps 8
364 20:12:23.116112 TxDqDly_Margin_A0==98 ps 10
365 20:12:23.121379 RxClkDly_Margin_A1==78 ps 8
366 20:12:23.121874 TxDqDly_Margin_A1==88 ps 9
367 20:12:23.122298 TrainedVREFDQ_A0==74
368 20:12:23.126911 TrainedVREFDQ_A1==74
369 20:12:23.127383 VrefDac_Margin_A0==24
370 20:12:23.127776 DeviceVref_Margin_A0==40
371 20:12:23.132471 VrefDac_Margin_A1==23
372 20:12:23.132951 DeviceVref_Margin_A1==40
373 20:12:23.133349
374 20:12:23.133742
375 20:12:23.134134 channel==1
376 20:12:23.138100 RxClkDly_Margin_A0==78 ps 8
377 20:12:23.138563 TxDqDly_Margin_A0==98 ps 10
378 20:12:23.143611 RxClkDly_Margin_A1==88 ps 9
379 20:12:23.144095 TxDqDly_Margin_A1==78 ps 8
380 20:12:23.149177 TrainedVREFDQ_A0==78
381 20:12:23.149638 TrainedVREFDQ_A1==75
382 20:12:23.150031 VrefDac_Margin_A0==22
383 20:12:23.154778 DeviceVref_Margin_A0==36
384 20:12:23.155245 VrefDac_Margin_A1==22
385 20:12:23.160441 DeviceVref_Margin_A1==39
386 20:12:23.160902
387 20:12:23.161300 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 20:12:23.161688
389 20:12:23.193927 soc_vref_reg_value 0x 00000019 00000018 00000017 00000016 00000018 00000015 00000017 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
390 20:12:23.194530 2D training succeed
391 20:12:23.199620 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 20:12:23.205169 auto size-- 65535DDR cs0 size: 2048MB
393 20:12:23.205656 DDR cs1 size: 2048MB
394 20:12:23.210797 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 20:12:23.211249 cs0 DataBus test pass
396 20:12:23.216329 cs1 DataBus test pass
397 20:12:23.216779 cs0 AddrBus test pass
398 20:12:23.217167 cs1 AddrBus test pass
399 20:12:23.217553
400 20:12:23.221991 100bdlr_step_size ps== 485
401 20:12:23.222461 result report
402 20:12:23.227588 boot times 0Enable ddr reg access
403 20:12:23.232770 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 20:12:23.246556 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 20:12:23.905282 bl2z: ptr: 05129330, size: 00001e40
406 20:12:23.914299 0.0;M3 CHK:0;cm4_sp_mode 0
407 20:12:23.914631 MVN_1=0x00000000
408 20:12:23.914847 MVN_2=0x00000000
409 20:12:23.925763 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 20:12:23.926110 OPS=0x04
411 20:12:23.926326 ring efuse init
412 20:12:23.928691 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 20:12:23.935126 [0.017354 Inits done]
414 20:12:23.935431 secure task start!
415 20:12:23.935647 high task start!
416 20:12:23.935863 low task start!
417 20:12:23.939420 run into bl31
418 20:12:23.948088 NOTICE: BL31: v1.3(release):4fc40b1
419 20:12:23.955864 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 20:12:23.956198 NOTICE: BL31: G12A normal boot!
421 20:12:23.971537 NOTICE: BL31: BL33 decompress pass
422 20:12:23.977260 ERROR: Error initializing runtime service opteed_fast
423 20:12:26.692898 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 20:12:26.693586 bl2_stage_init 0x01
425 20:12:26.694069 bl2_stage_init 0x81
426 20:12:26.698411 hw id: 0x0000 - pwm id 0x01
427 20:12:26.698941 bl2_stage_init 0xc1
428 20:12:26.704074 bl2_stage_init 0x02
429 20:12:26.704633
430 20:12:26.705078 L0:00000000
431 20:12:26.705564 L1:00000703
432 20:12:26.706027 L2:00008067
433 20:12:26.706453 L3:15000000
434 20:12:26.709634 S1:00000000
435 20:12:26.710112 B2:20282000
436 20:12:26.710545 B1:a0f83180
437 20:12:26.710971
438 20:12:26.711397 TE: 69109
439 20:12:26.711819
440 20:12:26.715225 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 20:12:26.715686
442 20:12:26.720805 Board ID = 1
443 20:12:26.721273 Set cpu clk to 24M
444 20:12:26.721702 Set clk81 to 24M
445 20:12:26.726422 Use GP1_pll as DSU clk.
446 20:12:26.726882 DSU clk: 1200 Mhz
447 20:12:26.727306 CPU clk: 1200 MHz
448 20:12:26.732030 Set clk81 to 166.6M
449 20:12:26.737640 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 20:12:26.738105 board id: 1
451 20:12:26.744800 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 20:12:26.755754 fw parse done
453 20:12:26.761710 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 20:12:26.804829 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 20:12:26.816050 PIEI prepare done
456 20:12:26.816603 fastboot data load
457 20:12:26.817044 fastboot data verify
458 20:12:26.821557 verify result: 266
459 20:12:26.827143 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 20:12:26.827605 LPDDR4 probe
461 20:12:26.828057 ddr clk to 1584MHz
462 20:12:26.835145 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 20:12:26.872857
464 20:12:26.873342 dmc_version 0001
465 20:12:26.879928 Check phy result
466 20:12:26.885906 INFO : End of CA training
467 20:12:26.886434 INFO : End of initialization
468 20:12:26.891490 INFO : Training has run successfully!
469 20:12:26.891968 Check phy result
470 20:12:26.897095 INFO : End of initialization
471 20:12:26.897576 INFO : End of read enable training
472 20:12:26.902710 INFO : End of fine write leveling
473 20:12:26.908322 INFO : End of Write leveling coarse delay
474 20:12:26.908867 INFO : Training has run successfully!
475 20:12:26.909325 Check phy result
476 20:12:26.913897 INFO : End of initialization
477 20:12:26.914388 INFO : End of read dq deskew training
478 20:12:26.919490 INFO : End of MPR read delay center optimization
479 20:12:26.925085 INFO : End of write delay center optimization
480 20:12:26.930718 INFO : End of read delay center optimization
481 20:12:26.931190 INFO : End of max read latency training
482 20:12:26.936288 INFO : Training has run successfully!
483 20:12:26.936759 1D training succeed
484 20:12:26.945497 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 20:12:26.993829 Check phy result
486 20:12:26.994382 INFO : End of initialization
487 20:12:27.021157 INFO : End of 2D read delay Voltage center optimization
488 20:12:27.045317 INFO : End of 2D read delay Voltage center optimization
489 20:12:27.102001 INFO : End of 2D write delay Voltage center optimization
490 20:12:27.156065 INFO : End of 2D write delay Voltage center optimization
491 20:12:27.161593 INFO : Training has run successfully!
492 20:12:27.162088
493 20:12:27.162537 channel==0
494 20:12:27.167173 RxClkDly_Margin_A0==78 ps 8
495 20:12:27.167683 TxDqDly_Margin_A0==98 ps 10
496 20:12:27.172777 RxClkDly_Margin_A1==88 ps 9
497 20:12:27.173090 TxDqDly_Margin_A1==98 ps 10
498 20:12:27.173328 TrainedVREFDQ_A0==76
499 20:12:27.178342 TrainedVREFDQ_A1==74
500 20:12:27.178634 VrefDac_Margin_A0==22
501 20:12:27.178875 DeviceVref_Margin_A0==38
502 20:12:27.184046 VrefDac_Margin_A1==22
503 20:12:27.184331 DeviceVref_Margin_A1==40
504 20:12:27.184576
505 20:12:27.184813
506 20:12:27.189575 channel==1
507 20:12:27.189858 RxClkDly_Margin_A0==88 ps 9
508 20:12:27.190099 TxDqDly_Margin_A0==98 ps 10
509 20:12:27.195100 RxClkDly_Margin_A1==78 ps 8
510 20:12:27.195377 TxDqDly_Margin_A1==78 ps 8
511 20:12:27.200698 TrainedVREFDQ_A0==78
512 20:12:27.200977 TrainedVREFDQ_A1==75
513 20:12:27.201217 VrefDac_Margin_A0==23
514 20:12:27.206295 DeviceVref_Margin_A0==36
515 20:12:27.206583 VrefDac_Margin_A1==21
516 20:12:27.211957 DeviceVref_Margin_A1==39
517 20:12:27.212279
518 20:12:27.212524 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 20:12:27.212764
520 20:12:27.245591 soc_vref_reg_value 0x 00000019 00000018 00000017 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
521 20:12:27.246220 2D training succeed
522 20:12:27.251170 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 20:12:27.256760 auto size-- 65535DDR cs0 size: 2048MB
524 20:12:27.257244 DDR cs1 size: 2048MB
525 20:12:27.262468 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 20:12:27.262951 cs0 DataBus test pass
527 20:12:27.268007 cs1 DataBus test pass
528 20:12:27.268493 cs0 AddrBus test pass
529 20:12:27.268938 cs1 AddrBus test pass
530 20:12:27.269375
531 20:12:27.273569 100bdlr_step_size ps== 471
532 20:12:27.274062 result report
533 20:12:27.279188 boot times 0Enable ddr reg access
534 20:12:27.284428 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 20:12:27.298302 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 20:12:27.957695 bl2z: ptr: 05129330, size: 00001e40
537 20:12:27.964157 0.0;M3 CHK:0;cm4_sp_mode 0
538 20:12:27.964446 MVN_1=0x00000000
539 20:12:27.964658 MVN_2=0x00000000
540 20:12:27.975657 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 20:12:27.976008 OPS=0x04
542 20:12:27.976243 ring efuse init
543 20:12:27.981258 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 20:12:27.981554 [0.017354 Inits done]
545 20:12:27.981771 secure task start!
546 20:12:27.988860 high task start!
547 20:12:27.989162 low task start!
548 20:12:27.989368 run into bl31
549 20:12:27.997439 NOTICE: BL31: v1.3(release):4fc40b1
550 20:12:28.005243 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 20:12:28.005555 NOTICE: BL31: G12A normal boot!
552 20:12:28.020856 NOTICE: BL31: BL33 decompress pass
553 20:12:28.026593 ERROR: Error initializing runtime service opteed_fast
554 20:12:29.393601 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 20:12:29.394190 bl2_stage_init 0x01
556 20:12:29.394612 bl2_stage_init 0x81
557 20:12:29.399251 hw id: 0x0000 - pwm id 0x01
558 20:12:29.399735 bl2_stage_init 0xc1
559 20:12:29.404719 bl2_stage_init 0x02
560 20:12:29.405193
561 20:12:29.405610 L0:00000000
562 20:12:29.406014 L1:00000703
563 20:12:29.406407 L2:00008067
564 20:12:29.406797 L3:15000000
565 20:12:29.410354 S1:00000000
566 20:12:29.410832 B2:20282000
567 20:12:29.411237 B1:a0f83180
568 20:12:29.411632
569 20:12:29.412063 TE: 70598
570 20:12:29.412464
571 20:12:29.415913 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 20:12:29.416423
573 20:12:29.421496 Board ID = 1
574 20:12:29.421973 Set cpu clk to 24M
575 20:12:29.422381 Set clk81 to 24M
576 20:12:29.427078 Use GP1_pll as DSU clk.
577 20:12:29.427548 DSU clk: 1200 Mhz
578 20:12:29.427955 CPU clk: 1200 MHz
579 20:12:29.432707 Set clk81 to 166.6M
580 20:12:29.438319 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 20:12:29.438790 board id: 1
582 20:12:29.445500 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 20:12:29.456354 fw parse done
584 20:12:29.462331 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 20:12:29.505445 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 20:12:29.516538 PIEI prepare done
587 20:12:29.517017 fastboot data load
588 20:12:29.517438 fastboot data verify
589 20:12:29.522120 verify result: 266
590 20:12:29.527741 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 20:12:29.528256 LPDDR4 probe
592 20:12:29.528667 ddr clk to 1584MHz
593 20:12:29.535746 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 20:12:29.573485
595 20:12:29.573995 dmc_version 0001
596 20:12:29.580500 Check phy result
597 20:12:29.586476 INFO : End of CA training
598 20:12:29.586952 INFO : End of initialization
599 20:12:29.592081 INFO : Training has run successfully!
600 20:12:29.592556 Check phy result
601 20:12:29.597656 INFO : End of initialization
602 20:12:29.598123 INFO : End of read enable training
603 20:12:29.603283 INFO : End of fine write leveling
604 20:12:29.608853 INFO : End of Write leveling coarse delay
605 20:12:29.609326 INFO : Training has run successfully!
606 20:12:29.609738 Check phy result
607 20:12:29.614507 INFO : End of initialization
608 20:12:29.614967 INFO : End of read dq deskew training
609 20:12:29.620080 INFO : End of MPR read delay center optimization
610 20:12:29.625636 INFO : End of write delay center optimization
611 20:12:29.631281 INFO : End of read delay center optimization
612 20:12:29.631753 INFO : End of max read latency training
613 20:12:29.636852 INFO : Training has run successfully!
614 20:12:29.637323 1D training succeed
615 20:12:29.646017 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 20:12:29.694384 Check phy result
617 20:12:29.694895 INFO : End of initialization
618 20:12:29.721778 INFO : End of 2D read delay Voltage center optimization
619 20:12:29.745960 INFO : End of 2D read delay Voltage center optimization
620 20:12:29.802651 INFO : End of 2D write delay Voltage center optimization
621 20:12:29.856661 INFO : End of 2D write delay Voltage center optimization
622 20:12:29.862275 INFO : Training has run successfully!
623 20:12:29.862745
624 20:12:29.863159 channel==0
625 20:12:29.867748 RxClkDly_Margin_A0==78 ps 8
626 20:12:29.868260 TxDqDly_Margin_A0==98 ps 10
627 20:12:29.871204 RxClkDly_Margin_A1==88 ps 9
628 20:12:29.871666 TxDqDly_Margin_A1==88 ps 9
629 20:12:29.876703 TrainedVREFDQ_A0==77
630 20:12:29.877173 TrainedVREFDQ_A1==75
631 20:12:29.877586 VrefDac_Margin_A0==24
632 20:12:29.882333 DeviceVref_Margin_A0==37
633 20:12:29.882794 VrefDac_Margin_A1==23
634 20:12:29.887916 DeviceVref_Margin_A1==39
635 20:12:29.888405
636 20:12:29.888815
637 20:12:29.889218 channel==1
638 20:12:29.889609 RxClkDly_Margin_A0==88 ps 9
639 20:12:29.893547 TxDqDly_Margin_A0==98 ps 10
640 20:12:29.894020 RxClkDly_Margin_A1==88 ps 9
641 20:12:29.899151 TxDqDly_Margin_A1==78 ps 8
642 20:12:29.899624 TrainedVREFDQ_A0==78
643 20:12:29.900064 TrainedVREFDQ_A1==75
644 20:12:29.904725 VrefDac_Margin_A0==23
645 20:12:29.905186 DeviceVref_Margin_A0==36
646 20:12:29.910330 VrefDac_Margin_A1==22
647 20:12:29.910799 DeviceVref_Margin_A1==39
648 20:12:29.911204
649 20:12:29.915934 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 20:12:29.916435
651 20:12:29.943742 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000016 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000062
652 20:12:29.949406 2D training succeed
653 20:12:29.955003 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 20:12:29.955475 auto size-- 65535DDR cs0 size: 2048MB
655 20:12:29.960589 DDR cs1 size: 2048MB
656 20:12:29.961060 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 20:12:29.966233 cs0 DataBus test pass
658 20:12:29.966710 cs1 DataBus test pass
659 20:12:29.967119 cs0 AddrBus test pass
660 20:12:29.971799 cs1 AddrBus test pass
661 20:12:29.972303
662 20:12:29.972716 100bdlr_step_size ps== 471
663 20:12:29.973123 result report
664 20:12:29.977405 boot times 0Enable ddr reg access
665 20:12:29.984847 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 20:12:29.998697 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 20:12:30.658882 bl2z: ptr: 05129330, size: 00001e40
668 20:12:30.666697 0.0;M3 CHK:0;cm4_sp_mode 0
669 20:12:30.667185 MVN_1=0x00000000
670 20:12:30.667596 MVN_2=0x00000000
671 20:12:30.678128 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 20:12:30.678613 OPS=0x04
673 20:12:30.679021 ring efuse init
674 20:12:30.681091 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 20:12:30.687035 [0.017354 Inits done]
676 20:12:30.687499 secure task start!
677 20:12:30.687901 high task start!
678 20:12:30.688327 low task start!
679 20:12:30.691380 run into bl31
680 20:12:30.699951 NOTICE: BL31: v1.3(release):4fc40b1
681 20:12:30.707764 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 20:12:30.708270 NOTICE: BL31: G12A normal boot!
683 20:12:30.723324 NOTICE: BL31: BL33 decompress pass
684 20:12:30.729009 ERROR: Error initializing runtime service opteed_fast
685 20:12:31.524344
686 20:12:31.525009
687 20:12:31.529706 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 20:12:31.530215
689 20:12:31.533070 Model: Libre Computer AML-S905D3-CC Solitude
690 20:12:31.680210 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 20:12:31.695448 DRAM: 2 GiB (effective 3.8 GiB)
692 20:12:31.796455 Core: 406 devices, 33 uclasses, devicetree: separate
693 20:12:31.802286 WDT: Not starting watchdog@f0d0
694 20:12:31.827389 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 20:12:31.839632 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 20:12:31.844583 ** Bad device specification mmc 0 **
697 20:12:31.854680 Card did not respond to voltage select! : -110
698 20:12:31.862490 ** Bad device specification mmc 0 **
699 20:12:31.862969 Couldn't find partition mmc 0
700 20:12:31.870802 Card did not respond to voltage select! : -110
701 20:12:31.876252 ** Bad device specification mmc 0 **
702 20:12:31.876726 Couldn't find partition mmc 0
703 20:12:31.881262 Error: could not access storage.
704 20:12:32.177826 Net: eth0: ethernet@ff3f0000
705 20:12:32.178318 starting USB...
706 20:12:32.422561 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 20:12:32.423202 Starting the controller
708 20:12:32.429512 USB XHCI 1.10
709 20:12:33.983607 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 20:12:33.991949 scanning usb for storage devices... 0 Storage Device(s) found
712 20:12:34.043435 Hit any key to stop autoboot: 1
713 20:12:34.044301 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 20:12:34.044942 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 20:12:34.045433 Setting prompt string to ['=>']
716 20:12:34.045912 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 20:12:34.057952 0
718 20:12:34.058837 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 20:12:34.160019 => setenv autoload no
721 20:12:34.160615 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 20:12:34.164730 setenv autoload no
724 20:12:34.265686 => setenv initrd_high 0xffffffff
725 20:12:34.266223 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 20:12:34.270487 setenv initrd_high 0xffffffff
728 20:12:34.371434 => setenv fdt_high 0xffffffff
729 20:12:34.371958 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 20:12:34.376142 setenv fdt_high 0xffffffff
732 20:12:34.477096 => dhcp
733 20:12:34.477590 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 20:12:34.481439 dhcp
735 20:12:35.537680 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 20:12:35.538102 Speed: 1000, full duplex
737 20:12:35.538330 BOOTP broadcast 1
738 20:12:35.560936 DHCP client bound to address 192.168.6.21 (23 ms)
740 20:12:35.662373 => setenv serverip 192.168.6.2
741 20:12:35.663138 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
742 20:12:35.667563 setenv serverip 192.168.6.2
744 20:12:35.768662 => tftpboot 0x01080000 936439/tftp-deploy-mxtyl1th/kernel/uImage
745 20:12:35.769462 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
746 20:12:35.776183 tftpboot 0x01080000 936439/tftp-deploy-mxtyl1th/kernel/uImage
747 20:12:35.776615 Speed: 1000, full duplex
748 20:12:35.776849 Using ethernet@ff3f0000 device
749 20:12:35.781643 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 20:12:35.787206 Filename '936439/tftp-deploy-mxtyl1th/kernel/uImage'.
751 20:12:35.791112 Load address: 0x1080000
752 20:12:37.829020 Loading: *############################## UDP wrong checksum 000000ff 0000a29c
753 20:12:37.886606 # UDP wrong checksum 000000ff 0000338f
754 20:12:38.958512 ################### 43.6 MiB
755 20:12:38.959129 13.8 MiB/s
756 20:12:38.959541 done
757 20:12:38.962822 Bytes transferred = 45713984 (2b98a40 hex)
759 20:12:39.064240 => tftpboot 0x08000000 936439/tftp-deploy-mxtyl1th/ramdisk/ramdisk.cpio.gz.uboot
760 20:12:39.065329 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
761 20:12:39.071752 tftpboot 0x08000000 936439/tftp-deploy-mxtyl1th/ramdisk/ramdisk.cpio.gz.uboot
762 20:12:39.072266 Speed: 1000, full duplex
763 20:12:39.072667 Using ethernet@ff3f0000 device
764 20:12:39.077321 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
765 20:12:39.087088 Filename '936439/tftp-deploy-mxtyl1th/ramdisk/ramdisk.cpio.gz.uboot'.
766 20:12:39.087543 Load address: 0x8000000
767 20:12:40.662216 Loading: *################################################# UDP wrong checksum 00000005 000097a3
768 20:12:42.725759 UDP wrong checksum 000000ff 0000e2ca
769 20:12:42.770088 UDP wrong checksum 000000ff 00007dbd
770 20:12:45.662019 T UDP wrong checksum 00000005 000097a3
771 20:12:51.596397 T UDP wrong checksum 000000ff 00003b19
772 20:12:51.656556 UDP wrong checksum 000000ff 0000cb0b
773 20:12:55.664217 T UDP wrong checksum 00000005 000097a3
774 20:13:15.668242 T T T T UDP wrong checksum 00000005 000097a3
775 20:13:22.486851 T UDP wrong checksum 000000ff 00004bb8
776 20:13:22.506305 UDP wrong checksum 000000ff 0000e1aa
777 20:13:26.645286 T UDP wrong checksum 000000ff 000046ec
778 20:13:26.656309 UDP wrong checksum 000000ff 0000dbde
779 20:13:35.672059 T
780 20:13:35.672728 Retry count exceeded; starting again
782 20:13:35.674241 end: 2.4.3 bootloader-commands (duration 00:01:02) [common]
785 20:13:35.676252 end: 2.4 uboot-commands (duration 00:01:21) [common]
787 20:13:35.677949 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
789 20:13:35.679134 end: 2 uboot-action (duration 00:01:21) [common]
791 20:13:35.680845 Cleaning after the job
792 20:13:35.681466 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936439/tftp-deploy-mxtyl1th/ramdisk
793 20:13:35.682872 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936439/tftp-deploy-mxtyl1th/kernel
794 20:13:35.732213 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936439/tftp-deploy-mxtyl1th/dtb
795 20:13:35.733030 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936439/tftp-deploy-mxtyl1th/modules
796 20:13:35.753484 start: 4.1 power-off (timeout 00:00:30) [common]
797 20:13:35.754128 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
798 20:13:35.796109 >> OK - accepted request
799 20:13:35.798045 Returned 0 in 0 seconds
800 20:13:35.899173 end: 4.1 power-off (duration 00:00:00) [common]
802 20:13:35.900892 start: 4.2 read-feedback (timeout 00:10:00) [common]
803 20:13:35.901996 Listened to connection for namespace 'common' for up to 1s
804 20:13:36.902818 Finalising connection for namespace 'common'
805 20:13:36.903592 Disconnecting from shell: Finalise
806 20:13:36.904233 =>
807 20:13:37.005308 end: 4.2 read-feedback (duration 00:00:01) [common]
808 20:13:37.006071 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/936439
809 20:13:37.322459 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/936439
810 20:13:37.323034 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.