Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:11:18.705042 lava-dispatcher, installed at version: 2024.01
2 21:11:18.705858 start: 0 validate
3 21:11:18.706366 Start time: 2024-11-04 21:11:18.706336+00:00 (UTC)
4 21:11:18.706921 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:11:18.707448 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 21:11:18.755183 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:11:18.755757 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-5-g557329bcecc2%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 21:11:18.793080 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:11:18.793811 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-5-g557329bcecc2%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 21:11:18.825251 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:11:18.825760 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-5-g557329bcecc2%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 21:11:18.862610 validate duration: 0.16
14 21:11:18.863434 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 21:11:18.863759 start: 1.1 download-retry (timeout 00:10:00) [common]
16 21:11:18.864075 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 21:11:18.864662 Not decompressing ramdisk as can be used compressed.
18 21:11:18.865133 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 21:11:18.865385 saving as /var/lib/lava/dispatcher/tmp/936402/tftp-deploy-ec9_ukzy/ramdisk/rootfs.cpio.gz
20 21:11:18.865638 total size: 47897469 (45 MB)
21 21:11:18.905024 progress 0 % (0 MB)
22 21:11:18.945751 progress 5 % (2 MB)
23 21:11:18.977189 progress 10 % (4 MB)
24 21:11:19.008876 progress 15 % (6 MB)
25 21:11:19.040076 progress 20 % (9 MB)
26 21:11:19.072032 progress 25 % (11 MB)
27 21:11:19.103009 progress 30 % (13 MB)
28 21:11:19.134721 progress 35 % (16 MB)
29 21:11:19.165848 progress 40 % (18 MB)
30 21:11:19.197235 progress 45 % (20 MB)
31 21:11:19.228878 progress 50 % (22 MB)
32 21:11:19.259858 progress 55 % (25 MB)
33 21:11:19.292030 progress 60 % (27 MB)
34 21:11:19.323112 progress 65 % (29 MB)
35 21:11:19.354575 progress 70 % (32 MB)
36 21:11:19.385509 progress 75 % (34 MB)
37 21:11:19.415365 progress 80 % (36 MB)
38 21:11:19.445530 progress 85 % (38 MB)
39 21:11:19.475389 progress 90 % (41 MB)
40 21:11:19.505179 progress 95 % (43 MB)
41 21:11:19.534998 progress 100 % (45 MB)
42 21:11:19.535724 45 MB downloaded in 0.67 s (68.17 MB/s)
43 21:11:19.536298 end: 1.1.1 http-download (duration 00:00:01) [common]
45 21:11:19.537176 end: 1.1 download-retry (duration 00:00:01) [common]
46 21:11:19.537468 start: 1.2 download-retry (timeout 00:09:59) [common]
47 21:11:19.537734 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 21:11:19.538289 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-5-g557329bcecc2/arm64/defconfig/gcc-12/kernel/Image
49 21:11:19.538550 saving as /var/lib/lava/dispatcher/tmp/936402/tftp-deploy-ec9_ukzy/kernel/Image
50 21:11:19.538758 total size: 45713920 (43 MB)
51 21:11:19.538968 No compression specified
52 21:11:19.576778 progress 0 % (0 MB)
53 21:11:19.604666 progress 5 % (2 MB)
54 21:11:19.633049 progress 10 % (4 MB)
55 21:11:19.661474 progress 15 % (6 MB)
56 21:11:19.689771 progress 20 % (8 MB)
57 21:11:19.718483 progress 25 % (10 MB)
58 21:11:19.747050 progress 30 % (13 MB)
59 21:11:19.775936 progress 35 % (15 MB)
60 21:11:19.804631 progress 40 % (17 MB)
61 21:11:19.832881 progress 45 % (19 MB)
62 21:11:19.861959 progress 50 % (21 MB)
63 21:11:19.893014 progress 55 % (24 MB)
64 21:11:19.921740 progress 60 % (26 MB)
65 21:11:19.949968 progress 65 % (28 MB)
66 21:11:19.978330 progress 70 % (30 MB)
67 21:11:20.007214 progress 75 % (32 MB)
68 21:11:20.036160 progress 80 % (34 MB)
69 21:11:20.064584 progress 85 % (37 MB)
70 21:11:20.093263 progress 90 % (39 MB)
71 21:11:20.121712 progress 95 % (41 MB)
72 21:11:20.150138 progress 100 % (43 MB)
73 21:11:20.150647 43 MB downloaded in 0.61 s (71.25 MB/s)
74 21:11:20.151131 end: 1.2.1 http-download (duration 00:00:01) [common]
76 21:11:20.151941 end: 1.2 download-retry (duration 00:00:01) [common]
77 21:11:20.152250 start: 1.3 download-retry (timeout 00:09:59) [common]
78 21:11:20.152519 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 21:11:20.152996 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-5-g557329bcecc2/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 21:11:20.153274 saving as /var/lib/lava/dispatcher/tmp/936402/tftp-deploy-ec9_ukzy/dtb/meson-g12b-a311d-libretech-cc.dtb
81 21:11:20.153485 total size: 54703 (0 MB)
82 21:11:20.153694 No compression specified
83 21:11:20.193939 progress 59 % (0 MB)
84 21:11:20.194785 progress 100 % (0 MB)
85 21:11:20.195329 0 MB downloaded in 0.04 s (1.25 MB/s)
86 21:11:20.195817 end: 1.3.1 http-download (duration 00:00:00) [common]
88 21:11:20.196678 end: 1.3 download-retry (duration 00:00:00) [common]
89 21:11:20.196939 start: 1.4 download-retry (timeout 00:09:59) [common]
90 21:11:20.197199 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 21:11:20.197661 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-5-g557329bcecc2/arm64/defconfig/gcc-12/modules.tar.xz
92 21:11:20.197907 saving as /var/lib/lava/dispatcher/tmp/936402/tftp-deploy-ec9_ukzy/modules/modules.tar
93 21:11:20.198110 total size: 11612232 (11 MB)
94 21:11:20.198320 Using unxz to decompress xz
95 21:11:20.230733 progress 0 % (0 MB)
96 21:11:20.296529 progress 5 % (0 MB)
97 21:11:20.371316 progress 10 % (1 MB)
98 21:11:20.467500 progress 15 % (1 MB)
99 21:11:20.560171 progress 20 % (2 MB)
100 21:11:20.639570 progress 25 % (2 MB)
101 21:11:20.714998 progress 30 % (3 MB)
102 21:11:20.793520 progress 35 % (3 MB)
103 21:11:20.866184 progress 40 % (4 MB)
104 21:11:20.941638 progress 45 % (5 MB)
105 21:11:21.025982 progress 50 % (5 MB)
106 21:11:21.103516 progress 55 % (6 MB)
107 21:11:21.188688 progress 60 % (6 MB)
108 21:11:21.269084 progress 65 % (7 MB)
109 21:11:21.349524 progress 70 % (7 MB)
110 21:11:21.427092 progress 75 % (8 MB)
111 21:11:21.510652 progress 80 % (8 MB)
112 21:11:21.592801 progress 85 % (9 MB)
113 21:11:21.672042 progress 90 % (9 MB)
114 21:11:21.750176 progress 95 % (10 MB)
115 21:11:21.827182 progress 100 % (11 MB)
116 21:11:21.838854 11 MB downloaded in 1.64 s (6.75 MB/s)
117 21:11:21.839594 end: 1.4.1 http-download (duration 00:00:02) [common]
119 21:11:21.841351 end: 1.4 download-retry (duration 00:00:02) [common]
120 21:11:21.841922 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 21:11:21.842468 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 21:11:21.842983 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 21:11:21.843494 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 21:11:21.844544 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_
125 21:11:21.845581 makedir: /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin
126 21:11:21.846300 makedir: /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/tests
127 21:11:21.846962 makedir: /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/results
128 21:11:21.847603 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-add-keys
129 21:11:21.848618 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-add-sources
130 21:11:21.849591 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-background-process-start
131 21:11:21.850577 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-background-process-stop
132 21:11:21.851625 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-common-functions
133 21:11:21.852641 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-echo-ipv4
134 21:11:21.853601 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-install-packages
135 21:11:21.854527 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-installed-packages
136 21:11:21.855490 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-os-build
137 21:11:21.856500 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-probe-channel
138 21:11:21.857461 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-probe-ip
139 21:11:21.858409 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-target-ip
140 21:11:21.859362 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-target-mac
141 21:11:21.860353 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-target-storage
142 21:11:21.861332 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-test-case
143 21:11:21.862274 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-test-event
144 21:11:21.863208 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-test-feedback
145 21:11:21.864170 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-test-raise
146 21:11:21.865111 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-test-reference
147 21:11:21.866045 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-test-runner
148 21:11:21.866994 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-test-set
149 21:11:21.867936 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-test-shell
150 21:11:21.868944 Updating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-install-packages (oe)
151 21:11:21.869997 Updating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/bin/lava-installed-packages (oe)
152 21:11:21.870875 Creating /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/environment
153 21:11:21.871633 LAVA metadata
154 21:11:21.872184 - LAVA_JOB_ID=936402
155 21:11:21.872632 - LAVA_DISPATCHER_IP=192.168.6.2
156 21:11:21.873315 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 21:11:21.875176 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 21:11:21.875790 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 21:11:21.876260 skipped lava-vland-overlay
160 21:11:21.876766 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 21:11:21.877288 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 21:11:21.877723 skipped lava-multinode-overlay
163 21:11:21.878217 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 21:11:21.878731 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 21:11:21.879222 Loading test definitions
166 21:11:21.879784 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 21:11:21.880174 Using /lava-936402 at stage 0
168 21:11:21.881430 uuid=936402_1.5.2.4.1 testdef=None
169 21:11:21.881771 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 21:11:21.882062 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 21:11:21.883854 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 21:11:21.884758 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 21:11:21.886999 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 21:11:21.887875 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 21:11:21.890059 runner path: /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/0/tests/0_igt-gpu-panfrost test_uuid 936402_1.5.2.4.1
178 21:11:21.890680 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 21:11:21.891538 Creating lava-test-runner.conf files
181 21:11:21.891762 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/936402/lava-overlay-kbx6wrv_/lava-936402/0 for stage 0
182 21:11:21.892146 - 0_igt-gpu-panfrost
183 21:11:21.892550 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 21:11:21.892860 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 21:11:21.916699 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 21:11:21.917129 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 21:11:21.917418 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 21:11:21.917707 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 21:11:21.917988 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 21:11:28.886963 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 21:11:28.887431 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 21:11:28.887678 extracting modules file /var/lib/lava/dispatcher/tmp/936402/tftp-deploy-ec9_ukzy/modules/modules.tar to /var/lib/lava/dispatcher/tmp/936402/extract-overlay-ramdisk-ov8r4o1b/ramdisk
193 21:11:30.315080 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 21:11:30.315562 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 21:11:30.315841 [common] Applying overlay /var/lib/lava/dispatcher/tmp/936402/compress-overlay-hl41ufyz/overlay-1.5.2.5.tar.gz to ramdisk
196 21:11:30.316092 [common] Applying overlay /var/lib/lava/dispatcher/tmp/936402/compress-overlay-hl41ufyz/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/936402/extract-overlay-ramdisk-ov8r4o1b/ramdisk
197 21:11:30.346192 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 21:11:30.346590 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 21:11:30.346858 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 21:11:30.347082 Converting downloaded kernel to a uImage
201 21:11:30.347391 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/936402/tftp-deploy-ec9_ukzy/kernel/Image /var/lib/lava/dispatcher/tmp/936402/tftp-deploy-ec9_ukzy/kernel/uImage
202 21:11:30.878710 output: Image Name:
203 21:11:30.879129 output: Created: Mon Nov 4 21:11:30 2024
204 21:11:30.879340 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 21:11:30.879542 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 21:11:30.879741 output: Load Address: 01080000
207 21:11:30.879939 output: Entry Point: 01080000
208 21:11:30.880175 output:
209 21:11:30.880507 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 21:11:30.880775 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 21:11:30.881039 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 21:11:30.881290 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 21:11:30.881544 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 21:11:30.881797 Building ramdisk /var/lib/lava/dispatcher/tmp/936402/extract-overlay-ramdisk-ov8r4o1b/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/936402/extract-overlay-ramdisk-ov8r4o1b/ramdisk
215 21:11:37.545048 >> 502412 blocks
216 21:11:58.140627 Adding RAMdisk u-boot header.
217 21:11:58.141383 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/936402/extract-overlay-ramdisk-ov8r4o1b/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/936402/extract-overlay-ramdisk-ov8r4o1b/ramdisk.cpio.gz.uboot
218 21:11:58.948318 output: Image Name:
219 21:11:58.949000 output: Created: Mon Nov 4 21:11:58 2024
220 21:11:58.949454 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 21:11:58.949898 output: Data Size: 65714341 Bytes = 64174.16 KiB = 62.67 MiB
222 21:11:58.950335 output: Load Address: 00000000
223 21:11:58.950766 output: Entry Point: 00000000
224 21:11:58.951192 output:
225 21:11:58.952305 rename /var/lib/lava/dispatcher/tmp/936402/extract-overlay-ramdisk-ov8r4o1b/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/936402/tftp-deploy-ec9_ukzy/ramdisk/ramdisk.cpio.gz.uboot
226 21:11:58.953087 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 21:11:58.953675 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 21:11:58.954246 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 21:11:58.954744 No LXC device requested
230 21:11:58.955283 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 21:11:58.955830 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 21:11:58.956438 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 21:11:58.956937 Checking files for TFTP limit of 4294967296 bytes.
234 21:11:58.959818 end: 1 tftp-deploy (duration 00:00:40) [common]
235 21:11:58.960476 start: 2 uboot-action (timeout 00:05:00) [common]
236 21:11:58.961059 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 21:11:58.961601 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 21:11:58.962146 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 21:11:58.962716 Using kernel file from prepare-kernel: 936402/tftp-deploy-ec9_ukzy/kernel/uImage
240 21:11:58.963378 substitutions:
241 21:11:58.963826 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 21:11:58.964305 - {DTB_ADDR}: 0x01070000
243 21:11:58.964746 - {DTB}: 936402/tftp-deploy-ec9_ukzy/dtb/meson-g12b-a311d-libretech-cc.dtb
244 21:11:58.965187 - {INITRD}: 936402/tftp-deploy-ec9_ukzy/ramdisk/ramdisk.cpio.gz.uboot
245 21:11:58.965620 - {KERNEL_ADDR}: 0x01080000
246 21:11:58.966052 - {KERNEL}: 936402/tftp-deploy-ec9_ukzy/kernel/uImage
247 21:11:58.966485 - {LAVA_MAC}: None
248 21:11:58.966959 - {PRESEED_CONFIG}: None
249 21:11:58.967390 - {PRESEED_LOCAL}: None
250 21:11:58.967819 - {RAMDISK_ADDR}: 0x08000000
251 21:11:58.968278 - {RAMDISK}: 936402/tftp-deploy-ec9_ukzy/ramdisk/ramdisk.cpio.gz.uboot
252 21:11:58.968714 - {ROOT_PART}: None
253 21:11:58.969142 - {ROOT}: None
254 21:11:58.969570 - {SERVER_IP}: 192.168.6.2
255 21:11:58.970002 - {TEE_ADDR}: 0x83000000
256 21:11:58.970433 - {TEE}: None
257 21:11:58.970862 Parsed boot commands:
258 21:11:58.971278 - setenv autoload no
259 21:11:58.971704 - setenv initrd_high 0xffffffff
260 21:11:58.972192 - setenv fdt_high 0xffffffff
261 21:11:58.972624 - dhcp
262 21:11:58.973054 - setenv serverip 192.168.6.2
263 21:11:58.973481 - tftpboot 0x01080000 936402/tftp-deploy-ec9_ukzy/kernel/uImage
264 21:11:58.973907 - tftpboot 0x08000000 936402/tftp-deploy-ec9_ukzy/ramdisk/ramdisk.cpio.gz.uboot
265 21:11:58.974336 - tftpboot 0x01070000 936402/tftp-deploy-ec9_ukzy/dtb/meson-g12b-a311d-libretech-cc.dtb
266 21:11:58.974786 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 21:11:58.975260 - bootm 0x01080000 0x08000000 0x01070000
268 21:11:58.975818 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 21:11:58.977487 start: 2.3 connect-device (timeout 00:05:00) [common]
271 21:11:58.977972 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 21:11:58.992652 Setting prompt string to ['lava-test: # ']
273 21:11:58.994274 end: 2.3 connect-device (duration 00:00:00) [common]
274 21:11:58.994918 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 21:11:58.995508 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 21:11:58.996253 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 21:11:58.997599 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 21:11:59.034267 >> OK - accepted request
279 21:11:59.036473 Returned 0 in 0 seconds
280 21:11:59.137676 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 21:11:59.139442 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 21:11:59.140086 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 21:11:59.140657 Setting prompt string to ['Hit any key to stop autoboot']
285 21:11:59.141154 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 21:11:59.142847 Trying 192.168.56.21...
287 21:11:59.143360 Connected to conserv1.
288 21:11:59.143815 Escape character is '^]'.
289 21:11:59.144291
290 21:11:59.144757 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 21:11:59.145220
292 21:12:10.597421 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 21:12:10.598096 bl2_stage_init 0x01
294 21:12:10.598600 bl2_stage_init 0x81
295 21:12:10.603141 hw id: 0x0000 - pwm id 0x01
296 21:12:10.603720 bl2_stage_init 0xc1
297 21:12:10.604324 bl2_stage_init 0x02
298 21:12:10.604788
299 21:12:10.609115 L0:00000000
300 21:12:10.609608 L1:20000703
301 21:12:10.610047 L2:00008067
302 21:12:10.610473 L3:14000000
303 21:12:10.614130 B2:00402000
304 21:12:10.614607 B1:e0f83180
305 21:12:10.615039
306 21:12:10.615469 TE: 58124
307 21:12:10.615899
308 21:12:10.619634 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 21:12:10.620138
310 21:12:10.620575 Board ID = 1
311 21:12:10.625357 Set A53 clk to 24M
312 21:12:10.625830 Set A73 clk to 24M
313 21:12:10.626260 Set clk81 to 24M
314 21:12:10.630925 A53 clk: 1200 MHz
315 21:12:10.631387 A73 clk: 1200 MHz
316 21:12:10.631818 CLK81: 166.6M
317 21:12:10.632279 smccc: 00012a92
318 21:12:10.636441 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 21:12:10.642021 board id: 1
320 21:12:10.647930 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 21:12:10.658580 fw parse done
322 21:12:10.664540 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 21:12:10.707152 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 21:12:10.718025 PIEI prepare done
325 21:12:10.718499 fastboot data load
326 21:12:10.718934 fastboot data verify
327 21:12:10.723816 verify result: 266
328 21:12:10.729423 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 21:12:10.729964 LPDDR4 probe
330 21:12:10.730441 ddr clk to 1584MHz
331 21:12:10.737344 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 21:12:10.774634
333 21:12:10.775162 dmc_version 0001
334 21:12:10.781351 Check phy result
335 21:12:10.787159 INFO : End of CA training
336 21:12:10.787663 INFO : End of initialization
337 21:12:10.792818 INFO : Training has run successfully!
338 21:12:10.793318 Check phy result
339 21:12:10.798359 INFO : End of initialization
340 21:12:10.798881 INFO : End of read enable training
341 21:12:10.804017 INFO : End of fine write leveling
342 21:12:10.809561 INFO : End of Write leveling coarse delay
343 21:12:10.810063 INFO : Training has run successfully!
344 21:12:10.810512 Check phy result
345 21:12:10.815158 INFO : End of initialization
346 21:12:10.815660 INFO : End of read dq deskew training
347 21:12:10.820766 INFO : End of MPR read delay center optimization
348 21:12:10.826377 INFO : End of write delay center optimization
349 21:12:10.831932 INFO : End of read delay center optimization
350 21:12:10.832473 INFO : End of max read latency training
351 21:12:10.837565 INFO : Training has run successfully!
352 21:12:10.838066 1D training succeed
353 21:12:10.846736 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 21:12:10.894411 Check phy result
355 21:12:10.894952 INFO : End of initialization
356 21:12:10.915949 INFO : End of 2D read delay Voltage center optimization
357 21:12:10.935390 INFO : End of 2D read delay Voltage center optimization
358 21:12:10.987204 INFO : End of 2D write delay Voltage center optimization
359 21:12:11.036432 INFO : End of 2D write delay Voltage center optimization
360 21:12:11.041932 INFO : Training has run successfully!
361 21:12:11.042437
362 21:12:11.042894 channel==0
363 21:12:11.047620 RxClkDly_Margin_A0==88 ps 9
364 21:12:11.048150 TxDqDly_Margin_A0==98 ps 10
365 21:12:11.053226 RxClkDly_Margin_A1==88 ps 9
366 21:12:11.053722 TxDqDly_Margin_A1==98 ps 10
367 21:12:11.054177 TrainedVREFDQ_A0==74
368 21:12:11.058256 TrainedVREFDQ_A1==74
369 21:12:11.060819 VrefDac_Margin_A0==25
370 21:12:11.061317 DeviceVref_Margin_A0==40
371 21:12:11.061764 VrefDac_Margin_A1==25
372 21:12:11.066333 DeviceVref_Margin_A1==40
373 21:12:11.066827
374 21:12:11.067281
375 21:12:11.067721 channel==1
376 21:12:11.072048 RxClkDly_Margin_A0==88 ps 9
377 21:12:11.072589 TxDqDly_Margin_A0==88 ps 9
378 21:12:11.073048 RxClkDly_Margin_A1==88 ps 9
379 21:12:11.077618 TxDqDly_Margin_A1==88 ps 9
380 21:12:11.078126 TrainedVREFDQ_A0==77
381 21:12:11.078877 TrainedVREFDQ_A1==77
382 21:12:11.084003 VrefDac_Margin_A0==23
383 21:12:11.084483 DeviceVref_Margin_A0==37
384 21:12:11.089545 VrefDac_Margin_A1==24
385 21:12:11.090013 DeviceVref_Margin_A1==37
386 21:12:11.090455
387 21:12:11.095179 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 21:12:11.095661
389 21:12:11.124431 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
390 21:12:11.125021 2D training succeed
391 21:12:11.135453 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 21:12:11.135938 auto size-- 65535DDR cs0 size: 2048MB
393 21:12:11.138967 DDR cs1 size: 2048MB
394 21:12:11.144556 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 21:12:11.145029 cs0 DataBus test pass
396 21:12:11.145473 cs1 DataBus test pass
397 21:12:11.150147 cs0 AddrBus test pass
398 21:12:11.150615 cs1 AddrBus test pass
399 21:12:11.151058
400 21:12:11.151498 100bdlr_step_size ps== 420
401 21:12:11.155754 result report
402 21:12:11.156255 boot times 0Enable ddr reg access
403 21:12:11.164514 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 21:12:11.177980 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 21:12:11.750122 0.0;M3 CHK:0;cm4_sp_mode 0
406 21:12:11.750571 MVN_1=0x00000000
407 21:12:11.755553 MVN_2=0x00000000
408 21:12:11.761290 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 21:12:11.761820 OPS=0x10
410 21:12:11.762301 ring efuse init
411 21:12:11.762664 chipver efuse init
412 21:12:11.767038 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 21:12:11.772694 [0.018961 Inits done]
414 21:12:11.773455 secure task start!
415 21:12:11.774047 high task start!
416 21:12:11.777241 low task start!
417 21:12:11.777860 run into bl31
418 21:12:11.783925 NOTICE: BL31: v1.3(release):4fc40b1
419 21:12:11.791751 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 21:12:11.792299 NOTICE: BL31: G12A normal boot!
421 21:12:11.817110 NOTICE: BL31: BL33 decompress pass
422 21:12:11.822808 ERROR: Error initializing runtime service opteed_fast
423 21:12:13.055506
424 21:12:13.056156
425 21:12:13.063965 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 21:12:13.064475
427 21:12:13.064895 Model: Libre Computer AML-A311D-CC Alta
428 21:12:13.272317 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 21:12:13.295749 DRAM: 2 GiB (effective 3.8 GiB)
430 21:12:13.438727 Core: 408 devices, 31 uclasses, devicetree: separate
431 21:12:13.444587 WDT: Not starting watchdog@f0d0
432 21:12:13.476843 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 21:12:13.489269 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 21:12:13.494285 ** Bad device specification mmc 0 **
435 21:12:13.504624 Card did not respond to voltage select! : -110
436 21:12:13.512298 ** Bad device specification mmc 0 **
437 21:12:13.512938 Couldn't find partition mmc 0
438 21:12:13.520609 Card did not respond to voltage select! : -110
439 21:12:13.526115 ** Bad device specification mmc 0 **
440 21:12:13.526575 Couldn't find partition mmc 0
441 21:12:13.531182 Error: could not access storage.
442 21:12:14.797942 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 21:12:14.798516 bl2_stage_init 0x01
444 21:12:14.798961 bl2_stage_init 0x81
445 21:12:14.803527 hw id: 0x0000 - pwm id 0x01
446 21:12:14.804076 bl2_stage_init 0xc1
447 21:12:14.804512 bl2_stage_init 0x02
448 21:12:14.804930
449 21:12:14.809107 L0:00000000
450 21:12:14.809616 L1:20000703
451 21:12:14.810041 L2:00008067
452 21:12:14.810453 L3:14000000
453 21:12:14.812025 B2:00402000
454 21:12:14.812548 B1:e0f83180
455 21:12:14.812961
456 21:12:14.813370 TE: 58167
457 21:12:14.813773
458 21:12:14.823023 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 21:12:14.823539
460 21:12:14.823961 Board ID = 1
461 21:12:14.824419 Set A53 clk to 24M
462 21:12:14.824825 Set A73 clk to 24M
463 21:12:14.828690 Set clk81 to 24M
464 21:12:14.829194 A53 clk: 1200 MHz
465 21:12:14.829614 A73 clk: 1200 MHz
466 21:12:14.834295 CLK81: 166.6M
467 21:12:14.834813 smccc: 00012abd
468 21:12:14.839943 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 21:12:14.840471 board id: 1
470 21:12:14.845465 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 21:12:14.859219 fw parse done
472 21:12:14.865192 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 21:12:14.907800 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 21:12:14.918700 PIEI prepare done
475 21:12:14.919201 fastboot data load
476 21:12:14.919621 fastboot data verify
477 21:12:14.924375 verify result: 266
478 21:12:14.929996 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 21:12:14.930504 LPDDR4 probe
480 21:12:14.930917 ddr clk to 1584MHz
481 21:12:14.937927 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 21:12:14.975122
483 21:12:14.975627 dmc_version 0001
484 21:12:14.981848 Check phy result
485 21:12:14.987734 INFO : End of CA training
486 21:12:14.988262 INFO : End of initialization
487 21:12:14.993328 INFO : Training has run successfully!
488 21:12:14.993828 Check phy result
489 21:12:14.999004 INFO : End of initialization
490 21:12:14.999502 INFO : End of read enable training
491 21:12:15.004514 INFO : End of fine write leveling
492 21:12:15.010104 INFO : End of Write leveling coarse delay
493 21:12:15.010602 INFO : Training has run successfully!
494 21:12:15.011020 Check phy result
495 21:12:15.015727 INFO : End of initialization
496 21:12:15.016268 INFO : End of read dq deskew training
497 21:12:15.021296 INFO : End of MPR read delay center optimization
498 21:12:15.026893 INFO : End of write delay center optimization
499 21:12:15.032503 INFO : End of read delay center optimization
500 21:12:15.033009 INFO : End of max read latency training
501 21:12:15.038128 INFO : Training has run successfully!
502 21:12:15.038624 1D training succeed
503 21:12:15.047255 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 21:12:15.094890 Check phy result
505 21:12:15.095396 INFO : End of initialization
506 21:12:15.116667 INFO : End of 2D read delay Voltage center optimization
507 21:12:15.136874 INFO : End of 2D read delay Voltage center optimization
508 21:12:15.188963 INFO : End of 2D write delay Voltage center optimization
509 21:12:15.238304 INFO : End of 2D write delay Voltage center optimization
510 21:12:15.243895 INFO : Training has run successfully!
511 21:12:15.244462
512 21:12:15.244897 channel==0
513 21:12:15.249498 RxClkDly_Margin_A0==88 ps 9
514 21:12:15.250002 TxDqDly_Margin_A0==98 ps 10
515 21:12:15.255096 RxClkDly_Margin_A1==88 ps 9
516 21:12:15.255611 TxDqDly_Margin_A1==98 ps 10
517 21:12:15.256063 TrainedVREFDQ_A0==74
518 21:12:15.260670 TrainedVREFDQ_A1==74
519 21:12:15.261172 VrefDac_Margin_A0==25
520 21:12:15.261592 DeviceVref_Margin_A0==40
521 21:12:15.266301 VrefDac_Margin_A1==25
522 21:12:15.266799 DeviceVref_Margin_A1==40
523 21:12:15.267214
524 21:12:15.267619
525 21:12:15.271868 channel==1
526 21:12:15.272405 RxClkDly_Margin_A0==98 ps 10
527 21:12:15.272823 TxDqDly_Margin_A0==98 ps 10
528 21:12:15.277462 RxClkDly_Margin_A1==88 ps 9
529 21:12:15.277962 TxDqDly_Margin_A1==88 ps 9
530 21:12:15.283091 TrainedVREFDQ_A0==77
531 21:12:15.283591 TrainedVREFDQ_A1==77
532 21:12:15.284039 VrefDac_Margin_A0==22
533 21:12:15.288666 DeviceVref_Margin_A0==37
534 21:12:15.289170 VrefDac_Margin_A1==24
535 21:12:15.294284 DeviceVref_Margin_A1==37
536 21:12:15.294780
537 21:12:15.295204 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 21:12:15.295610
539 21:12:15.327818 soc_vref_reg_value 0x 00000019 00000019 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
540 21:12:15.328384 2D training succeed
541 21:12:15.333484 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 21:12:15.339085 auto size-- 65535DDR cs0 size: 2048MB
543 21:12:15.339591 DDR cs1 size: 2048MB
544 21:12:15.344685 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 21:12:15.345191 cs0 DataBus test pass
546 21:12:15.350275 cs1 DataBus test pass
547 21:12:15.350776 cs0 AddrBus test pass
548 21:12:15.351191 cs1 AddrBus test pass
549 21:12:15.351604
550 21:12:15.355867 100bdlr_step_size ps== 420
551 21:12:15.356407 result report
552 21:12:15.361471 boot times 0Enable ddr reg access
553 21:12:15.366817 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 21:12:15.380292 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 21:12:15.953937 0.0;M3 CHK:0;cm4_sp_mode 0
556 21:12:15.954502 MVN_1=0x00000000
557 21:12:15.959527 MVN_2=0x00000000
558 21:12:15.965282 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 21:12:15.965812 OPS=0x10
560 21:12:15.966248 ring efuse init
561 21:12:15.966659 chipver efuse init
562 21:12:15.970822 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 21:12:15.976421 [0.018961 Inits done]
564 21:12:15.976918 secure task start!
565 21:12:15.977312 high task start!
566 21:12:15.981030 low task start!
567 21:12:15.981677 run into bl31
568 21:12:15.987655 NOTICE: BL31: v1.3(release):4fc40b1
569 21:12:15.995464 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 21:12:15.995960 NOTICE: BL31: G12A normal boot!
571 21:12:16.020844 NOTICE: BL31: BL33 decompress pass
572 21:12:16.026521 ERROR: Error initializing runtime service opteed_fast
573 21:12:17.259566
574 21:12:17.260186
575 21:12:17.268065 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 21:12:17.268587
577 21:12:17.269017 Model: Libre Computer AML-A311D-CC Alta
578 21:12:17.476438 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 21:12:17.499748 DRAM: 2 GiB (effective 3.8 GiB)
580 21:12:17.642807 Core: 408 devices, 31 uclasses, devicetree: separate
581 21:12:17.648711 WDT: Not starting watchdog@f0d0
582 21:12:17.680889 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 21:12:17.693281 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 21:12:17.698387 ** Bad device specification mmc 0 **
585 21:12:17.708621 Card did not respond to voltage select! : -110
586 21:12:17.716241 ** Bad device specification mmc 0 **
587 21:12:17.716890 Couldn't find partition mmc 0
588 21:12:17.724590 Card did not respond to voltage select! : -110
589 21:12:17.730086 ** Bad device specification mmc 0 **
590 21:12:17.730741 Couldn't find partition mmc 0
591 21:12:17.735173 Error: could not access storage.
592 21:12:18.077778 Net: eth0: ethernet@ff3f0000
593 21:12:18.078536 starting USB...
594 21:12:18.329751 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 21:12:18.330544 Starting the controller
596 21:12:18.336603 USB XHCI 1.10
597 21:12:20.048465 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
598 21:12:20.049288 bl2_stage_init 0x81
599 21:12:20.053978 hw id: 0x0000 - pwm id 0x01
600 21:12:20.054664 bl2_stage_init 0xc1
601 21:12:20.055214 bl2_stage_init 0x02
602 21:12:20.055754
603 21:12:20.059548 L0:00000000
604 21:12:20.060262 L1:20000703
605 21:12:20.060828 L2:00008067
606 21:12:20.061366 L3:14000000
607 21:12:20.061890 B2:00402000
608 21:12:20.062869 B1:e0f83180
609 21:12:20.063477
610 21:12:20.064054 TE: 58150
611 21:12:20.064615
612 21:12:20.073563 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 21:12:20.074132
614 21:12:20.074570 Board ID = 1
615 21:12:20.074989 Set A53 clk to 24M
616 21:12:20.075401 Set A73 clk to 24M
617 21:12:20.079147 Set clk81 to 24M
618 21:12:20.079663 A53 clk: 1200 MHz
619 21:12:20.080117 A73 clk: 1200 MHz
620 21:12:20.086333 CLK81: 166.6M
621 21:12:20.086851 smccc: 00012aab
622 21:12:20.088117 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 21:12:20.093718 board id: 1
624 21:12:20.099051 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 21:12:20.109517 fw parse done
626 21:12:20.115462 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 21:12:20.158052 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 21:12:20.169017 PIEI prepare done
629 21:12:20.169536 fastboot data load
630 21:12:20.169957 fastboot data verify
631 21:12:20.174588 verify result: 266
632 21:12:20.180201 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 21:12:20.180697 LPDDR4 probe
634 21:12:20.181113 ddr clk to 1584MHz
635 21:12:20.188211 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 21:12:20.225519
637 21:12:20.226046 dmc_version 0001
638 21:12:20.232273 Check phy result
639 21:12:20.238089 INFO : End of CA training
640 21:12:20.238587 INFO : End of initialization
641 21:12:20.243667 INFO : Training has run successfully!
642 21:12:20.244205 Check phy result
643 21:12:20.249262 INFO : End of initialization
644 21:12:20.249756 INFO : End of read enable training
645 21:12:20.252534 INFO : End of fine write leveling
646 21:12:20.258063 INFO : End of Write leveling coarse delay
647 21:12:20.263689 INFO : Training has run successfully!
648 21:12:20.264365 Check phy result
649 21:12:20.264936 INFO : End of initialization
650 21:12:20.269274 INFO : End of read dq deskew training
651 21:12:20.272772 INFO : End of MPR read delay center optimization
652 21:12:20.278278 INFO : End of write delay center optimization
653 21:12:20.283889 INFO : End of read delay center optimization
654 21:12:20.284405 INFO : End of max read latency training
655 21:12:20.289490 INFO : Training has run successfully!
656 21:12:20.289976 1D training succeed
657 21:12:20.297647 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 21:12:20.345180 Check phy result
659 21:12:20.345678 INFO : End of initialization
660 21:12:20.366947 INFO : End of 2D read delay Voltage center optimization
661 21:12:20.387174 INFO : End of 2D read delay Voltage center optimization
662 21:12:20.439246 INFO : End of 2D write delay Voltage center optimization
663 21:12:20.488645 INFO : End of 2D write delay Voltage center optimization
664 21:12:20.494280 INFO : Training has run successfully!
665 21:12:20.494808
666 21:12:20.495233 channel==0
667 21:12:20.499904 RxClkDly_Margin_A0==88 ps 9
668 21:12:20.500457 TxDqDly_Margin_A0==98 ps 10
669 21:12:20.505424 RxClkDly_Margin_A1==88 ps 9
670 21:12:20.505933 TxDqDly_Margin_A1==98 ps 10
671 21:12:20.506354 TrainedVREFDQ_A0==74
672 21:12:20.511005 TrainedVREFDQ_A1==74
673 21:12:20.511521 VrefDac_Margin_A0==25
674 21:12:20.511938 DeviceVref_Margin_A0==40
675 21:12:20.516646 VrefDac_Margin_A1==25
676 21:12:20.517160 DeviceVref_Margin_A1==40
677 21:12:20.517575
678 21:12:20.517981
679 21:12:20.522181 channel==1
680 21:12:20.522708 RxClkDly_Margin_A0==98 ps 10
681 21:12:20.523123 TxDqDly_Margin_A0==88 ps 9
682 21:12:20.527894 RxClkDly_Margin_A1==88 ps 9
683 21:12:20.528440 TxDqDly_Margin_A1==88 ps 9
684 21:12:20.533449 TrainedVREFDQ_A0==75
685 21:12:20.533963 TrainedVREFDQ_A1==77
686 21:12:20.534378 VrefDac_Margin_A0==22
687 21:12:20.539036 DeviceVref_Margin_A0==38
688 21:12:20.539550 VrefDac_Margin_A1==24
689 21:12:20.544558 DeviceVref_Margin_A1==37
690 21:12:20.545060
691 21:12:20.545477 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 21:12:20.545885
693 21:12:20.578104 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
694 21:12:20.578701 2D training succeed
695 21:12:20.583851 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 21:12:20.589350 auto size-- 65535DDR cs0 size: 2048MB
697 21:12:20.589851 DDR cs1 size: 2048MB
698 21:12:20.594956 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 21:12:20.595455 cs0 DataBus test pass
700 21:12:20.600515 cs1 DataBus test pass
701 21:12:20.601008 cs0 AddrBus test pass
702 21:12:20.601420 cs1 AddrBus test pass
703 21:12:20.601821
704 21:12:20.606110 100bdlr_step_size ps== 420
705 21:12:20.606611 result report
706 21:12:20.611740 boot times 0Enable ddr reg access
707 21:12:20.617020 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 21:12:20.630455 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 21:12:21.204254 0.0;M3 CHK:0;cm4_sp_mode 0
710 21:12:21.204849 MVN_1=0x00000000
711 21:12:21.209757 MVN_2=0x00000000
712 21:12:21.215549 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 21:12:21.216115 OPS=0x10
714 21:12:21.216583 ring efuse init
715 21:12:21.216991 chipver efuse init
716 21:12:21.221182 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 21:12:21.226704 [0.018961 Inits done]
718 21:12:21.227186 secure task start!
719 21:12:21.227576 high task start!
720 21:12:21.231268 low task start!
721 21:12:21.231738 run into bl31
722 21:12:21.237891 NOTICE: BL31: v1.3(release):4fc40b1
723 21:12:21.245760 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 21:12:21.246252 NOTICE: BL31: G12A normal boot!
725 21:12:21.271074 NOTICE: BL31: BL33 decompress pass
726 21:12:21.276877 ERROR: Error initializing runtime service opteed_fast
727 21:12:22.509653
728 21:12:22.510246
729 21:12:22.518148 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 21:12:22.518640
731 21:12:22.519054 Model: Libre Computer AML-A311D-CC Alta
732 21:12:22.726566 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 21:12:22.749910 DRAM: 2 GiB (effective 3.8 GiB)
734 21:12:22.892824 Core: 408 devices, 31 uclasses, devicetree: separate
735 21:12:22.898802 WDT: Not starting watchdog@f0d0
736 21:12:22.931023 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 21:12:22.943317 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 21:12:22.948466 ** Bad device specification mmc 0 **
739 21:12:22.958766 Card did not respond to voltage select! : -110
740 21:12:22.966524 ** Bad device specification mmc 0 **
741 21:12:22.967014 Couldn't find partition mmc 0
742 21:12:22.974673 Card did not respond to voltage select! : -110
743 21:12:22.980292 ** Bad device specification mmc 0 **
744 21:12:22.980758 Couldn't find partition mmc 0
745 21:12:22.985378 Error: could not access storage.
746 21:12:23.327805 Net: eth0: ethernet@ff3f0000
747 21:12:23.328421 starting USB...
748 21:12:23.579574 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 21:12:23.580194 Starting the controller
750 21:12:23.586639 USB XHCI 1.10
751 21:12:25.748396 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
752 21:12:25.749224 bl2_stage_init 0x81
753 21:12:25.753958 hw id: 0x0000 - pwm id 0x01
754 21:12:25.754587 bl2_stage_init 0xc1
755 21:12:25.755137 bl2_stage_init 0x02
756 21:12:25.755681
757 21:12:25.759665 L0:00000000
758 21:12:25.760332 L1:20000703
759 21:12:25.760875 L2:00008067
760 21:12:25.761397 L3:14000000
761 21:12:25.761920 B2:00402000
762 21:12:25.762866 B1:e0f83180
763 21:12:25.763423
764 21:12:25.763957 TE: 58150
765 21:12:25.764521
766 21:12:25.773649 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
767 21:12:25.774151
768 21:12:25.774579 Board ID = 1
769 21:12:25.774984 Set A53 clk to 24M
770 21:12:25.775386 Set A73 clk to 24M
771 21:12:25.779153 Set clk81 to 24M
772 21:12:25.779619 A53 clk: 1200 MHz
773 21:12:25.780054 A73 clk: 1200 MHz
774 21:12:25.784807 CLK81: 166.6M
775 21:12:25.785273 smccc: 00012aac
776 21:12:25.790362 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
777 21:12:25.790833 board id: 1
778 21:12:25.799113 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
779 21:12:25.809527 fw parse done
780 21:12:25.815457 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
781 21:12:25.858043 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
782 21:12:25.868958 PIEI prepare done
783 21:12:25.869435 fastboot data load
784 21:12:25.869846 fastboot data verify
785 21:12:25.874598 verify result: 266
786 21:12:25.880240 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
787 21:12:25.880730 LPDDR4 probe
788 21:12:25.881138 ddr clk to 1584MHz
789 21:12:25.888126 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
790 21:12:25.925425
791 21:12:25.925960 dmc_version 0001
792 21:12:25.932149 Check phy result
793 21:12:25.937974 INFO : End of CA training
794 21:12:25.938480 INFO : End of initialization
795 21:12:25.943577 INFO : Training has run successfully!
796 21:12:25.944099 Check phy result
797 21:12:25.949191 INFO : End of initialization
798 21:12:25.949666 INFO : End of read enable training
799 21:12:25.952511 INFO : End of fine write leveling
800 21:12:25.958123 INFO : End of Write leveling coarse delay
801 21:12:25.963699 INFO : Training has run successfully!
802 21:12:25.964218 Check phy result
803 21:12:25.964629 INFO : End of initialization
804 21:12:25.969308 INFO : End of read dq deskew training
805 21:12:25.974907 INFO : End of MPR read delay center optimization
806 21:12:25.975404 INFO : End of write delay center optimization
807 21:12:25.980510 INFO : End of read delay center optimization
808 21:12:25.986123 INFO : End of max read latency training
809 21:12:25.986608 INFO : Training has run successfully!
810 21:12:25.991725 1D training succeed
811 21:12:25.997616 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
812 21:12:26.045161 Check phy result
813 21:12:26.045695 INFO : End of initialization
814 21:12:26.067737 INFO : End of 2D read delay Voltage center optimization
815 21:12:26.087964 INFO : End of 2D read delay Voltage center optimization
816 21:12:26.140026 INFO : End of 2D write delay Voltage center optimization
817 21:12:26.189393 INFO : End of 2D write delay Voltage center optimization
818 21:12:26.195022 INFO : Training has run successfully!
819 21:12:26.195658
820 21:12:26.196292 channel==0
821 21:12:26.200603 RxClkDly_Margin_A0==88 ps 9
822 21:12:26.201226 TxDqDly_Margin_A0==98 ps 10
823 21:12:26.206207 RxClkDly_Margin_A1==88 ps 9
824 21:12:26.206810 TxDqDly_Margin_A1==98 ps 10
825 21:12:26.207385 TrainedVREFDQ_A0==74
826 21:12:26.211848 TrainedVREFDQ_A1==75
827 21:12:26.212507 VrefDac_Margin_A0==24
828 21:12:26.213058 DeviceVref_Margin_A0==40
829 21:12:26.217392 VrefDac_Margin_A1==25
830 21:12:26.218009 DeviceVref_Margin_A1==39
831 21:12:26.218517
832 21:12:26.219020
833 21:12:26.222986 channel==1
834 21:12:26.223574 RxClkDly_Margin_A0==98 ps 10
835 21:12:26.224133 TxDqDly_Margin_A0==88 ps 9
836 21:12:26.228583 RxClkDly_Margin_A1==98 ps 10
837 21:12:26.229176 TxDqDly_Margin_A1==98 ps 10
838 21:12:26.234195 TrainedVREFDQ_A0==77
839 21:12:26.234810 TrainedVREFDQ_A1==77
840 21:12:26.235325 VrefDac_Margin_A0==22
841 21:12:26.239774 DeviceVref_Margin_A0==37
842 21:12:26.240404 VrefDac_Margin_A1==22
843 21:12:26.245384 DeviceVref_Margin_A1==37
844 21:12:26.245976
845 21:12:26.246489 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
846 21:12:26.250967
847 21:12:26.278994 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000017 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
848 21:12:26.279703 2D training succeed
849 21:12:26.284588 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
850 21:12:26.290172 auto size-- 65535DDR cs0 size: 2048MB
851 21:12:26.290765 DDR cs1 size: 2048MB
852 21:12:26.295779 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
853 21:12:26.296537 cs0 DataBus test pass
854 21:12:26.301381 cs1 DataBus test pass
855 21:12:26.301973 cs0 AddrBus test pass
856 21:12:26.302497 cs1 AddrBus test pass
857 21:12:26.302996
858 21:12:26.307062 100bdlr_step_size ps== 420
859 21:12:26.307665 result report
860 21:12:26.312658 boot times 0Enable ddr reg access
861 21:12:26.318020 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
862 21:12:26.331459 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
863 21:12:26.904494 0.0;M3 CHK:0;cm4_sp_mode 0
864 21:12:26.905317 MVN_1=0x00000000
865 21:12:26.910053 MVN_2=0x00000000
866 21:12:26.915736 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
867 21:12:26.916439 OPS=0x10
868 21:12:26.917009 ring efuse init
869 21:12:26.917536 chipver efuse init
870 21:12:26.921309 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
871 21:12:26.926875 [0.018961 Inits done]
872 21:12:26.927474 secure task start!
873 21:12:26.928033 high task start!
874 21:12:26.931460 low task start!
875 21:12:26.932088 run into bl31
876 21:12:26.938131 NOTICE: BL31: v1.3(release):4fc40b1
877 21:12:26.945926 NOTICE: BL31: Built : 15:58:17, May 22 2019
878 21:12:26.946556 NOTICE: BL31: G12A normal boot!
879 21:12:26.971921 NOTICE: BL31: BL33 decompress pass
880 21:12:26.977666 ERROR: Error initializing runtime service opteed_fast
881 21:12:28.210501
882 21:12:28.211309
883 21:12:28.218859 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
884 21:12:28.219484
885 21:12:28.220080 Model: Libre Computer AML-A311D-CC Alta
886 21:12:28.427274 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
887 21:12:28.450685 DRAM: 2 GiB (effective 3.8 GiB)
888 21:12:28.593674 Core: 408 devices, 31 uclasses, devicetree: separate
889 21:12:28.599549 WDT: Not starting watchdog@f0d0
890 21:12:28.631893 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
891 21:12:28.644226 Loading Environment from FAT... Card did not respond to voltage select! : -110
892 21:12:28.649227 ** Bad device specification mmc 0 **
893 21:12:28.659584 Card did not respond to voltage select! : -110
894 21:12:28.667225 ** Bad device specification mmc 0 **
895 21:12:28.667867 Couldn't find partition mmc 0
896 21:12:28.675572 Card did not respond to voltage select! : -110
897 21:12:28.681077 ** Bad device specification mmc 0 **
898 21:12:28.681706 Couldn't find partition mmc 0
899 21:12:28.686132 Error: could not access storage.
900 21:12:29.028578 Net: eth0: ethernet@ff3f0000
901 21:12:29.029333 starting USB...
902 21:12:29.280437 Bus usb@ff500000: Register 3000140 NbrPorts 3
903 21:12:29.281192 Starting the controller
904 21:12:29.287400 USB XHCI 1.10
905 21:12:30.841519 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
906 21:12:30.849903 scanning usb for storage devices... 0 Storage Device(s) found
908 21:12:30.903170 Hit any key to stop autoboot: 1
909 21:12:30.905057 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
910 21:12:30.906276 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
911 21:12:30.907279 Setting prompt string to ['=>']
912 21:12:30.908336 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
913 21:12:30.917333 0
914 21:12:30.918256 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
915 21:12:30.918774 Sending with 10 millisecond of delay
917 21:12:32.053700 => setenv autoload no
918 21:12:32.064307 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
919 21:12:32.067051 setenv autoload no
920 21:12:32.067621 Sending with 10 millisecond of delay
922 21:12:33.864442 => setenv initrd_high 0xffffffff
923 21:12:33.875021 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
924 21:12:33.875552 setenv initrd_high 0xffffffff
925 21:12:33.876043 Sending with 10 millisecond of delay
927 21:12:35.492883 => setenv fdt_high 0xffffffff
928 21:12:35.503644 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
929 21:12:35.504474 setenv fdt_high 0xffffffff
930 21:12:35.505193 Sending with 10 millisecond of delay
932 21:12:35.796935 => dhcp
933 21:12:35.807569 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
934 21:12:35.808410 dhcp
935 21:12:35.808862 Speed: 1000, full duplex
936 21:12:35.809270 BOOTP broadcast 1
937 21:12:35.816693 DHCP client bound to address 192.168.6.27 (9 ms)
938 21:12:35.817388 Sending with 10 millisecond of delay
940 21:12:37.540028 => setenv serverip 192.168.6.2
941 21:12:37.550908 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
942 21:12:37.551905 setenv serverip 192.168.6.2
943 21:12:37.552742 Sending with 10 millisecond of delay
945 21:12:41.277542 => tftpboot 0x01080000 936402/tftp-deploy-ec9_ukzy/kernel/uImage
946 21:12:41.288300 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
947 21:12:41.289096 tftpboot 0x01080000 936402/tftp-deploy-ec9_ukzy/kernel/uImage
948 21:12:41.289530 Speed: 1000, full duplex
949 21:12:41.289932 Using ethernet@ff3f0000 device
950 21:12:41.291133 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
951 21:12:41.296678 Filename '936402/tftp-deploy-ec9_ukzy/kernel/uImage'.
952 21:12:41.300657 Load address: 0x1080000
953 21:12:44.128427 Loading: *################################################## 43.6 MiB
954 21:12:44.129057 15.4 MiB/s
955 21:12:44.129466 done
956 21:12:44.132342 Bytes transferred = 45713984 (2b98a40 hex)
957 21:12:44.133106 Sending with 10 millisecond of delay
959 21:12:48.823077 => tftpboot 0x08000000 936402/tftp-deploy-ec9_ukzy/ramdisk/ramdisk.cpio.gz.uboot
960 21:12:48.833801 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
961 21:12:48.834567 tftpboot 0x08000000 936402/tftp-deploy-ec9_ukzy/ramdisk/ramdisk.cpio.gz.uboot
962 21:12:48.834998 Speed: 1000, full duplex
963 21:12:48.835399 Using ethernet@ff3f0000 device
964 21:12:48.836625 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
965 21:12:48.845408 Filename '936402/tftp-deploy-ec9_ukzy/ramdisk/ramdisk.cpio.gz.uboot'.
966 21:12:48.845889 Load address: 0x8000000
967 21:13:00.011339 Loading: *#########T ######################################## UDP wrong checksum 0000000f 00000cdf
968 21:13:02.767832 UDP wrong checksum 000000ff 0000efd7
969 21:13:02.819603 UDP wrong checksum 000000ff 000080ca
970 21:13:05.013465 T UDP wrong checksum 0000000f 00000cdf
971 21:13:10.781909 T UDP wrong checksum 000000ff 000088e6
972 21:13:10.819130 UDP wrong checksum 000000ff 000012d9
973 21:13:15.015573 T UDP wrong checksum 0000000f 00000cdf
974 21:13:30.814704 T T T UDP wrong checksum 000000ff 0000b4cb
975 21:13:30.821839 UDP wrong checksum 000000ff 000042be
976 21:13:35.019516 T UDP wrong checksum 0000000f 00000cdf
977 21:13:50.023549 T T
978 21:13:50.024211 Retry count exceeded; starting again
980 21:13:50.025662 end: 2.4.3 bootloader-commands (duration 00:01:19) [common]
983 21:13:50.027452 end: 2.4 uboot-commands (duration 00:01:51) [common]
985 21:13:50.028890 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
987 21:13:50.029931 end: 2 uboot-action (duration 00:01:51) [common]
989 21:13:50.031498 Cleaning after the job
990 21:13:50.032066 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936402/tftp-deploy-ec9_ukzy/ramdisk
991 21:13:50.033193 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936402/tftp-deploy-ec9_ukzy/kernel
992 21:13:50.077856 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936402/tftp-deploy-ec9_ukzy/dtb
993 21:13:50.078692 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936402/tftp-deploy-ec9_ukzy/modules
994 21:13:50.097085 start: 4.1 power-off (timeout 00:00:30) [common]
995 21:13:50.097763 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
996 21:13:50.130588 >> OK - accepted request
997 21:13:50.132605 Returned 0 in 0 seconds
998 21:13:50.233609 end: 4.1 power-off (duration 00:00:00) [common]
1000 21:13:50.234585 start: 4.2 read-feedback (timeout 00:10:00) [common]
1001 21:13:50.235235 Listened to connection for namespace 'common' for up to 1s
1002 21:13:51.236203 Finalising connection for namespace 'common'
1003 21:13:51.236895 Disconnecting from shell: Finalise
1004 21:13:51.237402 =>
1005 21:13:51.338365 end: 4.2 read-feedback (duration 00:00:01) [common]
1006 21:13:51.339008 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/936402
1007 21:13:52.048992 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/936402
1008 21:13:52.049607 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.