Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 03:54:54.344413 lava-dispatcher, installed at version: 2024.01
2 03:54:54.345219 start: 0 validate
3 03:54:54.345694 Start time: 2024-11-05 03:54:54.345663+00:00 (UTC)
4 03:54:54.346248 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 03:54:54.346792 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 03:54:54.391692 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 03:54:54.392342 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-77-g2e1b3cc9d7f7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 03:54:54.422309 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 03:54:54.422963 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-77-g2e1b3cc9d7f7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 03:54:55.471077 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 03:54:55.471566 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-77-g2e1b3cc9d7f7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 03:54:55.508259 validate duration: 1.16
14 03:54:55.509717 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 03:54:55.510326 start: 1.1 download-retry (timeout 00:10:00) [common]
16 03:54:55.510902 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 03:54:55.511867 Not decompressing ramdisk as can be used compressed.
18 03:54:55.512630 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 03:54:55.513128 saving as /var/lib/lava/dispatcher/tmp/937875/tftp-deploy-sut681ak/ramdisk/rootfs.cpio.gz
20 03:54:55.513639 total size: 8181887 (7 MB)
21 03:54:55.550347 progress 0 % (0 MB)
22 03:54:55.561745 progress 5 % (0 MB)
23 03:54:55.573081 progress 10 % (0 MB)
24 03:54:55.584945 progress 15 % (1 MB)
25 03:54:55.591697 progress 20 % (1 MB)
26 03:54:55.597391 progress 25 % (1 MB)
27 03:54:55.602591 progress 30 % (2 MB)
28 03:54:55.608362 progress 35 % (2 MB)
29 03:54:55.613575 progress 40 % (3 MB)
30 03:54:55.619170 progress 45 % (3 MB)
31 03:54:55.624480 progress 50 % (3 MB)
32 03:54:55.630110 progress 55 % (4 MB)
33 03:54:55.635516 progress 60 % (4 MB)
34 03:54:55.641106 progress 65 % (5 MB)
35 03:54:55.646281 progress 70 % (5 MB)
36 03:54:55.651855 progress 75 % (5 MB)
37 03:54:55.657016 progress 80 % (6 MB)
38 03:54:55.662657 progress 85 % (6 MB)
39 03:54:55.667846 progress 90 % (7 MB)
40 03:54:55.673450 progress 95 % (7 MB)
41 03:54:55.678135 progress 100 % (7 MB)
42 03:54:55.678752 7 MB downloaded in 0.17 s (47.26 MB/s)
43 03:54:55.679310 end: 1.1.1 http-download (duration 00:00:00) [common]
45 03:54:55.680258 end: 1.1 download-retry (duration 00:00:00) [common]
46 03:54:55.680572 start: 1.2 download-retry (timeout 00:10:00) [common]
47 03:54:55.680854 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 03:54:55.681320 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-77-g2e1b3cc9d7f7/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 03:54:55.681566 saving as /var/lib/lava/dispatcher/tmp/937875/tftp-deploy-sut681ak/kernel/Image
50 03:54:55.681782 total size: 66443776 (63 MB)
51 03:54:55.682000 No compression specified
52 03:54:55.715780 progress 0 % (0 MB)
53 03:54:55.756139 progress 5 % (3 MB)
54 03:54:55.796033 progress 10 % (6 MB)
55 03:54:55.836281 progress 15 % (9 MB)
56 03:54:55.875752 progress 20 % (12 MB)
57 03:54:55.915396 progress 25 % (15 MB)
58 03:54:55.955569 progress 30 % (19 MB)
59 03:54:55.997244 progress 35 % (22 MB)
60 03:54:56.037223 progress 40 % (25 MB)
61 03:54:56.076876 progress 45 % (28 MB)
62 03:54:56.117231 progress 50 % (31 MB)
63 03:54:56.157138 progress 55 % (34 MB)
64 03:54:56.197311 progress 60 % (38 MB)
65 03:54:56.237545 progress 65 % (41 MB)
66 03:54:56.277554 progress 70 % (44 MB)
67 03:54:56.317725 progress 75 % (47 MB)
68 03:54:56.358154 progress 80 % (50 MB)
69 03:54:56.398626 progress 85 % (53 MB)
70 03:54:56.438109 progress 90 % (57 MB)
71 03:54:56.478058 progress 95 % (60 MB)
72 03:54:56.517256 progress 100 % (63 MB)
73 03:54:56.517954 63 MB downloaded in 0.84 s (75.78 MB/s)
74 03:54:56.518444 end: 1.2.1 http-download (duration 00:00:01) [common]
76 03:54:56.519294 end: 1.2 download-retry (duration 00:00:01) [common]
77 03:54:56.519571 start: 1.3 download-retry (timeout 00:09:59) [common]
78 03:54:56.519836 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 03:54:56.520562 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-77-g2e1b3cc9d7f7/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 03:54:56.520878 saving as /var/lib/lava/dispatcher/tmp/937875/tftp-deploy-sut681ak/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 03:54:56.521091 total size: 53209 (0 MB)
82 03:54:56.521302 No compression specified
83 03:54:56.563707 progress 61 % (0 MB)
84 03:54:56.564557 progress 100 % (0 MB)
85 03:54:56.565101 0 MB downloaded in 0.04 s (1.15 MB/s)
86 03:54:56.565575 end: 1.3.1 http-download (duration 00:00:00) [common]
88 03:54:56.566389 end: 1.3 download-retry (duration 00:00:00) [common]
89 03:54:56.566651 start: 1.4 download-retry (timeout 00:09:59) [common]
90 03:54:56.566913 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 03:54:56.567361 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-77-g2e1b3cc9d7f7/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 03:54:56.567602 saving as /var/lib/lava/dispatcher/tmp/937875/tftp-deploy-sut681ak/modules/modules.tar
93 03:54:56.567807 total size: 16128444 (15 MB)
94 03:54:56.568040 Using unxz to decompress xz
95 03:54:56.599252 progress 0 % (0 MB)
96 03:54:56.700985 progress 5 % (0 MB)
97 03:54:56.818993 progress 10 % (1 MB)
98 03:54:56.934710 progress 15 % (2 MB)
99 03:54:57.066260 progress 20 % (3 MB)
100 03:54:57.203880 progress 25 % (3 MB)
101 03:54:57.310694 progress 30 % (4 MB)
102 03:54:57.422889 progress 35 % (5 MB)
103 03:54:57.529257 progress 40 % (6 MB)
104 03:54:57.635811 progress 45 % (6 MB)
105 03:54:57.753420 progress 50 % (7 MB)
106 03:54:57.862819 progress 55 % (8 MB)
107 03:54:57.982798 progress 60 % (9 MB)
108 03:54:58.097027 progress 65 % (10 MB)
109 03:54:58.208376 progress 70 % (10 MB)
110 03:54:58.327391 progress 75 % (11 MB)
111 03:54:58.442826 progress 80 % (12 MB)
112 03:54:58.558029 progress 85 % (13 MB)
113 03:54:58.666069 progress 90 % (13 MB)
114 03:54:58.772076 progress 95 % (14 MB)
115 03:54:58.892998 progress 100 % (15 MB)
116 03:54:58.904984 15 MB downloaded in 2.34 s (6.58 MB/s)
117 03:54:58.905584 end: 1.4.1 http-download (duration 00:00:02) [common]
119 03:54:58.906434 end: 1.4 download-retry (duration 00:00:02) [common]
120 03:54:58.906708 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 03:54:58.906977 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 03:54:58.907229 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 03:54:58.907486 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 03:54:58.908172 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74
125 03:54:58.909049 makedir: /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin
126 03:54:58.909693 makedir: /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/tests
127 03:54:58.910309 makedir: /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/results
128 03:54:58.910924 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-add-keys
129 03:54:58.912151 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-add-sources
130 03:54:58.913134 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-background-process-start
131 03:54:58.914075 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-background-process-stop
132 03:54:58.915046 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-common-functions
133 03:54:58.915957 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-echo-ipv4
134 03:54:58.916913 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-install-packages
135 03:54:58.917805 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-installed-packages
136 03:54:58.918717 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-os-build
137 03:54:58.919671 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-probe-channel
138 03:54:58.920623 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-probe-ip
139 03:54:58.921519 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-target-ip
140 03:54:58.922402 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-target-mac
141 03:54:58.923282 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-target-storage
142 03:54:58.924220 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-test-case
143 03:54:58.925162 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-test-event
144 03:54:58.926056 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-test-feedback
145 03:54:58.926993 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-test-raise
146 03:54:58.927934 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-test-reference
147 03:54:58.928886 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-test-runner
148 03:54:58.929781 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-test-set
149 03:54:58.930664 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-test-shell
150 03:54:58.931578 Updating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-install-packages (oe)
151 03:54:58.932566 Updating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/bin/lava-installed-packages (oe)
152 03:54:58.933390 Creating /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/environment
153 03:54:58.934097 LAVA metadata
154 03:54:58.934589 - LAVA_JOB_ID=937875
155 03:54:58.935030 - LAVA_DISPATCHER_IP=192.168.6.2
156 03:54:58.935685 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 03:54:58.937491 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 03:54:58.938093 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 03:54:58.938514 skipped lava-vland-overlay
160 03:54:58.939002 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 03:54:58.939506 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 03:54:58.939933 skipped lava-multinode-overlay
163 03:54:58.940493 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 03:54:58.941000 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 03:54:58.941472 Loading test definitions
166 03:54:58.942019 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 03:54:58.942464 Using /lava-937875 at stage 0
168 03:54:58.944425 uuid=937875_1.5.2.4.1 testdef=None
169 03:54:58.944774 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 03:54:58.945054 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 03:54:58.946877 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 03:54:58.947724 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 03:54:58.950007 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 03:54:58.950893 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 03:54:58.953114 runner path: /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/0/tests/0_dmesg test_uuid 937875_1.5.2.4.1
178 03:54:58.953679 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 03:54:58.954472 Creating lava-test-runner.conf files
181 03:54:58.954680 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/937875/lava-overlay-vm03zk74/lava-937875/0 for stage 0
182 03:54:58.955009 - 0_dmesg
183 03:54:58.955367 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 03:54:58.955653 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 03:54:58.979269 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 03:54:58.979661 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 03:54:58.979931 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 03:54:58.980228 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 03:54:58.980498 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 03:54:59.882819 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 03:54:59.883285 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 03:54:59.883532 extracting modules file /var/lib/lava/dispatcher/tmp/937875/tftp-deploy-sut681ak/modules/modules.tar to /var/lib/lava/dispatcher/tmp/937875/extract-overlay-ramdisk-defl210c/ramdisk
193 03:55:01.410004 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 03:55:01.410478 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 03:55:01.410762 [common] Applying overlay /var/lib/lava/dispatcher/tmp/937875/compress-overlay-ewv8712y/overlay-1.5.2.5.tar.gz to ramdisk
196 03:55:01.410978 [common] Applying overlay /var/lib/lava/dispatcher/tmp/937875/compress-overlay-ewv8712y/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/937875/extract-overlay-ramdisk-defl210c/ramdisk
197 03:55:01.441234 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 03:55:01.441632 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 03:55:01.441909 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 03:55:01.442137 Converting downloaded kernel to a uImage
201 03:55:01.442453 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/937875/tftp-deploy-sut681ak/kernel/Image /var/lib/lava/dispatcher/tmp/937875/tftp-deploy-sut681ak/kernel/uImage
202 03:55:02.120308 output: Image Name:
203 03:55:02.120731 output: Created: Tue Nov 5 03:55:01 2024
204 03:55:02.120940 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 03:55:02.121146 output: Data Size: 66443776 Bytes = 64886.50 KiB = 63.37 MiB
206 03:55:02.121350 output: Load Address: 01080000
207 03:55:02.121549 output: Entry Point: 01080000
208 03:55:02.121747 output:
209 03:55:02.122080 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 03:55:02.122347 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 03:55:02.122617 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 03:55:02.122871 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 03:55:02.123127 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 03:55:02.123383 Building ramdisk /var/lib/lava/dispatcher/tmp/937875/extract-overlay-ramdisk-defl210c/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/937875/extract-overlay-ramdisk-defl210c/ramdisk
215 03:55:05.350072 >> 254425 blocks
216 03:55:16.286359 Adding RAMdisk u-boot header.
217 03:55:16.286797 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/937875/extract-overlay-ramdisk-defl210c/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/937875/extract-overlay-ramdisk-defl210c/ramdisk.cpio.gz.uboot
218 03:55:16.637195 output: Image Name:
219 03:55:16.637595 output: Created: Tue Nov 5 03:55:16 2024
220 03:55:16.637806 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 03:55:16.638011 output: Data Size: 33574263 Bytes = 32787.37 KiB = 32.02 MiB
222 03:55:16.638213 output: Load Address: 00000000
223 03:55:16.638413 output: Entry Point: 00000000
224 03:55:16.638609 output:
225 03:55:16.639192 rename /var/lib/lava/dispatcher/tmp/937875/extract-overlay-ramdisk-defl210c/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/937875/tftp-deploy-sut681ak/ramdisk/ramdisk.cpio.gz.uboot
226 03:55:16.639601 end: 1.5.8 compress-ramdisk (duration 00:00:15) [common]
227 03:55:16.639886 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
228 03:55:16.640404 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
229 03:55:16.640911 No LXC device requested
230 03:55:16.641463 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 03:55:16.642021 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
232 03:55:16.642563 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 03:55:16.643016 Checking files for TFTP limit of 4294967296 bytes.
234 03:55:16.645968 end: 1 tftp-deploy (duration 00:00:21) [common]
235 03:55:16.646598 start: 2 uboot-action (timeout 00:05:00) [common]
236 03:55:16.647170 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 03:55:16.647716 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 03:55:16.648312 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 03:55:16.648895 Using kernel file from prepare-kernel: 937875/tftp-deploy-sut681ak/kernel/uImage
240 03:55:16.649583 substitutions:
241 03:55:16.650039 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 03:55:16.650486 - {DTB_ADDR}: 0x01070000
243 03:55:16.650926 - {DTB}: 937875/tftp-deploy-sut681ak/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 03:55:16.651371 - {INITRD}: 937875/tftp-deploy-sut681ak/ramdisk/ramdisk.cpio.gz.uboot
245 03:55:16.651811 - {KERNEL_ADDR}: 0x01080000
246 03:55:16.652281 - {KERNEL}: 937875/tftp-deploy-sut681ak/kernel/uImage
247 03:55:16.652723 - {LAVA_MAC}: None
248 03:55:16.653201 - {PRESEED_CONFIG}: None
249 03:55:16.653638 - {PRESEED_LOCAL}: None
250 03:55:16.654071 - {RAMDISK_ADDR}: 0x08000000
251 03:55:16.654505 - {RAMDISK}: 937875/tftp-deploy-sut681ak/ramdisk/ramdisk.cpio.gz.uboot
252 03:55:16.654939 - {ROOT_PART}: None
253 03:55:16.655374 - {ROOT}: None
254 03:55:16.655805 - {SERVER_IP}: 192.168.6.2
255 03:55:16.656276 - {TEE_ADDR}: 0x83000000
256 03:55:16.656709 - {TEE}: None
257 03:55:16.657141 Parsed boot commands:
258 03:55:16.657561 - setenv autoload no
259 03:55:16.657991 - setenv initrd_high 0xffffffff
260 03:55:16.658420 - setenv fdt_high 0xffffffff
261 03:55:16.658845 - dhcp
262 03:55:16.659272 - setenv serverip 192.168.6.2
263 03:55:16.659700 - tftpboot 0x01080000 937875/tftp-deploy-sut681ak/kernel/uImage
264 03:55:16.660157 - tftpboot 0x08000000 937875/tftp-deploy-sut681ak/ramdisk/ramdisk.cpio.gz.uboot
265 03:55:16.660591 - tftpboot 0x01070000 937875/tftp-deploy-sut681ak/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 03:55:16.661021 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 03:55:16.661458 - bootm 0x01080000 0x08000000 0x01070000
268 03:55:16.662001 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 03:55:16.663627 start: 2.3 connect-device (timeout 00:05:00) [common]
271 03:55:16.664135 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 03:55:16.679880 Setting prompt string to ['lava-test: # ']
273 03:55:16.681529 end: 2.3 connect-device (duration 00:00:00) [common]
274 03:55:16.682176 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 03:55:16.682759 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 03:55:16.683315 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 03:55:16.684571 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 03:55:16.722308 >> OK - accepted request
279 03:55:16.724774 Returned 0 in 0 seconds
280 03:55:16.825962 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 03:55:16.827735 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 03:55:16.828433 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 03:55:16.828992 Setting prompt string to ['Hit any key to stop autoboot']
285 03:55:16.829490 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 03:55:16.831659 Trying 192.168.56.21...
287 03:55:16.832254 Connected to conserv1.
288 03:55:16.832723 Escape character is '^]'.
289 03:55:16.833202
290 03:55:16.833676 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 03:55:16.834161
292 03:55:24.347081 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 03:55:24.347515 bl2_stage_init 0x01
294 03:55:24.347742 bl2_stage_init 0x81
295 03:55:24.352657 hw id: 0x0000 - pwm id 0x01
296 03:55:24.353026 bl2_stage_init 0xc1
297 03:55:24.353342 bl2_stage_init 0x02
298 03:55:24.353646
299 03:55:24.358152 L0:00000000
300 03:55:24.358526 L1:00000703
301 03:55:24.358758 L2:00008067
302 03:55:24.358961 L3:15000000
303 03:55:24.359162 S1:00000000
304 03:55:24.360130 B2:20282000
305 03:55:24.365595 B1:a0f83180
306 03:55:24.365930
307 03:55:24.366232 TE: 70522
308 03:55:24.366541
309 03:55:24.371403 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 03:55:24.371746
311 03:55:24.372069 Board ID = 1
312 03:55:24.376848 Set cpu clk to 24M
313 03:55:24.377103 Set clk81 to 24M
314 03:55:24.377305 Use GP1_pll as DSU clk.
315 03:55:24.377506 DSU clk: 1200 Mhz
316 03:55:24.382303 CPU clk: 1200 MHz
317 03:55:24.382665 Set clk81 to 166.6M
318 03:55:24.387875 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 03:55:24.388256 board id: 1
320 03:55:24.397349 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 03:55:24.409105 fw parse done
322 03:55:24.415022 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 03:55:24.457465 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 03:55:24.469312 PIEI prepare done
325 03:55:24.469616 fastboot data load
326 03:55:24.469830 fastboot data verify
327 03:55:24.474786 verify result: 266
328 03:55:24.480444 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 03:55:24.480820 LPDDR4 probe
330 03:55:24.481134 ddr clk to 1584MHz
331 03:55:24.488365 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 03:55:24.526170
333 03:55:24.526492 dmc_version 0001
334 03:55:24.533166 Check phy result
335 03:55:24.539106 INFO : End of CA training
336 03:55:24.539466 INFO : End of initialization
337 03:55:24.544760 INFO : Training has run successfully!
338 03:55:24.545014 Check phy result
339 03:55:24.550324 INFO : End of initialization
340 03:55:24.550584 INFO : End of read enable training
341 03:55:24.553685 INFO : End of fine write leveling
342 03:55:24.559396 INFO : End of Write leveling coarse delay
343 03:55:24.564801 INFO : Training has run successfully!
344 03:55:24.565070 Check phy result
345 03:55:24.565276 INFO : End of initialization
346 03:55:24.570435 INFO : End of read dq deskew training
347 03:55:24.573903 INFO : End of MPR read delay center optimization
348 03:55:24.579444 INFO : End of write delay center optimization
349 03:55:24.585046 INFO : End of read delay center optimization
350 03:55:24.585422 INFO : End of max read latency training
351 03:55:24.590661 INFO : Training has run successfully!
352 03:55:24.590912 1D training succeed
353 03:55:24.598814 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 03:55:24.647043 Check phy result
355 03:55:24.647382 INFO : End of initialization
356 03:55:24.674463 INFO : End of 2D read delay Voltage center optimization
357 03:55:24.698396 INFO : End of 2D read delay Voltage center optimization
358 03:55:24.755406 INFO : End of 2D write delay Voltage center optimization
359 03:55:24.809443 INFO : End of 2D write delay Voltage center optimization
360 03:55:24.815011 INFO : Training has run successfully!
361 03:55:24.815288
362 03:55:24.815497 channel==0
363 03:55:24.820666 RxClkDly_Margin_A0==78 ps 8
364 03:55:24.820936 TxDqDly_Margin_A0==98 ps 10
365 03:55:24.823826 RxClkDly_Margin_A1==88 ps 9
366 03:55:24.824121 TxDqDly_Margin_A1==88 ps 9
367 03:55:24.830063 TrainedVREFDQ_A0==74
368 03:55:24.830333 TrainedVREFDQ_A1==74
369 03:55:24.830535 VrefDac_Margin_A0==23
370 03:55:24.835603 DeviceVref_Margin_A0==40
371 03:55:24.835975 VrefDac_Margin_A1==22
372 03:55:24.841166 DeviceVref_Margin_A1==40
373 03:55:24.841547
374 03:55:24.841862
375 03:55:24.842085 channel==1
376 03:55:24.842285 RxClkDly_Margin_A0==78 ps 8
377 03:55:24.846826 TxDqDly_Margin_A0==98 ps 10
378 03:55:24.847190 RxClkDly_Margin_A1==78 ps 8
379 03:55:24.852355 TxDqDly_Margin_A1==88 ps 9
380 03:55:24.852719 TrainedVREFDQ_A0==78
381 03:55:24.853032 TrainedVREFDQ_A1==75
382 03:55:24.857960 VrefDac_Margin_A0==22
383 03:55:24.858220 DeviceVref_Margin_A0==36
384 03:55:24.858426 VrefDac_Margin_A1==20
385 03:55:24.863521 DeviceVref_Margin_A1==39
386 03:55:24.863884
387 03:55:24.869119 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 03:55:24.869477
389 03:55:24.897171 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000018 00000015 00000016 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 03:55:24.897518 2D training succeed
391 03:55:24.908387 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 03:55:24.908866 auto size-- 65535DDR cs0 size: 2048MB
393 03:55:24.913989 DDR cs1 size: 2048MB
394 03:55:24.914289 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 03:55:24.919576 cs0 DataBus test pass
396 03:55:24.919866 cs1 DataBus test pass
397 03:55:24.920104 cs0 AddrBus test pass
398 03:55:24.925131 cs1 AddrBus test pass
399 03:55:24.925414
400 03:55:24.925625 100bdlr_step_size ps== 471
401 03:55:24.925833 result report
402 03:55:24.930729 boot times 0Enable ddr reg access
403 03:55:24.937723 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 03:55:24.951558 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 03:55:25.610540 bl2z: ptr: 05129330, size: 00001e40
406 03:55:25.619340 0.0;M3 CHK:0;cm4_sp_mode 0
407 03:55:25.619797 MVN_1=0x00000000
408 03:55:25.620075 MVN_2=0x00000000
409 03:55:25.630851 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 03:55:25.631162 OPS=0x04
411 03:55:25.631386 ring efuse init
412 03:55:25.636427 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 03:55:25.636713 [0.017354 Inits done]
414 03:55:25.636935 secure task start!
415 03:55:25.643682 high task start!
416 03:55:25.643965 low task start!
417 03:55:25.644211 run into bl31
418 03:55:25.652367 NOTICE: BL31: v1.3(release):4fc40b1
419 03:55:25.660116 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 03:55:25.660410 NOTICE: BL31: G12A normal boot!
421 03:55:25.675615 NOTICE: BL31: BL33 decompress pass
422 03:55:25.681419 ERROR: Error initializing runtime service opteed_fast
423 03:55:28.394133 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 03:55:28.394557 bl2_stage_init 0x01
425 03:55:28.394772 bl2_stage_init 0x81
426 03:55:28.399943 hw id: 0x0000 - pwm id 0x01
427 03:55:28.400296 bl2_stage_init 0xc1
428 03:55:28.405283 bl2_stage_init 0x02
429 03:55:28.405588
430 03:55:28.405805 L0:00000000
431 03:55:28.406012 L1:00000703
432 03:55:28.406218 L2:00008067
433 03:55:28.406423 L3:15000000
434 03:55:28.410868 S1:00000000
435 03:55:28.411170 B2:20282000
436 03:55:28.411386 B1:a0f83180
437 03:55:28.411591
438 03:55:28.411797 TE: 69952
439 03:55:28.412119
440 03:55:28.416446 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 03:55:28.416947
442 03:55:28.422065 Board ID = 1
443 03:55:28.422543 Set cpu clk to 24M
444 03:55:28.422981 Set clk81 to 24M
445 03:55:28.427722 Use GP1_pll as DSU clk.
446 03:55:28.428224 DSU clk: 1200 Mhz
447 03:55:28.428657 CPU clk: 1200 MHz
448 03:55:28.433230 Set clk81 to 166.6M
449 03:55:28.438857 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 03:55:28.439328 board id: 1
451 03:55:28.446045 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 03:55:28.456771 fw parse done
453 03:55:28.462837 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 03:55:28.505349 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 03:55:28.516308 PIEI prepare done
456 03:55:28.516793 fastboot data load
457 03:55:28.517234 fastboot data verify
458 03:55:28.521863 verify result: 266
459 03:55:28.527468 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 03:55:28.527948 LPDDR4 probe
461 03:55:28.528430 ddr clk to 1584MHz
462 03:55:28.535516 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 03:55:28.572700
464 03:55:28.573217 dmc_version 0001
465 03:55:28.579388 Check phy result
466 03:55:28.585309 INFO : End of CA training
467 03:55:28.585883 INFO : End of initialization
468 03:55:28.590886 INFO : Training has run successfully!
469 03:55:28.591384 Check phy result
470 03:55:28.596532 INFO : End of initialization
471 03:55:28.597032 INFO : End of read enable training
472 03:55:28.602118 INFO : End of fine write leveling
473 03:55:28.607712 INFO : End of Write leveling coarse delay
474 03:55:28.608304 INFO : Training has run successfully!
475 03:55:28.608773 Check phy result
476 03:55:28.613332 INFO : End of initialization
477 03:55:28.613830 INFO : End of read dq deskew training
478 03:55:28.619011 INFO : End of MPR read delay center optimization
479 03:55:28.624632 INFO : End of write delay center optimization
480 03:55:28.630196 INFO : End of read delay center optimization
481 03:55:28.630715 INFO : End of max read latency training
482 03:55:28.635707 INFO : Training has run successfully!
483 03:55:28.636249 1D training succeed
484 03:55:28.644917 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 03:55:28.692534 Check phy result
486 03:55:28.693042 INFO : End of initialization
487 03:55:28.714969 INFO : End of 2D read delay Voltage center optimization
488 03:55:28.733990 INFO : End of 2D read delay Voltage center optimization
489 03:55:28.786044 INFO : End of 2D write delay Voltage center optimization
490 03:55:28.835043 INFO : End of 2D write delay Voltage center optimization
491 03:55:28.840624 INFO : Training has run successfully!
492 03:55:28.841126
493 03:55:28.841596 channel==0
494 03:55:28.846197 RxClkDly_Margin_A0==78 ps 8
495 03:55:28.846690 TxDqDly_Margin_A0==98 ps 10
496 03:55:28.849521 RxClkDly_Margin_A1==88 ps 9
497 03:55:28.850011 TxDqDly_Margin_A1==88 ps 9
498 03:55:28.855037 TrainedVREFDQ_A0==74
499 03:55:28.855523 TrainedVREFDQ_A1==74
500 03:55:28.856020 VrefDac_Margin_A0==23
501 03:55:28.860655 DeviceVref_Margin_A0==40
502 03:55:28.861150 VrefDac_Margin_A1==23
503 03:55:28.866256 DeviceVref_Margin_A1==40
504 03:55:28.866744
505 03:55:28.867200
506 03:55:28.867645 channel==1
507 03:55:28.868124 RxClkDly_Margin_A0==78 ps 8
508 03:55:28.871844 TxDqDly_Margin_A0==98 ps 10
509 03:55:28.872356 RxClkDly_Margin_A1==78 ps 8
510 03:55:28.877495 TxDqDly_Margin_A1==88 ps 9
511 03:55:28.877997 TrainedVREFDQ_A0==78
512 03:55:28.878450 TrainedVREFDQ_A1==76
513 03:55:28.883038 VrefDac_Margin_A0==22
514 03:55:28.883527 DeviceVref_Margin_A0==36
515 03:55:28.888653 VrefDac_Margin_A1==22
516 03:55:28.889144 DeviceVref_Margin_A1==38
517 03:55:28.889591
518 03:55:28.894254 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 03:55:28.894749
520 03:55:28.922271 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000015 00000017 dram_vref_reg_value 0x 00000061
521 03:55:28.927876 2D training succeed
522 03:55:28.933545 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 03:55:28.934065 auto size-- 65535DDR cs0 size: 2048MB
524 03:55:28.939066 DDR cs1 size: 2048MB
525 03:55:28.939583 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 03:55:28.944645 cs0 DataBus test pass
527 03:55:28.945139 cs1 DataBus test pass
528 03:55:28.945598 cs0 AddrBus test pass
529 03:55:28.950271 cs1 AddrBus test pass
530 03:55:28.950833
531 03:55:28.951303 100bdlr_step_size ps== 478
532 03:55:28.951761 result report
533 03:55:28.955897 boot times 0Enable ddr reg access
534 03:55:28.963404 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 03:55:28.977212 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 03:55:29.631945 bl2z: ptr: 05129330, size: 00001e40
537 03:55:29.639354 0.0;M3 CHK:0;cm4_sp_mode 0
538 03:55:29.640027 MVN_1=0x00000000
539 03:55:29.640584 MVN_2=0x00000000
540 03:55:29.650952 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 03:55:29.651599 OPS=0x04
542 03:55:29.652253 ring efuse init
543 03:55:29.656492 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 03:55:29.657124 [0.017319 Inits done]
545 03:55:29.657673 secure task start!
546 03:55:29.664434 high task start!
547 03:55:29.665054 low task start!
548 03:55:29.665598 run into bl31
549 03:55:29.673035 NOTICE: BL31: v1.3(release):4fc40b1
550 03:55:29.680818 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 03:55:29.681453 NOTICE: BL31: G12A normal boot!
552 03:55:29.696436 NOTICE: BL31: BL33 decompress pass
553 03:55:29.702087 ERROR: Error initializing runtime service opteed_fast
554 03:55:31.096122 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 03:55:31.096888 bl2_stage_init 0x01
556 03:55:31.097443 bl2_stage_init 0x81
557 03:55:31.101566 hw id: 0x0000 - pwm id 0x01
558 03:55:31.102147 bl2_stage_init 0xc1
559 03:55:31.107203 bl2_stage_init 0x02
560 03:55:31.107790
561 03:55:31.108380 L0:00000000
562 03:55:31.108912 L1:00000703
563 03:55:31.109424 L2:00008067
564 03:55:31.109931 L3:15000000
565 03:55:31.112770 S1:00000000
566 03:55:31.113332 B2:20282000
567 03:55:31.113853 B1:a0f83180
568 03:55:31.114360
569 03:55:31.114882 TE: 71552
570 03:55:31.115392
571 03:55:31.118333 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 03:55:31.118904
573 03:55:31.124055 Board ID = 1
574 03:55:31.124644 Set cpu clk to 24M
575 03:55:31.125186 Set clk81 to 24M
576 03:55:31.129607 Use GP1_pll as DSU clk.
577 03:55:31.130208 DSU clk: 1200 Mhz
578 03:55:31.130748 CPU clk: 1200 MHz
579 03:55:31.135192 Set clk81 to 166.6M
580 03:55:31.140808 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 03:55:31.141386 board id: 1
582 03:55:31.147190 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 03:55:31.158799 fw parse done
584 03:55:31.164737 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 03:55:31.207220 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 03:55:31.218210 PIEI prepare done
587 03:55:31.218793 fastboot data load
588 03:55:31.219351 fastboot data verify
589 03:55:31.223757 verify result: 266
590 03:55:31.229367 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 03:55:31.229948 LPDDR4 probe
592 03:55:31.230474 ddr clk to 1584MHz
593 03:55:31.237376 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 03:55:31.274671
595 03:55:31.275300 dmc_version 0001
596 03:55:31.280603 Check phy result
597 03:55:31.287218 INFO : End of CA training
598 03:55:31.287802 INFO : End of initialization
599 03:55:31.292832 INFO : Training has run successfully!
600 03:55:31.293415 Check phy result
601 03:55:31.298417 INFO : End of initialization
602 03:55:31.298982 INFO : End of read enable training
603 03:55:31.304031 INFO : End of fine write leveling
604 03:55:31.309648 INFO : End of Write leveling coarse delay
605 03:55:31.310243 INFO : Training has run successfully!
606 03:55:31.310783 Check phy result
607 03:55:31.315235 INFO : End of initialization
608 03:55:31.315794 INFO : End of read dq deskew training
609 03:55:31.320866 INFO : End of MPR read delay center optimization
610 03:55:31.326478 INFO : End of write delay center optimization
611 03:55:31.332013 INFO : End of read delay center optimization
612 03:55:31.332609 INFO : End of max read latency training
613 03:55:31.337612 INFO : Training has run successfully!
614 03:55:31.338202 1D training succeed
615 03:55:31.346833 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 03:55:31.394518 Check phy result
617 03:55:31.395148 INFO : End of initialization
618 03:55:31.416859 INFO : End of 2D read delay Voltage center optimization
619 03:55:31.436022 INFO : End of 2D read delay Voltage center optimization
620 03:55:31.487841 INFO : End of 2D write delay Voltage center optimization
621 03:55:31.537153 INFO : End of 2D write delay Voltage center optimization
622 03:55:31.542709 INFO : Training has run successfully!
623 03:55:31.543306
624 03:55:31.543879 channel==0
625 03:55:31.548217 RxClkDly_Margin_A0==78 ps 8
626 03:55:31.548822 TxDqDly_Margin_A0==88 ps 9
627 03:55:31.551419 RxClkDly_Margin_A1==88 ps 9
628 03:55:31.552009 TxDqDly_Margin_A1==98 ps 10
629 03:55:31.557021 TrainedVREFDQ_A0==74
630 03:55:31.557617 TrainedVREFDQ_A1==75
631 03:55:31.558154 VrefDac_Margin_A0==22
632 03:55:31.562615 DeviceVref_Margin_A0==40
633 03:55:31.563187 VrefDac_Margin_A1==23
634 03:55:31.568428 DeviceVref_Margin_A1==39
635 03:55:31.569012
636 03:55:31.569546
637 03:55:31.570060 channel==1
638 03:55:31.570566 RxClkDly_Margin_A0==78 ps 8
639 03:55:31.573765 TxDqDly_Margin_A0==88 ps 9
640 03:55:31.574357 RxClkDly_Margin_A1==88 ps 9
641 03:55:31.579433 TxDqDly_Margin_A1==88 ps 9
642 03:55:31.580031 TrainedVREFDQ_A0==75
643 03:55:31.580569 TrainedVREFDQ_A1==78
644 03:55:31.585020 VrefDac_Margin_A0==22
645 03:55:31.585580 DeviceVref_Margin_A0==38
646 03:55:31.590563 VrefDac_Margin_A1==20
647 03:55:31.591119 DeviceVref_Margin_A1==36
648 03:55:31.591644
649 03:55:31.596443 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 03:55:31.597053
651 03:55:31.624137 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
652 03:55:31.629776 2D training succeed
653 03:55:31.635316 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 03:55:31.635904 auto size-- 65535DDR cs0 size: 2048MB
655 03:55:31.640924 DDR cs1 size: 2048MB
656 03:55:31.641511 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 03:55:31.646521 cs0 DataBus test pass
658 03:55:31.647093 cs1 DataBus test pass
659 03:55:31.647625 cs0 AddrBus test pass
660 03:55:31.652262 cs1 AddrBus test pass
661 03:55:31.652834
662 03:55:31.653376 100bdlr_step_size ps== 478
663 03:55:31.653914 result report
664 03:55:31.657690 boot times 0Enable ddr reg access
665 03:55:31.665158 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 03:55:31.679010 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 03:55:32.334069 bl2z: ptr: 05129330, size: 00001e40
668 03:55:32.341176 0.0;M3 CHK:0;cm4_sp_mode 0
669 03:55:32.341661 MVN_1=0x00000000
670 03:55:32.342083 MVN_2=0x00000000
671 03:55:32.352684 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 03:55:32.353140 OPS=0x04
673 03:55:32.353558 ring efuse init
674 03:55:32.358266 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 03:55:32.358716 [0.017319 Inits done]
676 03:55:32.359121 secure task start!
677 03:55:32.366142 high task start!
678 03:55:32.366573 low task start!
679 03:55:32.366979 run into bl31
680 03:55:32.374775 NOTICE: BL31: v1.3(release):4fc40b1
681 03:55:32.382537 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 03:55:32.382980 NOTICE: BL31: G12A normal boot!
683 03:55:32.398073 NOTICE: BL31: BL33 decompress pass
684 03:55:32.403255 ERROR: Error initializing runtime service opteed_fast
685 03:55:33.199233
686 03:55:33.199874
687 03:55:33.205026 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 03:55:33.205592
689 03:55:33.208487 Model: Libre Computer AML-S905D3-CC Solitude
690 03:55:33.355075 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 03:55:33.369579 DRAM: 2 GiB (effective 3.8 GiB)
692 03:55:33.471494 Core: 406 devices, 33 uclasses, devicetree: separate
693 03:55:33.477313 WDT: Not starting watchdog@f0d0
694 03:55:33.502463 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 03:55:33.514570 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 03:55:33.519534 ** Bad device specification mmc 0 **
697 03:55:33.529597 Card did not respond to voltage select! : -110
698 03:55:33.537209 ** Bad device specification mmc 0 **
699 03:55:33.537630 Couldn't find partition mmc 0
700 03:55:33.545549 Card did not respond to voltage select! : -110
701 03:55:33.551052 ** Bad device specification mmc 0 **
702 03:55:33.551468 Couldn't find partition mmc 0
703 03:55:33.556178 Error: could not access storage.
704 03:55:33.851783 Net: eth0: ethernet@ff3f0000
705 03:55:33.852297 starting USB...
706 03:55:34.097317 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 03:55:34.097928 Starting the controller
708 03:55:34.104268 USB XHCI 1.10
709 03:55:35.660561 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 03:55:35.668852 scanning usb for storage devices... 0 Storage Device(s) found
712 03:55:35.720323 Hit any key to stop autoboot: 1
713 03:55:35.721177 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 03:55:35.721778 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 03:55:35.722258 Setting prompt string to ['=>']
716 03:55:35.722738 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 03:55:35.734882 0
718 03:55:35.735758 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 03:55:35.836999 => setenv autoload no
721 03:55:35.837717 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 03:55:35.842528 setenv autoload no
724 03:55:35.944018 => setenv initrd_high 0xffffffff
725 03:55:35.944726 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 03:55:35.948931 setenv initrd_high 0xffffffff
728 03:55:36.050374 => setenv fdt_high 0xffffffff
729 03:55:36.051120 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 03:55:36.055386 setenv fdt_high 0xffffffff
732 03:55:36.156865 => dhcp
733 03:55:36.157603 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 03:55:36.161558 dhcp
735 03:55:37.267624 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 03:55:37.268246 Speed: 1000, full duplex
737 03:55:37.268678 BOOTP broadcast 1
738 03:55:37.276592 DHCP client bound to address 192.168.6.21 (8 ms)
740 03:55:37.378111 => setenv serverip 192.168.6.2
741 03:55:37.378817 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
742 03:55:37.382422 setenv serverip 192.168.6.2
744 03:55:37.483837 => tftpboot 0x01080000 937875/tftp-deploy-sut681ak/kernel/uImage
745 03:55:37.484585 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
746 03:55:37.491133 tftpboot 0x01080000 937875/tftp-deploy-sut681ak/kernel/uImage
747 03:55:37.491593 Speed: 1000, full duplex
748 03:55:37.492037 Using ethernet@ff3f0000 device
749 03:55:37.496923 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 03:55:37.502154 Filename '937875/tftp-deploy-sut681ak/kernel/uImage'.
751 03:55:37.506144 Load address: 0x1080000
752 03:55:40.330513 Loading: *############################ UDP wrong checksum 000000ff 0000fd64
753 03:55:40.359721 UDP wrong checksum 000000ff 00009357
754 03:55:42.480033 ###################### 63.4 MiB
755 03:55:42.480639 12.7 MiB/s
756 03:55:42.481073 done
757 03:55:42.484423 Bytes transferred = 66443840 (3f5da40 hex)
759 03:55:42.585947 => tftpboot 0x08000000 937875/tftp-deploy-sut681ak/ramdisk/ramdisk.cpio.gz.uboot
760 03:55:42.586864 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
761 03:55:42.593684 tftpboot 0x08000000 937875/tftp-deploy-sut681ak/ramdisk/ramdisk.cpio.gz.uboot
762 03:55:42.594174 Speed: 1000, full duplex
763 03:55:42.594592 Using ethernet@ff3f0000 device
764 03:55:42.599038 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
765 03:55:42.608822 Filename '937875/tftp-deploy-sut681ak/ramdisk/ramdisk.cpio.gz.uboot'.
766 03:55:42.609309 Load address: 0x8000000
767 03:55:43.801422 Loading: *# UDP wrong checksum 000000ff 000083a5
768 03:55:43.861499 UDP wrong checksum 000000ff 00001f98
769 03:55:49.900089 T ################################################ UDP wrong checksum 00000007 000082e3
770 03:55:54.900056 T UDP wrong checksum 00000007 000082e3
771 03:56:04.903355 T T UDP wrong checksum 00000007 000082e3
772 03:56:18.046145 T T UDP wrong checksum 000000ff 00005588
773 03:56:18.053188 UDP wrong checksum 000000ff 0000dd7a
774 03:56:19.349127 UDP wrong checksum 000000ff 00004e01
775 03:56:19.383335 UDP wrong checksum 000000ff 0000d2f3
776 03:56:24.907308 T T UDP wrong checksum 00000007 000082e3
777 03:56:29.331648 UDP wrong checksum 000000ff 0000788c
778 03:56:29.344824 UDP wrong checksum 000000ff 0000017f
779 03:56:38.613594 T T UDP wrong checksum 000000ff 0000a1b9
780 03:56:39.911187
781 03:56:39.911832 Retry count exceeded; starting again
783 03:56:39.913289 end: 2.4.3 bootloader-commands (duration 00:01:04) [common]
786 03:56:39.915181 end: 2.4 uboot-commands (duration 00:01:23) [common]
788 03:56:39.916753 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
790 03:56:39.917924 end: 2 uboot-action (duration 00:01:23) [common]
792 03:56:39.919538 Cleaning after the job
793 03:56:39.920157 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/937875/tftp-deploy-sut681ak/ramdisk
794 03:56:39.921627 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/937875/tftp-deploy-sut681ak/kernel
795 03:56:39.978317 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/937875/tftp-deploy-sut681ak/dtb
796 03:56:39.979171 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/937875/tftp-deploy-sut681ak/modules
797 03:56:40.010980 start: 4.1 power-off (timeout 00:00:30) [common]
798 03:56:40.011670 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
799 03:56:40.046116 >> OK - accepted request
800 03:56:40.048351 Returned 0 in 0 seconds
801 03:56:40.149388 end: 4.1 power-off (duration 00:00:00) [common]
803 03:56:40.150442 start: 4.2 read-feedback (timeout 00:10:00) [common]
804 03:56:40.151103 Listened to connection for namespace 'common' for up to 1s
805 03:56:41.152068 Finalising connection for namespace 'common'
806 03:56:41.152606 Disconnecting from shell: Finalise
807 03:56:41.152888 =>
808 03:56:41.253596 end: 4.2 read-feedback (duration 00:00:01) [common]
809 03:56:41.254137 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/937875
810 03:56:41.551794 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/937875
811 03:56:41.552443 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.