Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 03:48:14.417062 lava-dispatcher, installed at version: 2024.01
2 03:48:14.417863 start: 0 validate
3 03:48:14.418336 Start time: 2024-11-05 03:48:14.418305+00:00 (UTC)
4 03:48:14.418876 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 03:48:14.419407 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 03:48:14.462030 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 03:48:14.462697 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-77-g2e1b3cc9d7f7%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fkernel%2FImage exists
8 03:48:14.493334 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 03:48:14.493979 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-77-g2e1b3cc9d7f7%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 03:48:15.546668 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 03:48:15.547258 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-77-g2e1b3cc9d7f7%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fmodules.tar.xz exists
12 03:48:15.594358 validate duration: 1.18
14 03:48:15.595234 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 03:48:15.595566 start: 1.1 download-retry (timeout 00:10:00) [common]
16 03:48:15.595858 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 03:48:15.596504 Not decompressing ramdisk as can be used compressed.
18 03:48:15.596976 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 03:48:15.597214 saving as /var/lib/lava/dispatcher/tmp/938073/tftp-deploy-410tia7z/ramdisk/rootfs.cpio.gz
20 03:48:15.597468 total size: 8181887 (7 MB)
21 03:48:15.635109 progress 0 % (0 MB)
22 03:48:15.647867 progress 5 % (0 MB)
23 03:48:15.660425 progress 10 % (0 MB)
24 03:48:15.670094 progress 15 % (1 MB)
25 03:48:15.675764 progress 20 % (1 MB)
26 03:48:15.681743 progress 25 % (1 MB)
27 03:48:15.687198 progress 30 % (2 MB)
28 03:48:15.693237 progress 35 % (2 MB)
29 03:48:15.698760 progress 40 % (3 MB)
30 03:48:15.704911 progress 45 % (3 MB)
31 03:48:15.710534 progress 50 % (3 MB)
32 03:48:15.716800 progress 55 % (4 MB)
33 03:48:15.722472 progress 60 % (4 MB)
34 03:48:15.728388 progress 65 % (5 MB)
35 03:48:15.733850 progress 70 % (5 MB)
36 03:48:15.739611 progress 75 % (5 MB)
37 03:48:15.745046 progress 80 % (6 MB)
38 03:48:15.750928 progress 85 % (6 MB)
39 03:48:15.756492 progress 90 % (7 MB)
40 03:48:15.762302 progress 95 % (7 MB)
41 03:48:15.767623 progress 100 % (7 MB)
42 03:48:15.768461 7 MB downloaded in 0.17 s (45.64 MB/s)
43 03:48:15.769097 end: 1.1.1 http-download (duration 00:00:00) [common]
45 03:48:15.770139 end: 1.1 download-retry (duration 00:00:00) [common]
46 03:48:15.770478 start: 1.2 download-retry (timeout 00:10:00) [common]
47 03:48:15.770799 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 03:48:15.771339 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-77-g2e1b3cc9d7f7/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/kernel/Image
49 03:48:15.771644 saving as /var/lib/lava/dispatcher/tmp/938073/tftp-deploy-410tia7z/kernel/Image
50 03:48:15.771897 total size: 39424512 (37 MB)
51 03:48:15.772170 No compression specified
52 03:48:15.808648 progress 0 % (0 MB)
53 03:48:15.836612 progress 5 % (1 MB)
54 03:48:15.864295 progress 10 % (3 MB)
55 03:48:15.889907 progress 15 % (5 MB)
56 03:48:15.916802 progress 20 % (7 MB)
57 03:48:15.943086 progress 25 % (9 MB)
58 03:48:15.968775 progress 30 % (11 MB)
59 03:48:15.995548 progress 35 % (13 MB)
60 03:48:16.021152 progress 40 % (15 MB)
61 03:48:16.048419 progress 45 % (16 MB)
62 03:48:16.074094 progress 50 % (18 MB)
63 03:48:16.099567 progress 55 % (20 MB)
64 03:48:16.124841 progress 60 % (22 MB)
65 03:48:16.151536 progress 65 % (24 MB)
66 03:48:16.177551 progress 70 % (26 MB)
67 03:48:16.203157 progress 75 % (28 MB)
68 03:48:16.228789 progress 80 % (30 MB)
69 03:48:16.254929 progress 85 % (31 MB)
70 03:48:16.280577 progress 90 % (33 MB)
71 03:48:16.306135 progress 95 % (35 MB)
72 03:48:16.331262 progress 100 % (37 MB)
73 03:48:16.331861 37 MB downloaded in 0.56 s (67.15 MB/s)
74 03:48:16.332395 end: 1.2.1 http-download (duration 00:00:01) [common]
76 03:48:16.333226 end: 1.2 download-retry (duration 00:00:01) [common]
77 03:48:16.333502 start: 1.3 download-retry (timeout 00:09:59) [common]
78 03:48:16.333767 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 03:48:16.334281 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-77-g2e1b3cc9d7f7/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 03:48:16.334917 saving as /var/lib/lava/dispatcher/tmp/938073/tftp-deploy-410tia7z/dtb/meson-g12b-a311d-libretech-cc.dtb
81 03:48:16.335130 total size: 54703 (0 MB)
82 03:48:16.335343 No compression specified
83 03:48:16.371724 progress 59 % (0 MB)
84 03:48:16.372885 progress 100 % (0 MB)
85 03:48:16.373541 0 MB downloaded in 0.04 s (1.36 MB/s)
86 03:48:16.374075 end: 1.3.1 http-download (duration 00:00:00) [common]
88 03:48:16.375031 end: 1.3 download-retry (duration 00:00:00) [common]
89 03:48:16.375304 start: 1.4 download-retry (timeout 00:09:59) [common]
90 03:48:16.375592 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 03:48:16.376194 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-77-g2e1b3cc9d7f7/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/modules.tar.xz
92 03:48:16.376520 saving as /var/lib/lava/dispatcher/tmp/938073/tftp-deploy-410tia7z/modules/modules.tar
93 03:48:16.376741 total size: 11765612 (11 MB)
94 03:48:16.376963 Using unxz to decompress xz
95 03:48:16.412547 progress 0 % (0 MB)
96 03:48:16.494565 progress 5 % (0 MB)
97 03:48:16.590866 progress 10 % (1 MB)
98 03:48:16.707880 progress 15 % (1 MB)
99 03:48:16.825855 progress 20 % (2 MB)
100 03:48:16.922639 progress 25 % (2 MB)
101 03:48:17.017385 progress 30 % (3 MB)
102 03:48:17.115736 progress 35 % (3 MB)
103 03:48:17.212022 progress 40 % (4 MB)
104 03:48:17.303160 progress 45 % (5 MB)
105 03:48:17.405306 progress 50 % (5 MB)
106 03:48:17.503482 progress 55 % (6 MB)
107 03:48:17.605836 progress 60 % (6 MB)
108 03:48:17.704653 progress 65 % (7 MB)
109 03:48:17.804610 progress 70 % (7 MB)
110 03:48:17.904451 progress 75 % (8 MB)
111 03:48:18.004866 progress 80 % (9 MB)
112 03:48:18.101812 progress 85 % (9 MB)
113 03:48:18.202286 progress 90 % (10 MB)
114 03:48:18.296955 progress 95 % (10 MB)
115 03:48:18.389349 progress 100 % (11 MB)
116 03:48:18.401465 11 MB downloaded in 2.02 s (5.54 MB/s)
117 03:48:18.402502 end: 1.4.1 http-download (duration 00:00:02) [common]
119 03:48:18.404340 end: 1.4 download-retry (duration 00:00:02) [common]
120 03:48:18.404979 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 03:48:18.405598 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 03:48:18.406172 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 03:48:18.406735 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 03:48:18.407812 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o
125 03:48:18.408798 makedir: /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin
126 03:48:18.409594 makedir: /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/tests
127 03:48:18.410337 makedir: /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/results
128 03:48:18.411016 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-add-keys
129 03:48:18.412101 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-add-sources
130 03:48:18.413170 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-background-process-start
131 03:48:18.414286 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-background-process-stop
132 03:48:18.415418 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-common-functions
133 03:48:18.416504 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-echo-ipv4
134 03:48:18.417565 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-install-packages
135 03:48:18.418664 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-installed-packages
136 03:48:18.419723 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-os-build
137 03:48:18.420813 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-probe-channel
138 03:48:18.421836 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-probe-ip
139 03:48:18.422890 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-target-ip
140 03:48:18.423955 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-target-mac
141 03:48:18.425029 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-target-storage
142 03:48:18.426058 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-test-case
143 03:48:18.427067 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-test-event
144 03:48:18.428250 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-test-feedback
145 03:48:18.429351 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-test-raise
146 03:48:18.430374 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-test-reference
147 03:48:18.431375 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-test-runner
148 03:48:18.432480 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-test-set
149 03:48:18.433512 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-test-shell
150 03:48:18.434538 Updating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-install-packages (oe)
151 03:48:18.435584 Updating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/bin/lava-installed-packages (oe)
152 03:48:18.436567 Creating /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/environment
153 03:48:18.437410 LAVA metadata
154 03:48:18.437970 - LAVA_JOB_ID=938073
155 03:48:18.438449 - LAVA_DISPATCHER_IP=192.168.6.2
156 03:48:18.439194 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 03:48:18.441251 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 03:48:18.441927 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 03:48:18.442396 skipped lava-vland-overlay
160 03:48:18.442935 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 03:48:18.443502 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 03:48:18.443976 skipped lava-multinode-overlay
163 03:48:18.444580 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 03:48:18.445141 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 03:48:18.445669 Loading test definitions
166 03:48:18.446336 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 03:48:18.446849 Using /lava-938073 at stage 0
168 03:48:18.449319 uuid=938073_1.5.2.4.1 testdef=None
169 03:48:18.449956 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 03:48:18.450528 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 03:48:18.454256 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 03:48:18.455873 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 03:48:18.460359 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 03:48:18.461242 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 03:48:18.463535 runner path: /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/0/tests/0_dmesg test_uuid 938073_1.5.2.4.1
178 03:48:18.464146 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 03:48:18.464977 Creating lava-test-runner.conf files
181 03:48:18.465205 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/938073/lava-overlay-gf5d1e0o/lava-938073/0 for stage 0
182 03:48:18.465585 - 0_dmesg
183 03:48:18.465948 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 03:48:18.466257 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 03:48:18.490913 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 03:48:18.491332 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 03:48:18.491599 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 03:48:18.491865 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 03:48:18.492164 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 03:48:19.488024 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 03:48:19.488529 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 03:48:19.488819 extracting modules file /var/lib/lava/dispatcher/tmp/938073/tftp-deploy-410tia7z/modules/modules.tar to /var/lib/lava/dispatcher/tmp/938073/extract-overlay-ramdisk-9n9b8yzn/ramdisk
193 03:48:20.858190 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 03:48:20.858656 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 03:48:20.858931 [common] Applying overlay /var/lib/lava/dispatcher/tmp/938073/compress-overlay-oajvl634/overlay-1.5.2.5.tar.gz to ramdisk
196 03:48:20.859143 [common] Applying overlay /var/lib/lava/dispatcher/tmp/938073/compress-overlay-oajvl634/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/938073/extract-overlay-ramdisk-9n9b8yzn/ramdisk
197 03:48:20.889814 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 03:48:20.890231 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 03:48:20.890498 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 03:48:20.890725 Converting downloaded kernel to a uImage
201 03:48:20.891027 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/938073/tftp-deploy-410tia7z/kernel/Image /var/lib/lava/dispatcher/tmp/938073/tftp-deploy-410tia7z/kernel/uImage
202 03:48:21.291629 output: Image Name:
203 03:48:21.292091 output: Created: Tue Nov 5 03:48:20 2024
204 03:48:21.292313 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 03:48:21.292518 output: Data Size: 39424512 Bytes = 38500.50 KiB = 37.60 MiB
206 03:48:21.292717 output: Load Address: 01080000
207 03:48:21.292916 output: Entry Point: 01080000
208 03:48:21.293112 output:
209 03:48:21.293443 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 03:48:21.293707 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 03:48:21.293974 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 03:48:21.294223 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 03:48:21.294475 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 03:48:21.294726 Building ramdisk /var/lib/lava/dispatcher/tmp/938073/extract-overlay-ramdisk-9n9b8yzn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/938073/extract-overlay-ramdisk-9n9b8yzn/ramdisk
215 03:48:23.944292 >> 188260 blocks
216 03:48:32.340731 Adding RAMdisk u-boot header.
217 03:48:32.341449 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/938073/extract-overlay-ramdisk-9n9b8yzn/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/938073/extract-overlay-ramdisk-9n9b8yzn/ramdisk.cpio.gz.uboot
218 03:48:32.661281 output: Image Name:
219 03:48:32.661708 output: Created: Tue Nov 5 03:48:32 2024
220 03:48:32.661917 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 03:48:32.662121 output: Data Size: 26757099 Bytes = 26129.98 KiB = 25.52 MiB
222 03:48:32.662321 output: Load Address: 00000000
223 03:48:32.662520 output: Entry Point: 00000000
224 03:48:32.662715 output:
225 03:48:32.663387 rename /var/lib/lava/dispatcher/tmp/938073/extract-overlay-ramdisk-9n9b8yzn/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/938073/tftp-deploy-410tia7z/ramdisk/ramdisk.cpio.gz.uboot
226 03:48:32.663806 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 03:48:32.664254 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 03:48:32.664888 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 03:48:32.665386 No LXC device requested
230 03:48:32.665932 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 03:48:32.666480 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 03:48:32.667018 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 03:48:32.667466 Checking files for TFTP limit of 4294967296 bytes.
234 03:48:32.670391 end: 1 tftp-deploy (duration 00:00:17) [common]
235 03:48:32.671010 start: 2 uboot-action (timeout 00:05:00) [common]
236 03:48:32.671581 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 03:48:32.672173 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 03:48:32.672782 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 03:48:32.673371 Using kernel file from prepare-kernel: 938073/tftp-deploy-410tia7z/kernel/uImage
240 03:48:32.674032 substitutions:
241 03:48:32.674478 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 03:48:32.674919 - {DTB_ADDR}: 0x01070000
243 03:48:32.675355 - {DTB}: 938073/tftp-deploy-410tia7z/dtb/meson-g12b-a311d-libretech-cc.dtb
244 03:48:32.675794 - {INITRD}: 938073/tftp-deploy-410tia7z/ramdisk/ramdisk.cpio.gz.uboot
245 03:48:32.676265 - {KERNEL_ADDR}: 0x01080000
246 03:48:32.676701 - {KERNEL}: 938073/tftp-deploy-410tia7z/kernel/uImage
247 03:48:32.677133 - {LAVA_MAC}: None
248 03:48:32.677609 - {PRESEED_CONFIG}: None
249 03:48:32.678041 - {PRESEED_LOCAL}: None
250 03:48:32.678472 - {RAMDISK_ADDR}: 0x08000000
251 03:48:32.678902 - {RAMDISK}: 938073/tftp-deploy-410tia7z/ramdisk/ramdisk.cpio.gz.uboot
252 03:48:32.679337 - {ROOT_PART}: None
253 03:48:32.679765 - {ROOT}: None
254 03:48:32.680228 - {SERVER_IP}: 192.168.6.2
255 03:48:32.680662 - {TEE_ADDR}: 0x83000000
256 03:48:32.681091 - {TEE}: None
257 03:48:32.681520 Parsed boot commands:
258 03:48:32.681936 - setenv autoload no
259 03:48:32.682360 - setenv initrd_high 0xffffffff
260 03:48:32.682783 - setenv fdt_high 0xffffffff
261 03:48:32.683207 - dhcp
262 03:48:32.683632 - setenv serverip 192.168.6.2
263 03:48:32.684084 - tftpboot 0x01080000 938073/tftp-deploy-410tia7z/kernel/uImage
264 03:48:32.684515 - tftpboot 0x08000000 938073/tftp-deploy-410tia7z/ramdisk/ramdisk.cpio.gz.uboot
265 03:48:32.684942 - tftpboot 0x01070000 938073/tftp-deploy-410tia7z/dtb/meson-g12b-a311d-libretech-cc.dtb
266 03:48:32.685369 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 03:48:32.685801 - bootm 0x01080000 0x08000000 0x01070000
268 03:48:32.686335 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 03:48:32.687951 start: 2.3 connect-device (timeout 00:05:00) [common]
271 03:48:32.688462 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 03:48:32.703924 Setting prompt string to ['lava-test: # ']
273 03:48:32.705592 end: 2.3 connect-device (duration 00:00:00) [common]
274 03:48:32.706242 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 03:48:32.706889 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 03:48:32.707540 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 03:48:32.708359 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 03:48:32.745197 >> OK - accepted request
279 03:48:32.747417 Returned 0 in 0 seconds
280 03:48:32.848620 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 03:48:32.850309 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 03:48:32.850900 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 03:48:32.851454 Setting prompt string to ['Hit any key to stop autoboot']
285 03:48:32.851951 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 03:48:32.853715 Trying 192.168.56.21...
287 03:48:32.854227 Connected to conserv1.
288 03:48:32.854691 Escape character is '^]'.
289 03:48:32.855162
290 03:48:32.855632 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 03:48:32.856144
292 03:48:44.075706 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 03:48:44.076453 bl2_stage_init 0x01
294 03:48:44.076938 bl2_stage_init 0x81
295 03:48:44.081337 hw id: 0x0000 - pwm id 0x01
296 03:48:44.081927 bl2_stage_init 0xc1
297 03:48:44.082396 bl2_stage_init 0x02
298 03:48:44.082847
299 03:48:44.086848 L0:00000000
300 03:48:44.087378 L1:20000703
301 03:48:44.087831 L2:00008067
302 03:48:44.088308 L3:14000000
303 03:48:44.089679 B2:00402000
304 03:48:44.090152 B1:e0f83180
305 03:48:44.090585
306 03:48:44.091020 TE: 58167
307 03:48:44.091450
308 03:48:44.100881 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 03:48:44.101416
310 03:48:44.101852 Board ID = 1
311 03:48:44.102287 Set A53 clk to 24M
312 03:48:44.102714 Set A73 clk to 24M
313 03:48:44.106416 Set clk81 to 24M
314 03:48:44.106922 A53 clk: 1200 MHz
315 03:48:44.107375 A73 clk: 1200 MHz
316 03:48:44.109919 CLK81: 166.6M
317 03:48:44.110394 smccc: 00012abd
318 03:48:44.115531 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 03:48:44.121069 board id: 1
320 03:48:44.126344 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 03:48:44.137047 fw parse done
322 03:48:44.142988 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 03:48:44.185501 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 03:48:44.196469 PIEI prepare done
325 03:48:44.197019 fastboot data load
326 03:48:44.197474 fastboot data verify
327 03:48:44.202077 verify result: 266
328 03:48:44.207596 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 03:48:44.208186 LPDDR4 probe
330 03:48:44.208655 ddr clk to 1584MHz
331 03:48:44.215626 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 03:48:44.252882
333 03:48:44.253500 dmc_version 0001
334 03:48:44.259506 Check phy result
335 03:48:44.265393 INFO : End of CA training
336 03:48:44.265924 INFO : End of initialization
337 03:48:44.271079 INFO : Training has run successfully!
338 03:48:44.271604 Check phy result
339 03:48:44.276578 INFO : End of initialization
340 03:48:44.277112 INFO : End of read enable training
341 03:48:44.279885 INFO : End of fine write leveling
342 03:48:44.285450 INFO : End of Write leveling coarse delay
343 03:48:44.291109 INFO : Training has run successfully!
344 03:48:44.291641 Check phy result
345 03:48:44.292129 INFO : End of initialization
346 03:48:44.296642 INFO : End of read dq deskew training
347 03:48:44.302244 INFO : End of MPR read delay center optimization
348 03:48:44.302798 INFO : End of write delay center optimization
349 03:48:44.307873 INFO : End of read delay center optimization
350 03:48:44.313423 INFO : End of max read latency training
351 03:48:44.313945 INFO : Training has run successfully!
352 03:48:44.319123 1D training succeed
353 03:48:44.325014 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 03:48:44.372625 Check phy result
355 03:48:44.373243 INFO : End of initialization
356 03:48:44.395277 INFO : End of 2D read delay Voltage center optimization
357 03:48:44.415473 INFO : End of 2D read delay Voltage center optimization
358 03:48:44.467587 INFO : End of 2D write delay Voltage center optimization
359 03:48:44.516920 INFO : End of 2D write delay Voltage center optimization
360 03:48:44.522594 INFO : Training has run successfully!
361 03:48:44.523175
362 03:48:44.523634 channel==0
363 03:48:44.528227 RxClkDly_Margin_A0==88 ps 9
364 03:48:44.528745 TxDqDly_Margin_A0==98 ps 10
365 03:48:44.531567 RxClkDly_Margin_A1==88 ps 9
366 03:48:44.532106 TxDqDly_Margin_A1==98 ps 10
367 03:48:44.537012 TrainedVREFDQ_A0==74
368 03:48:44.537552 TrainedVREFDQ_A1==74
369 03:48:44.538002 VrefDac_Margin_A0==24
370 03:48:44.542610 DeviceVref_Margin_A0==40
371 03:48:44.543153 VrefDac_Margin_A1==24
372 03:48:44.548273 DeviceVref_Margin_A1==40
373 03:48:44.548833
374 03:48:44.549296
375 03:48:44.549740 channel==1
376 03:48:44.550179 RxClkDly_Margin_A0==98 ps 10
377 03:48:44.551711 TxDqDly_Margin_A0==98 ps 10
378 03:48:44.557221 RxClkDly_Margin_A1==98 ps 10
379 03:48:44.557773 TxDqDly_Margin_A1==88 ps 9
380 03:48:44.558224 TrainedVREFDQ_A0==77
381 03:48:44.562873 TrainedVREFDQ_A1==77
382 03:48:44.563405 VrefDac_Margin_A0==22
383 03:48:44.568419 DeviceVref_Margin_A0==37
384 03:48:44.568990 VrefDac_Margin_A1==24
385 03:48:44.569453 DeviceVref_Margin_A1==37
386 03:48:44.569903
387 03:48:44.573975 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 03:48:44.574542
389 03:48:44.607535 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 03:48:44.608245 2D training succeed
391 03:48:44.613191 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 03:48:44.618790 auto size-- 65535DDR cs0 size: 2048MB
393 03:48:44.619334 DDR cs1 size: 2048MB
394 03:48:44.624352 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 03:48:44.624894 cs0 DataBus test pass
396 03:48:44.625337 cs1 DataBus test pass
397 03:48:44.629978 cs0 AddrBus test pass
398 03:48:44.630516 cs1 AddrBus test pass
399 03:48:44.630960
400 03:48:44.635574 100bdlr_step_size ps== 420
401 03:48:44.636170 result report
402 03:48:44.636616 boot times 0Enable ddr reg access
403 03:48:44.645402 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 03:48:44.658972 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 03:48:45.232523 0.0;M3 CHK:0;cm4_sp_mode 0
406 03:48:45.233142 MVN_1=0x00000000
407 03:48:45.238161 MVN_2=0x00000000
408 03:48:45.243793 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 03:48:45.244380 OPS=0x10
410 03:48:45.244849 ring efuse init
411 03:48:45.245298 chipver efuse init
412 03:48:45.249391 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 03:48:45.254998 [0.018961 Inits done]
414 03:48:45.255548 secure task start!
415 03:48:45.256037 high task start!
416 03:48:45.259600 low task start!
417 03:48:45.260163 run into bl31
418 03:48:45.266213 NOTICE: BL31: v1.3(release):4fc40b1
419 03:48:45.274000 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 03:48:45.274549 NOTICE: BL31: G12A normal boot!
421 03:48:45.299381 NOTICE: BL31: BL33 decompress pass
422 03:48:45.305045 ERROR: Error initializing runtime service opteed_fast
423 03:48:46.537965
424 03:48:46.538657
425 03:48:46.546442 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 03:48:46.546989
427 03:48:46.547453 Model: Libre Computer AML-A311D-CC Alta
428 03:48:46.754430 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 03:48:46.778086 DRAM: 2 GiB (effective 3.8 GiB)
430 03:48:46.921228 Core: 408 devices, 31 uclasses, devicetree: separate
431 03:48:46.927621 WDT: Not starting watchdog@f0d0
432 03:48:46.959421 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 03:48:46.971860 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 03:48:46.976868 ** Bad device specification mmc 0 **
435 03:48:46.987175 Card did not respond to voltage select! : -110
436 03:48:46.994842 ** Bad device specification mmc 0 **
437 03:48:46.995432 Couldn't find partition mmc 0
438 03:48:47.003197 Card did not respond to voltage select! : -110
439 03:48:47.008687 ** Bad device specification mmc 0 **
440 03:48:47.009245 Couldn't find partition mmc 0
441 03:48:47.013766 Error: could not access storage.
442 03:48:48.275912 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 03:48:48.276364 bl2_stage_init 0x01
444 03:48:48.276603 bl2_stage_init 0x81
445 03:48:48.281484 hw id: 0x0000 - pwm id 0x01
446 03:48:48.281915 bl2_stage_init 0xc1
447 03:48:48.282242 bl2_stage_init 0x02
448 03:48:48.282561
449 03:48:48.287012 L0:00000000
450 03:48:48.287422 L1:20000703
451 03:48:48.287667 L2:00008067
452 03:48:48.287881 L3:14000000
453 03:48:48.292653 B2:00402000
454 03:48:48.293061 B1:e0f83180
455 03:48:48.293385
456 03:48:48.293698 TE: 58124
457 03:48:48.294003
458 03:48:48.298213 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 03:48:48.298616
460 03:48:48.298851 Board ID = 1
461 03:48:48.303799 Set A53 clk to 24M
462 03:48:48.304116 Set A73 clk to 24M
463 03:48:48.304328 Set clk81 to 24M
464 03:48:48.309469 A53 clk: 1200 MHz
465 03:48:48.309865 A73 clk: 1200 MHz
466 03:48:48.310190 CLK81: 166.6M
467 03:48:48.310492 smccc: 00012a92
468 03:48:48.315084 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 03:48:48.320651 board id: 1
470 03:48:48.326580 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 03:48:48.337276 fw parse done
472 03:48:48.343142 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 03:48:48.385802 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 03:48:48.396686 PIEI prepare done
475 03:48:48.397011 fastboot data load
476 03:48:48.397228 fastboot data verify
477 03:48:48.402329 verify result: 266
478 03:48:48.407914 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 03:48:48.408237 LPDDR4 probe
480 03:48:48.408450 ddr clk to 1584MHz
481 03:48:48.415924 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 03:48:48.452323
483 03:48:48.452691 dmc_version 0001
484 03:48:48.459847 Check phy result
485 03:48:48.465723 INFO : End of CA training
486 03:48:48.466018 INFO : End of initialization
487 03:48:48.471328 INFO : Training has run successfully!
488 03:48:48.471769 Check phy result
489 03:48:48.476914 INFO : End of initialization
490 03:48:48.477207 INFO : End of read enable training
491 03:48:48.482600 INFO : End of fine write leveling
492 03:48:48.488256 INFO : End of Write leveling coarse delay
493 03:48:48.488830 INFO : Training has run successfully!
494 03:48:48.489306 Check phy result
495 03:48:48.493752 INFO : End of initialization
496 03:48:48.494307 INFO : End of read dq deskew training
497 03:48:48.499344 INFO : End of MPR read delay center optimization
498 03:48:48.504891 INFO : End of write delay center optimization
499 03:48:48.510594 INFO : End of read delay center optimization
500 03:48:48.511145 INFO : End of max read latency training
501 03:48:48.516200 INFO : Training has run successfully!
502 03:48:48.516712 1D training succeed
503 03:48:48.525293 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 03:48:48.573021 Check phy result
505 03:48:48.573618 INFO : End of initialization
506 03:48:48.594768 INFO : End of 2D read delay Voltage center optimization
507 03:48:48.613392 INFO : End of 2D read delay Voltage center optimization
508 03:48:48.666076 INFO : End of 2D write delay Voltage center optimization
509 03:48:48.715574 INFO : End of 2D write delay Voltage center optimization
510 03:48:48.720995 INFO : Training has run successfully!
511 03:48:48.721546
512 03:48:48.722030 channel==0
513 03:48:48.726610 RxClkDly_Margin_A0==88 ps 9
514 03:48:48.727120 TxDqDly_Margin_A0==98 ps 10
515 03:48:48.732219 RxClkDly_Margin_A1==88 ps 9
516 03:48:48.732599 TxDqDly_Margin_A1==98 ps 10
517 03:48:48.732833 TrainedVREFDQ_A0==74
518 03:48:48.737850 TrainedVREFDQ_A1==75
519 03:48:48.738205 VrefDac_Margin_A0==25
520 03:48:48.738434 DeviceVref_Margin_A0==40
521 03:48:48.743414 VrefDac_Margin_A1==25
522 03:48:48.743898 DeviceVref_Margin_A1==39
523 03:48:48.744311
524 03:48:48.744679
525 03:48:48.749021 channel==1
526 03:48:48.749372 RxClkDly_Margin_A0==88 ps 9
527 03:48:48.749632 TxDqDly_Margin_A0==88 ps 9
528 03:48:48.754686 RxClkDly_Margin_A1==88 ps 9
529 03:48:48.755169 TxDqDly_Margin_A1==88 ps 9
530 03:48:48.760202 TrainedVREFDQ_A0==74
531 03:48:48.760552 TrainedVREFDQ_A1==77
532 03:48:48.760777 VrefDac_Margin_A0==23
533 03:48:48.765808 DeviceVref_Margin_A0==40
534 03:48:48.766162 VrefDac_Margin_A1==24
535 03:48:48.771401 DeviceVref_Margin_A1==37
536 03:48:48.771754
537 03:48:48.772005 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 03:48:48.772234
539 03:48:48.805028 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
540 03:48:48.805443 2D training succeed
541 03:48:48.810679 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 03:48:48.816230 auto size-- 65535DDR cs0 size: 2048MB
543 03:48:48.816602 DDR cs1 size: 2048MB
544 03:48:48.821820 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 03:48:48.822199 cs0 DataBus test pass
546 03:48:48.827436 cs1 DataBus test pass
547 03:48:48.827811 cs0 AddrBus test pass
548 03:48:48.828076 cs1 AddrBus test pass
549 03:48:48.828308
550 03:48:48.833039 100bdlr_step_size ps== 420
551 03:48:48.833401 result report
552 03:48:48.838685 boot times 0Enable ddr reg access
553 03:48:48.843597 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 03:48:48.856533 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 03:48:49.430920 0.0;M3 CHK:0;cm4_sp_mode 0
556 03:48:49.431477 MVN_1=0x00000000
557 03:48:49.436473 MVN_2=0x00000000
558 03:48:49.442232 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 03:48:49.442574 OPS=0x10
560 03:48:49.442799 ring efuse init
561 03:48:49.443011 chipver efuse init
562 03:48:49.447861 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 03:48:49.453498 [0.018961 Inits done]
564 03:48:49.453814 secure task start!
565 03:48:49.454031 high task start!
566 03:48:49.457310 low task start!
567 03:48:49.457616 run into bl31
568 03:48:49.464732 NOTICE: BL31: v1.3(release):4fc40b1
569 03:48:49.472211 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 03:48:49.472776 NOTICE: BL31: G12A normal boot!
571 03:48:49.497877 NOTICE: BL31: BL33 decompress pass
572 03:48:49.503002 ERROR: Error initializing runtime service opteed_fast
573 03:48:50.736539
574 03:48:50.737080
575 03:48:50.744389 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 03:48:50.745029
577 03:48:50.745390 Model: Libre Computer AML-A311D-CC Alta
578 03:48:50.952814 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 03:48:50.976603 DRAM: 2 GiB (effective 3.8 GiB)
580 03:48:51.120157 Core: 408 devices, 31 uclasses, devicetree: separate
581 03:48:51.124791 WDT: Not starting watchdog@f0d0
582 03:48:51.158044 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 03:48:51.170666 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 03:48:51.174295 ** Bad device specification mmc 0 **
585 03:48:51.185687 Card did not respond to voltage select! : -110
586 03:48:51.192511 ** Bad device specification mmc 0 **
587 03:48:51.192852 Couldn't find partition mmc 0
588 03:48:51.201592 Card did not respond to voltage select! : -110
589 03:48:51.207101 ** Bad device specification mmc 0 **
590 03:48:51.207426 Couldn't find partition mmc 0
591 03:48:51.211970 Error: could not access storage.
592 03:48:51.554205 Net: eth0: ethernet@ff3f0000
593 03:48:51.554615 starting USB...
594 03:48:51.806795 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 03:48:51.807203 Starting the controller
596 03:48:51.812759 USB XHCI 1.10
597 03:48:53.527723 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 03:48:53.528176 bl2_stage_init 0x01
599 03:48:53.528427 bl2_stage_init 0x81
600 03:48:53.533231 hw id: 0x0000 - pwm id 0x01
601 03:48:53.533549 bl2_stage_init 0xc1
602 03:48:53.533778 bl2_stage_init 0x02
603 03:48:53.534006
604 03:48:53.538929 L0:00000000
605 03:48:53.539251 L1:20000703
606 03:48:53.539477 L2:00008067
607 03:48:53.539702 L3:14000000
608 03:48:53.541781 B2:00402000
609 03:48:53.542100 B1:e0f83180
610 03:48:53.542327
611 03:48:53.542554 TE: 58159
612 03:48:53.542774
613 03:48:53.552857 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 03:48:53.553214
615 03:48:53.553452 Board ID = 1
616 03:48:53.553678 Set A53 clk to 24M
617 03:48:53.553894 Set A73 clk to 24M
618 03:48:53.558537 Set clk81 to 24M
619 03:48:53.558874 A53 clk: 1200 MHz
620 03:48:53.559103 A73 clk: 1200 MHz
621 03:48:53.562643 CLK81: 166.6M
622 03:48:53.562958 smccc: 00012ab5
623 03:48:53.567433 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 03:48:53.573006 board id: 1
625 03:48:53.577601 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 03:48:53.589014 fw parse done
627 03:48:53.594857 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 03:48:53.636701 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 03:48:53.648528 PIEI prepare done
630 03:48:53.649158 fastboot data load
631 03:48:53.649709 fastboot data verify
632 03:48:53.654186 verify result: 266
633 03:48:53.659812 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 03:48:53.660460 LPDDR4 probe
635 03:48:53.660999 ddr clk to 1584MHz
636 03:48:53.666883 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 03:48:53.704633
638 03:48:53.705253 dmc_version 0001
639 03:48:53.711530 Check phy result
640 03:48:53.717467 INFO : End of CA training
641 03:48:53.717834 INFO : End of initialization
642 03:48:53.723229 INFO : Training has run successfully!
643 03:48:53.723601 Check phy result
644 03:48:53.728739 INFO : End of initialization
645 03:48:53.729093 INFO : End of read enable training
646 03:48:53.734312 INFO : End of fine write leveling
647 03:48:53.739879 INFO : End of Write leveling coarse delay
648 03:48:53.740256 INFO : Training has run successfully!
649 03:48:53.740497 Check phy result
650 03:48:53.745471 INFO : End of initialization
651 03:48:53.745816 INFO : End of read dq deskew training
652 03:48:53.751206 INFO : End of MPR read delay center optimization
653 03:48:53.756691 INFO : End of write delay center optimization
654 03:48:53.762300 INFO : End of read delay center optimization
655 03:48:53.762662 INFO : End of max read latency training
656 03:48:53.768040 INFO : Training has run successfully!
657 03:48:53.768640 1D training succeed
658 03:48:53.776241 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 03:48:53.823765 Check phy result
660 03:48:53.824440 INFO : End of initialization
661 03:48:53.845928 INFO : End of 2D read delay Voltage center optimization
662 03:48:53.864621 INFO : End of 2D read delay Voltage center optimization
663 03:48:53.916958 INFO : End of 2D write delay Voltage center optimization
664 03:48:53.966697 INFO : End of 2D write delay Voltage center optimization
665 03:48:53.972255 INFO : Training has run successfully!
666 03:48:53.972587
667 03:48:53.972825 channel==0
668 03:48:53.977862 RxClkDly_Margin_A0==88 ps 9
669 03:48:53.978191 TxDqDly_Margin_A0==98 ps 10
670 03:48:53.983479 RxClkDly_Margin_A1==88 ps 9
671 03:48:53.983805 TxDqDly_Margin_A1==98 ps 10
672 03:48:53.984086 TrainedVREFDQ_A0==74
673 03:48:53.989104 TrainedVREFDQ_A1==74
674 03:48:53.989447 VrefDac_Margin_A0==25
675 03:48:53.989678 DeviceVref_Margin_A0==40
676 03:48:53.994662 VrefDac_Margin_A1==25
677 03:48:53.994989 DeviceVref_Margin_A1==40
678 03:48:53.995223
679 03:48:53.995444
680 03:48:54.000266 channel==1
681 03:48:54.000606 RxClkDly_Margin_A0==88 ps 9
682 03:48:54.000854 TxDqDly_Margin_A0==88 ps 9
683 03:48:54.005869 RxClkDly_Margin_A1==88 ps 9
684 03:48:54.006206 TxDqDly_Margin_A1==88 ps 9
685 03:48:54.011476 TrainedVREFDQ_A0==76
686 03:48:54.011808 TrainedVREFDQ_A1==77
687 03:48:54.012079 VrefDac_Margin_A0==23
688 03:48:54.017080 DeviceVref_Margin_A0==38
689 03:48:54.017410 VrefDac_Margin_A1==24
690 03:48:54.022659 DeviceVref_Margin_A1==37
691 03:48:54.022984
692 03:48:54.023221 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 03:48:54.023440
694 03:48:54.056305 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
695 03:48:54.056705 2D training succeed
696 03:48:54.061849 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 03:48:54.067526 auto size-- 65535DDR cs0 size: 2048MB
698 03:48:54.067876 DDR cs1 size: 2048MB
699 03:48:54.073142 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 03:48:54.073499 cs0 DataBus test pass
701 03:48:54.078666 cs1 DataBus test pass
702 03:48:54.079006 cs0 AddrBus test pass
703 03:48:54.079241 cs1 AddrBus test pass
704 03:48:54.079460
705 03:48:54.084280 100bdlr_step_size ps== 420
706 03:48:54.084608 result report
707 03:48:54.089836 boot times 0Enable ddr reg access
708 03:48:54.094107 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 03:48:54.107492 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 03:48:54.680508 0.0;M3 CHK:0;cm4_sp_mode 0
711 03:48:54.680890 MVN_1=0x00000000
712 03:48:54.686003 MVN_2=0x00000000
713 03:48:54.691877 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 03:48:54.692521 OPS=0x10
715 03:48:54.692997 ring efuse init
716 03:48:54.693451 chipver efuse init
717 03:48:54.697349 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 03:48:54.703004 [0.018961 Inits done]
719 03:48:54.703549 secure task start!
720 03:48:54.704047 high task start!
721 03:48:54.706576 low task start!
722 03:48:54.707103 run into bl31
723 03:48:54.714261 NOTICE: BL31: v1.3(release):4fc40b1
724 03:48:54.721189 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 03:48:54.721721 NOTICE: BL31: G12A normal boot!
726 03:48:54.747273 NOTICE: BL31: BL33 decompress pass
727 03:48:54.752599 ERROR: Error initializing runtime service opteed_fast
728 03:48:55.986538
729 03:48:55.987214
730 03:48:55.993927 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 03:48:55.994498
732 03:48:55.994998 Model: Libre Computer AML-A311D-CC Alta
733 03:48:56.202105 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 03:48:56.225273 DRAM: 2 GiB (effective 3.8 GiB)
735 03:48:56.369020 Core: 408 devices, 31 uclasses, devicetree: separate
736 03:48:56.374251 WDT: Not starting watchdog@f0d0
737 03:48:56.407193 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 03:48:56.419632 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 03:48:56.423742 ** Bad device specification mmc 0 **
740 03:48:56.435050 Card did not respond to voltage select! : -110
741 03:48:56.441699 ** Bad device specification mmc 0 **
742 03:48:56.442254 Couldn't find partition mmc 0
743 03:48:56.450914 Card did not respond to voltage select! : -110
744 03:48:56.456547 ** Bad device specification mmc 0 **
745 03:48:56.457066 Couldn't find partition mmc 0
746 03:48:56.460825 Error: could not access storage.
747 03:48:56.805013 Net: eth0: ethernet@ff3f0000
748 03:48:56.805648 starting USB...
749 03:48:57.056802 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 03:48:57.057422 Starting the controller
751 03:48:57.063735 USB XHCI 1.10
752 03:48:59.226536 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 03:48:59.227203 bl2_stage_init 0x01
754 03:48:59.227684 bl2_stage_init 0x81
755 03:48:59.232220 hw id: 0x0000 - pwm id 0x01
756 03:48:59.232744 bl2_stage_init 0xc1
757 03:48:59.233207 bl2_stage_init 0x02
758 03:48:59.233658
759 03:48:59.237667 L0:00000000
760 03:48:59.238173 L1:20000703
761 03:48:59.238626 L2:00008067
762 03:48:59.239069 L3:14000000
763 03:48:59.243206 B2:00402000
764 03:48:59.243701 B1:e0f83180
765 03:48:59.244195
766 03:48:59.244649 TE: 58159
767 03:48:59.245099
768 03:48:59.248726 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 03:48:59.249244
770 03:48:59.249705 Board ID = 1
771 03:48:59.254437 Set A53 clk to 24M
772 03:48:59.254948 Set A73 clk to 24M
773 03:48:59.255401 Set clk81 to 24M
774 03:48:59.259968 A53 clk: 1200 MHz
775 03:48:59.260496 A73 clk: 1200 MHz
776 03:48:59.260946 CLK81: 166.6M
777 03:48:59.261389 smccc: 00012ab5
778 03:48:59.265558 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 03:48:59.271252 board id: 1
780 03:48:59.277039 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 03:48:59.288393 fw parse done
782 03:48:59.293332 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 03:48:59.336160 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 03:48:59.347074 PIEI prepare done
785 03:48:59.347593 fastboot data load
786 03:48:59.348101 fastboot data verify
787 03:48:59.352711 verify result: 266
788 03:48:59.358397 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 03:48:59.358922 LPDDR4 probe
790 03:48:59.359379 ddr clk to 1584MHz
791 03:48:59.366270 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 03:48:59.402573
793 03:48:59.403133 dmc_version 0001
794 03:48:59.410305 Check phy result
795 03:48:59.416036 INFO : End of CA training
796 03:48:59.416528 INFO : End of initialization
797 03:48:59.421639 INFO : Training has run successfully!
798 03:48:59.422118 Check phy result
799 03:48:59.427249 INFO : End of initialization
800 03:48:59.427762 INFO : End of read enable training
801 03:48:59.430517 INFO : End of fine write leveling
802 03:48:59.436083 INFO : End of Write leveling coarse delay
803 03:48:59.441652 INFO : Training has run successfully!
804 03:48:59.442136 Check phy result
805 03:48:59.442585 INFO : End of initialization
806 03:48:59.447278 INFO : End of read dq deskew training
807 03:48:59.452980 INFO : End of MPR read delay center optimization
808 03:48:59.453478 INFO : End of write delay center optimization
809 03:48:59.458459 INFO : End of read delay center optimization
810 03:48:59.464080 INFO : End of max read latency training
811 03:48:59.464566 INFO : Training has run successfully!
812 03:48:59.469649 1D training succeed
813 03:48:59.475627 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 03:48:59.523280 Check phy result
815 03:48:59.523803 INFO : End of initialization
816 03:48:59.545806 INFO : End of 2D read delay Voltage center optimization
817 03:48:59.566197 INFO : End of 2D read delay Voltage center optimization
818 03:48:59.618188 INFO : End of 2D write delay Voltage center optimization
819 03:48:59.667391 INFO : End of 2D write delay Voltage center optimization
820 03:48:59.673018 INFO : Training has run successfully!
821 03:48:59.673500
822 03:48:59.673956 channel==0
823 03:48:59.678547 RxClkDly_Margin_A0==88 ps 9
824 03:48:59.679021 TxDqDly_Margin_A0==98 ps 10
825 03:48:59.684201 RxClkDly_Margin_A1==88 ps 9
826 03:48:59.684680 TxDqDly_Margin_A1==98 ps 10
827 03:48:59.685148 TrainedVREFDQ_A0==74
828 03:48:59.689783 TrainedVREFDQ_A1==74
829 03:48:59.690333 VrefDac_Margin_A0==24
830 03:48:59.690791 DeviceVref_Margin_A0==40
831 03:48:59.695362 VrefDac_Margin_A1==24
832 03:48:59.695900 DeviceVref_Margin_A1==40
833 03:48:59.696392
834 03:48:59.696827
835 03:48:59.701054 channel==1
836 03:48:59.701525 RxClkDly_Margin_A0==98 ps 10
837 03:48:59.701957 TxDqDly_Margin_A0==88 ps 9
838 03:48:59.706545 RxClkDly_Margin_A1==88 ps 9
839 03:48:59.707017 TxDqDly_Margin_A1==88 ps 9
840 03:48:59.712190 TrainedVREFDQ_A0==74
841 03:48:59.712690 TrainedVREFDQ_A1==77
842 03:48:59.713128 VrefDac_Margin_A0==23
843 03:48:59.717792 DeviceVref_Margin_A0==40
844 03:48:59.718261 VrefDac_Margin_A1==24
845 03:48:59.723348 DeviceVref_Margin_A1==37
846 03:48:59.723804
847 03:48:59.724286 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 03:48:59.724722
849 03:48:59.757083 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
850 03:48:59.757615 2D training succeed
851 03:48:59.762553 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 03:48:59.768214 auto size-- 65535DDR cs0 size: 2048MB
853 03:48:59.768690 DDR cs1 size: 2048MB
854 03:48:59.773914 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 03:48:59.774385 cs0 DataBus test pass
856 03:48:59.779446 cs1 DataBus test pass
857 03:48:59.779909 cs0 AddrBus test pass
858 03:48:59.780379 cs1 AddrBus test pass
859 03:48:59.780809
860 03:48:59.785008 100bdlr_step_size ps== 420
861 03:48:59.785475 result report
862 03:48:59.790544 boot times 0Enable ddr reg access
863 03:48:59.795793 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 03:48:59.809281 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 03:49:00.383026 0.0;M3 CHK:0;cm4_sp_mode 0
866 03:49:00.383458 MVN_1=0x00000000
867 03:49:00.388457 MVN_2=0x00000000
868 03:49:00.394244 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 03:49:00.394723 OPS=0x10
870 03:49:00.395079 ring efuse init
871 03:49:00.395309 chipver efuse init
872 03:49:00.399805 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 03:49:00.405467 [0.018961 Inits done]
874 03:49:00.406056 secure task start!
875 03:49:00.406530 high task start!
876 03:49:00.410003 low task start!
877 03:49:00.410520 run into bl31
878 03:49:00.416724 NOTICE: BL31: v1.3(release):4fc40b1
879 03:49:00.424481 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 03:49:00.425017 NOTICE: BL31: G12A normal boot!
881 03:49:00.449830 NOTICE: BL31: BL33 decompress pass
882 03:49:00.455509 ERROR: Error initializing runtime service opteed_fast
883 03:49:01.688452
884 03:49:01.689085
885 03:49:01.696777 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 03:49:01.697304
887 03:49:01.697766 Model: Libre Computer AML-A311D-CC Alta
888 03:49:01.905282 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 03:49:01.928713 DRAM: 2 GiB (effective 3.8 GiB)
890 03:49:02.071711 Core: 408 devices, 31 uclasses, devicetree: separate
891 03:49:02.077550 WDT: Not starting watchdog@f0d0
892 03:49:02.109890 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 03:49:02.122248 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 03:49:02.127205 ** Bad device specification mmc 0 **
895 03:49:02.137566 Card did not respond to voltage select! : -110
896 03:49:02.145938 ** Bad device specification mmc 0 **
897 03:49:02.146501 Couldn't find partition mmc 0
898 03:49:02.153620 Card did not respond to voltage select! : -110
899 03:49:02.159042 ** Bad device specification mmc 0 **
900 03:49:02.159664 Couldn't find partition mmc 0
901 03:49:02.164234 Error: could not access storage.
902 03:49:02.506502 Net: eth0: ethernet@ff3f0000
903 03:49:02.507150 starting USB...
904 03:49:02.758373 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 03:49:02.759019 Starting the controller
906 03:49:02.765327 USB XHCI 1.10
907 03:49:04.319345 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 03:49:04.327787 scanning usb for storage devices... 0 Storage Device(s) found
910 03:49:04.378901 Hit any key to stop autoboot: 1
911 03:49:04.379662 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
912 03:49:04.380055 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
913 03:49:04.380353 Setting prompt string to ['=>']
914 03:49:04.380632 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
915 03:49:04.385274 0
916 03:49:04.385895 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 03:49:04.386200 Sending with 10 millisecond of delay
919 03:49:05.520926 => setenv autoload no
920 03:49:05.531761 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
921 03:49:05.537387 setenv autoload no
922 03:49:05.538195 Sending with 10 millisecond of delay
924 03:49:07.336223 => setenv initrd_high 0xffffffff
925 03:49:07.347069 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
926 03:49:07.348051 setenv initrd_high 0xffffffff
927 03:49:07.348942 Sending with 10 millisecond of delay
929 03:49:08.969821 => setenv fdt_high 0xffffffff
930 03:49:08.980495 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
931 03:49:08.981187 setenv fdt_high 0xffffffff
932 03:49:08.981686 Sending with 10 millisecond of delay
934 03:49:09.273318 => dhcp
935 03:49:09.283869 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
936 03:49:09.284424 dhcp
937 03:49:09.284662 Speed: 1000, full duplex
938 03:49:09.284872 BOOTP broadcast 1
939 03:49:09.289762 DHCP client bound to address 192.168.6.27 (5 ms)
940 03:49:09.290242 Sending with 10 millisecond of delay
942 03:49:10.966409 => setenv serverip 192.168.6.2
943 03:49:10.977156 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
944 03:49:10.977957 setenv serverip 192.168.6.2
945 03:49:10.978650 Sending with 10 millisecond of delay
947 03:49:14.702543 => tftpboot 0x01080000 938073/tftp-deploy-410tia7z/kernel/uImage
948 03:49:14.713553 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
949 03:49:14.714450 tftpboot 0x01080000 938073/tftp-deploy-410tia7z/kernel/uImage
950 03:49:14.714907 Speed: 1000, full duplex
951 03:49:14.715322 Using ethernet@ff3f0000 device
952 03:49:14.716978 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
953 03:49:14.722046 Filename '938073/tftp-deploy-410tia7z/kernel/uImage'.
954 03:49:14.726024 Load address: 0x1080000
955 03:49:17.195868 Loading: *################################################## 37.6 MiB
956 03:49:17.196536 15.2 MiB/s
957 03:49:17.196945 done
958 03:49:17.199952 Bytes transferred = 39424576 (2599240 hex)
959 03:49:17.200688 Sending with 10 millisecond of delay
961 03:49:21.888179 => tftpboot 0x08000000 938073/tftp-deploy-410tia7z/ramdisk/ramdisk.cpio.gz.uboot
962 03:49:21.898966 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
963 03:49:21.899747 tftpboot 0x08000000 938073/tftp-deploy-410tia7z/ramdisk/ramdisk.cpio.gz.uboot
964 03:49:21.900256 Speed: 1000, full duplex
965 03:49:21.900675 Using ethernet@ff3f0000 device
966 03:49:21.902886 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
967 03:49:21.912295 Filename '938073/tftp-deploy-410tia7z/ramdisk/ramdisk.cpio.gz.uboot'.
968 03:49:21.912745 Load address: 0x8000000
969 03:49:29.599918 Loading: *#T ################################################ UDP wrong checksum 00000005 00009dc3
970 03:49:34.600450 T UDP wrong checksum 00000005 00009dc3
971 03:49:44.603493 T T UDP wrong checksum 00000005 00009dc3
972 03:50:02.491186 T T T UDP wrong checksum 000000ff 00002468
973 03:50:02.505283 UDP wrong checksum 000000ff 0000ad5a
974 03:50:02.672520 UDP wrong checksum 000000ff 0000ba9f
975 03:50:02.712057 UDP wrong checksum 000000ff 00003f92
976 03:50:04.605927 UDP wrong checksum 00000005 00009dc3
977 03:50:07.161913 T UDP wrong checksum 000000ff 0000a765
978 03:50:07.205303 UDP wrong checksum 000000ff 00003358
979 03:50:19.610463 T T
980 03:50:19.610905 Retry count exceeded; starting again
982 03:50:19.612697 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
985 03:50:19.614444 end: 2.4 uboot-commands (duration 00:01:47) [common]
987 03:50:19.615763 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
989 03:50:19.616824 end: 2 uboot-action (duration 00:01:47) [common]
991 03:50:19.618395 Cleaning after the job
992 03:50:19.618948 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/938073/tftp-deploy-410tia7z/ramdisk
993 03:50:19.620285 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/938073/tftp-deploy-410tia7z/kernel
994 03:50:19.661920 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/938073/tftp-deploy-410tia7z/dtb
995 03:50:19.662753 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/938073/tftp-deploy-410tia7z/modules
996 03:50:19.684925 start: 4.1 power-off (timeout 00:00:30) [common]
997 03:50:19.685610 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
998 03:50:19.717622 >> OK - accepted request
999 03:50:19.719681 Returned 0 in 0 seconds
1000 03:50:19.820591 end: 4.1 power-off (duration 00:00:00) [common]
1002 03:50:19.822288 start: 4.2 read-feedback (timeout 00:10:00) [common]
1003 03:50:19.823428 Listened to connection for namespace 'common' for up to 1s
1004 03:50:20.823560 Finalising connection for namespace 'common'
1005 03:50:20.824103 Disconnecting from shell: Finalise
1006 03:50:20.824422 =>
1007 03:50:20.925068 end: 4.2 read-feedback (duration 00:00:01) [common]
1008 03:50:20.925513 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/938073
1009 03:50:21.198932 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/938073
1010 03:50:21.199555 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.