Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 03:58:54.754327 lava-dispatcher, installed at version: 2024.01
2 03:58:54.755138 start: 0 validate
3 03:58:54.755603 Start time: 2024-11-05 03:58:54.755572+00:00 (UTC)
4 03:58:54.756171 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 03:58:54.756715 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 03:58:54.794787 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 03:58:54.795350 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-77-g2e1b3cc9d7f7%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fkernel%2FImage exists
8 03:58:54.826609 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 03:58:54.827231 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-77-g2e1b3cc9d7f7%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 03:58:55.888371 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 03:58:55.888879 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-77-g2e1b3cc9d7f7%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fmodules.tar.xz exists
12 03:58:55.926124 validate duration: 1.17
14 03:58:55.926977 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 03:58:55.927303 start: 1.1 download-retry (timeout 00:10:00) [common]
16 03:58:55.927606 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 03:58:55.928214 Not decompressing ramdisk as can be used compressed.
18 03:58:55.928644 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 03:58:55.928914 saving as /var/lib/lava/dispatcher/tmp/938074/tftp-deploy-tydysjib/ramdisk/rootfs.cpio.gz
20 03:58:55.929190 total size: 8181887 (7 MB)
21 03:58:55.964882 progress 0 % (0 MB)
22 03:58:55.975032 progress 5 % (0 MB)
23 03:58:55.985074 progress 10 % (0 MB)
24 03:58:55.995791 progress 15 % (1 MB)
25 03:58:56.001134 progress 20 % (1 MB)
26 03:58:56.006734 progress 25 % (1 MB)
27 03:58:56.012073 progress 30 % (2 MB)
28 03:58:56.017594 progress 35 % (2 MB)
29 03:58:56.022768 progress 40 % (3 MB)
30 03:58:56.028294 progress 45 % (3 MB)
31 03:58:56.033438 progress 50 % (3 MB)
32 03:58:56.039016 progress 55 % (4 MB)
33 03:58:56.044173 progress 60 % (4 MB)
34 03:58:56.049665 progress 65 % (5 MB)
35 03:58:56.054845 progress 70 % (5 MB)
36 03:58:56.060401 progress 75 % (5 MB)
37 03:58:56.065597 progress 80 % (6 MB)
38 03:58:56.071066 progress 85 % (6 MB)
39 03:58:56.076205 progress 90 % (7 MB)
40 03:58:56.081721 progress 95 % (7 MB)
41 03:58:56.086493 progress 100 % (7 MB)
42 03:58:56.087146 7 MB downloaded in 0.16 s (49.41 MB/s)
43 03:58:56.087880 end: 1.1.1 http-download (duration 00:00:00) [common]
45 03:58:56.088879 end: 1.1 download-retry (duration 00:00:00) [common]
46 03:58:56.089192 start: 1.2 download-retry (timeout 00:10:00) [common]
47 03:58:56.089479 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 03:58:56.089999 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-77-g2e1b3cc9d7f7/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/kernel/Image
49 03:58:56.090276 saving as /var/lib/lava/dispatcher/tmp/938074/tftp-deploy-tydysjib/kernel/Image
50 03:58:56.090495 total size: 39424512 (37 MB)
51 03:58:56.090712 No compression specified
52 03:58:56.126666 progress 0 % (0 MB)
53 03:58:56.151160 progress 5 % (1 MB)
54 03:58:56.175600 progress 10 % (3 MB)
55 03:58:56.199941 progress 15 % (5 MB)
56 03:58:56.224098 progress 20 % (7 MB)
57 03:58:56.248100 progress 25 % (9 MB)
58 03:58:56.272390 progress 30 % (11 MB)
59 03:58:56.297138 progress 35 % (13 MB)
60 03:58:56.321122 progress 40 % (15 MB)
61 03:58:56.345388 progress 45 % (16 MB)
62 03:58:56.369395 progress 50 % (18 MB)
63 03:58:56.393329 progress 55 % (20 MB)
64 03:58:56.417490 progress 60 % (22 MB)
65 03:58:56.441935 progress 65 % (24 MB)
66 03:58:56.466131 progress 70 % (26 MB)
67 03:58:56.490260 progress 75 % (28 MB)
68 03:58:56.514292 progress 80 % (30 MB)
69 03:58:56.538244 progress 85 % (31 MB)
70 03:58:56.562699 progress 90 % (33 MB)
71 03:58:56.586794 progress 95 % (35 MB)
72 03:58:56.610834 progress 100 % (37 MB)
73 03:58:56.611367 37 MB downloaded in 0.52 s (72.18 MB/s)
74 03:58:56.611862 end: 1.2.1 http-download (duration 00:00:01) [common]
76 03:58:56.612740 end: 1.2 download-retry (duration 00:00:01) [common]
77 03:58:56.613037 start: 1.3 download-retry (timeout 00:09:59) [common]
78 03:58:56.613317 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 03:58:56.613814 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-77-g2e1b3cc9d7f7/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 03:58:56.614099 saving as /var/lib/lava/dispatcher/tmp/938074/tftp-deploy-tydysjib/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 03:58:56.614319 total size: 53209 (0 MB)
82 03:58:56.614538 No compression specified
83 03:58:56.655708 progress 61 % (0 MB)
84 03:58:56.656571 progress 100 % (0 MB)
85 03:58:56.657127 0 MB downloaded in 0.04 s (1.19 MB/s)
86 03:58:56.657598 end: 1.3.1 http-download (duration 00:00:00) [common]
88 03:58:56.658430 end: 1.3 download-retry (duration 00:00:00) [common]
89 03:58:56.658752 start: 1.4 download-retry (timeout 00:09:59) [common]
90 03:58:56.659052 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 03:58:56.659553 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-77-g2e1b3cc9d7f7/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/modules.tar.xz
92 03:58:56.659804 saving as /var/lib/lava/dispatcher/tmp/938074/tftp-deploy-tydysjib/modules/modules.tar
93 03:58:56.660035 total size: 11765612 (11 MB)
94 03:58:56.660248 Using unxz to decompress xz
95 03:58:56.696852 progress 0 % (0 MB)
96 03:58:56.763799 progress 5 % (0 MB)
97 03:58:56.842434 progress 10 % (1 MB)
98 03:58:56.940701 progress 15 % (1 MB)
99 03:58:57.037318 progress 20 % (2 MB)
100 03:58:57.118239 progress 25 % (2 MB)
101 03:58:57.196279 progress 30 % (3 MB)
102 03:58:57.277341 progress 35 % (3 MB)
103 03:58:57.358018 progress 40 % (4 MB)
104 03:58:57.435108 progress 45 % (5 MB)
105 03:58:57.520760 progress 50 % (5 MB)
106 03:58:57.603443 progress 55 % (6 MB)
107 03:58:57.689539 progress 60 % (6 MB)
108 03:58:57.771659 progress 65 % (7 MB)
109 03:58:57.854374 progress 70 % (7 MB)
110 03:58:57.938381 progress 75 % (8 MB)
111 03:58:58.023933 progress 80 % (9 MB)
112 03:58:58.105282 progress 85 % (9 MB)
113 03:58:58.192975 progress 90 % (10 MB)
114 03:58:58.275956 progress 95 % (10 MB)
115 03:58:58.355446 progress 100 % (11 MB)
116 03:58:58.366494 11 MB downloaded in 1.71 s (6.58 MB/s)
117 03:58:58.367068 end: 1.4.1 http-download (duration 00:00:02) [common]
119 03:58:58.367892 end: 1.4 download-retry (duration 00:00:02) [common]
120 03:58:58.368407 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 03:58:58.368984 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 03:58:58.369521 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 03:58:58.370073 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 03:58:58.372379 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq
125 03:58:58.373797 makedir: /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin
126 03:58:58.374795 makedir: /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/tests
127 03:58:58.375557 makedir: /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/results
128 03:58:58.376321 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-add-keys
129 03:58:58.377416 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-add-sources
130 03:58:58.378465 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-background-process-start
131 03:58:58.379498 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-background-process-stop
132 03:58:58.380606 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-common-functions
133 03:58:58.381610 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-echo-ipv4
134 03:58:58.382587 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-install-packages
135 03:58:58.383549 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-installed-packages
136 03:58:58.384552 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-os-build
137 03:58:58.385518 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-probe-channel
138 03:58:58.386476 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-probe-ip
139 03:58:58.387430 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-target-ip
140 03:58:58.388466 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-target-mac
141 03:58:58.389446 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-target-storage
142 03:58:58.390430 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-test-case
143 03:58:58.391395 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-test-event
144 03:58:58.392424 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-test-feedback
145 03:58:58.393396 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-test-raise
146 03:58:58.394352 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-test-reference
147 03:58:58.395313 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-test-runner
148 03:58:58.396315 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-test-set
149 03:58:58.397285 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-test-shell
150 03:58:58.398258 Updating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-install-packages (oe)
151 03:58:58.399294 Updating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/bin/lava-installed-packages (oe)
152 03:58:58.400217 Creating /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/environment
153 03:58:58.401001 LAVA metadata
154 03:58:58.401532 - LAVA_JOB_ID=938074
155 03:58:58.402006 - LAVA_DISPATCHER_IP=192.168.6.2
156 03:58:58.402727 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 03:58:58.404660 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 03:58:58.405253 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 03:58:58.405664 skipped lava-vland-overlay
160 03:58:58.406149 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 03:58:58.406651 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 03:58:58.407075 skipped lava-multinode-overlay
163 03:58:58.407551 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 03:58:58.408078 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 03:58:58.408557 Loading test definitions
166 03:58:58.409096 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 03:58:58.409533 Using /lava-938074 at stage 0
168 03:58:58.411684 uuid=938074_1.5.2.4.1 testdef=None
169 03:58:58.412196 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 03:58:58.412476 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 03:58:58.414302 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 03:58:58.415114 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 03:58:58.417431 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 03:58:58.418270 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:58) [common]
177 03:58:58.420453 runner path: /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/0/tests/0_dmesg test_uuid 938074_1.5.2.4.1
178 03:58:58.421018 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 03:58:58.421789 Creating lava-test-runner.conf files
181 03:58:58.421997 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/938074/lava-overlay-k9oo84tq/lava-938074/0 for stage 0
182 03:58:58.422329 - 0_dmesg
183 03:58:58.422676 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 03:58:58.422971 start: 1.5.2.5 compress-overlay (timeout 00:09:58) [common]
185 03:58:58.446635 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 03:58:58.447031 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 03:58:58.447295 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 03:58:58.447563 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 03:58:58.447826 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 03:58:59.369172 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 03:58:59.369689 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 03:58:59.370217 extracting modules file /var/lib/lava/dispatcher/tmp/938074/tftp-deploy-tydysjib/modules/modules.tar to /var/lib/lava/dispatcher/tmp/938074/extract-overlay-ramdisk-bgen8h5v/ramdisk
193 03:59:00.720988 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 03:59:00.721478 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 03:59:00.721758 [common] Applying overlay /var/lib/lava/dispatcher/tmp/938074/compress-overlay-k1pq9_dn/overlay-1.5.2.5.tar.gz to ramdisk
196 03:59:00.721970 [common] Applying overlay /var/lib/lava/dispatcher/tmp/938074/compress-overlay-k1pq9_dn/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/938074/extract-overlay-ramdisk-bgen8h5v/ramdisk
197 03:59:00.751790 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 03:59:00.752234 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 03:59:00.752508 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 03:59:00.752735 Converting downloaded kernel to a uImage
201 03:59:00.753037 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/938074/tftp-deploy-tydysjib/kernel/Image /var/lib/lava/dispatcher/tmp/938074/tftp-deploy-tydysjib/kernel/uImage
202 03:59:01.146930 output: Image Name:
203 03:59:01.147346 output: Created: Tue Nov 5 03:59:00 2024
204 03:59:01.147554 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 03:59:01.147760 output: Data Size: 39424512 Bytes = 38500.50 KiB = 37.60 MiB
206 03:59:01.147961 output: Load Address: 01080000
207 03:59:01.148196 output: Entry Point: 01080000
208 03:59:01.148395 output:
209 03:59:01.148727 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 03:59:01.148996 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 03:59:01.149265 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 03:59:01.149520 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 03:59:01.149775 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 03:59:01.150031 Building ramdisk /var/lib/lava/dispatcher/tmp/938074/extract-overlay-ramdisk-bgen8h5v/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/938074/extract-overlay-ramdisk-bgen8h5v/ramdisk
215 03:59:03.598268 >> 188260 blocks
216 03:59:11.985622 Adding RAMdisk u-boot header.
217 03:59:11.986352 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/938074/extract-overlay-ramdisk-bgen8h5v/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/938074/extract-overlay-ramdisk-bgen8h5v/ramdisk.cpio.gz.uboot
218 03:59:12.252105 output: Image Name:
219 03:59:12.252933 output: Created: Tue Nov 5 03:59:11 2024
220 03:59:12.253371 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 03:59:12.253778 output: Data Size: 26755761 Bytes = 26128.67 KiB = 25.52 MiB
222 03:59:12.254176 output: Load Address: 00000000
223 03:59:12.254570 output: Entry Point: 00000000
224 03:59:12.254958 output:
225 03:59:12.255975 rename /var/lib/lava/dispatcher/tmp/938074/extract-overlay-ramdisk-bgen8h5v/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/938074/tftp-deploy-tydysjib/ramdisk/ramdisk.cpio.gz.uboot
226 03:59:12.256704 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 03:59:12.257240 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 03:59:12.257798 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 03:59:12.258243 No LXC device requested
230 03:59:12.258733 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 03:59:12.259233 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 03:59:12.259714 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 03:59:12.260154 Checking files for TFTP limit of 4294967296 bytes.
234 03:59:12.263015 end: 1 tftp-deploy (duration 00:00:16) [common]
235 03:59:12.263595 start: 2 uboot-action (timeout 00:05:00) [common]
236 03:59:12.264146 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 03:59:12.264648 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 03:59:12.265148 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 03:59:12.265670 Using kernel file from prepare-kernel: 938074/tftp-deploy-tydysjib/kernel/uImage
240 03:59:12.266266 substitutions:
241 03:59:12.266668 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 03:59:12.267067 - {DTB_ADDR}: 0x01070000
243 03:59:12.267461 - {DTB}: 938074/tftp-deploy-tydysjib/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 03:59:12.267854 - {INITRD}: 938074/tftp-deploy-tydysjib/ramdisk/ramdisk.cpio.gz.uboot
245 03:59:12.268277 - {KERNEL_ADDR}: 0x01080000
246 03:59:12.268668 - {KERNEL}: 938074/tftp-deploy-tydysjib/kernel/uImage
247 03:59:12.269060 - {LAVA_MAC}: None
248 03:59:12.269489 - {PRESEED_CONFIG}: None
249 03:59:12.269885 - {PRESEED_LOCAL}: None
250 03:59:12.270273 - {RAMDISK_ADDR}: 0x08000000
251 03:59:12.270654 - {RAMDISK}: 938074/tftp-deploy-tydysjib/ramdisk/ramdisk.cpio.gz.uboot
252 03:59:12.271045 - {ROOT_PART}: None
253 03:59:12.271626 - {ROOT}: None
254 03:59:12.272075 - {SERVER_IP}: 192.168.6.2
255 03:59:12.272477 - {TEE_ADDR}: 0x83000000
256 03:59:12.272868 - {TEE}: None
257 03:59:12.273255 Parsed boot commands:
258 03:59:12.273633 - setenv autoload no
259 03:59:12.274022 - setenv initrd_high 0xffffffff
260 03:59:12.274408 - setenv fdt_high 0xffffffff
261 03:59:12.274791 - dhcp
262 03:59:12.275176 - setenv serverip 192.168.6.2
263 03:59:12.275562 - tftpboot 0x01080000 938074/tftp-deploy-tydysjib/kernel/uImage
264 03:59:12.275949 - tftpboot 0x08000000 938074/tftp-deploy-tydysjib/ramdisk/ramdisk.cpio.gz.uboot
265 03:59:12.276360 - tftpboot 0x01070000 938074/tftp-deploy-tydysjib/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 03:59:12.276746 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 03:59:12.277140 - bootm 0x01080000 0x08000000 0x01070000
268 03:59:12.277635 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 03:59:12.279105 start: 2.3 connect-device (timeout 00:05:00) [common]
271 03:59:12.279549 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 03:59:12.294876 Setting prompt string to ['lava-test: # ']
273 03:59:12.296410 end: 2.3 connect-device (duration 00:00:00) [common]
274 03:59:12.296996 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 03:59:12.297544 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 03:59:12.298077 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 03:59:12.299204 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 03:59:12.336952 >> OK - accepted request
279 03:59:12.339593 Returned 0 in 0 seconds
280 03:59:12.440712 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 03:59:12.442282 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 03:59:12.442938 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 03:59:12.443463 Setting prompt string to ['Hit any key to stop autoboot']
285 03:59:12.443910 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 03:59:12.445514 Trying 192.168.56.21...
287 03:59:12.445992 Connected to conserv1.
288 03:59:12.446415 Escape character is '^]'.
289 03:59:12.446843
290 03:59:12.447260 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 03:59:12.447691
292 03:59:19.617037 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 03:59:19.617642 bl2_stage_init 0x01
294 03:59:19.618068 bl2_stage_init 0x81
295 03:59:19.622554 hw id: 0x0000 - pwm id 0x01
296 03:59:19.623013 bl2_stage_init 0xc1
297 03:59:19.628139 bl2_stage_init 0x02
298 03:59:19.628586
299 03:59:19.629001 L0:00000000
300 03:59:19.629400 L1:00000703
301 03:59:19.629789 L2:00008067
302 03:59:19.630177 L3:15000000
303 03:59:19.633643 S1:00000000
304 03:59:19.634069 B2:20282000
305 03:59:19.634463 B1:a0f83180
306 03:59:19.634851
307 03:59:19.635238 TE: 71222
308 03:59:19.635626
309 03:59:19.639237 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 03:59:19.639671
311 03:59:19.644863 Board ID = 1
312 03:59:19.645288 Set cpu clk to 24M
313 03:59:19.645678 Set clk81 to 24M
314 03:59:19.650455 Use GP1_pll as DSU clk.
315 03:59:19.650872 DSU clk: 1200 Mhz
316 03:59:19.651262 CPU clk: 1200 MHz
317 03:59:19.656042 Set clk81 to 166.6M
318 03:59:19.661613 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 03:59:19.662041 board id: 1
320 03:59:19.668844 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 03:59:19.679595 fw parse done
322 03:59:19.685473 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 03:59:19.728137 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 03:59:19.738994 PIEI prepare done
325 03:59:19.739419 fastboot data load
326 03:59:19.739812 fastboot data verify
327 03:59:19.744643 verify result: 266
328 03:59:19.750241 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 03:59:19.750661 LPDDR4 probe
330 03:59:19.751071 ddr clk to 1584MHz
331 03:59:19.758236 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 03:59:19.795588
333 03:59:19.796205 dmc_version 0001
334 03:59:19.801284 Check phy result
335 03:59:19.808140 INFO : End of CA training
336 03:59:19.808689 INFO : End of initialization
337 03:59:19.813761 INFO : Training has run successfully!
338 03:59:19.814287 Check phy result
339 03:59:19.819361 INFO : End of initialization
340 03:59:19.819869 INFO : End of read enable training
341 03:59:19.824997 INFO : End of fine write leveling
342 03:59:19.830532 INFO : End of Write leveling coarse delay
343 03:59:19.831048 INFO : Training has run successfully!
344 03:59:19.831492 Check phy result
345 03:59:19.836240 INFO : End of initialization
346 03:59:19.836770 INFO : End of read dq deskew training
347 03:59:19.841771 INFO : End of MPR read delay center optimization
348 03:59:19.847358 INFO : End of write delay center optimization
349 03:59:19.852997 INFO : End of read delay center optimization
350 03:59:19.853516 INFO : End of max read latency training
351 03:59:19.858502 INFO : Training has run successfully!
352 03:59:19.859048 1D training succeed
353 03:59:19.867778 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 03:59:19.915468 Check phy result
355 03:59:19.916185 INFO : End of initialization
356 03:59:19.937736 INFO : End of 2D read delay Voltage center optimization
357 03:59:19.956962 INFO : End of 2D read delay Voltage center optimization
358 03:59:20.008906 INFO : End of 2D write delay Voltage center optimization
359 03:59:20.058018 INFO : End of 2D write delay Voltage center optimization
360 03:59:20.063629 INFO : Training has run successfully!
361 03:59:20.064235
362 03:59:20.064702 channel==0
363 03:59:20.069122 RxClkDly_Margin_A0==78 ps 8
364 03:59:20.069668 TxDqDly_Margin_A0==98 ps 10
365 03:59:20.074870 RxClkDly_Margin_A1==69 ps 7
366 03:59:20.075473 TxDqDly_Margin_A1==98 ps 10
367 03:59:20.075943 TrainedVREFDQ_A0==74
368 03:59:20.080382 TrainedVREFDQ_A1==74
369 03:59:20.080963 VrefDac_Margin_A0==22
370 03:59:20.081438 DeviceVref_Margin_A0==40
371 03:59:20.085959 VrefDac_Margin_A1==22
372 03:59:20.086524 DeviceVref_Margin_A1==40
373 03:59:20.086975
374 03:59:20.087433
375 03:59:20.091461 channel==1
376 03:59:20.092030 RxClkDly_Margin_A0==88 ps 9
377 03:59:20.092489 TxDqDly_Margin_A0==98 ps 10
378 03:59:20.097233 RxClkDly_Margin_A1==78 ps 8
379 03:59:20.097567 TxDqDly_Margin_A1==88 ps 9
380 03:59:20.102758 TrainedVREFDQ_A0==78
381 03:59:20.103070 TrainedVREFDQ_A1==75
382 03:59:20.103301 VrefDac_Margin_A0==22
383 03:59:20.108226 DeviceVref_Margin_A0==36
384 03:59:20.108543 VrefDac_Margin_A1==22
385 03:59:20.113820 DeviceVref_Margin_A1==39
386 03:59:20.114107
387 03:59:20.114340 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 03:59:20.114561
389 03:59:20.147505 soc_vref_reg_value 0x 00000019 00000018 00000017 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
390 03:59:20.147872 2D training succeed
391 03:59:20.152925 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 03:59:20.158590 auto size-- 65535DDR cs0 size: 2048MB
393 03:59:20.158896 DDR cs1 size: 2048MB
394 03:59:20.164084 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 03:59:20.164397 cs0 DataBus test pass
396 03:59:20.169671 cs1 DataBus test pass
397 03:59:20.169955 cs0 AddrBus test pass
398 03:59:20.170178 cs1 AddrBus test pass
399 03:59:20.170393
400 03:59:20.175273 100bdlr_step_size ps== 464
401 03:59:20.175559 result report
402 03:59:20.180852 boot times 0Enable ddr reg access
403 03:59:20.186135 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 03:59:20.200002 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 03:59:20.855791 bl2z: ptr: 05129330, size: 00001e40
406 03:59:20.862031 0.0;M3 CHK:0;cm4_sp_mode 0
407 03:59:20.862381 MVN_1=0x00000000
408 03:59:20.862619 MVN_2=0x00000000
409 03:59:20.866834 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 03:59:20.867239 OPS=0x04
411 03:59:20.872754 ring efuse init
412 03:59:20.878380 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 03:59:20.878780 [0.017319 Inits done]
414 03:59:20.879041 secure task start!
415 03:59:20.885179 high task start!
416 03:59:20.885490 low task start!
417 03:59:20.885713 run into bl31
418 03:59:20.893835 NOTICE: BL31: v1.3(release):4fc40b1
419 03:59:20.901590 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 03:59:20.901933 NOTICE: BL31: G12A normal boot!
421 03:59:20.917105 NOTICE: BL31: BL33 decompress pass
422 03:59:20.922806 ERROR: Error initializing runtime service opteed_fast
423 03:59:23.664598 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 03:59:23.665270 bl2_stage_init 0x01
425 03:59:23.665769 bl2_stage_init 0x81
426 03:59:23.670104 hw id: 0x0000 - pwm id 0x01
427 03:59:23.670619 bl2_stage_init 0xc1
428 03:59:23.675116 bl2_stage_init 0x02
429 03:59:23.675663
430 03:59:23.676156 L0:00000000
431 03:59:23.676592 L1:00000703
432 03:59:23.677020 L2:00008067
433 03:59:23.680562 L3:15000000
434 03:59:23.681028 S1:00000000
435 03:59:23.681460 B2:20282000
436 03:59:23.681884 B1:a0f83180
437 03:59:23.682304
438 03:59:23.682727 TE: 67628
439 03:59:23.683151
440 03:59:23.691787 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 03:59:23.692291
442 03:59:23.692725 Board ID = 1
443 03:59:23.693161 Set cpu clk to 24M
444 03:59:23.693589 Set clk81 to 24M
445 03:59:23.697390 Use GP1_pll as DSU clk.
446 03:59:23.697867 DSU clk: 1200 Mhz
447 03:59:23.698295 CPU clk: 1200 MHz
448 03:59:23.703076 Set clk81 to 166.6M
449 03:59:23.708585 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 03:59:23.709047 board id: 1
451 03:59:23.716478 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 03:59:23.727428 fw parse done
453 03:59:23.733372 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 03:59:23.776495 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 03:59:23.787572 PIEI prepare done
456 03:59:23.788074 fastboot data load
457 03:59:23.788516 fastboot data verify
458 03:59:23.793248 verify result: 266
459 03:59:23.798886 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 03:59:23.799346 LPDDR4 probe
461 03:59:23.799773 ddr clk to 1584MHz
462 03:59:23.806799 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 03:59:23.844595
464 03:59:23.845108 dmc_version 0001
465 03:59:23.851539 Check phy result
466 03:59:23.857593 INFO : End of CA training
467 03:59:23.858114 INFO : End of initialization
468 03:59:23.863221 INFO : Training has run successfully!
469 03:59:23.863721 Check phy result
470 03:59:23.868785 INFO : End of initialization
471 03:59:23.869271 INFO : End of read enable training
472 03:59:23.872182 INFO : End of fine write leveling
473 03:59:23.877671 INFO : End of Write leveling coarse delay
474 03:59:23.883305 INFO : Training has run successfully!
475 03:59:23.883774 Check phy result
476 03:59:23.884257 INFO : End of initialization
477 03:59:23.888891 INFO : End of read dq deskew training
478 03:59:23.894530 INFO : End of MPR read delay center optimization
479 03:59:23.894998 INFO : End of write delay center optimization
480 03:59:23.900187 INFO : End of read delay center optimization
481 03:59:23.905694 INFO : End of max read latency training
482 03:59:23.906164 INFO : Training has run successfully!
483 03:59:23.911331 1D training succeed
484 03:59:23.917277 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 03:59:23.965523 Check phy result
486 03:59:23.966054 INFO : End of initialization
487 03:59:23.992007 INFO : End of 2D read delay Voltage center optimization
488 03:59:24.017075 INFO : End of 2D read delay Voltage center optimization
489 03:59:24.073788 INFO : End of 2D write delay Voltage center optimization
490 03:59:24.127942 INFO : End of 2D write delay Voltage center optimization
491 03:59:24.133443 INFO : Training has run successfully!
492 03:59:24.133942
493 03:59:24.134395 channel==0
494 03:59:24.139062 RxClkDly_Margin_A0==78 ps 8
495 03:59:24.139552 TxDqDly_Margin_A0==98 ps 10
496 03:59:24.142250 RxClkDly_Margin_A1==88 ps 9
497 03:59:24.142755 TxDqDly_Margin_A1==88 ps 9
498 03:59:24.147746 TrainedVREFDQ_A0==75
499 03:59:24.148291 TrainedVREFDQ_A1==74
500 03:59:24.148748 VrefDac_Margin_A0==23
501 03:59:24.153501 DeviceVref_Margin_A0==39
502 03:59:24.154172 VrefDac_Margin_A1==23
503 03:59:24.159235 DeviceVref_Margin_A1==40
504 03:59:24.159771
505 03:59:24.160268
506 03:59:24.160724 channel==1
507 03:59:24.161166 RxClkDly_Margin_A0==78 ps 8
508 03:59:24.164628 TxDqDly_Margin_A0==98 ps 10
509 03:59:24.165157 RxClkDly_Margin_A1==78 ps 8
510 03:59:24.170618 TxDqDly_Margin_A1==88 ps 9
511 03:59:24.171334 TrainedVREFDQ_A0==78
512 03:59:24.171832 TrainedVREFDQ_A1==75
513 03:59:24.175913 VrefDac_Margin_A0==22
514 03:59:24.176594 DeviceVref_Margin_A0==36
515 03:59:24.181821 VrefDac_Margin_A1==20
516 03:59:24.182221 DeviceVref_Margin_A1==39
517 03:59:24.182484
518 03:59:24.187038 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 03:59:24.187497
520 03:59:24.214919 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000019 00000016 00000018 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
521 03:59:24.220512 2D training succeed
522 03:59:24.226955 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 03:59:24.227329 auto size-- 65535DDR cs0 size: 2048MB
524 03:59:24.231875 DDR cs1 size: 2048MB
525 03:59:24.232283 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 03:59:24.237482 cs0 DataBus test pass
527 03:59:24.237852 cs1 DataBus test pass
528 03:59:24.238130 cs0 AddrBus test pass
529 03:59:24.243050 cs1 AddrBus test pass
530 03:59:24.243434
531 03:59:24.243706 100bdlr_step_size ps== 471
532 03:59:24.243961 result report
533 03:59:24.248572 boot times 0Enable ddr reg access
534 03:59:24.256062 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 03:59:24.268903 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 03:59:24.929692 bl2z: ptr: 05129330, size: 00001e40
537 03:59:24.938868 0.0;M3 CHK:0;cm4_sp_mode 0
538 03:59:24.939399 MVN_1=0x00000000
539 03:59:24.939863 MVN_2=0x00000000
540 03:59:24.950371 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 03:59:24.950891 OPS=0x04
542 03:59:24.951352 ring efuse init
543 03:59:24.956056 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 03:59:24.956584 [0.017354 Inits done]
545 03:59:24.957040 secure task start!
546 03:59:24.963533 high task start!
547 03:59:24.964122 low task start!
548 03:59:24.964584 run into bl31
549 03:59:24.972334 NOTICE: BL31: v1.3(release):4fc40b1
550 03:59:24.980162 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 03:59:24.980818 NOTICE: BL31: G12A normal boot!
552 03:59:24.995729 NOTICE: BL31: BL33 decompress pass
553 03:59:25.001370 ERROR: Error initializing runtime service opteed_fast
554 03:59:26.365480 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 03:59:26.366146 bl2_stage_init 0x01
556 03:59:26.366620 bl2_stage_init 0x81
557 03:59:26.371071 hw id: 0x0000 - pwm id 0x01
558 03:59:26.371625 bl2_stage_init 0xc1
559 03:59:26.376706 bl2_stage_init 0x02
560 03:59:26.377217
561 03:59:26.377678 L0:00000000
562 03:59:26.378123 L1:00000703
563 03:59:26.378563 L2:00008067
564 03:59:26.379004 L3:15000000
565 03:59:26.382281 S1:00000000
566 03:59:26.382785 B2:20282000
567 03:59:26.383232 B1:a0f83180
568 03:59:26.383671
569 03:59:26.384148 TE: 69338
570 03:59:26.384590
571 03:59:26.387899 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 03:59:26.388450
573 03:59:26.393536 Board ID = 1
574 03:59:26.394041 Set cpu clk to 24M
575 03:59:26.394488 Set clk81 to 24M
576 03:59:26.399003 Use GP1_pll as DSU clk.
577 03:59:26.399502 DSU clk: 1200 Mhz
578 03:59:26.399946 CPU clk: 1200 MHz
579 03:59:26.404539 Set clk81 to 166.6M
580 03:59:26.410406 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 03:59:26.410910 board id: 1
582 03:59:26.417347 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 03:59:26.428012 fw parse done
584 03:59:26.433964 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 03:59:26.476587 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 03:59:26.487650 PIEI prepare done
587 03:59:26.488240 fastboot data load
588 03:59:26.488709 fastboot data verify
589 03:59:26.493195 verify result: 266
590 03:59:26.498797 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 03:59:26.499329 LPDDR4 probe
592 03:59:26.499781 ddr clk to 1584MHz
593 03:59:26.506748 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 03:59:26.544090
595 03:59:26.544652 dmc_version 0001
596 03:59:26.550797 Check phy result
597 03:59:26.556700 INFO : End of CA training
598 03:59:26.557214 INFO : End of initialization
599 03:59:26.562312 INFO : Training has run successfully!
600 03:59:26.562830 Check phy result
601 03:59:26.567907 INFO : End of initialization
602 03:59:26.568446 INFO : End of read enable training
603 03:59:26.571261 INFO : End of fine write leveling
604 03:59:26.576794 INFO : End of Write leveling coarse delay
605 03:59:26.582436 INFO : Training has run successfully!
606 03:59:26.582960 Check phy result
607 03:59:26.583415 INFO : End of initialization
608 03:59:26.587959 INFO : End of read dq deskew training
609 03:59:26.593544 INFO : End of MPR read delay center optimization
610 03:59:26.594053 INFO : End of write delay center optimization
611 03:59:26.599242 INFO : End of read delay center optimization
612 03:59:26.604852 INFO : End of max read latency training
613 03:59:26.605368 INFO : Training has run successfully!
614 03:59:26.610456 1D training succeed
615 03:59:26.616342 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 03:59:26.663822 Check phy result
617 03:59:26.664416 INFO : End of initialization
618 03:59:26.686160 INFO : End of 2D read delay Voltage center optimization
619 03:59:26.705355 INFO : End of 2D read delay Voltage center optimization
620 03:59:26.757305 INFO : End of 2D write delay Voltage center optimization
621 03:59:26.806529 INFO : End of 2D write delay Voltage center optimization
622 03:59:26.812083 INFO : Training has run successfully!
623 03:59:26.812602
624 03:59:26.813064 channel==0
625 03:59:26.817671 RxClkDly_Margin_A0==88 ps 9
626 03:59:26.818183 TxDqDly_Margin_A0==88 ps 9
627 03:59:26.823247 RxClkDly_Margin_A1==88 ps 9
628 03:59:26.823756 TxDqDly_Margin_A1==88 ps 9
629 03:59:26.824252 TrainedVREFDQ_A0==74
630 03:59:26.828794 TrainedVREFDQ_A1==74
631 03:59:26.829305 VrefDac_Margin_A0==24
632 03:59:26.829751 DeviceVref_Margin_A0==40
633 03:59:26.834471 VrefDac_Margin_A1==23
634 03:59:26.834978 DeviceVref_Margin_A1==40
635 03:59:26.835426
636 03:59:26.835871
637 03:59:26.836357 channel==1
638 03:59:26.840058 RxClkDly_Margin_A0==78 ps 8
639 03:59:26.840571 TxDqDly_Margin_A0==98 ps 10
640 03:59:26.845629 RxClkDly_Margin_A1==88 ps 9
641 03:59:26.846136 TxDqDly_Margin_A1==78 ps 8
642 03:59:26.851271 TrainedVREFDQ_A0==78
643 03:59:26.851783 TrainedVREFDQ_A1==75
644 03:59:26.852277 VrefDac_Margin_A0==22
645 03:59:26.856862 DeviceVref_Margin_A0==36
646 03:59:26.857374 VrefDac_Margin_A1==22
647 03:59:26.857824 DeviceVref_Margin_A1==39
648 03:59:26.862445
649 03:59:26.862952 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 03:59:26.863401
651 03:59:26.895906 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000016 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
652 03:59:26.896541 2D training succeed
653 03:59:26.901587 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 03:59:26.907170 auto size-- 65535DDR cs0 size: 2048MB
655 03:59:26.907687 DDR cs1 size: 2048MB
656 03:59:26.912755 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 03:59:26.913266 cs0 DataBus test pass
658 03:59:26.918457 cs1 DataBus test pass
659 03:59:26.918977 cs0 AddrBus test pass
660 03:59:26.919430 cs1 AddrBus test pass
661 03:59:26.919863
662 03:59:26.923974 100bdlr_step_size ps== 478
663 03:59:26.924532 result report
664 03:59:26.929570 boot times 0Enable ddr reg access
665 03:59:26.934665 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 03:59:26.948487 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 03:59:27.603780 bl2z: ptr: 05129330, size: 00001e40
668 03:59:27.611676 0.0;M3 CHK:0;cm4_sp_mode 0
669 03:59:27.612263 MVN_1=0x00000000
670 03:59:27.612727 MVN_2=0x00000000
671 03:59:27.623036 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 03:59:27.623559 OPS=0x04
673 03:59:27.624043 ring efuse init
674 03:59:27.626119 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 03:59:27.632439 [0.017319 Inits done]
676 03:59:27.632940 secure task start!
677 03:59:27.633393 high task start!
678 03:59:27.633835 low task start!
679 03:59:27.636797 run into bl31
680 03:59:27.645203 NOTICE: BL31: v1.3(release):4fc40b1
681 03:59:27.653180 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 03:59:27.653675 NOTICE: BL31: G12A normal boot!
683 03:59:27.668713 NOTICE: BL31: BL33 decompress pass
684 03:59:27.674317 ERROR: Error initializing runtime service opteed_fast
685 03:59:28.469835
686 03:59:28.470494
687 03:59:28.475129 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 03:59:28.475638
689 03:59:28.478695 Model: Libre Computer AML-S905D3-CC Solitude
690 03:59:28.625720 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 03:59:28.641055 DRAM: 2 GiB (effective 3.8 GiB)
692 03:59:28.742033 Core: 406 devices, 33 uclasses, devicetree: separate
693 03:59:28.747913 WDT: Not starting watchdog@f0d0
694 03:59:28.773002 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 03:59:28.785177 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 03:59:28.790164 ** Bad device specification mmc 0 **
697 03:59:28.800193 Card did not respond to voltage select! : -110
698 03:59:28.807912 ** Bad device specification mmc 0 **
699 03:59:28.808466 Couldn't find partition mmc 0
700 03:59:28.816198 Card did not respond to voltage select! : -110
701 03:59:28.821820 ** Bad device specification mmc 0 **
702 03:59:28.822303 Couldn't find partition mmc 0
703 03:59:28.826757 Error: could not access storage.
704 03:59:29.124235 Net: eth0: ethernet@ff3f0000
705 03:59:29.124880 starting USB...
706 03:59:29.369121 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 03:59:29.369705 Starting the controller
708 03:59:29.375930 USB XHCI 1.10
709 03:59:30.932355 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 03:59:30.940462 scanning usb for storage devices... 0 Storage Device(s) found
712 03:59:30.991718 Hit any key to stop autoboot: 1
713 03:59:30.992612 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 03:59:30.992992 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 03:59:30.993285 Setting prompt string to ['=>']
716 03:59:30.993555 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 03:59:31.006472 0
718 03:59:31.007114 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 03:59:31.108063 => setenv autoload no
721 03:59:31.109113 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 03:59:31.114524 setenv autoload no
724 03:59:31.216102 => setenv initrd_high 0xffffffff
725 03:59:31.217101 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 03:59:31.221541 setenv initrd_high 0xffffffff
728 03:59:31.323209 => setenv fdt_high 0xffffffff
729 03:59:31.324104 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 03:59:31.328740 setenv fdt_high 0xffffffff
732 03:59:31.430662 => dhcp
733 03:59:31.431458 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 03:59:31.434714 dhcp
735 03:59:32.040979 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 03:59:32.041482 Speed: 1000, full duplex
737 03:59:32.041772 BOOTP broadcast 1
738 03:59:32.289744 BOOTP broadcast 2
739 03:59:32.300658 DHCP client bound to address 192.168.6.21 (258 ms)
741 03:59:32.402689 => setenv serverip 192.168.6.2
742 03:59:32.403686 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
743 03:59:32.408326 setenv serverip 192.168.6.2
745 03:59:32.510177 => tftpboot 0x01080000 938074/tftp-deploy-tydysjib/kernel/uImage
746 03:59:32.511069 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
747 03:59:32.517854 tftpboot 0x01080000 938074/tftp-deploy-tydysjib/kernel/uImage
748 03:59:32.518466 Speed: 1000, full duplex
749 03:59:32.519009 Using ethernet@ff3f0000 device
750 03:59:32.523404 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
751 03:59:32.529017 Filename '938074/tftp-deploy-tydysjib/kernel/uImage'.
752 03:59:32.532895 Load address: 0x1080000
753 03:59:35.063618 Loading: *################################################## 37.6 MiB
754 03:59:35.064342 14.8 MiB/s
755 03:59:35.064845 done
756 03:59:35.067877 Bytes transferred = 39424576 (2599240 hex)
758 03:59:35.169602 => tftpboot 0x08000000 938074/tftp-deploy-tydysjib/ramdisk/ramdisk.cpio.gz.uboot
759 03:59:35.170397 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
760 03:59:35.177365 tftpboot 0x08000000 938074/tftp-deploy-tydysjib/ramdisk/ramdisk.cpio.gz.uboot
761 03:59:35.177920 Speed: 1000, full duplex
762 03:59:35.178382 Using ethernet@ff3f0000 device
763 03:59:35.182721 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
764 03:59:35.192499 Filename '938074/tftp-deploy-tydysjib/ramdisk/ramdisk.cpio.gz.uboot'.
765 03:59:35.193045 Load address: 0x8000000
766 03:59:36.815044 Loading: *################################################# UDP wrong checksum 00000005 0000f22c
767 03:59:37.465114 UDP wrong checksum 000000ff 00007801
768 03:59:37.478307 UDP wrong checksum 000000ff 00000df4
769 03:59:41.815567 T UDP wrong checksum 00000005 0000f22c
770 03:59:51.817765 T T UDP wrong checksum 00000005 0000f22c
771 04:00:11.821721 T T T T UDP wrong checksum 00000005 0000f22c
772 04:00:31.826465 T T T
773 04:00:31.826897 Retry count exceeded; starting again
775 04:00:31.828612 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
778 04:00:31.829558 end: 2.4 uboot-commands (duration 00:01:20) [common]
780 04:00:31.830279 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
782 04:00:31.830886 end: 2 uboot-action (duration 00:01:20) [common]
784 04:00:31.831713 Cleaning after the job
785 04:00:31.832078 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/938074/tftp-deploy-tydysjib/ramdisk
786 04:00:31.833100 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/938074/tftp-deploy-tydysjib/kernel
787 04:00:31.854495 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/938074/tftp-deploy-tydysjib/dtb
788 04:00:31.855315 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/938074/tftp-deploy-tydysjib/modules
789 04:00:31.878869 start: 4.1 power-off (timeout 00:00:30) [common]
790 04:00:31.879567 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
791 04:00:31.913588 >> OK - accepted request
792 04:00:31.915787 Returned 0 in 0 seconds
793 04:00:32.016643 end: 4.1 power-off (duration 00:00:00) [common]
795 04:00:32.017574 start: 4.2 read-feedback (timeout 00:10:00) [common]
796 04:00:32.018244 Listened to connection for namespace 'common' for up to 1s
797 04:00:33.018422 Finalising connection for namespace 'common'
798 04:00:33.019106 Disconnecting from shell: Finalise
799 04:00:33.019612 =>
800 04:00:33.120630 end: 4.2 read-feedback (duration 00:00:01) [common]
801 04:00:33.121245 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/938074
802 04:00:33.478349 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/938074
803 04:00:33.478982 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.