Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 27
- Errors: 0
- Boot result: PASS
- Kernel Errors: 66
1 19:48:10.384032 lava-dispatcher, installed at version: 2024.01
2 19:48:10.384807 start: 0 validate
3 19:48:10.385285 Start time: 2024-11-06 19:48:10.385254+00:00 (UTC)
4 19:48:10.385821 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 19:48:10.386362 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 19:48:10.428944 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 19:48:10.429481 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fkernel%2FzImage exists
8 19:48:10.457657 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 19:48:10.458279 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 19:48:10.487666 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 19:48:10.488192 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 19:48:10.521060 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 19:48:10.521581 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fmodules.tar.xz exists
14 19:48:10.556103 validate duration: 0.17
16 19:48:10.557034 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:48:10.557404 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:48:10.557728 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:48:10.558367 Not decompressing ramdisk as can be used compressed.
20 19:48:10.558825 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 19:48:10.559100 saving as /var/lib/lava/dispatcher/tmp/948572/tftp-deploy-mc8odb6d/ramdisk/initrd.cpio.gz
22 19:48:10.559373 total size: 4775763 (4 MB)
23 19:48:10.593811 progress 0 % (0 MB)
24 19:48:10.597375 progress 5 % (0 MB)
25 19:48:10.600756 progress 10 % (0 MB)
26 19:48:10.604142 progress 15 % (0 MB)
27 19:48:10.607770 progress 20 % (0 MB)
28 19:48:10.610988 progress 25 % (1 MB)
29 19:48:10.614145 progress 30 % (1 MB)
30 19:48:10.617779 progress 35 % (1 MB)
31 19:48:10.620923 progress 40 % (1 MB)
32 19:48:10.624087 progress 45 % (2 MB)
33 19:48:10.627239 progress 50 % (2 MB)
34 19:48:10.630787 progress 55 % (2 MB)
35 19:48:10.633924 progress 60 % (2 MB)
36 19:48:10.637077 progress 65 % (2 MB)
37 19:48:10.640607 progress 70 % (3 MB)
38 19:48:10.643708 progress 75 % (3 MB)
39 19:48:10.646965 progress 80 % (3 MB)
40 19:48:10.650158 progress 85 % (3 MB)
41 19:48:10.653698 progress 90 % (4 MB)
42 19:48:10.656761 progress 95 % (4 MB)
43 19:48:10.659639 progress 100 % (4 MB)
44 19:48:10.660316 4 MB downloaded in 0.10 s (45.13 MB/s)
45 19:48:10.660857 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:48:10.661771 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:48:10.662084 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:48:10.662372 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:48:10.662852 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm/multi_v7_defconfig/clang-16/kernel/zImage
51 19:48:10.663109 saving as /var/lib/lava/dispatcher/tmp/948572/tftp-deploy-mc8odb6d/kernel/zImage
52 19:48:10.663329 total size: 12042752 (11 MB)
53 19:48:10.663552 No compression specified
54 19:48:10.701452 progress 0 % (0 MB)
55 19:48:10.712071 progress 5 % (0 MB)
56 19:48:10.721533 progress 10 % (1 MB)
57 19:48:10.730025 progress 15 % (1 MB)
58 19:48:10.740456 progress 20 % (2 MB)
59 19:48:10.748936 progress 25 % (2 MB)
60 19:48:10.758808 progress 30 % (3 MB)
61 19:48:10.767406 progress 35 % (4 MB)
62 19:48:10.778392 progress 40 % (4 MB)
63 19:48:10.786543 progress 45 % (5 MB)
64 19:48:10.794486 progress 50 % (5 MB)
65 19:48:10.803474 progress 55 % (6 MB)
66 19:48:10.812975 progress 60 % (6 MB)
67 19:48:10.821262 progress 65 % (7 MB)
68 19:48:10.831383 progress 70 % (8 MB)
69 19:48:10.841535 progress 75 % (8 MB)
70 19:48:10.852115 progress 80 % (9 MB)
71 19:48:10.862196 progress 85 % (9 MB)
72 19:48:10.872774 progress 90 % (10 MB)
73 19:48:10.882213 progress 95 % (10 MB)
74 19:48:10.891148 progress 100 % (11 MB)
75 19:48:10.891760 11 MB downloaded in 0.23 s (50.28 MB/s)
76 19:48:10.892263 end: 1.2.1 http-download (duration 00:00:00) [common]
78 19:48:10.893080 end: 1.2 download-retry (duration 00:00:00) [common]
79 19:48:10.893354 start: 1.3 download-retry (timeout 00:10:00) [common]
80 19:48:10.893616 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 19:48:10.894075 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm/multi_v7_defconfig/clang-16/dtbs/ti/omap/am335x-boneblack.dtb
82 19:48:10.894346 saving as /var/lib/lava/dispatcher/tmp/948572/tftp-deploy-mc8odb6d/dtb/am335x-boneblack.dtb
83 19:48:10.894551 total size: 70568 (0 MB)
84 19:48:10.894758 No compression specified
85 19:48:10.935004 progress 46 % (0 MB)
86 19:48:10.935886 progress 92 % (0 MB)
87 19:48:10.936637 progress 100 % (0 MB)
88 19:48:10.937092 0 MB downloaded in 0.04 s (1.58 MB/s)
89 19:48:10.937603 end: 1.3.1 http-download (duration 00:00:00) [common]
91 19:48:10.938528 end: 1.3 download-retry (duration 00:00:00) [common]
92 19:48:10.938845 start: 1.4 download-retry (timeout 00:10:00) [common]
93 19:48:10.939162 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 19:48:10.939661 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 19:48:10.939928 saving as /var/lib/lava/dispatcher/tmp/948572/tftp-deploy-mc8odb6d/nfsrootfs/full.rootfs.tar
96 19:48:10.940174 total size: 117747780 (112 MB)
97 19:48:10.940411 Using unxz to decompress xz
98 19:48:10.990556 progress 0 % (0 MB)
99 19:48:11.721917 progress 5 % (5 MB)
100 19:48:12.470362 progress 10 % (11 MB)
101 19:48:13.239767 progress 15 % (16 MB)
102 19:48:13.968630 progress 20 % (22 MB)
103 19:48:14.545833 progress 25 % (28 MB)
104 19:48:15.346613 progress 30 % (33 MB)
105 19:48:16.152756 progress 35 % (39 MB)
106 19:48:16.484631 progress 40 % (44 MB)
107 19:48:16.837479 progress 45 % (50 MB)
108 19:48:17.507633 progress 50 % (56 MB)
109 19:48:18.314533 progress 55 % (61 MB)
110 19:48:19.043762 progress 60 % (67 MB)
111 19:48:19.760758 progress 65 % (73 MB)
112 19:48:20.523462 progress 70 % (78 MB)
113 19:48:21.283164 progress 75 % (84 MB)
114 19:48:22.020726 progress 80 % (89 MB)
115 19:48:22.736805 progress 85 % (95 MB)
116 19:48:23.533349 progress 90 % (101 MB)
117 19:48:24.305458 progress 95 % (106 MB)
118 19:48:25.121800 progress 100 % (112 MB)
119 19:48:25.135319 112 MB downloaded in 14.20 s (7.91 MB/s)
120 19:48:25.136221 end: 1.4.1 http-download (duration 00:00:14) [common]
122 19:48:25.137868 end: 1.4 download-retry (duration 00:00:14) [common]
123 19:48:25.138398 start: 1.5 download-retry (timeout 00:09:45) [common]
124 19:48:25.138921 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 19:48:25.139750 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm/multi_v7_defconfig/clang-16/modules.tar.xz
126 19:48:25.140264 saving as /var/lib/lava/dispatcher/tmp/948572/tftp-deploy-mc8odb6d/modules/modules.tar
127 19:48:25.140697 total size: 6912192 (6 MB)
128 19:48:25.141119 Using unxz to decompress xz
129 19:48:25.184291 progress 0 % (0 MB)
130 19:48:25.220277 progress 5 % (0 MB)
131 19:48:25.269549 progress 10 % (0 MB)
132 19:48:25.315101 progress 15 % (1 MB)
133 19:48:25.366565 progress 20 % (1 MB)
134 19:48:25.415678 progress 25 % (1 MB)
135 19:48:25.465908 progress 30 % (2 MB)
136 19:48:25.510820 progress 35 % (2 MB)
137 19:48:25.559736 progress 40 % (2 MB)
138 19:48:25.603582 progress 45 % (2 MB)
139 19:48:25.651809 progress 50 % (3 MB)
140 19:48:25.698318 progress 55 % (3 MB)
141 19:48:25.744162 progress 60 % (3 MB)
142 19:48:25.790023 progress 65 % (4 MB)
143 19:48:25.834532 progress 70 % (4 MB)
144 19:48:25.884447 progress 75 % (4 MB)
145 19:48:25.927709 progress 80 % (5 MB)
146 19:48:25.976215 progress 85 % (5 MB)
147 19:48:26.019949 progress 90 % (5 MB)
148 19:48:26.067614 progress 95 % (6 MB)
149 19:48:26.111454 progress 100 % (6 MB)
150 19:48:26.126794 6 MB downloaded in 0.99 s (6.69 MB/s)
151 19:48:26.127391 end: 1.5.1 http-download (duration 00:00:01) [common]
153 19:48:26.128547 end: 1.5 download-retry (duration 00:00:01) [common]
154 19:48:26.129092 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 19:48:26.129609 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 19:48:43.331269 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/948572/extract-nfsrootfs-56h1q9v0
157 19:48:43.331877 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 19:48:43.332193 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
159 19:48:43.332826 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71
160 19:48:43.333249 makedir: /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin
161 19:48:43.333568 makedir: /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/tests
162 19:48:43.333876 makedir: /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/results
163 19:48:43.334201 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-add-keys
164 19:48:43.334729 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-add-sources
165 19:48:43.335231 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-background-process-start
166 19:48:43.335761 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-background-process-stop
167 19:48:43.336361 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-common-functions
168 19:48:43.336950 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-echo-ipv4
169 19:48:43.337455 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-install-packages
170 19:48:43.337928 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-installed-packages
171 19:48:43.338393 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-os-build
172 19:48:43.338859 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-probe-channel
173 19:48:43.339331 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-probe-ip
174 19:48:43.339834 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-target-ip
175 19:48:43.340369 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-target-mac
176 19:48:43.340849 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-target-storage
177 19:48:43.341329 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-test-case
178 19:48:43.341802 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-test-event
179 19:48:43.342275 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-test-feedback
180 19:48:43.342747 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-test-raise
181 19:48:43.343210 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-test-reference
182 19:48:43.343707 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-test-runner
183 19:48:43.344239 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-test-set
184 19:48:43.344727 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-test-shell
185 19:48:43.345208 Updating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-add-keys (debian)
186 19:48:43.345730 Updating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-add-sources (debian)
187 19:48:43.346230 Updating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-install-packages (debian)
188 19:48:43.346719 Updating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-installed-packages (debian)
189 19:48:43.347203 Updating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/bin/lava-os-build (debian)
190 19:48:43.347624 Creating /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/environment
191 19:48:43.348007 LAVA metadata
192 19:48:43.348270 - LAVA_JOB_ID=948572
193 19:48:43.348485 - LAVA_DISPATCHER_IP=192.168.6.2
194 19:48:43.348843 start: 1.6.2.1 ssh-authorize (timeout 00:09:27) [common]
195 19:48:43.349819 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 19:48:43.350125 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:27) [common]
197 19:48:43.350330 skipped lava-vland-overlay
198 19:48:43.350567 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 19:48:43.350819 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:27) [common]
200 19:48:43.351033 skipped lava-multinode-overlay
201 19:48:43.351270 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 19:48:43.351518 start: 1.6.2.4 test-definition (timeout 00:09:27) [common]
203 19:48:43.351759 Loading test definitions
204 19:48:43.352078 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:27) [common]
205 19:48:43.352304 Using /lava-948572 at stage 0
206 19:48:43.353376 uuid=948572_1.6.2.4.1 testdef=None
207 19:48:43.353674 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 19:48:43.353934 start: 1.6.2.4.2 test-overlay (timeout 00:09:27) [common]
209 19:48:43.355455 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 19:48:43.356268 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:27) [common]
212 19:48:43.358169 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 19:48:43.358999 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:27) [common]
215 19:48:43.360873 runner path: /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/0/tests/0_timesync-off test_uuid 948572_1.6.2.4.1
216 19:48:43.361424 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 19:48:43.362234 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
219 19:48:43.362452 Using /lava-948572 at stage 0
220 19:48:43.362804 Fetching tests from https://github.com/kernelci/test-definitions.git
221 19:48:43.363100 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/0/tests/1_kselftest-dt'
222 19:48:46.653214 Running '/usr/bin/git checkout kernelci.org
223 19:48:47.101847 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 19:48:47.103283 uuid=948572_1.6.2.4.5 testdef=None
225 19:48:47.103621 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 19:48:47.104895 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
228 19:48:47.110876 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 19:48:47.112638 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
231 19:48:47.120440 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 19:48:47.122250 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
234 19:48:47.130150 runner path: /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/0/tests/1_kselftest-dt test_uuid 948572_1.6.2.4.5
235 19:48:47.130731 BOARD='beaglebone-black'
236 19:48:47.131177 BRANCH='mainline'
237 19:48:47.131610 SKIPFILE='/dev/null'
238 19:48:47.132075 SKIP_INSTALL='True'
239 19:48:47.132505 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz'
240 19:48:47.132944 TST_CASENAME=''
241 19:48:47.133487 TST_CMDFILES='dt'
242 19:48:47.134607 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 19:48:47.136314 Creating lava-test-runner.conf files
245 19:48:47.136755 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/948572/lava-overlay-p6ie1f71/lava-948572/0 for stage 0
246 19:48:47.137469 - 0_timesync-off
247 19:48:47.137974 - 1_kselftest-dt
248 19:48:47.138656 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 19:48:47.139236 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
250 19:49:10.431811 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 19:49:10.432281 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 19:49:10.432546 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 19:49:10.432816 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 19:49:10.433078 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 19:49:10.791581 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 19:49:10.792087 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 19:49:10.792344 extracting modules file /var/lib/lava/dispatcher/tmp/948572/tftp-deploy-mc8odb6d/modules/modules.tar to /var/lib/lava/dispatcher/tmp/948572/extract-nfsrootfs-56h1q9v0
258 19:49:11.665011 extracting modules file /var/lib/lava/dispatcher/tmp/948572/tftp-deploy-mc8odb6d/modules/modules.tar to /var/lib/lava/dispatcher/tmp/948572/extract-overlay-ramdisk-0m1gthtr/ramdisk
259 19:49:12.565922 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 19:49:12.566380 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 19:49:12.566655 [common] Applying overlay to NFS
262 19:49:12.566868 [common] Applying overlay /var/lib/lava/dispatcher/tmp/948572/compress-overlay-_ofd0fo_/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/948572/extract-nfsrootfs-56h1q9v0
263 19:49:15.341436 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 19:49:15.341900 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 19:49:15.342173 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 19:49:15.342448 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 19:49:15.342698 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 19:49:15.342955 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 19:49:15.343203 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 19:49:15.343456 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 19:49:15.343707 Building ramdisk /var/lib/lava/dispatcher/tmp/948572/extract-overlay-ramdisk-0m1gthtr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/948572/extract-overlay-ramdisk-0m1gthtr/ramdisk
272 19:49:16.389336 >> 78982 blocks
273 19:49:21.430087 Adding RAMdisk u-boot header.
274 19:49:21.448908 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/948572/extract-overlay-ramdisk-0m1gthtr/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/948572/extract-overlay-ramdisk-0m1gthtr/ramdisk.cpio.gz.uboot
275 19:49:21.614629 output: Image Name:
276 19:49:21.615040 output: Created: Wed Nov 6 19:49:21 2024
277 19:49:21.615253 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 19:49:21.615459 output: Data Size: 15346424 Bytes = 14986.74 KiB = 14.64 MiB
279 19:49:21.615660 output: Load Address: 00000000
280 19:49:21.615860 output: Entry Point: 00000000
281 19:49:21.616243 output:
282 19:49:21.617655 rename /var/lib/lava/dispatcher/tmp/948572/extract-overlay-ramdisk-0m1gthtr/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/948572/tftp-deploy-mc8odb6d/ramdisk/ramdisk.cpio.gz.uboot
283 19:49:21.618459 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 19:49:21.619106 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 19:49:21.619702 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 19:49:21.620231 No LXC device requested
287 19:49:21.620783 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 19:49:21.621339 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 19:49:21.621879 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 19:49:21.622333 Checking files for TFTP limit of 4294967296 bytes.
291 19:49:21.625254 end: 1 tftp-deploy (duration 00:01:11) [common]
292 19:49:21.625878 start: 2 uboot-action (timeout 00:05:00) [common]
293 19:49:21.626455 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 19:49:21.626997 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 19:49:21.627542 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 19:49:21.628382 substitutions:
297 19:49:21.628849 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 19:49:21.629296 - {DTB_ADDR}: 0x88000000
299 19:49:21.629738 - {DTB}: 948572/tftp-deploy-mc8odb6d/dtb/am335x-boneblack.dtb
300 19:49:21.630174 - {INITRD}: 948572/tftp-deploy-mc8odb6d/ramdisk/ramdisk.cpio.gz.uboot
301 19:49:21.630608 - {KERNEL_ADDR}: 0x82000000
302 19:49:21.631038 - {KERNEL}: 948572/tftp-deploy-mc8odb6d/kernel/zImage
303 19:49:21.631469 - {LAVA_MAC}: None
304 19:49:21.631939 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/948572/extract-nfsrootfs-56h1q9v0
305 19:49:21.632411 - {NFS_SERVER_IP}: 192.168.6.2
306 19:49:21.632844 - {PRESEED_CONFIG}: None
307 19:49:21.633273 - {PRESEED_LOCAL}: None
308 19:49:21.633698 - {RAMDISK_ADDR}: 0x83000000
309 19:49:21.634122 - {RAMDISK}: 948572/tftp-deploy-mc8odb6d/ramdisk/ramdisk.cpio.gz.uboot
310 19:49:21.634554 - {ROOT_PART}: None
311 19:49:21.634978 - {ROOT}: None
312 19:49:21.635403 - {SERVER_IP}: 192.168.6.2
313 19:49:21.635827 - {TEE_ADDR}: 0x83000000
314 19:49:21.636279 - {TEE}: None
315 19:49:21.636706 Parsed boot commands:
316 19:49:21.637122 - setenv autoload no
317 19:49:21.637540 - setenv initrd_high 0xffffffff
318 19:49:21.637964 - setenv fdt_high 0xffffffff
319 19:49:21.638386 - dhcp
320 19:49:21.638801 - setenv serverip 192.168.6.2
321 19:49:21.639220 - tftp 0x82000000 948572/tftp-deploy-mc8odb6d/kernel/zImage
322 19:49:21.639643 - tftp 0x83000000 948572/tftp-deploy-mc8odb6d/ramdisk/ramdisk.cpio.gz.uboot
323 19:49:21.640091 - setenv initrd_size ${filesize}
324 19:49:21.640515 - tftp 0x88000000 948572/tftp-deploy-mc8odb6d/dtb/am335x-boneblack.dtb
325 19:49:21.640937 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/948572/extract-nfsrootfs-56h1q9v0,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 19:49:21.641373 - bootz 0x82000000 0x83000000 0x88000000
327 19:49:21.641909 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 19:49:21.643530 start: 2.3 connect-device (timeout 00:05:00) [common]
330 19:49:21.644014 [common] connect-device Connecting to device using 'telnet conserv3 3001'
331 19:49:21.659401 Setting prompt string to ['lava-test: # ']
332 19:49:21.661057 end: 2.3 connect-device (duration 00:00:00) [common]
333 19:49:21.661709 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 19:49:21.662312 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 19:49:21.663055 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 19:49:21.664480 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-04'
337 19:49:21.702609 >> OK - accepted request
338 19:49:21.704800 Returned 0 in 0 seconds
339 19:49:21.806024 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 19:49:21.807885 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 19:49:21.808568 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 19:49:21.809137 Setting prompt string to ['Hit any key to stop autoboot']
344 19:49:21.809640 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 19:49:21.811350 Trying 192.168.56.22...
346 19:49:21.811875 Connected to conserv3.
347 19:49:21.812374 Escape character is '^]'.
348 19:49:21.812824
349 19:49:21.813287 ser2net port telnet,3001 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 19:49:21.813749
351 19:49:59.029573
352 19:49:59.036211 U-Boot SPL 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
353 19:49:59.036790 Trying to boot from MMC1
354 19:49:59.611619
355 19:49:59.612323
356 19:49:59.617185 U-Boot 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
357 19:49:59.617703
358 19:49:59.618194 CPU : AM335X-GP rev 2.0
359 19:49:59.622353 Model: TI AM335x BeagleBone Black
360 19:49:59.622866 DRAM: 512 MiB
361 19:49:59.706877 Core: 160 devices, 18 uclasses, devicetree: separate
362 19:49:59.720641 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
363 19:50:00.121432 NAND: 0 MiB
364 19:50:00.131470 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
365 19:50:00.206180 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
366 19:50:00.227587 <ethaddr> not set. Validating first E-fuse MAC
367 19:50:00.257403 Net: eth2: ethernet@4a100000, eth3: usb_ether
369 19:50:00.315795 Hit any key to stop autoboot: 2
370 19:50:00.316675 end: 2.4.2 bootloader-interrupt (duration 00:00:39) [common]
371 19:50:00.317317 start: 2.4.3 bootloader-commands (timeout 00:04:21) [common]
372 19:50:00.317844 Setting prompt string to ['=>']
373 19:50:00.318381 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:21)
374 19:50:00.325743 0
375 19:50:00.326685 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
376 19:50:00.327251 Sending with 10 millisecond of delay
378 19:50:01.462060 => setenv autoload no
379 19:50:01.472902 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
380 19:50:01.478216 setenv autoload no
381 19:50:01.479010 Sending with 10 millisecond of delay
383 19:50:03.275763 => setenv initrd_high 0xffffffff
384 19:50:03.286585 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
385 19:50:03.287480 setenv initrd_high 0xffffffff
386 19:50:03.288265 Sending with 10 millisecond of delay
388 19:50:04.904396 => setenv fdt_high 0xffffffff
389 19:50:04.915133 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
390 19:50:04.916099 setenv fdt_high 0xffffffff
391 19:50:04.916852 Sending with 10 millisecond of delay
393 19:50:05.208676 => dhcp
394 19:50:05.219371 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
395 19:50:05.220268 dhcp
396 19:50:05.221993 link up on port 0, speed 100, full duplex
397 19:50:05.222498 BOOTP broadcast 1
398 19:50:05.322019 DHCP client bound to address 192.168.6.16 (97 ms)
399 19:50:05.322825 Sending with 10 millisecond of delay
401 19:50:07.000006 => setenv serverip 192.168.6.2
402 19:50:07.010811 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
403 19:50:07.011711 setenv serverip 192.168.6.2
404 19:50:07.012538 Sending with 10 millisecond of delay
406 19:50:10.495008 => tftp 0x82000000 948572/tftp-deploy-mc8odb6d/kernel/zImage
407 19:50:10.505848 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
408 19:50:10.506803 tftp 0x82000000 948572/tftp-deploy-mc8odb6d/kernel/zImage
409 19:50:10.507276 link up on port 0, speed 100, full duplex
410 19:50:10.510452 Using ethernet@4a100000 device
411 19:50:10.516122 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
412 19:50:10.523310 Filename '948572/tftp-deploy-mc8odb6d/kernel/zImage'.
413 19:50:10.523819 Load address: 0x82000000
414 19:50:12.894604 Loading: *################################################## 11.5 MiB
415 19:50:12.895282 4.8 MiB/s
416 19:50:12.895764 done
417 19:50:12.898921 Bytes transferred = 12042752 (b7c200 hex)
418 19:50:12.899736 Sending with 10 millisecond of delay
420 19:50:17.345615 => tftp 0x83000000 948572/tftp-deploy-mc8odb6d/ramdisk/ramdisk.cpio.gz.uboot
421 19:50:17.356430 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
422 19:50:17.357355 tftp 0x83000000 948572/tftp-deploy-mc8odb6d/ramdisk/ramdisk.cpio.gz.uboot
423 19:50:17.357825 link up on port 0, speed 100, full duplex
424 19:50:17.361225 Using ethernet@4a100000 device
425 19:50:17.366831 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
426 19:50:17.375567 Filename '948572/tftp-deploy-mc8odb6d/ramdisk/ramdisk.cpio.gz.uboot'.
427 19:50:17.376132 Load address: 0x83000000
428 19:50:20.392286 Loading: *################################################## 14.6 MiB
429 19:50:20.392947 4.9 MiB/s
430 19:50:20.393428 done
431 19:50:20.396645 Bytes transferred = 15346488 (ea2b38 hex)
432 19:50:20.397470 Sending with 10 millisecond of delay
434 19:50:22.254560 => setenv initrd_size ${filesize}
435 19:50:22.265368 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:59)
436 19:50:22.266248 setenv initrd_size ${filesize}
437 19:50:22.267003 Sending with 10 millisecond of delay
439 19:50:26.411562 => tftp 0x88000000 948572/tftp-deploy-mc8odb6d/dtb/am335x-boneblack.dtb
440 19:50:26.422443 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:55)
441 19:50:26.423382 tftp 0x88000000 948572/tftp-deploy-mc8odb6d/dtb/am335x-boneblack.dtb
442 19:50:26.423853 link up on port 0, speed 100, full duplex
443 19:50:26.427619 Using ethernet@4a100000 device
444 19:50:26.432969 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
445 19:50:26.444818 Filename '948572/tftp-deploy-mc8odb6d/dtb/am335x-boneblack.dtb'.
446 19:50:26.445337 Load address: 0x88000000
447 19:50:26.455645 Loading: *################################################## 68.9 KiB
448 19:50:26.456181 4.2 MiB/s
449 19:50:26.464124 done
450 19:50:26.464621 Bytes transferred = 70568 (113a8 hex)
451 19:50:26.465338 Sending with 10 millisecond of delay
453 19:50:39.644023 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/948572/extract-nfsrootfs-56h1q9v0,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
454 19:50:39.654892 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:42)
455 19:50:39.655826 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/948572/extract-nfsrootfs-56h1q9v0,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
456 19:50:39.656641 Sending with 10 millisecond of delay
458 19:50:41.995734 => bootz 0x82000000 0x83000000 0x88000000
459 19:50:42.006669 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
460 19:50:42.007260 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:40)
461 19:50:42.008401 bootz 0x82000000 0x83000000 0x88000000
462 19:50:42.008902 Kernel image @ 0x82000000 [ 0x000000 - 0xb7c200 ]
463 19:50:42.009369 ## Loading init Ramdisk from Legacy Image at 83000000 ...
464 19:50:42.014034 Image Name:
465 19:50:42.014552 Created: 2024-11-06 19:49:21 UTC
466 19:50:42.019554 Image Type: ARM Linux RAMDisk Image (uncompressed)
467 19:50:42.025124 Data Size: 15346424 Bytes = 14.6 MiB
468 19:50:42.025630 Load Address: 00000000
469 19:50:42.031283 Entry Point: 00000000
470 19:50:42.205918 Verifying Checksum ... OK
471 19:50:42.206517 ## Flattened Device Tree blob at 88000000
472 19:50:42.212334 Booting using the fdt blob at 0x88000000
473 19:50:42.212833 Working FDT set to 88000000
474 19:50:42.217953 Using Device Tree in place at 88000000, end 880143a7
475 19:50:42.222278 Working FDT set to 88000000
476 19:50:42.235516
477 19:50:42.236039 Starting kernel ...
478 19:50:42.236508
479 19:50:42.237453 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
480 19:50:42.238097 start: 2.4.4 auto-login-action (timeout 00:03:39) [common]
481 19:50:42.238619 Setting prompt string to ['Linux version [0-9]']
482 19:50:42.239124 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
483 19:50:42.239642 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
484 19:50:43.131814 [ 0.000000] Booting Linux on physical CPU 0x0
485 19:50:43.137747 start: 2.4.4.1 login-action (timeout 00:03:38) [common]
486 19:50:43.138346 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
487 19:50:43.138867 Setting prompt string to []
488 19:50:43.139413 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
489 19:50:43.139922 Using line separator: #'\n'#
490 19:50:43.140423 No login prompt set.
491 19:50:43.140905 Parsing kernel messages
492 19:50:43.141349 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
493 19:50:43.142232 [login-action] Waiting for messages, (timeout 00:03:38)
494 19:50:43.142732 Waiting using forced prompt support (timeout 00:01:49)
495 19:50:43.148736 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j365246-arm-clang-16-multi-v7-defconfig-jv5r6) (Debian clang version 16.0.6 (15~deb12u1), Debian LLD 16.0.6) #1 SMP Wed Nov 6 18:55:05 UTC 2024
496 19:50:43.160272 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
497 19:50:43.165994 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
498 19:50:43.171711 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
499 19:50:43.177404 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
500 19:50:43.183193 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
501 19:50:43.188935 [ 0.000000] Memory policy: Data cache writeback
502 19:50:43.195672 [ 0.000000] efi: UEFI not found.
503 19:50:43.196201 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
504 19:50:43.204436 [ 0.000000] Zone ranges:
505 19:50:43.210227 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
506 19:50:43.215927 [ 0.000000] Normal empty
507 19:50:43.216440 [ 0.000000] HighMem empty
508 19:50:43.218797 [ 0.000000] Movable zone start for each node
509 19:50:43.224535 [ 0.000000] Early memory node ranges
510 19:50:43.230260 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
511 19:50:43.238439 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
512 19:50:43.256606 [ 0.000000] CPU: All CPU(s) started in SVC mode.
513 19:50:43.262301 [ 0.000000] AM335X ES2.0 (sgx neon)
514 19:50:43.274006 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
515 19:50:43.291881 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/948572/extract-nfsrootfs-56h1q9v0,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
516 19:50:43.303261 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
517 19:50:43.308974 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
518 19:50:43.314732 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
519 19:50:43.324754 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
520 19:50:43.354087 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
521 19:50:43.360105 <6>[ 0.000000] trace event string verifier disabled
522 19:50:43.360594 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
523 19:50:43.365793 <6>[ 0.000000] rcu: RCU event tracing is enabled.
524 19:50:43.377271 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
525 19:50:43.383040 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
526 19:50:43.389371 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
527 19:50:43.405377 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
528 19:50:43.422991 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
529 19:50:43.429730 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
530 19:50:43.529476 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
531 19:50:43.538146 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
532 19:50:43.550556 <6>[ 0.008338] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
533 19:50:43.558743 <6>[ 0.019184] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
534 19:50:43.568304 <6>[ 0.034213] Console: colour dummy device 80x30
535 19:50:43.574457 Matched prompt #6: WARNING:
536 19:50:43.574985 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
537 19:50:43.579835 <3>[ 0.039111] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
538 19:50:43.585587 <3>[ 0.046189] This ensures that you still see kernel messages. Please
539 19:50:43.588844 <3>[ 0.052917] update your kernel commandline.
540 19:50:43.629325 <6>[ 0.057531] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
541 19:50:43.635092 <6>[ 0.096192] CPU: Testing write buffer coherency: ok
542 19:50:43.640978 <6>[ 0.101561] CPU0: Spectre v2: using BPIALL workaround
543 19:50:43.641475 <6>[ 0.107026] pid_max: default: 32768 minimum: 301
544 19:50:43.652463 <6>[ 0.112226] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
545 19:50:43.659429 <6>[ 0.120052] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
546 19:50:43.666622 <6>[ 0.129432] CPU0: thread -1, cpu 0, socket -1, mpidr 0
547 19:50:43.675048 <6>[ 0.136472] Setting up static identity map for 0x80300000 - 0x803000ac
548 19:50:43.680797 <6>[ 0.146172] rcu: Hierarchical SRCU implementation.
549 19:50:43.687562 <6>[ 0.151456] rcu: Max phase no-delay instances is 1000.
550 19:50:43.697333 <6>[ 0.162840] EFI services will not be available.
551 19:50:43.703139 <6>[ 0.168139] smp: Bringing up secondary CPUs ...
552 19:50:43.708839 <6>[ 0.173195] smp: Brought up 1 node, 1 CPU
553 19:50:43.714634 <6>[ 0.177593] SMP: Total of 1 processors activated (996.14 BogoMIPS).
554 19:50:43.720568 <6>[ 0.184368] CPU: All CPU(s) started in SVC mode.
555 19:50:43.740930 <6>[ 0.189577] Memory: 404436K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50612K reserved, 65536K cma-reserved, 0K highmem)
556 19:50:43.741445 <6>[ 0.205876] devtmpfs: initialized
557 19:50:43.764559 <6>[ 0.224340] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
558 19:50:43.776075 <6>[ 0.232958] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
559 19:50:43.782003 <6>[ 0.243420] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
560 19:50:43.792793 <6>[ 0.255705] pinctrl core: initialized pinctrl subsystem
561 19:50:43.802356 <6>[ 0.266571] DMI not present or invalid.
562 19:50:43.810710 <6>[ 0.272481] NET: Registered PF_NETLINK/PF_ROUTE protocol family
563 19:50:43.820241 <6>[ 0.281480] DMA: preallocated 256 KiB pool for atomic coherent allocations
564 19:50:43.835523 <6>[ 0.293121] thermal_sys: Registered thermal governor 'step_wise'
565 19:50:43.836098 <6>[ 0.293298] cpuidle: using governor menu
566 19:50:43.862923 <6>[ 0.328763] No ATAGs?
567 19:50:43.869139 <6>[ 0.331505] hw-breakpoint: debug architecture 0x4 unsupported.
568 19:50:43.879521 <6>[ 0.343637] Serial: AMBA PL011 UART driver
569 19:50:43.909929 <6>[ 0.375712] iommu: Default domain type: Translated
570 19:50:43.919035 <6>[ 0.381067] iommu: DMA domain TLB invalidation policy: strict mode
571 19:50:43.945384 <5>[ 0.410564] SCSI subsystem initialized
572 19:50:43.951341 <6>[ 0.415484] usbcore: registered new interface driver usbfs
573 19:50:43.957030 <6>[ 0.421528] usbcore: registered new interface driver hub
574 19:50:43.963862 <6>[ 0.427312] usbcore: registered new device driver usb
575 19:50:43.969586 <6>[ 0.433879] pps_core: LinuxPPS API ver. 1 registered
576 19:50:43.981221 <6>[ 0.439266] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
577 19:50:43.987413 <6>[ 0.448996] PTP clock support registered
578 19:50:43.987898 <6>[ 0.453464] EDAC MC: Ver: 3.0.0
579 19:50:44.042603 <6>[ 0.505889] scmi_core: SCMI protocol bus registered
580 19:50:44.057350 <6>[ 0.522573] vgaarb: loaded
581 19:50:44.063460 <6>[ 0.526370] clocksource: Switched to clocksource dmtimer
582 19:50:44.098422 <6>[ 0.563929] NET: Registered PF_INET protocol family
583 19:50:44.111203 <6>[ 0.569642] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
584 19:50:44.116962 <6>[ 0.578673] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
585 19:50:44.128413 <6>[ 0.587608] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
586 19:50:44.134178 <6>[ 0.595855] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
587 19:50:44.145769 <6>[ 0.604142] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
588 19:50:44.151615 <6>[ 0.611869] TCP: Hash tables configured (established 4096 bind 4096)
589 19:50:44.157368 <6>[ 0.618789] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
590 19:50:44.163353 <6>[ 0.625805] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
591 19:50:44.170837 <6>[ 0.633411] NET: Registered PF_UNIX/PF_LOCAL protocol family
592 19:50:44.263143 <6>[ 0.723329] RPC: Registered named UNIX socket transport module.
593 19:50:44.263739 <6>[ 0.729778] RPC: Registered udp transport module.
594 19:50:44.268959 <6>[ 0.734885] RPC: Registered tcp transport module.
595 19:50:44.274775 <6>[ 0.740006] RPC: Registered tcp-with-tls transport module.
596 19:50:44.287757 <6>[ 0.745913] RPC: Registered tcp NFSv4.1 backchannel transport module.
597 19:50:44.288346 <6>[ 0.752839] PCI: CLS 0 bytes, default 64
598 19:50:44.295020 <5>[ 0.758698] Initialise system trusted keyrings
599 19:50:44.313280 <6>[ 0.776039] Trying to unpack rootfs image as initramfs...
600 19:50:44.387532 <6>[ 0.847106] workingset: timestamp_bits=30 max_order=17 bucket_order=0
601 19:50:44.392377 <6>[ 0.854636] squashfs: version 4.0 (2009/01/31) Phillip Lougher
602 19:50:44.428509 <5>[ 0.894070] NFS: Registering the id_resolver key type
603 19:50:44.434134 <5>[ 0.899749] Key type id_resolver registered
604 19:50:44.439947 <5>[ 0.904328] Key type id_legacy registered
605 19:50:44.445680 <6>[ 0.908797] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
606 19:50:44.455222 <6>[ 0.915968] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
607 19:50:44.521292 <5>[ 0.987093] Key type asymmetric registered
608 19:50:44.527269 <5>[ 0.991618] Asymmetric key parser 'x509' registered
609 19:50:44.535546 <6>[ 0.997171] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
610 19:50:44.541393 <6>[ 1.005058] io scheduler mq-deadline registered
611 19:50:44.550152 <6>[ 1.010031] io scheduler kyber registered
612 19:50:44.550719 <6>[ 1.014483] io scheduler bfq registered
613 19:50:44.656282 <6>[ 1.118380] ledtrig-cpu: registered to indicate activity on CPUs
614 19:50:44.937476 <6>[ 1.399276] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
615 19:50:44.965741 <6>[ 1.431337] msm_serial: driver initialized
616 19:50:44.971841 <6>[ 1.436126] SuperH (H)SCI(F) driver initialized
617 19:50:44.977802 <6>[ 1.441440] STMicroelectronics ASC driver initialized
618 19:50:44.983013 <6>[ 1.447126] STM32 USART driver initialized
619 19:50:45.104271 <6>[ 1.569388] brd: module loaded
620 19:50:45.134867 <6>[ 1.599922] loop: module loaded
621 19:50:45.169664 <6>[ 1.634480] CAN device driver interface
622 19:50:45.176481 <6>[ 1.639797] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
623 19:50:45.182146 <6>[ 1.646910] e1000e: Intel(R) PRO/1000 Network Driver
624 19:50:45.188028 <6>[ 1.652301] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
625 19:50:45.193724 <6>[ 1.658778] igb: Intel(R) Gigabit Ethernet Network Driver
626 19:50:45.201990 <6>[ 1.664599] igb: Copyright (c) 2007-2014 Intel Corporation.
627 19:50:45.213762 <6>[ 1.673841] pegasus: Pegasus/Pegasus II USB Ethernet driver
628 19:50:45.219617 <6>[ 1.680021] usbcore: registered new interface driver pegasus
629 19:50:45.225388 <6>[ 1.686151] usbcore: registered new interface driver asix
630 19:50:45.231213 <6>[ 1.692041] usbcore: registered new interface driver ax88179_178a
631 19:50:45.236956 <6>[ 1.698639] usbcore: registered new interface driver cdc_ether
632 19:50:45.242757 <6>[ 1.704938] usbcore: registered new interface driver smsc75xx
633 19:50:45.248632 <6>[ 1.711197] usbcore: registered new interface driver smsc95xx
634 19:50:45.254318 <6>[ 1.717440] usbcore: registered new interface driver net1080
635 19:50:45.260187 <6>[ 1.723559] usbcore: registered new interface driver cdc_subset
636 19:50:45.265888 <6>[ 1.729974] usbcore: registered new interface driver zaurus
637 19:50:45.273688 <6>[ 1.736022] usbcore: registered new interface driver cdc_ncm
638 19:50:45.283427 <6>[ 1.745487] usbcore: registered new interface driver usb-storage
639 19:50:45.293110 <6>[ 1.756779] i2c_dev: i2c /dev entries driver
640 19:50:45.317749 <5>[ 1.775422] cpuidle: enable-method property 'ti,am3352' found operations
641 19:50:45.323831 <6>[ 1.784997] sdhci: Secure Digital Host Controller Interface driver
642 19:50:45.331060 <6>[ 1.791782] sdhci: Copyright(c) Pierre Ossman
643 19:50:45.338316 <6>[ 1.798340] Synopsys Designware Multimedia Card Interface Driver
644 19:50:45.343747 <6>[ 1.806214] sdhci-pltfm: SDHCI platform and OF driver helper
645 19:50:45.357957 <6>[ 1.816250] usbcore: registered new interface driver usbhid
646 19:50:45.358302 <6>[ 1.822375] usbhid: USB HID core driver
647 19:50:45.370865 <6>[ 1.834011] NET: Registered PF_INET6 protocol family
648 19:50:45.845606 <6>[ 2.311079] Segment Routing with IPv6
649 19:50:45.851560 <6>[ 2.315227] In-situ OAM (IOAM) with IPv6
650 19:50:45.858171 <6>[ 2.319736] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
651 19:50:45.865304 <6>[ 2.327126] NET: Registered PF_PACKET protocol family
652 19:50:45.871381 <6>[ 2.332615] can: controller area network core
653 19:50:45.871938 <6>[ 2.337521] NET: Registered PF_CAN protocol family
654 19:50:45.877134 <6>[ 2.342725] can: raw protocol
655 19:50:45.882985 <6>[ 2.346047] can: broadcast manager protocol
656 19:50:45.889213 <6>[ 2.350669] can: netlink gateway - max_hops=1
657 19:50:45.889783 <5>[ 2.356173] Key type dns_resolver registered
658 19:50:45.895497 <6>[ 2.361246] ThumbEE CPU extension supported.
659 19:50:45.901711 <5>[ 2.365941] Registering SWP/SWPB emulation handler
660 19:50:45.909840 <3>[ 2.371646] omap_voltage_late_init: Voltage driver support not added
661 19:50:46.094084 <5>[ 2.557378] Loading compiled-in X.509 certificates
662 19:50:46.222829 <6>[ 2.675691] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
663 19:50:46.230096 <6>[ 2.692393] pinctrl-single 44e10800.pinmux: 142 pins, size 568
664 19:50:46.256772 <3>[ 2.716502] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
665 19:50:46.437105 <3>[ 2.896875] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
666 19:50:46.633078 <6>[ 3.097124] OMAP GPIO hardware version 0.1
667 19:50:46.653882 <6>[ 3.115994] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
668 19:50:46.756611 <4>[ 3.218470] at24 2-0054: supply vcc not found, using dummy regulator
669 19:50:46.790506 <4>[ 3.252373] at24 2-0055: supply vcc not found, using dummy regulator
670 19:50:46.829401 <4>[ 3.291260] at24 2-0056: supply vcc not found, using dummy regulator
671 19:50:46.868515 <4>[ 3.330381] at24 2-0057: supply vcc not found, using dummy regulator
672 19:50:46.907850 <6>[ 3.370472] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
673 19:50:46.963200 <3>[ 3.422836] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
674 19:50:46.989110 <6>[ 3.443945] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
675 19:50:47.009989 <4>[ 3.470556] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
676 19:50:47.026401 <4>[ 3.486966] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
677 19:50:47.084920 <6>[ 3.546838] omap_rng 48310000.rng: Random Number Generator ver. 20
678 19:50:47.108780 <5>[ 3.573536] random: crng init done
679 19:50:47.140465 <6>[ 3.604585] Freeing initrd memory: 14988K
680 19:50:47.155936 <6>[ 3.616461] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
681 19:50:47.209192 <6>[ 3.668809] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
682 19:50:47.215076 <6>[ 3.679155] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
683 19:50:47.226827 <6>[ 3.686490] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
684 19:50:47.232745 <6>[ 3.693946] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
685 19:50:47.244183 <6>[ 3.702073] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
686 19:50:47.251655 <6>[ 3.713717] cpsw-switch 4a100000.switch: Detected MACID = c8:a0:30:c2:c5:7d
687 19:50:47.264786 <5>[ 3.722831] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
688 19:50:47.293045 <3>[ 3.753143] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
689 19:50:47.298884 <6>[ 3.761741] edma 49000000.dma: TI EDMA DMA engine driver
690 19:50:47.370979 <3>[ 3.830432] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
691 19:50:47.385804 <6>[ 3.844881] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
692 19:50:47.398788 <3>[ 3.862133] l3-aon-clkctrl:0000:0: failed to disable
693 19:50:47.455149 <6>[ 3.915218] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
694 19:50:47.460917 <6>[ 3.924737] printk: legacy console [ttyS0] enabled
695 19:50:47.466581 <6>[ 3.924737] printk: legacy console [ttyS0] enabled
696 19:50:47.472292 <6>[ 3.935080] printk: legacy bootconsole [omap8250] disabled
697 19:50:47.478104 <6>[ 3.935080] printk: legacy bootconsole [omap8250] disabled
698 19:50:47.508090 <4>[ 3.967193] tps65217-pmic: Failed to locate of_node [id: -1]
699 19:50:47.511719 <4>[ 3.974590] tps65217-bl: Failed to locate of_node [id: -1]
700 19:50:47.528387 <6>[ 3.994498] tps65217 0-0024: TPS65217 ID 0xe version 1.2
701 19:50:47.548860 <6>[ 4.001497] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
702 19:50:47.560463 <6>[ 4.015192] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
703 19:50:47.563245 <6>[ 4.027086] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
704 19:50:47.586486 <6>[ 4.047049] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
705 19:50:47.592464 <6>[ 4.056106] sdhci-omap 48060000.mmc: Got CD GPIO
706 19:50:47.600546 <4>[ 4.061325] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
707 19:50:47.615314 <4>[ 4.075117] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
708 19:50:47.621965 <4>[ 4.083797] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
709 19:50:47.631664 <4>[ 4.092520] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
710 19:50:47.677751 <6>[ 4.137246] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
711 19:50:47.684925 <6>[ 4.145456] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
712 19:50:47.695964 <6>[ 4.156583] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
713 19:50:47.714854 <6>[ 4.176667] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
714 19:50:47.747610 <6>[ 4.204536] mmc0: new high speed SDHC card at address 0001
715 19:50:47.748210 <6>[ 4.211682] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
716 19:50:47.754229 <6>[ 4.220056] mmcblk0: p1
717 19:50:47.788521 <4>[ 4.247335] mmc1: unexpected status 0x2000980 after switch
718 19:50:47.794666 <4>[ 4.254874] mmc1: unexpected status 0x2000900 after switch
719 19:50:47.801092 <4>[ 4.261151] mmc1: unexpected status 0x2000900 after switch
720 19:50:47.806746 <4>[ 4.267746] mmc1: unexpected status 0x2000900 after switch
721 19:50:47.813545 <6>[ 4.273590] mmc1: new high speed MMC card at address 0001
722 19:50:47.828259 <6>[ 4.280447] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
723 19:50:47.828800 <6>[ 4.292248] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
724 19:50:49.531099 <4>[ 5.989547] mmc1: unexpected status 0x2000980 after switch
725 19:50:49.537382 <4>[ 5.997436] mmc1: unexpected status 0x2000900 after switch
726 19:50:49.538951 <4>[ 6.003972] mmc1: unexpected status 0x2000900 after switch
727 19:50:49.547721 <4>[ 6.010802] mmc1: unexpected status 0x2000900 after switch
728 19:50:49.977215 <6>[ 6.437451] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
729 19:50:50.080614 <5>[ 6.466388] Sending DHCP requests ., OK
730 19:50:50.092059 <6>[ 6.550902] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.16
731 19:50:50.092591 <6>[ 6.559101] IP-Config: Complete:
732 19:50:50.105996 <6>[ 6.562639] device=eth0, hwaddr=c8:a0:30:c2:c5:7d, ipaddr=192.168.6.16, mask=255.255.255.0, gw=192.168.6.1
733 19:50:50.111694 <6>[ 6.573175] host=192.168.6.16, domain=, nis-domain=(none)
734 19:50:50.117353 <6>[ 6.579390] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
735 19:50:50.124205 <6>[ 6.579427] nameserver0=10.255.253.1
736 19:50:50.130189 <6>[ 6.592040] clk: Disabling unused clocks
737 19:50:50.130690 <6>[ 6.596785] PM: genpd: Disabling unused power domains
738 19:50:50.151090 <6>[ 6.613677] Freeing unused kernel image (initmem) memory: 2048K
739 19:50:50.158630 <6>[ 6.623544] Run /init as init process
740 19:50:50.182316 Loading, please wait...
741 19:50:50.306214 <3>[ 6.766231] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
742 19:50:50.319493 Starting systemd-udevd version 252.22-1~deb12u1
743 19:50:51.077530 <3>[ 7.537441] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
744 19:50:51.847700 <3>[ 8.308715] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
745 19:50:52.606773 <3>[ 9.066959] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
746 19:50:53.405695 <3>[ 9.865854] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
747 19:50:53.548551 <4>[ 10.008422] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
748 19:50:53.799074 <4>[ 10.257973] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
749 19:50:53.939332 <6>[ 10.405755] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
750 19:50:53.949357 <6>[ 10.411670] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
751 19:50:54.212616 <6>[ 10.677509] hub 1-0:1.0: USB hub found
752 19:50:54.226441 <3>[ 10.686714] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
753 19:50:54.251720 <6>[ 10.716467] hub 1-0:1.0: 1 port detected
754 19:50:54.295617 <6>[ 10.760187] tda998x 0-0070: found TDA19988
755 19:50:55.000240 <3>[ 11.460514] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
756 19:50:55.115043 <6>[ 11.577231] usb 1-1: new low-speed USB device number 2 using musb-hdrc
757 19:50:55.273309 <3>[ 11.736633] usb 1-1: device descriptor read/64, error -71
758 19:50:55.543536 <3>[ 12.006914] usb 1-1: device descriptor read/64, error -71
759 19:50:55.782543 <3>[ 12.243284] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
760 19:50:55.790637 <3>[ 12.252254] Buffer I/O error on dev mmcblk1, logical block 0, async page read
761 19:50:55.855155 <6>[ 12.317400] usb 1-1: new low-speed USB device number 3 using musb-hdrc
762 19:50:56.003292 <3>[ 12.466659] usb 1-1: device descriptor read/64, error -71
763 19:50:56.243325 <3>[ 12.706686] usb 1-1: device descriptor read/64, error -71
764 19:50:56.360226 <6>[ 12.824245] usb usb1-port1: attempt power cycle
765 19:50:56.664457 <6>[ 13.126556] usb 1-1: new low-speed USB device number 4 using musb-hdrc
766 19:50:57.214590 <6>[ 13.676676] usb 1-1: new low-speed USB device number 5 using musb-hdrc
767 19:50:58.988720 <3>[ 15.448771] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
768 19:50:59.757045 <3>[ 16.217185] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
769 19:51:00.525431 <3>[ 16.985603] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
770 19:51:01.293765 <3>[ 17.754033] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
771 19:51:02.062217 <3>[ 18.522470] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
772 19:51:02.830713 <3>[ 19.291012] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
773 19:51:03.599080 <3>[ 20.059433] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
774 19:51:04.366947 <3>[ 20.827804] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
775 19:51:04.372712 <3>[ 20.836746] Buffer I/O error on dev mmcblk1, logical block 0, async page read
776 19:51:04.379881 <6>[ 20.844378] mmcblk1: unable to read partition table
777 19:51:04.387088 <6>[ 20.851103] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
778 19:51:04.405849 <6>[ 20.869744] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
779 19:51:04.428388 <6>[ 20.890973] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
780 19:51:07.665551 <3>[ 24.125050] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
781 19:51:08.434815 <3>[ 24.894353] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
782 19:51:09.204095 <3>[ 25.663606] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
783 19:51:09.973295 <3>[ 26.432828] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
784 19:51:10.742402 <3>[ 27.202044] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
785 19:51:11.510577 <3>[ 27.971245] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
786 19:51:12.280802 <3>[ 28.740451] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
787 19:51:13.049968 <3>[ 29.509715] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
788 19:51:16.277911 <3>[ 32.738052] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
789 19:51:17.046985 <3>[ 33.507166] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
790 19:51:17.815829 <3>[ 34.276085] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
791 19:51:18.584695 <3>[ 35.044938] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
792 19:51:19.353570 <3>[ 35.813828] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
793 19:51:20.122543 <3>[ 36.582706] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
794 19:51:20.891169 <3>[ 37.351545] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
795 19:51:21.658952 <3>[ 38.120425] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
796 19:51:21.668036 <3>[ 38.129859] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
797 19:51:21.732981 Begin: Loading essential drivers ... done.
798 19:51:21.740611 Begin: Running /scripts/init-premount ... done.
799 19:51:21.751791 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
800 19:51:21.756260 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
801 19:51:21.765367 Device /sys/class/net/eth0 found
802 19:51:21.765872 done.
803 19:51:21.825977 Begin: Waiting up to 180 secs for any network device to become available ... done.
804 19:51:21.912677 IP-Config: eth0 hardware address c8:a0:30:c2:c5:7d mtu 1500 DHCP
805 19:51:22.037958 IP-Config: eth0 guessed broadcast address 192.168.6.255
806 19:51:22.043582 IP-Config: eth0 complete (dhcp from 192.168.6.1):
807 19:51:22.048941 address: 192.168.6.16 broadcast: 192.168.6.255 netmask: 255.255.255.0
808 19:51:22.057792 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
809 19:51:22.062751 rootserver: 192.168.6.1 rootpath:
810 19:51:22.063255 filename :
811 19:51:22.192578 done.
812 19:51:22.204086 Begin: Running /scripts/nfs-bottom ... done.
813 19:51:22.281475 Begin: Running /scripts/init-bottom ... done.
814 19:51:24.403140 <30>[ 40.866106] systemd[1]: System time before build time, advancing clock.
815 19:51:24.581102 <30>[ 41.017946] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
816 19:51:24.589790 <30>[ 41.054618] systemd[1]: Detected architecture arm.
817 19:51:24.602355
818 19:51:24.602883 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
819 19:51:24.603352
820 19:51:24.633520 <30>[ 41.097156] systemd[1]: Hostname set to <debian-bookworm-armhf>.
821 19:51:26.839678 <30>[ 43.302196] systemd[1]: Queued start job for default target graphical.target.
822 19:51:26.856827 <30>[ 43.317395] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
823 19:51:26.864503 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
824 19:51:26.889368 <30>[ 43.348826] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
825 19:51:26.896796 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
826 19:51:26.921906 <30>[ 43.382754] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
827 19:51:26.935129 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
828 19:51:26.957429 <30>[ 43.418311] systemd[1]: Created slice user.slice - User and Session Slice.
829 19:51:26.964127 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
830 19:51:26.992671 <30>[ 43.447766] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
831 19:51:26.998718 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
832 19:51:27.016573 <30>[ 43.477537] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
833 19:51:27.027592 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
834 19:51:27.057288 <30>[ 43.507367] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
835 19:51:27.063684 <30>[ 43.527774] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
836 19:51:27.072206 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
837 19:51:27.095709 <30>[ 43.556920] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
838 19:51:27.104090 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
839 19:51:27.127080 <30>[ 43.587235] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
840 19:51:27.135066 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
841 19:51:27.156560 <30>[ 43.617438] systemd[1]: Reached target paths.target - Path Units.
842 19:51:27.161714 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
843 19:51:27.186046 <30>[ 43.647011] systemd[1]: Reached target remote-fs.target - Remote File Systems.
844 19:51:27.193490 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
845 19:51:27.215851 <30>[ 43.676936] systemd[1]: Reached target slices.target - Slice Units.
846 19:51:27.221392 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
847 19:51:27.245975 <30>[ 43.707064] systemd[1]: Reached target swap.target - Swaps.
848 19:51:27.250102 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
849 19:51:27.276367 <30>[ 43.737194] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
850 19:51:27.284290 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
851 19:51:27.307478 <30>[ 43.768141] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
852 19:51:27.315668 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
853 19:51:27.396626 <30>[ 43.852722] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
854 19:51:27.409545 <30>[ 43.870272] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
855 19:51:27.417968 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
856 19:51:27.448645 <30>[ 43.910875] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
857 19:51:27.461139 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
858 19:51:27.489850 <30>[ 43.949317] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
859 19:51:27.497047 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
860 19:51:27.532990 <30>[ 43.994407] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
861 19:51:27.546406 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
862 19:51:27.567947 <30>[ 44.028408] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
863 19:51:27.576624 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
864 19:51:27.603603 <30>[ 44.058201] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
865 19:51:27.620204 <30>[ 44.074941] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
866 19:51:27.670056 <30>[ 44.131824] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
867 19:51:27.696103 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
868 19:51:27.747513 <30>[ 44.209135] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
869 19:51:27.776411 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
870 19:51:27.846967 <30>[ 44.307564] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
871 19:51:27.866236 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
872 19:51:27.926733 <30>[ 44.387867] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
873 19:51:27.954981 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
874 19:51:28.006055 <30>[ 44.467632] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
875 19:51:28.033730 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
876 19:51:28.087119 <30>[ 44.549176] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
877 19:51:28.112615 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
878 19:51:28.167440 <30>[ 44.628341] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
879 19:51:28.196711 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
880 19:51:28.245953 <30>[ 44.707742] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
881 19:51:28.256783 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
882 19:51:28.295728 <30>[ 44.757704] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
883 19:51:28.324249 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
884 19:51:28.353199 <28>[ 44.808670] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
885 19:51:28.361735 <28>[ 44.822758] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
886 19:51:28.405481 <30>[ 44.867872] systemd[1]: Starting systemd-journald.service - Journal Service...
887 19:51:28.424378 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
888 19:51:28.506889 <30>[ 44.968632] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
889 19:51:28.528616 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
890 19:51:28.587636 <30>[ 45.049641] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
891 19:51:28.636329 Starting [0;1;39msystemd-network-g… units from Kernel command line...
892 19:51:28.690488 <30>[ 45.150899] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
893 19:51:28.739330 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
894 19:51:28.810524 <30>[ 45.271761] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
895 19:51:28.874804 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
896 19:51:28.926742 <30>[ 45.389585] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
897 19:51:28.985960 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
898 19:51:29.008153 <30>[ 45.470009] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
899 19:51:29.041901 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
900 19:51:29.063469 <30>[ 45.524370] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
901 19:51:29.096765 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
902 19:51:29.215969 <30>[ 45.678590] systemd[1]: modprobe@configfs.service: Deactivated successfully.
903 19:51:29.246335 <30>[ 45.707844] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
904 19:51:29.275922 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
905 19:51:29.286511 <30>[ 45.749254] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
906 19:51:29.325720 <30>[ 45.786873] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
907 19:51:29.334153 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
908 19:51:29.351127 <30>[ 45.813859] systemd[1]: Started systemd-journald.service - Journal Service.
909 19:51:29.384897 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
910 19:51:29.425680 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
911 19:51:29.458447 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
912 19:51:29.487212 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
913 19:51:29.511619 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
914 19:51:29.539366 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
915 19:51:29.558252 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
916 19:51:29.585791 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
917 19:51:29.620385 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
918 19:51:29.675593 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
919 19:51:29.725027 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
920 19:51:29.795336 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
921 19:51:29.867293 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
922 19:51:29.961898 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
923 19:51:30.098534 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
924 19:51:30.152634 <46>[ 46.614523] systemd-journald[164]: Received client request to flush runtime journal.
925 19:51:30.219216 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
926 19:51:30.314417 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
927 19:51:31.435577 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
928 19:51:31.488237 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
929 19:51:32.002754 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
930 19:51:32.128019 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
931 19:51:32.155415 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
932 19:51:32.175442 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
933 19:51:32.255878 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
934 19:51:32.294737 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
935 19:51:33.288057 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
936 19:51:33.361001 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
937 19:51:33.633007 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
938 19:51:33.741409 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
939 19:51:33.818035 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
940 19:51:35.415673 <4>[ 51.880523] mmc1: unexpected status 0x2000980 after switch
941 19:51:35.496070 <4>[ 51.960663] mmc1: unexpected status 0x2000900 after switch
942 19:51:35.588668 <4>[ 52.053283] mmc1: unexpected status 0x2000900 after switch
943 19:51:35.699976 <4>[ 52.164637] mmc1: unexpected status 0x2000900 after switch
944 19:51:35.801072 [[0m[0;31m* [0m] (1 of 5) Job dev-ttyS0.device/start running (8s / 1min 30s)
945 19:51:35.906906 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
946 19:51:36.168340 [K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
947 19:51:36.308390 <5>[ 52.771794] cfg80211: Loading compiled-in X.509 certificates for regulatory database
948 19:51:37.187019 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
949 19:51:37.966680 <5>[ 54.431042] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
950 19:51:38.022135 <5>[ 54.484945] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
951 19:51:38.035471 <4>[ 54.497640] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
952 19:51:38.041523 <6>[ 54.506770] cfg80211: failed to load regulatory.db
953 19:51:38.994369 <46>[ 55.200895] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
954 19:51:38.995089 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
955 19:51:38.995674 <46>[ 55.334790] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
956 19:51:38.997360 <3>[ 55.427325] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
957 19:51:39.023949 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
958 19:51:39.728986 <3>[ 56.189443] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
959 19:51:40.505891 <3>[ 56.966654] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
960 19:51:41.279312 <3>[ 57.740182] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
961 19:51:42.053672 <3>[ 58.514399] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
962 19:51:42.825712 <3>[ 59.286648] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
963 19:51:43.606103 <3>[ 60.066657] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
964 19:51:44.405240 <3>[ 60.865968] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
965 19:51:47.674968 <3>[ 64.136254] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
966 19:51:48.433742 <3>[ 64.895116] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
967 19:51:48.466089 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
968 19:51:48.485580 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
969 19:51:48.506963 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
970 19:51:48.527637 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
971 19:51:48.599725 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
972 19:51:48.647843 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
973 19:51:48.720226 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
974 19:51:48.771846 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
975 19:51:48.821297 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
976 19:51:48.851691 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
977 19:51:48.893073 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
978 19:51:48.919784 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
979 19:51:48.959944 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
980 19:51:49.017671 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
981 19:51:49.051126 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
982 19:51:49.079269 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
983 19:51:49.112281 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
984 19:51:49.194816 <3>[ 65.657041] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
985 19:51:49.205963 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
986 19:51:49.227357 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
987 19:51:49.245786 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
988 19:51:49.287536 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
989 19:51:49.303275 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
990 19:51:49.335321 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
991 19:51:49.395138 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
992 19:51:49.443502 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
993 19:51:49.542944 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
994 19:51:49.632322 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
995 19:51:49.698313 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
996 19:51:49.733021 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
997 19:51:49.748342 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
998 19:51:49.966510 <3>[ 66.428041] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
999 19:51:50.076547 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1000 19:51:50.139191 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1001 19:51:50.207685 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1002 19:51:50.228672 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1003 19:51:50.257264 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1004 19:51:50.424518 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1005 19:51:50.727153 <3>[ 67.188531] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1006 19:51:50.847204 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1007 19:51:50.895722 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1008 19:51:50.921277 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1009 19:51:51.004218 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1010 19:51:51.197321 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1011 19:51:51.343703
1012 19:51:51.346381 Debian GNU/Linux 12 worm-armhf login: root (automatic login)
1013 19:51:51.346898
1014 19:51:51.486073 <3>[ 67.947825] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1015 19:51:51.720713 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Wed Nov 6 18:55:05 UTC 2024 armv7l
1016 19:51:51.721297
1017 19:51:51.726313 The programs included with the Debian GNU/Linux system are free software;
1018 19:51:51.732040 the exact distribution terms for each program are described in the
1019 19:51:51.737442 individual files in /usr/share/doc/*/copyright.
1020 19:51:51.737950
1021 19:51:51.745591 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1022 19:51:51.746110 permitted by applicable law.
1023 19:51:52.245040 <3>[ 68.706623] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1024 19:51:53.002786 <3>[ 69.465536] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1025 19:51:53.011885 <3>[ 69.474918] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
1026 19:51:56.731619 Unable to match end of the kernel message
1028 19:51:56.733389 Setting prompt string to ['/ #']
1029 19:51:56.734040 end: 2.4.4.1 login-action (duration 00:01:14) [common]
1031 19:51:56.735616 end: 2.4.4 auto-login-action (duration 00:01:14) [common]
1032 19:51:56.736311 start: 2.4.5 expect-shell-connection (timeout 00:02:25) [common]
1033 19:51:56.736834 Setting prompt string to ['/ #']
1034 19:51:56.737317 Forcing a shell prompt, looking for ['/ #']
1036 19:51:56.788391 / #
1037 19:51:56.789058 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1038 19:51:56.789576 Waiting using forced prompt support (timeout 00:02:30)
1039 19:51:56.793832
1040 19:51:56.797907 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1041 19:51:56.798543 start: 2.4.6 export-device-env (timeout 00:02:25) [common]
1042 19:51:56.799082 Sending with 10 millisecond of delay
1044 19:52:01.786886 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/948572/extract-nfsrootfs-56h1q9v0'
1045 19:52:01.797884 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/948572/extract-nfsrootfs-56h1q9v0'
1046 19:52:01.799405 Sending with 10 millisecond of delay
1048 19:52:03.897420 / # export NFS_SERVER_IP='192.168.6.2'
1049 19:52:03.908400 export NFS_SERVER_IP='192.168.6.2'
1050 19:52:03.909805 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1051 19:52:03.910463 end: 2.4 uboot-commands (duration 00:02:42) [common]
1052 19:52:03.911109 end: 2 uboot-action (duration 00:02:42) [common]
1053 19:52:03.911735 start: 3 lava-test-retry (timeout 00:06:07) [common]
1054 19:52:03.912444 start: 3.1 lava-test-shell (timeout 00:06:07) [common]
1055 19:52:03.912971 Using namespace: common
1057 19:52:04.014220 / # #
1058 19:52:04.014903 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1059 19:52:04.019403 #
1060 19:52:04.026260 Using /lava-948572
1062 19:52:04.127491 / # export SHELL=/bin/bash
1063 19:52:04.132960 export SHELL=/bin/bash
1065 19:52:04.240316 / # . /lava-948572/environment
1066 19:52:04.245774 . /lava-948572/environment
1068 19:52:04.359204 / # /lava-948572/bin/lava-test-runner /lava-948572/0
1069 19:52:04.359862 Test shell timeout: 10s (minimum of the action and connection timeout)
1070 19:52:04.363486 /lava-948572/bin/lava-test-runner /lava-948572/0
1071 19:52:04.760973 + export TESTRUN_ID=0_timesync-off
1072 19:52:04.768789 + TESTRUN_ID=0_timesync-off
1073 19:52:04.769292 + cd /lava-948572/0/tests/0_timesync-off
1074 19:52:04.769759 ++ cat uuid
1075 19:52:04.785648 + UUID=948572_1.6.2.4.1
1076 19:52:04.786154 + set +x
1077 19:52:04.794152 <LAVA_SIGNAL_STARTRUN 0_timesync-off 948572_1.6.2.4.1>
1078 19:52:04.794647 + systemctl stop systemd-timesyncd
1079 19:52:04.795404 Received signal: <STARTRUN> 0_timesync-off 948572_1.6.2.4.1
1080 19:52:04.795886 Starting test lava.0_timesync-off (948572_1.6.2.4.1)
1081 19:52:04.796518 Skipping test definition patterns.
1082 19:52:05.080848 + set +x
1083 19:52:05.081398 <LAVA_SIGNAL_ENDRUN 0_timesync-off 948572_1.6.2.4.1>
1084 19:52:05.082123 Received signal: <ENDRUN> 0_timesync-off 948572_1.6.2.4.1
1085 19:52:05.082656 Ending use of test pattern.
1086 19:52:05.083110 Ending test lava.0_timesync-off (948572_1.6.2.4.1), duration 0.29
1088 19:52:05.249348 + export TESTRUN_ID=1_kselftest-dt
1089 19:52:05.257327 + TESTRUN_ID=1_kselftest-dt
1090 19:52:05.257834 + cd /lava-948572/0/tests/1_kselftest-dt
1091 19:52:05.258306 ++ cat uuid
1092 19:52:05.274340 + UUID=948572_1.6.2.4.5
1093 19:52:05.274835 + set +x
1094 19:52:05.279925 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 948572_1.6.2.4.5>
1095 19:52:05.280459 + cd ./automated/linux/kselftest/
1096 19:52:05.281198 Received signal: <STARTRUN> 1_kselftest-dt 948572_1.6.2.4.5
1097 19:52:05.281673 Starting test lava.1_kselftest-dt (948572_1.6.2.4.5)
1098 19:52:05.282206 Skipping test definition patterns.
1099 19:52:05.308429 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1100 19:52:05.425498 INFO: install_deps skipped
1101 19:52:06.200858 --2024-11-06 19:52:06-- http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz
1102 19:52:06.229332 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1103 19:52:06.370224 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1104 19:52:06.511003 HTTP request sent, awaiting response... 200 OK
1105 19:52:06.511551 Length: 2557256 (2.4M) [application/octet-stream]
1106 19:52:06.516578 Saving to: 'kselftest_armhf.tar.gz'
1107 19:52:06.517067
1108 19:52:08.213907
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 180KB/s
kselftest_armhf.tar 7%[> ] 194.76K 352KB/s
kselftest_armhf.tar 15%[==> ] 386.01K 464KB/s
kselftest_armhf.tar 46%[========> ] 1.12M 1.01MB/s
kselftest_armhf.tar 64%[===========> ] 1.56M 1.17MB/s
kselftest_armhf.tar 84%[===============> ] 2.05M 1.33MB/s
kselftest_armhf.tar 100%[===================>] 2.44M 1.44MB/s in 1.7s
1109 19:52:08.214601
1110 19:52:08.520541 2024-11-06 19:52:08 (1.44 MB/s) - 'kselftest_armhf.tar.gz' saved [2557256/2557256]
1111 19:52:08.521210
1112 19:52:19.427438 skiplist:
1113 19:52:19.428205 ========================================
1114 19:52:19.432094 ========================================
1115 19:52:19.532914 dt:test_unprobed_devices.sh
1116 19:52:19.560312 ============== Tests to run ===============
1117 19:52:19.568772 dt:test_unprobed_devices.sh
1118 19:52:19.572724 ===========End Tests to run ===============
1119 19:52:19.580460 shardfile-dt pass
1120 19:52:19.804873 <12>[ 96.272383] kselftest: Running tests in dt
1121 19:52:19.834787 TAP version 13
1122 19:52:19.859257 1..1
1123 19:52:19.915833 # timeout set to 45
1124 19:52:19.916351 # selftests: dt: test_unprobed_devices.sh
1125 19:52:20.701868 # TAP version 13
1126 19:52:46.325755 # 1..257
1127 19:52:46.503119 # ok 1 / # SKIP
1128 19:52:46.520344 # ok 2 /clk_mcasp0
1129 19:52:46.594621 # ok 3 /clk_mcasp0_fixed # SKIP
1130 19:52:46.666690 # ok 4 /cpus/cpu@0 # SKIP
1131 19:52:46.739553 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1132 19:52:46.765499 # ok 6 /fixedregulator0
1133 19:52:46.781283 # ok 7 /leds
1134 19:52:46.805023 # ok 8 /ocp
1135 19:52:46.833390 # ok 9 /ocp/interconnect@44c00000
1136 19:52:46.856982 # ok 10 /ocp/interconnect@44c00000/segment@0
1137 19:52:46.876176 # ok 11 /ocp/interconnect@44c00000/segment@100000
1138 19:52:46.905851 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1139 19:52:46.979619 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1140 19:52:46.998158 # ok 14 /ocp/interconnect@44c00000/segment@200000
1141 19:52:47.021757 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1142 19:52:47.135747 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1143 19:52:47.210534 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1144 19:52:47.282401 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1145 19:52:47.355068 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1146 19:52:47.428632 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1147 19:52:47.507014 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1148 19:52:47.577101 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1149 19:52:47.650846 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1150 19:52:47.729844 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1151 19:52:47.802280 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1152 19:52:47.877088 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1153 19:52:47.946876 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1154 19:52:48.021031 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1155 19:52:48.095899 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1156 19:52:48.168559 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1157 19:52:48.243312 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1158 19:52:48.316921 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1159 19:52:48.391196 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1160 19:52:48.464965 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1161 19:52:48.539334 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1162 19:52:48.612640 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1163 19:52:48.687590 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1164 19:52:48.762223 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1165 19:52:48.836415 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1166 19:52:48.912803 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1167 19:52:48.984863 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1168 19:52:49.060061 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1169 19:52:49.134665 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1170 19:52:49.209138 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1171 19:52:49.283124 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1172 19:52:49.361606 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1173 19:52:49.433471 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1174 19:52:49.505453 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1175 19:52:49.579881 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1176 19:52:49.661376 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1177 19:52:49.733465 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1178 19:52:49.810981 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1179 19:52:49.883393 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1180 19:52:49.960683 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1181 19:52:50.033282 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1182 19:52:50.105751 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1183 19:52:50.180342 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1184 19:52:50.259041 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1185 19:52:50.332787 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1186 19:52:50.407145 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1187 19:52:50.480549 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1188 19:52:50.559383 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1189 19:52:50.632634 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1190 19:52:50.704170 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1191 19:52:50.791312 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1192 19:52:50.860839 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1193 19:52:50.933552 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1194 19:52:51.005144 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1195 19:52:51.078617 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1196 19:52:51.160240 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1197 19:52:51.233172 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1198 19:52:51.309699 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1199 19:52:51.383272 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1200 19:52:51.458620 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1201 19:52:51.528967 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1202 19:52:51.603690 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1203 19:52:51.676637 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1204 19:52:51.750897 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1205 19:52:51.829429 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1206 19:52:51.903088 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1207 19:52:51.982291 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1208 19:52:52.052935 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1209 19:52:52.127054 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1210 19:52:52.201724 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1211 19:52:52.271134 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1212 19:52:52.349882 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1213 19:52:52.422176 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1214 19:52:52.498793 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1215 19:52:52.570692 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1216 19:52:52.645408 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1217 19:52:52.718003 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1218 19:52:52.796396 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1219 19:52:52.867388 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1220 19:52:52.942890 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1221 19:52:52.964728 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1222 19:52:52.989775 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1223 19:52:53.014803 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1224 19:52:53.038915 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1225 19:52:53.063732 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1226 19:52:53.088139 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1227 19:52:53.113085 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1228 19:52:53.135692 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1229 19:52:53.249038 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1230 19:52:53.271387 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1231 19:52:53.295586 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1232 19:52:53.319595 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1233 19:52:53.431793 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1234 19:52:53.505306 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1235 19:52:53.584063 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1236 19:52:53.659603 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1237 19:52:53.733767 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1238 19:52:53.808678 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1239 19:52:53.878814 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1240 19:52:53.956286 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1241 19:52:54.028416 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1242 19:52:54.103359 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1243 19:52:54.178205 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1244 19:52:54.252432 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1245 19:52:54.325698 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1246 19:52:54.402193 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1247 19:52:54.481532 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1248 19:52:54.554829 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1249 19:52:54.574696 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1250 19:52:54.647580 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1251 19:52:54.719387 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1252 19:52:54.798748 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1253 19:52:54.819694 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1254 19:52:54.891408 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1255 19:52:54.914792 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1256 19:52:54.987553 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1257 19:52:55.011641 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1258 19:52:55.036533 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1259 19:52:55.060281 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1260 19:52:55.085453 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1261 19:52:55.109650 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1262 19:52:55.133893 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1263 19:52:55.161047 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1264 19:52:55.237357 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1265 19:52:55.259524 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1266 19:52:55.283887 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1267 19:52:55.361875 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1268 19:52:55.437979 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1269 19:52:55.454853 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1270 19:52:55.563171 # not ok 144 /ocp/interconnect@47c00000
1271 19:52:55.632004 # not ok 145 /ocp/interconnect@47c00000/segment@0
1272 19:52:55.653488 # ok 146 /ocp/interconnect@48000000
1273 19:52:55.678931 # ok 147 /ocp/interconnect@48000000/segment@0
1274 19:52:55.708771 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1275 19:52:55.729231 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1276 19:52:55.756461 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1277 19:52:55.779203 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1278 19:52:55.800912 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1279 19:52:55.830464 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1280 19:52:55.849934 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1281 19:52:55.924139 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1282 19:52:56.000597 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1283 19:52:56.024524 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1284 19:52:56.049887 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1285 19:52:56.076384 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1286 19:52:56.099841 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1287 19:52:56.123468 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1288 19:52:56.144969 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1289 19:52:56.169046 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1290 19:52:56.193075 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1291 19:52:56.219242 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1292 19:52:56.245853 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1293 19:52:56.269255 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1294 19:52:56.295827 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1295 19:52:56.318649 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1296 19:52:56.339676 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1297 19:52:56.369273 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1298 19:52:56.394308 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1299 19:52:56.418106 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1300 19:52:56.440153 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1301 19:52:56.465002 # ok 175 /ocp/interconnect@48000000/segment@100000
1302 19:52:56.489555 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1303 19:52:56.512011 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1304 19:52:56.587633 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1305 19:52:56.668592 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1306 19:52:56.736842 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1307 19:52:56.812692 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1308 19:52:56.889812 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1309 19:52:56.963272 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1310 19:52:57.034687 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1311 19:52:57.110056 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1312 19:52:57.130324 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1313 19:52:57.154651 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1314 19:52:57.178442 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1315 19:52:57.207324 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1316 19:52:57.229544 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1317 19:52:57.252552 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1318 19:52:57.275616 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1319 19:52:57.300922 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1320 19:52:57.324297 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1321 19:52:57.348307 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1322 19:52:57.377147 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1323 19:52:57.400070 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1324 19:52:57.419504 # ok 198 /ocp/interconnect@48000000/segment@200000
1325 19:52:57.449258 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1326 19:52:57.522413 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1327 19:52:57.546077 # ok 201 /ocp/interconnect@48000000/segment@300000
1328 19:52:57.569201 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1329 19:52:57.591724 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1330 19:52:57.616316 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1331 19:52:57.640275 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1332 19:52:57.668484 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1333 19:52:57.689556 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1334 19:52:57.763652 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1335 19:52:57.786367 # ok 209 /ocp/interconnect@4a000000
1336 19:52:57.806806 # ok 210 /ocp/interconnect@4a000000/segment@0
1337 19:52:57.832749 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1338 19:52:57.857904 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1339 19:52:57.883831 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1340 19:52:57.905903 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1341 19:52:57.980341 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1342 19:52:58.091288 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1343 19:52:58.163914 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1344 19:52:58.276067 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1345 19:52:58.348574 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1346 19:52:58.421165 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1347 19:52:58.520729 # not ok 221 /ocp/interconnect@4b140000
1348 19:52:58.595189 # not ok 222 /ocp/interconnect@4b140000/segment@0
1349 19:52:58.673806 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1350 19:52:58.695491 # ok 224 /ocp/target-module@40300000
1351 19:52:58.717213 # ok 225 /ocp/target-module@40300000/sram@0
1352 19:52:58.791238 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1353 19:52:58.865234 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1354 19:52:58.885477 # ok 228 /ocp/target-module@47400000
1355 19:52:58.915626 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1356 19:52:58.937561 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1357 19:52:58.962175 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1358 19:52:58.985366 # ok 232 /ocp/target-module@47400000/usb@1400
1359 19:52:59.007323 # ok 233 /ocp/target-module@47400000/usb@1800
1360 19:52:59.026959 # ok 234 /ocp/target-module@47810000
1361 19:52:59.054256 # ok 235 /ocp/target-module@49000000
1362 19:52:59.071554 # ok 236 /ocp/target-module@49000000/dma@0
1363 19:52:59.096149 # ok 237 /ocp/target-module@49800000
1364 19:52:59.124233 # ok 238 /ocp/target-module@49800000/dma@0
1365 19:52:59.142265 # ok 239 /ocp/target-module@49900000
1366 19:52:59.166910 # ok 240 /ocp/target-module@49900000/dma@0
1367 19:52:59.188633 # ok 241 /ocp/target-module@49a00000
1368 19:52:59.216318 # ok 242 /ocp/target-module@49a00000/dma@0
1369 19:52:59.236405 # ok 243 /ocp/target-module@4c000000
1370 19:52:59.313652 # not ok 244 /ocp/target-module@4c000000/emif@0
1371 19:52:59.331272 # ok 245 /ocp/target-module@50000000
1372 19:52:59.356376 # ok 246 /ocp/target-module@53100000
1373 19:52:59.429350 # not ok 247 /ocp/target-module@53100000/sham@0
1374 19:52:59.455508 # ok 248 /ocp/target-module@53500000
1375 19:52:59.527507 # not ok 249 /ocp/target-module@53500000/aes@0
1376 19:52:59.553387 # ok 250 /ocp/target-module@56000000
1377 19:52:59.658572 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1378 19:52:59.733023 # ok 252 /opp-table # SKIP
1379 19:52:59.799850 # ok 253 /soc # SKIP
1380 19:52:59.824926 # ok 254 /sound
1381 19:52:59.847622 # ok 255 /target-module@4b000000
1382 19:52:59.873072 # ok 256 /target-module@4b000000/target-module@140000
1383 19:52:59.894354 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1384 19:52:59.902701 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1385 19:52:59.911745 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1386 19:53:02.066127 dt_test_unprobed_devices_sh_ skip
1387 19:53:02.071667 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1388 19:53:02.077118 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1389 19:53:02.077649 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1390 19:53:02.085877 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1391 19:53:02.086353 dt_test_unprobed_devices_sh_fixedregulator0 pass
1392 19:53:02.091624 dt_test_unprobed_devices_sh_leds pass
1393 19:53:02.097029 dt_test_unprobed_devices_sh_ocp pass
1394 19:53:02.102609 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1395 19:53:02.108230 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1396 19:53:02.113919 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1397 19:53:02.119458 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1398 19:53:02.130738 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1399 19:53:02.136207 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1400 19:53:02.141910 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1401 19:53:02.153285 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1402 19:53:02.164558 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1403 19:53:02.170052 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1404 19:53:02.181308 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1405 19:53:02.192653 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1406 19:53:02.203674 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1407 19:53:02.214871 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1408 19:53:02.220477 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1409 19:53:02.231706 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1410 19:53:02.242884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1411 19:53:02.254014 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1412 19:53:02.259575 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1413 19:53:02.270790 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1414 19:53:02.281994 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1415 19:53:02.293191 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1416 19:53:02.304377 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1417 19:53:02.310054 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1418 19:53:02.321161 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1419 19:53:02.332344 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1420 19:53:02.343544 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1421 19:53:02.349157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1422 19:53:02.360410 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1423 19:53:02.371522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1424 19:53:02.382738 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1425 19:53:02.393935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1426 19:53:02.405138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1427 19:53:02.416340 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1428 19:53:02.427541 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1429 19:53:02.438733 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1430 19:53:02.449900 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1431 19:53:02.461094 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1432 19:53:02.472286 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1433 19:53:02.483488 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1434 19:53:02.494704 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1435 19:53:02.505907 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1436 19:53:02.517086 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1437 19:53:02.528320 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1438 19:53:02.539541 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1439 19:53:02.550628 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1440 19:53:02.561872 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1441 19:53:02.573041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1442 19:53:02.584242 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1443 19:53:02.595394 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1444 19:53:02.601086 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1445 19:53:02.612215 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1446 19:53:02.623461 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1447 19:53:02.634589 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1448 19:53:02.645778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1449 19:53:02.657011 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1450 19:53:02.668229 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1451 19:53:02.679362 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1452 19:53:02.690609 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1453 19:53:02.701779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1454 19:53:02.713041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1455 19:53:02.718605 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1456 19:53:02.729830 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1457 19:53:02.740953 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1458 19:53:02.752194 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1459 19:53:02.763364 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1460 19:53:02.774516 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1461 19:53:02.785737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1462 19:53:02.796929 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1463 19:53:02.808226 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1464 19:53:02.819329 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1465 19:53:02.830586 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1466 19:53:02.841684 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1467 19:53:02.852891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1468 19:53:02.864160 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1469 19:53:02.875273 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1470 19:53:02.880909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1471 19:53:02.892069 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1472 19:53:02.903287 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1473 19:53:02.914519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1474 19:53:02.925663 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1475 19:53:02.936905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1476 19:53:02.948040 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1477 19:53:02.959189 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1478 19:53:02.970412 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1479 19:53:02.981658 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1480 19:53:02.992861 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1481 19:53:03.004021 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1482 19:53:03.009636 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1483 19:53:03.020843 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1484 19:53:03.032059 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1485 19:53:03.037633 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1486 19:53:03.048807 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1487 19:53:03.054451 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1488 19:53:03.065592 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1489 19:53:03.076724 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1490 19:53:03.082370 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1491 19:53:03.093673 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1492 19:53:03.104733 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1493 19:53:03.115891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1494 19:53:03.127174 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1495 19:53:03.138388 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1496 19:53:03.149590 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1497 19:53:03.166438 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1498 19:53:03.177610 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1499 19:53:03.188850 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1500 19:53:03.200061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1501 19:53:03.211238 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1502 19:53:03.222481 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1503 19:53:03.233804 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1504 19:53:03.250632 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1505 19:53:03.261814 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1506 19:53:03.273018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1507 19:53:03.289897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1508 19:53:03.301062 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1509 19:53:03.306733 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1510 19:53:03.317817 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1511 19:53:03.323407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1512 19:53:03.334635 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1513 19:53:03.345820 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1514 19:53:03.351397 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1515 19:53:03.362672 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1516 19:53:03.368343 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1517 19:53:03.379451 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1518 19:53:03.385039 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1519 19:53:03.396208 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1520 19:53:03.401835 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1521 19:53:03.412990 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1522 19:53:03.424191 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1523 19:53:03.435340 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1524 19:53:03.441036 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1525 19:53:03.452295 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1526 19:53:03.463352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1527 19:53:03.474531 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1528 19:53:03.480186 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1529 19:53:03.485754 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1530 19:53:03.491334 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1531 19:53:03.496946 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1532 19:53:03.502586 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1533 19:53:03.513770 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1534 19:53:03.519346 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1535 19:53:03.530475 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1536 19:53:03.536192 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1537 19:53:03.541712 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1538 19:53:03.552911 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1539 19:53:03.558464 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1540 19:53:03.569712 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1541 19:53:03.575266 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1542 19:53:03.586450 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1543 19:53:03.592104 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1544 19:53:03.603244 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1545 19:53:03.608836 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1546 19:53:03.614428 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1547 19:53:03.625687 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1548 19:53:03.631251 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1549 19:53:03.642443 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1550 19:53:03.648078 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1551 19:53:03.659240 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1552 19:53:03.664834 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1553 19:53:03.676030 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1554 19:53:03.681703 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1555 19:53:03.692798 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1556 19:53:03.698439 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1557 19:53:03.709603 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1558 19:53:03.715220 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1559 19:53:03.726399 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1560 19:53:03.732021 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1561 19:53:03.737602 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1562 19:53:03.748799 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1563 19:53:03.760017 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1564 19:53:03.771166 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1565 19:53:03.782392 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1566 19:53:03.793583 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1567 19:53:03.799186 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1568 19:53:03.810387 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1569 19:53:03.821596 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1570 19:53:03.832788 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1571 19:53:03.844016 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1572 19:53:03.849609 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1573 19:53:03.860784 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1574 19:53:03.866397 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1575 19:53:03.877577 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1576 19:53:03.883160 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1577 19:53:03.894356 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1578 19:53:03.899973 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1579 19:53:03.911129 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1580 19:53:03.916774 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1581 19:53:03.927905 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1582 19:53:03.933530 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1583 19:53:03.944722 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1584 19:53:03.950319 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1585 19:53:03.961499 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1586 19:53:03.967104 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1587 19:53:03.972722 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1588 19:53:03.983877 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1589 19:53:03.989491 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1590 19:53:04.000739 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1591 19:53:04.006287 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1592 19:53:04.017479 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1593 19:53:04.023077 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1594 19:53:04.028752 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1595 19:53:04.034277 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1596 19:53:04.045468 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1597 19:53:04.051064 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1598 19:53:04.062253 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1599 19:53:04.067851 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1600 19:53:04.079033 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1601 19:53:04.090239 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1602 19:53:04.101442 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1603 19:53:04.107019 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1604 19:53:04.118223 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1605 19:53:04.129427 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1606 19:53:04.135044 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1607 19:53:04.140649 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1608 19:53:04.146251 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1609 19:53:04.151853 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1610 19:53:04.157471 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1611 19:53:04.163075 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1612 19:53:04.168695 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1613 19:53:04.174270 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1614 19:53:04.185533 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1615 19:53:04.191084 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1616 19:53:04.196670 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1617 19:53:04.202269 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1618 19:53:04.207854 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1619 19:53:04.213495 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1620 19:53:04.219087 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1621 19:53:04.224783 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1622 19:53:04.230288 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1623 19:53:04.235926 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1624 19:53:04.241534 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1625 19:53:04.247092 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1626 19:53:04.252761 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1627 19:53:04.258296 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1628 19:53:04.263862 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1629 19:53:04.269487 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1630 19:53:04.275094 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1631 19:53:04.280786 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1632 19:53:04.286292 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1633 19:53:04.291905 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1634 19:53:04.297509 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1635 19:53:04.303149 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1636 19:53:04.308774 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1637 19:53:04.314313 dt_test_unprobed_devices_sh_opp-table skip
1638 19:53:04.314790 dt_test_unprobed_devices_sh_soc skip
1639 19:53:04.319888 dt_test_unprobed_devices_sh_sound pass
1640 19:53:04.325520 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1641 19:53:04.331140 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1642 19:53:04.336773 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1643 19:53:04.342331 dt_test_unprobed_devices_sh fail
1644 19:53:04.347921 + ../../utils/send-to-lava.sh ./output/result.txt
1645 19:53:04.352586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1646 19:53:04.353536 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1648 19:53:04.370889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1649 19:53:04.371672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1651 19:53:04.458480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1652 19:53:04.459250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1654 19:53:04.552266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1655 19:53:04.553041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1657 19:53:04.639586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1658 19:53:04.640404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1660 19:53:04.727408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1661 19:53:04.728200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1663 19:53:04.834013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1664 19:53:04.834809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1666 19:53:04.929095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1667 19:53:04.929942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1669 19:53:05.017610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1670 19:53:05.018471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1672 19:53:05.113411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1673 19:53:05.114309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1675 19:53:05.207802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1676 19:53:05.208656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1678 19:53:05.304101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1679 19:53:05.304935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1681 19:53:05.393550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1682 19:53:05.394382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1684 19:53:05.483197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1685 19:53:05.484111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1687 19:53:05.574787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1688 19:53:05.575571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1690 19:53:05.664404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1691 19:53:05.665174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1693 19:53:05.753106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1694 19:53:05.753863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1696 19:53:05.848183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1697 19:53:05.848948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1699 19:53:05.936989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1700 19:53:05.937737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1702 19:53:06.024749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1703 19:53:06.025492 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1705 19:53:06.118343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1706 19:53:06.119084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1708 19:53:06.212427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1709 19:53:06.213182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1711 19:53:06.300968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1712 19:53:06.301711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1714 19:53:06.388344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1715 19:53:06.389105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1717 19:53:06.475413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1718 19:53:06.476180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1720 19:53:06.564515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1721 19:53:06.565283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1723 19:53:06.656679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1724 19:53:06.657430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1726 19:53:06.752393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1727 19:53:06.753135 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1729 19:53:06.841227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1730 19:53:06.841987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1732 19:53:06.928519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1733 19:53:06.929283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1735 19:53:07.014102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1736 19:53:07.014855 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1738 19:53:07.109655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1739 19:53:07.110440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1741 19:53:07.196807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1742 19:53:07.197621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1744 19:53:07.285875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1745 19:53:07.286607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1747 19:53:07.378225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1748 19:53:07.379008 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1750 19:53:07.468059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1751 19:53:07.468812 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1753 19:53:07.555737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1754 19:53:07.556531 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1756 19:53:07.650564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1757 19:53:07.651310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1759 19:53:07.744942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1760 19:53:07.745698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1762 19:53:07.833056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1763 19:53:07.833808 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1765 19:53:07.920773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1766 19:53:07.921530 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1768 19:53:08.014594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1769 19:53:08.015338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1771 19:53:08.102993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1772 19:53:08.103734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1774 19:53:08.191788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1775 19:53:08.192597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1777 19:53:08.284234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1778 19:53:08.284981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1780 19:53:08.373099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1781 19:53:08.373866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1783 19:53:08.461608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1784 19:53:08.462353 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1786 19:53:08.554861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1787 19:53:08.555607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1789 19:53:08.643431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1790 19:53:08.644214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1792 19:53:08.737279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1793 19:53:08.738036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1795 19:53:08.832068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1796 19:53:08.832834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1798 19:53:08.929762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1799 19:53:08.930515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1801 19:53:09.023001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1802 19:53:09.023736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1804 19:53:09.117263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1805 19:53:09.118009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1807 19:53:09.206361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1808 19:53:09.207122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1810 19:53:09.294459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1811 19:53:09.295210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1813 19:53:09.387765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1814 19:53:09.388577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1816 19:53:09.475734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1817 19:53:09.476528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1819 19:53:09.563805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1820 19:53:09.564598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1822 19:53:09.658529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1823 19:53:09.659284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1825 19:53:09.747811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1826 19:53:09.748596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1828 19:53:09.836234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1829 19:53:09.836974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1831 19:53:09.931294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1832 19:53:09.932070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1834 19:53:10.025946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1835 19:53:10.026689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1837 19:53:10.115277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1838 19:53:10.116050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1840 19:53:10.203046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1841 19:53:10.203803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1843 19:53:10.298925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1844 19:53:10.299669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1846 19:53:10.394853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1847 19:53:10.395604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1849 19:53:10.488489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1850 19:53:10.489233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1852 19:53:10.582567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1853 19:53:10.583349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1855 19:53:10.671392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1856 19:53:10.672142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1858 19:53:10.759418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1859 19:53:10.760168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1861 19:53:10.847379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1862 19:53:10.848219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1864 19:53:10.944156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1865 19:53:10.944936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1867 19:53:11.037668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1868 19:53:11.038412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1870 19:53:11.132073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1871 19:53:11.132832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1873 19:53:11.225575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1874 19:53:11.226330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1876 19:53:11.319946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1877 19:53:11.320750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1879 19:53:11.407377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1880 19:53:11.408166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1882 19:53:11.501576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1883 19:53:11.502324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1885 19:53:11.594866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1886 19:53:11.595602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1888 19:53:11.684002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1889 19:53:11.684751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1891 19:53:11.772939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1892 19:53:11.773677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1894 19:53:11.867523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1895 19:53:11.868310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1897 19:53:11.963636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1898 19:53:11.964416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1900 19:53:12.058493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1901 19:53:12.059245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1903 19:53:12.147350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1904 19:53:12.148135 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1906 19:53:12.241119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1907 19:53:12.241972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1909 19:53:12.330172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1910 19:53:12.330941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1912 19:53:12.426193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1913 19:53:12.427003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1915 19:53:12.520962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1916 19:53:12.521741 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1918 19:53:12.612320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1919 19:53:12.613119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1921 19:53:12.702663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1922 19:53:12.703435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1924 19:53:12.796535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1925 19:53:12.797328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1927 19:53:12.890450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1928 19:53:12.891238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1930 19:53:12.978166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1931 19:53:12.978943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1933 19:53:13.070314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1934 19:53:13.071076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1936 19:53:13.176694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1937 19:53:13.177485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1939 19:53:13.271492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1940 19:53:13.272306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1942 19:53:13.359502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1943 19:53:13.360294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1945 19:53:13.446706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1946 19:53:13.447466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1948 19:53:13.540517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1949 19:53:13.541314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1951 19:53:13.628329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1952 19:53:13.629089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1954 19:53:13.716485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1955 19:53:13.717243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1957 19:53:13.811300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1958 19:53:13.812090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1960 19:53:13.899329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1961 19:53:13.900092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1963 19:53:13.987484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1964 19:53:13.988275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1966 19:53:14.075366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1967 19:53:14.076144 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1969 19:53:14.166070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1970 19:53:14.166817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1972 19:53:14.259643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1973 19:53:14.260433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1975 19:53:14.353172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1976 19:53:14.353947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1978 19:53:14.440800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1979 19:53:14.441561 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1981 19:53:14.528076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1982 19:53:14.528834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1984 19:53:14.616465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1985 19:53:14.617204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1987 19:53:14.711034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1988 19:53:14.711775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1990 19:53:14.799959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1991 19:53:14.800737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1993 19:53:14.896502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1994 19:53:14.897243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1996 19:53:14.989772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1997 19:53:14.990513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1999 19:53:15.077731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
2000 19:53:15.078469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
2002 19:53:15.164890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
2003 19:53:15.165644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
2005 19:53:15.257679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
2007 19:53:15.260870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
2008 19:53:15.345422 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
2010 19:53:15.348598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2011 19:53:15.433219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2013 19:53:15.436326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2014 19:53:15.529413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2015 19:53:15.530160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2017 19:53:15.622280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2018 19:53:15.623053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2020 19:53:15.708644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2021 19:53:15.709432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2023 19:53:15.796383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2024 19:53:15.797128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2026 19:53:15.883113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2027 19:53:15.883897 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2029 19:53:15.978988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2030 19:53:15.979790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2032 19:53:16.065919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2033 19:53:16.066670 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2035 19:53:16.154371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2036 19:53:16.155124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2038 19:53:16.241727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2039 19:53:16.242467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2041 19:53:16.336253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2042 19:53:16.337021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2044 19:53:16.423458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2045 19:53:16.424217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2047 19:53:16.512291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2048 19:53:16.513033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2050 19:53:16.605516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2051 19:53:16.606265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2053 19:53:16.699551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2054 19:53:16.700334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2056 19:53:16.794844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2057 19:53:16.795594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2059 19:53:16.883804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2060 19:53:16.884600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2062 19:53:16.975847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2063 19:53:16.976655 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2065 19:53:17.069665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2066 19:53:17.070439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2068 19:53:17.162932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2069 19:53:17.163763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2071 19:53:17.253060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2072 19:53:17.253882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2074 19:53:17.340009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2075 19:53:17.340762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2077 19:53:17.429780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2078 19:53:17.430691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2080 19:53:17.519096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2081 19:53:17.520034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2083 19:53:17.606779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2084 19:53:17.607571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2086 19:53:17.700513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2087 19:53:17.701257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2089 19:53:17.795432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2090 19:53:17.796178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2092 19:53:17.883400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2093 19:53:17.884156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2095 19:53:17.970903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2096 19:53:17.971643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2098 19:53:18.072836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2099 19:53:18.073585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2101 19:53:18.170707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2102 19:53:18.171455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2104 19:53:18.259932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2105 19:53:18.260722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2107 19:53:18.352209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2108 19:53:18.352959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2110 19:53:18.439743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2111 19:53:18.440549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2113 19:53:18.537299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2114 19:53:18.538045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2116 19:53:18.628323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2117 19:53:18.629056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2119 19:53:18.722580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2120 19:53:18.723316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2122 19:53:18.809803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2123 19:53:18.810543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2125 19:53:18.898862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2126 19:53:18.899612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2128 19:53:18.991715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2129 19:53:18.992493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2131 19:53:19.080107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2132 19:53:19.080844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2134 19:53:19.167085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2135 19:53:19.167836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2137 19:53:19.257895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2138 19:53:19.258637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2140 19:53:19.349242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2141 19:53:19.349995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2143 19:53:19.442674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2144 19:53:19.443440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2146 19:53:19.534870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2147 19:53:19.535609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2149 19:53:19.624178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2150 19:53:19.624929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2152 19:53:19.716979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2153 19:53:19.717718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2155 19:53:19.805375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2156 19:53:19.806117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2158 19:53:19.897151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2159 19:53:19.897906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2161 19:53:19.986167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2162 19:53:19.986909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2164 19:53:20.079307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2165 19:53:20.080066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2167 19:53:20.172772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2168 19:53:20.173527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2170 19:53:20.258544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2171 19:53:20.259283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2173 19:53:20.353590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2174 19:53:20.354345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2176 19:53:20.442027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2177 19:53:20.442789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2179 19:53:20.531668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2180 19:53:20.532461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2182 19:53:20.625762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2183 19:53:20.626504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2185 19:53:20.717992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2186 19:53:20.718731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2188 19:53:20.806853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2189 19:53:20.807606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2191 19:53:20.893471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2192 19:53:20.894214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2194 19:53:20.988408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2195 19:53:20.989164 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2197 19:53:21.074824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2198 19:53:21.075569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2200 19:53:21.170659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2201 19:53:21.171410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2203 19:53:21.257470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2204 19:53:21.258214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2206 19:53:21.349351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2207 19:53:21.350103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2209 19:53:21.442911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2210 19:53:21.443659 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2212 19:53:21.533110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2213 19:53:21.533857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2215 19:53:21.621402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2216 19:53:21.622151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2218 19:53:21.716015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2219 19:53:21.716774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2221 19:53:21.802183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2222 19:53:21.802922 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2224 19:53:21.890516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2225 19:53:21.891260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2227 19:53:21.982730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2228 19:53:21.983501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2230 19:53:22.078955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2231 19:53:22.079714 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2233 19:53:22.172219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2234 19:53:22.172978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2236 19:53:22.260791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2237 19:53:22.261611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2239 19:53:22.352227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2240 19:53:22.352968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2242 19:53:22.447386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2243 19:53:22.448186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2245 19:53:22.540351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2246 19:53:22.541109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2248 19:53:22.627133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2249 19:53:22.627876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2251 19:53:22.716342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2252 19:53:22.717085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2254 19:53:22.804139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2255 19:53:22.804886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2257 19:53:22.897805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2258 19:53:22.898562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2260 19:53:22.985115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2261 19:53:22.985876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2263 19:53:23.072389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2264 19:53:23.073135 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2266 19:53:23.165279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2267 19:53:23.166042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2269 19:53:23.256843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2270 19:53:23.257594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2272 19:53:23.346168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2273 19:53:23.346921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2275 19:53:23.434595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2276 19:53:23.435345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2278 19:53:23.525458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2279 19:53:23.526222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2281 19:53:23.621087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2282 19:53:23.621841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2284 19:53:23.715306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2285 19:53:23.716092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2287 19:53:23.801807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2288 19:53:23.802557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2290 19:53:23.890724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2291 19:53:23.891485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2293 19:53:23.984909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2294 19:53:23.985666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2296 19:53:24.074800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2297 19:53:24.075548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2299 19:53:24.162149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2300 19:53:24.162896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2302 19:53:24.255194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2303 19:53:24.255937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2305 19:53:24.349558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2306 19:53:24.350306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2308 19:53:24.438632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2309 19:53:24.439430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2311 19:53:24.527641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2312 19:53:24.528435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2314 19:53:24.615098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2315 19:53:24.615836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2317 19:53:24.707573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2318 19:53:24.708341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2320 19:53:24.796984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2321 19:53:24.797723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2323 19:53:24.885652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2324 19:53:24.886402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2326 19:53:24.970514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2328 19:53:24.973670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2329 19:53:25.058584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2330 19:53:25.059318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2332 19:53:25.154212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2333 19:53:25.154963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2335 19:53:25.241451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2336 19:53:25.242196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2338 19:53:25.330003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2339 19:53:25.330813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2341 19:53:25.423435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2342 19:53:25.424182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2344 19:53:25.516167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2345 19:53:25.516898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2347 19:53:25.603493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2348 19:53:25.604282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2350 19:53:25.690864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2351 19:53:25.691602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2353 19:53:25.778637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2354 19:53:25.779369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2356 19:53:25.872264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2357 19:53:25.873002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2359 19:53:25.966751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2360 19:53:25.967484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2362 19:53:26.059130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2363 19:53:26.059867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2365 19:53:26.148004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2366 19:53:26.148750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2368 19:53:26.235847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2369 19:53:26.236635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2371 19:53:26.329677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2372 19:53:26.330409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2374 19:53:26.416971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2375 19:53:26.417714 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2377 19:53:26.506120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2378 19:53:26.506865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2380 19:53:26.598791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2381 19:53:26.599537 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2383 19:53:26.693334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2384 19:53:26.694069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2386 19:53:26.782363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2387 19:53:26.783112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2389 19:53:26.869179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2390 19:53:26.869922 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2392 19:53:26.964596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2393 19:53:26.965334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2395 19:53:27.051405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2396 19:53:27.052151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2398 19:53:27.146410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2399 19:53:27.147160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2401 19:53:27.232703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2402 19:53:27.233450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2404 19:53:27.324636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2405 19:53:27.325420 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2407 19:53:27.413460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2408 19:53:27.414190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2410 19:53:27.502146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2411 19:53:27.502866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2413 19:53:27.597439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2414 19:53:27.598216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2416 19:53:27.685990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2417 19:53:27.686724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2419 19:53:27.770583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2420 19:53:27.771075 + set +x
2421 19:53:27.771784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2423 19:53:27.779502 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 948572_1.6.2.4.5>
2424 19:53:27.780009 <LAVA_TEST_RUNNER EXIT>
2425 19:53:27.780722 Received signal: <ENDRUN> 1_kselftest-dt 948572_1.6.2.4.5
2426 19:53:27.781215 Ending use of test pattern.
2427 19:53:27.781670 Ending test lava.1_kselftest-dt (948572_1.6.2.4.5), duration 82.50
2429 19:53:27.783336 ok: lava_test_shell seems to have completed
2430 19:53:27.797532 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2431 19:53:27.799599 end: 3.1 lava-test-shell (duration 00:01:24) [common]
2432 19:53:27.800262 end: 3 lava-test-retry (duration 00:01:24) [common]
2433 19:53:27.800891 start: 4 finalize (timeout 00:04:43) [common]
2434 19:53:27.801513 start: 4.1 power-off (timeout 00:00:30) [common]
2435 19:53:27.802605 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-04'
2436 19:53:27.836576 >> OK - accepted request
2437 19:53:27.838396 Returned 0 in 0 seconds
2438 19:53:27.939559 end: 4.1 power-off (duration 00:00:00) [common]
2440 19:53:27.941372 start: 4.2 read-feedback (timeout 00:04:43) [common]
2441 19:53:27.942557 Listened to connection for namespace 'common' for up to 1s
2442 19:53:27.943481 Listened to connection for namespace 'common' for up to 1s
2443 19:53:28.943313 Finalising connection for namespace 'common'
2444 19:53:28.944052 Disconnecting from shell: Finalise
2445 19:53:28.944621 / #
2446 19:53:29.045586 end: 4.2 read-feedback (duration 00:00:01) [common]
2447 19:53:29.046253 end: 4 finalize (duration 00:00:01) [common]
2448 19:53:29.046975 Cleaning after the job
2449 19:53:29.047632 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948572/tftp-deploy-mc8odb6d/ramdisk
2450 19:53:29.058190 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948572/tftp-deploy-mc8odb6d/kernel
2451 19:53:29.063640 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948572/tftp-deploy-mc8odb6d/dtb
2452 19:53:29.064975 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948572/tftp-deploy-mc8odb6d/nfsrootfs
2453 19:53:29.164153 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948572/tftp-deploy-mc8odb6d/modules
2454 19:53:29.175336 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/948572
2455 19:53:32.106906 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/948572
2456 19:53:32.107483 Job finished correctly