Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 19:21:22.258984 lava-dispatcher, installed at version: 2024.01
2 19:21:22.259794 start: 0 validate
3 19:21:22.260296 Start time: 2024-11-06 19:21:22.260264+00:00 (UTC)
4 19:21:22.260895 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 19:21:22.261453 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 19:21:22.291180 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 19:21:22.291751 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 19:21:22.316502 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 19:21:22.317156 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 19:21:22.347246 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 19:21:22.347785 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 19:21:22.370473 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 19:21:22.371159 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 19:21:22.412149 validate duration: 0.15
16 19:21:22.413146 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:21:22.413527 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:21:22.413883 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:21:22.414928 Not decompressing ramdisk as can be used compressed.
20 19:21:22.415447 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 19:21:22.415754 saving as /var/lib/lava/dispatcher/tmp/948501/tftp-deploy-dih1vpji/ramdisk/initrd.cpio.gz
22 19:21:22.416075 total size: 4775763 (4 MB)
23 19:21:22.445482 progress 0 % (0 MB)
24 19:21:22.449234 progress 5 % (0 MB)
25 19:21:22.452928 progress 10 % (0 MB)
26 19:21:22.456936 progress 15 % (0 MB)
27 19:21:22.460887 progress 20 % (0 MB)
28 19:21:22.464076 progress 25 % (1 MB)
29 19:21:22.467238 progress 30 % (1 MB)
30 19:21:22.471009 progress 35 % (1 MB)
31 19:21:22.474314 progress 40 % (1 MB)
32 19:21:22.477660 progress 45 % (2 MB)
33 19:21:22.480821 progress 50 % (2 MB)
34 19:21:22.484609 progress 55 % (2 MB)
35 19:21:22.488061 progress 60 % (2 MB)
36 19:21:22.491501 progress 65 % (2 MB)
37 19:21:22.495503 progress 70 % (3 MB)
38 19:21:22.498744 progress 75 % (3 MB)
39 19:21:22.501780 progress 80 % (3 MB)
40 19:21:22.504810 progress 85 % (3 MB)
41 19:21:22.509010 progress 90 % (4 MB)
42 19:21:22.512302 progress 95 % (4 MB)
43 19:21:22.515609 progress 100 % (4 MB)
44 19:21:22.516412 4 MB downloaded in 0.10 s (45.41 MB/s)
45 19:21:22.517090 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:21:22.518280 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:21:22.518670 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:21:22.518958 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:21:22.519529 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 19:21:22.519888 saving as /var/lib/lava/dispatcher/tmp/948501/tftp-deploy-dih1vpji/kernel/zImage
52 19:21:22.520210 total size: 11440640 (10 MB)
53 19:21:22.520558 No compression specified
54 19:21:22.555795 progress 0 % (0 MB)
55 19:21:22.564896 progress 5 % (0 MB)
56 19:21:22.572364 progress 10 % (1 MB)
57 19:21:22.580313 progress 15 % (1 MB)
58 19:21:22.587499 progress 20 % (2 MB)
59 19:21:22.595851 progress 25 % (2 MB)
60 19:21:22.603357 progress 30 % (3 MB)
61 19:21:22.610949 progress 35 % (3 MB)
62 19:21:22.618200 progress 40 % (4 MB)
63 19:21:22.626397 progress 45 % (4 MB)
64 19:21:22.634144 progress 50 % (5 MB)
65 19:21:22.643695 progress 55 % (6 MB)
66 19:21:22.651829 progress 60 % (6 MB)
67 19:21:22.659512 progress 65 % (7 MB)
68 19:21:22.667671 progress 70 % (7 MB)
69 19:21:22.675642 progress 75 % (8 MB)
70 19:21:22.684113 progress 80 % (8 MB)
71 19:21:22.691867 progress 85 % (9 MB)
72 19:21:22.699478 progress 90 % (9 MB)
73 19:21:22.706478 progress 95 % (10 MB)
74 19:21:22.713642 progress 100 % (10 MB)
75 19:21:22.714199 10 MB downloaded in 0.19 s (56.25 MB/s)
76 19:21:22.714679 end: 1.2.1 http-download (duration 00:00:00) [common]
78 19:21:22.715499 end: 1.2 download-retry (duration 00:00:00) [common]
79 19:21:22.715780 start: 1.3 download-retry (timeout 00:10:00) [common]
80 19:21:22.716046 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 19:21:22.716517 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 19:21:22.716805 saving as /var/lib/lava/dispatcher/tmp/948501/tftp-deploy-dih1vpji/dtb/am335x-boneblack.dtb
83 19:21:22.717014 total size: 70568 (0 MB)
84 19:21:22.717224 No compression specified
85 19:21:22.749278 progress 46 % (0 MB)
86 19:21:22.750161 progress 92 % (0 MB)
87 19:21:22.750877 progress 100 % (0 MB)
88 19:21:22.751275 0 MB downloaded in 0.03 s (1.97 MB/s)
89 19:21:22.751730 end: 1.3.1 http-download (duration 00:00:00) [common]
91 19:21:22.752540 end: 1.3 download-retry (duration 00:00:00) [common]
92 19:21:22.752804 start: 1.4 download-retry (timeout 00:10:00) [common]
93 19:21:22.753066 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 19:21:22.753631 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 19:21:22.753958 saving as /var/lib/lava/dispatcher/tmp/948501/tftp-deploy-dih1vpji/nfsrootfs/full.rootfs.tar
96 19:21:22.754173 total size: 117747780 (112 MB)
97 19:21:22.754396 Using unxz to decompress xz
98 19:21:22.791603 progress 0 % (0 MB)
99 19:21:23.581890 progress 5 % (5 MB)
100 19:21:24.376332 progress 10 % (11 MB)
101 19:21:25.145069 progress 15 % (16 MB)
102 19:21:25.857638 progress 20 % (22 MB)
103 19:21:26.430446 progress 25 % (28 MB)
104 19:21:27.232668 progress 30 % (33 MB)
105 19:21:28.034245 progress 35 % (39 MB)
106 19:21:28.379026 progress 40 % (44 MB)
107 19:21:28.723533 progress 45 % (50 MB)
108 19:21:29.379692 progress 50 % (56 MB)
109 19:21:30.186167 progress 55 % (61 MB)
110 19:21:30.910220 progress 60 % (67 MB)
111 19:21:31.615772 progress 65 % (73 MB)
112 19:21:32.371881 progress 70 % (78 MB)
113 19:21:33.125215 progress 75 % (84 MB)
114 19:21:33.846062 progress 80 % (89 MB)
115 19:21:34.549629 progress 85 % (95 MB)
116 19:21:35.363413 progress 90 % (101 MB)
117 19:21:36.147774 progress 95 % (106 MB)
118 19:21:36.960706 progress 100 % (112 MB)
119 19:21:36.973001 112 MB downloaded in 14.22 s (7.90 MB/s)
120 19:21:36.973790 end: 1.4.1 http-download (duration 00:00:14) [common]
122 19:21:36.975683 end: 1.4 download-retry (duration 00:00:14) [common]
123 19:21:36.976276 start: 1.5 download-retry (timeout 00:09:45) [common]
124 19:21:36.976852 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 19:21:36.977750 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 19:21:36.978325 saving as /var/lib/lava/dispatcher/tmp/948501/tftp-deploy-dih1vpji/modules/modules.tar
127 19:21:36.978789 total size: 6610036 (6 MB)
128 19:21:36.979252 Using unxz to decompress xz
129 19:21:37.018875 progress 0 % (0 MB)
130 19:21:37.055035 progress 5 % (0 MB)
131 19:21:37.097787 progress 10 % (0 MB)
132 19:21:37.140840 progress 15 % (0 MB)
133 19:21:37.184774 progress 20 % (1 MB)
134 19:21:37.230707 progress 25 % (1 MB)
135 19:21:37.273283 progress 30 % (1 MB)
136 19:21:37.315364 progress 35 % (2 MB)
137 19:21:37.358805 progress 40 % (2 MB)
138 19:21:37.401693 progress 45 % (2 MB)
139 19:21:37.445123 progress 50 % (3 MB)
140 19:21:37.489899 progress 55 % (3 MB)
141 19:21:37.540680 progress 60 % (3 MB)
142 19:21:37.586231 progress 65 % (4 MB)
143 19:21:37.629364 progress 70 % (4 MB)
144 19:21:37.675289 progress 75 % (4 MB)
145 19:21:37.718226 progress 80 % (5 MB)
146 19:21:37.760305 progress 85 % (5 MB)
147 19:21:37.802877 progress 90 % (5 MB)
148 19:21:37.845893 progress 95 % (6 MB)
149 19:21:37.889514 progress 100 % (6 MB)
150 19:21:37.902565 6 MB downloaded in 0.92 s (6.82 MB/s)
151 19:21:37.903136 end: 1.5.1 http-download (duration 00:00:01) [common]
153 19:21:37.903950 end: 1.5 download-retry (duration 00:00:01) [common]
154 19:21:37.904220 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 19:21:37.904485 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 19:21:55.608671 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/948501/extract-nfsrootfs-do2non8y
157 19:21:55.609280 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
158 19:21:55.609568 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
159 19:21:55.610268 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx
160 19:21:55.610722 makedir: /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin
161 19:21:55.611056 makedir: /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/tests
162 19:21:55.611371 makedir: /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/results
163 19:21:55.611709 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-add-keys
164 19:21:55.612348 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-add-sources
165 19:21:55.612900 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-background-process-start
166 19:21:55.613498 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-background-process-stop
167 19:21:55.614094 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-common-functions
168 19:21:55.614622 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-echo-ipv4
169 19:21:55.615125 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-install-packages
170 19:21:55.615611 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-installed-packages
171 19:21:55.616088 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-os-build
172 19:21:55.616570 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-probe-channel
173 19:21:55.617074 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-probe-ip
174 19:21:55.617563 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-target-ip
175 19:21:55.618104 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-target-mac
176 19:21:55.618608 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-target-storage
177 19:21:55.619104 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-test-case
178 19:21:55.619602 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-test-event
179 19:21:55.620089 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-test-feedback
180 19:21:55.620578 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-test-raise
181 19:21:55.621058 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-test-reference
182 19:21:55.621576 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-test-runner
183 19:21:55.622093 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-test-set
184 19:21:55.622606 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-test-shell
185 19:21:55.623107 Updating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-add-keys (debian)
186 19:21:55.623642 Updating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-add-sources (debian)
187 19:21:55.624150 Updating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-install-packages (debian)
188 19:21:55.624660 Updating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-installed-packages (debian)
189 19:21:55.625175 Updating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/bin/lava-os-build (debian)
190 19:21:55.625635 Creating /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/environment
191 19:21:55.626054 LAVA metadata
192 19:21:55.626320 - LAVA_JOB_ID=948501
193 19:21:55.626535 - LAVA_DISPATCHER_IP=192.168.6.3
194 19:21:55.626900 start: 1.6.2.1 ssh-authorize (timeout 00:09:27) [common]
195 19:21:55.627870 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 19:21:55.628184 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:27) [common]
197 19:21:55.628390 skipped lava-vland-overlay
198 19:21:55.628629 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 19:21:55.628881 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:27) [common]
200 19:21:55.629082 skipped lava-multinode-overlay
201 19:21:55.629318 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 19:21:55.629566 start: 1.6.2.4 test-definition (timeout 00:09:27) [common]
203 19:21:55.629842 Loading test definitions
204 19:21:55.630126 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:27) [common]
205 19:21:55.630368 Using /lava-948501 at stage 0
206 19:21:55.631482 uuid=948501_1.6.2.4.1 testdef=None
207 19:21:55.631790 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 19:21:55.632051 start: 1.6.2.4.2 test-overlay (timeout 00:09:27) [common]
209 19:21:55.633642 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 19:21:55.634458 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:27) [common]
212 19:21:55.636447 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 19:21:55.637270 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:27) [common]
215 19:21:55.639146 runner path: /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/0/tests/0_timesync-off test_uuid 948501_1.6.2.4.1
216 19:21:55.639720 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 19:21:55.640533 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
219 19:21:55.640754 Using /lava-948501 at stage 0
220 19:21:55.641105 Fetching tests from https://github.com/kernelci/test-definitions.git
221 19:21:55.641393 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/0/tests/1_kselftest-dt'
222 19:21:59.321080 Running '/usr/bin/git checkout kernelci.org
223 19:21:59.611649 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 19:21:59.613090 uuid=948501_1.6.2.4.5 testdef=None
225 19:21:59.613439 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 19:21:59.614248 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
228 19:21:59.617105 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 19:21:59.617983 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
231 19:21:59.621764 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 19:21:59.622675 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
234 19:21:59.626364 runner path: /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/0/tests/1_kselftest-dt test_uuid 948501_1.6.2.4.5
235 19:21:59.626685 BOARD='beaglebone-black'
236 19:21:59.626912 BRANCH='mainline'
237 19:21:59.627120 SKIPFILE='/dev/null'
238 19:21:59.627323 SKIP_INSTALL='True'
239 19:21:59.627525 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 19:21:59.627733 TST_CASENAME=''
241 19:21:59.627937 TST_CMDFILES='dt'
242 19:21:59.628534 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 19:21:59.629349 Creating lava-test-runner.conf files
245 19:21:59.629566 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/948501/lava-overlay-avcx0yfx/lava-948501/0 for stage 0
246 19:21:59.629967 - 0_timesync-off
247 19:21:59.630232 - 1_kselftest-dt
248 19:21:59.630596 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 19:21:59.630898 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
250 19:22:23.986473 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 19:22:23.986920 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
252 19:22:23.987216 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 19:22:23.987528 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 19:22:23.987818 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
255 19:22:24.337343 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 19:22:24.337845 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
257 19:22:24.338119 extracting modules file /var/lib/lava/dispatcher/tmp/948501/tftp-deploy-dih1vpji/modules/modules.tar to /var/lib/lava/dispatcher/tmp/948501/extract-nfsrootfs-do2non8y
258 19:22:25.227481 extracting modules file /var/lib/lava/dispatcher/tmp/948501/tftp-deploy-dih1vpji/modules/modules.tar to /var/lib/lava/dispatcher/tmp/948501/extract-overlay-ramdisk-creoh4lu/ramdisk
259 19:22:26.129068 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 19:22:26.129521 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
261 19:22:26.129834 [common] Applying overlay to NFS
262 19:22:26.130078 [common] Applying overlay /var/lib/lava/dispatcher/tmp/948501/compress-overlay-lbavkdaq/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/948501/extract-nfsrootfs-do2non8y
263 19:22:28.851093 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 19:22:28.851576 start: 1.6.6 prepare-kernel (timeout 00:08:54) [common]
265 19:22:28.851881 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:54) [common]
266 19:22:28.852206 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 19:22:28.852489 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 19:22:28.852769 start: 1.6.7 configure-preseed-file (timeout 00:08:54) [common]
269 19:22:28.853039 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 19:22:28.853315 start: 1.6.8 compress-ramdisk (timeout 00:08:54) [common]
271 19:22:28.853556 Building ramdisk /var/lib/lava/dispatcher/tmp/948501/extract-overlay-ramdisk-creoh4lu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/948501/extract-overlay-ramdisk-creoh4lu/ramdisk
272 19:22:29.844920 >> 74900 blocks
273 19:22:34.383577 Adding RAMdisk u-boot header.
274 19:22:34.384047 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/948501/extract-overlay-ramdisk-creoh4lu/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/948501/extract-overlay-ramdisk-creoh4lu/ramdisk.cpio.gz.uboot
275 19:22:34.555168 output: Image Name:
276 19:22:34.555612 output: Created: Wed Nov 6 19:22:34 2024
277 19:22:34.555824 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 19:22:34.556035 output: Data Size: 14791033 Bytes = 14444.37 KiB = 14.11 MiB
279 19:22:34.556259 output: Load Address: 00000000
280 19:22:34.556526 output: Entry Point: 00000000
281 19:22:34.556757 output:
282 19:22:34.557765 rename /var/lib/lava/dispatcher/tmp/948501/extract-overlay-ramdisk-creoh4lu/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/948501/tftp-deploy-dih1vpji/ramdisk/ramdisk.cpio.gz.uboot
283 19:22:34.558277 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 19:22:34.558779 end: 1.6 prepare-tftp-overlay (duration 00:00:57) [common]
285 19:22:34.559158 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:48) [common]
286 19:22:34.559555 No LXC device requested
287 19:22:34.559882 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 19:22:34.560201 start: 1.8 deploy-device-env (timeout 00:08:48) [common]
289 19:22:34.560508 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 19:22:34.560849 Checking files for TFTP limit of 4294967296 bytes.
291 19:22:34.562490 end: 1 tftp-deploy (duration 00:01:12) [common]
292 19:22:34.562888 start: 2 uboot-action (timeout 00:05:00) [common]
293 19:22:34.563235 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 19:22:34.563569 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 19:22:34.563906 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 19:22:34.564380 substitutions:
297 19:22:34.564668 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 19:22:34.564905 - {DTB_ADDR}: 0x88000000
299 19:22:34.565134 - {DTB}: 948501/tftp-deploy-dih1vpji/dtb/am335x-boneblack.dtb
300 19:22:34.565379 - {INITRD}: 948501/tftp-deploy-dih1vpji/ramdisk/ramdisk.cpio.gz.uboot
301 19:22:34.565630 - {KERNEL_ADDR}: 0x82000000
302 19:22:34.565891 - {KERNEL}: 948501/tftp-deploy-dih1vpji/kernel/zImage
303 19:22:34.566116 - {LAVA_MAC}: None
304 19:22:34.566380 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/948501/extract-nfsrootfs-do2non8y
305 19:22:34.566630 - {NFS_SERVER_IP}: 192.168.6.3
306 19:22:34.566857 - {PRESEED_CONFIG}: None
307 19:22:34.567112 - {PRESEED_LOCAL}: None
308 19:22:34.567337 - {RAMDISK_ADDR}: 0x83000000
309 19:22:34.567558 - {RAMDISK}: 948501/tftp-deploy-dih1vpji/ramdisk/ramdisk.cpio.gz.uboot
310 19:22:34.567847 - {ROOT_PART}: None
311 19:22:34.568325 - {ROOT}: None
312 19:22:34.568779 - {SERVER_IP}: 192.168.6.3
313 19:22:34.569096 - {TEE_ADDR}: 0x83000000
314 19:22:34.569304 - {TEE}: None
315 19:22:34.569514 Parsed boot commands:
316 19:22:34.569714 - setenv autoload no
317 19:22:34.569966 - setenv initrd_high 0xffffffff
318 19:22:34.570443 - setenv fdt_high 0xffffffff
319 19:22:34.570894 - dhcp
320 19:22:34.571227 - setenv serverip 192.168.6.3
321 19:22:34.571446 - tftp 0x82000000 948501/tftp-deploy-dih1vpji/kernel/zImage
322 19:22:34.571687 - tftp 0x83000000 948501/tftp-deploy-dih1vpji/ramdisk/ramdisk.cpio.gz.uboot
323 19:22:34.571902 - setenv initrd_size ${filesize}
324 19:22:34.572187 - tftp 0x88000000 948501/tftp-deploy-dih1vpji/dtb/am335x-boneblack.dtb
325 19:22:34.572635 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/948501/extract-nfsrootfs-do2non8y,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 19:22:34.573064 - bootz 0x82000000 0x83000000 0x88000000
327 19:22:34.573493 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 19:22:34.574400 start: 2.3 connect-device (timeout 00:05:00) [common]
330 19:22:34.574675 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 19:22:34.587116 Setting prompt string to ['lava-test: # ']
332 19:22:34.588160 end: 2.3 connect-device (duration 00:00:00) [common]
333 19:22:34.588578 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 19:22:34.588921 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 19:22:34.589244 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 19:22:34.590053 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 19:22:34.623934 >> OK - accepted request
338 19:22:34.625205 Returned 0 in 0 seconds
339 19:22:34.726101 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 19:22:34.727965 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 19:22:34.729011 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 19:22:34.729674 Setting prompt string to ['Hit any key to stop autoboot']
344 19:22:34.730077 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 19:22:34.731083 Trying 192.168.56.22...
346 19:22:34.731412 Connected to conserv3.
347 19:22:34.731675 Escape character is '^]'.
348 19:22:34.731915
349 19:22:34.732191 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 19:22:34.732410
351 19:22:43.489573
352 19:22:43.496464 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 19:22:43.496974 Trying to boot from MMC1
354 19:22:47.541317
355 19:22:47.548214 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
356 19:22:47.548554 Trying to boot from MMC1
357 19:22:50.223672
358 19:22:50.230557 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
359 19:22:50.230884 Trying to boot from MMC1
360 19:22:50.814006
361 19:22:50.814568
362 19:22:50.819367 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 19:22:50.819775
364 19:22:50.820041 CPU : AM335X-GP rev 2.0
365 19:22:50.824519 Model: TI AM335x BeagleBone Black
366 19:22:50.824805 DRAM: 512 MiB
367 19:22:50.904413 Core: 160 devices, 18 uclasses, devicetree: separate
368 19:22:50.918282 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
369 19:22:51.318963 NAND: 0 MiB
370 19:22:51.329421 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
371 19:22:51.443576 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
372 19:22:51.465597 <ethaddr> not set. Validating first E-fuse MAC
373 19:22:51.496027 Net: eth2: ethernet@4a100000, eth3: usb_ether
375 19:22:51.554101 Hit any key to stop autoboot: 2
376 19:22:51.555084 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
377 19:22:51.555785 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
378 19:22:51.556328 Setting prompt string to ['=>']
379 19:22:51.556870 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
380 19:22:51.564639 0
381 19:22:51.565642 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
382 19:22:51.566252 Sending with 10 millisecond of delay
384 19:22:52.701234 => setenv autoload no
385 19:22:52.712172 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
386 19:22:52.717584 setenv autoload no
387 19:22:52.718389 Sending with 10 millisecond of delay
389 19:22:54.515462 => setenv initrd_high 0xffffffff
390 19:22:54.526377 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
391 19:22:54.526922 setenv initrd_high 0xffffffff
392 19:22:54.527429 Sending with 10 millisecond of delay
394 19:22:56.144006 => setenv fdt_high 0xffffffff
395 19:22:56.154538 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
396 19:22:56.155046 setenv fdt_high 0xffffffff
397 19:22:56.155520 Sending with 10 millisecond of delay
399 19:22:56.446883 => dhcp
400 19:22:56.457452 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
401 19:22:56.458070 dhcp
402 19:22:56.460083 link up on port 0, speed 100, full duplex
403 19:22:56.460362 BOOTP broadcast 1
404 19:22:56.712141 BOOTP broadcast 2
405 19:22:57.214201 BOOTP broadcast 3
406 19:22:58.216082 BOOTP broadcast 4
407 19:23:00.221941 BOOTP broadcast 5
408 19:23:00.413989 DHCP client bound to address 192.168.6.8 (3952 ms)
409 19:23:00.414615 Sending with 10 millisecond of delay
411 19:23:02.092783 => setenv serverip 192.168.6.3
412 19:23:02.103550 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
413 19:23:02.104418 setenv serverip 192.168.6.3
414 19:23:02.105287 Sending with 10 millisecond of delay
416 19:23:05.591850 => tftp 0x82000000 948501/tftp-deploy-dih1vpji/kernel/zImage
417 19:23:05.602487 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:29)
418 19:23:05.603172 tftp 0x82000000 948501/tftp-deploy-dih1vpji/kernel/zImage
419 19:23:05.603432 link up on port 0, speed 100, full duplex
420 19:23:05.607443 Using ethernet@4a100000 device
421 19:23:05.613883 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
422 19:23:05.614253 Filename '948501/tftp-deploy-dih1vpji/kernel/zImage'.
423 19:23:05.616333 Load address: 0x82000000
424 19:23:07.795876 Loading: *################################################## 10.9 MiB
425 19:23:07.796723 5 MiB/s
426 19:23:07.797317 done
427 19:23:07.798993 Bytes transferred = 11440640 (ae9200 hex)
428 19:23:07.799936 Sending with 10 millisecond of delay
430 19:23:12.248201 => tftp 0x83000000 948501/tftp-deploy-dih1vpji/ramdisk/ramdisk.cpio.gz.uboot
431 19:23:12.259310 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
432 19:23:12.260471 tftp 0x83000000 948501/tftp-deploy-dih1vpji/ramdisk/ramdisk.cpio.gz.uboot
433 19:23:12.261060 link up on port 0, speed 100, full duplex
434 19:23:12.264223 Using ethernet@4a100000 device
435 19:23:12.269878 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
436 19:23:12.273422 Filename '948501/tftp-deploy-dih1vpji/ramdisk/ramdisk.cpio.gz.uboot'.
437 19:23:12.277595 Load address: 0x83000000
438 19:23:14.924856 Loading: *################################################## 14.1 MiB
439 19:23:14.925235 5.3 MiB/s
440 19:23:14.925473 done
441 19:23:14.928885 Bytes transferred = 14791097 (e1b1b9 hex)
442 19:23:14.929499 Sending with 10 millisecond of delay
444 19:23:16.787637 => setenv initrd_size ${filesize}
445 19:23:16.798302 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
446 19:23:16.799452 setenv initrd_size ${filesize}
447 19:23:16.800264 Sending with 10 millisecond of delay
449 19:23:20.946128 => tftp 0x88000000 948501/tftp-deploy-dih1vpji/dtb/am335x-boneblack.dtb
450 19:23:20.956709 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
451 19:23:20.957268 tftp 0x88000000 948501/tftp-deploy-dih1vpji/dtb/am335x-boneblack.dtb
452 19:23:20.957523 link up on port 0, speed 100, full duplex
453 19:23:20.961265 Using ethernet@4a100000 device
454 19:23:20.967003 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
455 19:23:20.977850 Filename '948501/tftp-deploy-dih1vpji/dtb/am335x-boneblack.dtb'.
456 19:23:20.978188 Load address: 0x88000000
457 19:23:20.987847 Loading: *################################################## 68.9 KiB
458 19:23:20.988185 4.8 MiB/s
459 19:23:20.996366 done
460 19:23:20.996672 Bytes transferred = 70568 (113a8 hex)
461 19:23:20.997139 Sending with 10 millisecond of delay
463 19:23:34.184161 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/948501/extract-nfsrootfs-do2non8y,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
464 19:23:34.197212 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
465 19:23:34.197806 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/948501/extract-nfsrootfs-do2non8y,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
466 19:23:34.198345 Sending with 10 millisecond of delay
468 19:23:36.537234 => bootz 0x82000000 0x83000000 0x88000000
469 19:23:36.548083 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
470 19:23:36.548688 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
471 19:23:36.549782 bootz 0x82000000 0x83000000 0x88000000
472 19:23:36.550316 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
473 19:23:36.550876 ## Loading init Ramdisk from Legacy Image at 83000000 ...
474 19:23:36.555443 Image Name:
475 19:23:36.555933 Created: 2024-11-06 19:22:34 UTC
476 19:23:36.564369 Image Type: ARM Linux RAMDisk Image (uncompressed)
477 19:23:36.564902 Data Size: 14791033 Bytes = 14.1 MiB
478 19:23:36.572740 Load Address: 00000000
479 19:23:36.573259 Entry Point: 00000000
480 19:23:36.740933 Verifying Checksum ... OK
481 19:23:36.741547 ## Flattened Device Tree blob at 88000000
482 19:23:36.747445 Booting using the fdt blob at 0x88000000
483 19:23:36.747978 Working FDT set to 88000000
484 19:23:36.753059 Using Device Tree in place at 88000000, end 880143a7
485 19:23:36.756448 Working FDT set to 88000000
486 19:23:36.770033
487 19:23:36.770575 Starting kernel ...
488 19:23:36.771038
489 19:23:36.771988 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
490 19:23:36.772622 start: 2.4.4 auto-login-action (timeout 00:03:58) [common]
491 19:23:36.773126 Setting prompt string to ['Linux version [0-9]']
492 19:23:36.773623 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
493 19:23:36.774174 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
494 19:23:37.612038 [ 0.000000] Booting Linux on physical CPU 0x0
495 19:23:37.618053 start: 2.4.4.1 login-action (timeout 00:03:57) [common]
496 19:23:37.618687 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
497 19:23:37.619220 Setting prompt string to []
498 19:23:37.619771 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
499 19:23:37.620287 Using line separator: #'\n'#
500 19:23:37.620748 No login prompt set.
501 19:23:37.621227 Parsing kernel messages
502 19:23:37.621673 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
503 19:23:37.622612 [login-action] Waiting for messages, (timeout 00:03:57)
504 19:23:37.623121 Waiting using forced prompt support (timeout 00:01:58)
505 19:23:37.634792 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j365315-arm-gcc-12-multi-v7-defconfig-45cmc) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Wed Nov 6 18:49:50 UTC 2024
506 19:23:37.640604 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
507 19:23:37.646267 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
508 19:23:37.657686 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
509 19:23:37.663462 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
510 19:23:37.669232 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
511 19:23:37.669776 [ 0.000000] Memory policy: Data cache writeback
512 19:23:37.675827 [ 0.000000] efi: UEFI not found.
513 19:23:37.681377 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
514 19:23:37.687046 [ 0.000000] Zone ranges:
515 19:23:37.692804 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
516 19:23:37.698616 [ 0.000000] Normal empty
517 19:23:37.699149 [ 0.000000] HighMem empty
518 19:23:37.704285 [ 0.000000] Movable zone start for each node
519 19:23:37.704857 [ 0.000000] Early memory node ranges
520 19:23:37.715719 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
521 19:23:37.721202 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
522 19:23:37.746623 [ 0.000000] CPU: All CPU(s) started in SVC mode.
523 19:23:37.752154 [ 0.000000] AM335X ES2.0 (sgx neon)
524 19:23:37.763803 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
525 19:23:37.781566 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/948501/extract-nfsrootfs-do2non8y,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
526 19:23:37.793036 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
527 19:23:37.798801 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
528 19:23:37.804647 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
529 19:23:37.814540 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
530 19:23:37.843650 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
531 19:23:37.849648 <6>[ 0.000000] trace event string verifier disabled
532 19:23:37.850245 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
533 19:23:37.857653 <6>[ 0.000000] rcu: RCU event tracing is enabled.
534 19:23:37.863411 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
535 19:23:37.874811 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
536 19:23:37.879136 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
537 19:23:37.894755 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
538 19:23:37.911925 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
539 19:23:37.917726 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
540 19:23:38.011249 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
541 19:23:38.022668 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
542 19:23:38.029460 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
543 19:23:38.042492 <6>[ 0.019135] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
544 19:23:38.049887 <6>[ 0.033950] Console: colour dummy device 80x30
545 19:23:38.056110 Matched prompt #6: WARNING:
546 19:23:38.056711 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
547 19:23:38.061416 <3>[ 0.038850] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
548 19:23:38.067121 <3>[ 0.045922] This ensures that you still see kernel messages. Please
549 19:23:38.070410 <3>[ 0.052646] update your kernel commandline.
550 19:23:38.110999 <6>[ 0.057258] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
551 19:23:38.116771 <6>[ 0.096136] CPU: Testing write buffer coherency: ok
552 19:23:38.122766 <6>[ 0.101500] CPU0: Spectre v2: using BPIALL workaround
553 19:23:38.123326 <6>[ 0.106966] pid_max: default: 32768 minimum: 301
554 19:23:38.134180 <6>[ 0.112155] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
555 19:23:38.141090 <6>[ 0.119975] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
556 19:23:38.147086 <6>[ 0.129327] CPU0: thread -1, cpu 0, socket -1, mpidr 0
557 19:23:38.218796 <6>[ 0.199518] Setting up static identity map for 0x80300000 - 0x803000ac
558 19:23:38.225022 <6>[ 0.209107] rcu: Hierarchical SRCU implementation.
559 19:23:38.233201 <6>[ 0.214390] rcu: Max phase no-delay instances is 1000.
560 19:23:38.241690 <6>[ 0.225423] EFI services will not be available.
561 19:23:38.247509 <6>[ 0.230794] smp: Bringing up secondary CPUs ...
562 19:23:38.253328 <6>[ 0.235767] smp: Brought up 1 node, 1 CPU
563 19:23:38.259019 <6>[ 0.240240] SMP: Total of 1 processors activated (996.14 BogoMIPS).
564 19:23:38.264929 <6>[ 0.246959] CPU: All CPU(s) started in SVC mode.
565 19:23:38.284322 <6>[ 0.252163] Memory: 405996K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
566 19:23:38.284900 <6>[ 0.268431] devtmpfs: initialized
567 19:23:38.307460 <6>[ 0.285512] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
568 19:23:38.318949 <6>[ 0.294095] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
569 19:23:38.324960 <6>[ 0.304535] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
570 19:23:38.335809 <6>[ 0.316839] pinctrl core: initialized pinctrl subsystem
571 19:23:38.344909 <6>[ 0.327459] DMI not present or invalid.
572 19:23:38.353309 <6>[ 0.333306] NET: Registered PF_NETLINK/PF_ROUTE protocol family
573 19:23:38.362801 <6>[ 0.342307] DMA: preallocated 256 KiB pool for atomic coherent allocations
574 19:23:38.377877 <6>[ 0.353751] thermal_sys: Registered thermal governor 'step_wise'
575 19:23:38.378440 <6>[ 0.353919] cpuidle: using governor menu
576 19:23:38.405492 <6>[ 0.389546] No ATAGs?
577 19:23:38.411686 <6>[ 0.392187] hw-breakpoint: debug architecture 0x4 unsupported.
578 19:23:38.421806 <6>[ 0.404040] Serial: AMBA PL011 UART driver
579 19:23:38.450814 <6>[ 0.434855] iommu: Default domain type: Translated
580 19:23:38.459921 <6>[ 0.440200] iommu: DMA domain TLB invalidation policy: strict mode
581 19:23:38.487308 <5>[ 0.470694] SCSI subsystem initialized
582 19:23:38.493139 <6>[ 0.475579] usbcore: registered new interface driver usbfs
583 19:23:38.498888 <6>[ 0.481615] usbcore: registered new interface driver hub
584 19:23:38.505756 <6>[ 0.487395] usbcore: registered new device driver usb
585 19:23:38.511410 <6>[ 0.493887] pps_core: LinuxPPS API ver. 1 registered
586 19:23:38.522890 <6>[ 0.499274] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
587 19:23:38.530147 <6>[ 0.509018] PTP clock support registered
588 19:23:38.530713 <6>[ 0.513480] EDAC MC: Ver: 3.0.0
589 19:23:38.580911 <6>[ 0.562443] scmi_core: SCMI protocol bus registered
590 19:23:38.605482 <6>[ 0.588823] vgaarb: loaded
591 19:23:38.611580 <6>[ 0.592658] clocksource: Switched to clocksource dmtimer
592 19:23:38.635879 <6>[ 0.619620] NET: Registered PF_INET protocol family
593 19:23:38.648399 <6>[ 0.625320] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
594 19:23:38.654261 <6>[ 0.634162] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
595 19:23:38.665732 <6>[ 0.643090] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
596 19:23:38.671501 <6>[ 0.651332] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
597 19:23:38.682988 <6>[ 0.659626] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
598 19:23:38.688899 <6>[ 0.667346] TCP: Hash tables configured (established 4096 bind 4096)
599 19:23:38.694739 <6>[ 0.674267] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
600 19:23:38.700627 <6>[ 0.681278] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
601 19:23:38.708122 <6>[ 0.688885] NET: Registered PF_UNIX/PF_LOCAL protocol family
602 19:23:38.794060 <6>[ 0.772472] RPC: Registered named UNIX socket transport module.
603 19:23:38.794607 <6>[ 0.778908] RPC: Registered udp transport module.
604 19:23:38.799839 <6>[ 0.784033] RPC: Registered tcp transport module.
605 19:23:38.808516 <6>[ 0.789137] RPC: Registered tcp-with-tls transport module.
606 19:23:38.814080 <6>[ 0.795058] RPC: Registered tcp NFSv4.1 backchannel transport module.
607 19:23:38.821467 <6>[ 0.801961] PCI: CLS 0 bytes, default 64
608 19:23:38.822888 <5>[ 0.807721] Initialise system trusted keyrings
609 19:23:38.846668 <6>[ 0.827820] Trying to unpack rootfs image as initramfs...
610 19:23:38.925128 <6>[ 0.903067] workingset: timestamp_bits=30 max_order=17 bucket_order=0
611 19:23:38.930021 <6>[ 0.910576] squashfs: version 4.0 (2009/01/31) Phillip Lougher
612 19:23:38.969248 <5>[ 0.953418] NFS: Registering the id_resolver key type
613 19:23:38.975060 <5>[ 0.959008] Key type id_resolver registered
614 19:23:38.981994 <5>[ 0.963696] Key type id_legacy registered
615 19:23:38.989355 <6>[ 0.968136] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
616 19:23:38.996342 <6>[ 0.975345] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
617 19:23:39.069012 <5>[ 1.053203] Key type asymmetric registered
618 19:23:39.074964 <5>[ 1.057727] Asymmetric key parser 'x509' registered
619 19:23:39.086417 <6>[ 1.063207] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
620 19:23:39.086961 <6>[ 1.071091] io scheduler mq-deadline registered
621 19:23:39.092258 <6>[ 1.076073] io scheduler kyber registered
622 19:23:39.097919 <6>[ 1.080525] io scheduler bfq registered
623 19:23:39.213085 <6>[ 1.193477] ledtrig-cpu: registered to indicate activity on CPUs
624 19:23:39.490151 <6>[ 1.470444] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
625 19:23:39.533365 <6>[ 1.517449] msm_serial: driver initialized
626 19:23:39.539468 <6>[ 1.522223] SuperH (H)SCI(F) driver initialized
627 19:23:39.545399 <6>[ 1.527549] STMicroelectronics ASC driver initialized
628 19:23:39.550612 <6>[ 1.533220] STM32 USART driver initialized
629 19:23:39.661303 <6>[ 1.644709] brd: module loaded
630 19:23:39.680851 <6>[ 1.664204] loop: module loaded
631 19:23:39.716761 <6>[ 1.700015] CAN device driver interface
632 19:23:39.723043 <6>[ 1.705171] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
633 19:23:39.728993 <6>[ 1.712067] e1000e: Intel(R) PRO/1000 Network Driver
634 19:23:39.734806 <6>[ 1.717525] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
635 19:23:39.740541 <6>[ 1.723962] igb: Intel(R) Gigabit Ethernet Network Driver
636 19:23:39.747875 <6>[ 1.729784] igb: Copyright (c) 2007-2014 Intel Corporation.
637 19:23:39.760485 <6>[ 1.738990] pegasus: Pegasus/Pegasus II USB Ethernet driver
638 19:23:39.766403 <6>[ 1.745135] usbcore: registered new interface driver pegasus
639 19:23:39.772211 <6>[ 1.751259] usbcore: registered new interface driver asix
640 19:23:39.778004 <6>[ 1.757144] usbcore: registered new interface driver ax88179_178a
641 19:23:39.783780 <6>[ 1.763734] usbcore: registered new interface driver cdc_ether
642 19:23:39.789542 <6>[ 1.770033] usbcore: registered new interface driver smsc75xx
643 19:23:39.795288 <6>[ 1.776274] usbcore: registered new interface driver smsc95xx
644 19:23:39.801093 <6>[ 1.782493] usbcore: registered new interface driver net1080
645 19:23:39.806907 <6>[ 1.788637] usbcore: registered new interface driver cdc_subset
646 19:23:39.812632 <6>[ 1.795045] usbcore: registered new interface driver zaurus
647 19:23:39.820273 <6>[ 1.801085] usbcore: registered new interface driver cdc_ncm
648 19:23:39.829015 <6>[ 1.810460] usbcore: registered new interface driver usb-storage
649 19:23:39.838340 <6>[ 1.821486] i2c_dev: i2c /dev entries driver
650 19:23:39.863865 <5>[ 1.839982] cpuidle: enable-method property 'ti,am3352' found operations
651 19:23:39.869806 <6>[ 1.849550] sdhci: Secure Digital Host Controller Interface driver
652 19:23:39.877789 <6>[ 1.856314] sdhci: Copyright(c) Pierre Ossman
653 19:23:39.884986 <6>[ 1.862935] Synopsys Designware Multimedia Card Interface Driver
654 19:23:39.890110 <6>[ 1.870875] sdhci-pltfm: SDHCI platform and OF driver helper
655 19:23:39.904267 <6>[ 1.880871] usbcore: registered new interface driver usbhid
656 19:23:39.904828 <6>[ 1.886993] usbhid: USB HID core driver
657 19:23:39.917292 <6>[ 1.898765] NET: Registered PF_INET6 protocol family
658 19:23:40.370093 <6>[ 2.354196] Segment Routing with IPv6
659 19:23:40.376258 <6>[ 2.358343] In-situ OAM (IOAM) with IPv6
660 19:23:40.382718 <6>[ 2.362871] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
661 19:23:40.390151 <6>[ 2.370111] NET: Registered PF_PACKET protocol family
662 19:23:40.395996 <6>[ 2.375693] can: controller area network core
663 19:23:40.396566 <6>[ 2.380517] NET: Registered PF_CAN protocol family
664 19:23:40.401668 <6>[ 2.385748] can: raw protocol
665 19:23:40.407458 <6>[ 2.389074] can: broadcast manager protocol
666 19:23:40.414352 <6>[ 2.393675] can: netlink gateway - max_hops=1
667 19:23:40.414906 <5>[ 2.399164] Key type dns_resolver registered
668 19:23:40.420108 <6>[ 2.404235] ThumbEE CPU extension supported.
669 19:23:40.426369 <5>[ 2.408921] Registering SWP/SWPB emulation handler
670 19:23:40.434549 <3>[ 2.414617] omap_voltage_late_init: Voltage driver support not added
671 19:23:40.630284 <5>[ 2.613037] Loading compiled-in X.509 certificates
672 19:23:40.750530 <6>[ 2.721731] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
673 19:23:40.756945 <6>[ 2.738443] pinctrl-single 44e10800.pinmux: 142 pins, size 568
674 19:23:40.784100 <3>[ 2.762031] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
675 19:23:40.997774 <3>[ 2.976947] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
676 19:23:41.180931 <6>[ 3.163268] OMAP GPIO hardware version 0.1
677 19:23:41.201499 <6>[ 3.181837] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
678 19:23:41.305385 <4>[ 3.285447] at24 2-0054: supply vcc not found, using dummy regulator
679 19:23:41.344263 <4>[ 3.324345] at24 2-0055: supply vcc not found, using dummy regulator
680 19:23:41.378793 <4>[ 3.358866] at24 2-0056: supply vcc not found, using dummy regulator
681 19:23:41.420289 <4>[ 3.400431] at24 2-0057: supply vcc not found, using dummy regulator
682 19:23:41.456885 <6>[ 3.437760] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
683 19:23:41.531864 <3>[ 3.508617] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
684 19:23:41.556240 <6>[ 3.529405] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
685 19:23:41.578176 <4>[ 3.555426] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
686 19:23:41.585922 <4>[ 3.564649] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
687 19:23:41.733459 <6>[ 3.713663] omap_rng 48310000.rng: Random Number Generator ver. 20
688 19:23:41.757007 <5>[ 3.739957] random: crng init done
689 19:23:41.804844 <6>[ 3.783452] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
690 19:23:41.871279 <6>[ 3.853509] Freeing initrd memory: 14448K
691 19:23:41.927302 <6>[ 3.905084] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
692 19:23:41.933106 <6>[ 3.915413] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
693 19:23:41.944846 <6>[ 3.922751] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
694 19:23:41.950621 <6>[ 3.930207] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
695 19:23:41.962145 <6>[ 3.938333] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
696 19:23:41.969521 <6>[ 3.949973] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
697 19:23:41.982587 <5>[ 3.958998] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
698 19:23:42.010191 <3>[ 3.988643] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
699 19:23:42.015893 <6>[ 3.997230] edma 49000000.dma: TI EDMA DMA engine driver
700 19:23:42.086849 <3>[ 4.064488] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
701 19:23:42.101598 <6>[ 4.078922] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
702 19:23:42.114551 <3>[ 4.095975] l3-aon-clkctrl:0000:0: failed to disable
703 19:23:42.162686 <6>[ 4.140992] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
704 19:23:42.168481 <6>[ 4.150507] printk: legacy console [ttyS0] enabled
705 19:23:42.171210 <6>[ 4.150507] printk: legacy console [ttyS0] enabled
706 19:23:42.176789 <6>[ 4.160841] printk: legacy bootconsole [omap8250] disabled
707 19:23:42.185646 <6>[ 4.160841] printk: legacy bootconsole [omap8250] disabled
708 19:23:42.226098 <4>[ 4.203392] tps65217-pmic: Failed to locate of_node [id: -1]
709 19:23:42.229726 <4>[ 4.210779] tps65217-bl: Failed to locate of_node [id: -1]
710 19:23:42.246084 <6>[ 4.230363] tps65217 0-0024: TPS65217 ID 0xe version 1.2
711 19:23:42.264427 <6>[ 4.237310] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
712 19:23:42.276112 <6>[ 4.250990] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
713 19:23:42.281885 <6>[ 4.262888] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
714 19:23:42.304324 <6>[ 4.283121] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
715 19:23:42.310316 <6>[ 4.292177] sdhci-omap 48060000.mmc: Got CD GPIO
716 19:23:42.318342 <4>[ 4.297398] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
717 19:23:42.332864 <4>[ 4.310800] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
718 19:23:42.339288 <4>[ 4.319560] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
719 19:23:42.349006 <4>[ 4.328140] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
720 19:23:42.447618 <6>[ 4.427427] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
721 19:23:42.494996 <6>[ 4.473473] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
722 19:23:42.501586 <6>[ 4.481938] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
723 19:23:42.510702 <6>[ 4.490909] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
724 19:23:42.584726 <6>[ 4.559882] mmc1: new high speed MMC card at address 0001
725 19:23:42.585294 <6>[ 4.567000] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
726 19:23:42.598628 <6>[ 4.576382] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
727 19:23:42.606558 <6>[ 4.588368] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
728 19:23:42.614929 <6>[ 4.596683] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
729 19:23:42.634822 <6>[ 4.611388] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
730 19:23:42.641691 <6>[ 4.620190] mmc0: new high speed SDHC card at address aaaa
731 19:23:42.644836 <6>[ 4.627182] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
732 19:23:42.675266 <6>[ 4.657374] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
733 19:23:44.775252 <6>[ 6.753720] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
734 19:23:44.878588 <5>[ 6.782680] Sending DHCP requests ., OK
735 19:23:44.889883 <6>[ 6.867122] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.8
736 19:23:44.890414 <6>[ 6.875214] IP-Config: Complete:
737 19:23:44.901110 <6>[ 6.878752] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.8, mask=255.255.255.0, gw=192.168.6.1
738 19:23:44.906848 <6>[ 6.889186] host=192.168.6.8, domain=, nis-domain=(none)
739 19:23:44.912515 <6>[ 6.895312] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
740 19:23:44.919158 <6>[ 6.895346] nameserver0=10.255.253.1
741 19:23:44.925172 <6>[ 6.907901] clk: Disabling unused clocks
742 19:23:44.930698 <6>[ 6.912507] PM: genpd: Disabling unused power domains
743 19:23:44.949688 <6>[ 6.930594] Freeing unused kernel image (initmem) memory: 2048K
744 19:23:44.956907 <6>[ 6.940088] Run /init as init process
745 19:23:44.983079 Loading, please wait...
746 19:23:45.058630 Starting systemd-udevd version 252.22-1~deb12u1
747 19:23:48.099146 <4>[ 10.076170] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
748 19:23:48.306264 <4>[ 10.283135] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
749 19:23:48.498576 <6>[ 10.483200] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
750 19:23:48.509346 <6>[ 10.488873] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
751 19:23:48.731453 <6>[ 10.714277] hub 1-0:1.0: USB hub found
752 19:23:48.753253 <6>[ 10.735814] tda998x 0-0070: found TDA19988
753 19:23:48.800107 <6>[ 10.782938] hub 1-0:1.0: 1 port detected
754 19:23:51.863928 Begin: Loading essential drivers ... done.
755 19:23:51.869921 Begin: Running /scripts/init-premount ... done.
756 19:23:51.875153 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
757 19:23:51.883360 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
758 19:23:51.888912 Device /sys/class/net/eth0 found
759 19:23:51.889284 done.
760 19:23:51.963319 Begin: Waiting up to 180 secs for any network device to become available ... done.
761 19:23:52.031456 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
762 19:23:52.142042 IP-Config: eth0 guessed broadcast address 192.168.6.255
763 19:23:52.147530 IP-Config: eth0 complete (dhcp from 192.168.6.1):
764 19:23:52.153045 address: 192.168.6.8 broadcast: 192.168.6.255 netmask: 255.255.255.0
765 19:23:52.164552 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
766 19:23:52.165121 rootserver: 192.168.6.1 rootpath:
767 19:23:52.167862 filename :
768 19:23:52.241703 done.
769 19:23:52.268522 Begin: Running /scripts/nfs-bottom ... done.
770 19:23:52.340037 Begin: Running /scripts/init-bottom ... done.
771 19:23:53.906123 <30>[ 15.886315] systemd[1]: System time before build time, advancing clock.
772 19:23:54.123502 <30>[ 16.077613] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
773 19:23:54.133291 <30>[ 16.115400] systemd[1]: Detected architecture arm.
774 19:23:54.145673
775 19:23:54.146193 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
776 19:23:54.146623
777 19:23:54.171559 <30>[ 16.152375] systemd[1]: Hostname set to <debian-bookworm-armhf>.
778 19:23:56.364717 <30>[ 18.344720] systemd[1]: Queued start job for default target graphical.target.
779 19:23:56.381480 <30>[ 18.359313] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
780 19:23:56.388212 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
781 19:23:56.418366 <30>[ 18.395452] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
782 19:23:56.425778 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
783 19:23:56.449730 <30>[ 18.428859] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
784 19:23:56.463758 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
785 19:23:56.485797 <30>[ 18.464484] systemd[1]: Created slice user.slice - User and Session Slice.
786 19:23:56.492463 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
787 19:23:56.516817 <30>[ 18.493801] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
788 19:23:56.528257 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
789 19:23:56.557260 <30>[ 18.534796] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
790 19:23:56.568282 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
791 19:23:56.606167 <30>[ 18.573585] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
792 19:23:56.612516 <30>[ 18.594022] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
793 19:23:56.621035 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
794 19:23:56.644512 <30>[ 18.623113] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
795 19:23:56.651759 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
796 19:23:56.675280 <30>[ 18.653594] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
797 19:23:56.683730 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
798 19:23:56.705281 <30>[ 18.683773] systemd[1]: Reached target paths.target - Path Units.
799 19:23:56.710343 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
800 19:23:56.734819 <30>[ 18.713336] systemd[1]: Reached target remote-fs.target - Remote File Systems.
801 19:23:56.742320 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
802 19:23:56.764606 <30>[ 18.743184] systemd[1]: Reached target slices.target - Slice Units.
803 19:23:56.769293 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
804 19:23:56.794889 <30>[ 18.773449] systemd[1]: Reached target swap.target - Swaps.
805 19:23:56.798954 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
806 19:23:56.825170 <30>[ 18.803551] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
807 19:23:56.833920 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
808 19:23:56.856175 <30>[ 18.834369] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
809 19:23:56.864442 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
810 19:23:56.944377 <30>[ 18.917878] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
811 19:23:56.957277 <30>[ 18.935564] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
812 19:23:56.965209 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
813 19:23:56.987919 <30>[ 18.965458] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
814 19:23:56.995337 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
815 19:23:57.017257 <30>[ 18.995700] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
816 19:23:57.025456 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
817 19:23:57.050434 <30>[ 19.027648] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
818 19:23:57.056072 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
819 19:23:57.087318 <30>[ 19.064385] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
820 19:23:57.094839 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
821 19:23:57.122072 <30>[ 19.094444] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
822 19:23:57.140680 <30>[ 19.113005] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
823 19:23:57.188841 <30>[ 19.168055] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
824 19:23:57.216573 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
825 19:23:57.278142 <30>[ 19.257220] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
826 19:23:57.295214 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
827 19:23:57.355871 <30>[ 19.333947] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
828 19:23:57.382976 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
829 19:23:57.435648 <30>[ 19.414382] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
830 19:23:57.453503 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
831 19:23:57.476919 <30>[ 19.456808] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
832 19:23:57.500445 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
833 19:23:57.556484 <30>[ 19.536126] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
834 19:23:57.571446 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
835 19:23:57.604571 <30>[ 19.582991] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
836 19:23:57.626610 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
837 19:23:57.686512 <30>[ 19.665948] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
838 19:23:57.715054 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
839 19:23:57.763665 <30>[ 19.744072] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
840 19:23:57.786036 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
841 19:23:57.814226 <28>[ 19.786848] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
842 19:23:57.822624 <28>[ 19.801300] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
843 19:23:57.875086 <30>[ 19.853702] systemd[1]: Starting systemd-journald.service - Journal Service...
844 19:23:57.881427 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
845 19:23:57.954044 <30>[ 19.934116] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
846 19:23:57.972832 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
847 19:23:58.026235 <30>[ 20.005631] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
848 19:23:58.074317 Starting [0;1;39msystemd-network-g… units from Kernel command line...
849 19:23:58.147554 <30>[ 20.125379] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
850 19:23:58.194937 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
851 19:23:58.266341 <30>[ 20.244947] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
852 19:23:58.323801 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
853 19:23:58.384725 <30>[ 20.364247] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
854 19:23:58.433894 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
855 19:23:58.456811 <30>[ 20.436143] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
856 19:23:58.491058 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
857 19:23:58.508740 <30>[ 20.486987] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
858 19:23:58.538556 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
859 19:23:58.668495 <30>[ 20.648567] systemd[1]: modprobe@configfs.service: Deactivated successfully.
860 19:23:58.705523 <30>[ 20.684435] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
861 19:23:58.734526 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
862 19:23:58.757928 <30>[ 20.738044] systemd[1]: Started systemd-journald.service - Journal Service.
863 19:23:58.788273 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
864 19:23:58.834562 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
865 19:23:58.860064 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
866 19:23:58.896007 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
867 19:23:58.920330 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
868 19:23:58.955782 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
869 19:23:58.984862 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
870 19:23:59.008294 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
871 19:23:59.037397 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
872 19:23:59.068159 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
873 19:23:59.125401 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
874 19:23:59.194603 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
875 19:23:59.250051 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
876 19:23:59.328700 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
877 19:23:59.404473 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
878 19:23:59.512604 <46>[ 21.491981] systemd-journald[164]: Received client request to flush runtime journal.
879 19:23:59.531827 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
880 19:23:59.744870 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
881 19:24:00.524775 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
882 19:24:00.834416 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
883 19:24:00.896938 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
884 19:24:01.197969 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
885 19:24:01.447036 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
886 19:24:01.466794 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
887 19:24:01.494864 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
888 19:24:01.569371 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
889 19:24:01.614533 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
890 19:24:02.530255 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
891 19:24:02.612186 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
892 19:24:02.702278 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
893 19:24:02.794619 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
894 19:24:02.845340 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
895 19:24:04.364625 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
896 19:24:05.519946 <5>[ 27.499442] cfg80211: Loading compiled-in X.509 certificates for regulatory database
897 19:24:05.558926 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
898 19:24:06.310649 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
899 19:24:06.573467 <5>[ 28.555178] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
900 19:24:06.656184 <5>[ 28.636127] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
901 19:24:06.673712 <4>[ 28.653233] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
902 19:24:06.679697 <6>[ 28.662218] cfg80211: failed to load regulatory.db
903 19:24:07.381198 <46>[ 29.351692] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
904 19:24:07.484376 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
905 19:24:07.566699 <46>[ 29.539335] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
906 19:24:07.947952 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
907 19:24:17.023194 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
908 19:24:17.050381 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
909 19:24:17.075692 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
910 19:24:17.096595 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
911 19:24:17.164303 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
912 19:24:17.208490 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
913 19:24:17.234516 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
914 19:24:17.324060 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
915 19:24:17.380788 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
916 19:24:17.409759 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
917 19:24:17.441154 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
918 19:24:17.479713 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
919 19:24:17.508276 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
920 19:24:17.555675 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
921 19:24:17.578151 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
922 19:24:17.626404 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
923 19:24:17.661647 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
924 19:24:17.691135 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
925 19:24:17.715216 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
926 19:24:17.737245 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
927 19:24:17.784883 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
928 19:24:17.803208 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
929 19:24:17.827277 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
930 19:24:17.905169 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
931 19:24:17.958566 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
932 19:24:18.033492 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
933 19:24:18.129937 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
934 19:24:18.207056 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
935 19:24:18.274220 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
936 19:24:18.294017 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
937 19:24:18.485124 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
938 19:24:18.545553 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
939 19:24:18.586095 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
940 19:24:18.603665 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
941 19:24:18.632474 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
942 19:24:18.845228 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
943 19:24:19.221227 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
944 19:24:19.276373 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
945 19:24:19.300272 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
946 19:24:19.365026 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
947 19:24:19.544985 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
948 19:24:19.694024
949 19:24:19.694687 Debian GNU/Linux 12worm-armhf login: root (automatic login)
950 19:24:19.697321
951 19:24:20.025359 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Wed Nov 6 18:49:50 UTC 2024 armv7l
952 19:24:20.026057
953 19:24:20.031084 The programs included with the Debian GNU/Linux system are free software;
954 19:24:20.036739 the exact distribution terms for each program are described in the
955 19:24:20.042318 individual files in /usr/share/doc/*/copyright.
956 19:24:20.042858
957 19:24:20.050257 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
958 19:24:20.050796 permitted by applicable law.
959 19:24:25.056007 Unable to match end of the kernel message
961 19:24:25.058555 Setting prompt string to ['/ #']
962 19:24:25.059308 end: 2.4.4.1 login-action (duration 00:00:47) [common]
964 19:24:25.061279 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
965 19:24:25.062199 start: 2.4.5 expect-shell-connection (timeout 00:03:10) [common]
966 19:24:25.062881 Setting prompt string to ['/ #']
967 19:24:25.063432 Forcing a shell prompt, looking for ['/ #']
969 19:24:25.114622 / #
970 19:24:25.115439 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
971 19:24:25.116012 Waiting using forced prompt support (timeout 00:02:30)
972 19:24:25.120422
973 19:24:25.130023 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
974 19:24:25.130952 start: 2.4.6 export-device-env (timeout 00:03:09) [common]
975 19:24:25.131650 Sending with 10 millisecond of delay
977 19:24:30.123000 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/948501/extract-nfsrootfs-do2non8y'
978 19:24:30.134947 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/948501/extract-nfsrootfs-do2non8y'
979 19:24:30.136368 Sending with 10 millisecond of delay
981 19:24:32.238775 / # export NFS_SERVER_IP='192.168.6.3'
982 19:24:32.249533 export NFS_SERVER_IP='192.168.6.3'
983 19:24:32.250253 end: 2.4.6 export-device-env (duration 00:00:07) [common]
984 19:24:32.250621 end: 2.4 uboot-commands (duration 00:01:58) [common]
985 19:24:32.251011 end: 2 uboot-action (duration 00:01:58) [common]
986 19:24:32.251333 start: 3 lava-test-retry (timeout 00:06:50) [common]
987 19:24:32.251720 start: 3.1 lava-test-shell (timeout 00:06:50) [common]
988 19:24:32.251999 Using namespace: common
990 19:24:32.352812 / # #
991 19:24:32.353359 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
992 19:24:32.358397 #
993 19:24:32.363986 Using /lava-948501
995 19:24:32.464934 / # export SHELL=/bin/bash
996 19:24:32.469715 export SHELL=/bin/bash
998 19:24:32.579164 / # . /lava-948501/environment
999 19:24:32.584451 . /lava-948501/environment
1001 19:24:32.697740 / # /lava-948501/bin/lava-test-runner /lava-948501/0
1002 19:24:32.698321 Test shell timeout: 10s (minimum of the action and connection timeout)
1003 19:24:32.703218 /lava-948501/bin/lava-test-runner /lava-948501/0
1004 19:24:33.097800 + export TESTRUN_ID=0_timesync-off
1005 19:24:33.105793 + TESTRUN_ID=0_timesync-off
1006 19:24:33.106169 + cd /lava-948501/0/tests/0_timesync-off
1007 19:24:33.106454 ++ cat uuid
1008 19:24:33.121359 + UUID=948501_1.6.2.4.1
1009 19:24:33.121769 + set +x
1010 19:24:33.130129 <LAVA_SIGNAL_STARTRUN 0_timesync-off 948501_1.6.2.4.1>
1011 19:24:33.130510 + systemctl stop systemd-timesyncd
1012 19:24:33.131065 Received signal: <STARTRUN> 0_timesync-off 948501_1.6.2.4.1
1013 19:24:33.131336 Starting test lava.0_timesync-off (948501_1.6.2.4.1)
1014 19:24:33.131635 Skipping test definition patterns.
1015 19:24:33.389448 + set +x
1016 19:24:33.389895 <LAVA_SIGNAL_ENDRUN 0_timesync-off 948501_1.6.2.4.1>
1017 19:24:33.390366 Received signal: <ENDRUN> 0_timesync-off 948501_1.6.2.4.1
1018 19:24:33.390657 Ending use of test pattern.
1019 19:24:33.390873 Ending test lava.0_timesync-off (948501_1.6.2.4.1), duration 0.26
1021 19:24:33.584835 + export TESTRUN_ID=1_kselftest-dt
1022 19:24:33.592365 + TESTRUN_ID=1_kselftest-dt
1023 19:24:33.593058 + cd /lava-948501/0/tests/1_kselftest-dt
1024 19:24:33.593560 ++ cat uuid
1025 19:24:33.611297 + UUID=948501_1.6.2.4.5
1026 19:24:33.611860 + set +x
1027 19:24:33.616815 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 948501_1.6.2.4.5>
1028 19:24:33.617302 + cd ./automated/linux/kselftest/
1029 19:24:33.618020 Received signal: <STARTRUN> 1_kselftest-dt 948501_1.6.2.4.5
1030 19:24:33.618495 Starting test lava.1_kselftest-dt (948501_1.6.2.4.5)
1031 19:24:33.619029 Skipping test definition patterns.
1032 19:24:33.644916 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1033 19:24:33.761883 INFO: install_deps skipped
1034 19:24:34.329456 --2024-11-06 19:24:34-- http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1035 19:24:34.364588 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1036 19:24:34.506704 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1037 19:24:34.648948 HTTP request sent, awaiting response... 200 OK
1038 19:24:34.649401 Length: 4106868 (3.9M) [application/octet-stream]
1039 19:24:34.661367 Saving to: 'kselftest_armhf.tar.gz'
1040 19:24:34.661917
1041 19:24:36.509535
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 181KB/s
kselftest_armhf.tar 5%[> ] 218.67K 386KB/s
kselftest_armhf.tar 21%[===> ] 854.73K 879KB/s
kselftest_armhf.tar 46%[========> ] 1.84M 1.43MB/s
kselftest_armhf.tar 72%[=============> ] 2.85M 1.92MB/s
kselftest_armhf.tar 84%[===============> ] 3.29M 1.95MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 2.11MB/s in 1.9s
1042 19:24:36.510025
1043 19:24:37.156207 2024-11-06 19:24:36 (2.11 MB/s) - 'kselftest_armhf.tar.gz' saved [4106868/4106868]
1044 19:24:37.156911
1045 19:24:52.268274 skiplist:
1046 19:24:52.268966 ========================================
1047 19:24:52.273704 ========================================
1048 19:24:52.377741 dt:test_unprobed_devices.sh
1049 19:24:52.414043 ============== Tests to run ===============
1050 19:24:52.421281 dt:test_unprobed_devices.sh
1051 19:24:52.425386 ===========End Tests to run ===============
1052 19:24:52.433152 shardfile-dt pass
1053 19:24:52.670032 <12>[ 74.654118] kselftest: Running tests in dt
1054 19:24:52.695688 TAP version 13
1055 19:24:52.719399 1..1
1056 19:24:52.773242 # timeout set to 45
1057 19:24:52.773909 # selftests: dt: test_unprobed_devices.sh
1058 19:24:53.606068 # TAP version 13
1059 19:25:18.438207 # 1..257
1060 19:25:18.614667 # ok 1 / # SKIP
1061 19:25:18.632776 # ok 2 /clk_mcasp0
1062 19:25:18.705981 # ok 3 /clk_mcasp0_fixed # SKIP
1063 19:25:18.773718 # ok 4 /cpus/cpu@0 # SKIP
1064 19:25:18.844854 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1065 19:25:18.873083 # ok 6 /fixedregulator0
1066 19:25:18.885734 # ok 7 /leds
1067 19:25:18.906652 # ok 8 /ocp
1068 19:25:18.935230 # ok 9 /ocp/interconnect@44c00000
1069 19:25:18.957156 # ok 10 /ocp/interconnect@44c00000/segment@0
1070 19:25:18.983709 # ok 11 /ocp/interconnect@44c00000/segment@100000
1071 19:25:19.001703 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1072 19:25:19.072843 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1073 19:25:19.093180 # ok 14 /ocp/interconnect@44c00000/segment@200000
1074 19:25:19.117223 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1075 19:25:19.222540 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1076 19:25:19.294077 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1077 19:25:19.366011 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1078 19:25:19.437801 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1079 19:25:19.509934 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1080 19:25:19.581392 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1081 19:25:19.654719 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1082 19:25:19.723911 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1083 19:25:19.795700 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1084 19:25:19.867200 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1085 19:25:19.937552 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1086 19:25:20.009782 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1087 19:25:20.083188 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1088 19:25:20.158192 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1089 19:25:20.230927 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1090 19:25:20.298388 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1091 19:25:20.369915 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1092 19:25:20.442963 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1093 19:25:20.512009 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1094 19:25:20.588382 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1095 19:25:20.658903 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1096 19:25:20.730909 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1097 19:25:20.801916 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1098 19:25:20.869134 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1099 19:25:20.940330 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1100 19:25:21.011394 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1101 19:25:21.088286 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1102 19:25:21.159243 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1103 19:25:21.231311 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1104 19:25:21.302494 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1105 19:25:21.370839 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1106 19:25:21.450006 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1107 19:25:21.515721 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1108 19:25:21.588357 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1109 19:25:21.659569 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1110 19:25:21.731124 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1111 19:25:21.807537 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1112 19:25:21.879269 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1113 19:25:21.951642 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1114 19:25:22.018041 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1115 19:25:22.089382 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1116 19:25:22.160650 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1117 19:25:22.231389 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1118 19:25:22.304210 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1119 19:25:22.379203 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1120 19:25:22.450494 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1121 19:25:22.521991 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1122 19:25:22.589760 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1123 19:25:22.662228 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1124 19:25:22.736875 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1125 19:25:22.808877 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1126 19:25:22.881479 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1127 19:25:22.952008 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1128 19:25:23.018696 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1129 19:25:23.090991 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1130 19:25:23.163568 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1131 19:25:23.235918 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1132 19:25:23.309266 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1133 19:25:23.380044 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1134 19:25:23.451369 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1135 19:25:23.527775 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1136 19:25:23.594955 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1137 19:25:23.665924 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1138 19:25:23.736480 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1139 19:25:23.807948 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1140 19:25:23.878962 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1141 19:25:23.949565 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1142 19:25:24.020207 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1143 19:25:24.093997 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1144 19:25:24.161889 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1145 19:25:24.234738 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1146 19:25:24.306830 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1147 19:25:24.378414 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1148 19:25:24.457871 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1149 19:25:24.525018 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1150 19:25:24.595402 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1151 19:25:24.669414 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1152 19:25:24.741241 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1153 19:25:24.818181 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1154 19:25:24.835886 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1155 19:25:24.859492 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1156 19:25:24.883455 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1157 19:25:24.907128 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1158 19:25:24.936025 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1159 19:25:24.970071 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1160 19:25:24.998399 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1161 19:25:25.019153 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1162 19:25:25.127242 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1163 19:25:25.146141 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1164 19:25:25.169885 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1165 19:25:25.193919 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1166 19:25:25.299838 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1167 19:25:25.378897 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1168 19:25:25.446166 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1169 19:25:25.517585 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1170 19:25:25.589370 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1171 19:25:25.661525 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1172 19:25:25.734620 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1173 19:25:25.803773 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1174 19:25:25.877523 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1175 19:25:25.949968 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1176 19:25:26.021848 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1177 19:25:26.095444 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1178 19:25:26.168935 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1179 19:25:26.242874 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1180 19:25:26.310401 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1181 19:25:26.381519 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1182 19:25:26.407480 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1183 19:25:26.478138 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1184 19:25:26.542112 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1185 19:25:26.618077 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1186 19:25:26.639139 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1187 19:25:26.705541 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1188 19:25:26.731321 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1189 19:25:26.799248 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1190 19:25:26.822798 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1191 19:25:26.846839 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1192 19:25:26.874542 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1193 19:25:26.899863 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1194 19:25:26.918453 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1195 19:25:26.942546 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1196 19:25:26.967844 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1197 19:25:27.041392 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1198 19:25:27.062849 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1199 19:25:27.085878 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1200 19:25:27.157130 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1201 19:25:27.227538 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1202 19:25:27.248445 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1203 19:25:27.349154 # not ok 144 /ocp/interconnect@47c00000
1204 19:25:27.420545 # not ok 145 /ocp/interconnect@47c00000/segment@0
1205 19:25:27.441305 # ok 146 /ocp/interconnect@48000000
1206 19:25:27.466895 # ok 147 /ocp/interconnect@48000000/segment@0
1207 19:25:27.489462 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1208 19:25:27.516882 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1209 19:25:27.538676 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1210 19:25:27.560497 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1211 19:25:27.582551 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1212 19:25:27.606693 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1213 19:25:27.634165 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1214 19:25:27.705356 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1215 19:25:27.777440 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1216 19:25:27.798524 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1217 19:25:27.823033 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1218 19:25:27.846746 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1219 19:25:27.869188 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1220 19:25:27.889390 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1221 19:25:27.913727 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1222 19:25:27.936363 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1223 19:25:27.965394 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1224 19:25:27.987801 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1225 19:25:28.009236 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1226 19:25:28.030650 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1227 19:25:28.058994 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1228 19:25:28.078527 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1229 19:25:28.106156 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1230 19:25:28.128636 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1231 19:25:28.151309 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1232 19:25:28.171276 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1233 19:25:28.196685 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1234 19:25:28.222228 # ok 175 /ocp/interconnect@48000000/segment@100000
1235 19:25:28.242713 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1236 19:25:28.266765 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1237 19:25:28.339700 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1238 19:25:28.415630 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1239 19:25:28.481512 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1240 19:25:28.556050 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1241 19:25:28.625470 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1242 19:25:28.698435 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1243 19:25:28.768012 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1244 19:25:28.841533 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1245 19:25:28.861580 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1246 19:25:28.884619 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1247 19:25:28.907700 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1248 19:25:28.932564 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1249 19:25:28.955718 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1250 19:25:28.980458 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1251 19:25:29.003138 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1252 19:25:29.029624 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1253 19:25:29.050896 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1254 19:25:29.078276 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1255 19:25:29.099029 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1256 19:25:29.121852 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1257 19:25:29.142126 # ok 198 /ocp/interconnect@48000000/segment@200000
1258 19:25:29.166470 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1259 19:25:29.244077 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1260 19:25:29.259269 # ok 201 /ocp/interconnect@48000000/segment@300000
1261 19:25:29.284445 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1262 19:25:29.313472 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1263 19:25:29.337585 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1264 19:25:29.359038 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1265 19:25:29.384541 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1266 19:25:29.408758 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1267 19:25:29.476993 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1268 19:25:29.495511 # ok 209 /ocp/interconnect@4a000000
1269 19:25:29.523283 # ok 210 /ocp/interconnect@4a000000/segment@0
1270 19:25:29.547817 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1271 19:25:29.569217 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1272 19:25:29.596934 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1273 19:25:29.618319 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1274 19:25:29.684802 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1275 19:25:29.790814 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1276 19:25:29.862130 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1277 19:25:29.967370 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1278 19:25:30.037088 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1279 19:25:30.108221 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1280 19:25:30.207069 # not ok 221 /ocp/interconnect@4b140000
1281 19:25:30.273402 # not ok 222 /ocp/interconnect@4b140000/segment@0
1282 19:25:30.347483 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1283 19:25:30.372049 # ok 224 /ocp/target-module@40300000
1284 19:25:30.390145 # ok 225 /ocp/target-module@40300000/sram@0
1285 19:25:30.468230 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1286 19:25:30.535022 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1287 19:25:30.556173 # ok 228 /ocp/target-module@47400000
1288 19:25:30.583282 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1289 19:25:30.606197 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1290 19:25:30.624404 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1291 19:25:30.651781 # ok 232 /ocp/target-module@47400000/usb@1400
1292 19:25:30.673907 # ok 233 /ocp/target-module@47400000/usb@1800
1293 19:25:30.690770 # ok 234 /ocp/target-module@47810000
1294 19:25:30.713759 # ok 235 /ocp/target-module@49000000
1295 19:25:30.741308 # ok 236 /ocp/target-module@49000000/dma@0
1296 19:25:30.763045 # ok 237 /ocp/target-module@49800000
1297 19:25:30.781843 # ok 238 /ocp/target-module@49800000/dma@0
1298 19:25:30.806104 # ok 239 /ocp/target-module@49900000
1299 19:25:30.828827 # ok 240 /ocp/target-module@49900000/dma@0
1300 19:25:30.852911 # ok 241 /ocp/target-module@49a00000
1301 19:25:30.875896 # ok 242 /ocp/target-module@49a00000/dma@0
1302 19:25:30.892964 # ok 243 /ocp/target-module@4c000000
1303 19:25:30.967161 # not ok 244 /ocp/target-module@4c000000/emif@0
1304 19:25:30.985264 # ok 245 /ocp/target-module@50000000
1305 19:25:31.007834 # ok 246 /ocp/target-module@53100000
1306 19:25:31.078891 # not ok 247 /ocp/target-module@53100000/sham@0
1307 19:25:31.104099 # ok 248 /ocp/target-module@53500000
1308 19:25:31.175555 # not ok 249 /ocp/target-module@53500000/aes@0
1309 19:25:31.192462 # ok 250 /ocp/target-module@56000000
1310 19:25:31.301253 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1311 19:25:31.369832 # ok 252 /opp-table # SKIP
1312 19:25:31.434206 # ok 253 /soc # SKIP
1313 19:25:31.459992 # ok 254 /sound
1314 19:25:31.483264 # ok 255 /target-module@4b000000
1315 19:25:31.507562 # ok 256 /target-module@4b000000/target-module@140000
1316 19:25:31.524867 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1317 19:25:31.532334 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1318 19:25:31.542109 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1319 19:25:33.837030 dt_test_unprobed_devices_sh_ skip
1320 19:25:33.842628 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1321 19:25:33.848304 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1322 19:25:33.848865 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1323 19:25:33.853861 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1324 19:25:33.859409 dt_test_unprobed_devices_sh_fixedregulator0 pass
1325 19:25:33.865076 dt_test_unprobed_devices_sh_leds pass
1326 19:25:33.865624 dt_test_unprobed_devices_sh_ocp pass
1327 19:25:33.870639 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1328 19:25:33.876220 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1329 19:25:33.881892 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1330 19:25:33.892935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1331 19:25:33.898656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1332 19:25:33.904143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1333 19:25:33.915310 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1334 19:25:33.920951 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1335 19:25:33.932175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1336 19:25:33.943553 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1337 19:25:33.954635 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1338 19:25:33.960289 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1339 19:25:33.971639 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1340 19:25:33.982791 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1341 19:25:33.993913 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1342 19:25:34.005109 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1343 19:25:34.010751 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1344 19:25:34.021900 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1345 19:25:34.033094 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1346 19:25:34.044277 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1347 19:25:34.055551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1348 19:25:34.061135 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1349 19:25:34.072306 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1350 19:25:34.083467 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1351 19:25:34.094750 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1352 19:25:34.100332 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1353 19:25:34.111433 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1354 19:25:34.122627 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1355 19:25:34.133881 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1356 19:25:34.145015 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1357 19:25:34.150652 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1358 19:25:34.161789 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1359 19:25:34.173027 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1360 19:25:34.184164 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1361 19:25:34.195366 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1362 19:25:34.206575 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1363 19:25:34.217683 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1364 19:25:34.228837 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1365 19:25:34.240019 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1366 19:25:34.251236 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1367 19:25:34.262468 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1368 19:25:34.273565 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1369 19:25:34.284870 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1370 19:25:34.296045 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1371 19:25:34.307355 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1372 19:25:34.318558 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1373 19:25:34.329749 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1374 19:25:34.340986 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1375 19:25:34.352242 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1376 19:25:34.363478 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1377 19:25:34.374845 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1378 19:25:34.386033 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1379 19:25:34.397186 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1380 19:25:34.408380 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1381 19:25:34.419671 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1382 19:25:34.430654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1383 19:25:34.436268 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1384 19:25:34.447539 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1385 19:25:34.458593 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1386 19:25:34.469883 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1387 19:25:34.481023 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1388 19:25:34.492190 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1389 19:25:34.503387 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1390 19:25:34.514571 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1391 19:25:34.525746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1392 19:25:34.536997 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1393 19:25:34.548271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1394 19:25:34.559506 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1395 19:25:34.571601 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1396 19:25:34.581897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1397 19:25:34.593109 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1398 19:25:34.604390 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1399 19:25:34.615647 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1400 19:25:34.626969 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1401 19:25:34.632523 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1402 19:25:34.643653 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1403 19:25:34.654810 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1404 19:25:34.665995 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1405 19:25:34.677258 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1406 19:25:34.682825 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1407 19:25:34.699552 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1408 19:25:34.710760 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1409 19:25:34.716420 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1410 19:25:34.733166 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1411 19:25:34.744372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1412 19:25:34.755612 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1413 19:25:34.761248 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1414 19:25:34.772347 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1415 19:25:34.783505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1416 19:25:34.789106 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1417 19:25:34.800331 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1418 19:25:34.811532 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1419 19:25:34.817155 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1420 19:25:34.828550 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1421 19:25:34.834041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1422 19:25:34.845216 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1423 19:25:34.856447 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1424 19:25:34.867670 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1425 19:25:34.878904 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1426 19:25:34.890082 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1427 19:25:34.901266 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1428 19:25:34.912442 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1429 19:25:34.923869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1430 19:25:34.934908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1431 19:25:34.946125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1432 19:25:34.957308 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1433 19:25:34.968474 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1434 19:25:34.985297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1435 19:25:34.996490 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1436 19:25:35.007683 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1437 19:25:35.018935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1438 19:25:35.030136 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1439 19:25:35.046953 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1440 19:25:35.058202 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1441 19:25:35.069441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1442 19:25:35.080785 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1443 19:25:35.086325 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1444 19:25:35.097545 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1445 19:25:35.108620 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1446 19:25:35.114130 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1447 19:25:35.125336 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1448 19:25:35.130947 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1449 19:25:35.142198 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1450 19:25:35.148950 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1451 19:25:35.159160 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1452 19:25:35.164820 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1453 19:25:35.175982 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1454 19:25:35.181539 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1455 19:25:35.192694 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1456 19:25:35.203766 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1457 19:25:35.214919 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1458 19:25:35.226268 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1459 19:25:35.237250 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1460 19:25:35.242838 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1461 19:25:35.254253 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1462 19:25:35.259767 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1463 19:25:35.265306 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1464 19:25:35.271135 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1465 19:25:35.276782 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1466 19:25:35.282128 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1467 19:25:35.293203 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1468 19:25:35.298800 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1469 19:25:35.304358 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1470 19:25:35.315701 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1471 19:25:35.321209 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1472 19:25:35.332398 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1473 19:25:35.338035 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1474 19:25:35.349171 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1475 19:25:35.354782 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1476 19:25:35.366006 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1477 19:25:35.371674 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1478 19:25:35.382768 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1479 19:25:35.388373 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1480 19:25:35.399552 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1481 19:25:35.405173 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1482 19:25:35.416328 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1483 19:25:35.421954 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1484 19:25:35.427531 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1485 19:25:35.438689 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1486 19:25:35.444286 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1487 19:25:35.455517 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1488 19:25:35.461079 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1489 19:25:35.472288 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1490 19:25:35.477919 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1491 19:25:35.489057 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1492 19:25:35.494657 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1493 19:25:35.500272 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1494 19:25:35.511418 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1495 19:25:35.516999 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1496 19:25:35.528197 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1497 19:25:35.539349 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1498 19:25:35.550626 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1499 19:25:35.561771 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1500 19:25:35.572949 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1501 19:25:35.584329 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1502 19:25:35.595333 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1503 19:25:35.606513 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1504 19:25:35.612152 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1505 19:25:35.623311 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1506 19:25:35.628969 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1507 19:25:35.640130 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1508 19:25:35.645725 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1509 19:25:35.656879 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1510 19:25:35.662562 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1511 19:25:35.673681 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1512 19:25:35.679296 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1513 19:25:35.690511 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1514 19:25:35.696072 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1515 19:25:35.707223 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1516 19:25:35.712830 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1517 19:25:35.724041 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1518 19:25:35.729658 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1519 19:25:35.735252 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1520 19:25:35.746394 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1521 19:25:35.752029 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1522 19:25:35.763146 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1523 19:25:35.768762 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1524 19:25:35.779996 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1525 19:25:35.785625 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1526 19:25:35.796754 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1527 19:25:35.802387 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1528 19:25:35.807970 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1529 19:25:35.813558 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1530 19:25:35.824726 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1531 19:25:35.835971 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1532 19:25:35.841563 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1533 19:25:35.847291 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1534 19:25:35.858262 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1535 19:25:35.869544 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1536 19:25:35.880771 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1537 19:25:35.891940 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1538 19:25:35.897495 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1539 19:25:35.903139 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1540 19:25:35.908735 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1541 19:25:35.914407 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1542 19:25:35.919948 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1543 19:25:35.925765 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1544 19:25:35.936901 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1545 19:25:35.942505 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1546 19:25:35.948116 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1547 19:25:35.953736 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1548 19:25:35.959299 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1549 19:25:35.970598 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1550 19:25:35.976216 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1551 19:25:35.981874 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1552 19:25:35.987402 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1553 19:25:35.992999 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1554 19:25:35.998590 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1555 19:25:36.004209 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1556 19:25:36.009855 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1557 19:25:36.015399 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1558 19:25:36.021114 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1559 19:25:36.026663 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1560 19:25:36.032241 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1561 19:25:36.037875 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1562 19:25:36.043451 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1563 19:25:36.049047 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1564 19:25:36.054644 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1565 19:25:36.060228 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1566 19:25:36.065883 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1567 19:25:36.071429 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1568 19:25:36.077046 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1569 19:25:36.082638 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1570 19:25:36.083166 dt_test_unprobed_devices_sh_opp-table skip
1571 19:25:36.088239 dt_test_unprobed_devices_sh_soc skip
1572 19:25:36.093924 dt_test_unprobed_devices_sh_sound pass
1573 19:25:36.099467 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1574 19:25:36.105099 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1575 19:25:36.110638 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1576 19:25:36.116233 dt_test_unprobed_devices_sh fail
1577 19:25:36.116768 + ../../utils/send-to-lava.sh ./output/result.txt
1578 19:25:36.123714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1579 19:25:36.124679 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1581 19:25:36.132789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1582 19:25:36.133579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1584 19:25:36.223722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1585 19:25:36.224513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1587 19:25:36.309918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1588 19:25:36.310709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1590 19:25:36.400985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1591 19:25:36.401788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1593 19:25:36.495714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1594 19:25:36.496513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1596 19:25:36.586314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1597 19:25:36.587317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1599 19:25:36.677286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1600 19:25:36.677849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1602 19:25:36.769640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1603 19:25:36.770434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1605 19:25:36.863270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1606 19:25:36.864028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1608 19:25:36.965796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1609 19:25:36.966580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1611 19:25:37.060388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1612 19:25:37.061145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1614 19:25:37.154077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1615 19:25:37.154856 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1617 19:25:37.246947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1618 19:25:37.247721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1620 19:25:37.336913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1621 19:25:37.337677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1623 19:25:37.430363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1624 19:25:37.430980 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1626 19:25:37.524341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1627 19:25:37.525088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1629 19:25:37.616631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1630 19:25:37.617430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1632 19:25:37.708675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1633 19:25:37.709445 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1635 19:25:37.800770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1636 19:25:37.801491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1638 19:25:37.894613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1639 19:25:37.895360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1641 19:25:37.987761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1642 19:25:37.988500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1644 19:25:38.078439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1645 19:25:38.079166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1647 19:25:38.169750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1648 19:25:38.170536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1650 19:25:38.260542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1651 19:25:38.261263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1653 19:25:38.353254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1654 19:25:38.354015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1656 19:25:38.443796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1657 19:25:38.444551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1659 19:25:38.535612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1660 19:25:38.536362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1662 19:25:38.627339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1663 19:25:38.628089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1665 19:25:38.719702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1666 19:25:38.720422 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1668 19:25:38.809678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1669 19:25:38.810466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1671 19:25:38.902256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1672 19:25:38.902990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1674 19:25:38.994596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1675 19:25:38.995388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1677 19:25:39.087979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1678 19:25:39.088772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1680 19:25:39.178503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1681 19:25:39.179281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1683 19:25:39.270987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1684 19:25:39.271748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1686 19:25:39.359669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1687 19:25:39.360166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1689 19:25:39.449192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1690 19:25:39.449703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1692 19:25:39.540478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1693 19:25:39.541101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1695 19:25:39.626224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1696 19:25:39.627072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1698 19:25:39.717949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1699 19:25:39.718768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1701 19:25:39.809182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1702 19:25:39.810016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1704 19:25:39.900919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1705 19:25:39.901778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1707 19:25:39.990542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1708 19:25:39.991393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1710 19:25:40.082174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1711 19:25:40.083036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1713 19:25:40.173687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1714 19:25:40.174590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1716 19:25:40.266811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1717 19:25:40.267860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1719 19:25:40.372054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1720 19:25:40.372968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1722 19:25:40.464433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1723 19:25:40.465273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1725 19:25:40.557063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1726 19:25:40.557923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1728 19:25:40.649298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1729 19:25:40.650100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1731 19:25:40.740472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1732 19:25:40.741328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1734 19:25:40.831208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1735 19:25:40.832036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1737 19:25:40.916943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1738 19:25:40.917771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1740 19:25:41.011949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1741 19:25:41.012819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1743 19:25:41.102992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1744 19:25:41.103833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1746 19:25:41.196016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1747 19:25:41.197019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1749 19:25:41.288689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1750 19:25:41.289540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1752 19:25:41.379997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1753 19:25:41.380843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1755 19:25:41.472215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1756 19:25:41.473108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1758 19:25:41.566139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1759 19:25:41.567090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1761 19:25:41.659258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1762 19:25:41.660199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1764 19:25:41.749325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1765 19:25:41.750347 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1767 19:25:41.840923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1768 19:25:41.841893 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1770 19:25:41.933935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1771 19:25:41.934854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1773 19:25:42.028510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1774 19:25:42.029426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1776 19:25:42.120741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1777 19:25:42.121705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1779 19:25:42.213115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1780 19:25:42.214076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1782 19:25:42.304816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1783 19:25:42.305452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1785 19:25:42.398927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1786 19:25:42.399875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1788 19:25:42.490131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1789 19:25:42.491059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1791 19:25:42.580717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1792 19:25:42.581633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1794 19:25:42.666121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1795 19:25:42.666736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1797 19:25:42.756678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1798 19:25:42.757639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1800 19:25:42.849373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1801 19:25:42.850360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1803 19:25:42.940405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1804 19:25:42.941365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1806 19:25:43.032159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1807 19:25:43.033119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1809 19:25:43.125571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1810 19:25:43.126685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1812 19:25:43.219562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1813 19:25:43.220657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1815 19:25:43.309828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1816 19:25:43.310509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1818 19:25:43.401589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1819 19:25:43.402291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1821 19:25:43.493494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1822 19:25:43.494953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1824 19:25:43.585894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1825 19:25:43.586793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1827 19:25:43.677537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1828 19:25:43.678234 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1830 19:25:43.769066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1831 19:25:43.769728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1833 19:25:43.861619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1834 19:25:43.862349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1836 19:25:43.952948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1837 19:25:43.953997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1839 19:25:44.045695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1840 19:25:44.046672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1842 19:25:44.134784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1843 19:25:44.135689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1845 19:25:44.228462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1846 19:25:44.229412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1848 19:25:44.320319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1849 19:25:44.321255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1851 19:25:44.410868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1852 19:25:44.411796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1854 19:25:44.505092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1855 19:25:44.505994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1857 19:25:44.600344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1858 19:25:44.601335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1860 19:25:44.692007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1861 19:25:44.692961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1863 19:25:44.780507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1864 19:25:44.781425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1866 19:25:44.871920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1867 19:25:44.872821 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1869 19:25:44.963542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1870 19:25:44.964468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1872 19:25:45.055541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1873 19:25:45.056496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1875 19:25:45.146926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1876 19:25:45.147882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1878 19:25:45.239748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1879 19:25:45.240691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1881 19:25:45.329577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1882 19:25:45.330548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1884 19:25:45.421429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1885 19:25:45.422583 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1887 19:25:45.513884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1888 19:25:45.514811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1890 19:25:45.607238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1891 19:25:45.608158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1893 19:25:45.700734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1894 19:25:45.701750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1896 19:25:45.794054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1897 19:25:45.795046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1899 19:25:45.887991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1900 19:25:45.888637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1902 19:25:45.981402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1903 19:25:45.982077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1905 19:25:46.073454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1906 19:25:46.074113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1908 19:25:46.166232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1909 19:25:46.166886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1911 19:25:46.258422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1912 19:25:46.259088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1914 19:25:46.350091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1915 19:25:46.350917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1917 19:25:46.441532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1918 19:25:46.442225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1920 19:25:46.526669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1921 19:25:46.527338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1923 19:25:46.620665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1924 19:25:46.621281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1926 19:25:46.713036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1927 19:25:46.713703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1929 19:25:46.804830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1930 19:25:46.805476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1932 19:25:46.897411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1933 19:25:46.898089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1935 19:25:46.988747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1936 19:25:46.989410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1938 19:25:47.080702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1940 19:25:47.082960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1941 19:25:47.173604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1943 19:25:47.176782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1944 19:25:47.274842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1946 19:25:47.277969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1947 19:25:47.368199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1948 19:25:47.368883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1950 19:25:47.459721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1951 19:25:47.460367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1953 19:25:47.550599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1954 19:25:47.551227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1956 19:25:47.642918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1957 19:25:47.643512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1959 19:25:47.736927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1960 19:25:47.737519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1962 19:25:47.828132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1963 19:25:47.828740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1965 19:25:47.913734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1966 19:25:47.914386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1968 19:25:48.006469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1969 19:25:48.007171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1971 19:25:48.098210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1972 19:25:48.098867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1974 19:25:48.189690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1975 19:25:48.190387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1977 19:25:48.281901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1978 19:25:48.282579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1980 19:25:48.375191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1981 19:25:48.375840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1983 19:25:48.467761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1984 19:25:48.468444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1986 19:25:48.560549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1987 19:25:48.561203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1989 19:25:48.663940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1990 19:25:48.664790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1992 19:25:48.765870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
1993 19:25:48.766713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
1995 19:25:48.857437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1996 19:25:48.858226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
1998 19:25:48.947207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
1999 19:25:48.947999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2001 19:25:49.039187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2002 19:25:49.039935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2004 19:25:49.131029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2005 19:25:49.131864 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2007 19:25:49.218602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2008 19:25:49.219480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2010 19:25:49.306712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2011 19:25:49.307380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2013 19:25:49.397996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2014 19:25:49.398620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2016 19:25:49.488766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2017 19:25:49.489409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2019 19:25:49.582600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2020 19:25:49.583215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2022 19:25:49.675717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2023 19:25:49.676354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2025 19:25:49.766754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2026 19:25:49.767393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2028 19:25:49.858627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2029 19:25:49.859282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2031 19:25:49.952374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2032 19:25:49.953052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2034 19:25:50.045988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2035 19:25:50.046646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2037 19:25:50.147111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2038 19:25:50.147794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2040 19:25:50.239742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2041 19:25:50.240395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2043 19:25:50.340980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2044 19:25:50.341722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2046 19:25:50.435487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2047 19:25:50.436150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2049 19:25:50.526033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2050 19:25:50.526669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2052 19:25:50.619203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2053 19:25:50.620071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2055 19:25:50.712371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2056 19:25:50.713231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2058 19:25:50.803861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2059 19:25:50.804711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2061 19:25:50.895817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2062 19:25:50.896650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2064 19:25:50.985434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2065 19:25:50.986340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2067 19:25:51.077407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2068 19:25:51.078341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2070 19:25:51.168575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2071 19:25:51.169451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2073 19:25:51.259596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2074 19:25:51.260489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2076 19:25:51.350949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2077 19:25:51.351792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2079 19:25:51.443247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2080 19:25:51.444074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2082 19:25:51.536934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2083 19:25:51.537787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2085 19:25:51.627047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2086 19:25:51.627672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2088 19:25:51.718273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2089 19:25:51.718936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2091 19:25:51.808564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2092 19:25:51.809253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2094 19:25:51.903200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2095 19:25:51.904178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2097 19:25:51.995020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2098 19:25:51.995950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2100 19:25:52.089613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2101 19:25:52.090597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2103 19:25:52.185407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2104 19:25:52.186050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2106 19:25:52.279819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2107 19:25:52.280927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2109 19:25:52.372469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2110 19:25:52.373337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2112 19:25:52.465483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2113 19:25:52.466418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2115 19:25:52.561731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2116 19:25:52.562604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2118 19:25:52.652314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2119 19:25:52.653183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2121 19:25:52.746831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2122 19:25:52.747741 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2124 19:25:52.839943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2125 19:25:52.840802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2127 19:25:52.931972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2128 19:25:52.932831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2130 19:25:53.022827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2131 19:25:53.023725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2133 19:25:53.116977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2134 19:25:53.118083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2136 19:25:53.207175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2137 19:25:53.208211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2139 19:25:53.306408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2140 19:25:53.307342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2142 19:25:53.399014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2143 19:25:53.399950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2145 19:25:53.493442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2146 19:25:53.494414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2148 19:25:53.596889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2149 19:25:53.597796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2151 19:25:53.696604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2152 19:25:53.697537 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2154 19:25:53.790968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2155 19:25:53.791899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2157 19:25:53.885645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2158 19:25:53.886604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2160 19:25:53.978174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2161 19:25:53.979075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2163 19:25:54.068770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2164 19:25:54.069683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2166 19:25:54.162379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2167 19:25:54.163305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2169 19:25:54.256872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2170 19:25:54.257761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2172 19:25:54.348594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2173 19:25:54.349494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2175 19:25:54.444101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2176 19:25:54.445010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2178 19:25:54.536871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2179 19:25:54.537789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2181 19:25:54.625342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2182 19:25:54.626619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2184 19:25:54.716879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2185 19:25:54.717840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2187 19:25:54.806609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2188 19:25:54.807241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2190 19:25:54.898904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2191 19:25:54.899552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2193 19:25:54.988784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2194 19:25:54.989387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2196 19:25:55.081112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2197 19:25:55.081869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2199 19:25:55.173132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2200 19:25:55.173970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2202 19:25:55.267137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2203 19:25:55.268040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2205 19:25:55.354924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2206 19:25:55.355804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2208 19:25:55.448487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2209 19:25:55.449403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2211 19:25:55.542605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2212 19:25:55.543512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2214 19:25:55.635702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2215 19:25:55.636602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2217 19:25:55.728755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2218 19:25:55.730242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2220 19:25:55.818279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2221 19:25:55.819183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2223 19:25:55.911963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2224 19:25:55.912885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2226 19:25:56.006798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2227 19:25:56.008164 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2229 19:25:56.099723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2230 19:25:56.100676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2232 19:25:56.189969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2233 19:25:56.190654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2235 19:25:56.287220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2236 19:25:56.287858 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2238 19:25:56.380881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2239 19:25:56.381494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2241 19:25:56.468625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2242 19:25:56.469215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2244 19:25:56.560772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2245 19:25:56.561365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2247 19:25:56.652395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2248 19:25:56.653003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2250 19:25:56.746145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2251 19:25:56.746746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2253 19:25:56.838981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2254 19:25:56.839585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2256 19:25:56.932482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2257 19:25:56.933080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2259 19:25:57.023088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2261 19:25:57.026231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2262 19:25:57.115031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2263 19:25:57.115610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2265 19:25:57.210916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2266 19:25:57.211490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2268 19:25:57.304698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2269 19:25:57.305278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2271 19:25:57.395361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2272 19:25:57.395941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2274 19:25:57.486667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2275 19:25:57.487242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2277 19:25:57.577989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2278 19:25:57.578559 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2280 19:25:57.668161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2281 19:25:57.668719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2283 19:25:57.760119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2284 19:25:57.760704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2286 19:25:57.851757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2287 19:25:57.852334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2289 19:25:57.944570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2290 19:25:57.945173 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2292 19:25:58.034992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2293 19:25:58.035555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2295 19:25:58.120150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2296 19:25:58.120731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2298 19:25:58.213311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2299 19:25:58.213883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2301 19:25:58.304031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2302 19:25:58.304617 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2304 19:25:58.395468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2305 19:25:58.396038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2307 19:25:58.485995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2308 19:25:58.486568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2310 19:25:58.576839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2311 19:25:58.577424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2313 19:25:58.666154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2314 19:25:58.666751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2316 19:25:58.754987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2317 19:25:58.755574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2319 19:25:58.840523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2320 19:25:58.841128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2322 19:25:58.932893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2323 19:25:58.933493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2325 19:25:59.023269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2326 19:25:59.023863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2328 19:25:59.112270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2329 19:25:59.113330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2331 19:25:59.204729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2332 19:25:59.205586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2334 19:25:59.292239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2335 19:25:59.293015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2337 19:25:59.381035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2338 19:25:59.381883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2340 19:25:59.469356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2341 19:25:59.470184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2343 19:25:59.562788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2344 19:25:59.563452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2346 19:25:59.655823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2347 19:25:59.656506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2349 19:25:59.748370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2350 19:25:59.749024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2352 19:25:59.836666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2353 19:25:59.837090 + set +x
2354 19:25:59.837590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2356 19:25:59.840958 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 948501_1.6.2.4.5>
2357 19:25:59.841506 Received signal: <ENDRUN> 1_kselftest-dt 948501_1.6.2.4.5
2358 19:25:59.841786 Ending use of test pattern.
2359 19:25:59.842288 Ending test lava.1_kselftest-dt (948501_1.6.2.4.5), duration 86.22
2361 19:25:59.847555 <LAVA_TEST_RUNNER EXIT>
2362 19:25:59.848269 ok: lava_test_shell seems to have completed
2363 19:25:59.861060 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2364 19:25:59.863010 end: 3.1 lava-test-shell (duration 00:01:28) [common]
2365 19:25:59.863616 end: 3 lava-test-retry (duration 00:01:28) [common]
2366 19:25:59.864186 start: 4 finalize (timeout 00:05:23) [common]
2367 19:25:59.864755 start: 4.1 power-off (timeout 00:00:30) [common]
2368 19:25:59.865703 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2369 19:25:59.901306 >> OK - accepted request
2370 19:25:59.903018 Returned 0 in 0 seconds
2371 19:26:00.004211 end: 4.1 power-off (duration 00:00:00) [common]
2373 19:26:00.005961 start: 4.2 read-feedback (timeout 00:05:22) [common]
2374 19:26:00.007109 Listened to connection for namespace 'common' for up to 1s
2375 19:26:00.007992 Listened to connection for namespace 'common' for up to 1s
2376 19:26:01.006920 Finalising connection for namespace 'common'
2377 19:26:01.007522 Disconnecting from shell: Finalise
2378 19:26:01.007912 / #
2379 19:26:01.108761 end: 4.2 read-feedback (duration 00:00:01) [common]
2380 19:26:01.109376 end: 4 finalize (duration 00:00:01) [common]
2381 19:26:01.109878 Cleaning after the job
2382 19:26:01.110342 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948501/tftp-deploy-dih1vpji/ramdisk
2383 19:26:01.115539 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948501/tftp-deploy-dih1vpji/kernel
2384 19:26:01.116936 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948501/tftp-deploy-dih1vpji/dtb
2385 19:26:01.117756 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948501/tftp-deploy-dih1vpji/nfsrootfs
2386 19:26:01.262268 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948501/tftp-deploy-dih1vpji/modules
2387 19:26:01.272412 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/948501
2388 19:26:04.451254 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/948501
2389 19:26:04.451867 Job finished correctly