Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:26:52.206913 lava-dispatcher, installed at version: 2024.01
2 20:26:52.207731 start: 0 validate
3 20:26:52.208239 Start time: 2024-11-06 20:26:52.208207+00:00 (UTC)
4 20:26:52.208792 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:26:52.209341 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 20:26:52.249057 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:26:52.249631 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fkernel%2FImage exists
8 20:26:52.283711 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:26:52.284409 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 20:26:53.339440 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:26:53.339969 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fmodules.tar.xz exists
12 20:26:53.389457 validate duration: 1.18
14 20:26:53.390311 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:26:53.390668 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:26:53.390977 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:26:53.391581 Not decompressing ramdisk as can be used compressed.
18 20:26:53.392033 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 20:26:53.392286 saving as /var/lib/lava/dispatcher/tmp/948787/tftp-deploy-95vtvp9a/ramdisk/rootfs.cpio.gz
20 20:26:53.392558 total size: 8181887 (7 MB)
21 20:26:53.432877 progress 0 % (0 MB)
22 20:26:53.438947 progress 5 % (0 MB)
23 20:26:53.444642 progress 10 % (0 MB)
24 20:26:53.450606 progress 15 % (1 MB)
25 20:26:53.456063 progress 20 % (1 MB)
26 20:26:53.461949 progress 25 % (1 MB)
27 20:26:53.467451 progress 30 % (2 MB)
28 20:26:53.475563 progress 35 % (2 MB)
29 20:26:53.480940 progress 40 % (3 MB)
30 20:26:53.486627 progress 45 % (3 MB)
31 20:26:53.492138 progress 50 % (3 MB)
32 20:26:53.498020 progress 55 % (4 MB)
33 20:26:53.503283 progress 60 % (4 MB)
34 20:26:53.509073 progress 65 % (5 MB)
35 20:26:53.514389 progress 70 % (5 MB)
36 20:26:53.520096 progress 75 % (5 MB)
37 20:26:53.525492 progress 80 % (6 MB)
38 20:26:53.531276 progress 85 % (6 MB)
39 20:26:53.536771 progress 90 % (7 MB)
40 20:26:53.542425 progress 95 % (7 MB)
41 20:26:53.547183 progress 100 % (7 MB)
42 20:26:53.547853 7 MB downloaded in 0.16 s (50.25 MB/s)
43 20:26:53.548448 end: 1.1.1 http-download (duration 00:00:00) [common]
45 20:26:53.549339 end: 1.1 download-retry (duration 00:00:00) [common]
46 20:26:53.549630 start: 1.2 download-retry (timeout 00:10:00) [common]
47 20:26:53.549899 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 20:26:53.550377 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/kernel/Image
49 20:26:53.550657 saving as /var/lib/lava/dispatcher/tmp/948787/tftp-deploy-95vtvp9a/kernel/Image
50 20:26:53.550867 total size: 39424512 (37 MB)
51 20:26:53.551079 No compression specified
52 20:26:53.588615 progress 0 % (0 MB)
53 20:26:53.613640 progress 5 % (1 MB)
54 20:26:53.637761 progress 10 % (3 MB)
55 20:26:53.661788 progress 15 % (5 MB)
56 20:26:53.685974 progress 20 % (7 MB)
57 20:26:53.710029 progress 25 % (9 MB)
58 20:26:53.734445 progress 30 % (11 MB)
59 20:26:53.759106 progress 35 % (13 MB)
60 20:26:53.783125 progress 40 % (15 MB)
61 20:26:53.807161 progress 45 % (16 MB)
62 20:26:53.831383 progress 50 % (18 MB)
63 20:26:53.855439 progress 55 % (20 MB)
64 20:26:53.879431 progress 60 % (22 MB)
65 20:26:53.903856 progress 65 % (24 MB)
66 20:26:53.928027 progress 70 % (26 MB)
67 20:26:53.952112 progress 75 % (28 MB)
68 20:26:53.976192 progress 80 % (30 MB)
69 20:26:54.000788 progress 85 % (31 MB)
70 20:26:54.024939 progress 90 % (33 MB)
71 20:26:54.048907 progress 95 % (35 MB)
72 20:26:54.073281 progress 100 % (37 MB)
73 20:26:54.073856 37 MB downloaded in 0.52 s (71.89 MB/s)
74 20:26:54.074343 end: 1.2.1 http-download (duration 00:00:01) [common]
76 20:26:54.075184 end: 1.2 download-retry (duration 00:00:01) [common]
77 20:26:54.075460 start: 1.3 download-retry (timeout 00:09:59) [common]
78 20:26:54.075723 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 20:26:54.076216 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 20:26:54.076502 saving as /var/lib/lava/dispatcher/tmp/948787/tftp-deploy-95vtvp9a/dtb/meson-g12b-a311d-libretech-cc.dtb
81 20:26:54.076710 total size: 54703 (0 MB)
82 20:26:54.076918 No compression specified
83 20:26:54.109625 progress 59 % (0 MB)
84 20:26:54.111065 progress 100 % (0 MB)
85 20:26:54.112106 0 MB downloaded in 0.04 s (1.47 MB/s)
86 20:26:54.112612 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:26:54.113445 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:26:54.113710 start: 1.4 download-retry (timeout 00:09:59) [common]
90 20:26:54.113973 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 20:26:54.114435 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/modules.tar.xz
92 20:26:54.114687 saving as /var/lib/lava/dispatcher/tmp/948787/tftp-deploy-95vtvp9a/modules/modules.tar
93 20:26:54.114893 total size: 11755752 (11 MB)
94 20:26:54.115105 Using unxz to decompress xz
95 20:26:54.146806 progress 0 % (0 MB)
96 20:26:54.213778 progress 5 % (0 MB)
97 20:26:54.288901 progress 10 % (1 MB)
98 20:26:54.386331 progress 15 % (1 MB)
99 20:26:54.482957 progress 20 % (2 MB)
100 20:26:54.562611 progress 25 % (2 MB)
101 20:26:54.640799 progress 30 % (3 MB)
102 20:26:54.722317 progress 35 % (3 MB)
103 20:26:54.802521 progress 40 % (4 MB)
104 20:26:54.879275 progress 45 % (5 MB)
105 20:26:54.964875 progress 50 % (5 MB)
106 20:26:55.047309 progress 55 % (6 MB)
107 20:26:55.132835 progress 60 % (6 MB)
108 20:26:55.218698 progress 65 % (7 MB)
109 20:26:55.307078 progress 70 % (7 MB)
110 20:26:55.391767 progress 75 % (8 MB)
111 20:26:55.476378 progress 80 % (9 MB)
112 20:26:55.553677 progress 85 % (9 MB)
113 20:26:55.638398 progress 90 % (10 MB)
114 20:26:55.718207 progress 95 % (10 MB)
115 20:26:55.796262 progress 100 % (11 MB)
116 20:26:55.811756 11 MB downloaded in 1.70 s (6.61 MB/s)
117 20:26:55.812755 end: 1.4.1 http-download (duration 00:00:02) [common]
119 20:26:55.814343 end: 1.4 download-retry (duration 00:00:02) [common]
120 20:26:55.814862 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 20:26:55.815374 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 20:26:55.815856 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:26:55.816388 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 20:26:55.817364 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9
125 20:26:55.818196 makedir: /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin
126 20:26:55.818838 makedir: /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/tests
127 20:26:55.819454 makedir: /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/results
128 20:26:55.820094 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-add-keys
129 20:26:55.821057 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-add-sources
130 20:26:55.822038 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-background-process-start
131 20:26:55.822982 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-background-process-stop
132 20:26:55.824060 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-common-functions
133 20:26:55.824996 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-echo-ipv4
134 20:26:55.825906 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-install-packages
135 20:26:55.826795 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-installed-packages
136 20:26:55.827685 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-os-build
137 20:26:55.828617 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-probe-channel
138 20:26:55.829521 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-probe-ip
139 20:26:55.830415 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-target-ip
140 20:26:55.831297 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-target-mac
141 20:26:55.832213 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-target-storage
142 20:26:55.833138 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-test-case
143 20:26:55.834122 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-test-event
144 20:26:55.835059 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-test-feedback
145 20:26:55.835952 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-test-raise
146 20:26:55.836902 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-test-reference
147 20:26:55.837797 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-test-runner
148 20:26:55.838711 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-test-set
149 20:26:55.839592 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-test-shell
150 20:26:55.840536 Updating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-install-packages (oe)
151 20:26:55.841514 Updating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/bin/lava-installed-packages (oe)
152 20:26:55.842407 Creating /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/environment
153 20:26:55.843116 LAVA metadata
154 20:26:55.843596 - LAVA_JOB_ID=948787
155 20:26:55.844049 - LAVA_DISPATCHER_IP=192.168.6.2
156 20:26:55.844719 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 20:26:55.846583 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 20:26:55.847192 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 20:26:55.847599 skipped lava-vland-overlay
160 20:26:55.848144 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 20:26:55.848673 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 20:26:55.849098 skipped lava-multinode-overlay
163 20:26:55.849575 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 20:26:55.850069 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 20:26:55.850550 Loading test definitions
166 20:26:55.851093 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 20:26:55.851530 Using /lava-948787 at stage 0
168 20:26:55.853884 uuid=948787_1.5.2.4.1 testdef=None
169 20:26:55.854481 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 20:26:55.854998 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 20:26:55.857375 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 20:26:55.858194 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 20:26:55.860534 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 20:26:55.861402 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:58) [common]
177 20:26:55.863620 runner path: /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/0/tests/0_dmesg test_uuid 948787_1.5.2.4.1
178 20:26:55.864224 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 20:26:55.865001 Creating lava-test-runner.conf files
181 20:26:55.865204 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/948787/lava-overlay-a13brxn9/lava-948787/0 for stage 0
182 20:26:55.865552 - 0_dmesg
183 20:26:55.865908 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 20:26:55.866191 start: 1.5.2.5 compress-overlay (timeout 00:09:58) [common]
185 20:26:55.890097 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 20:26:55.890535 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 20:26:55.890802 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 20:26:55.891071 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 20:26:55.891334 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 20:26:56.925601 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 20:26:56.926073 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 20:26:56.926320 extracting modules file /var/lib/lava/dispatcher/tmp/948787/tftp-deploy-95vtvp9a/modules/modules.tar to /var/lib/lava/dispatcher/tmp/948787/extract-overlay-ramdisk-m43gu4hv/ramdisk
193 20:26:58.254235 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 20:26:58.254723 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 20:26:58.255012 [common] Applying overlay /var/lib/lava/dispatcher/tmp/948787/compress-overlay-qokaxkaj/overlay-1.5.2.5.tar.gz to ramdisk
196 20:26:58.255240 [common] Applying overlay /var/lib/lava/dispatcher/tmp/948787/compress-overlay-qokaxkaj/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/948787/extract-overlay-ramdisk-m43gu4hv/ramdisk
197 20:26:58.285679 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 20:26:58.286112 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 20:26:58.286381 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 20:26:58.286606 Converting downloaded kernel to a uImage
201 20:26:58.286911 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/948787/tftp-deploy-95vtvp9a/kernel/Image /var/lib/lava/dispatcher/tmp/948787/tftp-deploy-95vtvp9a/kernel/uImage
202 20:26:58.678283 output: Image Name:
203 20:26:58.678783 output: Created: Wed Nov 6 20:26:58 2024
204 20:26:58.679040 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 20:26:58.679288 output: Data Size: 39424512 Bytes = 38500.50 KiB = 37.60 MiB
206 20:26:58.679532 output: Load Address: 01080000
207 20:26:58.679773 output: Entry Point: 01080000
208 20:26:58.680043 output:
209 20:26:58.680453 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 20:26:58.680780 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 20:26:58.681109 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 20:26:58.681414 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 20:26:58.681726 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 20:26:58.682037 Building ramdisk /var/lib/lava/dispatcher/tmp/948787/extract-overlay-ramdisk-m43gu4hv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/948787/extract-overlay-ramdisk-m43gu4hv/ramdisk
215 20:27:01.365586 >> 188260 blocks
216 20:27:09.792240 Adding RAMdisk u-boot header.
217 20:27:09.792737 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/948787/extract-overlay-ramdisk-m43gu4hv/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/948787/extract-overlay-ramdisk-m43gu4hv/ramdisk.cpio.gz.uboot
218 20:27:10.122699 output: Image Name:
219 20:27:10.123115 output: Created: Wed Nov 6 20:27:09 2024
220 20:27:10.123528 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 20:27:10.123937 output: Data Size: 26755835 Bytes = 26128.75 KiB = 25.52 MiB
222 20:27:10.124395 output: Load Address: 00000000
223 20:27:10.124791 output: Entry Point: 00000000
224 20:27:10.125182 output:
225 20:27:10.126192 rename /var/lib/lava/dispatcher/tmp/948787/extract-overlay-ramdisk-m43gu4hv/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/948787/tftp-deploy-95vtvp9a/ramdisk/ramdisk.cpio.gz.uboot
226 20:27:10.126900 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 20:27:10.127447 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 20:27:10.127973 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 20:27:10.128468 No LXC device requested
230 20:27:10.128973 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 20:27:10.129485 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 20:27:10.129978 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 20:27:10.130391 Checking files for TFTP limit of 4294967296 bytes.
234 20:27:10.133089 end: 1 tftp-deploy (duration 00:00:17) [common]
235 20:27:10.133664 start: 2 uboot-action (timeout 00:05:00) [common]
236 20:27:10.134195 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 20:27:10.134702 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 20:27:10.135207 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 20:27:10.135742 Using kernel file from prepare-kernel: 948787/tftp-deploy-95vtvp9a/kernel/uImage
240 20:27:10.136406 substitutions:
241 20:27:10.136825 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 20:27:10.137229 - {DTB_ADDR}: 0x01070000
243 20:27:10.137632 - {DTB}: 948787/tftp-deploy-95vtvp9a/dtb/meson-g12b-a311d-libretech-cc.dtb
244 20:27:10.138034 - {INITRD}: 948787/tftp-deploy-95vtvp9a/ramdisk/ramdisk.cpio.gz.uboot
245 20:27:10.138432 - {KERNEL_ADDR}: 0x01080000
246 20:27:10.138825 - {KERNEL}: 948787/tftp-deploy-95vtvp9a/kernel/uImage
247 20:27:10.139220 - {LAVA_MAC}: None
248 20:27:10.139653 - {PRESEED_CONFIG}: None
249 20:27:10.140076 - {PRESEED_LOCAL}: None
250 20:27:10.140471 - {RAMDISK_ADDR}: 0x08000000
251 20:27:10.140857 - {RAMDISK}: 948787/tftp-deploy-95vtvp9a/ramdisk/ramdisk.cpio.gz.uboot
252 20:27:10.141248 - {ROOT_PART}: None
253 20:27:10.141637 - {ROOT}: None
254 20:27:10.142025 - {SERVER_IP}: 192.168.6.2
255 20:27:10.142419 - {TEE_ADDR}: 0x83000000
256 20:27:10.142806 - {TEE}: None
257 20:27:10.143196 Parsed boot commands:
258 20:27:10.143573 - setenv autoload no
259 20:27:10.143959 - setenv initrd_high 0xffffffff
260 20:27:10.144377 - setenv fdt_high 0xffffffff
261 20:27:10.144767 - dhcp
262 20:27:10.145154 - setenv serverip 192.168.6.2
263 20:27:10.145538 - tftpboot 0x01080000 948787/tftp-deploy-95vtvp9a/kernel/uImage
264 20:27:10.145927 - tftpboot 0x08000000 948787/tftp-deploy-95vtvp9a/ramdisk/ramdisk.cpio.gz.uboot
265 20:27:10.146314 - tftpboot 0x01070000 948787/tftp-deploy-95vtvp9a/dtb/meson-g12b-a311d-libretech-cc.dtb
266 20:27:10.146700 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 20:27:10.147099 - bootm 0x01080000 0x08000000 0x01070000
268 20:27:10.147599 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 20:27:10.149148 start: 2.3 connect-device (timeout 00:05:00) [common]
271 20:27:10.149601 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 20:27:10.164237 Setting prompt string to ['lava-test: # ']
273 20:27:10.165705 end: 2.3 connect-device (duration 00:00:00) [common]
274 20:27:10.166301 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 20:27:10.166870 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 20:27:10.167410 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 20:27:10.168592 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 20:27:10.207142 >> OK - accepted request
279 20:27:10.208999 Returned 0 in 0 seconds
280 20:27:10.310096 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 20:27:10.311725 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 20:27:10.312356 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 20:27:10.312871 Setting prompt string to ['Hit any key to stop autoboot']
285 20:27:10.313330 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 20:27:10.314925 Trying 192.168.56.21...
287 20:27:10.315398 Connected to conserv1.
288 20:27:10.315809 Escape character is '^]'.
289 20:27:10.316262
290 20:27:10.316692 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 20:27:10.317123
292 20:27:22.390919 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 20:27:22.391559 bl2_stage_init 0x01
294 20:27:22.392056 bl2_stage_init 0x81
295 20:27:22.396503 hw id: 0x0000 - pwm id 0x01
296 20:27:22.397030 bl2_stage_init 0xc1
297 20:27:22.397437 bl2_stage_init 0x02
298 20:27:22.397840
299 20:27:22.402188 L0:00000000
300 20:27:22.402644 L1:20000703
301 20:27:22.403047 L2:00008067
302 20:27:22.403438 L3:14000000
303 20:27:22.407569 B2:00402000
304 20:27:22.408019 B1:e0f83180
305 20:27:22.408414
306 20:27:22.408800 TE: 58159
307 20:27:22.409181
308 20:27:22.413241 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 20:27:22.413659
310 20:27:22.414043 Board ID = 1
311 20:27:22.418853 Set A53 clk to 24M
312 20:27:22.419268 Set A73 clk to 24M
313 20:27:22.419650 Set clk81 to 24M
314 20:27:22.424464 A53 clk: 1200 MHz
315 20:27:22.424882 A73 clk: 1200 MHz
316 20:27:22.425264 CLK81: 166.6M
317 20:27:22.425645 smccc: 00012ab5
318 20:27:22.430025 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 20:27:22.435540 board id: 1
320 20:27:22.441625 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 20:27:22.452073 fw parse done
322 20:27:22.457989 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 20:27:22.500631 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 20:27:22.511512 PIEI prepare done
325 20:27:22.512009 fastboot data load
326 20:27:22.512407 fastboot data verify
327 20:27:22.517639 verify result: 266
328 20:27:22.522881 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 20:27:22.523392 LPDDR4 probe
330 20:27:22.523792 ddr clk to 1584MHz
331 20:27:22.530899 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 20:27:22.568181
333 20:27:22.568746 dmc_version 0001
334 20:27:22.574730 Check phy result
335 20:27:22.580607 INFO : End of CA training
336 20:27:22.581056 INFO : End of initialization
337 20:27:22.586197 INFO : Training has run successfully!
338 20:27:22.586628 Check phy result
339 20:27:22.591779 INFO : End of initialization
340 20:27:22.592239 INFO : End of read enable training
341 20:27:22.597333 INFO : End of fine write leveling
342 20:27:22.602940 INFO : End of Write leveling coarse delay
343 20:27:22.603366 INFO : Training has run successfully!
344 20:27:22.603763 Check phy result
345 20:27:22.608541 INFO : End of initialization
346 20:27:22.608972 INFO : End of read dq deskew training
347 20:27:22.614157 INFO : End of MPR read delay center optimization
348 20:27:22.619732 INFO : End of write delay center optimization
349 20:27:22.625353 INFO : End of read delay center optimization
350 20:27:22.625800 INFO : End of max read latency training
351 20:27:22.630943 INFO : Training has run successfully!
352 20:27:22.631378 1D training succeed
353 20:27:22.640257 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 20:27:22.687784 Check phy result
355 20:27:22.688383 INFO : End of initialization
356 20:27:22.709344 INFO : End of 2D read delay Voltage center optimization
357 20:27:22.729391 INFO : End of 2D read delay Voltage center optimization
358 20:27:22.781343 INFO : End of 2D write delay Voltage center optimization
359 20:27:22.830604 INFO : End of 2D write delay Voltage center optimization
360 20:27:22.836219 INFO : Training has run successfully!
361 20:27:22.836562
362 20:27:22.836800 channel==0
363 20:27:22.841807 RxClkDly_Margin_A0==88 ps 9
364 20:27:22.842135 TxDqDly_Margin_A0==98 ps 10
365 20:27:22.847403 RxClkDly_Margin_A1==88 ps 9
366 20:27:22.847731 TxDqDly_Margin_A1==98 ps 10
367 20:27:22.847967 TrainedVREFDQ_A0==74
368 20:27:22.852958 TrainedVREFDQ_A1==75
369 20:27:22.853286 VrefDac_Margin_A0==25
370 20:27:22.853517 DeviceVref_Margin_A0==40
371 20:27:22.858564 VrefDac_Margin_A1==25
372 20:27:22.858887 DeviceVref_Margin_A1==39
373 20:27:22.859118
374 20:27:22.859336
375 20:27:22.864173 channel==1
376 20:27:22.864501 RxClkDly_Margin_A0==98 ps 10
377 20:27:22.864731 TxDqDly_Margin_A0==98 ps 10
378 20:27:22.869765 RxClkDly_Margin_A1==98 ps 10
379 20:27:22.870095 TxDqDly_Margin_A1==88 ps 9
380 20:27:22.875404 TrainedVREFDQ_A0==77
381 20:27:22.875741 TrainedVREFDQ_A1==77
382 20:27:22.875969 VrefDac_Margin_A0==22
383 20:27:22.880965 DeviceVref_Margin_A0==37
384 20:27:22.881299 VrefDac_Margin_A1==22
385 20:27:22.886591 DeviceVref_Margin_A1==37
386 20:27:22.886939
387 20:27:22.887175 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 20:27:22.892184
389 20:27:22.920145 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 20:27:22.920562 2D training succeed
391 20:27:22.925759 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 20:27:22.931389 auto size-- 65535DDR cs0 size: 2048MB
393 20:27:22.931709 DDR cs1 size: 2048MB
394 20:27:22.936963 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 20:27:22.937292 cs0 DataBus test pass
396 20:27:22.942558 cs1 DataBus test pass
397 20:27:22.942880 cs0 AddrBus test pass
398 20:27:22.943110 cs1 AddrBus test pass
399 20:27:22.943324
400 20:27:22.948200 100bdlr_step_size ps== 420
401 20:27:22.948532 result report
402 20:27:22.953757 boot times 0Enable ddr reg access
403 20:27:22.959205 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 20:27:22.972610 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 20:27:23.544694 0.0;M3 CHK:0;cm4_sp_mode 0
406 20:27:23.545119 MVN_1=0x00000000
407 20:27:23.550198 MVN_2=0x00000000
408 20:27:23.555971 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 20:27:23.556340 OPS=0x10
410 20:27:23.556568 ring efuse init
411 20:27:23.556784 chipver efuse init
412 20:27:23.561557 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 20:27:23.567147 [0.018960 Inits done]
414 20:27:23.567469 secure task start!
415 20:27:23.567699 high task start!
416 20:27:23.571740 low task start!
417 20:27:23.572098 run into bl31
418 20:27:23.578405 NOTICE: BL31: v1.3(release):4fc40b1
419 20:27:23.586191 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 20:27:23.586646 NOTICE: BL31: G12A normal boot!
421 20:27:23.611575 NOTICE: BL31: BL33 decompress pass
422 20:27:23.617211 ERROR: Error initializing runtime service opteed_fast
423 20:27:24.850169
424 20:27:24.850597
425 20:27:24.858530 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 20:27:24.858858
427 20:27:24.859083 Model: Libre Computer AML-A311D-CC Alta
428 20:27:25.066962 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 20:27:25.090322 DRAM: 2 GiB (effective 3.8 GiB)
430 20:27:25.233345 Core: 408 devices, 31 uclasses, devicetree: separate
431 20:27:25.239198 WDT: Not starting watchdog@f0d0
432 20:27:25.271467 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 20:27:25.283907 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 20:27:25.288912 ** Bad device specification mmc 0 **
435 20:27:25.299226 Card did not respond to voltage select! : -110
436 20:27:25.306894 ** Bad device specification mmc 0 **
437 20:27:25.307202 Couldn't find partition mmc 0
438 20:27:25.315222 Card did not respond to voltage select! : -110
439 20:27:25.320751 ** Bad device specification mmc 0 **
440 20:27:25.321045 Couldn't find partition mmc 0
441 20:27:25.325833 Error: could not access storage.
442 20:27:26.591536 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 20:27:26.592191 bl2_stage_init 0x01
444 20:27:26.592489 bl2_stage_init 0x81
445 20:27:26.597047 hw id: 0x0000 - pwm id 0x01
446 20:27:26.597493 bl2_stage_init 0xc1
447 20:27:26.597884 bl2_stage_init 0x02
448 20:27:26.598154
449 20:27:26.602629 L0:00000000
450 20:27:26.603080 L1:20000703
451 20:27:26.603471 L2:00008067
452 20:27:26.603743 L3:14000000
453 20:27:26.608228 B2:00402000
454 20:27:26.608570 B1:e0f83180
455 20:27:26.608812
456 20:27:26.609045 TE: 58124
457 20:27:26.609279
458 20:27:26.613837 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 20:27:26.614155
460 20:27:26.614396 Board ID = 1
461 20:27:26.619427 Set A53 clk to 24M
462 20:27:26.619871 Set A73 clk to 24M
463 20:27:26.620294 Set clk81 to 24M
464 20:27:26.625146 A53 clk: 1200 MHz
465 20:27:26.625612 A73 clk: 1200 MHz
466 20:27:26.625888 CLK81: 166.6M
467 20:27:26.626122 smccc: 00012a92
468 20:27:26.630620 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 20:27:26.636213 board id: 1
470 20:27:26.642109 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 20:27:26.652785 fw parse done
472 20:27:26.658774 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 20:27:26.701402 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 20:27:26.712322 PIEI prepare done
475 20:27:26.712714 fastboot data load
476 20:27:26.712957 fastboot data verify
477 20:27:26.717873 verify result: 266
478 20:27:26.723499 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 20:27:26.724023 LPDDR4 probe
480 20:27:26.724310 ddr clk to 1584MHz
481 20:27:26.731454 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 20:27:26.768729
483 20:27:26.769139 dmc_version 0001
484 20:27:26.775372 Check phy result
485 20:27:26.781253 INFO : End of CA training
486 20:27:26.781703 INFO : End of initialization
487 20:27:26.786853 INFO : Training has run successfully!
488 20:27:26.787160 Check phy result
489 20:27:26.792458 INFO : End of initialization
490 20:27:26.792912 INFO : End of read enable training
491 20:27:26.798055 INFO : End of fine write leveling
492 20:27:26.803651 INFO : End of Write leveling coarse delay
493 20:27:26.804114 INFO : Training has run successfully!
494 20:27:26.804603 Check phy result
495 20:27:26.809382 INFO : End of initialization
496 20:27:26.809930 INFO : End of read dq deskew training
497 20:27:26.814961 INFO : End of MPR read delay center optimization
498 20:27:26.820549 INFO : End of write delay center optimization
499 20:27:26.826198 INFO : End of read delay center optimization
500 20:27:26.826713 INFO : End of max read latency training
501 20:27:26.831797 INFO : Training has run successfully!
502 20:27:26.832356 1D training succeed
503 20:27:26.840942 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 20:27:26.888595 Check phy result
505 20:27:26.889165 INFO : End of initialization
506 20:27:26.910319 INFO : End of 2D read delay Voltage center optimization
507 20:27:26.930545 INFO : End of 2D read delay Voltage center optimization
508 20:27:26.982684 INFO : End of 2D write delay Voltage center optimization
509 20:27:27.032028 INFO : End of 2D write delay Voltage center optimization
510 20:27:27.037544 INFO : Training has run successfully!
511 20:27:27.038170
512 20:27:27.038637 channel==0
513 20:27:27.043213 RxClkDly_Margin_A0==88 ps 9
514 20:27:27.043821 TxDqDly_Margin_A0==98 ps 10
515 20:27:27.048755 RxClkDly_Margin_A1==88 ps 9
516 20:27:27.049338 TxDqDly_Margin_A1==98 ps 10
517 20:27:27.049804 TrainedVREFDQ_A0==74
518 20:27:27.054371 TrainedVREFDQ_A1==74
519 20:27:27.054975 VrefDac_Margin_A0==25
520 20:27:27.055436 DeviceVref_Margin_A0==40
521 20:27:27.059938 VrefDac_Margin_A1==25
522 20:27:27.060537 DeviceVref_Margin_A1==40
523 20:27:27.060986
524 20:27:27.061429
525 20:27:27.065540 channel==1
526 20:27:27.066105 RxClkDly_Margin_A0==98 ps 10
527 20:27:27.066558 TxDqDly_Margin_A0==98 ps 10
528 20:27:27.071193 RxClkDly_Margin_A1==98 ps 10
529 20:27:27.071766 TxDqDly_Margin_A1==88 ps 9
530 20:27:27.076820 TrainedVREFDQ_A0==77
531 20:27:27.077470 TrainedVREFDQ_A1==77
532 20:27:27.077942 VrefDac_Margin_A0==22
533 20:27:27.082360 DeviceVref_Margin_A0==37
534 20:27:27.082924 VrefDac_Margin_A1==22
535 20:27:27.087941 DeviceVref_Margin_A1==37
536 20:27:27.088541
537 20:27:27.088998 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 20:27:27.093501
539 20:27:27.121447 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
540 20:27:27.122093 2D training succeed
541 20:27:27.127229 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 20:27:27.134940 auto size-- 65535DDR cs0 size: 2048MB
543 20:27:27.135328 DDR cs1 size: 2048MB
544 20:27:27.138322 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 20:27:27.138879 cs0 DataBus test pass
546 20:27:27.143916 cs1 DataBus test pass
547 20:27:27.144503 cs0 AddrBus test pass
548 20:27:27.144956 cs1 AddrBus test pass
549 20:27:27.145403
550 20:27:27.149499 100bdlr_step_size ps== 420
551 20:27:27.150077 result report
552 20:27:27.155172 boot times 0Enable ddr reg access
553 20:27:27.160554 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 20:27:27.173941 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 20:27:27.747779 0.0;M3 CHK:0;cm4_sp_mode 0
556 20:27:27.748214 MVN_1=0x00000000
557 20:27:27.754329 MVN_2=0x00000000
558 20:27:27.759023 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 20:27:27.759525 OPS=0x10
560 20:27:27.759931 ring efuse init
561 20:27:27.760361 chipver efuse init
562 20:27:27.764577 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 20:27:27.770194 [0.018961 Inits done]
564 20:27:27.770686 secure task start!
565 20:27:27.771077 high task start!
566 20:27:27.774820 low task start!
567 20:27:27.775304 run into bl31
568 20:27:27.781399 NOTICE: BL31: v1.3(release):4fc40b1
569 20:27:27.789353 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 20:27:27.789877 NOTICE: BL31: G12A normal boot!
571 20:27:27.814668 NOTICE: BL31: BL33 decompress pass
572 20:27:27.820202 ERROR: Error initializing runtime service opteed_fast
573 20:27:29.053201
574 20:27:29.053808
575 20:27:29.061652 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 20:27:29.062114
577 20:27:29.062525 Model: Libre Computer AML-A311D-CC Alta
578 20:27:29.270958 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 20:27:29.294572 DRAM: 2 GiB (effective 3.8 GiB)
580 20:27:29.441079 Core: 408 devices, 31 uclasses, devicetree: separate
581 20:27:29.442829 WDT: Not starting watchdog@f0d0
582 20:27:29.474617 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 20:27:29.487016 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 20:27:29.491879 ** Bad device specification mmc 0 **
585 20:27:29.502310 Card did not respond to voltage select! : -110
586 20:27:29.510157 ** Bad device specification mmc 0 **
587 20:27:29.510673 Couldn't find partition mmc 0
588 20:27:29.518172 Card did not respond to voltage select! : -110
589 20:27:29.523704 ** Bad device specification mmc 0 **
590 20:27:29.524468 Couldn't find partition mmc 0
591 20:27:29.528857 Error: could not access storage.
592 20:27:29.877074 Net: eth0: ethernet@ff3f0000
593 20:27:29.877750 starting USB...
594 20:27:30.124136 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 20:27:30.124777 Starting the controller
596 20:27:30.131231 USB XHCI 1.10
597 20:27:31.840344 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 20:27:31.840972 bl2_stage_init 0x01
599 20:27:31.841393 bl2_stage_init 0x81
600 20:27:31.845871 hw id: 0x0000 - pwm id 0x01
601 20:27:31.846338 bl2_stage_init 0xc1
602 20:27:31.846746 bl2_stage_init 0x02
603 20:27:31.847142
604 20:27:31.851461 L0:00000000
605 20:27:31.851938 L1:20000703
606 20:27:31.852406 L2:00008067
607 20:27:31.852815 L3:14000000
608 20:27:31.854324 B2:00402000
609 20:27:31.854756 B1:e0f83180
610 20:27:31.855151
611 20:27:31.855547 TE: 58124
612 20:27:31.855942
613 20:27:31.865580 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 20:27:31.866074
615 20:27:31.866487 Board ID = 1
616 20:27:31.866882 Set A53 clk to 24M
617 20:27:31.867308 Set A73 clk to 24M
618 20:27:31.871047 Set clk81 to 24M
619 20:27:31.871501 A53 clk: 1200 MHz
620 20:27:31.871921 A73 clk: 1200 MHz
621 20:27:31.876856 CLK81: 166.6M
622 20:27:31.877333 smccc: 00012a92
623 20:27:31.882415 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 20:27:31.882867 board id: 1
625 20:27:31.891016 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 20:27:31.901442 fw parse done
627 20:27:31.907391 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 20:27:31.949992 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 20:27:31.960899 PIEI prepare done
630 20:27:31.961396 fastboot data load
631 20:27:31.961805 fastboot data verify
632 20:27:31.966632 verify result: 266
633 20:27:31.972210 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 20:27:31.972684 LPDDR4 probe
635 20:27:31.973090 ddr clk to 1584MHz
636 20:27:31.980254 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 20:27:32.017540
638 20:27:32.018336 dmc_version 0001
639 20:27:32.024096 Check phy result
640 20:27:32.029990 INFO : End of CA training
641 20:27:32.030719 INFO : End of initialization
642 20:27:32.035543 INFO : Training has run successfully!
643 20:27:32.036245 Check phy result
644 20:27:32.041318 INFO : End of initialization
645 20:27:32.042022 INFO : End of read enable training
646 20:27:32.047344 INFO : End of fine write leveling
647 20:27:32.052361 INFO : End of Write leveling coarse delay
648 20:27:32.052988 INFO : Training has run successfully!
649 20:27:32.053528 Check phy result
650 20:27:32.057971 INFO : End of initialization
651 20:27:32.058730 INFO : End of read dq deskew training
652 20:27:32.063551 INFO : End of MPR read delay center optimization
653 20:27:32.069420 INFO : End of write delay center optimization
654 20:27:32.074782 INFO : End of read delay center optimization
655 20:27:32.075404 INFO : End of max read latency training
656 20:27:32.080367 INFO : Training has run successfully!
657 20:27:32.081008 1D training succeed
658 20:27:32.089549 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 20:27:32.137189 Check phy result
660 20:27:32.138094 INFO : End of initialization
661 20:27:32.159641 INFO : End of 2D read delay Voltage center optimization
662 20:27:32.179742 INFO : End of 2D read delay Voltage center optimization
663 20:27:32.231717 INFO : End of 2D write delay Voltage center optimization
664 20:27:32.280880 INFO : End of 2D write delay Voltage center optimization
665 20:27:32.293814 INFO : Training has run successfully!
666 20:27:32.294403
667 20:27:32.294827 channel==0
668 20:27:32.295235 RxClkDly_Margin_A0==88 ps 9
669 20:27:32.295634 TxDqDly_Margin_A0==98 ps 10
670 20:27:32.296442 RxClkDly_Margin_A1==88 ps 9
671 20:27:32.296877 TxDqDly_Margin_A1==98 ps 10
672 20:27:32.301977 TrainedVREFDQ_A0==74
673 20:27:32.302455 TrainedVREFDQ_A1==74
674 20:27:32.302880 VrefDac_Margin_A0==25
675 20:27:32.307598 DeviceVref_Margin_A0==40
676 20:27:32.308291 VrefDac_Margin_A1==25
677 20:27:32.308718 DeviceVref_Margin_A1==40
678 20:27:32.313203
679 20:27:32.313703
680 20:27:32.314110 channel==1
681 20:27:32.314523 RxClkDly_Margin_A0==98 ps 10
682 20:27:32.318893 TxDqDly_Margin_A0==98 ps 10
683 20:27:32.319388 RxClkDly_Margin_A1==98 ps 10
684 20:27:32.324424 TxDqDly_Margin_A1==88 ps 9
685 20:27:32.324919 TrainedVREFDQ_A0==77
686 20:27:32.325313 TrainedVREFDQ_A1==77
687 20:27:32.329950 VrefDac_Margin_A0==22
688 20:27:32.330391 DeviceVref_Margin_A0==37
689 20:27:32.330798 VrefDac_Margin_A1==22
690 20:27:32.335591 DeviceVref_Margin_A1==37
691 20:27:32.336118
692 20:27:32.341135 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 20:27:32.341572
694 20:27:32.369157 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 20:27:32.369735 2D training succeed
696 20:27:32.380378 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 20:27:32.380873 auto size-- 65535DDR cs0 size: 2048MB
698 20:27:32.385962 DDR cs1 size: 2048MB
699 20:27:32.386435 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 20:27:32.386829 cs0 DataBus test pass
701 20:27:32.391570 cs1 DataBus test pass
702 20:27:32.392065 cs0 AddrBus test pass
703 20:27:32.397169 cs1 AddrBus test pass
704 20:27:32.397614
705 20:27:32.398006 100bdlr_step_size ps== 420
706 20:27:32.398398 result report
707 20:27:32.402819 boot times 0Enable ddr reg access
708 20:27:32.409433 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 20:27:32.422885 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 20:27:32.994960 0.0;M3 CHK:0;cm4_sp_mode 0
711 20:27:32.995581 MVN_1=0x00000000
712 20:27:33.000405 MVN_2=0x00000000
713 20:27:33.006168 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 20:27:33.006673 OPS=0x10
715 20:27:33.007097 ring efuse init
716 20:27:33.007505 chipver efuse init
717 20:27:33.011822 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 20:27:33.017359 [0.018961 Inits done]
719 20:27:33.017847 secure task start!
720 20:27:33.018234 high task start!
721 20:27:33.021914 low task start!
722 20:27:33.022371 run into bl31
723 20:27:33.028561 NOTICE: BL31: v1.3(release):4fc40b1
724 20:27:33.036386 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 20:27:33.036873 NOTICE: BL31: G12A normal boot!
726 20:27:33.061848 NOTICE: BL31: BL33 decompress pass
727 20:27:33.067408 ERROR: Error initializing runtime service opteed_fast
728 20:27:34.300384
729 20:27:34.301002
730 20:27:34.308671 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 20:27:34.309135
732 20:27:34.309548 Model: Libre Computer AML-A311D-CC Alta
733 20:27:34.517151 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 20:27:34.540460 DRAM: 2 GiB (effective 3.8 GiB)
735 20:27:34.683496 Core: 408 devices, 31 uclasses, devicetree: separate
736 20:27:34.689337 WDT: Not starting watchdog@f0d0
737 20:27:34.721629 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 20:27:34.734093 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 20:27:34.739072 ** Bad device specification mmc 0 **
740 20:27:34.749396 Card did not respond to voltage select! : -110
741 20:27:34.757073 ** Bad device specification mmc 0 **
742 20:27:34.757525 Couldn't find partition mmc 0
743 20:27:34.765369 Card did not respond to voltage select! : -110
744 20:27:34.770886 ** Bad device specification mmc 0 **
745 20:27:34.771330 Couldn't find partition mmc 0
746 20:27:34.775949 Error: could not access storage.
747 20:27:35.118414 Net: eth0: ethernet@ff3f0000
748 20:27:35.118972 starting USB...
749 20:27:35.370257 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 20:27:35.370853 Starting the controller
751 20:27:35.377189 USB XHCI 1.10
752 20:27:37.540231 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 20:27:37.540888 bl2_stage_init 0x01
754 20:27:37.541352 bl2_stage_init 0x81
755 20:27:37.545908 hw id: 0x0000 - pwm id 0x01
756 20:27:37.546423 bl2_stage_init 0xc1
757 20:27:37.546876 bl2_stage_init 0x02
758 20:27:37.547316
759 20:27:37.551523 L0:00000000
760 20:27:37.552060 L1:20000703
761 20:27:37.552513 L2:00008067
762 20:27:37.552951 L3:14000000
763 20:27:37.557121 B2:00402000
764 20:27:37.557622 B1:e0f83180
765 20:27:37.558072
766 20:27:37.558511 TE: 58124
767 20:27:37.558947
768 20:27:37.562627 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 20:27:37.563129
770 20:27:37.563578 Board ID = 1
771 20:27:37.568341 Set A53 clk to 24M
772 20:27:37.568842 Set A73 clk to 24M
773 20:27:37.569286 Set clk81 to 24M
774 20:27:37.573892 A53 clk: 1200 MHz
775 20:27:37.574386 A73 clk: 1200 MHz
776 20:27:37.574829 CLK81: 166.6M
777 20:27:37.575265 smccc: 00012a92
778 20:27:37.579540 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 20:27:37.585117 board id: 1
780 20:27:37.591141 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 20:27:37.601521 fw parse done
782 20:27:37.607460 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 20:27:37.650058 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 20:27:37.660995 PIEI prepare done
785 20:27:37.661498 fastboot data load
786 20:27:37.661943 fastboot data verify
787 20:27:37.666707 verify result: 266
788 20:27:37.672319 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 20:27:37.672821 LPDDR4 probe
790 20:27:37.673265 ddr clk to 1584MHz
791 20:27:37.680230 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 20:27:37.717523
793 20:27:37.718046 dmc_version 0001
794 20:27:37.724237 Check phy result
795 20:27:37.730079 INFO : End of CA training
796 20:27:37.730589 INFO : End of initialization
797 20:27:37.735659 INFO : Training has run successfully!
798 20:27:37.736198 Check phy result
799 20:27:37.741267 INFO : End of initialization
800 20:27:37.741761 INFO : End of read enable training
801 20:27:37.744602 INFO : End of fine write leveling
802 20:27:37.750179 INFO : End of Write leveling coarse delay
803 20:27:37.755762 INFO : Training has run successfully!
804 20:27:37.756292 Check phy result
805 20:27:37.756738 INFO : End of initialization
806 20:27:37.761364 INFO : End of read dq deskew training
807 20:27:37.766980 INFO : End of MPR read delay center optimization
808 20:27:37.767478 INFO : End of write delay center optimization
809 20:27:37.772569 INFO : End of read delay center optimization
810 20:27:37.778167 INFO : End of max read latency training
811 20:27:37.778663 INFO : Training has run successfully!
812 20:27:37.783792 1D training succeed
813 20:27:37.789668 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 20:27:37.837215 Check phy result
815 20:27:37.837731 INFO : End of initialization
816 20:27:37.858814 INFO : End of 2D read delay Voltage center optimization
817 20:27:37.878932 INFO : End of 2D read delay Voltage center optimization
818 20:27:37.930832 INFO : End of 2D write delay Voltage center optimization
819 20:27:37.980100 INFO : End of 2D write delay Voltage center optimization
820 20:27:37.985676 INFO : Training has run successfully!
821 20:27:37.986176
822 20:27:37.986626 channel==0
823 20:27:37.991251 RxClkDly_Margin_A0==88 ps 9
824 20:27:37.991746 TxDqDly_Margin_A0==98 ps 10
825 20:27:37.996831 RxClkDly_Margin_A1==88 ps 9
826 20:27:37.997328 TxDqDly_Margin_A1==98 ps 10
827 20:27:37.997789 TrainedVREFDQ_A0==74
828 20:27:38.002494 TrainedVREFDQ_A1==74
829 20:27:38.003022 VrefDac_Margin_A0==25
830 20:27:38.003467 DeviceVref_Margin_A0==40
831 20:27:38.008071 VrefDac_Margin_A1==26
832 20:27:38.008578 DeviceVref_Margin_A1==40
833 20:27:38.008999
834 20:27:38.009421
835 20:27:38.013670 channel==1
836 20:27:38.014154 RxClkDly_Margin_A0==98 ps 10
837 20:27:38.014579 TxDqDly_Margin_A0==88 ps 9
838 20:27:38.019237 RxClkDly_Margin_A1==88 ps 9
839 20:27:38.019718 TxDqDly_Margin_A1==88 ps 9
840 20:27:38.024840 TrainedVREFDQ_A0==76
841 20:27:38.025324 TrainedVREFDQ_A1==77
842 20:27:38.025751 VrefDac_Margin_A0==22
843 20:27:38.030421 DeviceVref_Margin_A0==38
844 20:27:38.030902 VrefDac_Margin_A1==24
845 20:27:38.036110 DeviceVref_Margin_A1==37
846 20:27:38.036597
847 20:27:38.037022 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 20:27:38.037445
849 20:27:38.069624 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
850 20:27:38.070163 2D training succeed
851 20:27:38.075223 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 20:27:38.080877 auto size-- 65535DDR cs0 size: 2048MB
853 20:27:38.081360 DDR cs1 size: 2048MB
854 20:27:38.086461 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 20:27:38.086946 cs0 DataBus test pass
856 20:27:38.092093 cs1 DataBus test pass
857 20:27:38.092577 cs0 AddrBus test pass
858 20:27:38.093003 cs1 AddrBus test pass
859 20:27:38.093421
860 20:27:38.097705 100bdlr_step_size ps== 420
861 20:27:38.098197 result report
862 20:27:38.103214 boot times 0Enable ddr reg access
863 20:27:38.108493 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 20:27:38.121909 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 20:27:38.694003 0.0;M3 CHK:0;cm4_sp_mode 0
866 20:27:38.694651 MVN_1=0x00000000
867 20:27:38.699452 MVN_2=0x00000000
868 20:27:38.705196 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 20:27:38.705735 OPS=0x10
870 20:27:38.706188 ring efuse init
871 20:27:38.706623 chipver efuse init
872 20:27:38.710779 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 20:27:38.716371 [0.018961 Inits done]
874 20:27:38.716884 secure task start!
875 20:27:38.717324 high task start!
876 20:27:38.720992 low task start!
877 20:27:38.721510 run into bl31
878 20:27:38.727648 NOTICE: BL31: v1.3(release):4fc40b1
879 20:27:38.735446 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 20:27:38.736005 NOTICE: BL31: G12A normal boot!
881 20:27:38.760828 NOTICE: BL31: BL33 decompress pass
882 20:27:38.766503 ERROR: Error initializing runtime service opteed_fast
883 20:27:39.999262
884 20:27:39.999858
885 20:27:40.006838 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 20:27:40.007342
887 20:27:40.007787 Model: Libre Computer AML-A311D-CC Alta
888 20:27:40.216185 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 20:27:40.239569 DRAM: 2 GiB (effective 3.8 GiB)
890 20:27:40.382569 Core: 408 devices, 31 uclasses, devicetree: separate
891 20:27:40.388445 WDT: Not starting watchdog@f0d0
892 20:27:40.420676 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 20:27:40.433084 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 20:27:40.438103 ** Bad device specification mmc 0 **
895 20:27:40.448472 Card did not respond to voltage select! : -110
896 20:27:40.456115 ** Bad device specification mmc 0 **
897 20:27:40.456613 Couldn't find partition mmc 0
898 20:27:40.464458 Card did not respond to voltage select! : -110
899 20:27:40.469985 ** Bad device specification mmc 0 **
900 20:27:40.470488 Couldn't find partition mmc 0
901 20:27:40.475029 Error: could not access storage.
902 20:27:40.817567 Net: eth0: ethernet@ff3f0000
903 20:27:40.818180 starting USB...
904 20:27:41.070458 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 20:27:41.071116 Starting the controller
906 20:27:41.077372 USB XHCI 1.10
907 20:27:42.880194 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 20:27:42.880838 bl2_stage_init 0x01
909 20:27:42.881299 bl2_stage_init 0x81
910 20:27:42.885831 hw id: 0x0000 - pwm id 0x01
911 20:27:42.886340 bl2_stage_init 0xc1
912 20:27:42.886795 bl2_stage_init 0x02
913 20:27:42.887238
914 20:27:42.891438 L0:00000000
915 20:27:42.891934 L1:20000703
916 20:27:42.892428 L2:00008067
917 20:27:42.892871 L3:14000000
918 20:27:42.897000 B2:00402000
919 20:27:42.897494 B1:e0f83180
920 20:27:42.897940
921 20:27:42.898380 TE: 58167
922 20:27:42.898816
923 20:27:42.902714 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 20:27:42.903216
925 20:27:42.903663 Board ID = 1
926 20:27:42.908276 Set A53 clk to 24M
927 20:27:42.908773 Set A73 clk to 24M
928 20:27:42.909217 Set clk81 to 24M
929 20:27:42.913801 A53 clk: 1200 MHz
930 20:27:42.914290 A73 clk: 1200 MHz
931 20:27:42.914731 CLK81: 166.6M
932 20:27:42.915165 smccc: 00012abe
933 20:27:42.919467 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 20:27:42.924977 board id: 1
935 20:27:42.930813 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 20:27:42.941551 fw parse done
937 20:27:42.947556 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 20:27:42.989928 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 20:27:43.000843 PIEI prepare done
940 20:27:43.001339 fastboot data load
941 20:27:43.001803 fastboot data verify
942 20:27:43.006585 verify result: 266
943 20:27:43.012144 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 20:27:43.012661 LPDDR4 probe
945 20:27:43.013086 ddr clk to 1584MHz
946 20:27:43.020111 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 20:27:43.057381
948 20:27:43.057881 dmc_version 0001
949 20:27:43.064056 Check phy result
950 20:27:43.069923 INFO : End of CA training
951 20:27:43.070406 INFO : End of initialization
952 20:27:43.075502 INFO : Training has run successfully!
953 20:27:43.076010 Check phy result
954 20:27:43.081103 INFO : End of initialization
955 20:27:43.081581 INFO : End of read enable training
956 20:27:43.086702 INFO : End of fine write leveling
957 20:27:43.092296 INFO : End of Write leveling coarse delay
958 20:27:43.092781 INFO : Training has run successfully!
959 20:27:43.093204 Check phy result
960 20:27:43.097915 INFO : End of initialization
961 20:27:43.098398 INFO : End of read dq deskew training
962 20:27:43.103499 INFO : End of MPR read delay center optimization
963 20:27:43.109100 INFO : End of write delay center optimization
964 20:27:43.114725 INFO : End of read delay center optimization
965 20:27:43.115200 INFO : End of max read latency training
966 20:27:43.120283 INFO : Training has run successfully!
967 20:27:43.120759 1D training succeed
968 20:27:43.129457 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 20:27:43.177106 Check phy result
970 20:27:43.177643 INFO : End of initialization
971 20:27:43.198711 INFO : End of 2D read delay Voltage center optimization
972 20:27:43.218837 INFO : End of 2D read delay Voltage center optimization
973 20:27:43.270734 INFO : End of 2D write delay Voltage center optimization
974 20:27:43.319977 INFO : End of 2D write delay Voltage center optimization
975 20:27:43.325560 INFO : Training has run successfully!
976 20:27:43.326057
977 20:27:43.326509 channel==0
978 20:27:43.331149 RxClkDly_Margin_A0==88 ps 9
979 20:27:43.331640 TxDqDly_Margin_A0==98 ps 10
980 20:27:43.336753 RxClkDly_Margin_A1==88 ps 9
981 20:27:43.337244 TxDqDly_Margin_A1==98 ps 10
982 20:27:43.337691 TrainedVREFDQ_A0==74
983 20:27:43.342354 TrainedVREFDQ_A1==74
984 20:27:43.342847 VrefDac_Margin_A0==25
985 20:27:43.343290 DeviceVref_Margin_A0==40
986 20:27:43.347938 VrefDac_Margin_A1==25
987 20:27:43.348456 DeviceVref_Margin_A1==40
988 20:27:43.348900
989 20:27:43.349341
990 20:27:43.353553 channel==1
991 20:27:43.354062 RxClkDly_Margin_A0==98 ps 10
992 20:27:43.354507 TxDqDly_Margin_A0==88 ps 9
993 20:27:43.359163 RxClkDly_Margin_A1==98 ps 10
994 20:27:43.359657 TxDqDly_Margin_A1==88 ps 9
995 20:27:43.364753 TrainedVREFDQ_A0==76
996 20:27:43.365253 TrainedVREFDQ_A1==77
997 20:27:43.365698 VrefDac_Margin_A0==22
998 20:27:43.370361 DeviceVref_Margin_A0==38
999 20:27:43.370859 VrefDac_Margin_A1==22
1000 20:27:43.376004 DeviceVref_Margin_A1==37
1001 20:27:43.376509
1002 20:27:43.376955 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 20:27:43.377395
1004 20:27:43.409512 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1005 20:27:43.410103 2D training succeed
1006 20:27:43.415159 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 20:27:43.420741 auto size-- 65535DDR cs0 size: 2048MB
1008 20:27:43.421255 DDR cs1 size: 2048MB
1009 20:27:43.426350 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 20:27:43.426855 cs0 DataBus test pass
1011 20:27:43.431932 cs1 DataBus test pass
1012 20:27:43.432469 cs0 AddrBus test pass
1013 20:27:43.432914 cs1 AddrBus test pass
1014 20:27:43.433352
1015 20:27:43.437533 100bdlr_step_size ps== 420
1016 20:27:43.438051 result report
1017 20:27:43.443156 boot times 0Enable ddr reg access
1018 20:27:43.448509 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 20:27:43.461917 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 20:27:44.033859 0.0;M3 CHK:0;cm4_sp_mode 0
1021 20:27:44.034499 MVN_1=0x00000000
1022 20:27:44.039461 MVN_2=0x00000000
1023 20:27:44.045204 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 20:27:44.045732 OPS=0x10
1025 20:27:44.046189 ring efuse init
1026 20:27:44.046633 chipver efuse init
1027 20:27:44.050800 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 20:27:44.056417 [0.018960 Inits done]
1029 20:27:44.056926 secure task start!
1030 20:27:44.057374 high task start!
1031 20:27:44.060963 low task start!
1032 20:27:44.061463 run into bl31
1033 20:27:44.067580 NOTICE: BL31: v1.3(release):4fc40b1
1034 20:27:44.074589 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 20:27:44.075106 NOTICE: BL31: G12A normal boot!
1036 20:27:44.100762 NOTICE: BL31: BL33 decompress pass
1037 20:27:44.105515 ERROR: Error initializing runtime service opteed_fast
1038 20:27:45.339315
1039 20:27:45.339963
1040 20:27:45.347730 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 20:27:45.348294
1042 20:27:45.348751 Model: Libre Computer AML-A311D-CC Alta
1043 20:27:45.556121 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 20:27:45.579486 DRAM: 2 GiB (effective 3.8 GiB)
1045 20:27:45.722466 Core: 408 devices, 31 uclasses, devicetree: separate
1046 20:27:45.728380 WDT: Not starting watchdog@f0d0
1047 20:27:45.760644 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 20:27:45.773047 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 20:27:45.778050 ** Bad device specification mmc 0 **
1050 20:27:45.788403 Card did not respond to voltage select! : -110
1051 20:27:45.796079 ** Bad device specification mmc 0 **
1052 20:27:45.796609 Couldn't find partition mmc 0
1053 20:27:45.804375 Card did not respond to voltage select! : -110
1054 20:27:45.809887 ** Bad device specification mmc 0 **
1055 20:27:45.810387 Couldn't find partition mmc 0
1056 20:27:45.814935 Error: could not access storage.
1057 20:27:46.157373 Net: eth0: ethernet@ff3f0000
1058 20:27:46.157967 starting USB...
1059 20:27:46.409233 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 20:27:46.409834 Starting the controller
1061 20:27:46.416222 USB XHCI 1.10
1062 20:27:47.972443 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 20:27:47.980767 scanning usb for storage devices... 0 Storage Device(s) found
1065 20:27:48.032421 Hit any key to stop autoboot: 1
1066 20:27:48.033507 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1067 20:27:48.034202 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1068 20:27:48.034729 Setting prompt string to ['=>']
1069 20:27:48.035241 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1070 20:27:48.048325 0
1071 20:27:48.049340 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 20:27:48.049865 Sending with 10 millisecond of delay
1074 20:27:49.184786 => setenv autoload no
1075 20:27:49.195697 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1076 20:27:49.198309 setenv autoload no
1077 20:27:49.198846 Sending with 10 millisecond of delay
1079 20:27:50.996666 => setenv initrd_high 0xffffffff
1080 20:27:51.007343 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1081 20:27:51.008092 setenv initrd_high 0xffffffff
1082 20:27:51.008617 Sending with 10 millisecond of delay
1084 20:27:52.637640 => setenv fdt_high 0xffffffff
1085 20:27:52.648561 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1086 20:27:52.649605 setenv fdt_high 0xffffffff
1087 20:27:52.650387 Sending with 10 millisecond of delay
1089 20:27:52.942865 => dhcp
1090 20:27:52.953449 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1091 20:27:52.954049 dhcp
1092 20:27:52.954306 Speed: 1000, full duplex
1093 20:27:52.954533 BOOTP broadcast 1
1094 20:27:52.961833 DHCP client bound to address 192.168.6.27 (8 ms)
1095 20:27:52.962372 Sending with 10 millisecond of delay
1097 20:27:54.638652 => setenv serverip 192.168.6.2
1098 20:27:54.649225 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1099 20:27:54.649809 setenv serverip 192.168.6.2
1100 20:27:54.650291 Sending with 10 millisecond of delay
1102 20:27:58.373471 => tftpboot 0x01080000 948787/tftp-deploy-95vtvp9a/kernel/uImage
1103 20:27:58.384282 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 20:27:58.385178 tftpboot 0x01080000 948787/tftp-deploy-95vtvp9a/kernel/uImage
1105 20:27:58.385663 Speed: 1000, full duplex
1106 20:27:58.386135 Using ethernet@ff3f0000 device
1107 20:27:58.386984 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 20:27:58.392378 Filename '948787/tftp-deploy-95vtvp9a/kernel/uImage'.
1109 20:27:58.395506 Load address: 0x1080000
1110 20:28:00.812937 Loading: *################################################## 37.6 MiB
1111 20:28:00.813586 15.5 MiB/s
1112 20:28:00.814060 done
1113 20:28:00.817399 Bytes transferred = 39424576 (2599240 hex)
1114 20:28:00.818230 Sending with 10 millisecond of delay
1116 20:28:05.505303 => tftpboot 0x08000000 948787/tftp-deploy-95vtvp9a/ramdisk/ramdisk.cpio.gz.uboot
1117 20:28:05.516124 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1118 20:28:05.516984 tftpboot 0x08000000 948787/tftp-deploy-95vtvp9a/ramdisk/ramdisk.cpio.gz.uboot
1119 20:28:05.517477 Speed: 1000, full duplex
1120 20:28:05.517924 Using ethernet@ff3f0000 device
1121 20:28:05.518766 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1122 20:28:05.530576 Filename '948787/tftp-deploy-95vtvp9a/ramdisk/ramdisk.cpio.gz.uboot'.
1123 20:28:05.531115 Load address: 0x8000000
1124 20:28:12.508277 Loading: *####T ############################################# UDP wrong checksum 00000005 0000ede7
1125 20:28:17.510408 T UDP wrong checksum 00000005 0000ede7
1126 20:28:22.156461 UDP wrong checksum 000000ff 00003573
1127 20:28:22.164350 UDP wrong checksum 000000ff 0000c365
1128 20:28:27.514611 T T UDP wrong checksum 00000005 0000ede7
1129 20:28:47.517541 T T T T UDP wrong checksum 00000005 0000ede7
1130 20:29:02.521736 T T
1131 20:29:02.522410 Retry count exceeded; starting again
1133 20:29:02.523934 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1136 20:29:02.526027 end: 2.4 uboot-commands (duration 00:01:52) [common]
1138 20:29:02.527723 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1140 20:29:02.528887 end: 2 uboot-action (duration 00:01:52) [common]
1142 20:29:02.530525 Cleaning after the job
1143 20:29:02.531113 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948787/tftp-deploy-95vtvp9a/ramdisk
1144 20:29:02.532728 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948787/tftp-deploy-95vtvp9a/kernel
1145 20:29:02.557685 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948787/tftp-deploy-95vtvp9a/dtb
1146 20:29:02.558973 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948787/tftp-deploy-95vtvp9a/modules
1147 20:29:02.565766 start: 4.1 power-off (timeout 00:00:30) [common]
1148 20:29:02.566862 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1149 20:29:02.603405 >> OK - accepted request
1150 20:29:02.605466 Returned 0 in 0 seconds
1151 20:29:02.706333 end: 4.1 power-off (duration 00:00:00) [common]
1153 20:29:02.708144 start: 4.2 read-feedback (timeout 00:10:00) [common]
1154 20:29:02.709370 Listened to connection for namespace 'common' for up to 1s
1155 20:29:03.709130 Finalising connection for namespace 'common'
1156 20:29:03.709886 Disconnecting from shell: Finalise
1157 20:29:03.710442 =>
1158 20:29:03.811529 end: 4.2 read-feedback (duration 00:00:01) [common]
1159 20:29:03.812331 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/948787
1160 20:29:04.084990 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/948787
1161 20:29:04.085602 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.