Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:39:32.373213 lava-dispatcher, installed at version: 2024.01
2 20:39:32.374011 start: 0 validate
3 20:39:32.374504 Start time: 2024-11-06 20:39:32.374472+00:00 (UTC)
4 20:39:32.375060 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:39:32.375599 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 20:39:32.421332 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:39:32.421900 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fkernel%2FImage exists
8 20:39:32.452287 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:39:32.452925 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 20:39:32.484523 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:39:32.485051 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 20:39:32.514290 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 20:39:32.515072 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fmodules.tar.xz exists
14 20:39:32.557223 validate duration: 0.18
16 20:39:32.558098 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:39:32.558442 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:39:32.558777 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:39:32.559410 Not decompressing ramdisk as can be used compressed.
20 20:39:32.560292 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 20:39:32.560869 saving as /var/lib/lava/dispatcher/tmp/948797/tftp-deploy-4s93p3h0/ramdisk/initrd.cpio.gz
22 20:39:32.561400 total size: 5628182 (5 MB)
23 20:39:32.604773 progress 0 % (0 MB)
24 20:39:32.610545 progress 5 % (0 MB)
25 20:39:32.618454 progress 10 % (0 MB)
26 20:39:32.625387 progress 15 % (0 MB)
27 20:39:32.633042 progress 20 % (1 MB)
28 20:39:32.638123 progress 25 % (1 MB)
29 20:39:32.642082 progress 30 % (1 MB)
30 20:39:32.646010 progress 35 % (1 MB)
31 20:39:32.649747 progress 40 % (2 MB)
32 20:39:32.653705 progress 45 % (2 MB)
33 20:39:32.657293 progress 50 % (2 MB)
34 20:39:32.661318 progress 55 % (2 MB)
35 20:39:32.665289 progress 60 % (3 MB)
36 20:39:32.668872 progress 65 % (3 MB)
37 20:39:32.672853 progress 70 % (3 MB)
38 20:39:32.676436 progress 75 % (4 MB)
39 20:39:32.680602 progress 80 % (4 MB)
40 20:39:32.684162 progress 85 % (4 MB)
41 20:39:32.688108 progress 90 % (4 MB)
42 20:39:32.691879 progress 95 % (5 MB)
43 20:39:32.695108 progress 100 % (5 MB)
44 20:39:32.695747 5 MB downloaded in 0.13 s (39.95 MB/s)
45 20:39:32.696325 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:39:32.697217 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:39:32.697508 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:39:32.697776 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:39:32.698241 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/kernel/Image
51 20:39:32.698509 saving as /var/lib/lava/dispatcher/tmp/948797/tftp-deploy-4s93p3h0/kernel/Image
52 20:39:32.698720 total size: 39424512 (37 MB)
53 20:39:32.698928 No compression specified
54 20:39:32.737245 progress 0 % (0 MB)
55 20:39:32.762844 progress 5 % (1 MB)
56 20:39:32.788512 progress 10 % (3 MB)
57 20:39:32.813741 progress 15 % (5 MB)
58 20:39:32.839010 progress 20 % (7 MB)
59 20:39:32.864374 progress 25 % (9 MB)
60 20:39:32.890147 progress 30 % (11 MB)
61 20:39:32.915933 progress 35 % (13 MB)
62 20:39:32.941329 progress 40 % (15 MB)
63 20:39:32.966520 progress 45 % (16 MB)
64 20:39:32.992084 progress 50 % (18 MB)
65 20:39:33.017295 progress 55 % (20 MB)
66 20:39:33.042322 progress 60 % (22 MB)
67 20:39:33.068116 progress 65 % (24 MB)
68 20:39:33.093934 progress 70 % (26 MB)
69 20:39:33.118973 progress 75 % (28 MB)
70 20:39:33.144304 progress 80 % (30 MB)
71 20:39:33.169582 progress 85 % (31 MB)
72 20:39:33.194972 progress 90 % (33 MB)
73 20:39:33.220606 progress 95 % (35 MB)
74 20:39:33.245630 progress 100 % (37 MB)
75 20:39:33.246152 37 MB downloaded in 0.55 s (68.68 MB/s)
76 20:39:33.246627 end: 1.2.1 http-download (duration 00:00:01) [common]
78 20:39:33.247489 end: 1.2 download-retry (duration 00:00:01) [common]
79 20:39:33.247768 start: 1.3 download-retry (timeout 00:09:59) [common]
80 20:39:33.248067 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 20:39:33.248546 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 20:39:33.248794 saving as /var/lib/lava/dispatcher/tmp/948797/tftp-deploy-4s93p3h0/dtb/meson-g12b-a311d-libretech-cc.dtb
83 20:39:33.249001 total size: 54703 (0 MB)
84 20:39:33.249210 No compression specified
85 20:39:33.293139 progress 59 % (0 MB)
86 20:39:33.293964 progress 100 % (0 MB)
87 20:39:33.294505 0 MB downloaded in 0.05 s (1.15 MB/s)
88 20:39:33.294961 end: 1.3.1 http-download (duration 00:00:00) [common]
90 20:39:33.295776 end: 1.3 download-retry (duration 00:00:00) [common]
91 20:39:33.296068 start: 1.4 download-retry (timeout 00:09:59) [common]
92 20:39:33.296341 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 20:39:33.296790 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 20:39:33.297030 saving as /var/lib/lava/dispatcher/tmp/948797/tftp-deploy-4s93p3h0/nfsrootfs/full.rootfs.tar
95 20:39:33.297234 total size: 107552908 (102 MB)
96 20:39:33.297441 Using unxz to decompress xz
97 20:39:33.334536 progress 0 % (0 MB)
98 20:39:34.026396 progress 5 % (5 MB)
99 20:39:34.738639 progress 10 % (10 MB)
100 20:39:35.446732 progress 15 % (15 MB)
101 20:39:36.188055 progress 20 % (20 MB)
102 20:39:36.751011 progress 25 % (25 MB)
103 20:39:37.364131 progress 30 % (30 MB)
104 20:39:38.088770 progress 35 % (35 MB)
105 20:39:38.446478 progress 40 % (41 MB)
106 20:39:38.867215 progress 45 % (46 MB)
107 20:39:39.548851 progress 50 % (51 MB)
108 20:39:40.227270 progress 55 % (56 MB)
109 20:39:40.978964 progress 60 % (61 MB)
110 20:39:41.729352 progress 65 % (66 MB)
111 20:39:42.458859 progress 70 % (71 MB)
112 20:39:43.224152 progress 75 % (76 MB)
113 20:39:43.898247 progress 80 % (82 MB)
114 20:39:44.595676 progress 85 % (87 MB)
115 20:39:45.317507 progress 90 % (92 MB)
116 20:39:46.017342 progress 95 % (97 MB)
117 20:39:46.751665 progress 100 % (102 MB)
118 20:39:46.764350 102 MB downloaded in 13.47 s (7.62 MB/s)
119 20:39:46.765095 end: 1.4.1 http-download (duration 00:00:13) [common]
121 20:39:46.766929 end: 1.4 download-retry (duration 00:00:13) [common]
122 20:39:46.767519 start: 1.5 download-retry (timeout 00:09:46) [common]
123 20:39:46.768141 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 20:39:46.769279 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/modules.tar.xz
125 20:39:46.769820 saving as /var/lib/lava/dispatcher/tmp/948797/tftp-deploy-4s93p3h0/modules/modules.tar
126 20:39:46.770287 total size: 11755752 (11 MB)
127 20:39:46.770757 Using unxz to decompress xz
128 20:39:46.819326 progress 0 % (0 MB)
129 20:39:46.887005 progress 5 % (0 MB)
130 20:39:46.962087 progress 10 % (1 MB)
131 20:39:47.059337 progress 15 % (1 MB)
132 20:39:47.155357 progress 20 % (2 MB)
133 20:39:47.234535 progress 25 % (2 MB)
134 20:39:47.312618 progress 30 % (3 MB)
135 20:39:47.391974 progress 35 % (3 MB)
136 20:39:47.471386 progress 40 % (4 MB)
137 20:39:47.546980 progress 45 % (5 MB)
138 20:39:47.632853 progress 50 % (5 MB)
139 20:39:47.714553 progress 55 % (6 MB)
140 20:39:47.799459 progress 60 % (6 MB)
141 20:39:47.880997 progress 65 % (7 MB)
142 20:39:47.965152 progress 70 % (7 MB)
143 20:39:48.051136 progress 75 % (8 MB)
144 20:39:48.134581 progress 80 % (9 MB)
145 20:39:48.211692 progress 85 % (9 MB)
146 20:39:48.295509 progress 90 % (10 MB)
147 20:39:48.374288 progress 95 % (10 MB)
148 20:39:48.451882 progress 100 % (11 MB)
149 20:39:48.465487 11 MB downloaded in 1.70 s (6.61 MB/s)
150 20:39:48.466239 end: 1.5.1 http-download (duration 00:00:02) [common]
152 20:39:48.467938 end: 1.5 download-retry (duration 00:00:02) [common]
153 20:39:48.468535 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 20:39:48.469081 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 20:39:58.226315 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/948797/extract-nfsrootfs-ttsyyh76
156 20:39:58.226924 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 20:39:58.227220 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 20:39:58.227933 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv
159 20:39:58.228433 makedir: /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin
160 20:39:58.228783 makedir: /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/tests
161 20:39:58.229105 makedir: /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/results
162 20:39:58.229448 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-add-keys
163 20:39:58.230002 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-add-sources
164 20:39:58.230522 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-background-process-start
165 20:39:58.231027 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-background-process-stop
166 20:39:58.231562 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-common-functions
167 20:39:58.232084 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-echo-ipv4
168 20:39:58.232588 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-install-packages
169 20:39:58.233086 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-installed-packages
170 20:39:58.233571 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-os-build
171 20:39:58.234059 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-probe-channel
172 20:39:58.234547 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-probe-ip
173 20:39:58.235054 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-target-ip
174 20:39:58.235569 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-target-mac
175 20:39:58.236084 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-target-storage
176 20:39:58.236600 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-test-case
177 20:39:58.237094 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-test-event
178 20:39:58.237579 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-test-feedback
179 20:39:58.238066 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-test-raise
180 20:39:58.238556 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-test-reference
181 20:39:58.239065 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-test-runner
182 20:39:58.239582 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-test-set
183 20:39:58.240106 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-test-shell
184 20:39:58.240613 Updating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-install-packages (oe)
185 20:39:58.241157 Updating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/bin/lava-installed-packages (oe)
186 20:39:58.241664 Creating /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/environment
187 20:39:58.242054 LAVA metadata
188 20:39:58.242319 - LAVA_JOB_ID=948797
189 20:39:58.242538 - LAVA_DISPATCHER_IP=192.168.6.2
190 20:39:58.242890 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 20:39:58.243824 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 20:39:58.244170 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 20:39:58.244382 skipped lava-vland-overlay
194 20:39:58.244626 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 20:39:58.244881 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 20:39:58.245099 skipped lava-multinode-overlay
197 20:39:58.245342 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 20:39:58.245594 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 20:39:58.245843 Loading test definitions
200 20:39:58.246120 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 20:39:58.246347 Using /lava-948797 at stage 0
202 20:39:58.247536 uuid=948797_1.6.2.4.1 testdef=None
203 20:39:58.247851 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 20:39:58.248145 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 20:39:58.249948 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 20:39:58.250773 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 20:39:58.253068 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 20:39:58.253905 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 20:39:58.256077 runner path: /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/0/tests/0_dmesg test_uuid 948797_1.6.2.4.1
212 20:39:58.256637 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 20:39:58.257401 Creating lava-test-runner.conf files
215 20:39:58.257603 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/948797/lava-overlay-lhposmsv/lava-948797/0 for stage 0
216 20:39:58.257938 - 0_dmesg
217 20:39:58.258280 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 20:39:58.258559 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 20:39:58.280219 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 20:39:58.280573 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 20:39:58.280836 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 20:39:58.281102 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 20:39:58.281368 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 20:39:58.888988 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 20:39:58.889467 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
226 20:39:58.889750 extracting modules file /var/lib/lava/dispatcher/tmp/948797/tftp-deploy-4s93p3h0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/948797/extract-nfsrootfs-ttsyyh76
227 20:40:00.264667 extracting modules file /var/lib/lava/dispatcher/tmp/948797/tftp-deploy-4s93p3h0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/948797/extract-overlay-ramdisk-woo58cd3/ramdisk
228 20:40:01.670508 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 20:40:01.670991 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
230 20:40:01.671270 [common] Applying overlay to NFS
231 20:40:01.671482 [common] Applying overlay /var/lib/lava/dispatcher/tmp/948797/compress-overlay-m8t8uyc0/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/948797/extract-nfsrootfs-ttsyyh76
232 20:40:01.700974 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 20:40:01.701338 start: 1.6.6 prepare-kernel (timeout 00:09:31) [common]
234 20:40:01.701632 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:31) [common]
235 20:40:01.701865 Converting downloaded kernel to a uImage
236 20:40:01.702162 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/948797/tftp-deploy-4s93p3h0/kernel/Image /var/lib/lava/dispatcher/tmp/948797/tftp-deploy-4s93p3h0/kernel/uImage
237 20:40:02.113482 output: Image Name:
238 20:40:02.113914 output: Created: Wed Nov 6 20:40:01 2024
239 20:40:02.114126 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 20:40:02.114331 output: Data Size: 39424512 Bytes = 38500.50 KiB = 37.60 MiB
241 20:40:02.114532 output: Load Address: 01080000
242 20:40:02.114733 output: Entry Point: 01080000
243 20:40:02.114932 output:
244 20:40:02.115268 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 20:40:02.115530 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 20:40:02.115795 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 20:40:02.116090 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 20:40:02.116358 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 20:40:02.116617 Building ramdisk /var/lib/lava/dispatcher/tmp/948797/extract-overlay-ramdisk-woo58cd3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/948797/extract-overlay-ramdisk-woo58cd3/ramdisk
250 20:40:04.301544 >> 173477 blocks
251 20:40:12.114919 Adding RAMdisk u-boot header.
252 20:40:12.115629 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/948797/extract-overlay-ramdisk-woo58cd3/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/948797/extract-overlay-ramdisk-woo58cd3/ramdisk.cpio.gz.uboot
253 20:40:12.409633 output: Image Name:
254 20:40:12.410058 output: Created: Wed Nov 6 20:40:12 2024
255 20:40:12.410274 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 20:40:12.410480 output: Data Size: 24139855 Bytes = 23574.08 KiB = 23.02 MiB
257 20:40:12.410681 output: Load Address: 00000000
258 20:40:12.410878 output: Entry Point: 00000000
259 20:40:12.411073 output:
260 20:40:12.411729 rename /var/lib/lava/dispatcher/tmp/948797/extract-overlay-ramdisk-woo58cd3/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/948797/tftp-deploy-4s93p3h0/ramdisk/ramdisk.cpio.gz.uboot
261 20:40:12.412329 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 20:40:12.412888 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
263 20:40:12.413429 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
264 20:40:12.413890 No LXC device requested
265 20:40:12.414384 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 20:40:12.414891 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
267 20:40:12.415377 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 20:40:12.415782 Checking files for TFTP limit of 4294967296 bytes.
269 20:40:12.418454 end: 1 tftp-deploy (duration 00:00:40) [common]
270 20:40:12.419023 start: 2 uboot-action (timeout 00:05:00) [common]
271 20:40:12.419546 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 20:40:12.420084 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 20:40:12.420595 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 20:40:12.421115 Using kernel file from prepare-kernel: 948797/tftp-deploy-4s93p3h0/kernel/uImage
275 20:40:12.421736 substitutions:
276 20:40:12.422136 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 20:40:12.422537 - {DTB_ADDR}: 0x01070000
278 20:40:12.422932 - {DTB}: 948797/tftp-deploy-4s93p3h0/dtb/meson-g12b-a311d-libretech-cc.dtb
279 20:40:12.423328 - {INITRD}: 948797/tftp-deploy-4s93p3h0/ramdisk/ramdisk.cpio.gz.uboot
280 20:40:12.423721 - {KERNEL_ADDR}: 0x01080000
281 20:40:12.424139 - {KERNEL}: 948797/tftp-deploy-4s93p3h0/kernel/uImage
282 20:40:12.424532 - {LAVA_MAC}: None
283 20:40:12.424960 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/948797/extract-nfsrootfs-ttsyyh76
284 20:40:12.425360 - {NFS_SERVER_IP}: 192.168.6.2
285 20:40:12.425750 - {PRESEED_CONFIG}: None
286 20:40:12.426139 - {PRESEED_LOCAL}: None
287 20:40:12.426525 - {RAMDISK_ADDR}: 0x08000000
288 20:40:12.426909 - {RAMDISK}: 948797/tftp-deploy-4s93p3h0/ramdisk/ramdisk.cpio.gz.uboot
289 20:40:12.427294 - {ROOT_PART}: None
290 20:40:12.427682 - {ROOT}: None
291 20:40:12.428090 - {SERVER_IP}: 192.168.6.2
292 20:40:12.428475 - {TEE_ADDR}: 0x83000000
293 20:40:12.428861 - {TEE}: None
294 20:40:12.429245 Parsed boot commands:
295 20:40:12.429617 - setenv autoload no
296 20:40:12.429998 - setenv initrd_high 0xffffffff
297 20:40:12.430379 - setenv fdt_high 0xffffffff
298 20:40:12.430759 - dhcp
299 20:40:12.431137 - setenv serverip 192.168.6.2
300 20:40:12.431519 - tftpboot 0x01080000 948797/tftp-deploy-4s93p3h0/kernel/uImage
301 20:40:12.431899 - tftpboot 0x08000000 948797/tftp-deploy-4s93p3h0/ramdisk/ramdisk.cpio.gz.uboot
302 20:40:12.432312 - tftpboot 0x01070000 948797/tftp-deploy-4s93p3h0/dtb/meson-g12b-a311d-libretech-cc.dtb
303 20:40:12.432696 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/948797/extract-nfsrootfs-ttsyyh76,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 20:40:12.433090 - bootm 0x01080000 0x08000000 0x01070000
305 20:40:12.433576 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 20:40:12.435041 start: 2.3 connect-device (timeout 00:05:00) [common]
308 20:40:12.435453 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 20:40:12.450110 Setting prompt string to ['lava-test: # ']
310 20:40:12.451593 end: 2.3 connect-device (duration 00:00:00) [common]
311 20:40:12.452255 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 20:40:12.452812 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 20:40:12.453364 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 20:40:12.454483 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 20:40:12.492825 >> OK - accepted request
316 20:40:12.495074 Returned 0 in 0 seconds
317 20:40:12.596179 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 20:40:12.597732 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 20:40:12.598291 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 20:40:12.598806 Setting prompt string to ['Hit any key to stop autoboot']
322 20:40:12.599261 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 20:40:12.600804 Trying 192.168.56.21...
324 20:40:12.601288 Connected to conserv1.
325 20:40:12.601702 Escape character is '^]'.
326 20:40:12.602114
327 20:40:12.602523 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 20:40:12.602934
329 20:40:24.475531 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 20:40:24.476205 bl2_stage_init 0x01
331 20:40:24.476622 bl2_stage_init 0x81
332 20:40:24.481087 hw id: 0x0000 - pwm id 0x01
333 20:40:24.481532 bl2_stage_init 0xc1
334 20:40:24.481927 bl2_stage_init 0x02
335 20:40:24.482316
336 20:40:24.486776 L0:00000000
337 20:40:24.487209 L1:20000703
338 20:40:24.487610 L2:00008067
339 20:40:24.488049 L3:14000000
340 20:40:24.489600 B2:00402000
341 20:40:24.490029 B1:e0f83180
342 20:40:24.490431
343 20:40:24.490820 TE: 58124
344 20:40:24.491209
345 20:40:24.500747 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 20:40:24.501173
347 20:40:24.501568 Board ID = 1
348 20:40:24.501956 Set A53 clk to 24M
349 20:40:24.502341 Set A73 clk to 24M
350 20:40:24.506328 Set clk81 to 24M
351 20:40:24.506741 A53 clk: 1200 MHz
352 20:40:24.507132 A73 clk: 1200 MHz
353 20:40:24.511933 CLK81: 166.6M
354 20:40:24.512379 smccc: 00012a91
355 20:40:24.517575 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 20:40:24.517996 board id: 1
357 20:40:24.526230 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 20:40:24.536813 fw parse done
359 20:40:24.542866 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 20:40:24.585276 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 20:40:24.596175 PIEI prepare done
362 20:40:24.596594 fastboot data load
363 20:40:24.596987 fastboot data verify
364 20:40:24.601825 verify result: 266
365 20:40:24.607428 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 20:40:24.607877 LPDDR4 probe
367 20:40:24.608326 ddr clk to 1584MHz
368 20:40:24.615405 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 20:40:24.652618
370 20:40:24.653043 dmc_version 0001
371 20:40:24.659319 Check phy result
372 20:40:24.665190 INFO : End of CA training
373 20:40:24.665605 INFO : End of initialization
374 20:40:24.670796 INFO : Training has run successfully!
375 20:40:24.671221 Check phy result
376 20:40:24.676394 INFO : End of initialization
377 20:40:24.676808 INFO : End of read enable training
378 20:40:24.681991 INFO : End of fine write leveling
379 20:40:24.687603 INFO : End of Write leveling coarse delay
380 20:40:24.688041 INFO : Training has run successfully!
381 20:40:24.688440 Check phy result
382 20:40:24.693185 INFO : End of initialization
383 20:40:24.693602 INFO : End of read dq deskew training
384 20:40:24.698794 INFO : End of MPR read delay center optimization
385 20:40:24.704398 INFO : End of write delay center optimization
386 20:40:24.709980 INFO : End of read delay center optimization
387 20:40:24.710407 INFO : End of max read latency training
388 20:40:24.715580 INFO : Training has run successfully!
389 20:40:24.716024 1D training succeed
390 20:40:24.724797 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 20:40:24.772356 Check phy result
392 20:40:24.772782 INFO : End of initialization
393 20:40:24.794797 INFO : End of 2D read delay Voltage center optimization
394 20:40:24.814916 INFO : End of 2D read delay Voltage center optimization
395 20:40:24.866808 INFO : End of 2D write delay Voltage center optimization
396 20:40:24.916067 INFO : End of 2D write delay Voltage center optimization
397 20:40:24.921628 INFO : Training has run successfully!
398 20:40:24.922043
399 20:40:24.922439 channel==0
400 20:40:24.927232 RxClkDly_Margin_A0==88 ps 9
401 20:40:24.927659 TxDqDly_Margin_A0==98 ps 10
402 20:40:24.932830 RxClkDly_Margin_A1==88 ps 9
403 20:40:24.933245 TxDqDly_Margin_A1==98 ps 10
404 20:40:24.933641 TrainedVREFDQ_A0==74
405 20:40:24.938421 TrainedVREFDQ_A1==74
406 20:40:24.938840 VrefDac_Margin_A0==24
407 20:40:24.939230 DeviceVref_Margin_A0==40
408 20:40:24.944024 VrefDac_Margin_A1==25
409 20:40:24.944440 DeviceVref_Margin_A1==40
410 20:40:24.944827
411 20:40:24.945215
412 20:40:24.949612 channel==1
413 20:40:24.950024 RxClkDly_Margin_A0==98 ps 10
414 20:40:24.950415 TxDqDly_Margin_A0==88 ps 9
415 20:40:24.955217 RxClkDly_Margin_A1==88 ps 9
416 20:40:24.955628 TxDqDly_Margin_A1==88 ps 9
417 20:40:24.960835 TrainedVREFDQ_A0==77
418 20:40:24.961251 TrainedVREFDQ_A1==77
419 20:40:24.961644 VrefDac_Margin_A0==22
420 20:40:24.966438 DeviceVref_Margin_A0==37
421 20:40:24.966849 VrefDac_Margin_A1==24
422 20:40:24.972054 DeviceVref_Margin_A1==37
423 20:40:24.972469
424 20:40:24.972860 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 20:40:24.973250
426 20:40:25.005641 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
427 20:40:25.006127 2D training succeed
428 20:40:25.011226 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 20:40:25.016827 auto size-- 65535DDR cs0 size: 2048MB
430 20:40:25.017241 DDR cs1 size: 2048MB
431 20:40:25.022430 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 20:40:25.022847 cs0 DataBus test pass
433 20:40:25.028053 cs1 DataBus test pass
434 20:40:25.028473 cs0 AddrBus test pass
435 20:40:25.028865 cs1 AddrBus test pass
436 20:40:25.029252
437 20:40:25.033640 100bdlr_step_size ps== 420
438 20:40:25.034065 result report
439 20:40:25.039247 boot times 0Enable ddr reg access
440 20:40:25.044505 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 20:40:25.057959 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 20:40:25.629851 0.0;M3 CHK:0;cm4_sp_mode 0
443 20:40:25.630296 MVN_1=0x00000000
444 20:40:25.635437 MVN_2=0x00000000
445 20:40:25.641200 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 20:40:25.641639 OPS=0x10
447 20:40:25.642051 ring efuse init
448 20:40:25.642464 chipver efuse init
449 20:40:25.646799 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 20:40:25.652405 [0.018961 Inits done]
451 20:40:25.652831 secure task start!
452 20:40:25.653233 high task start!
453 20:40:25.656957 low task start!
454 20:40:25.657382 run into bl31
455 20:40:25.663609 NOTICE: BL31: v1.3(release):4fc40b1
456 20:40:25.671420 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 20:40:25.671865 NOTICE: BL31: G12A normal boot!
458 20:40:25.696860 NOTICE: BL31: BL33 decompress pass
459 20:40:25.702566 ERROR: Error initializing runtime service opteed_fast
460 20:40:26.935550
461 20:40:26.936292
462 20:40:26.943920 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 20:40:26.944562
464 20:40:26.945047 Model: Libre Computer AML-A311D-CC Alta
465 20:40:27.152255 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 20:40:27.175659 DRAM: 2 GiB (effective 3.8 GiB)
467 20:40:27.318571 Core: 408 devices, 31 uclasses, devicetree: separate
468 20:40:27.324451 WDT: Not starting watchdog@f0d0
469 20:40:27.356695 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 20:40:27.369146 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 20:40:27.374148 ** Bad device specification mmc 0 **
472 20:40:27.384487 Card did not respond to voltage select! : -110
473 20:40:27.392164 ** Bad device specification mmc 0 **
474 20:40:27.392670 Couldn't find partition mmc 0
475 20:40:27.400488 Card did not respond to voltage select! : -110
476 20:40:27.405997 ** Bad device specification mmc 0 **
477 20:40:27.406501 Couldn't find partition mmc 0
478 20:40:27.411062 Error: could not access storage.
479 20:40:28.675906 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 20:40:28.676570 bl2_stage_init 0x01
481 20:40:28.677046 bl2_stage_init 0x81
482 20:40:28.681546 hw id: 0x0000 - pwm id 0x01
483 20:40:28.682059 bl2_stage_init 0xc1
484 20:40:28.682515 bl2_stage_init 0x02
485 20:40:28.682963
486 20:40:28.687119 L0:00000000
487 20:40:28.687621 L1:20000703
488 20:40:28.688115 L2:00008067
489 20:40:28.688565 L3:14000000
490 20:40:28.692768 B2:00402000
491 20:40:28.693284 B1:e0f83180
492 20:40:28.693745
493 20:40:28.694196 TE: 58124
494 20:40:28.694641
495 20:40:28.698318 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 20:40:28.698825
497 20:40:28.699280 Board ID = 1
498 20:40:28.703905 Set A53 clk to 24M
499 20:40:28.704437 Set A73 clk to 24M
500 20:40:28.704895 Set clk81 to 24M
501 20:40:28.709513 A53 clk: 1200 MHz
502 20:40:28.710016 A73 clk: 1200 MHz
503 20:40:28.710470 CLK81: 166.6M
504 20:40:28.710919 smccc: 00012a91
505 20:40:28.715083 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 20:40:28.720752 board id: 1
507 20:40:28.726581 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 20:40:28.737246 fw parse done
509 20:40:28.743209 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 20:40:28.785814 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 20:40:28.796772 PIEI prepare done
512 20:40:28.797274 fastboot data load
513 20:40:28.797736 fastboot data verify
514 20:40:28.802428 verify result: 266
515 20:40:28.808053 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 20:40:28.808559 LPDDR4 probe
517 20:40:28.809011 ddr clk to 1584MHz
518 20:40:28.816035 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 20:40:28.853248
520 20:40:28.853756 dmc_version 0001
521 20:40:28.859955 Check phy result
522 20:40:28.865864 INFO : End of CA training
523 20:40:28.866361 INFO : End of initialization
524 20:40:28.871400 INFO : Training has run successfully!
525 20:40:28.871899 Check phy result
526 20:40:28.877021 INFO : End of initialization
527 20:40:28.877517 INFO : End of read enable training
528 20:40:28.882608 INFO : End of fine write leveling
529 20:40:28.888247 INFO : End of Write leveling coarse delay
530 20:40:28.888751 INFO : Training has run successfully!
531 20:40:28.889207 Check phy result
532 20:40:28.893895 INFO : End of initialization
533 20:40:28.894390 INFO : End of read dq deskew training
534 20:40:28.899412 INFO : End of MPR read delay center optimization
535 20:40:28.905000 INFO : End of write delay center optimization
536 20:40:28.910620 INFO : End of read delay center optimization
537 20:40:28.911138 INFO : End of max read latency training
538 20:40:28.916249 INFO : Training has run successfully!
539 20:40:28.916749 1D training succeed
540 20:40:28.925338 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 20:40:28.972979 Check phy result
542 20:40:28.973486 INFO : End of initialization
543 20:40:28.995588 INFO : End of 2D read delay Voltage center optimization
544 20:40:29.015800 INFO : End of 2D read delay Voltage center optimization
545 20:40:29.067789 INFO : End of 2D write delay Voltage center optimization
546 20:40:29.117174 INFO : End of 2D write delay Voltage center optimization
547 20:40:29.122788 INFO : Training has run successfully!
548 20:40:29.123285
549 20:40:29.123757 channel==0
550 20:40:29.128389 RxClkDly_Margin_A0==88 ps 9
551 20:40:29.128888 TxDqDly_Margin_A0==98 ps 10
552 20:40:29.133973 RxClkDly_Margin_A1==78 ps 8
553 20:40:29.134476 TxDqDly_Margin_A1==98 ps 10
554 20:40:29.134935 TrainedVREFDQ_A0==74
555 20:40:29.139578 TrainedVREFDQ_A1==74
556 20:40:29.140121 VrefDac_Margin_A0==24
557 20:40:29.140578 DeviceVref_Margin_A0==40
558 20:40:29.145179 VrefDac_Margin_A1==26
559 20:40:29.145679 DeviceVref_Margin_A1==40
560 20:40:29.146130
561 20:40:29.146573
562 20:40:29.150801 channel==1
563 20:40:29.151301 RxClkDly_Margin_A0==98 ps 10
564 20:40:29.151759 TxDqDly_Margin_A0==98 ps 10
565 20:40:29.156389 RxClkDly_Margin_A1==98 ps 10
566 20:40:29.156888 TxDqDly_Margin_A1==88 ps 9
567 20:40:29.161980 TrainedVREFDQ_A0==77
568 20:40:29.162486 TrainedVREFDQ_A1==77
569 20:40:29.162939 VrefDac_Margin_A0==22
570 20:40:29.167580 DeviceVref_Margin_A0==37
571 20:40:29.168105 VrefDac_Margin_A1==24
572 20:40:29.173181 DeviceVref_Margin_A1==37
573 20:40:29.173680
574 20:40:29.174129 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 20:40:29.178789
576 20:40:29.206743 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
577 20:40:29.207274 2D training succeed
578 20:40:29.212367 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 20:40:29.217967 auto size-- 65535DDR cs0 size: 2048MB
580 20:40:29.218472 DDR cs1 size: 2048MB
581 20:40:29.223569 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 20:40:29.224103 cs0 DataBus test pass
583 20:40:29.229163 cs1 DataBus test pass
584 20:40:29.229667 cs0 AddrBus test pass
585 20:40:29.230119 cs1 AddrBus test pass
586 20:40:29.230562
587 20:40:29.234760 100bdlr_step_size ps== 420
588 20:40:29.235272 result report
589 20:40:29.240364 boot times 0Enable ddr reg access
590 20:40:29.245799 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 20:40:29.259255 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 20:40:29.833111 0.0;M3 CHK:0;cm4_sp_mode 0
593 20:40:29.833740 MVN_1=0x00000000
594 20:40:29.838691 MVN_2=0x00000000
595 20:40:29.844461 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 20:40:29.845090 OPS=0x10
597 20:40:29.845598 ring efuse init
598 20:40:29.846061 chipver efuse init
599 20:40:29.849937 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 20:40:29.855541 [0.018961 Inits done]
601 20:40:29.856154 secure task start!
602 20:40:29.856602 high task start!
603 20:40:29.860202 low task start!
604 20:40:29.860756 run into bl31
605 20:40:29.866793 NOTICE: BL31: v1.3(release):4fc40b1
606 20:40:29.874615 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 20:40:29.875182 NOTICE: BL31: G12A normal boot!
608 20:40:29.899897 NOTICE: BL31: BL33 decompress pass
609 20:40:29.905588 ERROR: Error initializing runtime service opteed_fast
610 20:40:31.138437
611 20:40:31.139023
612 20:40:31.146935 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 20:40:31.147448
614 20:40:31.147911 Model: Libre Computer AML-A311D-CC Alta
615 20:40:31.355289 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 20:40:31.378676 DRAM: 2 GiB (effective 3.8 GiB)
617 20:40:31.521627 Core: 408 devices, 31 uclasses, devicetree: separate
618 20:40:31.527621 WDT: Not starting watchdog@f0d0
619 20:40:31.559798 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 20:40:31.572331 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 20:40:31.577343 ** Bad device specification mmc 0 **
622 20:40:31.587514 Card did not respond to voltage select! : -110
623 20:40:31.595217 ** Bad device specification mmc 0 **
624 20:40:31.595727 Couldn't find partition mmc 0
625 20:40:31.603524 Card did not respond to voltage select! : -110
626 20:40:31.609020 ** Bad device specification mmc 0 **
627 20:40:31.609529 Couldn't find partition mmc 0
628 20:40:31.614150 Error: could not access storage.
629 20:40:31.956646 Net: eth0: ethernet@ff3f0000
630 20:40:31.957262 starting USB...
631 20:40:32.208942 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 20:40:32.209382 Starting the controller
633 20:40:32.215677 USB XHCI 1.10
634 20:40:33.924994 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 20:40:33.925696 bl2_stage_init 0x01
636 20:40:33.926183 bl2_stage_init 0x81
637 20:40:33.930581 hw id: 0x0000 - pwm id 0x01
638 20:40:33.931105 bl2_stage_init 0xc1
639 20:40:33.931574 bl2_stage_init 0x02
640 20:40:33.932076
641 20:40:33.936069 L0:00000000
642 20:40:33.936589 L1:20000703
643 20:40:33.937048 L2:00008067
644 20:40:33.937502 L3:14000000
645 20:40:33.939018 B2:00402000
646 20:40:33.939520 B1:e0f83180
647 20:40:33.939975
648 20:40:33.940468 TE: 58159
649 20:40:33.940922
650 20:40:33.950125 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 20:40:33.950644
652 20:40:33.951111 Board ID = 1
653 20:40:33.951558 Set A53 clk to 24M
654 20:40:33.952031 Set A73 clk to 24M
655 20:40:33.955822 Set clk81 to 24M
656 20:40:33.956367 A53 clk: 1200 MHz
657 20:40:33.956825 A73 clk: 1200 MHz
658 20:40:33.959239 CLK81: 166.6M
659 20:40:33.959742 smccc: 00012ab5
660 20:40:33.964818 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 20:40:33.970395 board id: 1
662 20:40:33.975728 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 20:40:33.986100 fw parse done
664 20:40:33.992097 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 20:40:34.034678 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 20:40:34.045696 PIEI prepare done
667 20:40:34.046239 fastboot data load
668 20:40:34.046703 fastboot data verify
669 20:40:34.051293 verify result: 266
670 20:40:34.056875 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 20:40:34.057395 LPDDR4 probe
672 20:40:34.057857 ddr clk to 1584MHz
673 20:40:34.064858 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 20:40:34.102089
675 20:40:34.102624 dmc_version 0001
676 20:40:34.108808 Check phy result
677 20:40:34.114660 INFO : End of CA training
678 20:40:34.115172 INFO : End of initialization
679 20:40:34.120271 INFO : Training has run successfully!
680 20:40:34.120788 Check phy result
681 20:40:34.125857 INFO : End of initialization
682 20:40:34.126365 INFO : End of read enable training
683 20:40:34.131482 INFO : End of fine write leveling
684 20:40:34.137056 INFO : End of Write leveling coarse delay
685 20:40:34.137571 INFO : Training has run successfully!
686 20:40:34.138033 Check phy result
687 20:40:34.142662 INFO : End of initialization
688 20:40:34.143175 INFO : End of read dq deskew training
689 20:40:34.148251 INFO : End of MPR read delay center optimization
690 20:40:34.153862 INFO : End of write delay center optimization
691 20:40:34.159456 INFO : End of read delay center optimization
692 20:40:34.159966 INFO : End of max read latency training
693 20:40:34.165067 INFO : Training has run successfully!
694 20:40:34.165581 1D training succeed
695 20:40:34.174214 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 20:40:34.221858 Check phy result
697 20:40:34.222384 INFO : End of initialization
698 20:40:34.244291 INFO : End of 2D read delay Voltage center optimization
699 20:40:34.264407 INFO : End of 2D read delay Voltage center optimization
700 20:40:34.316303 INFO : End of 2D write delay Voltage center optimization
701 20:40:34.365536 INFO : End of 2D write delay Voltage center optimization
702 20:40:34.371127 INFO : Training has run successfully!
703 20:40:34.371638
704 20:40:34.372143 channel==0
705 20:40:34.376739 RxClkDly_Margin_A0==88 ps 9
706 20:40:34.377267 TxDqDly_Margin_A0==98 ps 10
707 20:40:34.382338 RxClkDly_Margin_A1==88 ps 9
708 20:40:34.382852 TxDqDly_Margin_A1==98 ps 10
709 20:40:34.383315 TrainedVREFDQ_A0==74
710 20:40:34.387924 TrainedVREFDQ_A1==74
711 20:40:34.388466 VrefDac_Margin_A0==25
712 20:40:34.388921 DeviceVref_Margin_A0==40
713 20:40:34.393537 VrefDac_Margin_A1==24
714 20:40:34.394050 DeviceVref_Margin_A1==40
715 20:40:34.394504
716 20:40:34.394952
717 20:40:34.399136 channel==1
718 20:40:34.399647 RxClkDly_Margin_A0==98 ps 10
719 20:40:34.400139 TxDqDly_Margin_A0==98 ps 10
720 20:40:34.404733 RxClkDly_Margin_A1==98 ps 10
721 20:40:34.405245 TxDqDly_Margin_A1==88 ps 9
722 20:40:34.410322 TrainedVREFDQ_A0==77
723 20:40:34.410828 TrainedVREFDQ_A1==77
724 20:40:34.411284 VrefDac_Margin_A0==22
725 20:40:34.415922 DeviceVref_Margin_A0==37
726 20:40:34.416459 VrefDac_Margin_A1==24
727 20:40:34.421531 DeviceVref_Margin_A1==37
728 20:40:34.422045
729 20:40:34.422498 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 20:40:34.427151
731 20:40:34.455112 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000017 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
732 20:40:34.455698 2D training succeed
733 20:40:34.460729 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 20:40:34.466318 auto size-- 65535DDR cs0 size: 2048MB
735 20:40:34.466832 DDR cs1 size: 2048MB
736 20:40:34.471940 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 20:40:34.472486 cs0 DataBus test pass
738 20:40:34.477533 cs1 DataBus test pass
739 20:40:34.478040 cs0 AddrBus test pass
740 20:40:34.478497 cs1 AddrBus test pass
741 20:40:34.478942
742 20:40:34.483113 100bdlr_step_size ps== 420
743 20:40:34.483634 result report
744 20:40:34.488682 boot times 0Enable ddr reg access
745 20:40:34.494134 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 20:40:34.507572 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 20:40:35.079532 0.0;M3 CHK:0;cm4_sp_mode 0
748 20:40:35.080179 MVN_1=0x00000000
749 20:40:35.085094 MVN_2=0x00000000
750 20:40:35.090851 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 20:40:35.091403 OPS=0x10
752 20:40:35.091851 ring efuse init
753 20:40:35.092331 chipver efuse init
754 20:40:35.096414 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 20:40:35.101996 [0.018961 Inits done]
756 20:40:35.102494 secure task start!
757 20:40:35.102932 high task start!
758 20:40:35.106580 low task start!
759 20:40:35.107074 run into bl31
760 20:40:35.113255 NOTICE: BL31: v1.3(release):4fc40b1
761 20:40:35.121063 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 20:40:35.121568 NOTICE: BL31: G12A normal boot!
763 20:40:35.146469 NOTICE: BL31: BL33 decompress pass
764 20:40:35.152191 ERROR: Error initializing runtime service opteed_fast
765 20:40:36.385184
766 20:40:36.385842
767 20:40:36.393552 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 20:40:36.394097
769 20:40:36.394565 Model: Libre Computer AML-A311D-CC Alta
770 20:40:36.602042 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 20:40:36.625365 DRAM: 2 GiB (effective 3.8 GiB)
772 20:40:36.768302 Core: 408 devices, 31 uclasses, devicetree: separate
773 20:40:36.774181 WDT: Not starting watchdog@f0d0
774 20:40:36.806443 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 20:40:36.818900 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 20:40:36.823976 ** Bad device specification mmc 0 **
777 20:40:36.834242 Card did not respond to voltage select! : -110
778 20:40:36.841892 ** Bad device specification mmc 0 **
779 20:40:36.842411 Couldn't find partition mmc 0
780 20:40:36.850232 Card did not respond to voltage select! : -110
781 20:40:36.855741 ** Bad device specification mmc 0 **
782 20:40:36.856294 Couldn't find partition mmc 0
783 20:40:36.860815 Error: could not access storage.
784 20:40:37.203261 Net: eth0: ethernet@ff3f0000
785 20:40:37.203875 starting USB...
786 20:40:37.455152 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 20:40:37.455775 Starting the controller
788 20:40:37.462076 USB XHCI 1.10
789 20:40:39.625058 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 20:40:39.625716 bl2_stage_init 0x01
791 20:40:39.626183 bl2_stage_init 0x81
792 20:40:39.630717 hw id: 0x0000 - pwm id 0x01
793 20:40:39.631234 bl2_stage_init 0xc1
794 20:40:39.631693 bl2_stage_init 0x02
795 20:40:39.632199
796 20:40:39.636280 L0:00000000
797 20:40:39.636786 L1:20000703
798 20:40:39.637242 L2:00008067
799 20:40:39.637687 L3:14000000
800 20:40:39.641840 B2:00402000
801 20:40:39.642341 B1:e0f83180
802 20:40:39.642797
803 20:40:39.643250 TE: 58124
804 20:40:39.643698
805 20:40:39.647459 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 20:40:39.647965
807 20:40:39.648458 Board ID = 1
808 20:40:39.653034 Set A53 clk to 24M
809 20:40:39.653541 Set A73 clk to 24M
810 20:40:39.653991 Set clk81 to 24M
811 20:40:39.658684 A53 clk: 1200 MHz
812 20:40:39.659193 A73 clk: 1200 MHz
813 20:40:39.659645 CLK81: 166.6M
814 20:40:39.660121 smccc: 00012a92
815 20:40:39.664257 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 20:40:39.669742 board id: 1
817 20:40:39.675642 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 20:40:39.686329 fw parse done
819 20:40:39.692258 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 20:40:39.734869 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 20:40:39.745774 PIEI prepare done
822 20:40:39.746283 fastboot data load
823 20:40:39.746745 fastboot data verify
824 20:40:39.751479 verify result: 266
825 20:40:39.757039 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 20:40:39.757555 LPDDR4 probe
827 20:40:39.758008 ddr clk to 1584MHz
828 20:40:39.765114 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 20:40:39.802324
830 20:40:39.802864 dmc_version 0001
831 20:40:39.809025 Check phy result
832 20:40:39.814852 INFO : End of CA training
833 20:40:39.815364 INFO : End of initialization
834 20:40:39.820466 INFO : Training has run successfully!
835 20:40:39.820978 Check phy result
836 20:40:39.826061 INFO : End of initialization
837 20:40:39.826573 INFO : End of read enable training
838 20:40:39.831708 INFO : End of fine write leveling
839 20:40:39.837250 INFO : End of Write leveling coarse delay
840 20:40:39.837761 INFO : Training has run successfully!
841 20:40:39.838214 Check phy result
842 20:40:39.842825 INFO : End of initialization
843 20:40:39.843334 INFO : End of read dq deskew training
844 20:40:39.848445 INFO : End of MPR read delay center optimization
845 20:40:39.854097 INFO : End of write delay center optimization
846 20:40:39.859691 INFO : End of read delay center optimization
847 20:40:39.860240 INFO : End of max read latency training
848 20:40:39.865257 INFO : Training has run successfully!
849 20:40:39.865768 1D training succeed
850 20:40:39.874326 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 20:40:39.921984 Check phy result
852 20:40:39.922529 INFO : End of initialization
853 20:40:39.943748 INFO : End of 2D read delay Voltage center optimization
854 20:40:39.964034 INFO : End of 2D read delay Voltage center optimization
855 20:40:40.016075 INFO : End of 2D write delay Voltage center optimization
856 20:40:40.065391 INFO : End of 2D write delay Voltage center optimization
857 20:40:40.070958 INFO : Training has run successfully!
858 20:40:40.071472
859 20:40:40.071935 channel==0
860 20:40:40.076568 RxClkDly_Margin_A0==88 ps 9
861 20:40:40.077097 TxDqDly_Margin_A0==98 ps 10
862 20:40:40.082141 RxClkDly_Margin_A1==88 ps 9
863 20:40:40.082653 TxDqDly_Margin_A1==98 ps 10
864 20:40:40.083125 TrainedVREFDQ_A0==74
865 20:40:40.087784 TrainedVREFDQ_A1==74
866 20:40:40.088352 VrefDac_Margin_A0==25
867 20:40:40.088813 DeviceVref_Margin_A0==40
868 20:40:40.093351 VrefDac_Margin_A1==25
869 20:40:40.093881 DeviceVref_Margin_A1==40
870 20:40:40.094317
871 20:40:40.094749
872 20:40:40.098935 channel==1
873 20:40:40.099441 RxClkDly_Margin_A0==98 ps 10
874 20:40:40.099877 TxDqDly_Margin_A0==88 ps 9
875 20:40:40.104529 RxClkDly_Margin_A1==98 ps 10
876 20:40:40.105029 TxDqDly_Margin_A1==108 ps 11
877 20:40:40.110138 TrainedVREFDQ_A0==76
878 20:40:40.110633 TrainedVREFDQ_A1==78
879 20:40:40.111069 VrefDac_Margin_A0==22
880 20:40:40.115729 DeviceVref_Margin_A0==38
881 20:40:40.116264 VrefDac_Margin_A1==24
882 20:40:40.121333 DeviceVref_Margin_A1==36
883 20:40:40.121826
884 20:40:40.122263 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 20:40:40.126927
886 20:40:40.154885 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
887 20:40:40.155446 2D training succeed
888 20:40:40.160555 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 20:40:40.166131 auto size-- 65535DDR cs0 size: 2048MB
890 20:40:40.166629 DDR cs1 size: 2048MB
891 20:40:40.171723 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 20:40:40.172261 cs0 DataBus test pass
893 20:40:40.177339 cs1 DataBus test pass
894 20:40:40.177837 cs0 AddrBus test pass
895 20:40:40.178272 cs1 AddrBus test pass
896 20:40:40.178701
897 20:40:40.182938 100bdlr_step_size ps== 420
898 20:40:40.183441 result report
899 20:40:40.188528 boot times 0Enable ddr reg access
900 20:40:40.194036 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 20:40:40.207515 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 20:40:40.781149 0.0;M3 CHK:0;cm4_sp_mode 0
903 20:40:40.781814 MVN_1=0x00000000
904 20:40:40.786635 MVN_2=0x00000000
905 20:40:40.792456 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 20:40:40.792980 OPS=0x10
907 20:40:40.793447 ring efuse init
908 20:40:40.793895 chipver efuse init
909 20:40:40.797969 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 20:40:40.803571 [0.018961 Inits done]
911 20:40:40.804125 secure task start!
912 20:40:40.804587 high task start!
913 20:40:40.808187 low task start!
914 20:40:40.808693 run into bl31
915 20:40:40.814791 NOTICE: BL31: v1.3(release):4fc40b1
916 20:40:40.822570 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 20:40:40.823081 NOTICE: BL31: G12A normal boot!
918 20:40:40.847939 NOTICE: BL31: BL33 decompress pass
919 20:40:40.853650 ERROR: Error initializing runtime service opteed_fast
920 20:40:42.086581
921 20:40:42.087232
922 20:40:42.094958 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 20:40:42.095492
924 20:40:42.095960 Model: Libre Computer AML-A311D-CC Alta
925 20:40:42.303411 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 20:40:42.326787 DRAM: 2 GiB (effective 3.8 GiB)
927 20:40:42.469796 Core: 408 devices, 31 uclasses, devicetree: separate
928 20:40:42.475626 WDT: Not starting watchdog@f0d0
929 20:40:42.507869 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 20:40:42.520298 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 20:40:42.525307 ** Bad device specification mmc 0 **
932 20:40:42.535668 Card did not respond to voltage select! : -110
933 20:40:42.543285 ** Bad device specification mmc 0 **
934 20:40:42.543790 Couldn't find partition mmc 0
935 20:40:42.551683 Card did not respond to voltage select! : -110
936 20:40:42.557147 ** Bad device specification mmc 0 **
937 20:40:42.557654 Couldn't find partition mmc 0
938 20:40:42.562209 Error: could not access storage.
939 20:40:42.904656 Net: eth0: ethernet@ff3f0000
940 20:40:42.905250 starting USB...
941 20:40:43.156579 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 20:40:43.157210 Starting the controller
943 20:40:43.163485 USB XHCI 1.10
944 20:40:45.024959 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 20:40:45.025611 bl2_stage_init 0x01
946 20:40:45.026086 bl2_stage_init 0x81
947 20:40:45.030549 hw id: 0x0000 - pwm id 0x01
948 20:40:45.031066 bl2_stage_init 0xc1
949 20:40:45.031523 bl2_stage_init 0x02
950 20:40:45.031971
951 20:40:45.036224 L0:00000000
952 20:40:45.036732 L1:20000703
953 20:40:45.037184 L2:00008067
954 20:40:45.037629 L3:14000000
955 20:40:45.041803 B2:00402000
956 20:40:45.042304 B1:e0f83180
957 20:40:45.042759
958 20:40:45.043210 TE: 58159
959 20:40:45.043658
960 20:40:45.047409 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 20:40:45.047915
962 20:40:45.048414 Board ID = 1
963 20:40:45.052931 Set A53 clk to 24M
964 20:40:45.053434 Set A73 clk to 24M
965 20:40:45.053887 Set clk81 to 24M
966 20:40:45.058586 A53 clk: 1200 MHz
967 20:40:45.059089 A73 clk: 1200 MHz
968 20:40:45.059544 CLK81: 166.6M
969 20:40:45.060020 smccc: 00012ab5
970 20:40:45.064210 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 20:40:45.069900 board id: 1
972 20:40:45.075720 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 20:40:45.086361 fw parse done
974 20:40:45.092376 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 20:40:45.134757 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 20:40:45.145661 PIEI prepare done
977 20:40:45.146157 fastboot data load
978 20:40:45.146594 fastboot data verify
979 20:40:45.151349 verify result: 266
980 20:40:45.156951 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 20:40:45.157441 LPDDR4 probe
982 20:40:45.157872 ddr clk to 1584MHz
983 20:40:45.164927 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 20:40:45.202225
985 20:40:45.202738 dmc_version 0001
986 20:40:45.208861 Check phy result
987 20:40:45.214746 INFO : End of CA training
988 20:40:45.215233 INFO : End of initialization
989 20:40:45.220332 INFO : Training has run successfully!
990 20:40:45.220818 Check phy result
991 20:40:45.226011 INFO : End of initialization
992 20:40:45.226547 INFO : End of read enable training
993 20:40:45.231554 INFO : End of fine write leveling
994 20:40:45.237220 INFO : End of Write leveling coarse delay
995 20:40:45.237735 INFO : Training has run successfully!
996 20:40:45.238184 Check phy result
997 20:40:45.242772 INFO : End of initialization
998 20:40:45.243308 INFO : End of read dq deskew training
999 20:40:45.248369 INFO : End of MPR read delay center optimization
1000 20:40:45.253931 INFO : End of write delay center optimization
1001 20:40:45.259542 INFO : End of read delay center optimization
1002 20:40:45.260086 INFO : End of max read latency training
1003 20:40:45.265139 INFO : Training has run successfully!
1004 20:40:45.265644 1D training succeed
1005 20:40:45.274297 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 20:40:45.321923 Check phy result
1007 20:40:45.322448 INFO : End of initialization
1008 20:40:45.344421 INFO : End of 2D read delay Voltage center optimization
1009 20:40:45.364512 INFO : End of 2D read delay Voltage center optimization
1010 20:40:45.416400 INFO : End of 2D write delay Voltage center optimization
1011 20:40:45.465674 INFO : End of 2D write delay Voltage center optimization
1012 20:40:45.471241 INFO : Training has run successfully!
1013 20:40:45.471751
1014 20:40:45.472278 channel==0
1015 20:40:45.476850 RxClkDly_Margin_A0==88 ps 9
1016 20:40:45.477361 TxDqDly_Margin_A0==98 ps 10
1017 20:40:45.480347 RxClkDly_Margin_A1==88 ps 9
1018 20:40:45.480853 TxDqDly_Margin_A1==98 ps 10
1019 20:40:45.485770 TrainedVREFDQ_A0==74
1020 20:40:45.486267 TrainedVREFDQ_A1==74
1021 20:40:45.486731 VrefDac_Margin_A0==24
1022 20:40:45.491279 DeviceVref_Margin_A0==40
1023 20:40:45.491764 VrefDac_Margin_A1==25
1024 20:40:45.496900 DeviceVref_Margin_A1==40
1025 20:40:45.497389
1026 20:40:45.497844
1027 20:40:45.498295 channel==1
1028 20:40:45.498740 RxClkDly_Margin_A0==98 ps 10
1029 20:40:45.502502 TxDqDly_Margin_A0==98 ps 10
1030 20:40:45.502998 RxClkDly_Margin_A1==88 ps 9
1031 20:40:45.508146 TxDqDly_Margin_A1==88 ps 9
1032 20:40:45.508639 TrainedVREFDQ_A0==77
1033 20:40:45.509093 TrainedVREFDQ_A1==77
1034 20:40:45.513700 VrefDac_Margin_A0==22
1035 20:40:45.514195 DeviceVref_Margin_A0==37
1036 20:40:45.519313 VrefDac_Margin_A1==24
1037 20:40:45.519800 DeviceVref_Margin_A1==37
1038 20:40:45.520280
1039 20:40:45.524892 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 20:40:45.525377
1041 20:40:45.552866 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1042 20:40:45.558502 2D training succeed
1043 20:40:45.564140 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 20:40:45.564641 auto size-- 65535DDR cs0 size: 2048MB
1045 20:40:45.569680 DDR cs1 size: 2048MB
1046 20:40:45.570168 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 20:40:45.575284 cs0 DataBus test pass
1048 20:40:45.575773 cs1 DataBus test pass
1049 20:40:45.576275 cs0 AddrBus test pass
1050 20:40:45.580911 cs1 AddrBus test pass
1051 20:40:45.581406
1052 20:40:45.581860 100bdlr_step_size ps== 420
1053 20:40:45.582317 result report
1054 20:40:45.586517 boot times 0Enable ddr reg access
1055 20:40:45.594100 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 20:40:45.607553 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 20:40:46.179603 0.0;M3 CHK:0;cm4_sp_mode 0
1058 20:40:46.180259 MVN_1=0x00000000
1059 20:40:46.185063 MVN_2=0x00000000
1060 20:40:46.190814 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 20:40:46.191316 OPS=0x10
1062 20:40:46.191778 ring efuse init
1063 20:40:46.192265 chipver efuse init
1064 20:40:46.196410 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 20:40:46.202018 [0.018961 Inits done]
1066 20:40:46.202512 secure task start!
1067 20:40:46.202962 high task start!
1068 20:40:46.206601 low task start!
1069 20:40:46.207101 run into bl31
1070 20:40:46.213209 NOTICE: BL31: v1.3(release):4fc40b1
1071 20:40:46.221007 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 20:40:46.221516 NOTICE: BL31: G12A normal boot!
1073 20:40:46.246499 NOTICE: BL31: BL33 decompress pass
1074 20:40:46.252214 ERROR: Error initializing runtime service opteed_fast
1075 20:40:47.485140
1076 20:40:47.485807
1077 20:40:47.493490 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 20:40:47.494016
1079 20:40:47.494478 Model: Libre Computer AML-A311D-CC Alta
1080 20:40:47.701883 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 20:40:47.725264 DRAM: 2 GiB (effective 3.8 GiB)
1082 20:40:47.868250 Core: 408 devices, 31 uclasses, devicetree: separate
1083 20:40:47.874117 WDT: Not starting watchdog@f0d0
1084 20:40:47.906408 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 20:40:47.918805 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 20:40:47.923811 ** Bad device specification mmc 0 **
1087 20:40:47.934155 Card did not respond to voltage select! : -110
1088 20:40:47.941797 ** Bad device specification mmc 0 **
1089 20:40:47.942306 Couldn't find partition mmc 0
1090 20:40:47.950140 Card did not respond to voltage select! : -110
1091 20:40:47.955674 ** Bad device specification mmc 0 **
1092 20:40:47.956219 Couldn't find partition mmc 0
1093 20:40:47.960720 Error: could not access storage.
1094 20:40:48.303151 Net: eth0: ethernet@ff3f0000
1095 20:40:48.303746 starting USB...
1096 20:40:48.555022 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 20:40:48.555618 Starting the controller
1098 20:40:48.561959 USB XHCI 1.10
1099 20:40:50.118294 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 20:40:50.126891 scanning usb for storage devices... 0 Storage Device(s) found
1102 20:40:50.178872 Hit any key to stop autoboot: 1
1103 20:40:50.179700 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1104 20:40:50.180519 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1105 20:40:50.181045 Setting prompt string to ['=>']
1106 20:40:50.181563 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1107 20:40:50.194227 0
1108 20:40:50.195171 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 20:40:50.195699 Sending with 10 millisecond of delay
1111 20:40:51.330706 => setenv autoload no
1112 20:40:51.341580 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1113 20:40:51.346987 setenv autoload no
1114 20:40:51.347785 Sending with 10 millisecond of delay
1116 20:40:53.144684 => setenv initrd_high 0xffffffff
1117 20:40:53.155522 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1118 20:40:53.156490 setenv initrd_high 0xffffffff
1119 20:40:53.157260 Sending with 10 millisecond of delay
1121 20:40:54.773725 => setenv fdt_high 0xffffffff
1122 20:40:54.784563 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 20:40:54.785488 setenv fdt_high 0xffffffff
1124 20:40:54.786262 Sending with 10 millisecond of delay
1126 20:40:55.078162 => dhcp
1127 20:40:55.089053 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1128 20:40:55.089579 dhcp
1129 20:40:55.089818 Speed: 1000, full duplex
1130 20:40:55.090033 BOOTP broadcast 1
1131 20:40:55.100426 DHCP client bound to address 192.168.6.27 (11 ms)
1132 20:40:55.101065 Sending with 10 millisecond of delay
1134 20:40:56.778211 => setenv serverip 192.168.6.2
1135 20:40:56.789071 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 20:40:56.790039 setenv serverip 192.168.6.2
1137 20:40:56.790790 Sending with 10 millisecond of delay
1139 20:41:00.514469 => tftpboot 0x01080000 948797/tftp-deploy-4s93p3h0/kernel/uImage
1140 20:41:00.525341 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 20:41:00.526261 tftpboot 0x01080000 948797/tftp-deploy-4s93p3h0/kernel/uImage
1142 20:41:00.526780 Speed: 1000, full duplex
1143 20:41:00.527248 Using ethernet@ff3f0000 device
1144 20:41:00.528350 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 20:41:00.533712 Filename '948797/tftp-deploy-4s93p3h0/kernel/uImage'.
1146 20:41:00.537686 Load address: 0x1080000
1147 20:41:02.972011 Loading: *################################################## 37.6 MiB
1148 20:41:02.972693 15.4 MiB/s
1149 20:41:02.973171 done
1150 20:41:02.976626 Bytes transferred = 39424576 (2599240 hex)
1151 20:41:02.977494 Sending with 10 millisecond of delay
1153 20:41:07.664468 => tftpboot 0x08000000 948797/tftp-deploy-4s93p3h0/ramdisk/ramdisk.cpio.gz.uboot
1154 20:41:07.675305 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1155 20:41:07.676241 tftpboot 0x08000000 948797/tftp-deploy-4s93p3h0/ramdisk/ramdisk.cpio.gz.uboot
1156 20:41:07.676745 Speed: 1000, full duplex
1157 20:41:07.677211 Using ethernet@ff3f0000 device
1158 20:41:07.678277 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 20:41:07.686900 Filename '948797/tftp-deploy-4s93p3h0/ramdisk/ramdisk.cpio.gz.uboot'.
1160 20:41:07.687453 Load address: 0x8000000
1161 20:41:15.094574 Loading: *##T ############################################### UDP wrong checksum 00000005 0000eb8d
1162 20:41:20.095334 T UDP wrong checksum 00000005 0000eb8d
1163 20:41:30.098154 T T UDP wrong checksum 00000005 0000eb8d
1164 20:41:50.100991 T T T T UDP wrong checksum 00000005 0000eb8d
1165 20:42:05.106196 T T
1166 20:42:05.106880 Retry count exceeded; starting again
1168 20:42:05.108502 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1171 20:42:05.110576 end: 2.4 uboot-commands (duration 00:01:53) [common]
1173 20:42:05.112138 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1175 20:42:05.113272 end: 2 uboot-action (duration 00:01:53) [common]
1177 20:42:05.114917 Cleaning after the job
1178 20:42:05.115512 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948797/tftp-deploy-4s93p3h0/ramdisk
1179 20:42:05.116971 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948797/tftp-deploy-4s93p3h0/kernel
1180 20:42:05.142088 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948797/tftp-deploy-4s93p3h0/dtb
1181 20:42:05.143419 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948797/tftp-deploy-4s93p3h0/nfsrootfs
1182 20:42:05.194206 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948797/tftp-deploy-4s93p3h0/modules
1183 20:42:05.203468 start: 4.1 power-off (timeout 00:00:30) [common]
1184 20:42:05.204090 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1185 20:42:05.237692 >> OK - accepted request
1186 20:42:05.239463 Returned 0 in 0 seconds
1187 20:42:05.340205 end: 4.1 power-off (duration 00:00:00) [common]
1189 20:42:05.341133 start: 4.2 read-feedback (timeout 00:10:00) [common]
1190 20:42:05.341769 Listened to connection for namespace 'common' for up to 1s
1191 20:42:06.342737 Finalising connection for namespace 'common'
1192 20:42:06.343453 Disconnecting from shell: Finalise
1193 20:42:06.343970 =>
1194 20:42:06.445093 end: 4.2 read-feedback (duration 00:00:01) [common]
1195 20:42:06.445810 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/948797
1196 20:42:08.519945 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/948797
1197 20:42:08.520577 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.