Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:24:31.936383 lava-dispatcher, installed at version: 2024.01
2 20:24:31.937186 start: 0 validate
3 20:24:31.937666 Start time: 2024-11-06 20:24:31.937635+00:00 (UTC)
4 20:24:31.938213 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:24:31.938766 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 20:24:31.978609 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:24:31.979183 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 20:24:32.013442 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:24:32.014394 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 20:24:35.077609 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:24:35.078138 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 20:24:35.122204 validate duration: 3.18
14 20:24:35.123661 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:24:35.124316 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:24:35.124883 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:24:35.125827 Not decompressing ramdisk as can be used compressed.
18 20:24:35.126558 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 20:24:35.127005 saving as /var/lib/lava/dispatcher/tmp/948429/tftp-deploy-0paqgbzk/ramdisk/rootfs.cpio.gz
20 20:24:35.127484 total size: 8181887 (7 MB)
21 20:24:35.169316 progress 0 % (0 MB)
22 20:24:35.180969 progress 5 % (0 MB)
23 20:24:35.192023 progress 10 % (0 MB)
24 20:24:35.203745 progress 15 % (1 MB)
25 20:24:35.210978 progress 20 % (1 MB)
26 20:24:35.216628 progress 25 % (1 MB)
27 20:24:35.221863 progress 30 % (2 MB)
28 20:24:35.227754 progress 35 % (2 MB)
29 20:24:35.233208 progress 40 % (3 MB)
30 20:24:35.238998 progress 45 % (3 MB)
31 20:24:35.244381 progress 50 % (3 MB)
32 20:24:35.249888 progress 55 % (4 MB)
33 20:24:35.254982 progress 60 % (4 MB)
34 20:24:35.260825 progress 65 % (5 MB)
35 20:24:35.266293 progress 70 % (5 MB)
36 20:24:35.272246 progress 75 % (5 MB)
37 20:24:35.277357 progress 80 % (6 MB)
38 20:24:35.282826 progress 85 % (6 MB)
39 20:24:35.287904 progress 90 % (7 MB)
40 20:24:35.293036 progress 95 % (7 MB)
41 20:24:35.297721 progress 100 % (7 MB)
42 20:24:35.298369 7 MB downloaded in 0.17 s (45.66 MB/s)
43 20:24:35.298938 end: 1.1.1 http-download (duration 00:00:00) [common]
45 20:24:35.299862 end: 1.1 download-retry (duration 00:00:00) [common]
46 20:24:35.300199 start: 1.2 download-retry (timeout 00:10:00) [common]
47 20:24:35.300487 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 20:24:35.300984 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm64/defconfig+debug/gcc-12/kernel/Image
49 20:24:35.301237 saving as /var/lib/lava/dispatcher/tmp/948429/tftp-deploy-0paqgbzk/kernel/Image
50 20:24:35.301453 total size: 169943552 (162 MB)
51 20:24:35.301673 No compression specified
52 20:24:35.341843 progress 0 % (0 MB)
53 20:24:35.445717 progress 5 % (8 MB)
54 20:24:35.549114 progress 10 % (16 MB)
55 20:24:35.653179 progress 15 % (24 MB)
56 20:24:35.757133 progress 20 % (32 MB)
57 20:24:35.861189 progress 25 % (40 MB)
58 20:24:35.967838 progress 30 % (48 MB)
59 20:24:36.072890 progress 35 % (56 MB)
60 20:24:36.178141 progress 40 % (64 MB)
61 20:24:36.285057 progress 45 % (72 MB)
62 20:24:36.390580 progress 50 % (81 MB)
63 20:24:36.496613 progress 55 % (89 MB)
64 20:24:36.602711 progress 60 % (97 MB)
65 20:24:36.708927 progress 65 % (105 MB)
66 20:24:36.815697 progress 70 % (113 MB)
67 20:24:36.921490 progress 75 % (121 MB)
68 20:24:37.036726 progress 80 % (129 MB)
69 20:24:37.164728 progress 85 % (137 MB)
70 20:24:37.292207 progress 90 % (145 MB)
71 20:24:37.418671 progress 95 % (153 MB)
72 20:24:37.543811 progress 100 % (162 MB)
73 20:24:37.544576 162 MB downloaded in 2.24 s (72.25 MB/s)
74 20:24:37.545167 end: 1.2.1 http-download (duration 00:00:02) [common]
76 20:24:37.546158 end: 1.2 download-retry (duration 00:00:02) [common]
77 20:24:37.546494 start: 1.3 download-retry (timeout 00:09:58) [common]
78 20:24:37.546815 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 20:24:37.547390 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 20:24:37.547722 saving as /var/lib/lava/dispatcher/tmp/948429/tftp-deploy-0paqgbzk/dtb/meson-g12b-a311d-libretech-cc.dtb
81 20:24:37.547976 total size: 54703 (0 MB)
82 20:24:37.548260 No compression specified
83 20:24:37.595514 progress 59 % (0 MB)
84 20:24:37.596569 progress 100 % (0 MB)
85 20:24:37.597254 0 MB downloaded in 0.05 s (1.06 MB/s)
86 20:24:37.597811 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:24:37.598799 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:24:37.599112 start: 1.4 download-retry (timeout 00:09:58) [common]
90 20:24:37.599437 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 20:24:37.600031 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 20:24:37.600344 saving as /var/lib/lava/dispatcher/tmp/948429/tftp-deploy-0paqgbzk/modules/modules.tar
93 20:24:37.600595 total size: 27662012 (26 MB)
94 20:24:37.600850 Using unxz to decompress xz
95 20:24:37.636481 progress 0 % (0 MB)
96 20:24:37.829046 progress 5 % (1 MB)
97 20:24:38.027787 progress 10 % (2 MB)
98 20:24:38.255546 progress 15 % (3 MB)
99 20:24:38.489581 progress 20 % (5 MB)
100 20:24:38.693060 progress 25 % (6 MB)
101 20:24:38.895354 progress 30 % (7 MB)
102 20:24:39.098486 progress 35 % (9 MB)
103 20:24:39.293166 progress 40 % (10 MB)
104 20:24:39.486084 progress 45 % (11 MB)
105 20:24:39.700996 progress 50 % (13 MB)
106 20:24:39.901178 progress 55 % (14 MB)
107 20:24:40.116358 progress 60 % (15 MB)
108 20:24:40.321175 progress 65 % (17 MB)
109 20:24:40.522651 progress 70 % (18 MB)
110 20:24:40.747124 progress 75 % (19 MB)
111 20:24:40.956114 progress 80 % (21 MB)
112 20:24:41.162015 progress 85 % (22 MB)
113 20:24:41.368027 progress 90 % (23 MB)
114 20:24:41.566998 progress 95 % (25 MB)
115 20:24:41.767900 progress 100 % (26 MB)
116 20:24:41.779617 26 MB downloaded in 4.18 s (6.31 MB/s)
117 20:24:41.780647 end: 1.4.1 http-download (duration 00:00:04) [common]
119 20:24:41.782819 end: 1.4 download-retry (duration 00:00:04) [common]
120 20:24:41.783530 start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
121 20:24:41.784253 start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
122 20:24:41.784919 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:24:41.785588 start: 1.5.2 lava-overlay (timeout 00:09:53) [common]
124 20:24:41.786949 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86
125 20:24:41.788113 makedir: /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin
126 20:24:41.789016 makedir: /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/tests
127 20:24:41.789855 makedir: /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/results
128 20:24:41.790658 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-add-keys
129 20:24:41.791931 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-add-sources
130 20:24:41.793238 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-background-process-start
131 20:24:41.794480 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-background-process-stop
132 20:24:41.795794 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-common-functions
133 20:24:41.797096 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-echo-ipv4
134 20:24:41.798357 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-install-packages
135 20:24:41.799554 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-installed-packages
136 20:24:41.800826 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-os-build
137 20:24:41.802019 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-probe-channel
138 20:24:41.803210 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-probe-ip
139 20:24:41.804443 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-target-ip
140 20:24:41.805632 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-target-mac
141 20:24:41.806805 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-target-storage
142 20:24:41.808020 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-test-case
143 20:24:41.809238 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-test-event
144 20:24:41.810400 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-test-feedback
145 20:24:41.811570 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-test-raise
146 20:24:41.812786 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-test-reference
147 20:24:41.813972 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-test-runner
148 20:24:41.815145 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-test-set
149 20:24:41.816390 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-test-shell
150 20:24:41.817626 Updating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-install-packages (oe)
151 20:24:41.818893 Updating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/bin/lava-installed-packages (oe)
152 20:24:41.820087 Creating /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/environment
153 20:24:41.820631 LAVA metadata
154 20:24:41.820966 - LAVA_JOB_ID=948429
155 20:24:41.821260 - LAVA_DISPATCHER_IP=192.168.6.2
156 20:24:41.821740 start: 1.5.2.1 ssh-authorize (timeout 00:09:53) [common]
157 20:24:41.822988 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 20:24:41.823379 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:53) [common]
159 20:24:41.823651 skipped lava-vland-overlay
160 20:24:41.823957 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 20:24:41.824335 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:53) [common]
162 20:24:41.824628 skipped lava-multinode-overlay
163 20:24:41.824954 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 20:24:41.825285 start: 1.5.2.4 test-definition (timeout 00:09:53) [common]
165 20:24:41.825607 Loading test definitions
166 20:24:41.825966 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:53) [common]
167 20:24:41.826255 Using /lava-948429 at stage 0
168 20:24:41.827756 uuid=948429_1.5.2.4.1 testdef=None
169 20:24:41.828160 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 20:24:41.828516 start: 1.5.2.4.2 test-overlay (timeout 00:09:53) [common]
171 20:24:41.830769 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 20:24:41.831763 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:53) [common]
174 20:24:41.834592 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 20:24:41.835628 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:53) [common]
177 20:24:41.838344 runner path: /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/0/tests/0_dmesg test_uuid 948429_1.5.2.4.1
178 20:24:41.839044 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 20:24:41.840017 Creating lava-test-runner.conf files
181 20:24:41.840291 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/948429/lava-overlay-y4b_jh86/lava-948429/0 for stage 0
182 20:24:41.840810 - 0_dmesg
183 20:24:41.841264 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 20:24:41.841613 start: 1.5.2.5 compress-overlay (timeout 00:09:53) [common]
185 20:24:41.870540 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 20:24:41.871033 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:53) [common]
187 20:24:41.871380 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 20:24:41.871722 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 20:24:41.872086 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
190 20:24:42.809996 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 20:24:42.810472 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
192 20:24:42.810744 extracting modules file /var/lib/lava/dispatcher/tmp/948429/tftp-deploy-0paqgbzk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/948429/extract-overlay-ramdisk-dd49icjk/ramdisk
193 20:24:44.469187 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 20:24:44.469681 start: 1.5.5 apply-overlay-tftp (timeout 00:09:51) [common]
195 20:24:44.469958 [common] Applying overlay /var/lib/lava/dispatcher/tmp/948429/compress-overlay-trt01x96/overlay-1.5.2.5.tar.gz to ramdisk
196 20:24:44.470170 [common] Applying overlay /var/lib/lava/dispatcher/tmp/948429/compress-overlay-trt01x96/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/948429/extract-overlay-ramdisk-dd49icjk/ramdisk
197 20:24:44.500429 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 20:24:44.500860 start: 1.5.6 prepare-kernel (timeout 00:09:51) [common]
199 20:24:44.501130 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:51) [common]
200 20:24:44.501358 Converting downloaded kernel to a uImage
201 20:24:44.501668 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/948429/tftp-deploy-0paqgbzk/kernel/Image /var/lib/lava/dispatcher/tmp/948429/tftp-deploy-0paqgbzk/kernel/uImage
202 20:24:46.178103 output: Image Name:
203 20:24:46.178580 output: Created: Wed Nov 6 20:24:44 2024
204 20:24:46.178811 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 20:24:46.179020 output: Data Size: 169943552 Bytes = 165960.50 KiB = 162.07 MiB
206 20:24:46.179227 output: Load Address: 01080000
207 20:24:46.179430 output: Entry Point: 01080000
208 20:24:46.179640 output:
209 20:24:46.180059 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 20:24:46.180426 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 20:24:46.180747 start: 1.5.7 configure-preseed-file (timeout 00:09:49) [common]
212 20:24:46.181058 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 20:24:46.181370 start: 1.5.8 compress-ramdisk (timeout 00:09:49) [common]
214 20:24:46.181684 Building ramdisk /var/lib/lava/dispatcher/tmp/948429/extract-overlay-ramdisk-dd49icjk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/948429/extract-overlay-ramdisk-dd49icjk/ramdisk
215 20:24:51.664885 >> 441545 blocks
216 20:25:09.960776 Adding RAMdisk u-boot header.
217 20:25:09.961487 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/948429/extract-overlay-ramdisk-dd49icjk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/948429/extract-overlay-ramdisk-dd49icjk/ramdisk.cpio.gz.uboot
218 20:25:10.618211 output: Image Name:
219 20:25:10.618626 output: Created: Wed Nov 6 20:25:09 2024
220 20:25:10.618834 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 20:25:10.619039 output: Data Size: 53579683 Bytes = 52323.91 KiB = 51.10 MiB
222 20:25:10.619240 output: Load Address: 00000000
223 20:25:10.619437 output: Entry Point: 00000000
224 20:25:10.619632 output:
225 20:25:10.620590 rename /var/lib/lava/dispatcher/tmp/948429/extract-overlay-ramdisk-dd49icjk/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/948429/tftp-deploy-0paqgbzk/ramdisk/ramdisk.cpio.gz.uboot
226 20:25:10.621320 end: 1.5.8 compress-ramdisk (duration 00:00:24) [common]
227 20:25:10.621852 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
228 20:25:10.622367 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:25) [common]
229 20:25:10.622815 No LXC device requested
230 20:25:10.623302 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 20:25:10.623800 start: 1.7 deploy-device-env (timeout 00:09:24) [common]
232 20:25:10.624336 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 20:25:10.624748 Checking files for TFTP limit of 4294967296 bytes.
234 20:25:10.627369 end: 1 tftp-deploy (duration 00:00:36) [common]
235 20:25:10.627932 start: 2 uboot-action (timeout 00:05:00) [common]
236 20:25:10.628487 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 20:25:10.628981 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 20:25:10.629473 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 20:25:10.629995 Using kernel file from prepare-kernel: 948429/tftp-deploy-0paqgbzk/kernel/uImage
240 20:25:10.630611 substitutions:
241 20:25:10.631018 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 20:25:10.631414 - {DTB_ADDR}: 0x01070000
243 20:25:10.631808 - {DTB}: 948429/tftp-deploy-0paqgbzk/dtb/meson-g12b-a311d-libretech-cc.dtb
244 20:25:10.632238 - {INITRD}: 948429/tftp-deploy-0paqgbzk/ramdisk/ramdisk.cpio.gz.uboot
245 20:25:10.632632 - {KERNEL_ADDR}: 0x01080000
246 20:25:10.633022 - {KERNEL}: 948429/tftp-deploy-0paqgbzk/kernel/uImage
247 20:25:10.633415 - {LAVA_MAC}: None
248 20:25:10.633839 - {PRESEED_CONFIG}: None
249 20:25:10.634229 - {PRESEED_LOCAL}: None
250 20:25:10.634614 - {RAMDISK_ADDR}: 0x08000000
251 20:25:10.634999 - {RAMDISK}: 948429/tftp-deploy-0paqgbzk/ramdisk/ramdisk.cpio.gz.uboot
252 20:25:10.635389 - {ROOT_PART}: None
253 20:25:10.635781 - {ROOT}: None
254 20:25:10.636199 - {SERVER_IP}: 192.168.6.2
255 20:25:10.636593 - {TEE_ADDR}: 0x83000000
256 20:25:10.636980 - {TEE}: None
257 20:25:10.637368 Parsed boot commands:
258 20:25:10.637744 - setenv autoload no
259 20:25:10.638128 - setenv initrd_high 0xffffffff
260 20:25:10.638510 - setenv fdt_high 0xffffffff
261 20:25:10.638890 - dhcp
262 20:25:10.639274 - setenv serverip 192.168.6.2
263 20:25:10.639654 - tftpboot 0x01080000 948429/tftp-deploy-0paqgbzk/kernel/uImage
264 20:25:10.640061 - tftpboot 0x08000000 948429/tftp-deploy-0paqgbzk/ramdisk/ramdisk.cpio.gz.uboot
265 20:25:10.640449 - tftpboot 0x01070000 948429/tftp-deploy-0paqgbzk/dtb/meson-g12b-a311d-libretech-cc.dtb
266 20:25:10.640834 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 20:25:10.641224 - bootm 0x01080000 0x08000000 0x01070000
268 20:25:10.641713 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 20:25:10.643175 start: 2.3 connect-device (timeout 00:05:00) [common]
271 20:25:10.643606 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 20:25:10.658560 Setting prompt string to ['lava-test: # ']
273 20:25:10.660056 end: 2.3 connect-device (duration 00:00:00) [common]
274 20:25:10.660656 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 20:25:10.661193 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 20:25:10.661700 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 20:25:10.662839 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 20:25:10.700101 >> OK - accepted request
279 20:25:10.702132 Returned 0 in 0 seconds
280 20:25:10.803255 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 20:25:10.804914 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 20:25:10.805474 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 20:25:10.805977 Setting prompt string to ['Hit any key to stop autoboot']
285 20:25:10.806414 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 20:25:10.808029 Trying 192.168.56.21...
287 20:25:10.808504 Connected to conserv1.
288 20:25:10.808920 Escape character is '^]'.
289 20:25:10.809338
290 20:25:10.809755 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 20:25:10.810176
292 20:25:21.750363 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 20:25:21.751011 bl2_stage_init 0x01
294 20:25:21.751444 bl2_stage_init 0x81
295 20:25:21.756017 hw id: 0x0000 - pwm id 0x01
296 20:25:21.756538 bl2_stage_init 0xc1
297 20:25:21.756954 bl2_stage_init 0x02
298 20:25:21.757362
299 20:25:21.761418 L0:00000000
300 20:25:21.761864 L1:20000703
301 20:25:21.762255 L2:00008067
302 20:25:21.762642 L3:14000000
303 20:25:21.764312 B2:00402000
304 20:25:21.764732 B1:e0f83180
305 20:25:21.765129
306 20:25:21.765520 TE: 58124
307 20:25:21.765908
308 20:25:21.775472 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 20:25:21.775907
310 20:25:21.776336 Board ID = 1
311 20:25:21.776722 Set A53 clk to 24M
312 20:25:21.777108 Set A73 clk to 24M
313 20:25:21.781089 Set clk81 to 24M
314 20:25:21.781507 A53 clk: 1200 MHz
315 20:25:21.781893 A73 clk: 1200 MHz
316 20:25:21.786802 CLK81: 166.6M
317 20:25:21.787226 smccc: 00012a91
318 20:25:21.792242 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 20:25:21.792674 board id: 1
320 20:25:21.800932 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 20:25:21.811497 fw parse done
322 20:25:21.817499 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 20:25:21.860124 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 20:25:21.870993 PIEI prepare done
325 20:25:21.871432 fastboot data load
326 20:25:21.871824 fastboot data verify
327 20:25:21.876696 verify result: 266
328 20:25:21.882310 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 20:25:21.882780 LPDDR4 probe
330 20:25:21.883171 ddr clk to 1584MHz
331 20:25:21.890343 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 20:25:21.927533
333 20:25:21.928140 dmc_version 0001
334 20:25:21.934140 Check phy result
335 20:25:21.940101 INFO : End of CA training
336 20:25:21.940603 INFO : End of initialization
337 20:25:21.945644 INFO : Training has run successfully!
338 20:25:21.946121 Check phy result
339 20:25:21.951230 INFO : End of initialization
340 20:25:21.951692 INFO : End of read enable training
341 20:25:21.954524 INFO : End of fine write leveling
342 20:25:21.960099 INFO : End of Write leveling coarse delay
343 20:25:21.965637 INFO : Training has run successfully!
344 20:25:21.966057 Check phy result
345 20:25:21.966452 INFO : End of initialization
346 20:25:21.971264 INFO : End of read dq deskew training
347 20:25:21.974651 INFO : End of MPR read delay center optimization
348 20:25:21.980321 INFO : End of write delay center optimization
349 20:25:21.985957 INFO : End of read delay center optimization
350 20:25:21.986389 INFO : End of max read latency training
351 20:25:21.991441 INFO : Training has run successfully!
352 20:25:21.991864 1D training succeed
353 20:25:21.999585 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 20:25:22.047370 Check phy result
355 20:25:22.047949 INFO : End of initialization
356 20:25:22.069067 INFO : End of 2D read delay Voltage center optimization
357 20:25:22.089216 INFO : End of 2D read delay Voltage center optimization
358 20:25:22.141483 INFO : End of 2D write delay Voltage center optimization
359 20:25:22.190801 INFO : End of 2D write delay Voltage center optimization
360 20:25:22.196290 INFO : Training has run successfully!
361 20:25:22.196735
362 20:25:22.197136 channel==0
363 20:25:22.201875 RxClkDly_Margin_A0==88 ps 9
364 20:25:22.202302 TxDqDly_Margin_A0==98 ps 10
365 20:25:22.205161 RxClkDly_Margin_A1==88 ps 9
366 20:25:22.205590 TxDqDly_Margin_A1==98 ps 10
367 20:25:22.210697 TrainedVREFDQ_A0==74
368 20:25:22.211124 TrainedVREFDQ_A1==74
369 20:25:22.216298 VrefDac_Margin_A0==25
370 20:25:22.216731 DeviceVref_Margin_A0==40
371 20:25:22.217126 VrefDac_Margin_A1==24
372 20:25:22.221992 DeviceVref_Margin_A1==40
373 20:25:22.222479
374 20:25:22.222910
375 20:25:22.223337 channel==1
376 20:25:22.223757 RxClkDly_Margin_A0==98 ps 10
377 20:25:22.225368 TxDqDly_Margin_A0==98 ps 10
378 20:25:22.230996 RxClkDly_Margin_A1==88 ps 9
379 20:25:22.231464 TxDqDly_Margin_A1==88 ps 9
380 20:25:22.231865 TrainedVREFDQ_A0==77
381 20:25:22.236577 TrainedVREFDQ_A1==77
382 20:25:22.237074 VrefDac_Margin_A0==22
383 20:25:22.242166 DeviceVref_Margin_A0==37
384 20:25:22.242645 VrefDac_Margin_A1==24
385 20:25:22.243038 DeviceVref_Margin_A1==37
386 20:25:22.243427
387 20:25:22.251167 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 20:25:22.251643
389 20:25:22.282039 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 20:25:22.282633 2D training succeed
391 20:25:22.287645 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 20:25:22.293116 auto size-- 65535DDR cs0 size: 2048MB
393 20:25:22.293628 DDR cs1 size: 2048MB
394 20:25:22.298748 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 20:25:22.299221 cs0 DataBus test pass
396 20:25:22.299635 cs1 DataBus test pass
397 20:25:22.304353 cs0 AddrBus test pass
398 20:25:22.304822 cs1 AddrBus test pass
399 20:25:22.305233
400 20:25:22.305636 100bdlr_step_size ps== 420
401 20:25:22.309940 result report
402 20:25:22.310406 boot times 0Enable ddr reg access
403 20:25:22.319083 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 20:25:22.332579 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 20:25:22.906254 0.0;M3 CHK:0;cm4_sp_mode 0
406 20:25:22.906862 MVN_1=0x00000000
407 20:25:22.912034 MVN_2=0x00000000
408 20:25:22.917454 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 20:25:22.917930 OPS=0x10
410 20:25:22.918346 ring efuse init
411 20:25:22.918747 chipver efuse init
412 20:25:22.923035 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 20:25:22.928971 [0.018961 Inits done]
414 20:25:22.929431 secure task start!
415 20:25:22.929843 high task start!
416 20:25:22.933243 low task start!
417 20:25:22.933722 run into bl31
418 20:25:22.939949 NOTICE: BL31: v1.3(release):4fc40b1
419 20:25:22.947789 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 20:25:22.948355 NOTICE: BL31: G12A normal boot!
421 20:25:22.973033 NOTICE: BL31: BL33 decompress pass
422 20:25:22.979099 ERROR: Error initializing runtime service opteed_fast
423 20:25:24.211667
424 20:25:24.212346
425 20:25:24.220048 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 20:25:24.220528
427 20:25:24.220953 Model: Libre Computer AML-A311D-CC Alta
428 20:25:24.428468 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 20:25:24.452172 DRAM: 2 GiB (effective 3.8 GiB)
430 20:25:24.594874 Core: 408 devices, 31 uclasses, devicetree: separate
431 20:25:24.600715 WDT: Not starting watchdog@f0d0
432 20:25:24.632937 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 20:25:24.645424 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 20:25:24.650412 ** Bad device specification mmc 0 **
435 20:25:24.660716 Card did not respond to voltage select! : -110
436 20:25:24.668417 ** Bad device specification mmc 0 **
437 20:25:24.668947 Couldn't find partition mmc 0
438 20:25:24.676698 Card did not respond to voltage select! : -110
439 20:25:24.682234 ** Bad device specification mmc 0 **
440 20:25:24.682718 Couldn't find partition mmc 0
441 20:25:24.687400 Error: could not access storage.
442 20:25:25.952804 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 20:25:25.953437 bl2_stage_init 0x01
444 20:25:25.953882 bl2_stage_init 0x81
445 20:25:25.957632 hw id: 0x0000 - pwm id 0x01
446 20:25:25.958188 bl2_stage_init 0xc1
447 20:25:25.958646 bl2_stage_init 0x02
448 20:25:25.959069
449 20:25:25.962003 L0:00000000
450 20:25:25.962455 L1:20000703
451 20:25:25.962866 L2:00008067
452 20:25:25.963267 L3:14000000
453 20:25:25.971075 B2:00402000
454 20:25:25.971541 B1:e0f83180
455 20:25:25.971949
456 20:25:25.972412 TE: 58124
457 20:25:25.972822
458 20:25:25.973678 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 20:25:25.974124
460 20:25:25.974530 Board ID = 1
461 20:25:25.979188 Set A53 clk to 24M
462 20:25:25.979655 Set A73 clk to 24M
463 20:25:25.980109 Set clk81 to 24M
464 20:25:25.984385 A53 clk: 1200 MHz
465 20:25:25.984832 A73 clk: 1200 MHz
466 20:25:25.985235 CLK81: 166.6M
467 20:25:25.985629 smccc: 00012a92
468 20:25:25.990061 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 20:25:25.996753 board id: 1
470 20:25:26.001498 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 20:25:26.013466 fw parse done
472 20:25:26.018768 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 20:25:26.060732 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 20:25:26.072678 PIEI prepare done
475 20:25:26.073257 fastboot data load
476 20:25:26.073728 fastboot data verify
477 20:25:26.077367 verify result: 266
478 20:25:26.082917 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 20:25:26.083437 LPDDR4 probe
480 20:25:26.083871 ddr clk to 1584MHz
481 20:25:26.092289 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 20:25:26.129211
483 20:25:26.129823 dmc_version 0001
484 20:25:26.135344 Check phy result
485 20:25:26.140717 INFO : End of CA training
486 20:25:26.141242 INFO : End of initialization
487 20:25:26.152243 INFO : Training has run successfully!
488 20:25:26.152794 Check phy result
489 20:25:26.153544 INFO : End of initialization
490 20:25:26.153979 INFO : End of read enable training
491 20:25:26.157518 INFO : End of fine write leveling
492 20:25:26.173901 INFO : End of Write leveling coarse delay
493 20:25:26.174504 INFO : Training has run successfully!
494 20:25:26.175040 Check phy result
495 20:25:26.175469 INFO : End of initialization
496 20:25:26.175870 INFO : End of read dq deskew training
497 20:25:26.176653 INFO : End of MPR read delay center optimization
498 20:25:26.180059 INFO : End of write delay center optimization
499 20:25:26.188563 INFO : End of read delay center optimization
500 20:25:26.189134 INFO : End of max read latency training
501 20:25:26.191089 INFO : Training has run successfully!
502 20:25:26.191605 1D training succeed
503 20:25:26.204141 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 20:25:26.249146 Check phy result
505 20:25:26.249765 INFO : End of initialization
506 20:25:26.269676 INFO : End of 2D read delay Voltage center optimization
507 20:25:26.290213 INFO : End of 2D read delay Voltage center optimization
508 20:25:26.344433 INFO : End of 2D write delay Voltage center optimization
509 20:25:26.391319 INFO : End of 2D write delay Voltage center optimization
510 20:25:26.398586 INFO : Training has run successfully!
511 20:25:26.399135
512 20:25:26.399567 channel==0
513 20:25:26.403812 RxClkDly_Margin_A0==88 ps 9
514 20:25:26.404448 TxDqDly_Margin_A0==98 ps 10
515 20:25:26.408103 RxClkDly_Margin_A1==88 ps 9
516 20:25:26.408623 TxDqDly_Margin_A1==98 ps 10
517 20:25:26.409070 TrainedVREFDQ_A0==74
518 20:25:26.413726 TrainedVREFDQ_A1==74
519 20:25:26.414253 VrefDac_Margin_A0==25
520 20:25:26.414686 DeviceVref_Margin_A0==40
521 20:25:26.419516 VrefDac_Margin_A1==25
522 20:25:26.420069 DeviceVref_Margin_A1==40
523 20:25:26.420482
524 20:25:26.420867
525 20:25:26.424865 channel==1
526 20:25:26.425360 RxClkDly_Margin_A0==98 ps 10
527 20:25:26.425780 TxDqDly_Margin_A0==88 ps 9
528 20:25:26.430577 RxClkDly_Margin_A1==88 ps 9
529 20:25:26.431089 TxDqDly_Margin_A1==88 ps 9
530 20:25:26.438207 TrainedVREFDQ_A0==77
531 20:25:26.438760 TrainedVREFDQ_A1==77
532 20:25:26.439186 VrefDac_Margin_A0==22
533 20:25:26.443196 DeviceVref_Margin_A0==37
534 20:25:26.443941 VrefDac_Margin_A1==24
535 20:25:26.448270 DeviceVref_Margin_A1==37
536 20:25:26.448847
537 20:25:26.449286 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 20:25:26.449693
539 20:25:26.482288 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
540 20:25:26.482903 2D training succeed
541 20:25:26.487740 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 20:25:26.492077 auto size-- 65535DDR cs0 size: 2048MB
543 20:25:26.492602 DDR cs1 size: 2048MB
544 20:25:26.500205 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 20:25:26.500768 cs0 DataBus test pass
546 20:25:26.503261 cs1 DataBus test pass
547 20:25:26.503801 cs0 AddrBus test pass
548 20:25:26.504316 cs1 AddrBus test pass
549 20:25:26.504749
550 20:25:26.508837 100bdlr_step_size ps== 420
551 20:25:26.509343 result report
552 20:25:26.517387 boot times 0Enable ddr reg access
553 20:25:26.521624 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 20:25:26.540705 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 20:25:27.107197 0.0;M3 CHK:0;cm4_sp_mode 0
556 20:25:27.107830 MVN_1=0x00000000
557 20:25:27.112353 MVN_2=0x00000000
558 20:25:27.118656 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 20:25:27.119171 OPS=0x10
560 20:25:27.119584 ring efuse init
561 20:25:27.120023 chipver efuse init
562 20:25:27.128278 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 20:25:27.130491 [0.018961 Inits done]
564 20:25:27.131004 secure task start!
565 20:25:27.131403 high task start!
566 20:25:27.133813 low task start!
567 20:25:27.134297 run into bl31
568 20:25:27.141719 NOTICE: BL31: v1.3(release):4fc40b1
569 20:25:27.149097 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 20:25:27.149555 NOTICE: BL31: G12A normal boot!
571 20:25:27.173635 NOTICE: BL31: BL33 decompress pass
572 20:25:27.180474 ERROR: Error initializing runtime service opteed_fast
573 20:25:28.412335
574 20:25:28.412971
575 20:25:28.420673 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 20:25:28.421219
577 20:25:28.421447 Model: Libre Computer AML-A311D-CC Alta
578 20:25:28.629179 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 20:25:28.652553 DRAM: 2 GiB (effective 3.8 GiB)
580 20:25:28.795485 Core: 408 devices, 31 uclasses, devicetree: separate
581 20:25:28.801400 WDT: Not starting watchdog@f0d0
582 20:25:28.833566 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 20:25:28.845994 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 20:25:28.851136 ** Bad device specification mmc 0 **
585 20:25:28.861401 Card did not respond to voltage select! : -110
586 20:25:28.868997 ** Bad device specification mmc 0 **
587 20:25:28.869449 Couldn't find partition mmc 0
588 20:25:28.877397 Card did not respond to voltage select! : -110
589 20:25:28.882917 ** Bad device specification mmc 0 **
590 20:25:28.883362 Couldn't find partition mmc 0
591 20:25:28.887966 Error: could not access storage.
592 20:25:29.231417 Net: eth0: ethernet@ff3f0000
593 20:25:29.232019 starting USB...
594 20:25:29.483565 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 20:25:29.484258 Starting the controller
596 20:25:29.490383 USB XHCI 1.10
597 20:25:31.199738 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 20:25:31.200387 bl2_stage_init 0x01
599 20:25:31.200819 bl2_stage_init 0x81
600 20:25:31.205217 hw id: 0x0000 - pwm id 0x01
601 20:25:31.205664 bl2_stage_init 0xc1
602 20:25:31.206073 bl2_stage_init 0x02
603 20:25:31.206475
604 20:25:31.210853 L0:00000000
605 20:25:31.211290 L1:20000703
606 20:25:31.211699 L2:00008067
607 20:25:31.212132 L3:14000000
608 20:25:31.216362 B2:00402000
609 20:25:31.216805 B1:e0f83180
610 20:25:31.217207
611 20:25:31.217613 TE: 58167
612 20:25:31.218013
613 20:25:31.221960 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 20:25:31.222408
615 20:25:31.222818 Board ID = 1
616 20:25:31.227636 Set A53 clk to 24M
617 20:25:31.228109 Set A73 clk to 24M
618 20:25:31.228519 Set clk81 to 24M
619 20:25:31.233200 A53 clk: 1200 MHz
620 20:25:31.233636 A73 clk: 1200 MHz
621 20:25:31.234040 CLK81: 166.6M
622 20:25:31.234436 smccc: 00012abd
623 20:25:31.238919 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 20:25:31.244348 board id: 1
625 20:25:31.250378 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 20:25:31.260989 fw parse done
627 20:25:31.266991 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 20:25:31.309420 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 20:25:31.320315 PIEI prepare done
630 20:25:31.320769 fastboot data load
631 20:25:31.321182 fastboot data verify
632 20:25:31.326033 verify result: 266
633 20:25:31.331561 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 20:25:31.332052 LPDDR4 probe
635 20:25:31.332474 ddr clk to 1584MHz
636 20:25:31.339573 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 20:25:31.376959
638 20:25:31.377521 dmc_version 0001
639 20:25:31.383589 Check phy result
640 20:25:31.389421 INFO : End of CA training
641 20:25:31.389902 INFO : End of initialization
642 20:25:31.395053 INFO : Training has run successfully!
643 20:25:31.395557 Check phy result
644 20:25:31.400680 INFO : End of initialization
645 20:25:31.401192 INFO : End of read enable training
646 20:25:31.406288 INFO : End of fine write leveling
647 20:25:31.419746 INFO : End of Write leveling coarse delay
648 20:25:31.420310 INFO : Training has run successfully!
649 20:25:31.420728 Check phy result
650 20:25:31.421131 INFO : End of initialization
651 20:25:31.422150 INFO : End of read dq deskew training
652 20:25:31.422666 INFO : End of MPR read delay center optimization
653 20:25:31.427709 INFO : End of write delay center optimization
654 20:25:31.433329 INFO : End of read delay center optimization
655 20:25:31.438911 INFO : End of max read latency training
656 20:25:31.439423 INFO : Training has run successfully!
657 20:25:31.439846 1D training succeed
658 20:25:31.449335 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 20:25:31.496629 Check phy result
660 20:25:31.497179 INFO : End of initialization
661 20:25:31.519264 INFO : End of 2D read delay Voltage center optimization
662 20:25:31.539413 INFO : End of 2D read delay Voltage center optimization
663 20:25:31.591459 INFO : End of 2D write delay Voltage center optimization
664 20:25:31.640820 INFO : End of 2D write delay Voltage center optimization
665 20:25:31.646358 INFO : Training has run successfully!
666 20:25:31.646857
667 20:25:31.647285 channel==0
668 20:25:31.651963 RxClkDly_Margin_A0==88 ps 9
669 20:25:31.652491 TxDqDly_Margin_A0==98 ps 10
670 20:25:31.657567 RxClkDly_Margin_A1==88 ps 9
671 20:25:31.658060 TxDqDly_Margin_A1==98 ps 10
672 20:25:31.658485 TrainedVREFDQ_A0==74
673 20:25:31.663165 TrainedVREFDQ_A1==75
674 20:25:31.663658 VrefDac_Margin_A0==24
675 20:25:31.664108 DeviceVref_Margin_A0==40
676 20:25:31.668758 VrefDac_Margin_A1==24
677 20:25:31.669243 DeviceVref_Margin_A1==39
678 20:25:31.669653
679 20:25:31.670054
680 20:25:31.674339 channel==1
681 20:25:31.674829 RxClkDly_Margin_A0==88 ps 9
682 20:25:31.675236 TxDqDly_Margin_A0==98 ps 10
683 20:25:31.679921 RxClkDly_Margin_A1==88 ps 9
684 20:25:31.680435 TxDqDly_Margin_A1==88 ps 9
685 20:25:31.685536 TrainedVREFDQ_A0==77
686 20:25:31.686028 TrainedVREFDQ_A1==77
687 20:25:31.686442 VrefDac_Margin_A0==22
688 20:25:31.691160 DeviceVref_Margin_A0==37
689 20:25:31.691666 VrefDac_Margin_A1==24
690 20:25:31.696801 DeviceVref_Margin_A1==37
691 20:25:31.697300
692 20:25:31.697710 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 20:25:31.698115
694 20:25:31.730300 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000018 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
695 20:25:31.730842 2D training succeed
696 20:25:31.735971 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 20:25:31.741562 auto size-- 65535DDR cs0 size: 2048MB
698 20:25:31.742048 DDR cs1 size: 2048MB
699 20:25:31.747154 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 20:25:31.747637 cs0 DataBus test pass
701 20:25:31.752754 cs1 DataBus test pass
702 20:25:31.753245 cs0 AddrBus test pass
703 20:25:31.753655 cs1 AddrBus test pass
704 20:25:31.754055
705 20:25:31.758352 100bdlr_step_size ps== 420
706 20:25:31.758843 result report
707 20:25:31.764005 boot times 0Enable ddr reg access
708 20:25:31.769251 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 20:25:31.782629 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 20:25:32.356549 0.0;M3 CHK:0;cm4_sp_mode 0
711 20:25:32.357153 MVN_1=0x00000000
712 20:25:32.361989 MVN_2=0x00000000
713 20:25:32.367718 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 20:25:32.368284 OPS=0x10
715 20:25:32.368686 ring efuse init
716 20:25:32.369074 chipver efuse init
717 20:25:32.373394 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 20:25:32.378860 [0.018960 Inits done]
719 20:25:32.379326 secure task start!
720 20:25:32.379718 high task start!
721 20:25:32.383463 low task start!
722 20:25:32.383925 run into bl31
723 20:25:32.390113 NOTICE: BL31: v1.3(release):4fc40b1
724 20:25:32.397944 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 20:25:32.398440 NOTICE: BL31: G12A normal boot!
726 20:25:32.423379 NOTICE: BL31: BL33 decompress pass
727 20:25:32.429034 ERROR: Error initializing runtime service opteed_fast
728 20:25:33.661954
729 20:25:33.662597
730 20:25:33.670468 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 20:25:33.671116
732 20:25:33.671560 Model: Libre Computer AML-A311D-CC Alta
733 20:25:33.879440 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 20:25:33.902277 DRAM: 2 GiB (effective 3.8 GiB)
735 20:25:34.045019 Core: 408 devices, 31 uclasses, devicetree: separate
736 20:25:34.050805 WDT: Not starting watchdog@f0d0
737 20:25:34.083044 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 20:25:34.095528 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 20:25:34.100567 ** Bad device specification mmc 0 **
740 20:25:34.110831 Card did not respond to voltage select! : -110
741 20:25:34.118531 ** Bad device specification mmc 0 **
742 20:25:34.118966 Couldn't find partition mmc 0
743 20:25:34.126820 Card did not respond to voltage select! : -110
744 20:25:34.132514 ** Bad device specification mmc 0 **
745 20:25:34.132949 Couldn't find partition mmc 0
746 20:25:34.137385 Error: could not access storage.
747 20:25:34.480890 Net: eth0: ethernet@ff3f0000
748 20:25:34.481378 starting USB...
749 20:25:34.732712 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 20:25:34.733169 Starting the controller
751 20:25:34.739684 USB XHCI 1.10
752 20:25:36.899555 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 20:25:36.900157 bl2_stage_init 0x01
754 20:25:36.900580 bl2_stage_init 0x81
755 20:25:36.905158 hw id: 0x0000 - pwm id 0x01
756 20:25:36.905601 bl2_stage_init 0xc1
757 20:25:36.906009 bl2_stage_init 0x02
758 20:25:36.906410
759 20:25:36.910808 L0:00000000
760 20:25:36.911238 L1:20000703
761 20:25:36.911637 L2:00008067
762 20:25:36.912064 L3:14000000
763 20:25:36.913674 B2:00402000
764 20:25:36.914095 B1:e0f83180
765 20:25:36.914496
766 20:25:36.914895 TE: 58167
767 20:25:36.915291
768 20:25:36.924933 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 20:25:36.925380
770 20:25:36.925801 Board ID = 1
771 20:25:36.926198 Set A53 clk to 24M
772 20:25:36.926591 Set A73 clk to 24M
773 20:25:36.930470 Set clk81 to 24M
774 20:25:36.930902 A53 clk: 1200 MHz
775 20:25:36.931303 A73 clk: 1200 MHz
776 20:25:36.933991 CLK81: 166.6M
777 20:25:36.934418 smccc: 00012abe
778 20:25:36.939505 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 20:25:36.945021 board id: 1
780 20:25:36.950280 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 20:25:36.960729 fw parse done
782 20:25:36.966701 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 20:25:37.009300 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 20:25:37.020296 PIEI prepare done
785 20:25:37.020738 fastboot data load
786 20:25:37.021143 fastboot data verify
787 20:25:37.025926 verify result: 266
788 20:25:37.031459 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 20:25:37.031888 LPDDR4 probe
790 20:25:37.032338 ddr clk to 1584MHz
791 20:25:37.039436 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 20:25:37.076666
793 20:25:37.077097 dmc_version 0001
794 20:25:37.083388 Check phy result
795 20:25:37.089258 INFO : End of CA training
796 20:25:37.089683 INFO : End of initialization
797 20:25:37.094919 INFO : Training has run successfully!
798 20:25:37.095341 Check phy result
799 20:25:37.100449 INFO : End of initialization
800 20:25:37.100877 INFO : End of read enable training
801 20:25:37.103797 INFO : End of fine write leveling
802 20:25:37.109373 INFO : End of Write leveling coarse delay
803 20:25:37.114972 INFO : Training has run successfully!
804 20:25:37.115396 Check phy result
805 20:25:37.115796 INFO : End of initialization
806 20:25:37.120560 INFO : End of read dq deskew training
807 20:25:37.123918 INFO : End of MPR read delay center optimization
808 20:25:37.129490 INFO : End of write delay center optimization
809 20:25:37.135107 INFO : End of read delay center optimization
810 20:25:37.135530 INFO : End of max read latency training
811 20:25:37.140699 INFO : Training has run successfully!
812 20:25:37.141124 1D training succeed
813 20:25:37.148894 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 20:25:37.196407 Check phy result
815 20:25:37.196830 INFO : End of initialization
816 20:25:37.218029 INFO : End of 2D read delay Voltage center optimization
817 20:25:37.238115 INFO : End of 2D read delay Voltage center optimization
818 20:25:37.290056 INFO : End of 2D write delay Voltage center optimization
819 20:25:37.339249 INFO : End of 2D write delay Voltage center optimization
820 20:25:37.345038 INFO : Training has run successfully!
821 20:25:37.345472
822 20:25:37.345879 channel==0
823 20:25:37.350612 RxClkDly_Margin_A0==88 ps 9
824 20:25:37.351033 TxDqDly_Margin_A0==98 ps 10
825 20:25:37.356719 RxClkDly_Margin_A1==88 ps 9
826 20:25:37.357138 TxDqDly_Margin_A1==88 ps 9
827 20:25:37.357538 TrainedVREFDQ_A0==74
828 20:25:37.361728 TrainedVREFDQ_A1==74
829 20:25:37.362194 VrefDac_Margin_A0==25
830 20:25:37.362604 DeviceVref_Margin_A0==40
831 20:25:37.367305 VrefDac_Margin_A1==25
832 20:25:37.367764 DeviceVref_Margin_A1==40
833 20:25:37.368185
834 20:25:37.368572
835 20:25:37.368956 channel==1
836 20:25:37.372845 RxClkDly_Margin_A0==98 ps 10
837 20:25:37.373265 TxDqDly_Margin_A0==98 ps 10
838 20:25:37.378434 RxClkDly_Margin_A1==98 ps 10
839 20:25:37.378844 TxDqDly_Margin_A1==88 ps 9
840 20:25:37.384064 TrainedVREFDQ_A0==77
841 20:25:37.384475 TrainedVREFDQ_A1==77
842 20:25:37.384862 VrefDac_Margin_A0==22
843 20:25:37.389689 DeviceVref_Margin_A0==37
844 20:25:37.390099 VrefDac_Margin_A1==22
845 20:25:37.395283 DeviceVref_Margin_A1==37
846 20:25:37.395690
847 20:25:37.396100 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 20:25:37.396485
849 20:25:37.428863 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
850 20:25:37.429318 2D training succeed
851 20:25:37.434473 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 20:25:37.440065 auto size-- 65535DDR cs0 size: 2048MB
853 20:25:37.440480 DDR cs1 size: 2048MB
854 20:25:37.445659 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 20:25:37.446069 cs0 DataBus test pass
856 20:25:37.451248 cs1 DataBus test pass
857 20:25:37.451653 cs0 AddrBus test pass
858 20:25:37.452076 cs1 AddrBus test pass
859 20:25:37.452461
860 20:25:37.456864 100bdlr_step_size ps== 420
861 20:25:37.457284 result report
862 20:25:37.462420 boot times 0Enable ddr reg access
863 20:25:37.467793 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 20:25:37.481277 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 20:25:38.053196 0.0;M3 CHK:0;cm4_sp_mode 0
866 20:25:38.053699 MVN_1=0x00000000
867 20:25:38.058743 MVN_2=0x00000000
868 20:25:38.064502 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 20:25:38.064935 OPS=0x10
870 20:25:38.065341 ring efuse init
871 20:25:38.065736 chipver efuse init
872 20:25:38.070107 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 20:25:38.075705 [0.018961 Inits done]
874 20:25:38.076165 secure task start!
875 20:25:38.076566 high task start!
876 20:25:38.080032 low task start!
877 20:25:38.080482 run into bl31
878 20:25:38.087027 NOTICE: BL31: v1.3(release):4fc40b1
879 20:25:38.094748 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 20:25:38.095180 NOTICE: BL31: G12A normal boot!
881 20:25:38.120095 NOTICE: BL31: BL33 decompress pass
882 20:25:38.125796 ERROR: Error initializing runtime service opteed_fast
883 20:25:39.358833
884 20:25:39.359386
885 20:25:39.366527 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 20:25:39.367053
887 20:25:39.367481 Model: Libre Computer AML-A311D-CC Alta
888 20:25:39.575526 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 20:25:39.598911 DRAM: 2 GiB (effective 3.8 GiB)
890 20:25:39.741920 Core: 408 devices, 31 uclasses, devicetree: separate
891 20:25:39.747770 WDT: Not starting watchdog@f0d0
892 20:25:39.780082 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 20:25:39.792511 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 20:25:39.797487 ** Bad device specification mmc 0 **
895 20:25:39.807824 Card did not respond to voltage select! : -110
896 20:25:39.815495 ** Bad device specification mmc 0 **
897 20:25:39.816017 Couldn't find partition mmc 0
898 20:25:39.823818 Card did not respond to voltage select! : -110
899 20:25:39.829317 ** Bad device specification mmc 0 **
900 20:25:39.829771 Couldn't find partition mmc 0
901 20:25:39.834398 Error: could not access storage.
902 20:25:40.175931 Net: eth0: ethernet@ff3f0000
903 20:25:40.176520 starting USB...
904 20:25:40.428702 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 20:25:40.429263 Starting the controller
906 20:25:40.435656 USB XHCI 1.10
907 20:25:42.191112 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 20:25:42.191713 bl2_stage_init 0x01
909 20:25:42.192209 bl2_stage_init 0x81
910 20:25:42.196723 hw id: 0x0000 - pwm id 0x01
911 20:25:42.197185 bl2_stage_init 0xc1
912 20:25:42.197606 bl2_stage_init 0x02
913 20:25:42.198013
914 20:25:42.202206 L0:00000000
915 20:25:42.202661 L1:20000703
916 20:25:42.203071 L2:00008067
917 20:25:42.203470 L3:14000000
918 20:25:42.207917 B2:00402000
919 20:25:42.208402 B1:e0f83180
920 20:25:42.208815
921 20:25:42.209225 TE: 58167
922 20:25:42.209622
923 20:25:42.213447 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 20:25:42.213915
925 20:25:42.214323 Board ID = 1
926 20:25:42.219143 Set A53 clk to 24M
927 20:25:42.219657 Set A73 clk to 24M
928 20:25:42.220118 Set clk81 to 24M
929 20:25:42.224699 A53 clk: 1200 MHz
930 20:25:42.225157 A73 clk: 1200 MHz
931 20:25:42.225569 CLK81: 166.6M
932 20:25:42.225971 smccc: 00012abe
933 20:25:42.230302 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 20:25:42.235920 board id: 1
935 20:25:42.241904 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 20:25:42.252438 fw parse done
937 20:25:42.258467 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 20:25:42.300879 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 20:25:42.311778 PIEI prepare done
940 20:25:42.312301 fastboot data load
941 20:25:42.312722 fastboot data verify
942 20:25:42.317453 verify result: 266
943 20:25:42.323063 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 20:25:42.323571 LPDDR4 probe
945 20:25:42.324022 ddr clk to 1584MHz
946 20:25:42.331024 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 20:25:42.368237
948 20:25:42.368685 dmc_version 0001
949 20:25:42.374992 Check phy result
950 20:25:42.380842 INFO : End of CA training
951 20:25:42.381332 INFO : End of initialization
952 20:25:42.386426 INFO : Training has run successfully!
953 20:25:42.386857 Check phy result
954 20:25:42.392062 INFO : End of initialization
955 20:25:42.392492 INFO : End of read enable training
956 20:25:42.397961 INFO : End of fine write leveling
957 20:25:42.403296 INFO : End of Write leveling coarse delay
958 20:25:42.403717 INFO : Training has run successfully!
959 20:25:42.404138 Check phy result
960 20:25:42.408819 INFO : End of initialization
961 20:25:42.409244 INFO : End of read dq deskew training
962 20:25:42.414414 INFO : End of MPR read delay center optimization
963 20:25:42.420061 INFO : End of write delay center optimization
964 20:25:42.425714 INFO : End of read delay center optimization
965 20:25:42.426199 INFO : End of max read latency training
966 20:25:42.431218 INFO : Training has run successfully!
967 20:25:42.431651 1D training succeed
968 20:25:42.440391 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 20:25:42.487999 Check phy result
970 20:25:42.488488 INFO : End of initialization
971 20:25:42.510554 INFO : End of 2D read delay Voltage center optimization
972 20:25:42.530785 INFO : End of 2D read delay Voltage center optimization
973 20:25:42.582774 INFO : End of 2D write delay Voltage center optimization
974 20:25:42.632209 INFO : End of 2D write delay Voltage center optimization
975 20:25:42.637751 INFO : Training has run successfully!
976 20:25:42.638210
977 20:25:42.638626 channel==0
978 20:25:42.643331 RxClkDly_Margin_A0==98 ps 10
979 20:25:42.643778 TxDqDly_Margin_A0==98 ps 10
980 20:25:42.648938 RxClkDly_Margin_A1==88 ps 9
981 20:25:42.649384 TxDqDly_Margin_A1==98 ps 10
982 20:25:42.649794 TrainedVREFDQ_A0==74
983 20:25:42.654571 TrainedVREFDQ_A1==74
984 20:25:42.655016 VrefDac_Margin_A0==25
985 20:25:42.660146 DeviceVref_Margin_A0==40
986 20:25:42.660583 VrefDac_Margin_A1==24
987 20:25:42.660989 DeviceVref_Margin_A1==40
988 20:25:42.661388
989 20:25:42.661790
990 20:25:42.665741 channel==1
991 20:25:42.666188 RxClkDly_Margin_A0==98 ps 10
992 20:25:42.666597 TxDqDly_Margin_A0==88 ps 9
993 20:25:42.671308 RxClkDly_Margin_A1==98 ps 10
994 20:25:42.671756 TxDqDly_Margin_A1==88 ps 9
995 20:25:42.676934 TrainedVREFDQ_A0==76
996 20:25:42.677383 TrainedVREFDQ_A1==77
997 20:25:42.677791 VrefDac_Margin_A0==22
998 20:25:42.682575 DeviceVref_Margin_A0==38
999 20:25:42.683021 VrefDac_Margin_A1==22
1000 20:25:42.688152 DeviceVref_Margin_A1==37
1001 20:25:42.688595
1002 20:25:42.689003 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 20:25:42.693721
1004 20:25:42.721890 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1005 20:25:42.722423 2D training succeed
1006 20:25:42.727338 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 20:25:42.732943 auto size-- 65535DDR cs0 size: 2048MB
1008 20:25:42.733405 DDR cs1 size: 2048MB
1009 20:25:42.738560 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 20:25:42.739010 cs0 DataBus test pass
1011 20:25:42.744160 cs1 DataBus test pass
1012 20:25:42.744614 cs0 AddrBus test pass
1013 20:25:42.745020 cs1 AddrBus test pass
1014 20:25:42.745419
1015 20:25:42.749771 100bdlr_step_size ps== 420
1016 20:25:42.750229 result report
1017 20:25:42.755444 boot times 0Enable ddr reg access
1018 20:25:42.760872 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 20:25:42.774266 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 20:25:43.348077 0.0;M3 CHK:0;cm4_sp_mode 0
1021 20:25:43.348654 MVN_1=0x00000000
1022 20:25:43.353478 MVN_2=0x00000000
1023 20:25:43.359234 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 20:25:43.359700 OPS=0x10
1025 20:25:43.360155 ring efuse init
1026 20:25:43.360572 chipver efuse init
1027 20:25:43.367466 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 20:25:43.368010 [0.018961 Inits done]
1029 20:25:43.374114 secure task start!
1030 20:25:43.374613 high task start!
1031 20:25:43.375033 low task start!
1032 20:25:43.375439 run into bl31
1033 20:25:43.381859 NOTICE: BL31: v1.3(release):4fc40b1
1034 20:25:43.388748 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 20:25:43.389261 NOTICE: BL31: G12A normal boot!
1036 20:25:43.414869 NOTICE: BL31: BL33 decompress pass
1037 20:25:43.419592 ERROR: Error initializing runtime service opteed_fast
1038 20:25:44.653566
1039 20:25:44.654192
1040 20:25:44.661848 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 20:25:44.662309
1042 20:25:44.662726 Model: Libre Computer AML-A311D-CC Alta
1043 20:25:44.870235 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 20:25:44.893547 DRAM: 2 GiB (effective 3.8 GiB)
1045 20:25:45.036564 Core: 408 devices, 31 uclasses, devicetree: separate
1046 20:25:45.042433 WDT: Not starting watchdog@f0d0
1047 20:25:45.074691 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 20:25:45.087167 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 20:25:45.092135 ** Bad device specification mmc 0 **
1050 20:25:45.102489 Card did not respond to voltage select! : -110
1051 20:25:45.110136 ** Bad device specification mmc 0 **
1052 20:25:45.110580 Couldn't find partition mmc 0
1053 20:25:45.118488 Card did not respond to voltage select! : -110
1054 20:25:45.124053 ** Bad device specification mmc 0 **
1055 20:25:45.124505 Couldn't find partition mmc 0
1056 20:25:45.128134 Error: could not access storage.
1057 20:25:45.471495 Net: eth0: ethernet@ff3f0000
1058 20:25:45.472063 starting USB...
1059 20:25:45.723287 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 20:25:45.723821 Starting the controller
1061 20:25:45.729349 USB XHCI 1.10
1062 20:25:47.287491 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 20:25:47.295886 scanning usb for storage devices... 0 Storage Device(s) found
1065 20:25:47.347451 Hit any key to stop autoboot: 1
1066 20:25:47.348306 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 20:25:47.348918 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1068 20:25:47.349408 Setting prompt string to ['=>']
1069 20:25:47.349895 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1070 20:25:47.363351 0
1071 20:25:47.364217 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 20:25:47.364709 Sending with 10 millisecond of delay
1074 20:25:48.499702 => setenv autoload no
1075 20:25:48.510637 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1076 20:25:48.513339 setenv autoload no
1077 20:25:48.513870 Sending with 10 millisecond of delay
1079 20:25:50.311482 => setenv initrd_high 0xffffffff
1080 20:25:50.322036 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1081 20:25:50.322580 setenv initrd_high 0xffffffff
1082 20:25:50.323106 Sending with 10 millisecond of delay
1084 20:25:51.939096 => setenv fdt_high 0xffffffff
1085 20:25:51.949863 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1086 20:25:51.950643 setenv fdt_high 0xffffffff
1087 20:25:51.951351 Sending with 10 millisecond of delay
1089 20:25:52.243208 => dhcp
1090 20:25:52.253939 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1091 20:25:52.254715 dhcp
1092 20:25:52.255148 Speed: 1000, full duplex
1093 20:25:52.255556 BOOTP broadcast 1
1094 20:25:52.262113 DHCP client bound to address 192.168.6.27 (8 ms)
1095 20:25:52.262803 Sending with 10 millisecond of delay
1097 20:25:53.938990 => setenv serverip 192.168.6.2
1098 20:25:53.949749 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1099 20:25:53.950624 setenv serverip 192.168.6.2
1100 20:25:53.951311 Sending with 10 millisecond of delay
1102 20:25:57.674545 => tftpboot 0x01080000 948429/tftp-deploy-0paqgbzk/kernel/uImage
1103 20:25:57.685305 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1104 20:25:57.685853 tftpboot 0x01080000 948429/tftp-deploy-0paqgbzk/kernel/uImage
1105 20:25:57.686126 Speed: 1000, full duplex
1106 20:25:57.686360 Using ethernet@ff3f0000 device
1107 20:25:57.687804 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 20:25:57.693299 Filename '948429/tftp-deploy-0paqgbzk/kernel/uImage'.
1109 20:25:57.697138 Load address: 0x1080000
1110 20:26:01.893189 Loading: *###################
1111 20:26:01.893820 TFTP error: trying to overwrite reserved memory...
1113 20:26:01.895226 end: 2.4.3 bootloader-commands (duration 00:00:15) [common]
1116 20:26:01.897275 end: 2.4 uboot-commands (duration 00:00:51) [common]
1118 20:26:01.898709 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
1120 20:26:01.899761 end: 2 uboot-action (duration 00:00:51) [common]
1122 20:26:01.901299 Cleaning after the job
1123 20:26:01.901831 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948429/tftp-deploy-0paqgbzk/ramdisk
1124 20:26:01.932036 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948429/tftp-deploy-0paqgbzk/kernel
1125 20:26:01.993547 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948429/tftp-deploy-0paqgbzk/dtb
1126 20:26:01.994409 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948429/tftp-deploy-0paqgbzk/modules
1127 20:26:02.053256 start: 4.1 power-off (timeout 00:00:30) [common]
1128 20:26:02.053941 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1129 20:26:02.087311 >> OK - accepted request
1130 20:26:02.089390 Returned 0 in 0 seconds
1131 20:26:02.190124 end: 4.1 power-off (duration 00:00:00) [common]
1133 20:26:02.191041 start: 4.2 read-feedback (timeout 00:10:00) [common]
1134 20:26:02.191678 Listened to connection for namespace 'common' for up to 1s
1135 20:26:03.192645 Finalising connection for namespace 'common'
1136 20:26:03.193135 Disconnecting from shell: Finalise
1137 20:26:03.193421 =>
1138 20:26:03.294000 end: 4.2 read-feedback (duration 00:00:01) [common]
1139 20:26:03.294328 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/948429
1140 20:26:03.596191 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/948429
1141 20:26:03.596805 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.