Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:12:51.464416 lava-dispatcher, installed at version: 2024.01
2 20:12:51.465224 start: 0 validate
3 20:12:51.465698 Start time: 2024-11-06 20:12:51.465668+00:00 (UTC)
4 20:12:51.466266 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:12:51.466803 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 20:12:51.500881 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:12:51.501452 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 20:12:51.532069 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:12:51.532713 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 20:12:52.581568 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:12:52.582053 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-99-g7758b206117da%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 20:12:52.620019 validate duration: 1.15
14 20:12:52.620888 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:12:52.621222 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:12:52.621537 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:12:52.622329 Not decompressing ramdisk as can be used compressed.
18 20:12:52.623127 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 20:12:52.623665 saving as /var/lib/lava/dispatcher/tmp/948445/tftp-deploy-o12iivdl/ramdisk/rootfs.cpio.gz
20 20:12:52.623964 total size: 8181887 (7 MB)
21 20:12:52.661313 progress 0 % (0 MB)
22 20:12:52.672245 progress 5 % (0 MB)
23 20:12:52.679282 progress 10 % (0 MB)
24 20:12:52.689506 progress 15 % (1 MB)
25 20:12:52.695128 progress 20 % (1 MB)
26 20:12:52.701350 progress 25 % (1 MB)
27 20:12:52.707017 progress 30 % (2 MB)
28 20:12:52.714341 progress 35 % (2 MB)
29 20:12:52.720136 progress 40 % (3 MB)
30 20:12:52.725990 progress 45 % (3 MB)
31 20:12:52.731398 progress 50 % (3 MB)
32 20:12:52.737158 progress 55 % (4 MB)
33 20:12:52.742485 progress 60 % (4 MB)
34 20:12:52.748292 progress 65 % (5 MB)
35 20:12:52.753651 progress 70 % (5 MB)
36 20:12:52.759314 progress 75 % (5 MB)
37 20:12:52.764640 progress 80 % (6 MB)
38 20:12:52.770693 progress 85 % (6 MB)
39 20:12:52.776265 progress 90 % (7 MB)
40 20:12:52.782244 progress 95 % (7 MB)
41 20:12:52.787305 progress 100 % (7 MB)
42 20:12:52.788013 7 MB downloaded in 0.16 s (47.58 MB/s)
43 20:12:52.788638 end: 1.1.1 http-download (duration 00:00:00) [common]
45 20:12:52.789605 end: 1.1 download-retry (duration 00:00:00) [common]
46 20:12:52.789939 start: 1.2 download-retry (timeout 00:10:00) [common]
47 20:12:52.790242 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 20:12:52.790752 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm64/defconfig+debug/gcc-12/kernel/Image
49 20:12:52.791031 saving as /var/lib/lava/dispatcher/tmp/948445/tftp-deploy-o12iivdl/kernel/Image
50 20:12:52.791259 total size: 169943552 (162 MB)
51 20:12:52.791489 No compression specified
52 20:12:52.829288 progress 0 % (0 MB)
53 20:12:52.934932 progress 5 % (8 MB)
54 20:12:53.039210 progress 10 % (16 MB)
55 20:12:53.147221 progress 15 % (24 MB)
56 20:12:53.256067 progress 20 % (32 MB)
57 20:12:53.366745 progress 25 % (40 MB)
58 20:12:53.476237 progress 30 % (48 MB)
59 20:12:53.586561 progress 35 % (56 MB)
60 20:12:53.695941 progress 40 % (64 MB)
61 20:12:53.810675 progress 45 % (72 MB)
62 20:12:53.926906 progress 50 % (81 MB)
63 20:12:54.037783 progress 55 % (89 MB)
64 20:12:54.148330 progress 60 % (97 MB)
65 20:12:54.259814 progress 65 % (105 MB)
66 20:12:54.370209 progress 70 % (113 MB)
67 20:12:54.481441 progress 75 % (121 MB)
68 20:12:54.592714 progress 80 % (129 MB)
69 20:12:54.703887 progress 85 % (137 MB)
70 20:12:54.814044 progress 90 % (145 MB)
71 20:12:54.924821 progress 95 % (153 MB)
72 20:12:55.036729 progress 100 % (162 MB)
73 20:12:55.037336 162 MB downloaded in 2.25 s (72.16 MB/s)
74 20:12:55.037825 end: 1.2.1 http-download (duration 00:00:02) [common]
76 20:12:55.038640 end: 1.2 download-retry (duration 00:00:02) [common]
77 20:12:55.038918 start: 1.3 download-retry (timeout 00:09:58) [common]
78 20:12:55.039188 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 20:12:55.039650 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 20:12:55.039926 saving as /var/lib/lava/dispatcher/tmp/948445/tftp-deploy-o12iivdl/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 20:12:55.040162 total size: 53209 (0 MB)
82 20:12:55.040374 No compression specified
83 20:12:55.077841 progress 61 % (0 MB)
84 20:12:55.078683 progress 100 % (0 MB)
85 20:12:55.079223 0 MB downloaded in 0.04 s (1.30 MB/s)
86 20:12:55.079687 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:12:55.080533 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:12:55.080801 start: 1.4 download-retry (timeout 00:09:58) [common]
90 20:12:55.081066 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 20:12:55.081582 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-99-g7758b206117da/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 20:12:55.081844 saving as /var/lib/lava/dispatcher/tmp/948445/tftp-deploy-o12iivdl/modules/modules.tar
93 20:12:55.082047 total size: 27662012 (26 MB)
94 20:12:55.082258 Using unxz to decompress xz
95 20:12:55.117546 progress 0 % (0 MB)
96 20:12:55.309679 progress 5 % (1 MB)
97 20:12:55.507889 progress 10 % (2 MB)
98 20:12:55.736538 progress 15 % (3 MB)
99 20:12:55.970693 progress 20 % (5 MB)
100 20:12:56.173144 progress 25 % (6 MB)
101 20:12:56.374242 progress 30 % (7 MB)
102 20:12:56.574964 progress 35 % (9 MB)
103 20:12:56.768871 progress 40 % (10 MB)
104 20:12:56.962602 progress 45 % (11 MB)
105 20:12:57.177782 progress 50 % (13 MB)
106 20:12:57.379302 progress 55 % (14 MB)
107 20:12:57.594882 progress 60 % (15 MB)
108 20:12:57.802877 progress 65 % (17 MB)
109 20:12:58.015293 progress 70 % (18 MB)
110 20:12:58.232812 progress 75 % (19 MB)
111 20:12:58.442099 progress 80 % (21 MB)
112 20:12:58.650142 progress 85 % (22 MB)
113 20:12:58.858199 progress 90 % (23 MB)
114 20:12:59.057370 progress 95 % (25 MB)
115 20:12:59.257528 progress 100 % (26 MB)
116 20:12:59.269205 26 MB downloaded in 4.19 s (6.30 MB/s)
117 20:12:59.269918 end: 1.4.1 http-download (duration 00:00:04) [common]
119 20:12:59.271548 end: 1.4 download-retry (duration 00:00:04) [common]
120 20:12:59.272133 start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
121 20:12:59.272676 start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
122 20:12:59.273179 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:12:59.273685 start: 1.5.2 lava-overlay (timeout 00:09:53) [common]
124 20:12:59.274727 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue
125 20:12:59.275624 makedir: /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin
126 20:12:59.276334 makedir: /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/tests
127 20:12:59.276978 makedir: /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/results
128 20:12:59.277601 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-add-keys
129 20:12:59.278719 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-add-sources
130 20:12:59.279671 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-background-process-start
131 20:12:59.280691 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-background-process-stop
132 20:12:59.281703 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-common-functions
133 20:12:59.282631 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-echo-ipv4
134 20:12:59.283645 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-install-packages
135 20:12:59.284610 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-installed-packages
136 20:12:59.285562 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-os-build
137 20:12:59.286470 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-probe-channel
138 20:12:59.287379 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-probe-ip
139 20:12:59.288325 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-target-ip
140 20:12:59.289255 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-target-mac
141 20:12:59.290171 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-target-storage
142 20:12:59.291101 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-test-case
143 20:12:59.292046 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-test-event
144 20:12:59.292974 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-test-feedback
145 20:12:59.293888 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-test-raise
146 20:12:59.294839 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-test-reference
147 20:12:59.295762 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-test-runner
148 20:12:59.296723 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-test-set
149 20:12:59.297636 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-test-shell
150 20:12:59.298586 Updating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-install-packages (oe)
151 20:12:59.299667 Updating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/bin/lava-installed-packages (oe)
152 20:12:59.300595 Creating /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/environment
153 20:12:59.301329 LAVA metadata
154 20:12:59.301819 - LAVA_JOB_ID=948445
155 20:12:59.302254 - LAVA_DISPATCHER_IP=192.168.6.2
156 20:12:59.302929 start: 1.5.2.1 ssh-authorize (timeout 00:09:53) [common]
157 20:12:59.304783 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 20:12:59.305377 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:53) [common]
159 20:12:59.305794 skipped lava-vland-overlay
160 20:12:59.306295 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 20:12:59.306810 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:53) [common]
162 20:12:59.307242 skipped lava-multinode-overlay
163 20:12:59.307737 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 20:12:59.308294 start: 1.5.2.4 test-definition (timeout 00:09:53) [common]
165 20:12:59.308786 Loading test definitions
166 20:12:59.309343 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:53) [common]
167 20:12:59.309788 Using /lava-948445 at stage 0
168 20:12:59.312051 uuid=948445_1.5.2.4.1 testdef=None
169 20:12:59.312627 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 20:12:59.313156 start: 1.5.2.4.2 test-overlay (timeout 00:09:53) [common]
171 20:12:59.316578 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 20:12:59.318141 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:53) [common]
174 20:12:59.321241 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 20:12:59.322100 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:53) [common]
177 20:12:59.325447 runner path: /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/0/tests/0_dmesg test_uuid 948445_1.5.2.4.1
178 20:12:59.326473 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 20:12:59.328019 Creating lava-test-runner.conf files
181 20:12:59.328253 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/948445/lava-overlay-4vkdg8ue/lava-948445/0 for stage 0
182 20:12:59.328649 - 0_dmesg
183 20:12:59.329025 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 20:12:59.329318 start: 1.5.2.5 compress-overlay (timeout 00:09:53) [common]
185 20:12:59.353571 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 20:12:59.353975 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:53) [common]
187 20:12:59.354262 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 20:12:59.354546 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 20:12:59.354824 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
190 20:13:00.359446 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 20:13:00.359927 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
192 20:13:00.360231 extracting modules file /var/lib/lava/dispatcher/tmp/948445/tftp-deploy-o12iivdl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/948445/extract-overlay-ramdisk-1zw5gj7i/ramdisk
193 20:13:02.028389 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 20:13:02.028876 start: 1.5.5 apply-overlay-tftp (timeout 00:09:51) [common]
195 20:13:02.029152 [common] Applying overlay /var/lib/lava/dispatcher/tmp/948445/compress-overlay-5r82l7wo/overlay-1.5.2.5.tar.gz to ramdisk
196 20:13:02.029366 [common] Applying overlay /var/lib/lava/dispatcher/tmp/948445/compress-overlay-5r82l7wo/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/948445/extract-overlay-ramdisk-1zw5gj7i/ramdisk
197 20:13:02.059485 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 20:13:02.059881 start: 1.5.6 prepare-kernel (timeout 00:09:51) [common]
199 20:13:02.060191 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:51) [common]
200 20:13:02.060419 Converting downloaded kernel to a uImage
201 20:13:02.060721 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/948445/tftp-deploy-o12iivdl/kernel/Image /var/lib/lava/dispatcher/tmp/948445/tftp-deploy-o12iivdl/kernel/uImage
202 20:13:03.736323 output: Image Name:
203 20:13:03.737007 output: Created: Wed Nov 6 20:13:02 2024
204 20:13:03.737251 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 20:13:03.737470 output: Data Size: 169943552 Bytes = 165960.50 KiB = 162.07 MiB
206 20:13:03.737681 output: Load Address: 01080000
207 20:13:03.737888 output: Entry Point: 01080000
208 20:13:03.738092 output:
209 20:13:03.738432 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 20:13:03.738715 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 20:13:03.739003 start: 1.5.7 configure-preseed-file (timeout 00:09:49) [common]
212 20:13:03.739271 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 20:13:03.739543 start: 1.5.8 compress-ramdisk (timeout 00:09:49) [common]
214 20:13:03.739811 Building ramdisk /var/lib/lava/dispatcher/tmp/948445/extract-overlay-ramdisk-1zw5gj7i/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/948445/extract-overlay-ramdisk-1zw5gj7i/ramdisk
215 20:13:09.240112 >> 441545 blocks
216 20:13:27.736150 Adding RAMdisk u-boot header.
217 20:13:27.736580 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/948445/extract-overlay-ramdisk-1zw5gj7i/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/948445/extract-overlay-ramdisk-1zw5gj7i/ramdisk.cpio.gz.uboot
218 20:13:28.282594 output: Image Name:
219 20:13:28.283054 output: Created: Wed Nov 6 20:13:27 2024
220 20:13:28.283493 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 20:13:28.283908 output: Data Size: 53581015 Bytes = 52325.21 KiB = 51.10 MiB
222 20:13:28.284373 output: Load Address: 00000000
223 20:13:28.284776 output: Entry Point: 00000000
224 20:13:28.285171 output:
225 20:13:28.286162 rename /var/lib/lava/dispatcher/tmp/948445/extract-overlay-ramdisk-1zw5gj7i/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/948445/tftp-deploy-o12iivdl/ramdisk/ramdisk.cpio.gz.uboot
226 20:13:28.286867 end: 1.5.8 compress-ramdisk (duration 00:00:25) [common]
227 20:13:28.287415 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
228 20:13:28.287948 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:24) [common]
229 20:13:28.288445 No LXC device requested
230 20:13:28.288961 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 20:13:28.289477 start: 1.7 deploy-device-env (timeout 00:09:24) [common]
232 20:13:28.289971 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 20:13:28.290384 Checking files for TFTP limit of 4294967296 bytes.
234 20:13:28.293054 end: 1 tftp-deploy (duration 00:00:36) [common]
235 20:13:28.293630 start: 2 uboot-action (timeout 00:05:00) [common]
236 20:13:28.294162 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 20:13:28.294669 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 20:13:28.295176 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 20:13:28.295710 Using kernel file from prepare-kernel: 948445/tftp-deploy-o12iivdl/kernel/uImage
240 20:13:28.296366 substitutions:
241 20:13:28.296785 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 20:13:28.297188 - {DTB_ADDR}: 0x01070000
243 20:13:28.297588 - {DTB}: 948445/tftp-deploy-o12iivdl/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 20:13:28.297987 - {INITRD}: 948445/tftp-deploy-o12iivdl/ramdisk/ramdisk.cpio.gz.uboot
245 20:13:28.298386 - {KERNEL_ADDR}: 0x01080000
246 20:13:28.298780 - {KERNEL}: 948445/tftp-deploy-o12iivdl/kernel/uImage
247 20:13:28.299177 - {LAVA_MAC}: None
248 20:13:28.299608 - {PRESEED_CONFIG}: None
249 20:13:28.300035 - {PRESEED_LOCAL}: None
250 20:13:28.300437 - {RAMDISK_ADDR}: 0x08000000
251 20:13:28.300827 - {RAMDISK}: 948445/tftp-deploy-o12iivdl/ramdisk/ramdisk.cpio.gz.uboot
252 20:13:28.301223 - {ROOT_PART}: None
253 20:13:28.301617 - {ROOT}: None
254 20:13:28.302006 - {SERVER_IP}: 192.168.6.2
255 20:13:28.302400 - {TEE_ADDR}: 0x83000000
256 20:13:28.302792 - {TEE}: None
257 20:13:28.303184 Parsed boot commands:
258 20:13:28.303564 - setenv autoload no
259 20:13:28.303955 - setenv initrd_high 0xffffffff
260 20:13:28.304375 - setenv fdt_high 0xffffffff
261 20:13:28.304769 - dhcp
262 20:13:28.305160 - setenv serverip 192.168.6.2
263 20:13:28.305550 - tftpboot 0x01080000 948445/tftp-deploy-o12iivdl/kernel/uImage
264 20:13:28.305941 - tftpboot 0x08000000 948445/tftp-deploy-o12iivdl/ramdisk/ramdisk.cpio.gz.uboot
265 20:13:28.306333 - tftpboot 0x01070000 948445/tftp-deploy-o12iivdl/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 20:13:28.306724 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 20:13:28.307121 - bootm 0x01080000 0x08000000 0x01070000
268 20:13:28.307616 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 20:13:28.309133 start: 2.3 connect-device (timeout 00:05:00) [common]
271 20:13:28.309602 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 20:13:28.323331 Setting prompt string to ['lava-test: # ']
273 20:13:28.324786 end: 2.3 connect-device (duration 00:00:00) [common]
274 20:13:28.325389 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 20:13:28.325947 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 20:13:28.326477 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 20:13:28.327637 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 20:13:28.378870 >> OK - accepted request
279 20:13:28.381056 Returned 0 in 0 seconds
280 20:13:28.482121 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 20:13:28.483691 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 20:13:28.484312 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 20:13:28.484829 Setting prompt string to ['Hit any key to stop autoboot']
285 20:13:28.485287 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 20:13:28.486852 Trying 192.168.56.21...
287 20:13:28.487321 Connected to conserv1.
288 20:13:28.487754 Escape character is '^]'.
289 20:13:28.488218
290 20:13:28.488649 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 20:13:28.489089
292 20:13:36.331040 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 20:13:36.331668 bl2_stage_init 0x01
294 20:13:36.332204 bl2_stage_init 0x81
295 20:13:36.336555 hw id: 0x0000 - pwm id 0x01
296 20:13:36.337009 bl2_stage_init 0xc1
297 20:13:36.341961 bl2_stage_init 0x02
298 20:13:36.342402
299 20:13:36.342809 L0:00000000
300 20:13:36.343209 L1:00000703
301 20:13:36.343605 L2:00008067
302 20:13:36.344026 L3:15000000
303 20:13:36.347560 S1:00000000
304 20:13:36.348008 B2:20282000
305 20:13:36.348428 B1:a0f83180
306 20:13:36.348826
307 20:13:36.349222 TE: 70328
308 20:13:36.349617
309 20:13:36.353025 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 20:13:36.353451
311 20:13:36.358708 Board ID = 1
312 20:13:36.359132 Set cpu clk to 24M
313 20:13:36.359530 Set clk81 to 24M
314 20:13:36.364378 Use GP1_pll as DSU clk.
315 20:13:36.364803 DSU clk: 1200 Mhz
316 20:13:36.365204 CPU clk: 1200 MHz
317 20:13:36.369895 Set clk81 to 166.6M
318 20:13:36.375430 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 20:13:36.375857 board id: 1
320 20:13:36.382910 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 20:13:36.393443 fw parse done
322 20:13:36.399374 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 20:13:36.442034 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 20:13:36.453004 PIEI prepare done
325 20:13:36.453445 fastboot data load
326 20:13:36.453854 fastboot data verify
327 20:13:36.458565 verify result: 266
328 20:13:36.464285 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 20:13:36.464706 LPDDR4 probe
330 20:13:36.465100 ddr clk to 1584MHz
331 20:13:36.472194 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 20:13:36.509390
333 20:13:36.509813 dmc_version 0001
334 20:13:36.516065 Check phy result
335 20:13:36.521960 INFO : End of CA training
336 20:13:36.522382 INFO : End of initialization
337 20:13:36.527629 INFO : Training has run successfully!
338 20:13:36.528088 Check phy result
339 20:13:36.533264 INFO : End of initialization
340 20:13:36.533681 INFO : End of read enable training
341 20:13:36.538797 INFO : End of fine write leveling
342 20:13:36.544391 INFO : End of Write leveling coarse delay
343 20:13:36.544806 INFO : Training has run successfully!
344 20:13:36.545203 Check phy result
345 20:13:36.549984 INFO : End of initialization
346 20:13:36.550401 INFO : End of read dq deskew training
347 20:13:36.555583 INFO : End of MPR read delay center optimization
348 20:13:36.561263 INFO : End of write delay center optimization
349 20:13:36.566793 INFO : End of read delay center optimization
350 20:13:36.567213 INFO : End of max read latency training
351 20:13:36.572386 INFO : Training has run successfully!
352 20:13:36.572803 1D training succeed
353 20:13:36.581560 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 20:13:36.629168 Check phy result
355 20:13:36.629606 INFO : End of initialization
356 20:13:36.651516 INFO : End of 2D read delay Voltage center optimization
357 20:13:36.670657 INFO : End of 2D read delay Voltage center optimization
358 20:13:36.722524 INFO : End of 2D write delay Voltage center optimization
359 20:13:36.771738 INFO : End of 2D write delay Voltage center optimization
360 20:13:36.777321 INFO : Training has run successfully!
361 20:13:36.777742
362 20:13:36.778146 channel==0
363 20:13:36.782905 RxClkDly_Margin_A0==78 ps 8
364 20:13:36.783324 TxDqDly_Margin_A0==88 ps 9
365 20:13:36.788518 RxClkDly_Margin_A1==88 ps 9
366 20:13:36.788951 TxDqDly_Margin_A1==88 ps 9
367 20:13:36.789353 TrainedVREFDQ_A0==74
368 20:13:36.794097 TrainedVREFDQ_A1==74
369 20:13:36.794519 VrefDac_Margin_A0==24
370 20:13:36.794912 DeviceVref_Margin_A0==40
371 20:13:36.799740 VrefDac_Margin_A1==23
372 20:13:36.800190 DeviceVref_Margin_A1==40
373 20:13:36.800596
374 20:13:36.800993
375 20:13:36.801387 channel==1
376 20:13:36.805334 RxClkDly_Margin_A0==88 ps 9
377 20:13:36.805755 TxDqDly_Margin_A0==98 ps 10
378 20:13:36.810893 RxClkDly_Margin_A1==78 ps 8
379 20:13:36.811312 TxDqDly_Margin_A1==88 ps 9
380 20:13:36.816510 TrainedVREFDQ_A0==78
381 20:13:36.816935 TrainedVREFDQ_A1==75
382 20:13:36.817335 VrefDac_Margin_A0==23
383 20:13:36.822100 DeviceVref_Margin_A0==36
384 20:13:36.822516 VrefDac_Margin_A1==22
385 20:13:36.822909 DeviceVref_Margin_A1==39
386 20:13:36.827707
387 20:13:36.828154 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 20:13:36.828558
389 20:13:36.861398 soc_vref_reg_value 0x 00000019 00000018 00000019 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000016 dram_vref_reg_value 0x 00000061
390 20:13:36.861894 2D training succeed
391 20:13:36.866906 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 20:13:36.872482 auto size-- 65535DDR cs0 size: 2048MB
393 20:13:36.872906 DDR cs1 size: 2048MB
394 20:13:36.878121 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 20:13:36.878538 cs0 DataBus test pass
396 20:13:36.883702 cs1 DataBus test pass
397 20:13:36.884157 cs0 AddrBus test pass
398 20:13:36.884557 cs1 AddrBus test pass
399 20:13:36.884949
400 20:13:36.889347 100bdlr_step_size ps== 478
401 20:13:36.889784 result report
402 20:13:36.894903 boot times 0Enable ddr reg access
403 20:13:36.900027 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 20:13:36.913829 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 20:13:37.568436 bl2z: ptr: 05129330, size: 00001e40
406 20:13:37.576173 0.0;M3 CHK:0;cm4_sp_mode 0
407 20:13:37.576617 MVN_1=0x00000000
408 20:13:37.577018 MVN_2=0x00000000
409 20:13:37.587631 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 20:13:37.588117 OPS=0x04
411 20:13:37.588530 ring efuse init
412 20:13:37.593372 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 20:13:37.593803 [0.017310 Inits done]
414 20:13:37.594200 secure task start!
415 20:13:37.600623 high task start!
416 20:13:37.601042 low task start!
417 20:13:37.601436 run into bl31
418 20:13:37.609250 NOTICE: BL31: v1.3(release):4fc40b1
419 20:13:37.617049 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 20:13:37.617478 NOTICE: BL31: G12A normal boot!
421 20:13:37.632608 NOTICE: BL31: BL33 decompress pass
422 20:13:37.638314 ERROR: Error initializing runtime service opteed_fast
423 20:13:40.382266 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 20:13:40.382882 bl2_stage_init 0x01
425 20:13:40.383311 bl2_stage_init 0x81
426 20:13:40.388021 hw id: 0x0000 - pwm id 0x01
427 20:13:40.388501 bl2_stage_init 0xc1
428 20:13:40.388912 bl2_stage_init 0x02
429 20:13:40.389315
430 20:13:40.393577 L0:00000000
431 20:13:40.394062 L1:00000703
432 20:13:40.394451 L2:00008067
433 20:13:40.394832 L3:15000000
434 20:13:40.395214 S1:00000000
435 20:13:40.399111 B2:20282000
436 20:13:40.399525 B1:a0f83180
437 20:13:40.399909
438 20:13:40.400331 TE: 71109
439 20:13:40.400717
440 20:13:40.404746 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 20:13:40.405156
442 20:13:40.410326 Board ID = 1
443 20:13:40.410740 Set cpu clk to 24M
444 20:13:40.411127 Set clk81 to 24M
445 20:13:40.416004 Use GP1_pll as DSU clk.
446 20:13:40.416446 DSU clk: 1200 Mhz
447 20:13:40.416830 CPU clk: 1200 MHz
448 20:13:40.417209 Set clk81 to 166.6M
449 20:13:40.427300 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 20:13:40.427876 board id: 1
451 20:13:40.433706 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 20:13:40.444551 fw parse done
453 20:13:40.450498 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 20:13:40.493721 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 20:13:40.504971 PIEI prepare done
456 20:13:40.505379 fastboot data load
457 20:13:40.505585 fastboot data verify
458 20:13:40.510244 verify result: 266
459 20:13:40.515897 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 20:13:40.516264 LPDDR4 probe
461 20:13:40.516511 ddr clk to 1584MHz
462 20:13:40.523914 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 20:13:40.561643
464 20:13:40.562203 dmc_version 0001
465 20:13:40.568543 Check phy result
466 20:13:40.574522 INFO : End of CA training
467 20:13:40.574945 INFO : End of initialization
468 20:13:40.580158 INFO : Training has run successfully!
469 20:13:40.580584 Check phy result
470 20:13:40.585767 INFO : End of initialization
471 20:13:40.586085 INFO : End of read enable training
472 20:13:40.591294 INFO : End of fine write leveling
473 20:13:40.596942 INFO : End of Write leveling coarse delay
474 20:13:40.597407 INFO : Training has run successfully!
475 20:13:40.597819 Check phy result
476 20:13:40.602603 INFO : End of initialization
477 20:13:40.603122 INFO : End of read dq deskew training
478 20:13:40.608161 INFO : End of MPR read delay center optimization
479 20:13:40.613951 INFO : End of write delay center optimization
480 20:13:40.620170 INFO : End of read delay center optimization
481 20:13:40.620714 INFO : End of max read latency training
482 20:13:40.624993 INFO : Training has run successfully!
483 20:13:40.625430 1D training succeed
484 20:13:40.634139 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 20:13:40.682446 Check phy result
486 20:13:40.682921 INFO : End of initialization
487 20:13:40.709916 INFO : End of 2D read delay Voltage center optimization
488 20:13:40.733991 INFO : End of 2D read delay Voltage center optimization
489 20:13:40.790691 INFO : End of 2D write delay Voltage center optimization
490 20:13:40.844770 INFO : End of 2D write delay Voltage center optimization
491 20:13:40.850271 INFO : Training has run successfully!
492 20:13:40.850695
493 20:13:40.851101 channel==0
494 20:13:40.855896 RxClkDly_Margin_A0==88 ps 9
495 20:13:40.856363 TxDqDly_Margin_A0==98 ps 10
496 20:13:40.861468 RxClkDly_Margin_A1==78 ps 8
497 20:13:40.861885 TxDqDly_Margin_A1==98 ps 10
498 20:13:40.862288 TrainedVREFDQ_A0==74
499 20:13:40.867061 TrainedVREFDQ_A1==74
500 20:13:40.867482 VrefDac_Margin_A0==23
501 20:13:40.867882 DeviceVref_Margin_A0==40
502 20:13:40.872677 VrefDac_Margin_A1==23
503 20:13:40.873102 DeviceVref_Margin_A1==40
504 20:13:40.873503
505 20:13:40.873898
506 20:13:40.878273 channel==1
507 20:13:40.878698 RxClkDly_Margin_A0==88 ps 9
508 20:13:40.879096 TxDqDly_Margin_A0==88 ps 9
509 20:13:40.883892 RxClkDly_Margin_A1==78 ps 8
510 20:13:40.884345 TxDqDly_Margin_A1==88 ps 9
511 20:13:40.889510 TrainedVREFDQ_A0==77
512 20:13:40.889948 TrainedVREFDQ_A1==77
513 20:13:40.890352 VrefDac_Margin_A0==22
514 20:13:40.895084 DeviceVref_Margin_A0==37
515 20:13:40.895503 VrefDac_Margin_A1==22
516 20:13:40.900664 DeviceVref_Margin_A1==37
517 20:13:40.901087
518 20:13:40.901485 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 20:13:40.901879
520 20:13:40.934313 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
521 20:13:40.934851 2D training succeed
522 20:13:40.939893 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 20:13:40.945473 auto size-- 65535DDR cs0 size: 2048MB
524 20:13:40.945926 DDR cs1 size: 2048MB
525 20:13:40.951064 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 20:13:40.951501 cs0 DataBus test pass
527 20:13:40.956659 cs1 DataBus test pass
528 20:13:40.957089 cs0 AddrBus test pass
529 20:13:40.957494 cs1 AddrBus test pass
530 20:13:40.957890
531 20:13:40.962263 100bdlr_step_size ps== 471
532 20:13:40.962699 result report
533 20:13:40.967857 boot times 0Enable ddr reg access
534 20:13:40.973051 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 20:13:40.986916 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 20:13:41.646576 bl2z: ptr: 05129330, size: 00001e40
537 20:13:41.655262 0.0;M3 CHK:0;cm4_sp_mode 0
538 20:13:41.655709 MVN_1=0x00000000
539 20:13:41.656164 MVN_2=0x00000000
540 20:13:41.666775 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 20:13:41.667216 OPS=0x04
542 20:13:41.667621 ring efuse init
543 20:13:41.674301 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 20:13:41.674738 [0.017354 Inits done]
545 20:13:41.675141 secure task start!
546 20:13:41.679725 high task start!
547 20:13:41.680183 low task start!
548 20:13:41.680586 run into bl31
549 20:13:41.688294 NOTICE: BL31: v1.3(release):4fc40b1
550 20:13:41.696132 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 20:13:41.696560 NOTICE: BL31: G12A normal boot!
552 20:13:41.711612 NOTICE: BL31: BL33 decompress pass
553 20:13:41.717270 ERROR: Error initializing runtime service opteed_fast
554 20:13:43.081873 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 20:13:43.082499 bl2_stage_init 0x01
556 20:13:43.082926 bl2_stage_init 0x81
557 20:13:43.087379 hw id: 0x0000 - pwm id 0x01
558 20:13:43.087818 bl2_stage_init 0xc1
559 20:13:43.092945 bl2_stage_init 0x02
560 20:13:43.093381
561 20:13:43.093790 L0:00000000
562 20:13:43.094187 L1:00000703
563 20:13:43.094578 L2:00008067
564 20:13:43.094969 L3:15000000
565 20:13:43.098561 S1:00000000
566 20:13:43.098989 B2:20282000
567 20:13:43.099385 B1:a0f83180
568 20:13:43.099775
569 20:13:43.100217 TE: 69536
570 20:13:43.100616
571 20:13:43.104079 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 20:13:43.104514
573 20:13:43.109816 Board ID = 1
574 20:13:43.110243 Set cpu clk to 24M
575 20:13:43.110642 Set clk81 to 24M
576 20:13:43.115450 Use GP1_pll as DSU clk.
577 20:13:43.115878 DSU clk: 1200 Mhz
578 20:13:43.116315 CPU clk: 1200 MHz
579 20:13:43.120979 Set clk81 to 166.6M
580 20:13:43.126487 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 20:13:43.126923 board id: 1
582 20:13:43.133775 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 20:13:43.144587 fw parse done
584 20:13:43.150618 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 20:13:43.193712 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 20:13:43.204730 PIEI prepare done
587 20:13:43.205045 fastboot data load
588 20:13:43.205269 fastboot data verify
589 20:13:43.210325 verify result: 266
590 20:13:43.215911 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 20:13:43.216212 LPDDR4 probe
592 20:13:43.216431 ddr clk to 1584MHz
593 20:13:43.223858 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 20:13:43.261598
595 20:13:43.261885 dmc_version 0001
596 20:13:43.268642 Check phy result
597 20:13:43.274613 INFO : End of CA training
598 20:13:43.274869 INFO : End of initialization
599 20:13:43.280223 INFO : Training has run successfully!
600 20:13:43.280468 Check phy result
601 20:13:43.285807 INFO : End of initialization
602 20:13:43.286045 INFO : End of read enable training
603 20:13:43.291412 INFO : End of fine write leveling
604 20:13:43.297000 INFO : End of Write leveling coarse delay
605 20:13:43.297246 INFO : Training has run successfully!
606 20:13:43.297447 Check phy result
607 20:13:43.302604 INFO : End of initialization
608 20:13:43.302835 INFO : End of read dq deskew training
609 20:13:43.308224 INFO : End of MPR read delay center optimization
610 20:13:43.313782 INFO : End of write delay center optimization
611 20:13:43.319417 INFO : End of read delay center optimization
612 20:13:43.319659 INFO : End of max read latency training
613 20:13:43.325009 INFO : Training has run successfully!
614 20:13:43.325256 1D training succeed
615 20:13:43.334271 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 20:13:43.382510 Check phy result
617 20:13:43.382773 INFO : End of initialization
618 20:13:43.409948 INFO : End of 2D read delay Voltage center optimization
619 20:13:43.434055 INFO : End of 2D read delay Voltage center optimization
620 20:13:43.490733 INFO : End of 2D write delay Voltage center optimization
621 20:13:43.544811 INFO : End of 2D write delay Voltage center optimization
622 20:13:43.550352 INFO : Training has run successfully!
623 20:13:43.550598
624 20:13:43.550801 channel==0
625 20:13:43.555912 RxClkDly_Margin_A0==69 ps 7
626 20:13:43.556188 TxDqDly_Margin_A0==98 ps 10
627 20:13:43.561564 RxClkDly_Margin_A1==69 ps 7
628 20:13:43.561807 TxDqDly_Margin_A1==98 ps 10
629 20:13:43.562009 TrainedVREFDQ_A0==74
630 20:13:43.567081 TrainedVREFDQ_A1==74
631 20:13:43.567331 VrefDac_Margin_A0==22
632 20:13:43.567530 DeviceVref_Margin_A0==40
633 20:13:43.572673 VrefDac_Margin_A1==23
634 20:13:43.572911 DeviceVref_Margin_A1==40
635 20:13:43.573109
636 20:13:43.573305
637 20:13:43.578365 channel==1
638 20:13:43.578602 RxClkDly_Margin_A0==78 ps 8
639 20:13:43.578804 TxDqDly_Margin_A0==98 ps 10
640 20:13:43.583870 RxClkDly_Margin_A1==78 ps 8
641 20:13:43.584146 TxDqDly_Margin_A1==88 ps 9
642 20:13:43.589573 TrainedVREFDQ_A0==78
643 20:13:43.589841 TrainedVREFDQ_A1==77
644 20:13:43.590047 VrefDac_Margin_A0==22
645 20:13:43.595136 DeviceVref_Margin_A0==36
646 20:13:43.595375 VrefDac_Margin_A1==22
647 20:13:43.600749 DeviceVref_Margin_A1==37
648 20:13:43.601005
649 20:13:43.601208 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 20:13:43.601403
651 20:13:43.634252 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
652 20:13:43.634553 2D training succeed
653 20:13:43.639818 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 20:13:43.645435 auto size-- 65535DDR cs0 size: 2048MB
655 20:13:43.645694 DDR cs1 size: 2048MB
656 20:13:43.651017 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 20:13:43.651263 cs0 DataBus test pass
658 20:13:43.656624 cs1 DataBus test pass
659 20:13:43.656898 cs0 AddrBus test pass
660 20:13:43.657112 cs1 AddrBus test pass
661 20:13:43.657313
662 20:13:43.662252 100bdlr_step_size ps== 471
663 20:13:43.662510 result report
664 20:13:43.667822 boot times 0Enable ddr reg access
665 20:13:43.673079 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 20:13:43.686948 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 20:13:44.346368 bl2z: ptr: 05129330, size: 00001e40
668 20:13:44.353237 0.0;M3 CHK:0;cm4_sp_mode 0
669 20:13:44.353500 MVN_1=0x00000000
670 20:13:44.353700 MVN_2=0x00000000
671 20:13:44.364729 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 20:13:44.364992 OPS=0x04
673 20:13:44.365198 ring efuse init
674 20:13:44.367646 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 20:13:44.373293 [0.017355 Inits done]
676 20:13:44.373653 secure task start!
677 20:13:44.373875 high task start!
678 20:13:44.374070 low task start!
679 20:13:44.377546 run into bl31
680 20:13:44.386103 NOTICE: BL31: v1.3(release):4fc40b1
681 20:13:44.393932 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 20:13:44.394186 NOTICE: BL31: G12A normal boot!
683 20:13:44.409401 NOTICE: BL31: BL33 decompress pass
684 20:13:44.415109 ERROR: Error initializing runtime service opteed_fast
685 20:13:45.210619
686 20:13:45.211006
687 20:13:45.216008 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 20:13:45.216396
689 20:13:45.219490 Model: Libre Computer AML-S905D3-CC Solitude
690 20:13:45.366505 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 20:13:45.381890 DRAM: 2 GiB (effective 3.8 GiB)
692 20:13:45.482839 Core: 406 devices, 33 uclasses, devicetree: separate
693 20:13:45.488767 WDT: Not starting watchdog@f0d0
694 20:13:45.513852 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 20:13:45.526105 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 20:13:45.531059 ** Bad device specification mmc 0 **
697 20:13:45.541111 Card did not respond to voltage select! : -110
698 20:13:45.548760 ** Bad device specification mmc 0 **
699 20:13:45.549185 Couldn't find partition mmc 0
700 20:13:45.557125 Card did not respond to voltage select! : -110
701 20:13:45.562625 ** Bad device specification mmc 0 **
702 20:13:45.563046 Couldn't find partition mmc 0
703 20:13:45.567676 Error: could not access storage.
704 20:13:45.864148 Net: eth0: ethernet@ff3f0000
705 20:13:45.864658 starting USB...
706 20:13:46.109050 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 20:13:46.109592 Starting the controller
708 20:13:46.115752 USB XHCI 1.10
709 20:13:47.671939 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 20:13:47.680207 scanning usb for storage devices... 0 Storage Device(s) found
712 20:13:47.731699 Hit any key to stop autoboot: 1
713 20:13:47.732522 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 20:13:47.733135 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 20:13:47.733626 Setting prompt string to ['=>']
716 20:13:47.734112 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 20:13:47.746256 0
718 20:13:47.747138 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 20:13:47.848361 => setenv autoload no
721 20:13:47.848975 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
722 20:13:47.853744 setenv autoload no
724 20:13:47.955214 => setenv initrd_high 0xffffffff
725 20:13:47.955824 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
726 20:13:47.960060 setenv initrd_high 0xffffffff
728 20:13:48.061459 => setenv fdt_high 0xffffffff
729 20:13:48.062044 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
730 20:13:48.066264 setenv fdt_high 0xffffffff
732 20:13:48.167689 => dhcp
733 20:13:48.168319 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 20:13:48.172337 dhcp
735 20:13:48.728033 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 20:13:48.728458 Speed: 1000, full duplex
737 20:13:48.728682 BOOTP broadcast 1
738 20:13:48.976616 BOOTP broadcast 2
739 20:13:49.012229 DHCP client bound to address 192.168.6.21 (284 ms)
741 20:13:49.113670 => setenv serverip 192.168.6.2
742 20:13:49.114290 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
743 20:13:49.118782 setenv serverip 192.168.6.2
745 20:13:49.220207 => tftpboot 0x01080000 948445/tftp-deploy-o12iivdl/kernel/uImage
746 20:13:49.221118 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
747 20:13:49.227695 tftpboot 0x01080000 948445/tftp-deploy-o12iivdl/kernel/uImage
748 20:13:49.228230 Speed: 1000, full duplex
749 20:13:49.228653 Using ethernet@ff3f0000 device
750 20:13:49.233102 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
751 20:13:49.238719 Filename '948445/tftp-deploy-o12iivdl/kernel/uImage'.
752 20:13:49.242653 Load address: 0x1080000
753 20:13:53.389659 Loading: *###################
754 20:13:53.390277 TFTP error: trying to overwrite reserved memory...
756 20:13:53.391691 end: 2.4.3 bootloader-commands (duration 00:00:06) [common]
759 20:13:53.393611 end: 2.4 uboot-commands (duration 00:00:25) [common]
761 20:13:53.394931 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
763 20:13:53.396024 end: 2 uboot-action (duration 00:00:25) [common]
765 20:13:53.397657 Cleaning after the job
766 20:13:53.398221 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948445/tftp-deploy-o12iivdl/ramdisk
767 20:13:53.428419 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948445/tftp-deploy-o12iivdl/kernel
768 20:13:53.477658 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948445/tftp-deploy-o12iivdl/dtb
769 20:13:53.478587 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948445/tftp-deploy-o12iivdl/modules
770 20:13:53.534261 start: 4.1 power-off (timeout 00:00:30) [common]
771 20:13:53.534947 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
772 20:13:53.567620 >> OK - accepted request
773 20:13:53.569814 Returned 0 in 0 seconds
774 20:13:53.670799 end: 4.1 power-off (duration 00:00:00) [common]
776 20:13:53.671731 start: 4.2 read-feedback (timeout 00:10:00) [common]
777 20:13:53.672493 Listened to connection for namespace 'common' for up to 1s
778 20:13:54.673391 Finalising connection for namespace 'common'
779 20:13:54.673904 Disconnecting from shell: Finalise
780 20:13:54.674185 =>
781 20:13:54.774937 end: 4.2 read-feedback (duration 00:00:01) [common]
782 20:13:54.775659 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/948445
783 20:13:55.110930 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/948445
784 20:13:55.111542 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.