Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 03:47:32.982853 lava-dispatcher, installed at version: 2024.01
2 03:47:32.983638 start: 0 validate
3 03:47:32.984110 Start time: 2024-11-04 03:47:32.984080+00:00 (UTC)
4 03:47:32.984699 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 03:47:32.985238 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 03:47:33.018532 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 03:47:33.019091 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fkernel%2FzImage exists
8 03:47:33.046816 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 03:47:33.047410 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 03:47:33.073142 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 03:47:33.073662 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 03:47:33.098343 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 03:47:33.098822 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fmodules.tar.xz exists
14 03:47:33.126378 validate duration: 0.14
16 03:47:33.127288 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 03:47:33.127608 start: 1.1 download-retry (timeout 00:10:00) [common]
18 03:47:33.127892 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 03:47:33.128482 Not decompressing ramdisk as can be used compressed.
20 03:47:33.128909 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 03:47:33.129179 saving as /var/lib/lava/dispatcher/tmp/932598/tftp-deploy-x_5s5lmz/ramdisk/initrd.cpio.gz
22 03:47:33.129439 total size: 4775763 (4 MB)
23 03:47:33.161350 progress 0 % (0 MB)
24 03:47:33.165086 progress 5 % (0 MB)
25 03:47:33.168240 progress 10 % (0 MB)
26 03:47:33.171384 progress 15 % (0 MB)
27 03:47:33.174864 progress 20 % (0 MB)
28 03:47:33.177941 progress 25 % (1 MB)
29 03:47:33.180982 progress 30 % (1 MB)
30 03:47:33.184402 progress 35 % (1 MB)
31 03:47:33.187516 progress 40 % (1 MB)
32 03:47:33.190556 progress 45 % (2 MB)
33 03:47:33.193641 progress 50 % (2 MB)
34 03:47:33.197212 progress 55 % (2 MB)
35 03:47:33.200441 progress 60 % (2 MB)
36 03:47:33.203680 progress 65 % (2 MB)
37 03:47:33.207204 progress 70 % (3 MB)
38 03:47:33.210279 progress 75 % (3 MB)
39 03:47:33.213205 progress 80 % (3 MB)
40 03:47:33.216170 progress 85 % (3 MB)
41 03:47:33.219411 progress 90 % (4 MB)
42 03:47:33.222376 progress 95 % (4 MB)
43 03:47:33.225315 progress 100 % (4 MB)
44 03:47:33.225991 4 MB downloaded in 0.10 s (47.18 MB/s)
45 03:47:33.226583 end: 1.1.1 http-download (duration 00:00:00) [common]
47 03:47:33.227468 end: 1.1 download-retry (duration 00:00:00) [common]
48 03:47:33.227760 start: 1.2 download-retry (timeout 00:10:00) [common]
49 03:47:33.228033 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 03:47:33.228525 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6/arm/multi_v7_defconfig/clang-15/kernel/zImage
51 03:47:33.228781 saving as /var/lib/lava/dispatcher/tmp/932598/tftp-deploy-x_5s5lmz/kernel/zImage
52 03:47:33.228990 total size: 12050944 (11 MB)
53 03:47:33.229200 No compression specified
54 03:47:33.263352 progress 0 % (0 MB)
55 03:47:33.271069 progress 5 % (0 MB)
56 03:47:33.278510 progress 10 % (1 MB)
57 03:47:33.286384 progress 15 % (1 MB)
58 03:47:33.293880 progress 20 % (2 MB)
59 03:47:33.301227 progress 25 % (2 MB)
60 03:47:33.309190 progress 30 % (3 MB)
61 03:47:33.316552 progress 35 % (4 MB)
62 03:47:33.324199 progress 40 % (4 MB)
63 03:47:33.333290 progress 45 % (5 MB)
64 03:47:33.340989 progress 50 % (5 MB)
65 03:47:33.348723 progress 55 % (6 MB)
66 03:47:33.355962 progress 60 % (6 MB)
67 03:47:33.363595 progress 65 % (7 MB)
68 03:47:33.371196 progress 70 % (8 MB)
69 03:47:33.378483 progress 75 % (8 MB)
70 03:47:33.386152 progress 80 % (9 MB)
71 03:47:33.393377 progress 85 % (9 MB)
72 03:47:33.400679 progress 90 % (10 MB)
73 03:47:33.407953 progress 95 % (10 MB)
74 03:47:33.414826 progress 100 % (11 MB)
75 03:47:33.415476 11 MB downloaded in 0.19 s (61.63 MB/s)
76 03:47:33.415959 end: 1.2.1 http-download (duration 00:00:00) [common]
78 03:47:33.416781 end: 1.2 download-retry (duration 00:00:00) [common]
79 03:47:33.417058 start: 1.3 download-retry (timeout 00:10:00) [common]
80 03:47:33.417355 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 03:47:33.417865 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
82 03:47:33.418133 saving as /var/lib/lava/dispatcher/tmp/932598/tftp-deploy-x_5s5lmz/dtb/am335x-boneblack.dtb
83 03:47:33.418341 total size: 70568 (0 MB)
84 03:47:33.418548 No compression specified
85 03:47:33.458432 progress 46 % (0 MB)
86 03:47:33.459257 progress 92 % (0 MB)
87 03:47:33.460036 progress 100 % (0 MB)
88 03:47:33.460522 0 MB downloaded in 0.04 s (1.60 MB/s)
89 03:47:33.461007 end: 1.3.1 http-download (duration 00:00:00) [common]
91 03:47:33.461900 end: 1.3 download-retry (duration 00:00:00) [common]
92 03:47:33.462185 start: 1.4 download-retry (timeout 00:10:00) [common]
93 03:47:33.462451 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 03:47:33.462984 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 03:47:33.463300 saving as /var/lib/lava/dispatcher/tmp/932598/tftp-deploy-x_5s5lmz/nfsrootfs/full.rootfs.tar
96 03:47:33.463573 total size: 117747780 (112 MB)
97 03:47:33.463794 Using unxz to decompress xz
98 03:47:33.494791 progress 0 % (0 MB)
99 03:47:34.215790 progress 5 % (5 MB)
100 03:47:34.948810 progress 10 % (11 MB)
101 03:47:35.712533 progress 15 % (16 MB)
102 03:47:36.428490 progress 20 % (22 MB)
103 03:47:37.002528 progress 25 % (28 MB)
104 03:47:37.807179 progress 30 % (33 MB)
105 03:47:38.602331 progress 35 % (39 MB)
106 03:47:38.926829 progress 40 % (44 MB)
107 03:47:39.270689 progress 45 % (50 MB)
108 03:47:39.916910 progress 50 % (56 MB)
109 03:47:40.717332 progress 55 % (61 MB)
110 03:47:41.436124 progress 60 % (67 MB)
111 03:47:42.140051 progress 65 % (73 MB)
112 03:47:42.889178 progress 70 % (78 MB)
113 03:47:43.634373 progress 75 % (84 MB)
114 03:47:44.354985 progress 80 % (89 MB)
115 03:47:45.050957 progress 85 % (95 MB)
116 03:47:45.824859 progress 90 % (101 MB)
117 03:47:46.572470 progress 95 % (106 MB)
118 03:47:47.376072 progress 100 % (112 MB)
119 03:47:47.388247 112 MB downloaded in 13.92 s (8.06 MB/s)
120 03:47:47.389197 end: 1.4.1 http-download (duration 00:00:14) [common]
122 03:47:47.391066 end: 1.4 download-retry (duration 00:00:14) [common]
123 03:47:47.391661 start: 1.5 download-retry (timeout 00:09:46) [common]
124 03:47:47.392242 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 03:47:47.393123 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6/arm/multi_v7_defconfig/clang-15/modules.tar.xz
126 03:47:47.393632 saving as /var/lib/lava/dispatcher/tmp/932598/tftp-deploy-x_5s5lmz/modules/modules.tar
127 03:47:47.394130 total size: 6912572 (6 MB)
128 03:47:47.394600 Using unxz to decompress xz
129 03:47:47.433324 progress 0 % (0 MB)
130 03:47:47.468490 progress 5 % (0 MB)
131 03:47:47.515999 progress 10 % (0 MB)
132 03:47:47.559434 progress 15 % (1 MB)
133 03:47:47.608890 progress 20 % (1 MB)
134 03:47:47.654008 progress 25 % (1 MB)
135 03:47:47.702186 progress 30 % (2 MB)
136 03:47:47.746960 progress 35 % (2 MB)
137 03:47:47.794570 progress 40 % (2 MB)
138 03:47:47.837654 progress 45 % (2 MB)
139 03:47:47.885431 progress 50 % (3 MB)
140 03:47:47.933243 progress 55 % (3 MB)
141 03:47:47.978919 progress 60 % (3 MB)
142 03:47:48.024875 progress 65 % (4 MB)
143 03:47:48.069706 progress 70 % (4 MB)
144 03:47:48.121623 progress 75 % (4 MB)
145 03:47:48.165094 progress 80 % (5 MB)
146 03:47:48.213520 progress 85 % (5 MB)
147 03:47:48.257446 progress 90 % (5 MB)
148 03:47:48.305375 progress 95 % (6 MB)
149 03:47:48.348994 progress 100 % (6 MB)
150 03:47:48.363131 6 MB downloaded in 0.97 s (6.80 MB/s)
151 03:47:48.363735 end: 1.5.1 http-download (duration 00:00:01) [common]
153 03:47:48.364559 end: 1.5 download-retry (duration 00:00:01) [common]
154 03:47:48.364830 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 03:47:48.365093 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 03:48:04.807536 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/932598/extract-nfsrootfs-ncz1sii6
157 03:48:04.808144 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 03:48:04.808450 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 03:48:04.809269 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot
160 03:48:04.810575 makedir: /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin
161 03:48:04.811047 makedir: /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/tests
162 03:48:04.811417 makedir: /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/results
163 03:48:04.811783 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-add-keys
164 03:48:04.812384 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-add-sources
165 03:48:04.812965 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-background-process-start
166 03:48:04.813522 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-background-process-stop
167 03:48:04.814156 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-common-functions
168 03:48:04.814710 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-echo-ipv4
169 03:48:04.815252 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-install-packages
170 03:48:04.815844 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-installed-packages
171 03:48:04.816395 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-os-build
172 03:48:04.816924 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-probe-channel
173 03:48:04.817447 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-probe-ip
174 03:48:04.818296 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-target-ip
175 03:48:04.819348 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-target-mac
176 03:48:04.819924 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-target-storage
177 03:48:04.820507 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-test-case
178 03:48:04.821120 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-test-event
179 03:48:04.821678 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-test-feedback
180 03:48:04.822289 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-test-raise
181 03:48:04.822820 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-test-reference
182 03:48:04.823330 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-test-runner
183 03:48:04.823839 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-test-set
184 03:48:04.824338 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-test-shell
185 03:48:04.824907 Updating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-add-keys (debian)
186 03:48:04.825781 Updating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-add-sources (debian)
187 03:48:04.826493 Updating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-install-packages (debian)
188 03:48:04.827089 Updating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-installed-packages (debian)
189 03:48:04.827688 Updating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/bin/lava-os-build (debian)
190 03:48:04.828203 Creating /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/environment
191 03:48:04.828639 LAVA metadata
192 03:48:04.828928 - LAVA_JOB_ID=932598
193 03:48:04.829148 - LAVA_DISPATCHER_IP=192.168.6.3
194 03:48:04.829541 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 03:48:04.830609 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 03:48:04.831018 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 03:48:04.831240 skipped lava-vland-overlay
198 03:48:04.831487 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 03:48:04.831745 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 03:48:04.831952 skipped lava-multinode-overlay
201 03:48:04.832193 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 03:48:04.832446 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 03:48:04.832712 Loading test definitions
204 03:48:04.833005 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 03:48:04.833256 Using /lava-932598 at stage 0
206 03:48:04.834709 uuid=932598_1.6.2.4.1 testdef=None
207 03:48:04.835389 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 03:48:04.836018 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 03:48:04.838167 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 03:48:04.839029 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 03:48:04.841184 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 03:48:04.842141 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 03:48:04.844315 runner path: /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/0/tests/0_timesync-off test_uuid 932598_1.6.2.4.1
216 03:48:04.845036 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 03:48:04.845985 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 03:48:04.846235 Using /lava-932598 at stage 0
220 03:48:04.846632 Fetching tests from https://github.com/kernelci/test-definitions.git
221 03:48:04.846952 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/0/tests/1_kselftest-dt'
222 03:48:08.317914 Running '/usr/bin/git checkout kernelci.org
223 03:48:08.608166 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 03:48:08.609632 uuid=932598_1.6.2.4.5 testdef=None
225 03:48:08.610165 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 03:48:08.611816 start: 1.6.2.4.6 test-overlay (timeout 00:09:25) [common]
228 03:48:08.617796 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 03:48:08.619589 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:25) [common]
231 03:48:08.627523 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 03:48:08.629351 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 03:48:08.637073 runner path: /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/0/tests/1_kselftest-dt test_uuid 932598_1.6.2.4.5
235 03:48:08.637672 BOARD='beaglebone-black'
236 03:48:08.638177 BRANCH='mainline'
237 03:48:08.638625 SKIPFILE='/dev/null'
238 03:48:08.639065 SKIP_INSTALL='True'
239 03:48:08.639497 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
240 03:48:08.639940 TST_CASENAME=''
241 03:48:08.640374 TST_CMDFILES='dt'
242 03:48:08.641443 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 03:48:08.643173 Creating lava-test-runner.conf files
245 03:48:08.643627 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/932598/lava-overlay-gay510ot/lava-932598/0 for stage 0
246 03:48:08.644355 - 0_timesync-off
247 03:48:08.644864 - 1_kselftest-dt
248 03:48:08.645574 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 03:48:08.646222 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 03:48:31.841365 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 03:48:31.841779 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 03:48:31.842073 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 03:48:31.842340 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 03:48:31.842597 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 03:48:32.192362 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 03:48:32.192815 start: 1.6.4 extract-modules (timeout 00:09:01) [common]
257 03:48:32.193057 extracting modules file /var/lib/lava/dispatcher/tmp/932598/tftp-deploy-x_5s5lmz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/932598/extract-nfsrootfs-ncz1sii6
258 03:48:33.076261 extracting modules file /var/lib/lava/dispatcher/tmp/932598/tftp-deploy-x_5s5lmz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/932598/extract-overlay-ramdisk-yey5zhs2/ramdisk
259 03:48:33.982732 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 03:48:33.983194 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 03:48:33.983439 [common] Applying overlay to NFS
262 03:48:33.983645 [common] Applying overlay /var/lib/lava/dispatcher/tmp/932598/compress-overlay-tphrm1_d/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/932598/extract-nfsrootfs-ncz1sii6
263 03:48:36.789339 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 03:48:36.789880 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 03:48:36.790170 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 03:48:36.790456 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 03:48:36.790718 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 03:48:36.790977 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 03:48:36.791225 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 03:48:36.791479 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 03:48:36.791704 Building ramdisk /var/lib/lava/dispatcher/tmp/932598/extract-overlay-ramdisk-yey5zhs2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/932598/extract-overlay-ramdisk-yey5zhs2/ramdisk
272 03:48:38.103958 >> 79012 blocks
273 03:48:43.138039 Adding RAMdisk u-boot header.
274 03:48:43.138702 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/932598/extract-overlay-ramdisk-yey5zhs2/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/932598/extract-overlay-ramdisk-yey5zhs2/ramdisk.cpio.gz.uboot
275 03:48:43.301225 output: Image Name:
276 03:48:43.301624 output: Created: Mon Nov 4 03:48:43 2024
277 03:48:43.301925 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 03:48:43.302393 output: Data Size: 15349380 Bytes = 14989.63 KiB = 14.64 MiB
279 03:48:43.302837 output: Load Address: 00000000
280 03:48:43.303272 output: Entry Point: 00000000
281 03:48:43.303706 output:
282 03:48:43.304769 rename /var/lib/lava/dispatcher/tmp/932598/extract-overlay-ramdisk-yey5zhs2/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/932598/tftp-deploy-x_5s5lmz/ramdisk/ramdisk.cpio.gz.uboot
283 03:48:43.305520 end: 1.6.8 compress-ramdisk (duration 00:00:07) [common]
284 03:48:43.306157 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 03:48:43.306731 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
286 03:48:43.307220 No LXC device requested
287 03:48:43.307758 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 03:48:43.308300 start: 1.8 deploy-device-env (timeout 00:08:50) [common]
289 03:48:43.308831 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 03:48:43.309275 Checking files for TFTP limit of 4294967296 bytes.
291 03:48:43.312184 end: 1 tftp-deploy (duration 00:01:10) [common]
292 03:48:43.312801 start: 2 uboot-action (timeout 00:05:00) [common]
293 03:48:43.313363 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 03:48:43.313932 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 03:48:43.314488 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 03:48:43.315262 substitutions:
297 03:48:43.315712 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 03:48:43.316150 - {DTB_ADDR}: 0x88000000
299 03:48:43.316584 - {DTB}: 932598/tftp-deploy-x_5s5lmz/dtb/am335x-boneblack.dtb
300 03:48:43.317015 - {INITRD}: 932598/tftp-deploy-x_5s5lmz/ramdisk/ramdisk.cpio.gz.uboot
301 03:48:43.317448 - {KERNEL_ADDR}: 0x82000000
302 03:48:43.317905 - {KERNEL}: 932598/tftp-deploy-x_5s5lmz/kernel/zImage
303 03:48:43.318338 - {LAVA_MAC}: None
304 03:48:43.318788 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/932598/extract-nfsrootfs-ncz1sii6
305 03:48:43.319219 - {NFS_SERVER_IP}: 192.168.6.3
306 03:48:43.319641 - {PRESEED_CONFIG}: None
307 03:48:43.320067 - {PRESEED_LOCAL}: None
308 03:48:43.320490 - {RAMDISK_ADDR}: 0x83000000
309 03:48:43.320914 - {RAMDISK}: 932598/tftp-deploy-x_5s5lmz/ramdisk/ramdisk.cpio.gz.uboot
310 03:48:43.321341 - {ROOT_PART}: None
311 03:48:43.321758 - {ROOT}: None
312 03:48:43.322207 - {SERVER_IP}: 192.168.6.3
313 03:48:43.322629 - {TEE_ADDR}: 0x83000000
314 03:48:43.323048 - {TEE}: None
315 03:48:43.323609 Parsed boot commands:
316 03:48:43.324028 - setenv autoload no
317 03:48:43.324452 - setenv initrd_high 0xffffffff
318 03:48:43.324876 - setenv fdt_high 0xffffffff
319 03:48:43.325301 - dhcp
320 03:48:43.325719 - setenv serverip 192.168.6.3
321 03:48:43.326171 - tftp 0x82000000 932598/tftp-deploy-x_5s5lmz/kernel/zImage
322 03:48:43.326594 - tftp 0x83000000 932598/tftp-deploy-x_5s5lmz/ramdisk/ramdisk.cpio.gz.uboot
323 03:48:43.327012 - setenv initrd_size ${filesize}
324 03:48:43.327428 - tftp 0x88000000 932598/tftp-deploy-x_5s5lmz/dtb/am335x-boneblack.dtb
325 03:48:43.327848 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/932598/extract-nfsrootfs-ncz1sii6,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 03:48:43.328279 - bootz 0x82000000 0x83000000 0x88000000
327 03:48:43.328826 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 03:48:43.330542 start: 2.3 connect-device (timeout 00:05:00) [common]
330 03:48:43.331008 [common] connect-device Connecting to device using 'telnet conserv3 3000'
331 03:48:43.345207 Setting prompt string to ['lava-test: # ']
332 03:48:43.347375 end: 2.3 connect-device (duration 00:00:00) [common]
333 03:48:43.348311 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 03:48:43.349015 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 03:48:43.349654 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 03:48:43.351100 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-03'
337 03:48:43.394056 >> OK - accepted request
338 03:48:43.396105 Returned 0 in 0 seconds
339 03:48:43.497324 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 03:48:43.499222 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 03:48:43.499850 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 03:48:43.500447 Setting prompt string to ['Hit any key to stop autoboot']
344 03:48:43.500948 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 03:48:43.502890 Trying 192.168.56.22...
346 03:48:43.503479 Connected to conserv3.
347 03:48:43.503960 Escape character is '^]'.
348 03:48:43.504405
349 03:48:43.504858 ser2net port telnet,3000 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 03:48:43.505321
351 03:48:52.091078
352 03:48:52.097969 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
353 03:48:52.098537 Trying to boot from MMC1
354 03:48:52.684218
355 03:48:52.684865
356 03:48:52.689613 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
357 03:48:52.690145
358 03:48:52.690591 CPU : AM335X-GP rev 2.0
359 03:48:52.694742 Model: TI AM335x BeagleBone Black
360 03:48:52.695222 DRAM: 512 MiB
361 03:48:56.170408
362 03:48:56.177243 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
363 03:48:56.177776 Trying to boot from MMC1
364 03:48:56.763195
365 03:48:56.763765
366 03:48:56.768555 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
367 03:48:56.769027
368 03:48:56.769471 CPU : AM335X-GP rev 2.0
369 03:48:56.773920 Model: TI AM335x BeagleBone Black
370 03:48:56.774415 DRAM: 512 MiB
371 03:48:58.871531
372 03:48:58.878254 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
373 03:48:58.878747 Trying to boot from MMC1
374 03:48:59.466953
375 03:48:59.467598
376 03:48:59.472364 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
377 03:48:59.472852
378 03:48:59.473296 CPU : AM335X-GP rev 2.0
379 03:48:59.477625 Model: TI AM335x BeagleBone Black
380 03:48:59.478138 DRAM: 512 MiB
381 03:48:59.562462 Core: 160 devices, 18 uclasses, devicetree: separate
382 03:48:59.576235 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
383 03:48:59.977139 NAND: 0 MiB
384 03:48:59.987025 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
385 03:49:00.061806 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
386 03:49:00.083101 <ethaddr> not set. Validating first E-fuse MAC
387 03:49:00.112059 Net: eth2: ethernet@4a100000, eth3: usb_ether
389 03:49:00.171228 Hit any key to stop autoboot: 2
390 03:49:00.172042 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
391 03:49:00.172666 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
392 03:49:00.173192 Setting prompt string to ['=>']
393 03:49:00.173715 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
394 03:49:00.181233 0
395 03:49:00.182140 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
396 03:49:00.182665 Sending with 10 millisecond of delay
398 03:49:01.317396 => setenv autoload no
399 03:49:01.328311 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
400 03:49:01.333761 setenv autoload no
401 03:49:01.334586 Sending with 10 millisecond of delay
403 03:49:03.131593 => setenv initrd_high 0xffffffff
404 03:49:03.142421 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
405 03:49:03.143315 setenv initrd_high 0xffffffff
406 03:49:03.144064 Sending with 10 millisecond of delay
408 03:49:04.760454 => setenv fdt_high 0xffffffff
409 03:49:04.771263 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
410 03:49:04.772166 setenv fdt_high 0xffffffff
411 03:49:04.772907 Sending with 10 millisecond of delay
413 03:49:05.064755 => dhcp
414 03:49:05.075455 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
415 03:49:05.076311 dhcp
416 03:49:05.078206 link up on port 0, speed 100, full duplex
417 03:49:05.078702 BOOTP broadcast 1
418 03:49:05.330302 BOOTP broadcast 2
419 03:49:05.831655 BOOTP broadcast 3
420 03:49:05.985443 DHCP client bound to address 192.168.6.23 (904 ms)
421 03:49:05.986332 Sending with 10 millisecond of delay
423 03:49:07.663371 => setenv serverip 192.168.6.3
424 03:49:07.674181 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
425 03:49:07.675086 setenv serverip 192.168.6.3
426 03:49:07.675783 Sending with 10 millisecond of delay
428 03:49:11.157768 => tftp 0x82000000 932598/tftp-deploy-x_5s5lmz/kernel/zImage
429 03:49:11.168599 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
430 03:49:11.169474 tftp 0x82000000 932598/tftp-deploy-x_5s5lmz/kernel/zImage
431 03:49:11.169956 link up on port 0, speed 100, full duplex
432 03:49:11.173477 Using ethernet@4a100000 device
433 03:49:11.179010 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
434 03:49:11.186391 Filename '932598/tftp-deploy-x_5s5lmz/kernel/zImage'.
435 03:49:11.186867 Load address: 0x82000000
436 03:49:13.486855 Loading: *################################################## 11.5 MiB
437 03:49:13.487348 5 MiB/s
438 03:49:13.487660 done
439 03:49:13.491468 Bytes transferred = 12050944 (b7e200 hex)
440 03:49:13.492026 Sending with 10 millisecond of delay
442 03:49:17.938725 => tftp 0x83000000 932598/tftp-deploy-x_5s5lmz/ramdisk/ramdisk.cpio.gz.uboot
443 03:49:17.949340 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
444 03:49:17.949946 tftp 0x83000000 932598/tftp-deploy-x_5s5lmz/ramdisk/ramdisk.cpio.gz.uboot
445 03:49:17.950204 link up on port 0, speed 100, full duplex
446 03:49:17.954097 Using ethernet@4a100000 device
447 03:49:17.959852 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
448 03:49:17.968488 Filename '932598/tftp-deploy-x_5s5lmz/ramdisk/ramdisk.cpio.gz.uboot'.
449 03:49:17.968839 Load address: 0x83000000
450 03:49:20.908455 Loading: *################################################## 14.6 MiB
451 03:49:20.908889 5 MiB/s
452 03:49:20.909109 done
453 03:49:20.912539 Bytes transferred = 15349444 (ea36c4 hex)
454 03:49:20.913066 Sending with 10 millisecond of delay
456 03:49:22.769689 => setenv initrd_size ${filesize}
457 03:49:22.780477 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
458 03:49:22.781253 setenv initrd_size ${filesize}
459 03:49:22.781959 Sending with 10 millisecond of delay
461 03:49:26.926587 => tftp 0x88000000 932598/tftp-deploy-x_5s5lmz/dtb/am335x-boneblack.dtb
462 03:49:26.937370 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
463 03:49:26.938281 tftp 0x88000000 932598/tftp-deploy-x_5s5lmz/dtb/am335x-boneblack.dtb
464 03:49:26.938710 link up on port 0, speed 100, full duplex
465 03:49:26.942257 Using ethernet@4a100000 device
466 03:49:26.947804 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
467 03:49:26.958236 Filename '932598/tftp-deploy-x_5s5lmz/dtb/am335x-boneblack.dtb'.
468 03:49:26.958681 Load address: 0x88000000
469 03:49:26.968366 Loading: *################################################## 68.9 KiB
470 03:49:26.968801 4.8 MiB/s
471 03:49:26.976984 done
472 03:49:26.977410 Bytes transferred = 70568 (113a8 hex)
473 03:49:26.978061 Sending with 10 millisecond of delay
475 03:49:40.151568 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/932598/extract-nfsrootfs-ncz1sii6,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
476 03:49:40.162373 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
477 03:49:40.163259 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/932598/extract-nfsrootfs-ncz1sii6,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 03:49:40.163968 Sending with 10 millisecond of delay
480 03:49:42.504408 => bootz 0x82000000 0x83000000 0x88000000
481 03:49:42.515210 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
482 03:49:42.515756 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
483 03:49:42.516771 bootz 0x82000000 0x83000000 0x88000000
484 03:49:42.517228 Kernel image @ 0x82000000 [ 0x000000 - 0xb7e200 ]
485 03:49:42.517720 ## Loading init Ramdisk from Legacy Image at 83000000 ...
486 03:49:42.523049 Image Name:
487 03:49:42.523494 Created: 2024-11-04 3:48:43 UTC
488 03:49:42.531684 Image Type: ARM Linux RAMDisk Image (uncompressed)
489 03:49:42.532139 Data Size: 15349380 Bytes = 14.6 MiB
490 03:49:42.539169 Load Address: 00000000
491 03:49:42.539615 Entry Point: 00000000
492 03:49:42.714731 Verifying Checksum ... OK
493 03:49:42.715217 ## Flattened Device Tree blob at 88000000
494 03:49:42.721227 Booting using the fdt blob at 0x88000000
495 03:49:42.721667 Working FDT set to 88000000
496 03:49:42.726770 Using Device Tree in place at 88000000, end 880143a7
497 03:49:42.731164 Working FDT set to 88000000
498 03:49:42.744350
499 03:49:42.744794 Starting kernel ...
500 03:49:42.745201
501 03:49:42.746087 end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
502 03:49:42.746673 start: 2.4.4 auto-login-action (timeout 00:04:01) [common]
503 03:49:42.747155 Setting prompt string to ['Linux version [0-9]']
504 03:49:42.747612 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 03:49:42.748074 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 03:49:43.640204 [ 0.000000] Booting Linux on physical CPU 0x0
507 03:49:43.646013 start: 2.4.4.1 login-action (timeout 00:04:00) [common]
508 03:49:43.646553 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 03:49:43.647016 Setting prompt string to []
510 03:49:43.647504 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 03:49:43.647984 Using line separator: #'\n'#
512 03:49:43.648391 No login prompt set.
513 03:49:43.648829 Parsing kernel messages
514 03:49:43.649221 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 03:49:43.650083 [login-action] Waiting for messages, (timeout 00:04:00)
516 03:49:43.650542 Waiting using forced prompt support (timeout 00:02:00)
517 03:49:43.659493 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j361380-arm-clang-15-multi-v7-defconfig-jwbm9) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Mon Nov 4 02:59:56 UTC 2024
518 03:49:43.665200 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 03:49:43.670794 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 03:49:43.679838 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 03:49:43.685547 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 03:49:43.691293 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 03:49:43.698007 [ 0.000000] Memory policy: Data cache writeback
524 03:49:43.698432 [ 0.000000] efi: UEFI not found.
525 03:49:43.706708 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 03:49:43.712493 [ 0.000000] Zone ranges:
527 03:49:43.718196 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 03:49:43.718623 [ 0.000000] Normal empty
529 03:49:43.723771 [ 0.000000] HighMem empty
530 03:49:43.729526 [ 0.000000] Movable zone start for each node
531 03:49:43.729977 [ 0.000000] Early memory node ranges
532 03:49:43.735270 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 03:49:43.744704 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 03:49:43.762813 [ 0.000000] CPU: All CPU(s) started in SVC mode.
535 03:49:43.768501 [ 0.000000] AM335X ES2.0 (sgx neon)
536 03:49:43.780269 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
537 03:49:43.797922 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/932598/extract-nfsrootfs-ncz1sii6,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
538 03:49:43.809439 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
539 03:49:43.815244 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
540 03:49:43.820994 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
541 03:49:43.830992 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
542 03:49:43.860434 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
543 03:49:43.866337 <6>[ 0.000000] trace event string verifier disabled
544 03:49:43.866769 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
545 03:49:43.872065 <6>[ 0.000000] rcu: RCU event tracing is enabled.
546 03:49:43.883579 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
547 03:49:43.889253 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
548 03:49:43.896536 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
549 03:49:43.911791 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
550 03:49:43.929428 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
551 03:49:43.936156 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
552 03:49:44.036014 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
553 03:49:44.047379 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
554 03:49:44.054301 <6>[ 0.008341] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
555 03:49:44.067361 <6>[ 0.019191] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
556 03:49:44.074777 <6>[ 0.034231] Console: colour dummy device 80x30
557 03:49:44.080951 Matched prompt #6: WARNING:
558 03:49:44.081422 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
559 03:49:44.086334 <3>[ 0.039134] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
560 03:49:44.092077 <3>[ 0.046209] This ensures that you still see kernel messages. Please
561 03:49:44.095330 <3>[ 0.052933] update your kernel commandline.
562 03:49:44.135820 <6>[ 0.057548] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
563 03:49:44.141503 <6>[ 0.096208] CPU: Testing write buffer coherency: ok
564 03:49:44.147446 <6>[ 0.101577] CPU0: Spectre v2: using BPIALL workaround
565 03:49:44.147924 <6>[ 0.107045] pid_max: default: 32768 minimum: 301
566 03:49:44.162018 <6>[ 0.112244] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 03:49:44.165968 <6>[ 0.120073] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 03:49:44.173021 <6>[ 0.129529] CPU0: thread -1, cpu 0, socket -1, mpidr 0
569 03:49:44.181540 <6>[ 0.136476] Setting up static identity map for 0x80300000 - 0x803000ac
570 03:49:44.187348 <6>[ 0.146212] rcu: Hierarchical SRCU implementation.
571 03:49:44.194998 <6>[ 0.151505] rcu: Max phase no-delay instances is 1000.
572 03:49:44.203718 <6>[ 0.162846] EFI services will not be available.
573 03:49:44.209614 <6>[ 0.168144] smp: Bringing up secondary CPUs ...
574 03:49:44.215285 <6>[ 0.173204] smp: Brought up 1 node, 1 CPU
575 03:49:44.223502 <6>[ 0.177603] SMP: Total of 1 processors activated (996.14 BogoMIPS).
576 03:49:44.229452 <6>[ 0.184378] CPU: All CPU(s) started in SVC mode.
577 03:49:44.241626 <6>[ 0.189588] Memory: 404432K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50616K reserved, 65536K cma-reserved, 0K highmem)
578 03:49:44.247291 <6>[ 0.205881] devtmpfs: initialized
579 03:49:44.270761 <6>[ 0.224010] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
580 03:49:44.279050 <6>[ 0.232629] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
581 03:49:44.288164 <6>[ 0.243090] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
582 03:49:44.298901 <6>[ 0.255368] pinctrl core: initialized pinctrl subsystem
583 03:49:44.308490 <6>[ 0.266222] DMI not present or invalid.
584 03:49:44.316825 <6>[ 0.272118] NET: Registered PF_NETLINK/PF_ROUTE protocol family
585 03:49:44.326441 <6>[ 0.281112] DMA: preallocated 256 KiB pool for atomic coherent allocations
586 03:49:44.341532 <6>[ 0.292747] thermal_sys: Registered thermal governor 'step_wise'
587 03:49:44.342120 <6>[ 0.292924] cpuidle: using governor menu
588 03:49:44.369023 <6>[ 0.328339] No ATAGs?
589 03:49:44.375182 <6>[ 0.331078] hw-breakpoint: debug architecture 0x4 unsupported.
590 03:49:44.385553 <6>[ 0.343220] Serial: AMBA PL011 UART driver
591 03:49:44.416415 <6>[ 0.375546] iommu: Default domain type: Translated
592 03:49:44.425421 <6>[ 0.380900] iommu: DMA domain TLB invalidation policy: strict mode
593 03:49:44.451921 <5>[ 0.410627] SCSI subsystem initialized
594 03:49:44.457893 <6>[ 0.415557] usbcore: registered new interface driver usbfs
595 03:49:44.463624 <6>[ 0.421627] usbcore: registered new interface driver hub
596 03:49:44.470478 <6>[ 0.427418] usbcore: registered new device driver usb
597 03:49:44.476161 <6>[ 0.433976] pps_core: LinuxPPS API ver. 1 registered
598 03:49:44.487670 <6>[ 0.439366] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
599 03:49:44.494911 <6>[ 0.449100] PTP clock support registered
600 03:49:44.495360 <6>[ 0.453570] EDAC MC: Ver: 3.0.0
601 03:49:44.552343 <6>[ 0.509137] scmi_core: SCMI protocol bus registered
602 03:49:44.558311 <6>[ 0.517361] vgaarb: loaded
603 03:49:44.570653 <6>[ 0.530136] clocksource: Switched to clocksource dmtimer
604 03:49:44.609869 <6>[ 0.568712] NET: Registered PF_INET protocol family
605 03:49:44.622551 <6>[ 0.574429] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
606 03:49:44.628430 <6>[ 0.583445] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
607 03:49:44.639835 <6>[ 0.592385] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
608 03:49:44.645675 <6>[ 0.600650] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
609 03:49:44.657136 <6>[ 0.608919] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
610 03:49:44.662971 <6>[ 0.616647] TCP: Hash tables configured (established 4096 bind 4096)
611 03:49:44.668843 <6>[ 0.623568] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
612 03:49:44.674747 <6>[ 0.630609] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
613 03:49:44.682320 <6>[ 0.638196] NET: Registered PF_UNIX/PF_LOCAL protocol family
614 03:49:44.763910 <6>[ 0.717549] RPC: Registered named UNIX socket transport module.
615 03:49:44.764691 <6>[ 0.724008] RPC: Registered udp transport module.
616 03:49:44.769726 <6>[ 0.729118] RPC: Registered tcp transport module.
617 03:49:44.778234 <6>[ 0.734240] RPC: Registered tcp-with-tls transport module.
618 03:49:44.784084 <6>[ 0.740167] RPC: Registered tcp NFSv4.1 backchannel transport module.
619 03:49:44.791533 <6>[ 0.747077] PCI: CLS 0 bytes, default 64
620 03:49:44.793716 <5>[ 0.752935] Initialise system trusted keyrings
621 03:49:44.817713 <6>[ 0.774020] Trying to unpack rootfs image as initramfs...
622 03:49:44.887911 <6>[ 0.841042] workingset: timestamp_bits=30 max_order=17 bucket_order=0
623 03:49:44.892624 <6>[ 0.848567] squashfs: version 4.0 (2009/01/31) Phillip Lougher
624 03:49:44.949944 <5>[ 0.909021] NFS: Registering the id_resolver key type
625 03:49:44.955573 <5>[ 0.914724] Key type id_resolver registered
626 03:49:44.961213 <5>[ 0.919302] Key type id_legacy registered
627 03:49:44.967179 <6>[ 0.923768] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
628 03:49:44.976690 <6>[ 0.930971] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
629 03:49:45.041571 <5>[ 1.000886] Key type asymmetric registered
630 03:49:45.047533 <5>[ 1.005414] Asymmetric key parser 'x509' registered
631 03:49:45.055869 <6>[ 1.010964] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
632 03:49:45.061600 <6>[ 1.018854] io scheduler mq-deadline registered
633 03:49:45.070503 <6>[ 1.023837] io scheduler kyber registered
634 03:49:45.071249 <6>[ 1.028293] io scheduler bfq registered
635 03:49:45.185024 <6>[ 1.140603] ledtrig-cpu: registered to indicate activity on CPUs
636 03:49:45.478914 <6>[ 1.434218] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 03:49:45.534039 <6>[ 1.493154] msm_serial: driver initialized
638 03:49:45.540246 <6>[ 1.497939] SuperH (H)SCI(F) driver initialized
639 03:49:45.546165 <6>[ 1.503307] STMicroelectronics ASC driver initialized
640 03:49:45.551206 <6>[ 1.508922] STM32 USART driver initialized
641 03:49:45.652331 <6>[ 1.611040] brd: module loaded
642 03:49:45.683668 <6>[ 1.642329] loop: module loaded
643 03:49:45.719827 <6>[ 1.678084] CAN device driver interface
644 03:49:45.726643 <6>[ 1.683425] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 03:49:45.732219 <6>[ 1.690530] e1000e: Intel(R) PRO/1000 Network Driver
646 03:49:45.738172 <6>[ 1.695922] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 03:49:45.743767 <6>[ 1.702382] igb: Intel(R) Gigabit Ethernet Network Driver
648 03:49:45.752089 <6>[ 1.708206] igb: Copyright (c) 2007-2014 Intel Corporation.
649 03:49:45.763863 <6>[ 1.717441] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 03:49:45.769573 <6>[ 1.723615] usbcore: registered new interface driver pegasus
651 03:49:45.775292 <6>[ 1.729745] usbcore: registered new interface driver asix
652 03:49:45.781171 <6>[ 1.735633] usbcore: registered new interface driver ax88179_178a
653 03:49:45.786886 <6>[ 1.742228] usbcore: registered new interface driver cdc_ether
654 03:49:45.792630 <6>[ 1.748529] usbcore: registered new interface driver smsc75xx
655 03:49:45.798510 <6>[ 1.754775] usbcore: registered new interface driver smsc95xx
656 03:49:45.804247 <6>[ 1.761013] usbcore: registered new interface driver net1080
657 03:49:45.810003 <6>[ 1.767133] usbcore: registered new interface driver cdc_subset
658 03:49:45.815774 <6>[ 1.773545] usbcore: registered new interface driver zaurus
659 03:49:45.823411 <6>[ 1.779587] usbcore: registered new interface driver cdc_ncm
660 03:49:45.833315 <6>[ 1.789077] usbcore: registered new interface driver usb-storage
661 03:49:45.842780 <6>[ 1.800333] i2c_dev: i2c /dev entries driver
662 03:49:45.867240 <5>[ 1.818639] cpuidle: enable-method property 'ti,am3352' found operations
663 03:49:45.873105 <6>[ 1.828207] sdhci: Secure Digital Host Controller Interface driver
664 03:49:45.881107 <6>[ 1.834973] sdhci: Copyright(c) Pierre Ossman
665 03:49:45.888227 <6>[ 1.841558] Synopsys Designware Multimedia Card Interface Driver
666 03:49:45.893419 <6>[ 1.849396] sdhci-pltfm: SDHCI platform and OF driver helper
667 03:49:45.907646 <6>[ 1.859403] usbcore: registered new interface driver usbhid
668 03:49:45.908018 <6>[ 1.865528] usbhid: USB HID core driver
669 03:49:45.920304 <6>[ 1.877205] NET: Registered PF_INET6 protocol family
670 03:49:46.395844 <6>[ 2.355291] Segment Routing with IPv6
671 03:49:46.401721 <6>[ 2.359438] In-situ OAM (IOAM) with IPv6
672 03:49:46.408601 <6>[ 2.363957] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
673 03:49:46.415745 <6>[ 2.371310] NET: Registered PF_PACKET protocol family
674 03:49:46.421675 <6>[ 2.376797] can: controller area network core
675 03:49:46.422214 <6>[ 2.381694] NET: Registered PF_CAN protocol family
676 03:49:46.427431 <6>[ 2.386899] can: raw protocol
677 03:49:46.430254 <6>[ 2.390250] can: broadcast manager protocol
678 03:49:46.436741 <6>[ 2.394829] can: netlink gateway - max_hops=1
679 03:49:46.442874 <5>[ 2.400408] Key type dns_resolver registered
680 03:49:46.448617 <6>[ 2.405410] ThumbEE CPU extension supported.
681 03:49:46.454831 <5>[ 2.410167] Registering SWP/SWPB emulation handler
682 03:49:46.460368 <3>[ 2.415828] omap_voltage_late_init: Voltage driver support not added
683 03:49:46.653635 <5>[ 2.610587] Loading compiled-in X.509 certificates
684 03:49:46.790794 <6>[ 2.737116] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
685 03:49:46.797913 <6>[ 2.753870] pinctrl-single 44e10800.pinmux: 142 pins, size 568
686 03:49:46.823910 <3>[ 2.778082] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
687 03:49:47.027791 <3>[ 2.981055] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
688 03:49:47.233606 <6>[ 3.191201] OMAP GPIO hardware version 0.1
689 03:49:47.254812 <6>[ 3.210455] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
690 03:49:47.335859 <4>[ 3.292225] at24 2-0054: supply vcc not found, using dummy regulator
691 03:49:47.370023 <4>[ 3.325480] at24 2-0055: supply vcc not found, using dummy regulator
692 03:49:47.408149 <4>[ 3.363621] at24 2-0056: supply vcc not found, using dummy regulator
693 03:49:47.447865 <4>[ 3.403309] at24 2-0057: supply vcc not found, using dummy regulator
694 03:49:47.486697 <6>[ 3.442942] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
695 03:49:47.544493 <3>[ 3.496729] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
696 03:49:47.569420 <6>[ 3.517963] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
697 03:49:47.590851 <4>[ 3.545083] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
698 03:49:47.606591 <4>[ 3.560805] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
699 03:49:47.695482 <6>[ 3.651159] omap_rng 48310000.rng: Random Number Generator ver. 20
700 03:49:47.719622 <5>[ 3.678095] random: crng init done
701 03:49:47.745916 <6>[ 3.703770] Freeing initrd memory: 14992K
702 03:49:47.766019 <6>[ 3.720154] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
703 03:49:47.819384 <6>[ 3.772612] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
704 03:49:47.825203 <6>[ 3.782975] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
705 03:49:47.836956 <6>[ 3.790323] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
706 03:49:47.842782 <6>[ 3.797799] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
707 03:49:47.854312 <6>[ 3.805936] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
708 03:49:47.861789 <6>[ 3.817581] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5c:d5:d8
709 03:49:47.874935 <5>[ 3.826680] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
710 03:49:47.903426 <3>[ 3.857160] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
711 03:49:47.909173 <6>[ 3.865765] edma 49000000.dma: TI EDMA DMA engine driver
712 03:49:47.982292 <3>[ 3.935370] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
713 03:49:47.997174 <6>[ 3.949877] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
714 03:49:48.010186 <3>[ 3.967109] l3-aon-clkctrl:0000:0: failed to disable
715 03:49:48.065282 <6>[ 4.018968] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
716 03:49:48.071020 <6>[ 4.028489] printk: legacy console [ttyS0] enabled
717 03:49:48.076692 <6>[ 4.028489] printk: legacy console [ttyS0] enabled
718 03:49:48.082365 <6>[ 4.038838] printk: legacy bootconsole [omap8250] disabled
719 03:49:48.088175 <6>[ 4.038838] printk: legacy bootconsole [omap8250] disabled
720 03:49:48.118226 <4>[ 4.070955] tps65217-pmic: Failed to locate of_node [id: -1]
721 03:49:48.120973 <4>[ 4.078375] tps65217-bl: Failed to locate of_node [id: -1]
722 03:49:48.138905 <6>[ 4.098558] tps65217 0-0024: TPS65217 ID 0xe version 1.2
723 03:49:48.159378 <6>[ 4.105598] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
724 03:49:48.171260 <6>[ 4.119364] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
725 03:49:48.173920 <6>[ 4.131284] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
726 03:49:48.197577 <6>[ 4.151647] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
727 03:49:48.203434 <6>[ 4.160807] sdhci-omap 48060000.mmc: Got CD GPIO
728 03:49:48.211528 <4>[ 4.165960] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
729 03:49:48.226353 <4>[ 4.179628] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
730 03:49:48.232848 <4>[ 4.188359] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
731 03:49:48.242238 <4>[ 4.197082] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
732 03:49:48.341777 <6>[ 4.296860] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
733 03:49:48.381704 <6>[ 4.335960] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 03:49:48.402315 <6>[ 4.355585] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
735 03:49:48.409068 <6>[ 4.364529] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
736 03:49:48.450045 <6>[ 4.399606] mmc0: new high speed SDHC card at address 0001
737 03:49:48.450551 <6>[ 4.407653] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
738 03:49:48.457162 <6>[ 4.416603] mmcblk0: p1
739 03:49:48.490000 <6>[ 4.441425] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
740 03:49:48.510201 <6>[ 4.461072] mmc1: new high speed MMC card at address 0001
741 03:49:48.510716 <6>[ 4.468335] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
742 03:49:48.519353 <6>[ 4.478125] mmcblk1:
743 03:49:48.523379 <6>[ 4.481463] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
744 03:49:48.531760 <6>[ 4.489032] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
745 03:49:48.540521 <6>[ 4.496521] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
746 03:49:50.637608 <6>[ 6.591204] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
747 03:49:50.790700 <5>[ 6.630231] Sending DHCP requests ., OK
748 03:49:50.802178 <6>[ 6.754585] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.23
749 03:49:50.802684 <6>[ 6.762751] IP-Config: Complete:
750 03:49:50.813445 <6>[ 6.766291] device=eth0, hwaddr=90:59:af:5c:d5:d8, ipaddr=192.168.6.23, mask=255.255.255.0, gw=192.168.6.1
751 03:49:50.819301 <6>[ 6.776814] host=192.168.6.23, domain=, nis-domain=(none)
752 03:49:50.831625 <6>[ 6.783032] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
753 03:49:50.832144 <6>[ 6.783068] nameserver0=10.255.253.1
754 03:49:50.837697 <6>[ 6.795695] clk: Disabling unused clocks
755 03:49:50.842740 <6>[ 6.800432] PM: genpd: Disabling unused power domains
756 03:49:50.861251 <6>[ 6.817165] Freeing unused kernel image (initmem) memory: 2048K
757 03:49:50.868730 <6>[ 6.827071] Run /init as init process
758 03:49:50.895205 Loading, please wait...
759 03:49:50.973208 Starting systemd-udevd version 252.22-1~deb12u1
760 03:49:54.152552 <4>[ 10.105050] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 03:49:54.309733 <4>[ 10.262232] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
762 03:49:54.522709 <6>[ 10.482608] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
763 03:49:54.533396 <6>[ 10.488288] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
764 03:49:54.775164 <6>[ 10.733676] hub 1-0:1.0: USB hub found
765 03:49:54.816345 <6>[ 10.774538] tda998x 0-0070: found TDA19988
766 03:49:54.842059 <6>[ 10.800427] hub 1-0:1.0: 1 port detected
767 03:49:57.836716 Begin: Loading essential drivers ... done.
768 03:49:57.846768 Begin: Running /scripts/init-premount ... done.
769 03:49:57.857988 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
770 03:49:57.861272 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
771 03:49:57.870467 Device /sys/class/net/eth0 found
772 03:49:57.870898 done.
773 03:49:57.952141 Begin: Waiting up to 180 secs for any network device to become available ... done.
774 03:49:58.022785 IP-Config: eth0 hardware address 90:59:af:5c:d5:d8 mtu 1500 DHCP
775 03:49:58.143371 IP-Config: eth0 guessed broadcast address 192.168.6.255
776 03:49:58.148825 IP-Config: eth0 complete (dhcp from 192.168.6.1):
777 03:49:58.154444 address: 192.168.6.23 broadcast: 192.168.6.255 netmask: 255.255.255.0
778 03:49:58.165628 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
779 03:49:58.166131 rootserver: 192.168.6.1 rootpath:
780 03:49:58.169275 filename :
781 03:49:58.234607 done.
782 03:49:58.246143 Begin: Running /scripts/nfs-bottom ... done.
783 03:49:58.317417 Begin: Running /scripts/init-bottom ... done.
784 03:49:59.882488 <30>[ 15.837983] systemd[1]: System time before build time, advancing clock.
785 03:50:00.087293 <30>[ 16.017630] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
786 03:50:00.128404 <30>[ 16.085754] systemd[1]: Detected architecture arm.
787 03:50:00.142719
788 03:50:00.143185 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
789 03:50:00.143598
790 03:50:00.174625 <30>[ 16.130870] systemd[1]: Hostname set to <debian-bookworm-armhf>.
791 03:50:02.359318 <30>[ 18.314573] systemd[1]: Queued start job for default target graphical.target.
792 03:50:02.376097 <30>[ 18.329264] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
793 03:50:02.383667 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
794 03:50:02.410384 <30>[ 18.362632] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
795 03:50:02.416907 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
796 03:50:02.442889 <30>[ 18.396454] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
797 03:50:02.456064 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
798 03:50:02.478584 <30>[ 18.432137] systemd[1]: Created slice user.slice - User and Session Slice.
799 03:50:02.485230 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
800 03:50:02.513948 <30>[ 18.461556] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
801 03:50:02.519925 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
802 03:50:02.537721 <30>[ 18.491326] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
803 03:50:02.546814 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
804 03:50:02.578713 <30>[ 18.521415] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
805 03:50:02.585227 <30>[ 18.541947] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
806 03:50:02.593793 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
807 03:50:02.616788 <30>[ 18.570660] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
808 03:50:02.625031 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
809 03:50:02.647503 <30>[ 18.601060] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
810 03:50:02.655971 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
811 03:50:02.677413 <30>[ 18.631208] systemd[1]: Reached target paths.target - Path Units.
812 03:50:02.682568 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
813 03:50:02.707014 <30>[ 18.660815] systemd[1]: Reached target remote-fs.target - Remote File Systems.
814 03:50:02.713528 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
815 03:50:02.736966 <30>[ 18.690796] systemd[1]: Reached target slices.target - Slice Units.
816 03:50:02.742441 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
817 03:50:02.767330 <30>[ 18.720933] systemd[1]: Reached target swap.target - Swaps.
818 03:50:02.770665 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
819 03:50:02.797805 <30>[ 18.750985] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
820 03:50:02.805774 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
821 03:50:02.829582 <30>[ 18.783458] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
822 03:50:02.842539 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
823 03:50:02.927161 <30>[ 18.875895] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
824 03:50:02.940101 <30>[ 18.893592] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
825 03:50:02.947956 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
826 03:50:02.970323 <30>[ 18.922995] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
827 03:50:02.976835 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
828 03:50:02.999935 <30>[ 18.953417] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
829 03:50:03.008043 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
830 03:50:03.031459 <30>[ 18.984913] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
831 03:50:03.037158 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
832 03:50:03.066478 <30>[ 19.021902] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
833 03:50:03.078266 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
834 03:50:03.104206 <30>[ 19.051910] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
835 03:50:03.123199 <30>[ 19.070763] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
836 03:50:03.167182 <30>[ 19.120823] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
837 03:50:03.174648 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
838 03:50:03.213266 <30>[ 19.167648] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
839 03:50:03.238112 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
840 03:50:03.290074 <30>[ 19.243496] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
841 03:50:03.307862 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
842 03:50:03.387531 <30>[ 19.341551] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
843 03:50:03.407208 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
844 03:50:03.466918 <30>[ 19.421340] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
845 03:50:03.495721 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
846 03:50:03.547237 <30>[ 19.502105] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
847 03:50:03.565752 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
848 03:50:03.604172 <30>[ 19.557727] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
849 03:50:03.635090 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
850 03:50:03.676789 <30>[ 19.631493] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
851 03:50:03.694582 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
852 03:50:03.755737 <30>[ 19.711371] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
853 03:50:03.776410 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
854 03:50:03.806079 <28>[ 19.752704] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
855 03:50:03.813508 <28>[ 19.768328] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
856 03:50:03.867952 <30>[ 19.823105] systemd[1]: Starting systemd-journald.service - Journal Service...
857 03:50:03.886205 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
858 03:50:03.958780 <30>[ 19.913295] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
859 03:50:03.979436 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
860 03:50:04.038461 <30>[ 19.993221] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
861 03:50:04.089186 Starting [0;1;39msystemd-network-g… units from Kernel command line...
862 03:50:04.179450 <30>[ 20.133616] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
863 03:50:04.229405 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
864 03:50:04.281902 <30>[ 20.235836] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
865 03:50:04.335955 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
866 03:50:04.388653 <30>[ 20.343571] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
867 03:50:04.436775 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
868 03:50:04.467401 <30>[ 20.422129] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
869 03:50:04.506615 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
870 03:50:04.530837 <30>[ 20.484512] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
871 03:50:04.559349 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
872 03:50:04.749638 <30>[ 20.705042] systemd[1]: modprobe@configfs.service: Deactivated successfully.
873 03:50:04.787604 <30>[ 20.741887] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
874 03:50:04.807411 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
875 03:50:04.837880 <30>[ 20.791855] systemd[1]: Started systemd-journald.service - Journal Service.
876 03:50:04.844603 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
877 03:50:04.888682 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
878 03:50:04.918943 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
879 03:50:04.949304 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
880 03:50:04.971661 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
881 03:50:05.008038 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
882 03:50:05.036964 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
883 03:50:05.060291 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
884 03:50:05.096801 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
885 03:50:05.126701 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
886 03:50:05.178819 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
887 03:50:05.222595 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
888 03:50:05.272400 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
889 03:50:05.365372 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
890 03:50:05.465910 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
891 03:50:05.608445 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
892 03:50:05.661134 <46>[ 21.616383] systemd-journald[163]: Received client request to flush runtime journal.
893 03:50:05.710151 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
894 03:50:05.865045 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
895 03:50:06.791212 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
896 03:50:06.864033 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
897 03:50:07.341655 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
898 03:50:07.499373 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
899 03:50:07.518854 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
900 03:50:07.537849 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
901 03:50:07.607109 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
902 03:50:07.655928 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
903 03:50:08.621603 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
904 03:50:08.689147 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
905 03:50:08.866660 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
906 03:50:08.985987 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
907 03:50:09.032184 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
908 03:50:10.318567 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
909 03:50:11.174082 <5>[ 27.129079] cfg80211: Loading compiled-in X.509 certificates for regulatory database
910 03:50:11.922306 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
911 03:50:12.836865 <5>[ 28.794745] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
912 03:50:12.848348 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
913 03:50:12.938254 <5>[ 28.894604] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
914 03:50:12.953349 <4>[ 28.908157] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
915 03:50:12.958721 <6>[ 28.917298] cfg80211: failed to load regulatory.db
916 03:50:13.900781 <46>[ 29.845841] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
917 03:50:13.965761 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
918 03:50:13.987373 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
919 03:50:14.075969 <46>[ 30.024862] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
920 03:50:23.156042 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
921 03:50:23.183755 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
922 03:50:23.208288 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
923 03:50:23.227934 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
924 03:50:23.286905 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
925 03:50:23.339171 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
926 03:50:23.387288 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
927 03:50:23.425989 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
928 03:50:23.472761 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
929 03:50:23.517431 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
930 03:50:23.541726 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
931 03:50:23.573659 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
932 03:50:23.603485 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
933 03:50:23.650983 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
934 03:50:23.681995 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
935 03:50:23.708681 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
936 03:50:23.750128 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
937 03:50:23.785511 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
938 03:50:23.808150 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
939 03:50:23.831264 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
940 03:50:23.868216 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
941 03:50:23.884809 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
942 03:50:23.908712 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
943 03:50:23.986445 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
944 03:50:24.025870 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
945 03:50:24.127830 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
946 03:50:24.219744 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
947 03:50:24.304828 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
948 03:50:24.336388 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
949 03:50:24.355547 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
950 03:50:24.548014 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
951 03:50:24.607474 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
952 03:50:24.679313 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
953 03:50:24.706937 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
954 03:50:24.736611 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
955 03:50:24.967009 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
956 03:50:25.303012 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
957 03:50:25.355945 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
958 03:50:25.381063 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
959 03:50:25.476265 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
960 03:50:25.659079 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
961 03:50:25.815431
962 03:50:25.818161 Debian GNU/Linux 12 deworm-armhf login: root (automatic login)
963 03:50:25.818797
964 03:50:26.157785 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Mon Nov 4 02:59:56 UTC 2024 armv7l
965 03:50:26.158428
966 03:50:26.163314 The programs included with the Debian GNU/Linux system are free software;
967 03:50:26.168978 the exact distribution terms for each program are described in the
968 03:50:26.174612 individual files in /usr/share/doc/*/copyright.
969 03:50:26.175138
970 03:50:26.181800 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
971 03:50:26.182348 permitted by applicable law.
972 03:50:30.815734 Unable to match end of the kernel message
974 03:50:30.817272 Setting prompt string to ['/ #']
975 03:50:30.817906 end: 2.4.4.1 login-action (duration 00:00:47) [common]
977 03:50:30.819301 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
978 03:50:30.819864 start: 2.4.5 expect-shell-connection (timeout 00:03:12) [common]
979 03:50:30.820361 Setting prompt string to ['/ #']
980 03:50:30.820802 Forcing a shell prompt, looking for ['/ #']
982 03:50:30.871784 / #
983 03:50:30.872406 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
984 03:50:30.872926 Waiting using forced prompt support (timeout 00:02:30)
985 03:50:30.876973
986 03:50:30.883182 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
987 03:50:30.883743 start: 2.4.6 export-device-env (timeout 00:03:12) [common]
988 03:50:30.884231 Sending with 10 millisecond of delay
990 03:50:35.871262 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/932598/extract-nfsrootfs-ncz1sii6'
991 03:50:35.882263 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/932598/extract-nfsrootfs-ncz1sii6'
992 03:50:35.883121 Sending with 10 millisecond of delay
994 03:50:37.980900 / # export NFS_SERVER_IP='192.168.6.3'
995 03:50:37.991765 export NFS_SERVER_IP='192.168.6.3'
996 03:50:37.992932 end: 2.4.6 export-device-env (duration 00:00:07) [common]
997 03:50:37.993578 end: 2.4 uboot-commands (duration 00:01:55) [common]
998 03:50:37.994327 end: 2 uboot-action (duration 00:01:55) [common]
999 03:50:37.995006 start: 3 lava-test-retry (timeout 00:06:55) [common]
1000 03:50:37.995678 start: 3.1 lava-test-shell (timeout 00:06:55) [common]
1001 03:50:37.996224 Using namespace: common
1003 03:50:38.097478 / # #
1004 03:50:38.098137 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1005 03:50:38.103061 #
1006 03:50:38.109498 Using /lava-932598
1008 03:50:38.210715 / # export SHELL=/bin/bash
1009 03:50:38.215079 export SHELL=/bin/bash
1011 03:50:38.323064 / # . /lava-932598/environment
1012 03:50:38.328324 . /lava-932598/environment
1014 03:50:38.441769 / # /lava-932598/bin/lava-test-runner /lava-932598/0
1015 03:50:38.442467 Test shell timeout: 10s (minimum of the action and connection timeout)
1016 03:50:38.447168 /lava-932598/bin/lava-test-runner /lava-932598/0
1017 03:50:38.882951 + export TESTRUN_ID=0_timesync-off
1018 03:50:38.890735 + TESTRUN_ID=0_timesync-off
1019 03:50:38.891230 + cd /lava-932598/0/tests/0_timesync-off
1020 03:50:38.891696 ++ cat uuid
1021 03:50:38.907720 + UUID=932598_1.6.2.4.1
1022 03:50:38.908212 + set +x
1023 03:50:38.915722 <LAVA_SIGNAL_STARTRUN 0_timesync-off 932598_1.6.2.4.1>
1024 03:50:38.916200 + systemctl stop systemd-timesyncd
1025 03:50:38.916968 Received signal: <STARTRUN> 0_timesync-off 932598_1.6.2.4.1
1026 03:50:38.917461 Starting test lava.0_timesync-off (932598_1.6.2.4.1)
1027 03:50:38.918094 Skipping test definition patterns.
1028 03:50:39.221706 + set +x
1029 03:50:39.222279 <LAVA_SIGNAL_ENDRUN 0_timesync-off 932598_1.6.2.4.1>
1030 03:50:39.222997 Received signal: <ENDRUN> 0_timesync-off 932598_1.6.2.4.1
1031 03:50:39.223540 Ending use of test pattern.
1032 03:50:39.223989 Ending test lava.0_timesync-off (932598_1.6.2.4.1), duration 0.31
1034 03:50:39.377335 + export TESTRUN_ID=1_kselftest-dt
1035 03:50:39.384365 + TESTRUN_ID=1_kselftest-dt
1036 03:50:39.384861 + cd /lava-932598/0/tests/1_kselftest-dt
1037 03:50:39.385319 ++ cat uuid
1038 03:50:39.402511 + UUID=932598_1.6.2.4.5
1039 03:50:39.403001 + set +x
1040 03:50:39.408065 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 932598_1.6.2.4.5>
1041 03:50:39.408539 + cd ./automated/linux/kselftest/
1042 03:50:39.409248 Received signal: <STARTRUN> 1_kselftest-dt 932598_1.6.2.4.5
1043 03:50:39.409711 Starting test lava.1_kselftest-dt (932598_1.6.2.4.5)
1044 03:50:39.410281 Skipping test definition patterns.
1045 03:50:39.434854 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1046 03:50:39.542048 INFO: install_deps skipped
1047 03:50:40.205678 --2024-11-04 03:50:40-- http://storage.kernelci.org/mainline/master/v6.12-rc6/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
1048 03:50:40.470800 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1049 03:50:40.616686 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1050 03:50:40.762179 HTTP request sent, awaiting response... 200 OK
1051 03:50:40.762661 Length: 2542484 (2.4M) [application/octet-stream]
1052 03:50:40.767648 Saving to: 'kselftest_armhf.tar.gz'
1053 03:50:40.768117
1054 03:50:42.533921
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 2%[ ] 49.92K 174KB/s
kselftest_armhf.tar 7%[> ] 194.76K 335KB/s
kselftest_armhf.tar 27%[====> ] 684.14K 747KB/s
kselftest_armhf.tar 50%[=========> ] 1.23M 1.08MB/s
kselftest_armhf.tar 63%[===========> ] 1.54M 1.06MB/s
kselftest_armhf.tar 95%[==================> ] 2.31M 1.40MB/s
kselftest_armhf.tar 100%[===================>] 2.42M 1.37MB/s in 1.8s
1055 03:50:42.534556
1056 03:50:42.894635 2024-11-04 03:50:42 (1.37 MB/s) - 'kselftest_armhf.tar.gz' saved [2542484/2542484]
1057 03:50:42.895245
1058 03:50:55.897303 skiplist:
1059 03:50:55.898026 ========================================
1060 03:50:55.902877 ========================================
1061 03:50:56.008239 dt:test_unprobed_devices.sh
1062 03:50:56.043969 ============== Tests to run ===============
1063 03:50:56.051534 dt:test_unprobed_devices.sh
1064 03:50:56.055447 ===========End Tests to run ===============
1065 03:50:56.064001 shardfile-dt pass
1066 03:50:56.308193 <12>[ 72.268051] kselftest: Running tests in dt
1067 03:50:56.337762 TAP version 13
1068 03:50:56.362284 1..1
1069 03:50:56.417470 # timeout set to 45
1070 03:50:56.417969 # selftests: dt: test_unprobed_devices.sh
1071 03:50:57.245964 # TAP version 13
1072 03:51:22.695220 # 1..257
1073 03:51:22.874560 # ok 1 / # SKIP
1074 03:51:22.896811 # ok 2 /clk_mcasp0
1075 03:51:22.976653 # ok 3 /clk_mcasp0_fixed # SKIP
1076 03:51:23.044107 # ok 4 /cpus/cpu@0 # SKIP
1077 03:51:23.122689 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1078 03:51:23.144121 # ok 6 /fixedregulator0
1079 03:51:23.159966 # ok 7 /leds
1080 03:51:23.185464 # ok 8 /ocp
1081 03:51:23.205675 # ok 9 /ocp/interconnect@44c00000
1082 03:51:23.233721 # ok 10 /ocp/interconnect@44c00000/segment@0
1083 03:51:23.253686 # ok 11 /ocp/interconnect@44c00000/segment@100000
1084 03:51:23.279878 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1085 03:51:23.351051 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1086 03:51:23.371250 # ok 14 /ocp/interconnect@44c00000/segment@200000
1087 03:51:23.400751 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1088 03:51:23.509523 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1089 03:51:23.580661 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1090 03:51:23.655645 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1091 03:51:23.728480 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1092 03:51:23.801359 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1093 03:51:23.879479 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1094 03:51:23.953318 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1095 03:51:24.022489 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1096 03:51:24.102413 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1097 03:51:24.172510 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1098 03:51:24.244532 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1099 03:51:24.316151 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1100 03:51:24.389866 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1101 03:51:24.463426 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1102 03:51:24.539239 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1103 03:51:24.613521 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1104 03:51:24.682830 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1105 03:51:24.755261 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1106 03:51:24.827694 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1107 03:51:24.901345 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1108 03:51:24.973117 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1109 03:51:25.047792 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1110 03:51:25.123915 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1111 03:51:25.195681 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1112 03:51:25.269621 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1113 03:51:25.342864 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1114 03:51:25.417550 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1115 03:51:25.491417 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1116 03:51:25.565713 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1117 03:51:25.639131 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1118 03:51:25.712261 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1119 03:51:25.785681 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1120 03:51:25.858352 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1121 03:51:25.933354 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1122 03:51:26.007863 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1123 03:51:26.081482 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1124 03:51:26.162135 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1125 03:51:26.230246 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1126 03:51:26.304895 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1127 03:51:26.379965 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1128 03:51:26.458352 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1129 03:51:26.532264 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1130 03:51:26.599468 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1131 03:51:26.680832 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1132 03:51:26.748285 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1133 03:51:26.821658 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1134 03:51:26.897105 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1135 03:51:26.975249 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1136 03:51:27.047482 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1137 03:51:27.120608 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1138 03:51:27.195472 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1139 03:51:27.270115 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1140 03:51:27.342466 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1141 03:51:27.416047 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1142 03:51:27.492611 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1143 03:51:27.564880 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1144 03:51:27.637321 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1145 03:51:27.710975 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1146 03:51:27.791380 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1147 03:51:27.860063 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1148 03:51:27.933245 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1149 03:51:28.010802 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1150 03:51:28.083822 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1151 03:51:28.152993 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1152 03:51:28.226956 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1153 03:51:28.300309 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1154 03:51:28.373881 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1155 03:51:28.446050 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1156 03:51:28.520907 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1157 03:51:28.594548 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1158 03:51:28.668079 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1159 03:51:28.742544 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1160 03:51:28.820049 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1161 03:51:28.894918 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1162 03:51:28.965250 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1163 03:51:29.036265 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1164 03:51:29.111792 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1165 03:51:29.189368 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1166 03:51:29.260098 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1167 03:51:29.281098 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1168 03:51:29.309945 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1169 03:51:29.331935 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1170 03:51:29.354285 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1171 03:51:29.378190 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1172 03:51:29.402688 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1173 03:51:29.426851 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1174 03:51:29.448493 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1175 03:51:29.558166 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1176 03:51:29.587536 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1177 03:51:29.612124 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1178 03:51:29.631357 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1179 03:51:29.741691 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1180 03:51:29.817500 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1181 03:51:29.890929 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1182 03:51:29.967186 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1183 03:51:30.038198 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1184 03:51:30.115220 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1185 03:51:30.187674 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1186 03:51:30.261256 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1187 03:51:30.334722 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1188 03:51:30.408665 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1189 03:51:30.483407 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1190 03:51:30.556931 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1191 03:51:30.633390 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1192 03:51:30.709753 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1193 03:51:30.779762 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1194 03:51:30.856474 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1195 03:51:30.876008 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1196 03:51:30.948490 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1197 03:51:31.018772 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1198 03:51:31.093217 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1199 03:51:31.115718 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1200 03:51:31.189341 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1201 03:51:31.216748 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1202 03:51:31.285384 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1203 03:51:31.310835 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1204 03:51:31.332940 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1205 03:51:31.363951 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1206 03:51:31.386570 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1207 03:51:31.409345 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1208 03:51:31.438352 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1209 03:51:31.462974 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1210 03:51:31.537248 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1211 03:51:31.559352 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1212 03:51:31.583684 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1213 03:51:31.661501 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1214 03:51:31.733110 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1215 03:51:31.756170 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1216 03:51:31.855894 # not ok 144 /ocp/interconnect@47c00000
1217 03:51:31.929708 # not ok 145 /ocp/interconnect@47c00000/segment@0
1218 03:51:31.954322 # ok 146 /ocp/interconnect@48000000
1219 03:51:31.978712 # ok 147 /ocp/interconnect@48000000/segment@0
1220 03:51:32.005064 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1221 03:51:32.028062 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1222 03:51:32.050465 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1223 03:51:32.072480 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1224 03:51:32.095676 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1225 03:51:32.121017 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1226 03:51:32.143125 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1227 03:51:32.220548 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1228 03:51:32.290973 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1229 03:51:32.313616 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1230 03:51:32.338060 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1231 03:51:32.361058 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1232 03:51:32.385952 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1233 03:51:32.410624 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1234 03:51:32.433522 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1235 03:51:32.455964 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1236 03:51:32.480342 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1237 03:51:32.503495 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1238 03:51:32.531114 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1239 03:51:32.558714 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1240 03:51:32.576702 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1241 03:51:32.605549 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1242 03:51:32.629015 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1243 03:51:32.650480 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1244 03:51:32.678740 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1245 03:51:32.700336 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1246 03:51:32.727015 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1247 03:51:32.748142 # ok 175 /ocp/interconnect@48000000/segment@100000
1248 03:51:32.770666 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1249 03:51:32.799011 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1250 03:51:32.872973 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1251 03:51:32.945730 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1252 03:51:33.021249 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1253 03:51:33.094766 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1254 03:51:33.165570 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1255 03:51:33.241136 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1256 03:51:33.314069 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1257 03:51:33.389072 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1258 03:51:33.408294 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1259 03:51:33.433044 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1260 03:51:33.456407 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1261 03:51:33.480864 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1262 03:51:33.511133 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1263 03:51:33.530980 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1264 03:51:33.552822 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1265 03:51:33.577335 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1266 03:51:33.602520 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1267 03:51:33.629173 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1268 03:51:33.650166 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1269 03:51:33.678596 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1270 03:51:33.698966 # ok 198 /ocp/interconnect@48000000/segment@200000
1271 03:51:33.726947 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1272 03:51:33.794757 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1273 03:51:33.816400 # ok 201 /ocp/interconnect@48000000/segment@300000
1274 03:51:33.841352 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1275 03:51:33.865459 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1276 03:51:33.891113 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1277 03:51:33.913749 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1278 03:51:33.937126 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1279 03:51:33.964992 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1280 03:51:34.040033 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1281 03:51:34.057697 # ok 209 /ocp/interconnect@4a000000
1282 03:51:34.083149 # ok 210 /ocp/interconnect@4a000000/segment@0
1283 03:51:34.109053 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1284 03:51:34.130701 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1285 03:51:34.159403 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1286 03:51:34.180374 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1287 03:51:34.250278 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1288 03:51:34.359169 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1289 03:51:34.431987 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1290 03:51:34.539659 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1291 03:51:34.611315 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1292 03:51:34.688368 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1293 03:51:34.788263 # not ok 221 /ocp/interconnect@4b140000
1294 03:51:34.865975 # not ok 222 /ocp/interconnect@4b140000/segment@0
1295 03:51:34.938978 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1296 03:51:34.956092 # ok 224 /ocp/target-module@40300000
1297 03:51:34.984259 # ok 225 /ocp/target-module@40300000/sram@0
1298 03:51:35.059770 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1299 03:51:35.130485 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1300 03:51:35.153317 # ok 228 /ocp/target-module@47400000
1301 03:51:35.178603 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1302 03:51:35.196762 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1303 03:51:35.220545 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1304 03:51:35.246971 # ok 232 /ocp/target-module@47400000/usb@1400
1305 03:51:35.268522 # ok 233 /ocp/target-module@47400000/usb@1800
1306 03:51:35.293564 # ok 234 /ocp/target-module@47810000
1307 03:51:35.310167 # ok 235 /ocp/target-module@49000000
1308 03:51:35.336805 # ok 236 /ocp/target-module@49000000/dma@0
1309 03:51:35.362034 # ok 237 /ocp/target-module@49800000
1310 03:51:35.385483 # ok 238 /ocp/target-module@49800000/dma@0
1311 03:51:35.403397 # ok 239 /ocp/target-module@49900000
1312 03:51:35.428236 # ok 240 /ocp/target-module@49900000/dma@0
1313 03:51:35.449214 # ok 241 /ocp/target-module@49a00000
1314 03:51:35.476761 # ok 242 /ocp/target-module@49a00000/dma@0
1315 03:51:35.497770 # ok 243 /ocp/target-module@4c000000
1316 03:51:35.573592 # not ok 244 /ocp/target-module@4c000000/emif@0
1317 03:51:35.595731 # ok 245 /ocp/target-module@50000000
1318 03:51:35.617840 # ok 246 /ocp/target-module@53100000
1319 03:51:35.687865 # not ok 247 /ocp/target-module@53100000/sham@0
1320 03:51:35.710100 # ok 248 /ocp/target-module@53500000
1321 03:51:35.783399 # not ok 249 /ocp/target-module@53500000/aes@0
1322 03:51:35.805233 # ok 250 /ocp/target-module@56000000
1323 03:51:35.912825 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1324 03:51:35.986811 # ok 252 /opp-table # SKIP
1325 03:51:36.054659 # ok 253 /soc # SKIP
1326 03:51:36.081190 # ok 254 /sound
1327 03:51:36.100908 # ok 255 /target-module@4b000000
1328 03:51:36.126501 # ok 256 /target-module@4b000000/target-module@140000
1329 03:51:36.148156 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1330 03:51:36.156563 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1331 03:51:36.164566 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1332 03:51:38.343919 dt_test_unprobed_devices_sh_ skip
1333 03:51:38.349480 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1334 03:51:38.354988 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1335 03:51:38.355508 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1336 03:51:38.360621 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1337 03:51:38.366044 dt_test_unprobed_devices_sh_fixedregulator0 pass
1338 03:51:38.371788 dt_test_unprobed_devices_sh_leds pass
1339 03:51:38.372246 dt_test_unprobed_devices_sh_ocp pass
1340 03:51:38.377289 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1341 03:51:38.383080 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1342 03:51:38.388481 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1343 03:51:38.399616 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1344 03:51:38.405271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1345 03:51:38.410897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1346 03:51:38.422186 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1347 03:51:38.427757 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1348 03:51:38.439061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1349 03:51:38.450272 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1350 03:51:38.461493 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1351 03:51:38.467175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1352 03:51:38.478277 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1353 03:51:38.489466 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1354 03:51:38.500695 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1355 03:51:38.511867 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1356 03:51:38.517533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1357 03:51:38.528666 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1358 03:51:38.539968 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1359 03:51:38.551124 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1360 03:51:38.562286 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1361 03:51:38.567910 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1362 03:51:38.579102 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1363 03:51:38.590222 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1364 03:51:38.601402 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1365 03:51:38.607165 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1366 03:51:38.618259 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1367 03:51:38.629417 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1368 03:51:38.640635 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1369 03:51:38.651802 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1370 03:51:38.657443 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1371 03:51:38.668621 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1372 03:51:38.679793 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1373 03:51:38.691010 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1374 03:51:38.702263 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1375 03:51:38.713412 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1376 03:51:38.724575 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1377 03:51:38.735759 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1378 03:51:38.746952 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1379 03:51:38.758134 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1380 03:51:38.769323 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1381 03:51:38.780523 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1382 03:51:38.791697 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1383 03:51:38.802883 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1384 03:51:38.814125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1385 03:51:38.825329 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1386 03:51:38.836499 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1387 03:51:38.847694 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1388 03:51:38.858883 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1389 03:51:38.870138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1390 03:51:38.881299 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1391 03:51:38.892452 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1392 03:51:38.903638 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1393 03:51:38.914851 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1394 03:51:38.926077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1395 03:51:38.937261 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1396 03:51:38.942893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1397 03:51:38.954037 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1398 03:51:38.965282 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1399 03:51:38.976449 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1400 03:51:38.987586 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1401 03:51:38.998837 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1402 03:51:39.010083 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1403 03:51:39.021310 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1404 03:51:39.032424 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1405 03:51:39.043608 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1406 03:51:39.054767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1407 03:51:39.066036 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1408 03:51:39.077151 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1409 03:51:39.088386 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1410 03:51:39.099578 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1411 03:51:39.110778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1412 03:51:39.121973 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1413 03:51:39.133207 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1414 03:51:39.138775 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1415 03:51:39.149956 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1416 03:51:39.161200 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1417 03:51:39.172328 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1418 03:51:39.183550 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1419 03:51:39.189188 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1420 03:51:39.205914 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1421 03:51:39.217101 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1422 03:51:39.222737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1423 03:51:39.239456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1424 03:51:39.250666 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1425 03:51:39.261860 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1426 03:51:39.267533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1427 03:51:39.278634 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1428 03:51:39.289884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1429 03:51:39.295463 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1430 03:51:39.306600 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1431 03:51:39.317891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1432 03:51:39.323462 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1433 03:51:39.334583 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1434 03:51:39.340254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1435 03:51:39.351391 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1436 03:51:39.362602 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1437 03:51:39.373766 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1438 03:51:39.384971 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1439 03:51:39.396202 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1440 03:51:39.407401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1441 03:51:39.418536 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1442 03:51:39.429721 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1443 03:51:39.440960 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1444 03:51:39.452198 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1445 03:51:39.463385 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1446 03:51:39.474565 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1447 03:51:39.491397 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1448 03:51:39.502543 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1449 03:51:39.513777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1450 03:51:39.524939 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1451 03:51:39.536125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1452 03:51:39.552946 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1453 03:51:39.564154 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1454 03:51:39.575402 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1455 03:51:39.586497 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1456 03:51:39.592171 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1457 03:51:39.603406 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1458 03:51:39.614490 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1459 03:51:39.620129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1460 03:51:39.631368 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1461 03:51:39.636961 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1462 03:51:39.648052 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1463 03:51:39.653716 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1464 03:51:39.664829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1465 03:51:39.670508 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1466 03:51:39.681634 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1467 03:51:39.687353 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1468 03:51:39.698440 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1469 03:51:39.709602 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1470 03:51:39.720889 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1471 03:51:39.731995 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1472 03:51:39.743187 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1473 03:51:39.748881 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1474 03:51:39.759975 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1475 03:51:39.765622 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1476 03:51:39.771228 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1477 03:51:39.776849 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1478 03:51:39.782448 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1479 03:51:39.788021 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1480 03:51:39.799160 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1481 03:51:39.804835 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1482 03:51:39.810428 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1483 03:51:39.821585 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1484 03:51:39.827253 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1485 03:51:39.838401 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1486 03:51:39.844011 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1487 03:51:39.855131 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1488 03:51:39.860793 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1489 03:51:39.871937 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1490 03:51:39.877629 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1491 03:51:39.888724 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1492 03:51:39.894474 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1493 03:51:39.905540 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1494 03:51:39.911190 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1495 03:51:39.922276 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1496 03:51:39.927977 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1497 03:51:39.933539 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1498 03:51:39.944681 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1499 03:51:39.950355 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1500 03:51:39.961488 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1501 03:51:39.967134 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1502 03:51:39.978295 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1503 03:51:39.983937 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1504 03:51:39.995055 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1505 03:51:40.000701 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1506 03:51:40.006346 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1507 03:51:40.017407 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1508 03:51:40.023106 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1509 03:51:40.034226 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1510 03:51:40.045431 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1511 03:51:40.056627 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1512 03:51:40.067837 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1513 03:51:40.079029 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1514 03:51:40.090201 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1515 03:51:40.101435 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1516 03:51:40.112602 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1517 03:51:40.118264 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1518 03:51:40.129444 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1519 03:51:40.135011 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1520 03:51:40.146198 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1521 03:51:40.151796 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1522 03:51:40.162972 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1523 03:51:40.168626 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1524 03:51:40.179777 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1525 03:51:40.185542 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1526 03:51:40.196539 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1527 03:51:40.202227 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1528 03:51:40.213311 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1529 03:51:40.218979 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1530 03:51:40.230120 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1531 03:51:40.235745 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1532 03:51:40.241349 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1533 03:51:40.252495 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1534 03:51:40.258123 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1535 03:51:40.269311 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1536 03:51:40.274968 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1537 03:51:40.286078 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1538 03:51:40.291719 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1539 03:51:40.302859 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1540 03:51:40.308523 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1541 03:51:40.314160 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1542 03:51:40.319758 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1543 03:51:40.330875 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1544 03:51:40.342073 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1545 03:51:40.347711 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1546 03:51:40.353335 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1547 03:51:40.364511 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1548 03:51:40.375606 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1549 03:51:40.386801 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1550 03:51:40.398035 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1551 03:51:40.403672 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1552 03:51:40.409285 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1553 03:51:40.414920 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1554 03:51:40.420541 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1555 03:51:40.426150 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1556 03:51:40.431734 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1557 03:51:40.442911 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1558 03:51:40.448538 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1559 03:51:40.454165 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1560 03:51:40.459748 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1561 03:51:40.465363 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1562 03:51:40.476521 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1563 03:51:40.482161 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1564 03:51:40.487764 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1565 03:51:40.493436 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1566 03:51:40.498967 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1567 03:51:40.504612 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1568 03:51:40.510217 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1569 03:51:40.515862 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1570 03:51:40.521449 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1571 03:51:40.526965 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1572 03:51:40.532607 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1573 03:51:40.538217 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1574 03:51:40.543808 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1575 03:51:40.549443 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1576 03:51:40.554970 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1577 03:51:40.560619 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1578 03:51:40.566203 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1579 03:51:40.571809 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1580 03:51:40.577436 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1581 03:51:40.582984 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1582 03:51:40.588612 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1583 03:51:40.589074 dt_test_unprobed_devices_sh_opp-table skip
1584 03:51:40.594235 dt_test_unprobed_devices_sh_soc skip
1585 03:51:40.599804 dt_test_unprobed_devices_sh_sound pass
1586 03:51:40.605419 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1587 03:51:40.611007 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1588 03:51:40.616628 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1589 03:51:40.622206 dt_test_unprobed_devices_sh fail
1590 03:51:40.622675 + ../../utils/send-to-lava.sh ./output/result.txt
1591 03:51:40.630145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1592 03:51:40.631003 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1594 03:51:40.640574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1595 03:51:40.641304 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1597 03:51:40.742346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1598 03:51:40.743119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1600 03:51:40.843706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1601 03:51:40.844478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1603 03:51:40.944618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1604 03:51:40.945400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1606 03:51:41.046903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1607 03:51:41.047789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1609 03:51:41.147054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1610 03:51:41.147722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1612 03:51:41.239083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1613 03:51:41.239768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1615 03:51:41.340660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1616 03:51:41.341308 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1618 03:51:41.444258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1619 03:51:41.444931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1621 03:51:41.546770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1622 03:51:41.547444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1624 03:51:41.706811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1625 03:51:41.707729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1627 03:51:41.809139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1628 03:51:41.810003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1630 03:51:41.905729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1631 03:51:41.906611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1633 03:51:42.004930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1634 03:51:42.005784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1636 03:51:42.107313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1637 03:51:42.108205 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1639 03:51:42.209060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1640 03:51:42.209953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1642 03:51:42.310166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1643 03:51:42.310994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1645 03:51:42.406700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1646 03:51:42.407589 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1648 03:51:42.502460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1649 03:51:42.503269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1651 03:51:42.599762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1652 03:51:42.600632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1654 03:51:42.696477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1655 03:51:42.697675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1657 03:51:42.792231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1658 03:51:42.793373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1660 03:51:42.888685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1661 03:51:42.889762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1663 03:51:42.985641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1664 03:51:42.986756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1666 03:51:43.085154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1667 03:51:43.086355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1669 03:51:43.182674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1670 03:51:43.183602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1672 03:51:43.280354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1673 03:51:43.281314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1675 03:51:43.378284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1676 03:51:43.379164 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1678 03:51:43.475661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1679 03:51:43.476526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1681 03:51:43.572983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1682 03:51:43.573881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1684 03:51:43.674858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1685 03:51:43.675853 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1687 03:51:43.770511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1688 03:51:43.771541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1690 03:51:43.866588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1691 03:51:43.867210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1693 03:51:43.964751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1694 03:51:43.965590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1696 03:51:44.062243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1697 03:51:44.063059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1699 03:51:44.151643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1700 03:51:44.152465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1702 03:51:44.248973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1703 03:51:44.249794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1705 03:51:44.346513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1706 03:51:44.347342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1708 03:51:44.442714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1709 03:51:44.443532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1711 03:51:44.538937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1712 03:51:44.539759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1714 03:51:44.635270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1715 03:51:44.636087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1717 03:51:44.732281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1718 03:51:44.733103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1720 03:51:44.828531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1721 03:51:44.829369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1723 03:51:44.924260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1724 03:51:44.925065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1726 03:51:45.021025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1727 03:51:45.021870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1729 03:51:45.117371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1730 03:51:45.118327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1732 03:51:45.213106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1733 03:51:45.214040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1735 03:51:45.309589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1736 03:51:45.310536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1738 03:51:45.406587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1739 03:51:45.407678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1741 03:51:45.502975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1742 03:51:45.503880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1744 03:51:45.598509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1745 03:51:45.599416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1747 03:51:45.695803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1748 03:51:45.696708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1750 03:51:45.795167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1751 03:51:45.796267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1753 03:51:45.892573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1754 03:51:45.893419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1756 03:51:45.988403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1757 03:51:45.989497 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1759 03:51:46.084398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1760 03:51:46.085331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1762 03:51:46.181556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1763 03:51:46.182502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1765 03:51:46.276300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1766 03:51:46.277206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1768 03:51:46.371964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1769 03:51:46.372866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1771 03:51:46.467784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1772 03:51:46.468659 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1774 03:51:46.564848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1775 03:51:46.565764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1777 03:51:46.661324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1778 03:51:46.662279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1780 03:51:46.757328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1781 03:51:46.758272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1783 03:51:46.853666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1784 03:51:46.854554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1786 03:51:46.951145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1787 03:51:46.951987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1789 03:51:47.050850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1790 03:51:47.051702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1792 03:51:47.150480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1793 03:51:47.151091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1795 03:51:47.246540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1796 03:51:47.247454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1798 03:51:47.345805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1799 03:51:47.346673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1801 03:51:47.445125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1802 03:51:47.446016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1804 03:51:47.540441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1805 03:51:47.541317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1807 03:51:47.639037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1808 03:51:47.639883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1810 03:51:47.737019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1811 03:51:47.737758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1813 03:51:47.834572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1814 03:51:47.835287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1816 03:51:47.929999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1817 03:51:47.930714 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1819 03:51:48.027479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1820 03:51:48.028202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1822 03:51:48.123193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1823 03:51:48.123953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1825 03:51:48.224494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1826 03:51:48.225251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1828 03:51:48.324074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1829 03:51:48.324813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1831 03:51:48.419656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1832 03:51:48.420923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1834 03:51:48.516108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1835 03:51:48.516972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1837 03:51:48.613702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1838 03:51:48.614580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1840 03:51:48.708763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1841 03:51:48.709618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1843 03:51:48.805746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1844 03:51:48.806627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1846 03:51:48.902316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1847 03:51:48.903256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1849 03:51:48.999396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1850 03:51:49.000304 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1852 03:51:49.095810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1853 03:51:49.096688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1855 03:51:49.192074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1856 03:51:49.192890 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1858 03:51:49.290899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1859 03:51:49.291756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1861 03:51:49.385588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1862 03:51:49.386493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1864 03:51:49.480090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1865 03:51:49.480920 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1867 03:51:49.578158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1868 03:51:49.579000 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1870 03:51:49.675143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1871 03:51:49.675990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1873 03:51:49.771877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1874 03:51:49.772740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1876 03:51:49.865629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1877 03:51:49.866498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1879 03:51:49.961784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1880 03:51:49.962648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1882 03:51:50.058626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1883 03:51:50.059421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1885 03:51:50.155484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1886 03:51:50.156318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1888 03:51:50.252300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1889 03:51:50.253301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1891 03:51:50.348106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1892 03:51:50.348972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1894 03:51:50.444427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1895 03:51:50.445283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1897 03:51:50.539231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1898 03:51:50.540095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1900 03:51:50.635547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1901 03:51:50.636414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1903 03:51:50.734079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1904 03:51:50.734955 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1906 03:51:50.830567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1907 03:51:50.831443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1909 03:51:50.931336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1910 03:51:50.932193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1912 03:51:51.027811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1913 03:51:51.028668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1915 03:51:51.128238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1916 03:51:51.129086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1918 03:51:51.229170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1919 03:51:51.230009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1921 03:51:51.327994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1922 03:51:51.329123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1924 03:51:51.424814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1925 03:51:51.425921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1927 03:51:51.522107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1928 03:51:51.523179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1930 03:51:51.617458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1931 03:51:51.618382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1933 03:51:51.714276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1934 03:51:51.715067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1936 03:51:51.812086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1937 03:51:51.812890 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1939 03:51:51.909241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1940 03:51:51.910309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1942 03:51:52.005676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1943 03:51:52.006787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1945 03:51:52.103575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1946 03:51:52.104601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1948 03:51:52.198690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1949 03:51:52.199759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1951 03:51:52.294306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1953 03:51:52.297385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1954 03:51:52.395396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1956 03:51:52.398596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1957 03:51:52.493537 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1959 03:51:52.496757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1960 03:51:52.591237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1961 03:51:52.592041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1963 03:51:52.686992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1964 03:51:52.687786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1966 03:51:52.782136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1967 03:51:52.782943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1969 03:51:52.879946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1970 03:51:52.880741 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1972 03:51:52.976941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1973 03:51:52.977737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1975 03:51:53.076099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1976 03:51:53.076919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1978 03:51:53.172346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1979 03:51:53.173179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1981 03:51:53.269159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1982 03:51:53.270127 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1984 03:51:53.366368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1985 03:51:53.367272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1987 03:51:53.463211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1988 03:51:53.464113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1990 03:51:53.559698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1991 03:51:53.560536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1993 03:51:53.656377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1994 03:51:53.657253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1996 03:51:53.753220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1997 03:51:53.754178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1999 03:51:53.850048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2000 03:51:53.850883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2002 03:51:53.948986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2003 03:51:53.949878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2005 03:51:54.046691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2006 03:51:54.047654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2008 03:51:54.144079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2009 03:51:54.144724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2011 03:51:54.243572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2012 03:51:54.244239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2014 03:51:54.340889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2015 03:51:54.341535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2017 03:51:54.435723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2018 03:51:54.436367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2020 03:51:54.529452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2021 03:51:54.530112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2023 03:51:54.616702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2024 03:51:54.617346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2026 03:51:54.712938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2027 03:51:54.713568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2029 03:51:54.808097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2030 03:51:54.808736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2032 03:51:54.908537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2033 03:51:54.909162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2035 03:51:55.006410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2036 03:51:55.007031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2038 03:51:55.102374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2039 03:51:55.103011 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2041 03:51:55.197663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2042 03:51:55.198321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2044 03:51:55.293292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2045 03:51:55.293929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2047 03:51:55.388802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2048 03:51:55.389432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2050 03:51:55.485687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2051 03:51:55.486348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2053 03:51:55.582415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2054 03:51:55.583063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2056 03:51:55.679599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2057 03:51:55.680231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2059 03:51:55.781524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2060 03:51:55.782188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2062 03:51:55.881611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2063 03:51:55.882244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2065 03:51:55.982259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2066 03:51:55.982891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2068 03:51:56.083638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2069 03:51:56.084270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2071 03:51:56.185538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2072 03:51:56.186193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2074 03:51:56.280951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2075 03:51:56.281576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2077 03:51:56.382984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2078 03:51:56.383621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2080 03:51:56.483327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2081 03:51:56.484005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2083 03:51:56.582514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2084 03:51:56.583178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2086 03:51:56.677449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2087 03:51:56.678126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2089 03:51:56.779702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2090 03:51:56.780358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2092 03:51:56.880043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2093 03:51:56.880701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2095 03:51:56.981456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2096 03:51:56.982142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2098 03:51:57.083152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2099 03:51:57.083789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2101 03:51:57.184718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2102 03:51:57.185360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2104 03:51:57.285292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2105 03:51:57.285936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2107 03:51:57.388074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2108 03:51:57.388710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2110 03:51:57.487399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2111 03:51:57.488064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2113 03:51:57.589273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2114 03:51:57.589949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2116 03:51:57.687988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2117 03:51:57.688667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2119 03:51:57.791012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2120 03:51:57.791679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2122 03:51:57.892806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2123 03:51:57.893478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2125 03:51:57.995768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2126 03:51:57.996436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2128 03:51:58.097148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2129 03:51:58.097843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2131 03:51:58.200135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2132 03:51:58.200796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2134 03:51:58.299188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2135 03:51:58.299844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2137 03:51:58.399511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2138 03:51:58.400172 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2140 03:51:58.502950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2141 03:51:58.503722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2143 03:51:58.603239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2144 03:51:58.603885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2146 03:51:58.705387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2147 03:51:58.706038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2149 03:51:58.803456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2150 03:51:58.804136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2152 03:51:58.902133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2153 03:51:58.902795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2155 03:51:59.003445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2156 03:51:59.004097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2158 03:51:59.099514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2159 03:51:59.100183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2161 03:51:59.194646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2162 03:51:59.195309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2164 03:51:59.298066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2165 03:51:59.298716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2167 03:51:59.397447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2168 03:51:59.398142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2170 03:51:59.499342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2171 03:51:59.500024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2173 03:51:59.600769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2174 03:51:59.601446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2176 03:51:59.700793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2177 03:51:59.701709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2179 03:51:59.803034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2180 03:51:59.803932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2182 03:51:59.904392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2183 03:51:59.905312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2185 03:52:00.003430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2186 03:52:00.004551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2188 03:52:00.106078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2189 03:52:00.106908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2191 03:52:00.207244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2192 03:52:00.208101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2194 03:52:00.561503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2195 03:52:00.562232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2196 03:52:00.563063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2198 03:52:00.564916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2200 03:52:00.566742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2201 03:52:00.567595 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2203 03:52:00.609141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2204 03:52:00.610189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2206 03:52:00.706757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2207 03:52:00.707590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2209 03:52:00.807760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2210 03:52:00.808460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2212 03:52:00.909418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2213 03:52:00.910149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2215 03:52:01.011468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2216 03:52:01.012151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2218 03:52:01.108809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2219 03:52:01.109471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2221 03:52:01.210141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2222 03:52:01.210822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2224 03:52:01.313030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2225 03:52:01.313712 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2227 03:52:01.445093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2228 03:52:01.445786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2230 03:52:01.547440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2231 03:52:01.548427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2233 03:52:01.646274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2234 03:52:01.646947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2236 03:52:01.748707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2237 03:52:01.749382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2239 03:52:01.851317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2240 03:52:01.851999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2242 03:52:01.954648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2243 03:52:01.955318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2245 03:52:02.054729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2246 03:52:02.055406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2248 03:52:02.155646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2249 03:52:02.156303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2251 03:52:02.257372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2252 03:52:02.258077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2254 03:52:02.354325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2255 03:52:02.355155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2257 03:52:02.456581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2258 03:52:02.457415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2260 03:52:02.556128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2261 03:52:02.557069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2263 03:52:02.657757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2264 03:52:02.658679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2266 03:52:02.759387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2267 03:52:02.760202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2269 03:52:02.862888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2270 03:52:02.863744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2272 03:52:02.960989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2274 03:52:02.963927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2275 03:52:03.063122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2276 03:52:03.063923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2278 03:52:03.166359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2279 03:52:03.167267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2281 03:52:03.267030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2282 03:52:03.267946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2284 03:52:03.368292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2285 03:52:03.369228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2287 03:52:03.469210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2288 03:52:03.470189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2290 03:52:03.570209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2291 03:52:03.571138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2293 03:52:03.670851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2294 03:52:03.671752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2296 03:52:03.772122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2297 03:52:03.772973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2299 03:52:03.874289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2300 03:52:03.875185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2302 03:52:03.976547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2303 03:52:03.977426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2305 03:52:04.079777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2306 03:52:04.080644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2308 03:52:04.180202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2309 03:52:04.181093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2311 03:52:04.281722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2312 03:52:04.282635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2314 03:52:04.383095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2315 03:52:04.383983 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2317 03:52:04.484176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2318 03:52:04.485055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2320 03:52:04.586189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2321 03:52:04.587091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2323 03:52:04.687362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2324 03:52:04.688265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2326 03:52:04.787703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2327 03:52:04.788522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2329 03:52:04.888723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2330 03:52:04.889619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2332 03:52:04.990913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2333 03:52:04.991809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2335 03:52:05.091736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2336 03:52:05.092694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2338 03:52:05.194917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2339 03:52:05.195849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2341 03:52:05.295233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2342 03:52:05.296165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2344 03:52:05.397482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2345 03:52:05.398447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2347 03:52:05.495671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2348 03:52:05.496361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2350 03:52:05.588601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2351 03:52:05.589527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2353 03:52:05.683008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2354 03:52:05.683923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2356 03:52:05.786278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2357 03:52:05.787149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2359 03:52:05.889158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2360 03:52:05.890124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2362 03:52:05.990896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2363 03:52:05.991752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2365 03:52:06.089284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2366 03:52:06.090009 + set +x
2367 03:52:06.090807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2369 03:52:06.094021 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 932598_1.6.2.4.5>
2370 03:52:06.094811 Received signal: <ENDRUN> 1_kselftest-dt 932598_1.6.2.4.5
2371 03:52:06.095319 Ending use of test pattern.
2372 03:52:06.095771 Ending test lava.1_kselftest-dt (932598_1.6.2.4.5), duration 86.69
2374 03:52:06.103521 <LAVA_TEST_RUNNER EXIT>
2375 03:52:06.104314 ok: lava_test_shell seems to have completed
2376 03:52:06.118709 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2377 03:52:06.120808 end: 3.1 lava-test-shell (duration 00:01:28) [common]
2378 03:52:06.121467 end: 3 lava-test-retry (duration 00:01:28) [common]
2379 03:52:06.122118 start: 4 finalize (timeout 00:05:27) [common]
2380 03:52:06.122773 start: 4.1 power-off (timeout 00:00:30) [common]
2381 03:52:06.123613 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-03'
2382 03:52:06.155579 >> OK - accepted request
2383 03:52:06.157485 Returned 0 in 0 seconds
2384 03:52:06.258660 end: 4.1 power-off (duration 00:00:00) [common]
2386 03:52:06.259719 start: 4.2 read-feedback (timeout 00:05:27) [common]
2387 03:52:06.260475 Listened to connection for namespace 'common' for up to 1s
2388 03:52:06.261131 Listened to connection for namespace 'common' for up to 1s
2389 03:52:07.261366 Finalising connection for namespace 'common'
2390 03:52:07.262084 Disconnecting from shell: Finalise
2391 03:52:07.262415 / #
2392 03:52:07.363139 end: 4.2 read-feedback (duration 00:00:01) [common]
2393 03:52:07.363670 end: 4 finalize (duration 00:00:01) [common]
2394 03:52:07.364037 Cleaning after the job
2395 03:52:07.364411 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932598/tftp-deploy-x_5s5lmz/ramdisk
2396 03:52:07.369398 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932598/tftp-deploy-x_5s5lmz/kernel
2397 03:52:07.373658 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932598/tftp-deploy-x_5s5lmz/dtb
2398 03:52:07.374576 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932598/tftp-deploy-x_5s5lmz/nfsrootfs
2399 03:52:07.526326 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932598/tftp-deploy-x_5s5lmz/modules
2400 03:52:07.538950 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/932598
2401 03:52:10.519252 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/932598
2402 03:52:10.519816 Job finished correctly