Boot log: beaglebone-black

    1 03:53:29.973670  lava-dispatcher, installed at version: 2023.08
    2 03:53:29.974049  start: 0 validate
    3 03:53:29.974278  Start time: 2024-11-04 03:53:29.974264+00:00 (UTC)
    4 03:53:29.974552  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
    5 03:53:30.320756  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc6/arm/multi_v7_defconfig/clang-15/kernel/zImage exists
    6 03:53:30.483104  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc6/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb exists
    7 03:53:30.646377  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
    8 03:53:30.809324  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc6/arm/multi_v7_defconfig/clang-15/modules.tar.xz exists
    9 03:53:30.979903  validate duration: 1.01
   11 03:53:30.981058  start: 1 tftp-deploy (timeout 00:10:00) [common]
   12 03:53:30.981556  start: 1.1 download-retry (timeout 00:10:00) [common]
   13 03:53:30.982004  start: 1.1.1 http-download (timeout 00:10:00) [common]
   14 03:53:30.982790  Not decompressing ramdisk as can be used compressed.
   15 03:53:30.983233  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
   16 03:53:30.983580  saving as /var/lib/lava/dispatcher/tmp/1216052/tftp-deploy-yd1p0v46/ramdisk/initrd.cpio.gz
   17 03:53:30.983930  total size: 4775763 (4 MB)
   18 03:53:31.308556  progress   0 % (0 MB)
   19 03:53:31.790544  progress   5 % (0 MB)
   20 03:53:32.151772  progress  10 % (0 MB)
   21 03:53:32.157925  progress  15 % (0 MB)
   22 03:53:32.164811  progress  20 % (0 MB)
   23 03:53:32.276492  progress  25 % (1 MB)
   24 03:53:32.426923  progress  30 % (1 MB)
   25 03:53:32.484648  progress  35 % (1 MB)
   26 03:53:32.636910  progress  40 % (1 MB)
   27 03:53:32.756552  progress  45 % (2 MB)
   28 03:53:32.808233  progress  50 % (2 MB)
   29 03:53:32.962377  progress  55 % (2 MB)
   30 03:53:33.113618  progress  60 % (2 MB)
   31 03:53:33.226500  progress  65 % (2 MB)
   32 03:53:33.286646  progress  70 % (3 MB)
   33 03:53:33.435252  progress  75 % (3 MB)
   34 03:53:33.547208  progress  80 % (3 MB)
   35 03:53:33.605265  progress  85 % (3 MB)
   36 03:53:33.752457  progress  90 % (4 MB)
   37 03:53:33.776463  progress  95 % (4 MB)
   38 03:53:33.922797  progress 100 % (4 MB)
   39 03:53:33.923846  4 MB downloaded in 2.94 s (1.55 MB/s)
   40 03:53:33.924532  end: 1.1.1 http-download (duration 00:00:03) [common]
   42 03:53:33.925749  end: 1.1 download-retry (duration 00:00:03) [common]
   43 03:53:33.926164  start: 1.2 download-retry (timeout 00:09:57) [common]
   44 03:53:33.926567  start: 1.2.1 http-download (timeout 00:09:57) [common]
   45 03:53:33.927154  downloading http://storage.kernelci.org/mainline/master/v6.12-rc6/arm/multi_v7_defconfig/clang-15/kernel/zImage
   46 03:53:33.927476  saving as /var/lib/lava/dispatcher/tmp/1216052/tftp-deploy-yd1p0v46/kernel/zImage
   47 03:53:33.927778  total size: 12050944 (11 MB)
   48 03:53:33.928082  No compression specified
   49 03:53:34.093089  progress   0 % (0 MB)
   50 03:53:34.287737  progress   5 % (0 MB)
   51 03:53:34.601005  progress  10 % (1 MB)
   52 03:53:35.054062  progress  15 % (1 MB)
   53 03:53:35.374058  progress  20 % (2 MB)
   54 03:53:35.689759  progress  25 % (2 MB)
   55 03:53:36.010501  progress  30 % (3 MB)
   56 03:53:36.204726  progress  35 % (4 MB)
   57 03:53:36.524761  progress  40 % (4 MB)
   58 03:53:36.841602  progress  45 % (5 MB)
   59 03:53:37.155612  progress  50 % (5 MB)
   60 03:53:37.472740  progress  55 % (6 MB)
   61 03:53:37.783850  progress  60 % (6 MB)
   62 03:53:38.100245  progress  65 % (7 MB)
   63 03:53:38.295234  progress  70 % (8 MB)
   64 03:53:38.606991  progress  75 % (8 MB)
   65 03:53:38.923162  progress  80 % (9 MB)
   66 03:53:39.233310  progress  85 % (9 MB)
   67 03:53:39.547912  progress  90 % (10 MB)
   68 03:53:39.862008  progress  95 % (10 MB)
   69 03:53:40.057595  progress 100 % (11 MB)
   70 03:53:40.058801  11 MB downloaded in 6.13 s (1.87 MB/s)
   71 03:53:40.059551  end: 1.2.1 http-download (duration 00:00:06) [common]
   73 03:53:40.060770  end: 1.2 download-retry (duration 00:00:06) [common]
   74 03:53:40.061027  start: 1.3 download-retry (timeout 00:09:51) [common]
   75 03:53:40.061419  start: 1.3.1 http-download (timeout 00:09:51) [common]
   76 03:53:40.113095  downloading http://storage.kernelci.org/mainline/master/v6.12-rc6/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
   77 03:53:40.113484  saving as /var/lib/lava/dispatcher/tmp/1216052/tftp-deploy-yd1p0v46/dtb/am335x-boneblack.dtb
   78 03:53:40.113800  total size: 70568 (0 MB)
   79 03:53:40.114110  No compression specified
   80 03:53:40.288028  progress  46 % (0 MB)
   81 03:53:40.290871  progress  92 % (0 MB)
   82 03:53:40.292115  progress 100 % (0 MB)
   83 03:53:40.292657  0 MB downloaded in 0.18 s (0.38 MB/s)
   84 03:53:40.293252  end: 1.3.1 http-download (duration 00:00:00) [common]
   86 03:53:40.294338  end: 1.3 download-retry (duration 00:00:00) [common]
   87 03:53:40.294731  start: 1.4 download-retry (timeout 00:09:51) [common]
   88 03:53:40.295169  start: 1.4.1 http-download (timeout 00:09:51) [common]
   89 03:53:40.295707  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
   90 03:53:40.296057  saving as /var/lib/lava/dispatcher/tmp/1216052/tftp-deploy-yd1p0v46/nfsrootfs/full.rootfs.tar
   91 03:53:40.296353  total size: 117747780 (112 MB)
   92 03:53:40.296659  Using unxz to decompress xz
   93 03:53:40.462661  progress   0 % (0 MB)
   94 03:53:43.692173  progress   5 % (5 MB)
   95 03:53:46.610217  progress  10 % (11 MB)
   96 03:53:49.476078  progress  15 % (16 MB)
   97 03:53:51.931393  progress  20 % (22 MB)
   98 03:53:53.848692  progress  25 % (28 MB)
   99 03:53:55.312528  progress  30 % (33 MB)
  100 03:53:56.866695  progress  35 % (39 MB)
  101 03:53:58.264235  progress  40 % (44 MB)
  102 03:53:59.565238  progress  45 % (50 MB)
  103 03:54:00.986937  progress  50 % (56 MB)
  104 03:54:02.602121  progress  55 % (61 MB)
  105 03:54:04.156338  progress  60 % (67 MB)
  106 03:54:05.666088  progress  65 % (73 MB)
  107 03:54:07.524993  progress  70 % (78 MB)
  108 03:54:09.088979  progress  75 % (84 MB)
  109 03:54:10.644276  progress  80 % (89 MB)
  110 03:54:12.490940  progress  85 % (95 MB)
  111 03:54:14.328474  progress  90 % (101 MB)
  112 03:54:16.295445  progress  95 % (106 MB)
  113 03:54:18.254111  progress 100 % (112 MB)
  114 03:54:18.267486  112 MB downloaded in 37.97 s (2.96 MB/s)
  115 03:54:18.268124  end: 1.4.1 http-download (duration 00:00:38) [common]
  117 03:54:18.269205  end: 1.4 download-retry (duration 00:00:38) [common]
  118 03:54:18.269610  start: 1.5 download-retry (timeout 00:09:13) [common]
  119 03:54:18.270013  start: 1.5.1 http-download (timeout 00:09:13) [common]
  120 03:54:18.270640  downloading http://storage.kernelci.org/mainline/master/v6.12-rc6/arm/multi_v7_defconfig/clang-15/modules.tar.xz
  121 03:54:18.270961  saving as /var/lib/lava/dispatcher/tmp/1216052/tftp-deploy-yd1p0v46/modules/modules.tar
  122 03:54:18.271262  total size: 6912572 (6 MB)
  123 03:54:18.271568  Using unxz to decompress xz
  124 03:54:18.437504  progress   0 % (0 MB)
  125 03:54:18.624330  progress   5 % (0 MB)
  126 03:54:18.772373  progress  10 % (0 MB)
  127 03:54:18.815049  progress  15 % (1 MB)
  128 03:54:18.937732  progress  20 % (1 MB)
  129 03:54:19.094623  progress  25 % (1 MB)
  130 03:54:19.253633  progress  30 % (2 MB)
  131 03:54:19.408581  progress  35 % (2 MB)
  132 03:54:19.565444  progress  40 % (2 MB)
  133 03:54:19.610181  progress  45 % (2 MB)
  134 03:54:19.767377  progress  50 % (3 MB)
  135 03:54:19.923120  progress  55 % (3 MB)
  136 03:54:20.070677  progress  60 % (3 MB)
  137 03:54:20.260905  progress  65 % (4 MB)
  138 03:54:20.404602  progress  70 % (4 MB)
  139 03:54:20.598255  progress  75 % (4 MB)
  140 03:54:20.727288  progress  80 % (5 MB)
  141 03:54:20.894175  progress  85 % (5 MB)
  142 03:54:21.059918  progress  90 % (5 MB)
  143 03:54:21.235300  progress  95 % (6 MB)
  144 03:54:21.399301  progress 100 % (6 MB)
  145 03:54:21.413440  6 MB downloaded in 3.14 s (2.10 MB/s)
  146 03:54:21.414090  end: 1.5.1 http-download (duration 00:00:03) [common]
  148 03:54:21.415196  end: 1.5 download-retry (duration 00:00:03) [common]
  149 03:54:21.415599  start: 1.6 prepare-tftp-overlay (timeout 00:09:10) [common]
  150 03:54:21.416001  start: 1.6.1 extract-nfsrootfs (timeout 00:09:10) [common]
  151 03:54:28.897823  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1216052/extract-nfsrootfs-t70l5rdy
  152 03:54:28.898135  end: 1.6.1 extract-nfsrootfs (duration 00:00:07) [common]
  153 03:54:28.898286  start: 1.6.2 lava-overlay (timeout 00:09:02) [common]
  154 03:54:28.898581  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8
  155 03:54:28.898824  makedir: /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin
  156 03:54:28.898997  makedir: /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/tests
  157 03:54:28.899166  makedir: /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/results
  158 03:54:28.899327  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-add-keys
  159 03:54:28.899574  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-add-sources
  160 03:54:28.899800  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-background-process-start
  161 03:54:28.900027  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-background-process-stop
  162 03:54:28.900266  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-common-functions
  163 03:54:28.900492  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-echo-ipv4
  164 03:54:28.900713  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-install-packages
  165 03:54:28.900967  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-installed-packages
  166 03:54:28.901199  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-os-build
  167 03:54:28.901415  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-probe-channel
  168 03:54:28.901629  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-probe-ip
  169 03:54:28.901846  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-target-ip
  170 03:54:28.902063  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-target-mac
  171 03:54:28.902279  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-target-storage
  172 03:54:28.902503  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-test-case
  173 03:54:28.902721  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-test-event
  174 03:54:28.902934  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-test-feedback
  175 03:54:28.903147  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-test-raise
  176 03:54:28.903368  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-test-reference
  177 03:54:28.903582  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-test-runner
  178 03:54:28.903799  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-test-set
  179 03:54:28.904015  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-test-shell
  180 03:54:28.904233  Updating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-add-keys (debian)
  181 03:54:28.937280  Updating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-add-sources (debian)
  182 03:54:28.937581  Updating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-install-packages (debian)
  183 03:54:28.937857  Updating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-installed-packages (debian)
  184 03:54:28.938141  Updating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/bin/lava-os-build (debian)
  185 03:54:28.938362  Creating /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/environment
  186 03:54:28.938531  LAVA metadata
  187 03:54:28.938649  - LAVA_JOB_ID=1216052
  188 03:54:28.938761  - LAVA_DISPATCHER_IP=172.16.3.3
  189 03:54:28.938933  start: 1.6.2.1 ssh-authorize (timeout 00:09:02) [common]
  190 03:54:28.939381  end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
  191 03:54:28.939535  start: 1.6.2.2 lava-vland-overlay (timeout 00:09:02) [common]
  192 03:54:28.939643  skipped lava-vland-overlay
  193 03:54:28.939772  end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
  194 03:54:28.939908  start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:02) [common]
  195 03:54:28.940019  skipped lava-multinode-overlay
  196 03:54:28.940147  end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
  197 03:54:28.940279  start: 1.6.2.4 test-definition (timeout 00:09:02) [common]
  198 03:54:28.940395  Loading test definitions
  199 03:54:28.940536  start: 1.6.2.4.1 inline-repo-action (timeout 00:09:02) [common]
  200 03:54:28.940650  Using /lava-1216052 at stage 0
  201 03:54:28.941262  uuid=1216052_1.6.2.4.1 testdef=None
  202 03:54:28.941416  end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
  203 03:54:28.941551  start: 1.6.2.4.2 test-overlay (timeout 00:09:02) [common]
  204 03:54:28.942339  end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
  206 03:54:28.942735  start: 1.6.2.4.3 test-install-overlay (timeout 00:09:02) [common]
  207 03:54:28.943718  end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
  209 03:54:28.944107  start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:02) [common]
  210 03:54:28.960317  runner path: /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/0/tests/0_timesync-off test_uuid 1216052_1.6.2.4.1
  211 03:54:28.960604  end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
  213 03:54:28.961026  start: 1.6.2.4.5 git-repo-action (timeout 00:09:02) [common]
  214 03:54:28.961175  Using /lava-1216052 at stage 0
  215 03:54:28.961343  Fetching tests from https://github.com/kernelci/test-definitions.git
  216 03:54:28.961463  Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/0/tests/1_kselftest-dt'
  217 03:54:34.420885  Running '/usr/bin/git checkout kernelci.org
  218 03:54:34.709899  Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
  219 03:54:34.711673  uuid=1216052_1.6.2.4.5 testdef=None
  220 03:54:34.712148  end: 1.6.2.4.5 git-repo-action (duration 00:00:06) [common]
  222 03:54:34.713013  start: 1.6.2.4.6 test-overlay (timeout 00:08:56) [common]
  223 03:54:34.716567  end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
  225 03:54:34.717382  start: 1.6.2.4.7 test-install-overlay (timeout 00:08:56) [common]
  226 03:54:34.722011  end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
  228 03:54:34.723162  start: 1.6.2.4.8 test-runscript-overlay (timeout 00:08:56) [common]
  229 03:54:34.727645  runner path: /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/0/tests/1_kselftest-dt test_uuid 1216052_1.6.2.4.5
  230 03:54:34.728034  BOARD='beaglebone-black'
  231 03:54:34.728349  BRANCH='mainline'
  232 03:54:34.728651  SKIPFILE='/dev/null'
  233 03:54:34.728895  SKIP_INSTALL='True'
  234 03:54:34.729014  TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
  235 03:54:34.729302  TST_CASENAME=''
  236 03:54:34.729592  TST_CMDFILES='dt'
  237 03:54:34.730297  end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
  239 03:54:34.731306  Creating lava-test-runner.conf files
  240 03:54:34.731606  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1216052/lava-overlay-dorua4r8/lava-1216052/0 for stage 0
  241 03:54:34.732056  - 0_timesync-off
  242 03:54:34.732374  - 1_kselftest-dt
  243 03:54:34.732856  end: 1.6.2.4 test-definition (duration 00:00:06) [common]
  244 03:54:34.733018  start: 1.6.2.5 compress-overlay (timeout 00:08:56) [common]
  245 03:54:44.274433  end: 1.6.2.5 compress-overlay (duration 00:00:10) [common]
  246 03:54:44.274676  start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:47) [common]
  247 03:54:44.274822  end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
  248 03:54:44.274969  end: 1.6.2 lava-overlay (duration 00:00:15) [common]
  249 03:54:44.275115  start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:47) [common]
  250 03:54:44.413832  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  251 03:54:44.414091  start: 1.6.4 extract-modules (timeout 00:08:47) [common]
  252 03:54:44.414220  extracting modules file /var/lib/lava/dispatcher/tmp/1216052/tftp-deploy-yd1p0v46/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1216052/extract-nfsrootfs-t70l5rdy
  253 03:54:44.808717  extracting modules file /var/lib/lava/dispatcher/tmp/1216052/tftp-deploy-yd1p0v46/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1216052/extract-overlay-ramdisk-vp2_p9kt/ramdisk
  254 03:54:45.199001  end: 1.6.4 extract-modules (duration 00:00:01) [common]
  255 03:54:45.199270  start: 1.6.5 apply-overlay-tftp (timeout 00:08:46) [common]
  256 03:54:45.199400  [common] Applying overlay to NFS
  257 03:54:45.199509  [common] Applying overlay /var/lib/lava/dispatcher/tmp/1216052/compress-overlay-tuxgr3q8/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1216052/extract-nfsrootfs-t70l5rdy
  258 03:54:46.512660  end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
  259 03:54:46.512930  start: 1.6.6 prepare-kernel (timeout 00:08:44) [common]
  260 03:54:46.513077  start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:44) [common]
  261 03:54:46.513227  end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
  262 03:54:46.513362  end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
  263 03:54:46.513499  start: 1.6.7 configure-preseed-file (timeout 00:08:44) [common]
  264 03:54:46.513630  end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
  265 03:54:46.513765  start: 1.6.8 compress-ramdisk (timeout 00:08:44) [common]
  266 03:54:46.513878  Building ramdisk /var/lib/lava/dispatcher/tmp/1216052/extract-overlay-ramdisk-vp2_p9kt/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1216052/extract-overlay-ramdisk-vp2_p9kt/ramdisk
  267 03:54:46.813869  >> 79012 blocks

  268 03:54:49.101495  Adding RAMdisk u-boot header.
  269 03:54:49.101923  mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1216052/extract-overlay-ramdisk-vp2_p9kt/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1216052/extract-overlay-ramdisk-vp2_p9kt/ramdisk.cpio.gz.uboot
  270 03:54:49.403860  output: Image Name:   
  271 03:54:49.404212  output: Created:      Mon Nov  4 03:54:49 2024
  272 03:54:49.404535  output: Image Type:   ARM Linux RAMDisk Image (uncompressed)
  273 03:54:49.404853  output: Data Size:    15357695 Bytes = 14997.75 KiB = 14.65 MiB
  274 03:54:49.404980  output: Load Address: 00000000
  275 03:54:49.405134  output: Entry Point:  00000000
  276 03:54:49.405427  output: 
  277 03:54:49.405907  rename /var/lib/lava/dispatcher/tmp/1216052/extract-overlay-ramdisk-vp2_p9kt/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1216052/tftp-deploy-yd1p0v46/ramdisk/ramdisk.cpio.gz.uboot
  278 03:54:49.406407  end: 1.6.8 compress-ramdisk (duration 00:00:03) [common]
  279 03:54:49.406820  end: 1.6 prepare-tftp-overlay (duration 00:00:28) [common]
  280 03:54:49.407223  start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
  281 03:54:49.407537  No LXC device requested
  282 03:54:49.407911  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  283 03:54:49.408305  start: 1.8 deploy-device-env (timeout 00:08:42) [common]
  284 03:54:49.408679  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  285 03:54:49.408922  Checking files for TFTP limit of 4294967296 bytes.
  286 03:54:49.410679  end: 1 tftp-deploy (duration 00:01:18) [common]
  287 03:54:49.411092  start: 2 uboot-action (timeout 00:05:00) [common]
  288 03:54:49.411498  start: 2.1 uboot-from-media (timeout 00:05:00) [common]
  289 03:54:49.411882  end: 2.1 uboot-from-media (duration 00:00:00) [common]
  290 03:54:49.412273  start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
  291 03:54:49.412858  substitutions:
  292 03:54:49.412991  - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
  293 03:54:49.413252  - {DTB_ADDR}: 0x88000000
  294 03:54:49.413547  - {DTB}: 1216052/tftp-deploy-yd1p0v46/dtb/am335x-boneblack.dtb
  295 03:54:49.413840  - {INITRD}: 1216052/tftp-deploy-yd1p0v46/ramdisk/ramdisk.cpio.gz.uboot
  296 03:54:49.414130  - {KERNEL_ADDR}: 0x82000000
  297 03:54:49.414420  - {KERNEL}: 1216052/tftp-deploy-yd1p0v46/kernel/zImage
  298 03:54:49.414707  - {LAVA_MAC}: None
  299 03:54:49.415011  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1216052/extract-nfsrootfs-t70l5rdy
  300 03:54:49.415301  - {NFS_SERVER_IP}: 172.16.3.3
  301 03:54:49.415584  - {PRESEED_CONFIG}: None
  302 03:54:49.415866  - {PRESEED_LOCAL}: None
  303 03:54:49.416146  - {RAMDISK_ADDR}: 0x83000000
  304 03:54:49.416426  - {RAMDISK}: 1216052/tftp-deploy-yd1p0v46/ramdisk/ramdisk.cpio.gz.uboot
  305 03:54:49.416708  - {ROOT_PART}: None
  306 03:54:49.416909  - {ROOT}: None
  307 03:54:49.417025  - {SERVER_IP}: 172.16.3.3
  308 03:54:49.417284  - {TEE_ADDR}: 0x83000000
  309 03:54:49.417563  - {TEE}: None
  310 03:54:49.417842  Parsed boot commands:
  311 03:54:49.418112  - setenv autoload no
  312 03:54:49.418390  - setenv initrd_high 0xffffffff
  313 03:54:49.418668  - setenv fdt_high 0xffffffff
  314 03:54:49.418944  - dhcp
  315 03:54:49.419218  - setenv serverip 172.16.3.3
  316 03:54:49.419494  - tftp 0x82000000 1216052/tftp-deploy-yd1p0v46/kernel/zImage
  317 03:54:49.419771  - tftp 0x83000000 1216052/tftp-deploy-yd1p0v46/ramdisk/ramdisk.cpio.gz.uboot
  318 03:54:49.420051  - setenv initrd_size ${filesize}
  319 03:54:49.420327  - tftp 0x88000000 1216052/tftp-deploy-yd1p0v46/dtb/am335x-boneblack.dtb
  320 03:54:49.420604  - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1216052/extract-nfsrootfs-t70l5rdy,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  321 03:54:49.420880  - bootz 0x82000000 0x83000000 0x88000000
  322 03:54:49.421045  end: 2.2 bootloader-overlay (duration 00:00:00) [common]
  324 03:54:49.422076  start: 2.3 connect-device (timeout 00:05:00) [common]
  325 03:54:49.422380  [common] connect-device Connecting to device using 'telnet ts5 2002'
  326 03:54:49.429403  Setting prompt string to ['lava-test: # ']
  327 03:54:49.429870  end: 2.3 connect-device (duration 00:00:00) [common]
  328 03:54:49.430066  start: 2.4 uboot-commands (timeout 00:05:00) [common]
  329 03:54:49.430250  start: 2.4.1 reset-device (timeout 00:05:00) [common]
  330 03:54:49.430426  start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
  331 03:54:49.430708  Calling: 'drpm' 'lf-bbb-02' 'powercycle'
  332 03:54:49.784287  >> OFF

  333 03:55:05.123579  >> ON

  334 03:55:05.124406  Returned 0 in 15 seconds
  335 03:55:05.225159  end: 2.4.1.1 pdu-reboot (duration 00:00:16) [common]
  337 03:55:05.226302  end: 2.4.1 reset-device (duration 00:00:16) [common]
  338 03:55:05.226739  start: 2.4.2 bootloader-interrupt (timeout 00:04:44) [common]
  339 03:55:05.227068  Setting prompt string to ['Hit any key to stop autoboot']
  340 03:55:05.227250  bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
  341 03:55:05.228255  Trying 192.168.1.205...
  342 03:55:05.228574  Connected to ts5.
  343 03:55:05.228895  Escape character is '^]'.
  344 03:55:05.229187  
  345 03:55:05.229473  ser2net port telnet,2002 device serialdev,/dev/ttyUSB-lf-bbb-02,115200n81,local [] (Debian GNU/Linux)
  346 03:55:05.229770  
  347 03:55:05.706254  
  348 03:55:05.715420  U-Boot SPL 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  349 03:55:05.715835  Trying to boot from MMC2
  350 03:55:06.228360  
  351 03:55:06.228765  
  352 03:55:06.233273  U-Boot 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  353 03:55:06.233679  
  354 03:55:06.234006  CPU  : AM335X-GP rev 2.1
  355 03:55:06.240176  Model: TI AM335x BeagleBone Black
  356 03:55:06.240572  DRAM:  512 MiB
  357 03:55:06.320980  WDT:   Started with servicing (60s timeout)
  358 03:55:06.727073  NAND:  0 MiB
  359 03:55:06.736905  MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
  360 03:55:06.770317  Loading Environment from FAT... <ethaddr> not set. Validating first E-fuse MAC
  361 03:55:06.800813  Net:   eth2: ethernet@4a100000, eth3: usb_ether
  362 03:55:06.858474  end: 2.4.2 bootloader-interrupt (duration 00:00:02) [common]
  363 03:55:06.858967  start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
  364 03:55:06.859351  Setting prompt string to ['=> ']
  365 03:55:06.859732  bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:43)
  366 03:55:06.868330  Hit any key to stop autoboot:  2   0 
  367 03:55:06.869095  Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  368 03:55:06.869484  Sending with 10 millisecond of delay
  370 03:55:08.006280  => setenv autoload no
  371 03:55:08.016938  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:41)
  372 03:55:08.020072  setenv autoload no
  373 03:55:08.020679  Sending with 10 millisecond of delay
  375 03:55:09.820857  => setenv initrd_high 0xffffffff
  376 03:55:09.831449  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:40)
  377 03:55:09.832089  setenv initrd_high 0xffffffff
  378 03:55:09.832660  Sending with 10 millisecond of delay
  380 03:55:11.452003  => setenv fdt_high 0xffffffff
  381 03:55:11.462612  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:38)
  382 03:55:11.463253  setenv fdt_high 0xffffffff
  383 03:55:11.463828  Sending with 10 millisecond of delay
  385 03:55:11.755896  => dhcp
  386 03:55:11.766455  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:38)
  387 03:55:11.767802  dhcp
  388 03:55:11.768186  link up on port 0, speed 100, full duplex
  389 03:55:11.768504  BOOTP broadcast 1
  390 03:55:11.823671  DHCP client bound to address 172.16.3.190 (50 ms)
  391 03:55:11.824303  Sending with 10 millisecond of delay
  393 03:55:13.443521  => setenv serverip 172.16.3.3
  394 03:55:13.454130  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:36)
  395 03:55:13.454757  setenv serverip 172.16.3.3
  396 03:55:13.455329  Sending with 10 millisecond of delay
  398 03:55:17.004900  => tftp 0x82000000 1216052/tftp-deploy-yd1p0v46/kernel/zImage
  399 03:55:17.015642  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
  400 03:55:17.017243  tftp 0x82000000 1216052/tftp-deploy-yd1p0v46/kernel/zImage
  401 03:55:17.017629  link up on port 0, speed 100, full duplex
  402 03:55:17.022035  Using ethernet@4a100000 device
  403 03:55:17.028042  TFTP from server 172.16.3.3; our IP address is 172.16.3.190
  404 03:55:17.034906  Filename '1216052/tftp-deploy-yd1p0v46/kernel/zImage'.
  405 03:55:17.035306  Load address: 0x82000000
  406 03:55:20.052655  Loading: *##################################################  11.5 MiB
  407 03:55:20.053186  	 3.8 MiB/s
  408 03:55:20.053501  done
  409 03:55:20.057076  Bytes transferred = 12050944 (b7e200 hex)
  410 03:55:20.057726  Sending with 10 millisecond of delay
  412 03:55:24.572550  => tftp 0x83000000 1216052/tftp-deploy-yd1p0v46/ramdisk/ramdisk.cpio.gz.uboot
  413 03:55:24.583243  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:25)
  414 03:55:24.584139  tftp 0x83000000 1216052/tftp-deploy-yd1p0v46/ramdisk/ramdisk.cpio.gz.uboot
  415 03:55:24.584474  link up on port 0, speed 100, full duplex
  416 03:55:24.590227  Using ethernet@4a100000 device
  417 03:55:24.595229  TFTP from server 172.16.3.3; our IP address is 172.16.3.190
  418 03:55:24.603003  Filename '1216052/tftp-deploy-yd1p0v46/ramdisk/ramdisk.cpio.gz.uboot'.
  419 03:55:24.603277  Load address: 0x83000000
  420 03:55:28.258300  Loading: *##################################################  14.6 MiB
  421 03:55:28.258567  	 4 MiB/s
  422 03:55:28.258695  done
  423 03:55:28.262519  Bytes transferred = 15357759 (ea573f hex)
  424 03:55:28.262881  Sending with 10 millisecond of delay
  426 03:55:30.120915  => setenv initrd_size ${filesize}
  427 03:55:30.131646  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:19)
  428 03:55:30.132285  setenv initrd_size ${filesize}
  429 03:55:30.132874  Sending with 10 millisecond of delay
  431 03:55:34.345885  => tftp 0x88000000 1216052/tftp-deploy-yd1p0v46/dtb/am335x-boneblack.dtb
  432 03:55:34.356484  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
  433 03:55:34.357498  tftp 0x88000000 1216052/tftp-deploy-yd1p0v46/dtb/am335x-boneblack.dtb
  434 03:55:34.357885  link up on port 0, speed 100, full duplex
  435 03:55:34.362534  Using ethernet@4a100000 device
  436 03:55:34.368513  TFTP from server 172.16.3.3; our IP address is 172.16.3.190
  437 03:55:34.378217  Filename '1216052/tftp-deploy-yd1p0v46/dtb/am335x-boneblack.dtb'.
  438 03:55:34.378423  Load address: 0x88000000
  439 03:55:34.399330  Loading: *##################################################  68.9 KiB
  440 03:55:34.399730  	 3.2 MiB/s
  441 03:55:34.400045  done
  442 03:55:34.404017  Bytes transferred = 70568 (113a8 hex)
  443 03:55:34.404650  Sending with 10 millisecond of delay
  445 03:55:47.786867  => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1216052/extract-nfsrootfs-t70l5rdy,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  446 03:55:47.797565  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:02)
  447 03:55:47.798206  setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1216052/extract-nfsrootfs-t70l5rdy,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  448 03:55:47.798800  Sending with 10 millisecond of delay
  450 03:55:50.141674  => bootz 0x82000000 0x83000000 0x88000000
  451 03:55:50.152301  Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  452 03:55:50.152756  bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:03:59)
  453 03:55:50.153508  bootz 0x82000000 0x83000000 0x88000000
  454 03:55:50.153845  Kernel image @ 0x82000000 [ 0x000000 - 0xb7e200 ]
  455 03:55:50.155901  ## Loading init Ramdisk from Legacy Image at 83000000 ...
  456 03:55:50.161062     Image Name:   
  457 03:55:50.161455     Created:      2024-11-04   3:54:49 UTC
  458 03:55:50.169777     Image Type:   ARM Linux RAMDisk Image (uncompressed)
  459 03:55:50.170171     Data Size:    15357695 Bytes = 14.6 MiB
  460 03:55:50.179034     Load Address: 00000000
  461 03:55:50.179429     Entry Point:  00000000
  462 03:55:50.353374     Verifying Checksum ... OK
  463 03:55:50.353765  ## Flattened Device Tree blob at 88000000
  464 03:55:50.359723     Booting using the fdt blob at 0x88000000
  465 03:55:50.365324     Using Device Tree in place at 88000000, end 880143a7
  466 03:55:50.378509  
  467 03:55:50.378901  Starting kernel ...
  468 03:55:50.379214  
  469 03:55:50.379915  end: 2.4.3 bootloader-commands (duration 00:00:44) [common]
  470 03:55:50.380348  start: 2.4.4 auto-login-action (timeout 00:03:59) [common]
  471 03:55:50.380701  Setting prompt string to ['Linux version [0-9]']
  472 03:55:50.381076  Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  473 03:55:50.381421  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
  474 03:55:51.271506  [    0.000000] Booting Linux on physical CPU 0x0
  475 03:55:51.278230  start: 2.4.4.1 login-action (timeout 00:03:58) [common]
  476 03:55:51.278657  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
  477 03:55:51.279008  Setting prompt string to []
  478 03:55:51.279357  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
  479 03:55:51.279699  Using line separator: #'\n'#
  480 03:55:51.280001  No login prompt set.
  481 03:55:51.280312  Parsing kernel messages
  482 03:55:51.280595  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
  483 03:55:51.281161  [login-action] Waiting for messages, (timeout 00:03:58)
  484 03:55:51.291328  [    0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j361380-arm-clang-15-multi-v7-defconfig-jwbm9) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Mon Nov  4 02:59:56 UTC 2024
  485 03:55:51.297676  [    0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
  486 03:55:51.303804  [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
  487 03:55:51.312574  [    0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
  488 03:55:51.318831  [    0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
  489 03:55:51.324954  [    0.000000] printk: legacy bootconsole [omap8250] enabled
  490 03:55:51.328394  [    0.000000] Memory policy: Data cache writeback
  491 03:55:51.328779  [    0.000000] efi: UEFI not found.
  492 03:55:51.336807  [    0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
  493 03:55:51.343211  [    0.000000] Zone ranges:
  494 03:55:51.348086  [    0.000000]   DMA      [mem 0x0000000080000000-0x000000009fdfffff]
  495 03:55:51.354209  [    0.000000]   Normal   empty
  496 03:55:51.354594  [    0.000000]   HighMem  empty
  497 03:55:51.357729  [    0.000000] Movable zone start for each node
  498 03:55:51.361766  [    0.000000] Early memory node ranges
  499 03:55:51.367863  [    0.000000]   node   0: [mem 0x0000000080000000-0x000000009fdfffff]
  500 03:55:51.377061  [    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
  501 03:55:51.395277  [    0.000000] CPU: All CPU(s) started in SVC mode.
  502 03:55:51.404904  [    0.000000] AM335X ES2.1 (sgx neon)
  503 03:55:51.408434  [    0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
  504 03:55:51.435894  [    0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1216052/extract-nfsrootfs-t70l5rdy,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
  505 03:55:51.439763  <6>[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
  506 03:55:51.446004  <6>[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
  507 03:55:51.458297  <6>[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130560
  508 03:55:51.463845  <6>[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
  509 03:55:51.493276  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
  510 03:55:51.499438  <6>[    0.000000] trace event string verifier disabled
  511 03:55:51.499834  <6>[    0.000000] rcu: Hierarchical RCU implementation.
  512 03:55:51.506889  <6>[    0.000000] rcu: 	RCU event tracing is enabled.
  513 03:55:51.513015  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
  514 03:55:51.522836  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
  515 03:55:51.529785  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
  516 03:55:51.544893  <6>[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
  517 03:55:51.562485  <6>[    0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
  518 03:55:51.568629  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
  519 03:55:51.668386  <6>[    0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
  520 03:55:51.676929  <6>[    0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
  521 03:55:51.689391  <6>[    0.008341] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
  522 03:55:51.697859  <6>[    0.019196] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
  523 03:55:51.707270  <6>[    0.034237] Console: colour dummy device 80x30
  524 03:55:51.713988  Matched prompt #6: WARNING:
  525 03:55:51.714392  Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
  526 03:55:51.719878  <3>[    0.039137] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
  527 03:55:51.722130  <3>[    0.046213] This ensures that you still see kernel messages. Please
  528 03:55:51.727813  <3>[    0.052940] update your kernel commandline.
  529 03:55:51.768896  <6>[    0.057554] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
  530 03:55:51.773938  <6>[    0.096210] CPU: Testing write buffer coherency: ok
  531 03:55:51.777502  <6>[    0.101579] CPU0: Spectre v2: using BPIALL workaround
  532 03:55:51.782555  <6>[    0.107047] pid_max: default: 32768 minimum: 301
  533 03:55:51.789055  <6>[    0.112242] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  534 03:55:51.798887  <6>[    0.120066] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  535 03:55:51.806354  <6>[    0.129516] CPU0: thread -1, cpu 0, socket -1, mpidr 0
  536 03:55:51.813063  <6>[    0.136467] Setting up static identity map for 0x80300000 - 0x803000ac
  537 03:55:51.819375  <6>[    0.146178] rcu: Hierarchical SRCU implementation.
  538 03:55:51.827394  <6>[    0.151468] rcu: 	Max phase no-delay instances is 1000.
  539 03:55:51.836008  <6>[    0.162803] EFI services will not be available.
  540 03:55:51.842152  <6>[    0.168092] smp: Bringing up secondary CPUs ...
  541 03:55:51.847134  <6>[    0.173157] smp: Brought up 1 node, 1 CPU
  542 03:55:51.855863  <6>[    0.177557] SMP: Total of 1 processors activated (996.14 BogoMIPS).
  543 03:55:51.862255  <6>[    0.184325] CPU: All CPU(s) started in SVC mode.
  544 03:55:51.880034  <6>[    0.189537] Memory: 404424K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50624K reserved, 65536K cma-reserved, 0K highmem)
  545 03:55:51.880450  <6>[    0.205819] devtmpfs: initialized
  546 03:55:51.903130  <6>[    0.223912] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
  547 03:55:51.911494  <6>[    0.232529] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
  548 03:55:51.919845  <6>[    0.242994] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
  549 03:55:51.931443  <6>[    0.255337] pinctrl core: initialized pinctrl subsystem
  550 03:55:51.941272  <6>[    0.266181] DMI not present or invalid.
  551 03:55:51.949889  <6>[    0.272067] NET: Registered PF_NETLINK/PF_ROUTE protocol family
  552 03:55:51.958018  <6>[    0.281074] DMA: preallocated 256 KiB pool for atomic coherent allocations
  553 03:55:51.974735  <6>[    0.292748] thermal_sys: Registered thermal governor 'step_wise'
  554 03:55:51.975125  <6>[    0.292922] cpuidle: using governor menu
  555 03:55:52.001147  <6>[    0.328311] No ATAGs?
  556 03:55:52.006806  <6>[    0.331053] hw-breakpoint: debug architecture 0x4 unsupported.
  557 03:55:52.018265  <6>[    0.343215] Serial: AMBA PL011 UART driver
  558 03:55:52.049053  <6>[    0.375551] iommu: Default domain type: Translated
  559 03:55:52.057113  <6>[    0.380904] iommu: DMA domain TLB invalidation policy: strict mode
  560 03:55:52.084632  <5>[    0.410615] SCSI subsystem initialized
  561 03:55:52.090754  <6>[    0.415543] usbcore: registered new interface driver usbfs
  562 03:55:52.095706  <6>[    0.421605] usbcore: registered new interface driver hub
  563 03:55:52.104353  <6>[    0.427401] usbcore: registered new device driver usb
  564 03:55:52.110631  <6>[    0.433975] pps_core: LinuxPPS API ver. 1 registered
  565 03:55:52.119082  <6>[    0.439367] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
  566 03:55:52.127263  <6>[    0.449101] PTP clock support registered
  567 03:55:52.127651  <6>[    0.453572] EDAC MC: Ver: 3.0.0
  568 03:55:52.184027  <6>[    0.509146] scmi_core: SCMI protocol bus registered
  569 03:55:52.190018  <6>[    0.517383] vgaarb: loaded
  570 03:55:52.203997  <6>[    0.530160] clocksource: Switched to clocksource dmtimer
  571 03:55:52.241891  <6>[    0.568751] NET: Registered PF_INET protocol family
  572 03:55:52.255267  <6>[    0.574475] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
  573 03:55:52.260158  <6>[    0.583492] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
  574 03:55:52.272627  <6>[    0.592428] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
  575 03:55:52.278708  <6>[    0.600693] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
  576 03:55:52.287385  <6>[    0.608963] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
  577 03:55:52.293303  <6>[    0.616691] TCP: Hash tables configured (established 4096 bind 4096)
  578 03:55:52.299522  <6>[    0.623615] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
  579 03:55:52.308034  <6>[    0.630654] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
  580 03:55:52.314828  <6>[    0.638235] NET: Registered PF_UNIX/PF_LOCAL protocol family
  581 03:55:52.395889  <6>[    0.717559] RPC: Registered named UNIX socket transport module.
  582 03:55:52.396281  <6>[    0.724018] RPC: Registered udp transport module.
  583 03:55:52.402137  <6>[    0.729126] RPC: Registered tcp transport module.
  584 03:55:52.408500  <6>[    0.734249] RPC: Registered tcp-with-tls transport module.
  585 03:55:52.420899  <6>[    0.740175] RPC: Registered tcp NFSv4.1 backchannel transport module.
  586 03:55:52.421290  <6>[    0.747085] PCI: CLS 0 bytes, default 64
  587 03:55:52.427811  <5>[    0.752974] Initialise system trusted keyrings
  588 03:55:52.450122  <6>[    0.774082] Trying to unpack rootfs image as initramfs...
  589 03:55:52.521050  <6>[    0.840536] workingset: timestamp_bits=30 max_order=17 bucket_order=0
  590 03:55:52.524115  <6>[    0.848061] squashfs: version 4.0 (2009/01/31) Phillip Lougher
  591 03:55:52.573894  <5>[    0.900464] NFS: Registering the id_resolver key type
  592 03:55:52.580000  <5>[    0.906059] Key type id_resolver registered
  593 03:55:52.584899  <5>[    0.910729] Key type id_legacy registered
  594 03:55:52.593400  <6>[    0.915169] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
  595 03:55:52.600128  <6>[    0.922375] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
  596 03:55:52.674138  <5>[    1.001338] Key type asymmetric registered
  597 03:55:52.680364  <5>[    1.005865] Asymmetric key parser 'x509' registered
  598 03:55:52.688979  <6>[    1.011370] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
  599 03:55:52.693999  <6>[    1.019260] io scheduler mq-deadline registered
  600 03:55:52.698882  <6>[    1.024242] io scheduler kyber registered
  601 03:55:52.703125  <6>[    1.028699] io scheduler bfq registered
  602 03:55:52.806999  <6>[    1.130250] ledtrig-cpu: registered to indicate activity on CPUs
  603 03:55:53.108602  <6>[    1.431302] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
  604 03:55:53.139565  <6>[    1.465617] msm_serial: driver initialized
  605 03:55:53.144684  <6>[    1.470701] SuperH (H)SCI(F) driver initialized
  606 03:55:53.150804  <6>[    1.475831] STMicroelectronics ASC driver initialized
  607 03:55:53.156443  <6>[    1.481536] STM32 USART driver initialized
  608 03:55:53.295338  <6>[    1.621427] brd: module loaded
  609 03:55:53.318355  <6>[    1.644141] loop: module loaded
  610 03:55:53.370314  <6>[    1.695992] CAN device driver interface
  611 03:55:53.376558  <6>[    1.701196] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
  612 03:55:53.382585  <6>[    1.708142] e1000e: Intel(R) PRO/1000 Network Driver
  613 03:55:53.388855  <6>[    1.713597] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
  614 03:55:53.393807  <6>[    1.720020] igb: Intel(R) Gigabit Ethernet Network Driver
  615 03:55:53.403439  <6>[    1.725867] igb: Copyright (c) 2007-2014 Intel Corporation.
  616 03:55:53.409531  <6>[    1.735175] pegasus: Pegasus/Pegasus II USB Ethernet driver
  617 03:55:53.420723  <6>[    1.741347] usbcore: registered new interface driver pegasus
  618 03:55:53.426879  <6>[    1.747479] usbcore: registered new interface driver asix
  619 03:55:53.432982  <6>[    1.753365] usbcore: registered new interface driver ax88179_178a
  620 03:55:53.437848  <6>[    1.759931] usbcore: registered new interface driver cdc_ether
  621 03:55:53.443884  <6>[    1.766254] usbcore: registered new interface driver smsc75xx
  622 03:55:53.448979  <6>[    1.772495] usbcore: registered new interface driver smsc95xx
  623 03:55:53.455111  <6>[    1.778712] usbcore: registered new interface driver net1080
  624 03:55:53.461171  <6>[    1.784866] usbcore: registered new interface driver cdc_subset
  625 03:55:53.466036  <6>[    1.791303] usbcore: registered new interface driver zaurus
  626 03:55:53.477011  <6>[    1.797349] usbcore: registered new interface driver cdc_ncm
  627 03:55:53.483700  <6>[    1.806888] usbcore: registered new interface driver usb-storage
  628 03:55:53.491987  <6>[    1.818021] i2c_dev: i2c /dev entries driver
  629 03:55:53.518366  <5>[    1.836790] cpuidle: enable-method property 'ti,am3352' found operations
  630 03:55:53.524292  <6>[    1.846420] sdhci: Secure Digital Host Controller Interface driver
  631 03:55:53.531757  <6>[    1.853202] sdhci: Copyright(c) Pierre Ossman
  632 03:55:53.537876  <6>[    1.859668] Synopsys Designware Multimedia Card Interface Driver
  633 03:55:53.544606  <6>[    1.867688] sdhci-pltfm: SDHCI platform and OF driver helper
  634 03:55:53.558995  <6>[    1.877668] usbcore: registered new interface driver usbhid
  635 03:55:53.559385  <6>[    1.883803] usbhid: USB HID core driver
  636 03:55:53.573119  <6>[    1.895622] NET: Registered PF_INET6 protocol family
  637 03:55:54.054066  <6>[    2.381016] Segment Routing with IPv6
  638 03:55:54.060054  <6>[    2.385166] In-situ OAM (IOAM) with IPv6
  639 03:55:54.066298  <6>[    2.389574] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
  640 03:55:54.073680  <6>[    2.396968] NET: Registered PF_PACKET protocol family
  641 03:55:54.079773  <6>[    2.402534] can: controller area network core
  642 03:55:54.085931  <6>[    2.407359] NET: Registered PF_CAN protocol family
  643 03:55:54.086319  <6>[    2.412586] can: raw protocol
  644 03:55:54.089396  <6>[    2.415914] can: broadcast manager protocol
  645 03:55:54.095773  <6>[    2.420512] can: netlink gateway - max_hops=1
  646 03:55:54.100913  <5>[    2.426095] Key type dns_resolver registered
  647 03:55:54.107045  <6>[    2.431185] ThumbEE CPU extension supported.
  648 03:55:54.110606  <5>[    2.435879] Registering SWP/SWPB emulation handler
  649 03:55:54.118906  <3>[    2.441585] omap_voltage_late_init: Voltage driver support not added
  650 03:55:54.315956  <5>[    2.641081] Loading compiled-in X.509 certificates
  651 03:55:54.431961  <6>[    2.746472] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
  652 03:55:54.439902  <6>[    2.763200] pinctrl-single 44e10800.pinmux: 142 pins, size 568
  653 03:55:54.465810  <3>[    2.787448] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
  654 03:55:54.668849  <3>[    2.990493] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
  655 03:55:54.865928  <6>[    3.191004] OMAP GPIO hardware version 0.1
  656 03:55:54.886103  <6>[    3.210033] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
  657 03:55:54.979243  <4>[    3.302357] at24 2-0054: supply vcc not found, using dummy regulator
  658 03:55:55.013205  <4>[    3.335839] at24 2-0055: supply vcc not found, using dummy regulator
  659 03:55:55.052371  <4>[    3.374980] at24 2-0056: supply vcc not found, using dummy regulator
  660 03:55:55.092810  <4>[    3.414860] at24 2-0057: supply vcc not found, using dummy regulator
  661 03:55:55.131089  <6>[    3.454895] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
  662 03:55:55.173720  <3>[    3.493169] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
  663 03:55:55.197936  <6>[    3.514596] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  664 03:55:55.220337  <4>[    3.541854] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  665 03:55:55.239747  <4>[    3.561189] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  666 03:55:55.317100  <6>[    3.640665] omap_rng 48310000.rng: Random Number Generator ver. 20
  667 03:55:55.342002  <5>[    3.667560] random: crng init done
  668 03:55:55.373436  <6>[    3.699040] Freeing initrd memory: 15000K
  669 03:55:55.388493  <6>[    3.710282] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
  670 03:55:55.442358  <6>[    3.762628] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
  671 03:55:55.447473  <6>[    3.772998] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
  672 03:55:55.460886  <6>[    3.780345] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
  673 03:55:55.466966  <6>[    3.787813] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
  674 03:55:55.475514  <6>[    3.795949] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
  675 03:55:55.487948  <6>[    3.807595] cpsw-switch 4a100000.switch: Detected MACID = 04:79:b7:e7:06:e0
  676 03:55:55.497200  <5>[    3.816714] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
  677 03:55:55.526856  <3>[    3.847174] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
  678 03:55:55.531143  <6>[    3.855774] edma 49000000.dma: TI EDMA DMA engine driver
  679 03:55:55.604547  <3>[    3.925232] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
  680 03:55:55.620058  <6>[    3.939730] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
  681 03:55:55.632688  <3>[    3.956975] l3-aon-clkctrl:0000:0: failed to disable
  682 03:55:55.687607  <6>[    4.008965] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
  683 03:55:55.692698  <6>[    4.018489] printk: legacy console [ttyS0] enabled
  684 03:55:55.698970  <6>[    4.018489] printk: legacy console [ttyS0] enabled
  685 03:55:55.705105  <6>[    4.028833] printk: legacy bootconsole [omap8250] disabled
  686 03:55:55.709688  <6>[    4.028833] printk: legacy bootconsole [omap8250] disabled
  687 03:55:55.741273  <4>[    4.061048] tps65217-pmic: Failed to locate of_node [id: -1]
  688 03:55:55.744460  <4>[    4.068459] tps65217-bl: Failed to locate of_node [id: -1]
  689 03:55:55.761356  <6>[    4.088567] tps65217 0-0024: TPS65217 ID 0xe version 1.2
  690 03:55:55.781364  <6>[    4.095579] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  691 03:55:55.793723  <6>[    4.109288] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
  692 03:55:55.797103  <6>[    4.121259] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
  693 03:55:55.820090  <6>[    4.141709] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
  694 03:55:55.826222  <6>[    4.150884] sdhci-omap 48060000.mmc: Got CD GPIO
  695 03:55:55.834169  <4>[    4.156035] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
  696 03:55:55.849107  <4>[    4.169661] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
  697 03:55:55.855121  <4>[    4.178454] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  698 03:55:55.865653  <4>[    4.187106] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  699 03:55:55.914382  <6>[    4.236754] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
  700 03:55:55.942137  <6>[    4.263644] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
  701 03:55:55.989536  <6>[    4.310468] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
  702 03:55:55.996479  <6>[    4.319318] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
  703 03:55:56.063775  <6>[    4.380714] mmc1: new high speed MMC card at address 0001
  704 03:55:56.064163  <6>[    4.388811] mmcblk1: mmc1:0001 M62704 3.56 GiB
  705 03:55:56.074642  <6>[    4.400041]  mmcblk1: p1
  706 03:55:56.080094  <6>[    4.405044] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
  707 03:55:56.090596  <6>[    4.415409] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
  708 03:55:56.105224  <6>[    4.426154] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
  709 03:55:56.113844  <6>[    4.433524] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
  710 03:55:58.190390  <6>[    6.511209] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
  711 03:55:58.303301  <5>[    6.550165] Sending DHCP requests ., OK
  712 03:55:58.314768  <6>[    6.634729] IP-Config: Got DHCP answer from 172.16.3.3, my address is 172.16.3.190
  713 03:55:58.315154  <6>[    6.642815] IP-Config: Complete:
  714 03:55:58.328641  <6>[    6.646355]      device=eth0, hwaddr=04:79:b7:e7:06:e0, ipaddr=172.16.3.190, mask=255.255.255.0, gw=172.16.3.3
  715 03:55:58.334889  <6>[    6.656794]      host=172.16.3.190, domain=denx.de, nis-domain=(none)
  716 03:55:58.339893  <6>[    6.663623]      bootserver=172.16.3.33, rootserver=172.16.3.3, rootpath=
  717 03:55:58.347252  <6>[    6.663660]      nameserver0=172.16.3.3
  718 03:55:58.347632  <6>[    6.674988]      ntpserver0=172.16.3.3
  719 03:55:58.353385  <6>[    6.680508] clk: Disabling unused clocks
  720 03:55:58.360141  <6>[    6.685124] PM: genpd: Disabling unused power domains
  721 03:55:58.378241  <6>[    6.702237] Freeing unused kernel image (initmem) memory: 2048K
  722 03:55:58.386440  <6>[    6.712084] Run /init as init process
  723 03:55:58.409136  Loading, please wait...
  724 03:55:58.487000  Starting systemd-udevd version 252.22-1~deb12u1
  725 03:56:01.551562  <4>[    9.871804] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  726 03:56:01.689358  <4>[   10.009431] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  727 03:56:01.863712  <6>[   10.191290] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
  728 03:56:01.874143  <6>[   10.196967] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
  729 03:56:02.145162  <6>[   10.471110] hub 1-0:1.0: USB hub found
  730 03:56:02.162906  <6>[   10.489526] tda998x 0-0070: found TDA19988
  731 03:56:02.174303  <6>[   10.500381] hub 1-0:1.0: 1 port detected
  732 03:56:05.058073  Begin: Loading essential drivers ... done.
  733 03:56:05.064321  Begin: Running /scripts/init-premount ... done.
  734 03:56:05.069178  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
  735 03:56:05.081108  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
  736 03:56:05.086624  Device /sys/class/net/eth0 found
  737 03:56:05.087009  done.
  738 03:56:05.147310  Begin: Waiting up to 180 secs for any network device to become available ... done.
  739 03:56:05.226637  IP-Config: eth0 hardware address 04:79:b7:e7:06:e0 mtu 1500 DHCP
  740 03:56:05.261607  IP-Config: eth0 complete (dhcp from 172.16.3.3):
  741 03:56:05.272848   address: 172.16.3.190     broadcast: 172.16.3.255     netmask: 255.255.255.0   
  742 03:56:05.276322   gateway: 172.16.3.3       dns0     : 172.16.3.3       dns1   : 0.0.0.0         
  743 03:56:05.287636   domain : denx.de                                                         
  744 03:56:05.288033   rootserver: 172.16.3.33 rootpath: 
  745 03:56:05.291951   filename  : this-host-is-not-configured.kpxe
  746 03:56:05.337636  done.
  747 03:56:05.348266  Begin: Running /scripts/nfs-bottom ... done.
  748 03:56:05.421695  Begin: Running /scripts/init-bottom ... done.
  749 03:56:06.879200  <30>[   15.202446] systemd[1]: System time before build time, advancing clock.
  750 03:56:07.161964  <30>[   15.459267] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
  751 03:56:07.171449  <30>[   15.496577] systemd[1]: Detected architecture arm.
  752 03:56:07.186205  
  753 03:56:07.186592  Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
  754 03:56:07.186903  
  755 03:56:07.216965  <30>[   15.540970] systemd[1]: Hostname set to <debian-bookworm-armhf>.
  756 03:56:09.569724  <30>[   17.891971] systemd[1]: Queued start job for default target graphical.target.
  757 03:56:09.586675  <30>[   17.907044] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
  758 03:56:09.593482  [[0;32m  OK  [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
  759 03:56:09.624718  <30>[   17.946221] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
  760 03:56:09.636598  [[0;32m  OK  [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
  761 03:56:09.661920  <30>[   17.983629] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
  762 03:56:09.670260  [[0;32m  OK  [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
  763 03:56:09.691434  <30>[   18.012242] systemd[1]: Created slice user.slice - User and Session Slice.
  764 03:56:09.697015  [[0;32m  OK  [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
  765 03:56:09.727243  <30>[   18.041553] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
  766 03:56:09.732751  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
  767 03:56:09.762256  <30>[   18.082474] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
  768 03:56:09.772962  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
  769 03:56:09.810225  <30>[   18.121124] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
  770 03:56:09.817707  <30>[   18.141583] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
  771 03:56:09.825619           Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
  772 03:56:09.848726  <30>[   18.170637] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
  773 03:56:09.856986  [[0;32m  OK  [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
  774 03:56:09.880077  <30>[   18.201040] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
  775 03:56:09.887334  [[0;32m  OK  [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
  776 03:56:09.909612  <30>[   18.231257] systemd[1]: Reached target paths.target - Path Units.
  777 03:56:09.913801  [[0;32m  OK  [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
  778 03:56:09.939228  <30>[   18.260788] systemd[1]: Reached target remote-fs.target - Remote File Systems.
  779 03:56:09.945825  [[0;32m  OK  [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
  780 03:56:09.968969  <30>[   18.290759] systemd[1]: Reached target slices.target - Slice Units.
  781 03:56:09.974447  [[0;32m  OK  [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
  782 03:56:09.999817  <30>[   18.320960] systemd[1]: Reached target swap.target - Swaps.
  783 03:56:10.002959  [[0;32m  OK  [0m] Reached target [0;1;39mswap.target[0m - Swaps.
  784 03:56:10.029102  <30>[   18.350992] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
  785 03:56:10.038339  [[0;32m  OK  [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
  786 03:56:10.060231  <30>[   18.381776] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
  787 03:56:10.068851  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
  788 03:56:10.154336  <30>[   18.470680] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
  789 03:56:10.166968  <30>[   18.488471] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
  790 03:56:10.176077  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
  791 03:56:10.201393  <30>[   18.521942] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
  792 03:56:10.208329  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
  793 03:56:10.233714  <30>[   18.554012] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
  794 03:56:10.240942  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
  795 03:56:10.263970  <30>[   18.585670] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
  796 03:56:10.270226  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
  797 03:56:10.300908  <30>[   18.623484] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
  798 03:56:10.314038  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
  799 03:56:10.347585  <30>[   18.662027] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
  800 03:56:10.362833  <30>[   18.678765] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
  801 03:56:10.413868  <30>[   18.736366] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
  802 03:56:10.433065           Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
  803 03:56:10.491283  <30>[   18.813824] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
  804 03:56:10.517604           Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
  805 03:56:10.591916  <30>[   18.913940] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
  806 03:56:10.607201           Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
  807 03:56:10.645475  <30>[   18.966952] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
  808 03:56:10.657422           Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
  809 03:56:10.711560  <30>[   19.033876] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
  810 03:56:10.730965           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  811 03:56:10.754244  <30>[   19.076783] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
  812 03:56:10.777878           Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
  813 03:56:10.832191  <30>[   19.153846] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
  814 03:56:10.850336           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  815 03:56:10.908648  <30>[   19.232066] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
  816 03:56:10.930899           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  817 03:56:11.001872  <30>[   19.324912] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
  818 03:56:11.018853           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  819 03:56:11.036961  <28>[   19.354791] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
  820 03:56:11.057365  <28>[   19.379229] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
  821 03:56:11.099816  <30>[   19.423773] systemd[1]: Starting systemd-journald.service - Journal Service...
  822 03:56:11.117822           Starting [0;1;39msystemd-journald.service[0m - Journal Service...
  823 03:56:11.196089  <30>[   19.518907] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
  824 03:56:11.221616           Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
  825 03:56:11.270935  <30>[   19.593423] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
  826 03:56:11.312389           Starting [0;1;39msystemd-network-g… units from Kernel command line...
  827 03:56:11.363473  <30>[   19.684682] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
  828 03:56:11.413167           Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
  829 03:56:11.502176  <30>[   19.823567] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
  830 03:56:11.545611           Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
  831 03:56:11.612516  <30>[   19.935049] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
  832 03:56:11.672555  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
  833 03:56:11.678665  <30>[   20.002583] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
  834 03:56:11.723027  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
  835 03:56:11.754078  <30>[   20.075796] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
  836 03:56:11.795632  [[0;32m  OK  [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
  837 03:56:11.982651  <30>[   20.305109] systemd[1]: modprobe@configfs.service: Deactivated successfully.
  838 03:56:12.019700  <30>[   20.342255] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
  839 03:56:12.049767  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
  840 03:56:12.069642  <30>[   20.391833] systemd[1]: Started systemd-journald.service - Journal Service.
  841 03:56:12.077547  [[0;32m  OK  [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
  842 03:56:12.109688  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  843 03:56:12.140549  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
  844 03:56:12.170345  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  845 03:56:12.193761  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  846 03:56:12.229915  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  847 03:56:12.258898  [[0;32m  OK  [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
  848 03:56:12.281275  [[0;32m  OK  [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
  849 03:56:12.301652  [[0;32m  OK  [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
  850 03:56:12.329575  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
  851 03:56:12.390795           Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
  852 03:56:12.442764           Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
  853 03:56:12.521063           Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
  854 03:56:12.614768           Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
  855 03:56:12.672563           Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
  856 03:56:12.821162  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
  857 03:56:12.829088  <46>[   21.152104] systemd-journald[162]: Received client request to flush runtime journal.
  858 03:56:13.038445  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
  859 03:56:13.123112  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
  860 03:56:13.159209  [[0;32m  OK  [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
  861 03:56:13.199385           Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
  862 03:56:14.736368  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
  863 03:56:14.759897  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
  864 03:56:14.778123  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
  865 03:56:14.849119           Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
  866 03:56:14.903374  [[0;32m  OK  [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
  867 03:56:14.986840           Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
  868 03:56:15.862054  [[0;32m  OK  [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
  869 03:56:15.939551           Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
  870 03:56:17.142038  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
  871 03:56:18.302199  [[0;32m  OK  [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
  872 03:56:18.736987  [[0;32m  OK  [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
  873 03:56:19.119338  <5>[   27.442646] cfg80211: Loading compiled-in X.509 certificates for regulatory database
  874 03:56:20.346987  <5>[   28.672627] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
  875 03:56:20.429823  <5>[   28.750994] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
  876 03:56:20.435920  <4>[   28.760691] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
  877 03:56:20.442707  <6>[   28.769662] cfg80211: failed to load regulatory.db
  878 03:56:20.832367  [[0m[0;31m*     [0m] Job systemd-networkd.service/start running (11s / 1min 36s)
  879 03:56:21.340449  M[K[[0;1;31m*[0m[0;31m*    [0m] Job systemd-networkd.service/start running (11s / 1min 36s)
  880 03:56:21.489590  M[K[[0;32m  OK  [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
  881 03:56:28.619215  [K[[0;32m  OK  [0m] Reached target [0;1;39mnetwork.target[0m - Network.
  882 03:56:28.639494  [[0;32m  OK  [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
  883 03:56:28.661219  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
  884 03:56:28.719491           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  885 03:56:28.760805           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  886 03:56:28.819927           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  887 03:56:28.867539           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  888 03:56:29.110409           Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
  889 03:56:29.188763           Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
  890 03:56:29.247010  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  891 03:56:29.288575  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  892 03:56:29.316217  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  893 03:56:29.345993  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  894 03:56:29.521480  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
  895 03:56:29.952420  [[0;32m  OK  [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
  896 03:56:29.980069  [[0;32m  OK  [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
  897 03:56:30.000352  [[0;32m  OK  [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
  898 03:56:30.018422  [[0;32m  OK  [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
  899 03:56:30.139022  [[0;32m  OK  [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
  900 03:56:30.317809  [[0;32m  OK  [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
  901 03:56:30.341482  [[0;32m  OK  [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
  902 03:56:30.416850  [[0;32m  OK  [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
  903 03:56:30.491014  [[0;32m  OK  [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
  904 03:56:30.509222  [[0;32m  OK  [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
  905 03:56:30.534801  [[0;32m  OK  [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
  906 03:56:30.564555  [[0;32m  OK  [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
  907 03:56:30.585977  [[0;32m  OK  [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
  908 03:56:30.650936           Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
  909 03:56:30.688830           Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
  910 03:56:30.877755           Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
  911 03:56:31.027607           Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
  912 03:56:31.107920           Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
  913 03:56:31.149525  [[0;32m  OK  [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
  914 03:56:31.169702  [[0;32m  OK  [0m] Reached target [0;1;39msound.target[0m - Sound Card.
  915 03:56:31.186675  [[0;32m  OK  [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
  916 03:56:31.551887           Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
  917 03:56:31.581722  [[0;32m  OK  [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
  918 03:56:31.668359  [[0;32m  OK  [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
  919 03:56:31.740439  [[0;32m  OK  [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
  920 03:56:31.767896  [[0;32m  OK  [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
  921 03:56:31.846291  [[0;32m  OK  [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
  922 03:56:32.196809  [[0;32m  OK  [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
  923 03:56:32.490311  [[0;32m  OK  [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
  924 03:56:32.534698  [[0;32m  OK  [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
  925 03:56:32.562424  [[0;32m  OK  [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
  926 03:56:32.655873           Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
  927 03:56:32.876417  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
  928 03:56:33.091918  
  929 03:56:33.092306  Debian GNU/Linux 12 debian-bookworm-armhf ttyS0
  930 03:56:33.092620  
  931 03:56:33.098515  debian-bookworm-armhlogin: root (automatic login)
  932 03:56:33.098907  
  933 03:56:33.459257  Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Mon Nov  4 02:59:56 UTC 2024 armv7l
  934 03:56:33.459648  
  935 03:56:33.465301  The programs included with the Debian GNU/Linux system are free software;
  936 03:56:33.472825  the exact distribution terms for each program are described in the
  937 03:56:33.473215  individual files in /usr/share/doc/*/copyright.
  938 03:56:33.473530  
  939 03:56:33.478863  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
  940 03:56:33.483206  permitted by applicable law.
  941 03:56:38.324698  Unable to match end of the kernel message
  943 03:56:38.325740  Setting prompt string to ['/ #']
  944 03:56:38.326165  end: 2.4.4.1 login-action (duration 00:00:47) [common]
  946 03:56:38.327107  end: 2.4.4 auto-login-action (duration 00:00:48) [common]
  947 03:56:38.327521  start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
  948 03:56:38.327866  Setting prompt string to ['/ #']
  949 03:56:38.328164  Forcing a shell prompt, looking for ['/ #']
  951 03:56:38.378887  / # 
  952 03:56:38.379464  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
  953 03:56:38.379906  Waiting using forced prompt support (timeout 00:02:30)
  954 03:56:38.386605  
  955 03:56:38.393486  end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
  956 03:56:38.393961  start: 2.4.6 export-device-env (timeout 00:03:11) [common]
  957 03:56:38.394332  Sending with 10 millisecond of delay
  959 03:56:43.451765  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1216052/extract-nfsrootfs-t70l5rdy'
  960 03:56:43.462447  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1216052/extract-nfsrootfs-t70l5rdy'
  961 03:56:43.465557  Sending with 10 millisecond of delay
  963 03:56:45.506768  / # export NFS_SERVER_IP='172.16.3.3'
  964 03:56:45.517435  export NFS_SERVER_IP='172.16.3.3'
  965 03:56:45.520888  end: 2.4.6 export-device-env (duration 00:00:07) [common]
  966 03:56:45.521368  end: 2.4 uboot-commands (duration 00:01:56) [common]
  967 03:56:45.521813  end: 2 uboot-action (duration 00:01:56) [common]
  968 03:56:45.522244  start: 3 lava-test-retry (timeout 00:06:45) [common]
  969 03:56:45.522691  start: 3.1 lava-test-shell (timeout 00:06:45) [common]
  970 03:56:45.523044  Using namespace: common
  972 03:56:45.623964  / # #
  973 03:56:45.624469  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
  974 03:56:45.631794  #
  975 03:56:45.637664  Using /lava-1216052
  977 03:56:45.738633  / # export SHELL=/bin/bash
  978 03:56:45.745819  export SHELL=/bin/bash
  980 03:56:45.853406  / # . /lava-1216052/environment
  981 03:56:45.861042  . /lava-1216052/environment
  983 03:56:45.974950  / # /lava-1216052/bin/lava-test-runner /lava-1216052/0
  984 03:56:45.975465  Test shell timeout: 10s (minimum of the action and connection timeout)
  985 03:56:45.982820  /lava-1216052/bin/lava-test-runner /lava-1216052/0
  986 03:56:46.569732  + export TESTRUN_ID=0_timesync-off
  987 03:56:46.577785  + TESTRUN_ID=0_timesync-off
  988 03:56:46.578176  + cd /lava-1216052/0/tests/0_timesync-off
  989 03:56:46.578520  ++ cat uuid
  990 03:56:46.596988  + UUID=1216052_1.6.2.4.1
  991 03:56:46.597391  + set +x
  992 03:56:46.601816  <LAVA_SIGNAL_STARTRUN 0_timesync-off 1216052_1.6.2.4.1>
  993 03:56:46.602474  Received signal: <STARTRUN> 0_timesync-off 1216052_1.6.2.4.1
  994 03:56:46.602810  Starting test lava.0_timesync-off (1216052_1.6.2.4.1)
  995 03:56:46.603193  Skipping test definition patterns.
  996 03:56:46.605095  + systemctl stop systemd-timesyncd
  997 03:56:46.889978  + set +x
  998 03:56:46.890599  Received signal: <ENDRUN> 0_timesync-off 1216052_1.6.2.4.1
  999 03:56:46.890993  Ending use of test pattern.
 1000 03:56:46.891302  Ending test lava.0_timesync-off (1216052_1.6.2.4.1), duration 0.29
 1002 03:56:46.894227  <LAVA_SIGNAL_ENDRUN 0_timesync-off 1216052_1.6.2.4.1>
 1003 03:56:47.212035  + export TESTRUN_ID=1_kselftest-dt
 1004 03:56:47.219917  + TESTRUN_ID=1_kselftest-dt
 1005 03:56:47.220324  + cd /lava-1216052/0/tests/1_kselftest-dt
 1006 03:56:47.220645  ++ cat uuid
 1007 03:56:47.238991  + UUID=1216052_1.6.2.4.5
 1008 03:56:47.239383  + set +x
 1009 03:56:47.245073  <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1216052_1.6.2.4.5>
 1010 03:56:47.245484  + cd ./automated/linux/kselftest/
 1011 03:56:47.246063  Received signal: <STARTRUN> 1_kselftest-dt 1216052_1.6.2.4.5
 1012 03:56:47.246410  Starting test lava.1_kselftest-dt (1216052_1.6.2.4.5)
 1013 03:56:47.246808  Skipping test definition patterns.
 1014 03:56:47.271339  + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
 1015 03:56:47.428167  INFO: install_deps skipped
 1016 03:56:48.189259  --2024-01-26 21:49:17--  http://storage.kernelci.org/mainline/master/v6.12-rc6/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
 1017 03:56:48.233635  Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
 1018 03:56:48.394377  Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
 1019 03:56:48.549493  HTTP request sent, awaiting response... 200 OK
 1020 03:56:48.549881  Length: 2542484 (2.4M) [application/octet-stream]
 1021 03:56:48.555577  Saving to: 'kselftest_armhf.tar.gz'
 1022 03:56:48.555962  
 1023 03:56:50.162572  kselftest_armhf.tar   0%[                    ]       0  --.-KB/s               kselftest_armhf.tar   2%[                    ]  49.92K   161KB/s               kselftest_armhf.tar   7%[>                   ] 194.76K   312KB/s               kselftest_armhf.tar  22%[===>                ] 563.85K   682KB/s               kselftest_armhf.tar  26%[====>               ] 665.85K   588KB/s               kselftest_armhf.tar  77%[==============>     ]   1.88M  1.41MB/s               kselftest_armhf.tar  89%[================>   ]   2.17M  1.39MB/s               kselftest_armhf.tar 100%[===================>]   2.42M  1.51MB/s    in 1.6s    
 1024 03:56:50.163009  
 1025 03:56:50.717967  2024-01-26 21:49:19 (1.51 MB/s) - 'kselftest_armhf.tar.gz' saved [2542484/2542484]
 1026 03:56:50.718424  
 1027 03:56:51.005264  tar: ./nsfs/pidns: time stamp 2024-11-04 03:13:12 is 24384231.874095995 s in the future
 1028 03:56:51.136568  tar: ./nsfs/config: time stamp 2024-10-27 19:28:30 is 23751549.741136037 s in the future
 1029 03:56:51.261375  tar: ./nsfs/owner: time stamp 2024-11-04 03:13:12 is 24384231.615579662 s in the future
 1030 03:56:51.394520  tar: ./nsfs: time stamp 2024-11-04 03:13:54 is 24384273.482018787 s in the future
 1031 03:56:51.553297  tar: ./cachestat/test_cachestat: time stamp 2024-11-04 03:12:10 is 24384169.323988412 s in the future
 1032 03:56:51.611608  tar: ./cachestat: time stamp 2024-11-04 03:13:44 is 24384263.265516787 s in the future
 1033 03:56:51.771277  tar: ./kselftest/prefix.pl: time stamp 2024-11-04 03:13:44 is 24384263.106676912 s in the future
 1034 03:56:51.880577  tar: ./kselftest/ktap_helpers.sh: time stamp 2024-10-27 19:28:30 is 23751548.998174495 s in the future
 1035 03:56:52.014108  tar: ./kselftest/runner.sh: time stamp 2024-11-04 03:13:44 is 24384262.865020162 s in the future
 1036 03:56:52.139123  tar: ./kselftest/ksft.py: time stamp 2024-11-04 03:13:44 is 24384262.739661495 s in the future
 1037 03:56:52.255496  tar: ./kselftest/module.sh: time stamp 2024-11-04 03:13:44 is 24384262.622933328 s in the future
 1038 03:56:52.305350  tar: ./kselftest: time stamp 2024-10-27 19:28:30 is 23751548.572805412 s in the future
 1039 03:56:52.464189  tar: ./cpufreq/governor.sh: time stamp 2024-10-27 19:28:30 is 23751548.414787912 s in the future
 1040 03:56:52.596338  tar: ./cpufreq/config: time stamp 2024-10-27 19:28:30 is 23751548.281215995 s in the future
 1041 03:56:52.705300  tar: ./cpufreq/cpufreq.sh: time stamp 2024-10-27 19:28:30 is 23751548.17290562 s in the future
 1042 03:56:52.823123  tar: ./cpufreq/special-tests.sh: time stamp 2024-10-27 19:28:30 is 23751548.055831912 s in the future
 1043 03:56:52.938449  tar: ./cpufreq/module.sh: time stamp 2024-10-27 19:28:30 is 23751547.939686828 s in the future
 1044 03:56:53.064514  tar: ./cpufreq/cpu.sh: time stamp 2024-10-27 19:28:30 is 23751547.81417712 s in the future
 1045 03:56:53.196898  tar: ./cpufreq/main.sh: time stamp 2024-10-27 19:28:30 is 23751547.680908078 s in the future
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 1097 03:56:59.631174  tar: ./net/netfilter/conntrack_reverse_clash: time stamp 2024-11-04 03:13:04 is 24384215.249180203 s in the future
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 1099 03:56:59.871565  tar: ./net/netfilter/nft_tproxy_udp.sh: time stamp 2024-10-27 19:28:30 is 23751541.007365411 s in the future
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 1130 03:57:03.909326  tar: ./net/tcp_ao/self-connect_ipv4: time stamp 2024-11-04 03:13:08 is 24384214.969078577 s in the future
 1131 03:57:04.075269  tar: ./net/tcp_ao/restore_ipv4: time stamp 2024-11-04 03:13:07 is 24384213.802334827 s in the future
 1132 03:57:04.267827  tar: ./net/tcp_ao/icmps-discard_ipv6: time stamp 2024-11-04 03:13:10 is 24384216.610381827 s in the future
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 1139 03:57:05.534759  tar: ./net/tcp_ao/seq-ext_ipv4: time stamp 2024-11-04 03:13:08 is 24384213.34317791 s in the future
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 1150 03:57:07.567679  tar: ./net/tcp_ao/icmps-accept_ipv4: time stamp 2024-11-04 03:13:06 is 24384209.310338952 s in the future
 1151 03:57:07.761260  tar: ./net/tcp_ao/setsockopt-closed_ipv6: time stamp 2024-11-04 03:13:11 is 24384214.116722535 s in the future
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 1158 03:57:08.755653  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-2pkt-send-5pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751532.125798368 s in the future
 1159 03:57:08.888184  tar: ./net/packetdrill/tcp_zerocopy_client.pkt: time stamp 2024-10-27 19:28:30 is 23751531.99161991 s in the future
 1160 03:57:09.014330  tar: ./net/packetdrill/tcp_zerocopy_fastopen-client.pkt: time stamp 2024-10-27 19:28:30 is 23751531.865632535 s in the future
 1161 03:57:09.138215  tar: ./net/packetdrill/defaults.sh: time stamp 2024-10-27 19:28:30 is 23751531.740315493 s in the future
 1162 03:57:09.256283  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-2pkt-send-6pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751531.624885743 s in the future
 1163 03:57:09.380642  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-4pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751531.50046966 s in the future
 1164 03:57:09.514277  tar: ./net/packetdrill/tcp_zerocopy_epoll_oneshot.pkt: time stamp 2024-10-27 19:28:30 is 23751531.365112618 s in the future
 1165 03:57:09.632366  tar: ./net/packetdrill/tcp_md5_md5-only-on-client-ack.pkt: time stamp 2024-10-27 19:28:30 is 23751531.248377326 s in the future
 1166 03:57:09.750281  tar: ./net/packetdrill/tcp_slow_start_slow-start-app-limited-9-packets-out.pkt: time stamp 2024-10-27 19:28:30 is 23751531.131460118 s in the future
 1167 03:57:09.865101  tar: ./net/packetdrill/tcp_slow_start_slow-start-fq-ack-per-2pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751531.016666368 s in the future
 1168 03:57:09.989215  tar: ./net/packetdrill/tcp_zerocopy_maxfrags.pkt: time stamp 2024-10-27 19:28:30 is 23751530.889619868 s in the future
 1169 03:57:10.121584  tar: ./net/packetdrill/config: time stamp 2024-10-27 19:28:30 is 23751530.755906368 s in the future
 1170 03:57:10.252265  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-1pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751530.630739243 s in the future
 1171 03:57:10.363772  tar: ./net/packetdrill/tcp_zerocopy_fastopen-server.pkt: time stamp 2024-10-27 19:28:30 is 23751530.516253826 s in the future
 1172 03:57:10.509299  tar: ./net/packetdrill/tcp_slow_start_slow-start-after-win-update.pkt: time stamp 2024-10-27 19:28:30 is 23751530.372071076 s in the future
 1173 03:57:10.633800  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-2pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751530.247266618 s in the future
 1174 03:57:10.757913  tar: ./net/packetdrill/tcp_zerocopy_closed.pkt: time stamp 2024-10-27 19:28:30 is 23751530.121768743 s in the future
 1175 03:57:10.888264  tar: ./net/packetdrill/set_sysctls.py: time stamp 2024-10-27 19:28:30 is 23751529.990744743 s in the future
 1176 03:57:11.026216  tar: ./net/packetdrill/tcp_slow_start_slow-start-after-idle.pkt: time stamp 2024-10-27 19:28:30 is 23751529.85508741 s in the future
 1177 03:57:11.139550  tar: ./net/packetdrill/ksft_runner.sh: time stamp 2024-10-27 19:28:30 is 23751529.738330118 s in the future
 1178 03:57:11.284080  tar: ./net/packetdrill/tcp_slow_start_slow-start-app-limited.pkt: time stamp 2024-10-27 19:28:30 is 23751529.596486659 s in the future
 1179 03:57:11.438748  tar: ./net/packetdrill/tcp_zerocopy_small.pkt: time stamp 2024-10-27 19:28:30 is 23751529.440336159 s in the future
 1180 03:57:11.582956  tar: ./net/packetdrill/tcp_zerocopy_batch.pkt: time stamp 2024-10-27 19:28:30 is 23751529.296252826 s in the future
 1181 03:57:11.699836  tar: ./net/packetdrill/tcp_inq_client.pkt: time stamp 2024-10-27 19:28:30 is 23751529.179549701 s in the future
 1182 03:57:11.891570  tar: ./net/packetdrill/tcp_zerocopy_epoll_edge.pkt: time stamp 2024-10-27 19:28:30 is 23751528.987628534 s in the future
 1183 03:57:12.023130  tar: ./net/packetdrill/tcp_zerocopy_epoll_exclusive.pkt: time stamp 2024-10-27 19:28:30 is 23751528.856479243 s in the future
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 2026 03:59:00.035020  tar: ./gpio/gpio-mockup-sysfs.sh: time stamp 2024-10-27 19:28:30 is 23751420.83719273 s in the future
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 2029 03:59:00.440161  tar: ./gpio/gpio-sim.sh: time stamp 2024-10-27 19:28:30 is 23751420.430985438 s in the future
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 2063 03:59:04.896349  tar: ./tpm2/test_smoke.sh: time stamp 2024-10-27 19:28:30 is 23751415.975698188 s in the future
 2064 03:59:05.024457  tar: ./tpm2/settings: time stamp 2024-10-27 19:28:30 is 23751415.846407771 s in the future
 2065 03:59:05.178956  tar: ./tpm2/test_space.sh: time stamp 2024-10-27 19:28:30 is 23751415.691990688 s in the future
 2066 03:59:05.234143  tar: ./tpm2: time stamp 2024-11-04 03:13:57 is 24384142.635983354 s in the future
 2067 03:59:05.407395  tar: ./ptrace/vmaccess: time stamp 2024-11-04 03:13:17 is 24384102.462996646 s in the future
 2068 03:59:05.534521  tar: ./ptrace/get_set_sud: time stamp 2024-11-04 03:13:17 is 24384102.336022396 s in the future
 2069 03:59:05.661607  tar: ./ptrace/peeksiginfo: time stamp 2024-11-04 03:13:17 is 24384102.209888813 s in the future
 2070 03:59:05.802358  tar: ./ptrace/get_syscall_info: time stamp 2024-11-04 03:13:17 is 24384102.068880188 s in the future
 2071 03:59:05.878723  tar: ./ptrace: time stamp 2024-11-04 03:13:54 is 24384138.991520312 s in the future
 2072 03:59:06.035394  tar: ./syscall_user_dispatch/sud_benchmark: time stamp 2024-11-04 03:13:24 is 24384108.837108312 s in the future
 2073 03:59:06.163263  tar: ./syscall_user_dispatch/config: time stamp 2024-10-27 19:28:30 is 23751414.707967396 s in the future
 2074 03:59:06.317939  tar: ./syscall_user_dispatch/sud_test: time stamp 2024-11-04 03:13:24 is 24384108.553931479 s in the future
 2075 03:59:06.377599  tar: ./syscall_user_dispatch: time stamp 2024-11-04 03:13:57 is 24384141.493631479 s in the future
 2076 03:59:06.607069  tar: ./resctrl/resctrl_tests: time stamp 2024-11-04 03:13:19 is 24384103.264985146 s in the future
 2077 03:59:06.742474  tar: ./resctrl/config: time stamp 2024-10-27 19:28:30 is 23751414.128316979 s in the future
 2078 03:59:06.886605  tar: ./resctrl/settings: time stamp 2024-10-27 19:28:30 is 23751413.983960646 s in the future
 2079 03:59:06.960924  tar: ./resctrl: time stamp 2024-11-04 03:13:55 is 24384138.910025604 s in the future
 2080 03:59:07.126188  tar: ./proc/setns-sysvipc: time stamp 2024-11-04 03:13:16 is 24384099.745206687 s in the future
 2081 03:59:07.250042  tar: ./proc/read: time stamp 2024-11-04 03:13:16 is 24384099.619640521 s in the future
 2082 03:59:07.379169  tar: ./proc/proc-subset-pid: time stamp 2024-11-04 03:13:15 is 24384098.491429937 s in the future
 2083 03:59:07.505144  tar: ./proc/proc-loadavg-001: time stamp 2024-11-04 03:13:15 is 24384098.366874604 s in the future
 2084 03:59:07.644240  tar: ./proc/proc-self-map-files-002: time stamp 2024-11-04 03:13:15 is 24384098.227672562 s in the future
 2085 03:59:07.777654  tar: ./proc/proc-empty-vm: time stamp 2024-11-04 03:13:15 is 24384098.093903104 s in the future
 2086 03:59:07.926879  tar: ./proc/proc-tid0: time stamp 2024-11-04 03:13:16 is 24384098.944254521 s in the future
 2087 03:59:08.062252  tar: ./proc/proc-pid-vm: time stamp 2024-11-04 03:13:15 is 24384097.807863896 s in the future
 2088 03:59:08.190243  tar: ./proc/proc-self-isnt-kthread: time stamp 2024-11-04 03:13:15 is 24384097.680864771 s in the future
 2089 03:59:08.340760  tar: ./proc/proc-2-is-kthread: time stamp 2024-11-04 03:13:14 is 24384096.534951271 s in the future
 2090 03:59:08.465648  tar: ./proc/proc-uptime-001: time stamp 2024-11-04 03:13:16 is 24384098.405915979 s in the future
 2091 03:59:08.599222  tar: ./proc/proc-uptime-002: time stamp 2024-11-04 03:13:16 is 24384098.272039521 s in the future
 2092 03:59:08.737941  tar: ./proc/proc-self-syscall: time stamp 2024-11-04 03:13:15 is 24384097.133832354 s in the future
 2093 03:59:08.858729  tar: ./proc/proc-multiple-procfs: time stamp 2024-11-04 03:13:17 is 24384099.013154437 s in the future
 2094 03:59:08.990995  tar: ./proc/config: time stamp 2024-10-27 19:28:30 is 23751411.879684562 s in the future
 2095 03:59:09.124474  tar: ./proc/thread-self: time stamp 2024-11-04 03:13:16 is 24384097.746783687 s in the future
 2096 03:59:09.274986  tar: ./proc/setns-dcache: time stamp 2024-11-04 03:13:16 is 24384097.596680895 s in the future
 2097 03:59:09.417757  tar: ./proc/proc-self-map-files-001: time stamp 2024-11-04 03:13:15 is 24384096.454365729 s in the future
 2098 03:59:09.591364  tar: ./proc/proc-self-wchan: time stamp 2024-11-04 03:13:15 is 24384096.279192604 s in the future
 2099 03:59:09.733307  tar: ./proc/proc-fsconfig-hidepid: time stamp 2024-11-04 03:13:17 is 24384098.138058145 s in the future
 2100 03:59:09.872230  tar: ./proc/fd-002-posix-eq: time stamp 2024-11-04 03:13:14 is 24384094.999861437 s in the future
 2101 03:59:10.008540  tar: ./proc/fd-001-lookup: time stamp 2024-11-04 03:13:14 is 24384094.862264104 s in the future
 2102 03:59:10.158767  tar: ./proc/fd-003-kthread: time stamp 2024-11-04 03:13:14 is 24384094.712309437 s in the future
 2103 03:59:10.307965  tar: ./proc/self: time stamp 2024-11-04 03:13:16 is 24384096.562531354 s in the future
 2104 03:59:10.381028  tar: ./proc: time stamp 2024-11-04 03:13:54 is 24384134.489118145 s in the future
 2105 03:59:10.580090  tar: ./core/close_range_test: time stamp 2024-11-04 03:12:13 is 24384033.291557104 s in the future
 2106 03:59:10.721936  tar: ./core/unshare_test: time stamp 2024-11-04 03:12:14 is 24384034.149365604 s in the future
 2107 03:59:10.780220  tar: ./core: time stamp 2024-11-04 03:13:45 is 24384125.088978604 s in the future
 2108 03:59:10.916630  tar: ./run_kselftest.sh: time stamp 2024-11-04 03:13:44 is 24384123.953764604 s in the future
 2109 03:59:11.106230  tar: ./futex/functional/futex_wait: time stamp 2024-11-04 03:12:37 is 24384056.766556937 s in the future
 2110 03:59:11.230214  tar: ./futex/functional/run.sh: time stamp 2024-10-27 19:28:30 is 23751409.640847979 s in the future
 2111 03:59:11.376436  tar: ./futex/functional/futex_wait_private_mapped_file: time stamp 2024-11-04 03:12:37 is 24384056.496720937 s in the future
 2112 03:59:11.520579  tar: ./futex/functional/futex_wait_wouldblock: time stamp 2024-11-04 03:12:36 is 24384055.352627728 s in the future
 2113 03:59:11.664602  tar: ./futex/functional/futex_wait_timeout: time stamp 2024-11-04 03:12:36 is 24384055.207638312 s in the future
 2114 03:59:11.809087  tar: ./futex/functional/futex_wait_uninitialized_heap: time stamp 2024-11-04 03:12:36 is 24384055.065122478 s in the future
 2115 03:59:11.950972  tar: ./futex/functional/futex_requeue: time stamp 2024-11-04 03:12:37 is 24384055.921058645 s in the future
 2116 03:59:12.096204  tar: ./futex/functional/futex_requeue_pi_signal_restart: time stamp 2024-11-04 03:12:36 is 24384054.777151728 s in the future
 2117 03:59:12.256201  tar: ./futex/functional/futex_waitv: time stamp 2024-11-04 03:12:37 is 24384055.615505812 s in the future
 2118 03:59:12.387593  tar: ./futex/functional/futex_requeue_pi_mismatched_ops: time stamp 2024-11-04 03:12:36 is 24384054.485459062 s in the future
 2119 03:59:12.534948  tar: ./futex/functional/futex_requeue_pi: time stamp 2024-11-04 03:12:36 is 24384054.337354478 s in the future
 2120 03:59:12.584534  tar: ./futex/functional: time stamp 2024-11-04 03:13:48 is 24384126.285636103 s in the future
 2121 03:59:12.730564  tar: ./futex/run.sh: time stamp 2024-11-04 03:13:48 is 24384126.139357062 s in the future
 2122 03:59:12.797258  tar: ./futex: time stamp 2024-11-04 03:13:48 is 24384126.072594228 s in the future
 2123 03:59:12.864055  tar: .: time stamp 2024-11-04 03:14:00 is 24384138.006019353 s in the future
 2124 03:59:13.147824  skiplist:
 2125 03:59:13.148212  ========================================
 2126 03:59:13.153323  ========================================
 2127 03:59:13.475871  dt:test_unprobed_devices.sh
 2128 03:59:13.594855  ============== Tests to run ===============
 2129 03:59:13.616001  dt:test_unprobed_devices.sh
 2130 03:59:13.620329  ===========End Tests to run ===============
 2131 03:59:13.653323  shardfile-dt pass
 2132 03:59:14.000484  <12>[  202.336646] kselftest: Running tests in dt
 2133 03:59:14.031168  TAP version 13
 2134 03:59:14.056958  1..1
 2135 03:59:14.114997  # timeout set to 45
 2136 03:59:14.115383  # selftests: dt: test_unprobed_devices.sh
 2137 03:59:14.896343  # TAP version 13
 2138 03:59:41.169627  # 1..257
 2139 03:59:41.353957  # ok 1 / # SKIP
 2140 03:59:41.377832  # ok 2 /clk_mcasp0
 2141 03:59:41.451710  # ok 3 /clk_mcasp0_fixed # SKIP
 2142 03:59:41.523104  # ok 4 /cpus/cpu@0 # SKIP
 2143 03:59:41.600097  # ok 5 /cpus/idle-states/mpu_gate # SKIP
 2144 03:59:41.626214  # ok 6 /fixedregulator0
 2145 03:59:41.642301  # ok 7 /leds
 2146 03:59:41.669053  # ok 8 /ocp
 2147 03:59:41.697008  # ok 9 /ocp/interconnect@44c00000
 2148 03:59:41.721264  # ok 10 /ocp/interconnect@44c00000/segment@0
 2149 03:59:41.743862  # ok 11 /ocp/interconnect@44c00000/segment@100000
 2150 03:59:41.766184  # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
 2151 03:59:41.845533  # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
 2152 03:59:41.864596  # ok 14 /ocp/interconnect@44c00000/segment@200000
 2153 03:59:41.890434  # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
 2154 03:59:42.002802  # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
 2155 03:59:42.081240  # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
 2156 03:59:42.159731  # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
 2157 03:59:42.236324  # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
 2158 03:59:42.314285  # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
 2159 03:59:42.390736  # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
 2160 03:59:42.468670  # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
 2161 03:59:42.545163  # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
 2162 03:59:42.622915  # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
 2163 03:59:42.700661  # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
 2164 03:59:42.781261  # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
 2165 03:59:42.854647  # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
 2166 03:59:42.933678  # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
 2167 03:59:43.010025  # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
 2168 03:59:43.085425  # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
 2169 03:59:43.163362  # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
 2170 03:59:43.240060  # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
 2171 03:59:43.319007  # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
 2172 03:59:43.394530  # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
 2173 03:59:43.473128  # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
 2174 03:59:43.549764  # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
 2175 03:59:43.632950  # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
 2176 03:59:43.705560  # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
 2177 03:59:43.783537  # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
 2178 03:59:43.861676  # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
 2179 03:59:43.938685  # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
 2180 03:59:44.015287  # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
 2181 03:59:44.094269  # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
 2182 03:59:44.172156  # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
 2183 03:59:44.248961  # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
 2184 03:59:44.326628  # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
 2185 03:59:44.407890  # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
 2186 03:59:44.483672  # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
 2187 03:59:44.561222  # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
 2188 03:59:44.640664  # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
 2189 03:59:44.765993  # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
 2190 03:59:44.796520  # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
 2191 03:59:44.874492  # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
 2192 03:59:44.952475  # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
 2193 03:59:45.029247  # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
 2194 03:59:45.112681  # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
 2195 03:59:45.185139  # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
 2196 03:59:45.261924  # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
 2197 03:59:45.340775  # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
 2198 03:59:45.423789  # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
 2199 03:59:45.496239  # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
 2200 03:59:45.574256  # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
 2201 03:59:45.650905  # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
 2202 03:59:45.733917  # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
 2203 03:59:45.807410  # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
 2204 03:59:45.887274  # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
 2205 03:59:45.963156  # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
 2206 03:59:46.040881  # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
 2207 03:59:46.117667  # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
 2208 03:59:46.195483  # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
 2209 03:59:46.273243  # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
 2210 03:59:46.351077  # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
 2211 03:59:46.433078  # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
 2212 03:59:46.506916  # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
 2213 03:59:46.586026  # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
 2214 03:59:46.662783  # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
 2215 03:59:46.740630  # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
 2216 03:59:46.817271  # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
 2217 03:59:46.893756  # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
 2218 03:59:46.973767  # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
 2219 03:59:47.050424  # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
 2220 03:59:47.131778  # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
 2221 03:59:47.204381  # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
 2222 03:59:47.281973  # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
 2223 03:59:47.359793  # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
 2224 03:59:47.437771  # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
 2225 03:59:47.513024  # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
 2226 03:59:47.591843  # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
 2227 03:59:47.672031  # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
 2228 03:59:47.750032  # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
 2229 03:59:47.825499  # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
 2230 03:59:47.905646  # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
 2231 03:59:47.983635  # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
 2232 03:59:48.062767  # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
 2233 03:59:48.084631  # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
 2234 03:59:48.109585  # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
 2235 03:59:48.134651  # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
 2236 03:59:48.160635  # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
 2237 03:59:48.189880  # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
 2238 03:59:48.211372  # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
 2239 03:59:48.240495  # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
 2240 03:59:48.259881  # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
 2241 03:59:48.375456  # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
 2242 03:59:48.400120  # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
 2243 03:59:48.426285  # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
 2244 03:59:48.450983  # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
 2245 03:59:48.565452  # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
 2246 03:59:48.645635  # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
 2247 03:59:48.724581  # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
 2248 03:59:48.802636  # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
 2249 03:59:48.883997  # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
 2250 03:59:48.964256  # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
 2251 03:59:49.038006  # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
 2252 03:59:49.114901  # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
 2253 03:59:49.194267  # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
 2254 03:59:49.272135  # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
 2255 03:59:49.350241  # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
 2256 03:59:49.428283  # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
 2257 03:59:49.507553  # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
 2258 03:59:49.584951  # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
 2259 03:59:49.665073  # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
 2260 03:59:49.743110  # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
 2261 03:59:49.770391  # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
 2262 03:59:49.842991  # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
 2263 03:59:49.918191  # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
 2264 03:59:50.001201  # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
 2265 03:59:50.023861  # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
 2266 03:59:50.097130  # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
 2267 03:59:50.124874  # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
 2268 03:59:50.199236  # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
 2269 03:59:50.221747  # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
 2270 03:59:50.252693  # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
 2271 03:59:50.274055  # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
 2272 03:59:50.298876  # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
 2273 03:59:50.324734  # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
 2274 03:59:50.349608  # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
 2275 03:59:50.375458  # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
 2276 03:59:50.455618  # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
 2277 03:59:50.478103  # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
 2278 03:59:50.503099  # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
 2279 03:59:50.579853  # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
 2280 03:59:50.657604  # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
 2281 03:59:50.680117  # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
 2282 03:59:50.789745  # not ok 144 /ocp/interconnect@47c00000
 2283 03:59:50.870801  # not ok 145 /ocp/interconnect@47c00000/segment@0
 2284 03:59:50.890853  # ok 146 /ocp/interconnect@48000000
 2285 03:59:50.915106  # ok 147 /ocp/interconnect@48000000/segment@0
 2286 03:59:50.943990  # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
 2287 03:59:50.965999  # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
 2288 03:59:50.990617  # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
 2289 03:59:51.015088  # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
 2290 03:59:51.043857  # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
 2291 03:59:51.066334  # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
 2292 03:59:51.090972  # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
 2293 03:59:51.172882  # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
 2294 03:59:51.246091  # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
 2295 03:59:51.272914  # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
 2296 03:59:51.298724  # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
 2297 03:59:51.323349  # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
 2298 03:59:51.347966  # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
 2299 03:59:51.367845  # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
 2300 03:59:51.394818  # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
 2301 03:59:51.422922  # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
 2302 03:59:51.444552  # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
 2303 03:59:51.472412  # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
 2304 03:59:51.494976  # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
 2305 03:59:51.521978  # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
 2306 03:59:51.544225  # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
 2307 03:59:51.567977  # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
 2308 03:59:51.594725  # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
 2309 03:59:51.617223  # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
 2310 03:59:51.642920  # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
 2311 03:59:51.671726  # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
 2312 03:59:51.694044  # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
 2313 03:59:51.715103  # ok 175 /ocp/interconnect@48000000/segment@100000
 2314 03:59:51.744093  # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
 2315 03:59:51.768597  # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
 2316 03:59:51.853214  # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
 2317 03:59:51.927982  # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
 2318 03:59:52.003804  # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
 2319 03:59:52.082945  # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
 2320 03:59:52.157580  # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
 2321 03:59:52.237439  # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
 2322 03:59:52.316175  # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
 2323 03:59:52.393218  # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
 2324 03:59:52.418075  # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
 2325 03:59:52.443785  # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
 2326 03:59:52.469600  # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
 2327 03:59:52.494215  # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
 2328 03:59:52.516567  # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
 2329 03:59:52.542171  # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
 2330 03:59:52.566588  # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
 2331 03:59:52.592289  # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
 2332 03:59:52.616727  # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
 2333 03:59:52.644547  # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
 2334 03:59:52.666088  # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
 2335 03:59:52.691802  # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
 2336 03:59:52.718484  # ok 198 /ocp/interconnect@48000000/segment@200000
 2337 03:59:52.743326  # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
 2338 03:59:52.818543  # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
 2339 03:59:52.841970  # ok 201 /ocp/interconnect@48000000/segment@300000
 2340 03:59:52.866208  # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
 2341 03:59:52.891922  # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
 2342 03:59:52.920903  # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
 2343 03:59:52.944550  # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
 2344 03:59:52.965954  # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
 2345 03:59:52.993958  # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
 2346 03:59:53.070179  # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
 2347 03:59:53.089116  # ok 209 /ocp/interconnect@4a000000
 2348 03:59:53.115325  # ok 210 /ocp/interconnect@4a000000/segment@0
 2349 03:59:53.142082  # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
 2350 03:59:53.173183  # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
 2351 03:59:53.195077  # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
 2352 03:59:53.222911  # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
 2353 03:59:53.299119  # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
 2354 03:59:53.412949  # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
 2355 03:59:53.491832  # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
 2356 03:59:53.598094  # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
 2357 03:59:53.674838  # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
 2358 03:59:53.755576  # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
 2359 03:59:53.861281  # not ok 221 /ocp/interconnect@4b140000
 2360 03:59:53.935076  # not ok 222 /ocp/interconnect@4b140000/segment@0
 2361 03:59:54.013298  # ok 223 /ocp/interrupt-controller@48200000 # SKIP
 2362 03:59:54.039569  # ok 224 /ocp/target-module@40300000
 2363 03:59:54.060660  # ok 225 /ocp/target-module@40300000/sram@0
 2364 03:59:54.139193  # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
 2365 03:59:54.220936  # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
 2366 03:59:54.240851  # ok 228 /ocp/target-module@47400000
 2367 03:59:54.268280  # ok 229 /ocp/target-module@47400000/dma-controller@2000
 2368 03:59:54.292662  # ok 230 /ocp/target-module@47400000/usb-phy@1300
 2369 03:59:54.312766  # ok 231 /ocp/target-module@47400000/usb-phy@1b00
 2370 03:59:54.335841  # ok 232 /ocp/target-module@47400000/usb@1400
 2371 03:59:54.360304  # ok 233 /ocp/target-module@47400000/usb@1800
 2372 03:59:54.383000  # ok 234 /ocp/target-module@47810000
 2373 03:59:54.411536  # ok 235 /ocp/target-module@49000000
 2374 03:59:54.435910  # ok 236 /ocp/target-module@49000000/dma@0
 2375 03:59:54.459116  # ok 237 /ocp/target-module@49800000
 2376 03:59:54.481189  # ok 238 /ocp/target-module@49800000/dma@0
 2377 03:59:54.503284  # ok 239 /ocp/target-module@49900000
 2378 03:59:54.527545  # ok 240 /ocp/target-module@49900000/dma@0
 2379 03:59:54.551667  # ok 241 /ocp/target-module@49a00000
 2380 03:59:54.580282  # ok 242 /ocp/target-module@49a00000/dma@0
 2381 03:59:54.601394  # ok 243 /ocp/target-module@4c000000
 2382 03:59:54.676414  # not ok 244 /ocp/target-module@4c000000/emif@0
 2383 03:59:54.699428  # ok 245 /ocp/target-module@50000000
 2384 03:59:54.727688  # ok 246 /ocp/target-module@53100000
 2385 03:59:54.805991  # not ok 247 /ocp/target-module@53100000/sham@0
 2386 03:59:54.824599  # ok 248 /ocp/target-module@53500000
 2387 03:59:54.901737  # not ok 249 /ocp/target-module@53500000/aes@0
 2388 03:59:54.928114  # ok 250 /ocp/target-module@56000000
 2389 03:59:55.038902  # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
 2390 03:59:55.116649  # ok 252 /opp-table # SKIP
 2391 03:59:55.189006  # ok 253 /soc # SKIP
 2392 03:59:55.209777  # ok 254 /sound
 2393 03:59:55.241488  # ok 255 /target-module@4b000000
 2394 03:59:55.262533  # ok 256 /target-module@4b000000/target-module@140000
 2395 03:59:55.283788  # ok 257 /target-module@4b000000/target-module@140000/pmu@0
 2396 03:59:55.293366  # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
 2397 03:59:55.301358  not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
 2398 03:59:57.710851  dt_test_unprobed_devices_sh_ skip
 2399 03:59:57.716936  dt_test_unprobed_devices_sh_clk_mcasp0 pass
 2400 03:59:57.721806  dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
 2401 03:59:57.722194  dt_test_unprobed_devices_sh_cpus_cpu_0 skip
 2402 03:59:57.729261  dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
 2403 03:59:57.735580  dt_test_unprobed_devices_sh_fixedregulator0 pass
 2404 03:59:57.735966  dt_test_unprobed_devices_sh_leds pass
 2405 03:59:57.741596  dt_test_unprobed_devices_sh_ocp pass
 2406 03:59:57.746564  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
 2407 03:59:57.751463  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
 2408 03:59:57.757591  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
 2409 03:59:57.767576  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
 2410 03:59:57.771340  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
 2411 03:59:57.783591  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
 2412 03:59:57.788547  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
 2413 03:59:57.799778  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
 2414 03:59:57.809616  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
 2415 03:59:57.814527  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
 2416 03:59:57.825523  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
 2417 03:59:57.835405  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
 2418 03:59:57.846400  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
 2419 03:59:57.856269  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
 2420 03:59:57.867272  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
 2421 03:59:57.877160  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
 2422 03:59:57.888139  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
 2423 03:59:57.897869  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
 2424 03:59:57.909088  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
 2425 03:59:57.918900  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
 2426 03:59:57.929845  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
 2427 03:59:57.939654  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
 2428 03:59:57.945764  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
 2429 03:59:57.955752  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
 2430 03:59:57.966896  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
 2431 03:59:57.976636  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
 2432 03:59:57.986642  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
 2433 03:59:57.997625  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
 2434 03:59:58.008633  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
 2435 03:59:58.018389  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
 2436 03:59:58.028355  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
 2437 03:59:58.039641  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
 2438 03:59:58.050640  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
 2439 03:59:58.059380  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
 2440 03:59:58.069029  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
 2441 03:59:58.084885  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
 2442 03:59:58.096058  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
 2443 03:59:58.105861  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
 2444 03:59:58.116889  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
 2445 03:59:58.126777  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
 2446 03:59:58.137991  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
 2447 03:59:58.147766  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
 2448 03:59:58.158760  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
 2449 03:59:58.173496  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
 2450 03:59:58.184632  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
 2451 03:59:58.195589  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
 2452 03:59:58.205313  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
 2453 03:59:58.216390  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
 2454 03:59:58.226239  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
 2455 03:59:58.237343  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
 2456 03:59:58.247144  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
 2457 03:59:58.258395  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
 2458 03:59:58.273008  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
 2459 03:59:58.279144  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
 2460 03:59:58.293896  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
 2461 03:59:58.304934  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
 2462 03:59:58.314755  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
 2463 03:59:58.325872  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
 2464 03:59:58.335637  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
 2465 03:59:58.346892  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
 2466 03:59:58.356624  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
 2467 03:59:58.367774  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
 2468 03:59:58.377488  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
 2469 03:59:58.388611  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
 2470 03:59:58.398397  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
 2471 03:59:58.409613  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
 2472 03:59:58.425646  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
 2473 03:59:58.435388  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
 2474 03:59:58.446529  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
 2475 03:59:58.456223  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
 2476 03:59:58.466336  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
 2477 03:59:58.477582  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
 2478 03:59:58.488579  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
 2479 03:59:58.498378  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
 2480 03:59:58.509510  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
 2481 03:59:58.519142  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
 2482 03:59:58.530248  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
 2483 03:59:58.540014  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
 2484 03:59:58.551021  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
 2485 03:59:58.560756  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
 2486 03:59:58.571749  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
 2487 03:59:58.586519  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
 2488 03:59:58.592618  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
 2489 03:59:58.607311  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
 2490 03:59:58.618503  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
 2491 03:59:58.628359  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
 2492 03:59:58.639517  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
 2493 03:59:58.649337  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
 2494 03:59:58.654391  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
 2495 03:59:58.665622  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
 2496 03:59:58.675655  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
 2497 03:59:58.686625  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
 2498 03:59:58.697638  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
 2499 03:59:58.702639  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
 2500 03:59:58.712639  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
 2501 03:59:58.718632  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
 2502 03:59:58.732354  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
 2503 03:59:58.738639  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
 2504 03:59:58.749635  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
 2505 03:59:58.764619  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
 2506 03:59:58.775646  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
 2507 03:59:58.786884  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
 2508 03:59:58.796882  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
 2509 03:59:58.807881  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
 2510 03:59:58.824025  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
 2511 03:59:58.833979  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
 2512 03:59:58.845262  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
 2513 03:59:58.859891  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
 2514 03:59:58.871022  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
 2515 03:59:58.880902  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
 2516 03:59:58.891883  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
 2517 03:59:58.907764  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
 2518 03:59:58.917739  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
 2519 03:59:58.933625  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
 2520 03:59:58.942394  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
 2521 03:59:58.953600  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
 2522 03:59:58.964611  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
 2523 03:59:58.970765  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
 2524 03:59:58.980608  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
 2525 03:59:58.990629  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
 2526 03:59:58.995632  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
 2527 03:59:59.006633  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
 2528 03:59:59.012610  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
 2529 03:59:59.022497  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
 2530 03:59:59.033483  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
 2531 03:59:59.038376  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
 2532 03:59:59.048362  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
 2533 03:59:59.060726  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
 2534 03:59:59.070375  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
 2535 03:59:59.081251  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
 2536 03:59:59.092367  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
 2537 03:59:59.097280  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
 2538 03:59:59.107291  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
 2539 03:59:59.118373  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
 2540 03:59:59.128144  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
 2541 03:59:59.134379  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
 2542 03:59:59.139262  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
 2543 03:59:59.144128  dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
 2544 03:59:59.149035  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
 2545 03:59:59.160014  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
 2546 03:59:59.164875  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
 2547 03:59:59.176015  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
 2548 03:59:59.181026  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
 2549 03:59:59.190782  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
 2550 03:59:59.196861  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
 2551 03:59:59.206763  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
 2552 03:59:59.211626  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
 2553 03:59:59.222764  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
 2554 03:59:59.232504  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
 2555 03:59:59.238641  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
 2556 03:59:59.248375  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
 2557 03:59:59.253333  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
 2558 03:59:59.264380  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
 2559 03:59:59.274393  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
 2560 03:59:59.280500  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
 2561 03:59:59.285329  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
 2562 03:59:59.295133  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
 2563 03:59:59.306108  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
 2564 03:59:59.311010  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
 2565 03:59:59.322260  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
 2566 03:59:59.327388  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
 2567 03:59:59.337152  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
 2568 03:59:59.343266  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
 2569 03:59:59.353150  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
 2570 03:59:59.364132  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
 2571 03:59:59.369010  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
 2572 03:59:59.378870  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
 2573 03:59:59.385051  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
 2574 03:59:59.394746  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
 2575 03:59:59.405769  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
 2576 03:59:59.415631  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
 2577 03:59:59.425479  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
 2578 03:59:59.436461  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
 2579 03:59:59.447638  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
 2580 03:59:59.457320  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
 2581 03:59:59.468367  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
 2582 03:59:59.478251  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
 2583 03:59:59.489235  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
 2584 03:59:59.494388  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
 2585 03:59:59.504247  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
 2586 03:59:59.515291  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
 2587 03:59:59.520222  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
 2588 03:59:59.531362  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
 2589 03:59:59.536262  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
 2590 03:59:59.545995  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
 2591 03:59:59.557010  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
 2592 03:59:59.566886  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
 2593 03:59:59.573033  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
 2594 03:59:59.582994  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
 2595 03:59:59.587881  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
 2596 03:59:59.593977  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
 2597 03:59:59.603999  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
 2598 03:59:59.609153  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
 2599 03:59:59.620128  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
 2600 03:59:59.630095  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
 2601 03:59:59.636304  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
 2602 03:59:59.646258  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
 2603 03:59:59.651123  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
 2604 03:59:59.662390  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
 2605 03:59:59.672124  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
 2606 03:59:59.678275  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
 2607 03:59:59.683375  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
 2608 03:59:59.688123  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
 2609 03:59:59.699137  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
 2610 03:59:59.708976  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
 2611 03:59:59.714095  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
 2612 03:59:59.725116  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
 2613 03:59:59.734868  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
 2614 03:59:59.745849  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
 2615 03:59:59.755845  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
 2616 03:59:59.761969  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
 2617 03:59:59.771874  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
 2618 03:59:59.776746  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
 2619 03:59:59.783137  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
 2620 03:59:59.787952  dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
 2621 03:59:59.797958  dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
 2622 03:59:59.804122  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
 2623 03:59:59.809011  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
 2624 03:59:59.818970  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
 2625 03:59:59.825324  dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
 2626 03:59:59.830092  dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
 2627 03:59:59.835140  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
 2628 03:59:59.840004  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
 2629 03:59:59.846096  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
 2630 03:59:59.855817  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
 2631 03:59:59.860862  dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
 2632 03:59:59.866875  dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
 2633 03:59:59.871869  dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
 2634 03:59:59.876723  dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
 2635 03:59:59.881546  dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
 2636 03:59:59.887743  dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
 2637 03:59:59.892596  dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
 2638 03:59:59.897475  dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
 2639 03:59:59.902345  dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
 2640 03:59:59.908454  dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
 2641 03:59:59.913429  dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
 2642 03:59:59.923244  dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
 2643 03:59:59.929312  dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
 2644 03:59:59.934194  dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
 2645 03:59:59.939096  dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
 2646 03:59:59.943924  dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
 2647 03:59:59.950174  dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
 2648 03:59:59.955109  dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
 2649 03:59:59.960076  dt_test_unprobed_devices_sh_opp-table skip
 2650 03:59:59.965001  dt_test_unprobed_devices_sh_soc skip
 2651 03:59:59.965381  dt_test_unprobed_devices_sh_sound pass
 2652 03:59:59.971066  dt_test_unprobed_devices_sh_target-module_4b000000 pass
 2653 03:59:59.975998  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
 2654 03:59:59.985818  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
 2655 03:59:59.986201  dt_test_unprobed_devices_sh fail
 2656 03:59:59.992696  + ../../utils/send-to-lava.sh ./output/result.txt
 2657 04:00:00.108872  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
 2658 04:00:00.109962  Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
 2660 04:00:00.296927  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
 2661 04:00:00.297549  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
 2663 04:00:00.555556  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
 2664 04:00:00.556181  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
 2666 04:00:00.752120  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
 2667 04:00:00.752736  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
 2669 04:00:00.946667  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
 2670 04:00:00.947289  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
 2672 04:00:01.159301  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
 2673 04:00:01.159918  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
 2675 04:00:01.356851  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
 2676 04:00:01.357472  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
 2678 04:00:01.542877  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
 2679 04:00:01.543495  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
 2681 04:00:01.742529  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
 2682 04:00:01.743153  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
 2684 04:00:01.949725  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
 2685 04:00:01.950340  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
 2687 04:00:02.146722  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
 2688 04:00:02.147340  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
 2690 04:00:02.343729  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
 2691 04:00:02.344350  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
 2693 04:00:02.539848  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
 2694 04:00:02.540466  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
 2696 04:00:02.732836  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
 2697 04:00:02.733456  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
 2699 04:00:02.924553  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
 2700 04:00:02.925200  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
 2702 04:00:03.132436  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
 2703 04:00:03.133080  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
 2705 04:00:03.317890  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
 2706 04:00:03.318511  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
 2708 04:00:03.513085  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
 2709 04:00:03.513706  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
 2711 04:00:03.698919  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
 2712 04:00:03.699545  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
 2714 04:00:03.884648  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
 2715 04:00:03.885300  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
 2717 04:00:04.073759  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
 2718 04:00:04.074381  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
 2720 04:00:04.276398  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
 2721 04:00:04.277050  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
 2723 04:00:04.462296  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
 2724 04:00:04.462921  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
 2726 04:00:04.645880  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
 2727 04:00:04.646501  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
 2729 04:00:04.827658  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
 2730 04:00:04.828283  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
 2732 04:00:05.027033  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
 2733 04:00:05.027654  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
 2735 04:00:05.227661  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
 2736 04:00:05.228283  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
 2738 04:00:05.404371  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
 2739 04:00:05.405078  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
 2741 04:00:05.623012  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
 2742 04:00:05.623652  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
 2744 04:00:05.819723  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
 2745 04:00:05.820318  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
 2747 04:00:06.002332  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
 2748 04:00:06.002929  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
 2750 04:00:06.195677  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
 2751 04:00:06.196321  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
 2753 04:00:06.380579  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
 2754 04:00:06.381229  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
 2756 04:00:06.581210  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
 2757 04:00:06.581801  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
 2759 04:00:06.763826  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
 2760 04:00:06.764416  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
 2762 04:00:06.939074  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
 2763 04:00:06.939726  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
 2765 04:00:07.138642  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
 2766 04:00:07.139265  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
 2768 04:00:07.323414  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
 2769 04:00:07.324059  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
 2771 04:00:07.512677  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
 2772 04:00:07.513340  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
 2774 04:00:07.703896  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
 2775 04:00:07.704518  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
 2777 04:00:07.933956  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
 2778 04:00:07.934577  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
 2780 04:00:08.138820  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
 2781 04:00:08.139438  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
 2783 04:00:08.333333  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
 2784 04:00:08.333953  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
 2786 04:00:08.536451  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
 2787 04:00:08.537107  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
 2789 04:00:08.774981  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
 2790 04:00:08.775599  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
 2792 04:00:08.970339  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
 2793 04:00:08.970960  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
 2795 04:00:09.181787  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
 2796 04:00:09.182409  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
 2798 04:00:09.357313  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
 2799 04:00:09.357937  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
 2801 04:00:09.547558  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
 2802 04:00:09.548188  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
 2804 04:00:09.764250  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
 2805 04:00:09.764881  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
 2807 04:00:09.954415  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
 2808 04:00:09.955038  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
 2810 04:00:10.158344  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
 2811 04:00:10.158966  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
 2813 04:00:10.364600  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
 2814 04:00:10.365271  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
 2816 04:00:10.565237  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
 2817 04:00:10.565862  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
 2819 04:00:10.779887  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
 2820 04:00:10.780511  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
 2822 04:00:10.976395  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
 2823 04:00:10.977035  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
 2825 04:00:11.173034  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
 2826 04:00:11.173655  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
 2828 04:00:11.365335  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
 2829 04:00:11.365955  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
 2831 04:00:11.563886  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
 2832 04:00:11.564505  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
 2834 04:00:11.753013  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
 2835 04:00:11.753632  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
 2837 04:00:11.945606  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
 2838 04:00:11.946225  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
 2840 04:00:12.134692  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
 2841 04:00:12.135309  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
 2843 04:00:12.323997  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
 2844 04:00:12.324617  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
 2846 04:00:12.512924  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
 2847 04:00:12.513545  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
 2849 04:00:12.703098  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
 2850 04:00:12.703717  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
 2852 04:00:12.894054  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
 2853 04:00:12.894676  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
 2855 04:00:13.087872  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
 2856 04:00:13.088495  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
 2858 04:00:13.308391  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
 2859 04:00:13.309006  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
 2861 04:00:13.514373  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
 2862 04:00:13.514998  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
 2864 04:00:13.724457  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
 2865 04:00:13.725112  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
 2867 04:00:13.925364  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
 2868 04:00:13.925982  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
 2870 04:00:14.130326  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
 2871 04:00:14.130946  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
 2873 04:00:14.380767  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
 2874 04:00:14.381430  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
 2876 04:00:14.580288  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
 2877 04:00:14.580886  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
 2879 04:00:14.769367  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
 2880 04:00:14.769989  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
 2882 04:00:14.958457  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
 2883 04:00:14.959082  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
 2885 04:00:15.143270  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
 2886 04:00:15.143893  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
 2888 04:00:15.330383  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
 2889 04:00:15.331003  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
 2891 04:00:15.522679  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
 2892 04:00:15.523302  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
 2894 04:00:15.716018  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
 2895 04:00:15.716640  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
 2897 04:00:15.944291  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
 2898 04:00:15.944880  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
 2900 04:00:16.174283  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
 2901 04:00:16.174906  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
 2903 04:00:16.372850  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
 2904 04:00:16.373468  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
 2906 04:00:16.571341  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
 2907 04:00:16.571965  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
 2909 04:00:16.771765  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
 2910 04:00:16.772386  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
 2912 04:00:16.995377  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
 2913 04:00:16.996001  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
 2915 04:00:17.212873  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
 2916 04:00:17.213495  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
 2918 04:00:17.435380  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
 2919 04:00:17.436002  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
 2921 04:00:17.629799  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
 2922 04:00:17.630418  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
 2924 04:00:17.840282  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
 2925 04:00:17.840880  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
 2927 04:00:18.033905  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
 2928 04:00:18.034529  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
 2930 04:00:18.216723  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
 2931 04:00:18.217369  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
 2933 04:00:18.413394  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
 2934 04:00:18.414014  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
 2936 04:00:18.615231  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
 2937 04:00:18.615858  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
 2939 04:00:18.810681  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
 2940 04:00:18.811308  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
 2942 04:00:18.987941  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
 2943 04:00:18.988563  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
 2945 04:00:19.174605  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
 2946 04:00:19.175227  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
 2948 04:00:19.370775  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
 2949 04:00:19.371401  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
 2951 04:00:19.557350  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
 2952 04:00:19.557973  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
 2954 04:00:19.737734  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
 2955 04:00:19.738355  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
 2957 04:00:19.933070  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
 2958 04:00:19.933693  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
 2960 04:00:20.114418  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
 2961 04:00:20.115042  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
 2963 04:00:20.311528  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
 2964 04:00:20.312153  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
 2966 04:00:20.525603  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
 2967 04:00:20.526225  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
 2969 04:00:20.719687  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
 2970 04:00:20.720308  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
 2972 04:00:20.914984  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
 2973 04:00:20.915605  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
 2975 04:00:21.105361  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
 2976 04:00:21.105985  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
 2978 04:00:21.285345  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
 2979 04:00:21.285964  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
 2981 04:00:21.480947  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
 2982 04:00:21.481571  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
 2984 04:00:21.685164  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
 2985 04:00:21.685786  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
 2987 04:00:21.892164  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
 2988 04:00:21.892805  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
 2990 04:00:22.096147  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
 2991 04:00:22.096773  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
 2993 04:00:22.279156  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
 2994 04:00:22.279777  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
 2996 04:00:22.455592  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
 2997 04:00:22.456214  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
 2999 04:00:22.657323  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
 3000 04:00:22.657950  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
 3002 04:00:22.844367  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
 3003 04:00:22.844986  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
 3005 04:00:23.045232  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
 3006 04:00:23.045856  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
 3008 04:00:23.225011  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
 3009 04:00:23.225635  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
 3011 04:00:23.414497  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
 3012 04:00:23.415118  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
 3014 04:00:23.608012  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
 3015 04:00:23.608635  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
 3017 04:00:23.824111  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
 3019 04:00:23.827129  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
 3020 04:00:24.032479  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
 3022 04:00:24.035476  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
 3023 04:00:24.222931  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
 3025 04:00:24.224937  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
 3026 04:00:24.422337  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
 3027 04:00:24.422959  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
 3029 04:00:24.611483  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
 3030 04:00:24.612108  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
 3032 04:00:24.810991  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
 3033 04:00:24.811612  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
 3035 04:00:25.003845  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
 3036 04:00:25.004463  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
 3038 04:00:25.204239  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
 3039 04:00:25.204873  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
 3041 04:00:25.398268  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
 3042 04:00:25.398891  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
 3044 04:00:25.584924  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
 3045 04:00:25.585546  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
 3047 04:00:25.793717  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
 3048 04:00:25.794337  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
 3050 04:00:25.986519  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
 3051 04:00:25.987141  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
 3053 04:00:26.221786  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
 3054 04:00:26.222404  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
 3056 04:00:26.424126  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
 3057 04:00:26.424741  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
 3059 04:00:26.620275  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
 3060 04:00:26.620873  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
 3062 04:00:26.814405  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
 3063 04:00:26.815023  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
 3065 04:00:27.012415  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
 3066 04:00:27.013056  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
 3068 04:00:27.204777  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
 3069 04:00:27.205420  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
 3071 04:00:27.376218  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
 3072 04:00:27.376858  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
 3074 04:00:27.566269  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
 3075 04:00:27.566892  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
 3077 04:00:27.757288  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
 3078 04:00:27.757908  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
 3080 04:00:27.964207  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
 3081 04:00:27.964850  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
 3083 04:00:28.155437  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
 3084 04:00:28.156059  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
 3086 04:00:28.372704  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
 3087 04:00:28.373347  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
 3089 04:00:28.613746  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
 3090 04:00:28.614368  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
 3092 04:00:28.806262  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
 3093 04:00:28.806881  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
 3095 04:00:29.003133  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
 3096 04:00:29.003749  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
 3098 04:00:29.179881  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
 3099 04:00:29.180496  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
 3101 04:00:29.373949  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
 3102 04:00:29.374568  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
 3104 04:00:29.574391  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
 3105 04:00:29.575010  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
 3107 04:00:29.783923  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
 3108 04:00:29.784547  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
 3110 04:00:29.971561  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
 3111 04:00:29.972181  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
 3113 04:00:30.159195  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
 3114 04:00:30.159815  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
 3116 04:00:30.369881  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
 3117 04:00:30.370497  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
 3119 04:00:30.544927  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
 3120 04:00:30.545546  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
 3122 04:00:30.750209  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
 3123 04:00:30.750830  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
 3125 04:00:30.931774  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
 3126 04:00:30.932395  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
 3128 04:00:31.139423  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
 3129 04:00:31.140040  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
 3131 04:00:31.336633  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
 3132 04:00:31.337328  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
 3134 04:00:31.524393  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
 3135 04:00:31.525009  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
 3137 04:00:31.705620  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
 3138 04:00:31.706239  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
 3140 04:00:31.900538  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
 3141 04:00:31.901186  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
 3143 04:00:32.107067  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
 3144 04:00:32.107691  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
 3146 04:00:32.320200  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
 3147 04:00:32.320882  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
 3149 04:00:32.509155  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
 3150 04:00:32.509771  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
 3152 04:00:32.716932  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
 3153 04:00:32.717554  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
 3155 04:00:32.913848  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
 3156 04:00:32.914469  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
 3158 04:00:33.088702  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
 3159 04:00:33.089354  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
 3161 04:00:33.286037  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
 3162 04:00:33.286655  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
 3164 04:00:33.505514  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
 3165 04:00:33.506132  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
 3167 04:00:33.701730  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
 3168 04:00:33.702350  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
 3170 04:00:33.875780  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
 3171 04:00:33.876394  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
 3173 04:00:34.051746  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
 3174 04:00:34.052366  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
 3176 04:00:34.258543  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
 3177 04:00:34.259163  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
 3179 04:00:34.486139  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
 3180 04:00:34.486760  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
 3182 04:00:34.673565  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
 3183 04:00:34.674185  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
 3185 04:00:34.875188  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
 3186 04:00:34.875807  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
 3188 04:00:35.087285  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
 3189 04:00:35.087906  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
 3191 04:00:35.304867  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
 3192 04:00:35.305496  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
 3194 04:00:35.514156  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
 3195 04:00:35.514780  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
 3197 04:00:35.726397  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
 3198 04:00:35.727027  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
 3200 04:00:35.910266  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
 3201 04:00:35.910890  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
 3203 04:00:36.111021  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
 3204 04:00:36.111639  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
 3206 04:00:36.305347  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
 3207 04:00:36.305973  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
 3209 04:00:36.522025  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
 3210 04:00:36.522647  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
 3212 04:00:36.718681  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
 3213 04:00:36.719304  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
 3215 04:00:36.891636  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
 3216 04:00:36.892257  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
 3218 04:00:37.091971  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
 3219 04:00:37.092591  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
 3221 04:00:37.300893  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
 3222 04:00:37.301506  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
 3224 04:00:37.502372  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
 3225 04:00:37.502989  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
 3227 04:00:37.693176  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
 3228 04:00:37.693795  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
 3230 04:00:37.894477  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
 3231 04:00:37.895094  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
 3233 04:00:38.100088  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
 3234 04:00:38.100709  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
 3236 04:00:38.302889  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
 3237 04:00:38.303508  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
 3239 04:00:38.483487  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
 3240 04:00:38.484101  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
 3242 04:00:38.670352  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
 3243 04:00:38.670972  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
 3245 04:00:38.860211  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
 3246 04:00:38.860843  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
 3248 04:00:39.053283  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
 3249 04:00:39.053904  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
 3251 04:00:39.240704  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
 3252 04:00:39.241354  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
 3254 04:00:39.450613  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
 3255 04:00:39.451231  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
 3257 04:00:39.652066  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
 3258 04:00:39.652684  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
 3260 04:00:39.847650  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
 3261 04:00:39.848267  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
 3263 04:00:40.042772  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
 3264 04:00:40.043390  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
 3266 04:00:40.260068  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
 3267 04:00:40.260688  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
 3269 04:00:40.460315  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
 3270 04:00:40.460932  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
 3272 04:00:40.658390  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
 3273 04:00:40.659006  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
 3275 04:00:40.826087  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
 3276 04:00:40.826709  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
 3278 04:00:41.013718  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
 3279 04:00:41.014333  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
 3281 04:00:41.210032  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
 3282 04:00:41.210651  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
 3284 04:00:41.408103  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
 3285 04:00:41.408723  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
 3287 04:00:41.618386  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
 3288 04:00:41.619010  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
 3290 04:00:41.813562  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
 3291 04:00:41.814188  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
 3293 04:00:42.022377  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
 3294 04:00:42.022996  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
 3296 04:00:42.228160  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
 3297 04:00:42.228807  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
 3299 04:00:42.419801  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
 3300 04:00:42.420422  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
 3302 04:00:42.608570  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
 3303 04:00:42.609224  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
 3305 04:00:42.810275  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
 3306 04:00:42.810894  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
 3308 04:00:43.022946  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
 3309 04:00:43.023573  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
 3311 04:00:43.212650  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
 3312 04:00:43.213303  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
 3314 04:00:43.436514  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
 3315 04:00:43.437208  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
 3317 04:00:43.611733  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
 3318 04:00:43.612354  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
 3320 04:00:43.797950  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
 3321 04:00:43.798571  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
 3323 04:00:43.983241  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
 3324 04:00:43.983860  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
 3326 04:00:44.183380  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
 3327 04:00:44.183999  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
 3329 04:00:44.382355  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
 3330 04:00:44.382973  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
 3332 04:00:44.577202  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
 3333 04:00:44.577822  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
 3335 04:00:44.771304  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
 3336 04:00:44.771930  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
 3338 04:00:44.968422  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
 3340 04:00:44.971407  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
 3341 04:00:45.176493  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
 3342 04:00:45.177145  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
 3344 04:00:45.409148  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
 3345 04:00:45.409766  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
 3347 04:00:45.622111  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
 3348 04:00:45.622734  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
 3350 04:00:45.830671  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
 3351 04:00:45.831291  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
 3353 04:00:46.027977  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
 3354 04:00:46.028597  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
 3356 04:00:46.227971  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
 3357 04:00:46.228589  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
 3359 04:00:46.416359  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
 3360 04:00:46.416978  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
 3362 04:00:46.613187  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
 3363 04:00:46.613805  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
 3365 04:00:46.833190  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
 3366 04:00:46.833812  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
 3368 04:00:47.037295  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
 3369 04:00:47.037920  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
 3371 04:00:47.238600  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
 3372 04:00:47.239219  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
 3374 04:00:47.446976  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
 3375 04:00:47.447591  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
 3377 04:00:47.664225  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
 3378 04:00:47.664869  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
 3380 04:00:47.860744  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
 3381 04:00:47.861393  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
 3383 04:00:48.052191  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
 3384 04:00:48.052830  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
 3386 04:00:48.268930  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
 3387 04:00:48.269548  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
 3389 04:00:48.457266  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
 3390 04:00:48.457886  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
 3392 04:00:48.658339  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
 3393 04:00:48.658959  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
 3395 04:00:48.851079  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
 3396 04:00:48.851697  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
 3398 04:00:49.043527  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
 3399 04:00:49.044141  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
 3401 04:00:49.251079  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
 3402 04:00:49.251696  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
 3404 04:00:49.470075  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
 3405 04:00:49.470697  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
 3407 04:00:49.670188  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
 3408 04:00:49.670806  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
 3410 04:00:49.853268  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
 3411 04:00:49.853888  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
 3413 04:00:50.049936  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
 3414 04:00:50.050569  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
 3416 04:00:50.251928  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
 3417 04:00:50.252546  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
 3419 04:00:50.444170  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
 3420 04:00:50.444810  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
 3422 04:00:50.638813  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
 3423 04:00:50.639435  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
 3425 04:00:50.837944  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
 3426 04:00:50.838566  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
 3428 04:00:51.037124  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
 3429 04:00:51.037741  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
 3431 04:00:51.237616  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
 3432 04:00:51.238000  + set +x
 3433 04:00:51.238547  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
 3435 04:00:51.241986  <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1216052_1.6.2.4.5>
 3436 04:00:51.242602  Received signal: <ENDRUN> 1_kselftest-dt 1216052_1.6.2.4.5
 3437 04:00:51.242946  Ending use of test pattern.
 3438 04:00:51.243250  Ending test lava.1_kselftest-dt (1216052_1.6.2.4.5), duration 244.00
 3440 04:00:51.312125  <LAVA_TEST_RUNNER EXIT>
 3441 04:00:51.312740  ok: lava_test_shell seems to have completed
 3442 04:00:51.320344  dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass

 3443 04:00:51.321804  end: 3.1 lava-test-shell (duration 00:04:06) [common]
 3444 04:00:51.322227  end: 3 lava-test-retry (duration 00:04:06) [common]
 3445 04:00:51.322646  start: 4 finalize (timeout 00:02:40) [common]
 3446 04:00:51.323072  start: 4.1 power-off (timeout 00:00:30) [common]
 3447 04:00:51.323567  Calling: 'drpm' 'lf-bbb-02' 'off'
 3448 04:00:51.638737  >> OFF

 3449 04:00:51.640111  Returned 0 in 0 seconds
 3450 04:00:51.741115  end: 4.1 power-off (duration 00:00:00) [common]
 3452 04:00:51.742264  start: 4.2 read-feedback (timeout 00:02:39) [common]
 3453 04:00:51.743134  Listened to connection for namespace 'common' for up to 1s
 3454 04:00:51.743824  Listened to connection for namespace 'common' for up to 1s
 3455 04:00:52.743367  Finalising connection for namespace 'common'
 3456 04:00:52.743857  Disconnecting from shell: Finalise
 3457 04:00:52.744233  / # 
 3458 04:00:52.845002  end: 4.2 read-feedback (duration 00:00:01) [common]
 3459 04:00:52.845514  end: 4 finalize (duration 00:00:02) [common]
 3460 04:00:52.846006  Cleaning after the job
 3461 04:00:52.846469  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1216052/tftp-deploy-yd1p0v46/ramdisk
 3462 04:00:52.852662  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1216052/tftp-deploy-yd1p0v46/kernel
 3463 04:00:52.857640  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1216052/tftp-deploy-yd1p0v46/dtb
 3464 04:00:52.858360  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1216052/tftp-deploy-yd1p0v46/nfsrootfs
 3465 04:00:52.969195  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1216052/tftp-deploy-yd1p0v46/modules
 3466 04:00:52.974868  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1216052
 3467 04:00:54.105314  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1216052
 3468 04:00:54.105636  Job finished correctly