Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 03:13:15.227229 lava-dispatcher, installed at version: 2024.01
2 03:13:15.228046 start: 0 validate
3 03:13:15.228521 Start time: 2024-11-04 03:13:15.228490+00:00 (UTC)
4 03:13:15.229056 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 03:13:15.229594 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 03:13:15.269181 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 03:13:15.269743 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 03:13:15.297837 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 03:13:15.298455 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 03:13:16.346299 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 03:13:16.346816 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 03:13:16.391038 validate duration: 1.16
14 03:13:16.392135 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 03:13:16.392497 start: 1.1 download-retry (timeout 00:10:00) [common]
16 03:13:16.392825 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 03:13:16.393448 Not decompressing ramdisk as can be used compressed.
18 03:13:16.393908 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 03:13:16.394212 saving as /var/lib/lava/dispatcher/tmp/932547/tftp-deploy-io43rhyg/ramdisk/rootfs.cpio.gz
20 03:13:16.394508 total size: 8181887 (7 MB)
21 03:13:16.429291 progress 0 % (0 MB)
22 03:13:16.439184 progress 5 % (0 MB)
23 03:13:16.449365 progress 10 % (0 MB)
24 03:13:16.458251 progress 15 % (1 MB)
25 03:13:16.463441 progress 20 % (1 MB)
26 03:13:16.468869 progress 25 % (1 MB)
27 03:13:16.474015 progress 30 % (2 MB)
28 03:13:16.479487 progress 35 % (2 MB)
29 03:13:16.484624 progress 40 % (3 MB)
30 03:13:16.490108 progress 45 % (3 MB)
31 03:13:16.495189 progress 50 % (3 MB)
32 03:13:16.500683 progress 55 % (4 MB)
33 03:13:16.505771 progress 60 % (4 MB)
34 03:13:16.511194 progress 65 % (5 MB)
35 03:13:16.516283 progress 70 % (5 MB)
36 03:13:16.521710 progress 75 % (5 MB)
37 03:13:16.526860 progress 80 % (6 MB)
38 03:13:16.532319 progress 85 % (6 MB)
39 03:13:16.537355 progress 90 % (7 MB)
40 03:13:16.542389 progress 95 % (7 MB)
41 03:13:16.547019 progress 100 % (7 MB)
42 03:13:16.547659 7 MB downloaded in 0.15 s (50.96 MB/s)
43 03:13:16.548256 end: 1.1.1 http-download (duration 00:00:00) [common]
45 03:13:16.549200 end: 1.1 download-retry (duration 00:00:00) [common]
46 03:13:16.549517 start: 1.2 download-retry (timeout 00:10:00) [common]
47 03:13:16.549809 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 03:13:16.550308 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6/arm64/defconfig+debug/gcc-12/kernel/Image
49 03:13:16.550563 saving as /var/lib/lava/dispatcher/tmp/932547/tftp-deploy-io43rhyg/kernel/Image
50 03:13:16.550784 total size: 169941504 (162 MB)
51 03:13:16.551007 No compression specified
52 03:13:16.586430 progress 0 % (0 MB)
53 03:13:16.692231 progress 5 % (8 MB)
54 03:13:16.798920 progress 10 % (16 MB)
55 03:13:16.905778 progress 15 % (24 MB)
56 03:13:17.012663 progress 20 % (32 MB)
57 03:13:17.118995 progress 25 % (40 MB)
58 03:13:17.224438 progress 30 % (48 MB)
59 03:13:17.332265 progress 35 % (56 MB)
60 03:13:17.440341 progress 40 % (64 MB)
61 03:13:17.546741 progress 45 % (72 MB)
62 03:13:17.654846 progress 50 % (81 MB)
63 03:13:17.761684 progress 55 % (89 MB)
64 03:13:17.866075 progress 60 % (97 MB)
65 03:13:17.970749 progress 65 % (105 MB)
66 03:13:18.077978 progress 70 % (113 MB)
67 03:13:18.183734 progress 75 % (121 MB)
68 03:13:18.291960 progress 80 % (129 MB)
69 03:13:18.398599 progress 85 % (137 MB)
70 03:13:18.505177 progress 90 % (145 MB)
71 03:13:18.611339 progress 95 % (153 MB)
72 03:13:18.713451 progress 100 % (162 MB)
73 03:13:18.714044 162 MB downloaded in 2.16 s (74.92 MB/s)
74 03:13:18.714532 end: 1.2.1 http-download (duration 00:00:02) [common]
76 03:13:18.715349 end: 1.2 download-retry (duration 00:00:02) [common]
77 03:13:18.715626 start: 1.3 download-retry (timeout 00:09:58) [common]
78 03:13:18.715893 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 03:13:18.716387 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 03:13:18.716659 saving as /var/lib/lava/dispatcher/tmp/932547/tftp-deploy-io43rhyg/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 03:13:18.716871 total size: 53209 (0 MB)
82 03:13:18.717082 No compression specified
83 03:13:18.756984 progress 61 % (0 MB)
84 03:13:18.758142 progress 100 % (0 MB)
85 03:13:18.758930 0 MB downloaded in 0.04 s (1.21 MB/s)
86 03:13:18.759634 end: 1.3.1 http-download (duration 00:00:00) [common]
88 03:13:18.761041 end: 1.3 download-retry (duration 00:00:00) [common]
89 03:13:18.761470 start: 1.4 download-retry (timeout 00:09:58) [common]
90 03:13:18.761869 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 03:13:18.762547 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 03:13:18.762919 saving as /var/lib/lava/dispatcher/tmp/932547/tftp-deploy-io43rhyg/modules/modules.tar
93 03:13:18.763219 total size: 27633176 (26 MB)
94 03:13:18.763543 Using unxz to decompress xz
95 03:13:18.804449 progress 0 % (0 MB)
96 03:13:19.043538 progress 5 % (1 MB)
97 03:13:19.302662 progress 10 % (2 MB)
98 03:13:19.603510 progress 15 % (3 MB)
99 03:13:19.885386 progress 20 % (5 MB)
100 03:13:20.079365 progress 25 % (6 MB)
101 03:13:20.276006 progress 30 % (7 MB)
102 03:13:20.478542 progress 35 % (9 MB)
103 03:13:20.668505 progress 40 % (10 MB)
104 03:13:20.858281 progress 45 % (11 MB)
105 03:13:21.066980 progress 50 % (13 MB)
106 03:13:21.262481 progress 55 % (14 MB)
107 03:13:21.472544 progress 60 % (15 MB)
108 03:13:21.676841 progress 65 % (17 MB)
109 03:13:21.873604 progress 70 % (18 MB)
110 03:13:22.080416 progress 75 % (19 MB)
111 03:13:22.277784 progress 80 % (21 MB)
112 03:13:22.479919 progress 85 % (22 MB)
113 03:13:22.680518 progress 90 % (23 MB)
114 03:13:22.877827 progress 95 % (25 MB)
115 03:13:23.069694 progress 100 % (26 MB)
116 03:13:23.080811 26 MB downloaded in 4.32 s (6.10 MB/s)
117 03:13:23.081666 end: 1.4.1 http-download (duration 00:00:04) [common]
119 03:13:23.083273 end: 1.4 download-retry (duration 00:00:04) [common]
120 03:13:23.083797 start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
121 03:13:23.084373 start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
122 03:13:23.084942 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 03:13:23.085472 start: 1.5.2 lava-overlay (timeout 00:09:53) [common]
124 03:13:23.086481 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp
125 03:13:23.087368 makedir: /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin
126 03:13:23.088038 makedir: /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/tests
127 03:13:23.088661 makedir: /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/results
128 03:13:23.089276 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-add-keys
129 03:13:23.090222 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-add-sources
130 03:13:23.091127 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-background-process-start
131 03:13:23.092075 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-background-process-stop
132 03:13:23.093042 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-common-functions
133 03:13:23.093938 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-echo-ipv4
134 03:13:23.094819 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-install-packages
135 03:13:23.095685 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-installed-packages
136 03:13:23.096594 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-os-build
137 03:13:23.097479 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-probe-channel
138 03:13:23.098345 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-probe-ip
139 03:13:23.099214 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-target-ip
140 03:13:23.100112 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-target-mac
141 03:13:23.101009 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-target-storage
142 03:13:23.101912 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-test-case
143 03:13:23.102795 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-test-event
144 03:13:23.103654 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-test-feedback
145 03:13:23.104587 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-test-raise
146 03:13:23.105479 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-test-reference
147 03:13:23.106353 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-test-runner
148 03:13:23.107226 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-test-set
149 03:13:23.108172 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-test-shell
150 03:13:23.109183 Updating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-install-packages (oe)
151 03:13:23.110136 Updating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/bin/lava-installed-packages (oe)
152 03:13:23.110939 Creating /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/environment
153 03:13:23.111622 LAVA metadata
154 03:13:23.112135 - LAVA_JOB_ID=932547
155 03:13:23.112563 - LAVA_DISPATCHER_IP=192.168.6.2
156 03:13:23.113204 start: 1.5.2.1 ssh-authorize (timeout 00:09:53) [common]
157 03:13:23.114959 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 03:13:23.115539 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:53) [common]
159 03:13:23.115950 skipped lava-vland-overlay
160 03:13:23.116479 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 03:13:23.116988 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:53) [common]
162 03:13:23.117411 skipped lava-multinode-overlay
163 03:13:23.117899 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 03:13:23.118397 start: 1.5.2.4 test-definition (timeout 00:09:53) [common]
165 03:13:23.118864 Loading test definitions
166 03:13:23.119404 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:53) [common]
167 03:13:23.119840 Using /lava-932547 at stage 0
168 03:13:23.122004 uuid=932547_1.5.2.4.1 testdef=None
169 03:13:23.122562 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 03:13:23.123078 start: 1.5.2.4.2 test-overlay (timeout 00:09:53) [common]
171 03:13:23.125581 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 03:13:23.126392 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:53) [common]
174 03:13:23.128654 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 03:13:23.129500 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:53) [common]
177 03:13:23.131648 runner path: /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/0/tests/0_dmesg test_uuid 932547_1.5.2.4.1
178 03:13:23.132208 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 03:13:23.132987 Creating lava-test-runner.conf files
181 03:13:23.133192 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/932547/lava-overlay-rljxh5tp/lava-932547/0 for stage 0
182 03:13:23.133522 - 0_dmesg
183 03:13:23.133876 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 03:13:23.134156 start: 1.5.2.5 compress-overlay (timeout 00:09:53) [common]
185 03:13:23.157573 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 03:13:23.157949 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:53) [common]
187 03:13:23.158217 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 03:13:23.158485 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 03:13:23.158748 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
190 03:13:24.076692 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 03:13:24.077246 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
192 03:13:24.077742 extracting modules file /var/lib/lava/dispatcher/tmp/932547/tftp-deploy-io43rhyg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/932547/extract-overlay-ramdisk-rjo529pb/ramdisk
193 03:13:25.794923 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 03:13:25.795521 start: 1.5.5 apply-overlay-tftp (timeout 00:09:51) [common]
195 03:13:25.795935 [common] Applying overlay /var/lib/lava/dispatcher/tmp/932547/compress-overlay-vj8ws_u1/overlay-1.5.2.5.tar.gz to ramdisk
196 03:13:25.796362 [common] Applying overlay /var/lib/lava/dispatcher/tmp/932547/compress-overlay-vj8ws_u1/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/932547/extract-overlay-ramdisk-rjo529pb/ramdisk
197 03:13:25.830387 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 03:13:25.830831 start: 1.5.6 prepare-kernel (timeout 00:09:51) [common]
199 03:13:25.831135 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:51) [common]
200 03:13:25.831392 Converting downloaded kernel to a uImage
201 03:13:25.831749 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/932547/tftp-deploy-io43rhyg/kernel/Image /var/lib/lava/dispatcher/tmp/932547/tftp-deploy-io43rhyg/kernel/uImage
202 03:13:27.565939 output: Image Name:
203 03:13:27.566362 output: Created: Mon Nov 4 03:13:25 2024
204 03:13:27.566598 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 03:13:27.566815 output: Data Size: 169941504 Bytes = 165958.50 KiB = 162.07 MiB
206 03:13:27.567028 output: Load Address: 01080000
207 03:13:27.567233 output: Entry Point: 01080000
208 03:13:27.567437 output:
209 03:13:27.567777 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 03:13:27.568087 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 03:13:27.568380 start: 1.5.7 configure-preseed-file (timeout 00:09:49) [common]
212 03:13:27.568649 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 03:13:27.568921 start: 1.5.8 compress-ramdisk (timeout 00:09:49) [common]
214 03:13:27.569188 Building ramdisk /var/lib/lava/dispatcher/tmp/932547/extract-overlay-ramdisk-rjo529pb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/932547/extract-overlay-ramdisk-rjo529pb/ramdisk
215 03:13:33.259065 >> 441543 blocks
216 03:13:53.423283 Adding RAMdisk u-boot header.
217 03:13:53.423947 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/932547/extract-overlay-ramdisk-rjo529pb/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/932547/extract-overlay-ramdisk-rjo529pb/ramdisk.cpio.gz.uboot
218 03:13:54.020245 output: Image Name:
219 03:13:54.020765 output: Created: Mon Nov 4 03:13:53 2024
220 03:13:54.021019 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 03:13:54.021271 output: Data Size: 53579698 Bytes = 52323.92 KiB = 51.10 MiB
222 03:13:54.021517 output: Load Address: 00000000
223 03:13:54.021760 output: Entry Point: 00000000
224 03:13:54.021993 output:
225 03:13:54.022693 rename /var/lib/lava/dispatcher/tmp/932547/extract-overlay-ramdisk-rjo529pb/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/932547/tftp-deploy-io43rhyg/ramdisk/ramdisk.cpio.gz.uboot
226 03:13:54.023193 end: 1.5.8 compress-ramdisk (duration 00:00:26) [common]
227 03:13:54.023538 end: 1.5 prepare-tftp-overlay (duration 00:00:31) [common]
228 03:13:54.023881 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:22) [common]
229 03:13:54.024521 No LXC device requested
230 03:13:54.025094 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 03:13:54.025617 start: 1.7 deploy-device-env (timeout 00:09:22) [common]
232 03:13:54.026116 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 03:13:54.026535 Checking files for TFTP limit of 4294967296 bytes.
234 03:13:54.029216 end: 1 tftp-deploy (duration 00:00:38) [common]
235 03:13:54.029797 start: 2 uboot-action (timeout 00:05:00) [common]
236 03:13:54.030321 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 03:13:54.030816 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 03:13:54.031317 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 03:13:54.031841 Using kernel file from prepare-kernel: 932547/tftp-deploy-io43rhyg/kernel/uImage
240 03:13:54.032502 substitutions:
241 03:13:54.032917 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 03:13:54.033322 - {DTB_ADDR}: 0x01070000
243 03:13:54.033721 - {DTB}: 932547/tftp-deploy-io43rhyg/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 03:13:54.034117 - {INITRD}: 932547/tftp-deploy-io43rhyg/ramdisk/ramdisk.cpio.gz.uboot
245 03:13:54.034515 - {KERNEL_ADDR}: 0x01080000
246 03:13:54.034913 - {KERNEL}: 932547/tftp-deploy-io43rhyg/kernel/uImage
247 03:13:54.035305 - {LAVA_MAC}: None
248 03:13:54.035738 - {PRESEED_CONFIG}: None
249 03:13:54.036165 - {PRESEED_LOCAL}: None
250 03:13:54.036560 - {RAMDISK_ADDR}: 0x08000000
251 03:13:54.036951 - {RAMDISK}: 932547/tftp-deploy-io43rhyg/ramdisk/ramdisk.cpio.gz.uboot
252 03:13:54.037345 - {ROOT_PART}: None
253 03:13:54.037736 - {ROOT}: None
254 03:13:54.038126 - {SERVER_IP}: 192.168.6.2
255 03:13:54.038519 - {TEE_ADDR}: 0x83000000
256 03:13:54.038909 - {TEE}: None
257 03:13:54.039298 Parsed boot commands:
258 03:13:54.039677 - setenv autoload no
259 03:13:54.040083 - setenv initrd_high 0xffffffff
260 03:13:54.040474 - setenv fdt_high 0xffffffff
261 03:13:54.040863 - dhcp
262 03:13:54.041251 - setenv serverip 192.168.6.2
263 03:13:54.041639 - tftpboot 0x01080000 932547/tftp-deploy-io43rhyg/kernel/uImage
264 03:13:54.042026 - tftpboot 0x08000000 932547/tftp-deploy-io43rhyg/ramdisk/ramdisk.cpio.gz.uboot
265 03:13:54.042413 - tftpboot 0x01070000 932547/tftp-deploy-io43rhyg/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 03:13:54.042802 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 03:13:54.043194 - bootm 0x01080000 0x08000000 0x01070000
268 03:13:54.043684 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 03:13:54.045200 start: 2.3 connect-device (timeout 00:05:00) [common]
271 03:13:54.045641 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 03:13:54.059773 Setting prompt string to ['lava-test: # ']
273 03:13:54.061259 end: 2.3 connect-device (duration 00:00:00) [common]
274 03:13:54.061860 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 03:13:54.062401 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 03:13:54.062927 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 03:13:54.064104 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 03:13:54.100901 >> OK - accepted request
279 03:13:54.103041 Returned 0 in 0 seconds
280 03:13:54.204150 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 03:13:54.205717 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 03:13:54.206284 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 03:13:54.206785 Setting prompt string to ['Hit any key to stop autoboot']
285 03:13:54.207232 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 03:13:54.208831 Trying 192.168.56.21...
287 03:13:54.209324 Connected to conserv1.
288 03:13:54.209724 Escape character is '^]'.
289 03:13:54.210144
290 03:13:54.210565 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 03:13:54.210987
292 03:14:01.735249 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 03:14:01.735890 bl2_stage_init 0x01
294 03:14:01.736388 bl2_stage_init 0x81
295 03:14:01.740876 hw id: 0x0000 - pwm id 0x01
296 03:14:01.741327 bl2_stage_init 0xc1
297 03:14:01.741748 bl2_stage_init 0x02
298 03:14:01.742158
299 03:14:01.746623 L0:00000000
300 03:14:01.747106 L1:00000703
301 03:14:01.747525 L2:00008067
302 03:14:01.747930 L3:15000000
303 03:14:01.748372 S1:00000000
304 03:14:01.749249 B2:20282000
305 03:14:01.749669 B1:a0f83180
306 03:14:01.750066
307 03:14:01.754699 TE: 69704
308 03:14:01.755155
309 03:14:01.760176 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 03:14:01.760608
311 03:14:01.761015 Board ID = 1
312 03:14:01.761417 Set cpu clk to 24M
313 03:14:01.765881 Set clk81 to 24M
314 03:14:01.766339 Use GP1_pll as DSU clk.
315 03:14:01.766750 DSU clk: 1200 Mhz
316 03:14:01.771500 CPU clk: 1200 MHz
317 03:14:01.772031 Set clk81 to 166.6M
318 03:14:01.776974 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 03:14:01.777417 board id: 1
320 03:14:01.785931 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 03:14:01.797567 fw parse done
322 03:14:01.802478 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 03:14:01.845753 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 03:14:01.857449 PIEI prepare done
325 03:14:01.857879 fastboot data load
326 03:14:01.858277 fastboot data verify
327 03:14:01.863009 verify result: 266
328 03:14:01.868764 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 03:14:01.869185 LPDDR4 probe
330 03:14:01.869575 ddr clk to 1584MHz
331 03:14:01.875912 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 03:14:01.913401
333 03:14:01.913847 dmc_version 0001
334 03:14:01.920947 Check phy result
335 03:14:01.927304 INFO : End of CA training
336 03:14:01.927721 INFO : End of initialization
337 03:14:01.932913 INFO : Training has run successfully!
338 03:14:01.933337 Check phy result
339 03:14:01.938533 INFO : End of initialization
340 03:14:01.938945 INFO : End of read enable training
341 03:14:01.941867 INFO : End of fine write leveling
342 03:14:01.947375 INFO : End of Write leveling coarse delay
343 03:14:01.952962 INFO : Training has run successfully!
344 03:14:01.953377 Check phy result
345 03:14:01.953769 INFO : End of initialization
346 03:14:01.958546 INFO : End of read dq deskew training
347 03:14:01.964181 INFO : End of MPR read delay center optimization
348 03:14:01.964598 INFO : End of write delay center optimization
349 03:14:01.969809 INFO : End of read delay center optimization
350 03:14:01.975393 INFO : End of max read latency training
351 03:14:01.975831 INFO : Training has run successfully!
352 03:14:01.980990 1D training succeed
353 03:14:01.986270 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 03:14:02.034567 Check phy result
355 03:14:02.035040 INFO : End of initialization
356 03:14:02.062050 INFO : End of 2D read delay Voltage center optimization
357 03:14:02.086229 INFO : End of 2D read delay Voltage center optimization
358 03:14:02.145906 INFO : End of 2D write delay Voltage center optimization
359 03:14:02.197545 INFO : End of 2D write delay Voltage center optimization
360 03:14:02.202996 INFO : Training has run successfully!
361 03:14:02.203439
362 03:14:02.203842 channel==0
363 03:14:02.208640 RxClkDly_Margin_A0==88 ps 9
364 03:14:02.209101 TxDqDly_Margin_A0==98 ps 10
365 03:14:02.214166 RxClkDly_Margin_A1==88 ps 9
366 03:14:02.214605 TxDqDly_Margin_A1==98 ps 10
367 03:14:02.215002 TrainedVREFDQ_A0==74
368 03:14:02.219919 TrainedVREFDQ_A1==74
369 03:14:02.220387 VrefDac_Margin_A0==22
370 03:14:02.220784 DeviceVref_Margin_A0==40
371 03:14:02.225376 VrefDac_Margin_A1==23
372 03:14:02.225806 DeviceVref_Margin_A1==40
373 03:14:02.226198
374 03:14:02.226588
375 03:14:02.230983 channel==1
376 03:14:02.231401 RxClkDly_Margin_A0==78 ps 8
377 03:14:02.231792 TxDqDly_Margin_A0==88 ps 9
378 03:14:02.236645 RxClkDly_Margin_A1==88 ps 9
379 03:14:02.237120 TxDqDly_Margin_A1==88 ps 9
380 03:14:02.242117 TrainedVREFDQ_A0==77
381 03:14:02.242539 TrainedVREFDQ_A1==75
382 03:14:02.242933 VrefDac_Margin_A0==22
383 03:14:02.247891 DeviceVref_Margin_A0==37
384 03:14:02.248330 VrefDac_Margin_A1==22
385 03:14:02.253400 DeviceVref_Margin_A1==39
386 03:14:02.253813
387 03:14:02.254212 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 03:14:02.254602
389 03:14:02.286968 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 03:14:02.287494 2D training succeed
391 03:14:02.292646 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 03:14:02.298183 auto size-- 65535DDR cs0 size: 2048MB
393 03:14:02.298605 DDR cs1 size: 2048MB
394 03:14:02.303948 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 03:14:02.304420 cs0 DataBus test pass
396 03:14:02.309404 cs1 DataBus test pass
397 03:14:02.309852 cs0 AddrBus test pass
398 03:14:02.310244 cs1 AddrBus test pass
399 03:14:02.310632
400 03:14:02.314988 100bdlr_step_size ps== 471
401 03:14:02.315449 result report
402 03:14:02.320538 boot times 0Enable ddr reg access
403 03:14:02.324848 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 03:14:02.339169 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 03:14:02.998369 bl2z: ptr: 05129330, size: 00001e40
406 03:14:03.006082 0.0;M3 CHK:0;cm4_sp_mode 0
407 03:14:03.006555 MVN_1=0x00000000
408 03:14:03.006970 MVN_2=0x00000000
409 03:14:03.017681 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 03:14:03.018137 OPS=0x04
411 03:14:03.018548 ring efuse init
412 03:14:03.023198 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 03:14:03.023638 [0.017354 Inits done]
414 03:14:03.024081 secure task start!
415 03:14:03.030597 high task start!
416 03:14:03.031020 low task start!
417 03:14:03.031420 run into bl31
418 03:14:03.039190 NOTICE: BL31: v1.3(release):4fc40b1
419 03:14:03.047016 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 03:14:03.047459 NOTICE: BL31: G12A normal boot!
421 03:14:03.062653 NOTICE: BL31: BL33 decompress pass
422 03:14:03.067379 ERROR: Error initializing runtime service opteed_fast
423 03:14:05.784738 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 03:14:05.785352 bl2_stage_init 0x01
425 03:14:05.785779 bl2_stage_init 0x81
426 03:14:05.790370 hw id: 0x0000 - pwm id 0x01
427 03:14:05.790846 bl2_stage_init 0xc1
428 03:14:05.795379 bl2_stage_init 0x02
429 03:14:05.795869
430 03:14:05.796378 L0:00000000
431 03:14:05.796769 L1:00000703
432 03:14:05.797154 L2:00008067
433 03:14:05.800814 L3:15000000
434 03:14:05.801235 S1:00000000
435 03:14:05.801626 B2:20282000
436 03:14:05.802014 B1:a0f83180
437 03:14:05.802401
438 03:14:05.802787 TE: 70274
439 03:14:05.803181
440 03:14:05.812033 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 03:14:05.812469
442 03:14:05.812854 Board ID = 1
443 03:14:05.813250 Set cpu clk to 24M
444 03:14:05.813634 Set clk81 to 24M
445 03:14:05.817650 Use GP1_pll as DSU clk.
446 03:14:05.818060 DSU clk: 1200 Mhz
447 03:14:05.818445 CPU clk: 1200 MHz
448 03:14:05.823286 Set clk81 to 166.6M
449 03:14:05.828806 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 03:14:05.829231 board id: 1
451 03:14:05.836699 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 03:14:05.847622 fw parse done
453 03:14:05.853581 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 03:14:05.896699 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 03:14:05.907902 PIEI prepare done
456 03:14:05.908415 fastboot data load
457 03:14:05.908819 fastboot data verify
458 03:14:05.913445 verify result: 266
459 03:14:05.919142 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 03:14:05.919575 LPDDR4 probe
461 03:14:05.919960 ddr clk to 1584MHz
462 03:14:05.927016 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 03:14:05.964781
464 03:14:05.965320 dmc_version 0001
465 03:14:05.971900 Check phy result
466 03:14:05.977903 INFO : End of CA training
467 03:14:05.978374 INFO : End of initialization
468 03:14:05.983533 INFO : Training has run successfully!
469 03:14:05.984070 Check phy result
470 03:14:05.989110 INFO : End of initialization
471 03:14:05.989599 INFO : End of read enable training
472 03:14:05.992450 INFO : End of fine write leveling
473 03:14:05.998010 INFO : End of Write leveling coarse delay
474 03:14:06.003619 INFO : Training has run successfully!
475 03:14:06.004125 Check phy result
476 03:14:06.004548 INFO : End of initialization
477 03:14:06.009258 INFO : End of read dq deskew training
478 03:14:06.012581 INFO : End of MPR read delay center optimization
479 03:14:06.018200 INFO : End of write delay center optimization
480 03:14:06.023718 INFO : End of read delay center optimization
481 03:14:06.024247 INFO : End of max read latency training
482 03:14:06.029453 INFO : Training has run successfully!
483 03:14:06.029943 1D training succeed
484 03:14:06.037559 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 03:14:06.085807 Check phy result
486 03:14:06.086340 INFO : End of initialization
487 03:14:06.113160 INFO : End of 2D read delay Voltage center optimization
488 03:14:06.137385 INFO : End of 2D read delay Voltage center optimization
489 03:14:06.203659 INFO : End of 2D write delay Voltage center optimization
490 03:14:06.248097 INFO : End of 2D write delay Voltage center optimization
491 03:14:06.253521 INFO : Training has run successfully!
492 03:14:06.254066
493 03:14:06.254541 channel==0
494 03:14:06.259261 RxClkDly_Margin_A0==88 ps 9
495 03:14:06.259887 TxDqDly_Margin_A0==98 ps 10
496 03:14:06.262479 RxClkDly_Margin_A1==88 ps 9
497 03:14:06.263073 TxDqDly_Margin_A1==88 ps 9
498 03:14:06.267970 TrainedVREFDQ_A0==76
499 03:14:06.268531 TrainedVREFDQ_A1==74
500 03:14:06.268999 VrefDac_Margin_A0==23
501 03:14:06.273586 DeviceVref_Margin_A0==38
502 03:14:06.274119 VrefDac_Margin_A1==23
503 03:14:06.279216 DeviceVref_Margin_A1==40
504 03:14:06.279750
505 03:14:06.280254
506 03:14:06.280711 channel==1
507 03:14:06.281269 RxClkDly_Margin_A0==78 ps 8
508 03:14:06.284837 TxDqDly_Margin_A0==98 ps 10
509 03:14:06.285435 RxClkDly_Margin_A1==78 ps 8
510 03:14:06.290461 TxDqDly_Margin_A1==88 ps 9
511 03:14:06.291000 TrainedVREFDQ_A0==78
512 03:14:06.291465 TrainedVREFDQ_A1==75
513 03:14:06.295961 VrefDac_Margin_A0==22
514 03:14:06.296522 DeviceVref_Margin_A0==36
515 03:14:06.301575 VrefDac_Margin_A1==22
516 03:14:06.302152 DeviceVref_Margin_A1==39
517 03:14:06.302766
518 03:14:06.307195 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 03:14:06.307811
520 03:14:06.335217 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
521 03:14:06.340806 2D training succeed
522 03:14:06.346471 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 03:14:06.347079 auto size-- 65535DDR cs0 size: 2048MB
524 03:14:06.352004 DDR cs1 size: 2048MB
525 03:14:06.352541 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 03:14:06.357620 cs0 DataBus test pass
527 03:14:06.358140 cs1 DataBus test pass
528 03:14:06.358603 cs0 AddrBus test pass
529 03:14:06.363220 cs1 AddrBus test pass
530 03:14:06.363744
531 03:14:06.364240 100bdlr_step_size ps== 471
532 03:14:06.364703 result report
533 03:14:06.368765 boot times 0Enable ddr reg access
534 03:14:06.376380 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 03:14:06.390172 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 03:14:07.050086 bl2z: ptr: 05129330, size: 00001e40
537 03:14:07.058170 0.0;M3 CHK:0;cm4_sp_mode 0
538 03:14:07.058752 MVN_1=0x00000000
539 03:14:07.059226 MVN_2=0x00000000
540 03:14:07.069753 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 03:14:07.070499 OPS=0x04
542 03:14:07.071259 ring efuse init
543 03:14:07.072704 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 03:14:07.078721 [0.017355 Inits done]
545 03:14:07.079331 secure task start!
546 03:14:07.079828 high task start!
547 03:14:07.080324 low task start!
548 03:14:07.082017 run into bl31
549 03:14:07.091699 NOTICE: BL31: v1.3(release):4fc40b1
550 03:14:07.099441 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 03:14:07.100092 NOTICE: BL31: G12A normal boot!
552 03:14:07.114924 NOTICE: BL31: BL33 decompress pass
553 03:14:07.120686 ERROR: Error initializing runtime service opteed_fast
554 03:14:08.482222 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 03:14:08.482856 bl2_stage_init 0x01
556 03:14:08.483339 bl2_stage_init 0x81
557 03:14:08.487911 hw id: 0x0000 - pwm id 0x01
558 03:14:08.488479 bl2_stage_init 0xc1
559 03:14:08.493500 bl2_stage_init 0x02
560 03:14:08.494183
561 03:14:08.494663 L0:00000000
562 03:14:08.495112 L1:00000703
563 03:14:08.495554 L2:00008067
564 03:14:08.496035 L3:15000000
565 03:14:08.499571 S1:00000000
566 03:14:08.500134 B2:20282000
567 03:14:08.500577 B1:a0f83180
568 03:14:08.501007
569 03:14:08.501443 TE: 67278
570 03:14:08.501874
571 03:14:08.505181 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 03:14:08.505706
573 03:14:08.510812 Board ID = 1
574 03:14:08.511324 Set cpu clk to 24M
575 03:14:08.511759 Set clk81 to 24M
576 03:14:08.516361 Use GP1_pll as DSU clk.
577 03:14:08.516882 DSU clk: 1200 Mhz
578 03:14:08.517321 CPU clk: 1200 MHz
579 03:14:08.517748 Set clk81 to 166.6M
580 03:14:08.527538 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 03:14:08.528100 board id: 1
582 03:14:08.533293 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 03:14:08.544888 fw parse done
584 03:14:08.550101 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 03:14:08.592852 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 03:14:08.604426 PIEI prepare done
587 03:14:08.604954 fastboot data load
588 03:14:08.605404 fastboot data verify
589 03:14:08.609986 verify result: 266
590 03:14:08.615605 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 03:14:08.616151 LPDDR4 probe
592 03:14:08.616597 ddr clk to 1584MHz
593 03:14:08.622983 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 03:14:08.660835
595 03:14:08.661355 dmc_version 0001
596 03:14:08.666992 Check phy result
597 03:14:08.673472 INFO : End of CA training
598 03:14:08.673982 INFO : End of initialization
599 03:14:08.679094 INFO : Training has run successfully!
600 03:14:08.679601 Check phy result
601 03:14:08.684714 INFO : End of initialization
602 03:14:08.685220 INFO : End of read enable training
603 03:14:08.690271 INFO : End of fine write leveling
604 03:14:08.695937 INFO : End of Write leveling coarse delay
605 03:14:08.696475 INFO : Training has run successfully!
606 03:14:08.696915 Check phy result
607 03:14:08.701447 INFO : End of initialization
608 03:14:08.701947 INFO : End of read dq deskew training
609 03:14:08.707041 INFO : End of MPR read delay center optimization
610 03:14:08.712675 INFO : End of write delay center optimization
611 03:14:08.718262 INFO : End of read delay center optimization
612 03:14:08.718766 INFO : End of max read latency training
613 03:14:08.723844 INFO : Training has run successfully!
614 03:14:08.724386 1D training succeed
615 03:14:08.732076 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 03:14:08.780478 Check phy result
617 03:14:08.781008 INFO : End of initialization
618 03:14:08.802807 INFO : End of 2D read delay Voltage center optimization
619 03:14:08.821580 INFO : End of 2D read delay Voltage center optimization
620 03:14:08.873758 INFO : End of 2D write delay Voltage center optimization
621 03:14:08.923090 INFO : End of 2D write delay Voltage center optimization
622 03:14:08.928873 INFO : Training has run successfully!
623 03:14:08.929374
624 03:14:08.929828 channel==0
625 03:14:08.934309 RxClkDly_Margin_A0==78 ps 8
626 03:14:08.934832 TxDqDly_Margin_A0==98 ps 10
627 03:14:08.939902 RxClkDly_Margin_A1==88 ps 9
628 03:14:08.940452 TxDqDly_Margin_A1==98 ps 10
629 03:14:08.940894 TrainedVREFDQ_A0==74
630 03:14:08.945525 TrainedVREFDQ_A1==74
631 03:14:08.946067 VrefDac_Margin_A0==23
632 03:14:08.946544 DeviceVref_Margin_A0==40
633 03:14:08.951132 VrefDac_Margin_A1==23
634 03:14:08.951676 DeviceVref_Margin_A1==40
635 03:14:08.952144
636 03:14:08.952582
637 03:14:08.956821 channel==1
638 03:14:08.957330 RxClkDly_Margin_A0==78 ps 8
639 03:14:08.957770 TxDqDly_Margin_A0==98 ps 10
640 03:14:08.962327 RxClkDly_Margin_A1==88 ps 9
641 03:14:08.962832 TxDqDly_Margin_A1==88 ps 9
642 03:14:08.967868 TrainedVREFDQ_A0==75
643 03:14:08.968403 TrainedVREFDQ_A1==77
644 03:14:08.968844 VrefDac_Margin_A0==22
645 03:14:08.973624 DeviceVref_Margin_A0==39
646 03:14:08.974121 VrefDac_Margin_A1==22
647 03:14:08.979079 DeviceVref_Margin_A1==37
648 03:14:08.979584
649 03:14:08.980052 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 03:14:08.980491
651 03:14:09.012862 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000019 00000017 00000019 00000015 00000017 00000015 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
652 03:14:09.013410 2D training succeed
653 03:14:09.018303 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 03:14:09.023914 auto size-- 65535DDR cs0 size: 2048MB
655 03:14:09.024454 DDR cs1 size: 2048MB
656 03:14:09.029517 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 03:14:09.030018 cs0 DataBus test pass
658 03:14:09.035081 cs1 DataBus test pass
659 03:14:09.035582 cs0 AddrBus test pass
660 03:14:09.036046 cs1 AddrBus test pass
661 03:14:09.036480
662 03:14:09.040758 100bdlr_step_size ps== 478
663 03:14:09.041265 result report
664 03:14:09.046286 boot times 0Enable ddr reg access
665 03:14:09.050654 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 03:14:09.064926 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 03:14:09.719798 bl2z: ptr: 05129330, size: 00001e40
668 03:14:09.726707 0.0;M3 CHK:0;cm4_sp_mode 0
669 03:14:09.727281 MVN_1=0x00000000
670 03:14:09.727750 MVN_2=0x00000000
671 03:14:09.738090 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 03:14:09.738630 OPS=0x04
673 03:14:09.739097 ring efuse init
674 03:14:09.743895 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 03:14:09.744478 [0.017319 Inits done]
676 03:14:09.744947 secure task start!
677 03:14:09.751109 high task start!
678 03:14:09.751642 low task start!
679 03:14:09.752131 run into bl31
680 03:14:09.760166 NOTICE: BL31: v1.3(release):4fc40b1
681 03:14:09.767534 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 03:14:09.768091 NOTICE: BL31: G12A normal boot!
683 03:14:09.783425 NOTICE: BL31: BL33 decompress pass
684 03:14:09.788838 ERROR: Error initializing runtime service opteed_fast
685 03:14:10.584619
686 03:14:10.585339
687 03:14:10.590024 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 03:14:10.590574
689 03:14:10.593344 Model: Libre Computer AML-S905D3-CC Solitude
690 03:14:10.739543 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 03:14:10.755130 DRAM: 2 GiB (effective 3.8 GiB)
692 03:14:10.856866 Core: 406 devices, 33 uclasses, devicetree: separate
693 03:14:10.862084 WDT: Not starting watchdog@f0d0
694 03:14:10.887957 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 03:14:10.900098 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 03:14:10.904296 ** Bad device specification mmc 0 **
697 03:14:10.915336 Card did not respond to voltage select! : -110
698 03:14:10.922814 ** Bad device specification mmc 0 **
699 03:14:10.923491 Couldn't find partition mmc 0
700 03:14:10.931041 Card did not respond to voltage select! : -110
701 03:14:10.936789 ** Bad device specification mmc 0 **
702 03:14:10.937692 Couldn't find partition mmc 0
703 03:14:10.941049 Error: could not access storage.
704 03:14:11.238201 Net: eth0: ethernet@ff3f0000
705 03:14:11.238929 starting USB...
706 03:14:11.483739 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 03:14:11.484414 Starting the controller
708 03:14:11.490062 USB XHCI 1.10
709 03:14:13.044947 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 03:14:13.052659 scanning usb for storage devices... 0 Storage Device(s) found
712 03:14:13.104271 Hit any key to stop autoboot: 1
713 03:14:13.105272 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 03:14:13.105954 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 03:14:13.106482 Setting prompt string to ['=>']
716 03:14:13.107012 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 03:14:13.119245 0
718 03:14:13.120870 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 03:14:13.222997 => setenv autoload no
721 03:14:13.223829 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 03:14:13.229985 setenv autoload no
724 03:14:13.331658 => setenv initrd_high 0xffffffff
725 03:14:13.332517 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 03:14:13.336836 setenv initrd_high 0xffffffff
728 03:14:13.438487 => setenv fdt_high 0xffffffff
729 03:14:13.439240 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 03:14:13.442622 setenv fdt_high 0xffffffff
732 03:14:13.545094 => dhcp
733 03:14:13.545829 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 03:14:13.549082 dhcp
735 03:14:14.605411 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 03:14:14.606073 Speed: 1000, full duplex
737 03:14:14.606550 BOOTP broadcast 1
738 03:14:14.616200 DHCP client bound to address 192.168.6.21 (10 ms)
740 03:14:14.717818 => setenv serverip 192.168.6.2
741 03:14:14.718612 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
742 03:14:14.722742 setenv serverip 192.168.6.2
744 03:14:14.824401 => tftpboot 0x01080000 932547/tftp-deploy-io43rhyg/kernel/uImage
745 03:14:14.825234 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
746 03:14:14.831934 tftpboot 0x01080000 932547/tftp-deploy-io43rhyg/kernel/uImage
747 03:14:14.832549 Speed: 1000, full duplex
748 03:14:14.833052 Using ethernet@ff3f0000 device
749 03:14:14.837459 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 03:14:14.843017 Filename '932547/tftp-deploy-io43rhyg/kernel/uImage'.
751 03:14:14.846539 Load address: 0x1080000
752 03:14:14.850278 Loading: * UDP wrong checksum 00000005 0000d614
753 03:14:19.082049 ###################
754 03:14:19.082462 TFTP error: trying to overwrite reserved memory...
756 03:14:19.083320 end: 2.4.3 bootloader-commands (duration 00:00:06) [common]
759 03:14:19.084312 end: 2.4 uboot-commands (duration 00:00:25) [common]
761 03:14:19.085026 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
763 03:14:19.085577 end: 2 uboot-action (duration 00:00:25) [common]
765 03:14:19.086398 Cleaning after the job
766 03:14:19.086720 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932547/tftp-deploy-io43rhyg/ramdisk
767 03:14:19.102899 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932547/tftp-deploy-io43rhyg/kernel
768 03:14:19.144924 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932547/tftp-deploy-io43rhyg/dtb
769 03:14:19.145747 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/932547/tftp-deploy-io43rhyg/modules
770 03:14:19.196186 start: 4.1 power-off (timeout 00:00:30) [common]
771 03:14:19.196858 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
772 03:14:19.229129 >> OK - accepted request
773 03:14:19.231210 Returned 0 in 0 seconds
774 03:14:19.332231 end: 4.1 power-off (duration 00:00:00) [common]
776 03:14:19.333669 start: 4.2 read-feedback (timeout 00:10:00) [common]
777 03:14:19.334514 Listened to connection for namespace 'common' for up to 1s
778 03:14:20.335507 Finalising connection for namespace 'common'
779 03:14:20.336194 Disconnecting from shell: Finalise
780 03:14:20.336597 =>
781 03:14:20.437447 end: 4.2 read-feedback (duration 00:00:01) [common]
782 03:14:20.438070 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/932547
783 03:14:20.817343 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/932547
784 03:14:20.818075 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.