Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 27
- Errors: 0
- Boot result: PASS
- Kernel Errors: 66
1 00:19:03.159074 lava-dispatcher, installed at version: 2024.01
2 00:19:03.159802 start: 0 validate
3 00:19:03.160304 Start time: 2024-11-11 00:19:03.160274+00:00 (UTC)
4 00:19:03.160818 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:19:03.161341 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 00:19:03.206183 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:19:03.206761 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fkernel%2FzImage exists
8 00:19:03.241235 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:19:03.241852 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 00:19:03.274170 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:19:03.274646 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 00:19:03.310596 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 00:19:03.311109 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fmodules.tar.xz exists
14 00:19:03.357886 validate duration: 0.20
16 00:19:03.359396 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:19:03.360009 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:19:03.360580 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:19:03.361518 Not decompressing ramdisk as can be used compressed.
20 00:19:03.362227 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 00:19:03.362698 saving as /var/lib/lava/dispatcher/tmp/973007/tftp-deploy-4p76_5io/ramdisk/initrd.cpio.gz
22 00:19:03.363185 total size: 4775763 (4 MB)
23 00:19:03.407005 progress 0 % (0 MB)
24 00:19:03.414779 progress 5 % (0 MB)
25 00:19:03.422154 progress 10 % (0 MB)
26 00:19:03.429719 progress 15 % (0 MB)
27 00:19:03.438002 progress 20 % (0 MB)
28 00:19:03.444561 progress 25 % (1 MB)
29 00:19:03.448143 progress 30 % (1 MB)
30 00:19:03.452132 progress 35 % (1 MB)
31 00:19:03.455350 progress 40 % (1 MB)
32 00:19:03.458726 progress 45 % (2 MB)
33 00:19:03.461986 progress 50 % (2 MB)
34 00:19:03.465758 progress 55 % (2 MB)
35 00:19:03.469137 progress 60 % (2 MB)
36 00:19:03.472315 progress 65 % (2 MB)
37 00:19:03.476139 progress 70 % (3 MB)
38 00:19:03.479499 progress 75 % (3 MB)
39 00:19:03.482783 progress 80 % (3 MB)
40 00:19:03.486182 progress 85 % (3 MB)
41 00:19:03.489840 progress 90 % (4 MB)
42 00:19:03.492887 progress 95 % (4 MB)
43 00:19:03.495822 progress 100 % (4 MB)
44 00:19:03.496503 4 MB downloaded in 0.13 s (34.17 MB/s)
45 00:19:03.497071 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:19:03.497979 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:19:03.498273 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:19:03.498541 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:19:03.499003 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm/multi_v7_defconfig/clang-15/kernel/zImage
51 00:19:03.499252 saving as /var/lib/lava/dispatcher/tmp/973007/tftp-deploy-4p76_5io/kernel/zImage
52 00:19:03.499459 total size: 12050944 (11 MB)
53 00:19:03.499670 No compression specified
54 00:19:03.537582 progress 0 % (0 MB)
55 00:19:03.545531 progress 5 % (0 MB)
56 00:19:03.553065 progress 10 % (1 MB)
57 00:19:03.560938 progress 15 % (1 MB)
58 00:19:03.568503 progress 20 % (2 MB)
59 00:19:03.576006 progress 25 % (2 MB)
60 00:19:03.583906 progress 30 % (3 MB)
61 00:19:03.591373 progress 35 % (4 MB)
62 00:19:03.599148 progress 40 % (4 MB)
63 00:19:03.606470 progress 45 % (5 MB)
64 00:19:03.613840 progress 50 % (5 MB)
65 00:19:03.621580 progress 55 % (6 MB)
66 00:19:03.628960 progress 60 % (6 MB)
67 00:19:03.636732 progress 65 % (7 MB)
68 00:19:03.644126 progress 70 % (8 MB)
69 00:19:03.651558 progress 75 % (8 MB)
70 00:19:03.659286 progress 80 % (9 MB)
71 00:19:03.666592 progress 85 % (9 MB)
72 00:19:03.674121 progress 90 % (10 MB)
73 00:19:03.681798 progress 95 % (10 MB)
74 00:19:03.688809 progress 100 % (11 MB)
75 00:19:03.689458 11 MB downloaded in 0.19 s (60.49 MB/s)
76 00:19:03.689936 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:19:03.690753 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:19:03.691029 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:19:03.691294 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:19:03.691759 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
82 00:19:03.692041 saving as /var/lib/lava/dispatcher/tmp/973007/tftp-deploy-4p76_5io/dtb/am335x-boneblack.dtb
83 00:19:03.692254 total size: 70568 (0 MB)
84 00:19:03.692467 No compression specified
85 00:19:03.731907 progress 46 % (0 MB)
86 00:19:03.732765 progress 92 % (0 MB)
87 00:19:03.733469 progress 100 % (0 MB)
88 00:19:03.733872 0 MB downloaded in 0.04 s (1.62 MB/s)
89 00:19:03.734332 end: 1.3.1 http-download (duration 00:00:00) [common]
91 00:19:03.735142 end: 1.3 download-retry (duration 00:00:00) [common]
92 00:19:03.735411 start: 1.4 download-retry (timeout 00:10:00) [common]
93 00:19:03.735674 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 00:19:03.736148 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 00:19:03.736402 saving as /var/lib/lava/dispatcher/tmp/973007/tftp-deploy-4p76_5io/nfsrootfs/full.rootfs.tar
96 00:19:03.736607 total size: 117747780 (112 MB)
97 00:19:03.736819 Using unxz to decompress xz
98 00:19:03.779450 progress 0 % (0 MB)
99 00:19:04.497906 progress 5 % (5 MB)
100 00:19:05.238192 progress 10 % (11 MB)
101 00:19:06.001875 progress 15 % (16 MB)
102 00:19:06.713308 progress 20 % (22 MB)
103 00:19:07.287400 progress 25 % (28 MB)
104 00:19:08.084981 progress 30 % (33 MB)
105 00:19:08.897045 progress 35 % (39 MB)
106 00:19:09.242492 progress 40 % (44 MB)
107 00:19:09.592656 progress 45 % (50 MB)
108 00:19:10.261799 progress 50 % (56 MB)
109 00:19:11.073473 progress 55 % (61 MB)
110 00:19:11.802264 progress 60 % (67 MB)
111 00:19:12.515757 progress 65 % (73 MB)
112 00:19:13.279788 progress 70 % (78 MB)
113 00:19:14.039516 progress 75 % (84 MB)
114 00:19:14.777563 progress 80 % (89 MB)
115 00:19:15.531064 progress 85 % (95 MB)
116 00:19:16.350115 progress 90 % (101 MB)
117 00:19:17.122827 progress 95 % (106 MB)
118 00:19:17.943880 progress 100 % (112 MB)
119 00:19:17.956956 112 MB downloaded in 14.22 s (7.90 MB/s)
120 00:19:17.957805 end: 1.4.1 http-download (duration 00:00:14) [common]
122 00:19:17.959397 end: 1.4 download-retry (duration 00:00:14) [common]
123 00:19:17.959909 start: 1.5 download-retry (timeout 00:09:45) [common]
124 00:19:17.960479 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 00:19:17.961264 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm/multi_v7_defconfig/clang-15/modules.tar.xz
126 00:19:17.961711 saving as /var/lib/lava/dispatcher/tmp/973007/tftp-deploy-4p76_5io/modules/modules.tar
127 00:19:17.962119 total size: 6920820 (6 MB)
128 00:19:17.962528 Using unxz to decompress xz
129 00:19:18.008938 progress 0 % (0 MB)
130 00:19:18.043970 progress 5 % (0 MB)
131 00:19:18.091518 progress 10 % (0 MB)
132 00:19:18.136358 progress 15 % (1 MB)
133 00:19:18.187531 progress 20 % (1 MB)
134 00:19:18.234374 progress 25 % (1 MB)
135 00:19:18.283217 progress 30 % (2 MB)
136 00:19:18.326706 progress 35 % (2 MB)
137 00:19:18.375123 progress 40 % (2 MB)
138 00:19:18.423653 progress 45 % (3 MB)
139 00:19:18.468235 progress 50 % (3 MB)
140 00:19:18.516083 progress 55 % (3 MB)
141 00:19:18.562596 progress 60 % (3 MB)
142 00:19:18.609831 progress 65 % (4 MB)
143 00:19:18.654743 progress 70 % (4 MB)
144 00:19:18.705323 progress 75 % (4 MB)
145 00:19:18.749214 progress 80 % (5 MB)
146 00:19:18.798418 progress 85 % (5 MB)
147 00:19:18.847284 progress 90 % (5 MB)
148 00:19:18.895366 progress 95 % (6 MB)
149 00:19:18.954828 progress 100 % (6 MB)
150 00:19:18.968651 6 MB downloaded in 1.01 s (6.56 MB/s)
151 00:19:18.969250 end: 1.5.1 http-download (duration 00:00:01) [common]
153 00:19:18.970088 end: 1.5 download-retry (duration 00:00:01) [common]
154 00:19:18.970362 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 00:19:18.970630 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 00:19:35.065957 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/973007/extract-nfsrootfs-6zno0km2
157 00:19:35.066564 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 00:19:35.066855 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 00:19:35.067593 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04
160 00:19:35.068070 makedir: /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin
161 00:19:35.068407 makedir: /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/tests
162 00:19:35.068719 makedir: /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/results
163 00:19:35.069047 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-add-keys
164 00:19:35.069593 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-add-sources
165 00:19:35.070142 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-background-process-start
166 00:19:35.070635 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-background-process-stop
167 00:19:35.071146 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-common-functions
168 00:19:35.071621 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-echo-ipv4
169 00:19:35.072122 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-install-packages
170 00:19:35.072601 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-installed-packages
171 00:19:35.073066 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-os-build
172 00:19:35.073547 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-probe-channel
173 00:19:35.074033 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-probe-ip
174 00:19:35.074501 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-target-ip
175 00:19:35.074962 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-target-mac
176 00:19:35.075427 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-target-storage
177 00:19:35.075902 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-test-case
178 00:19:35.076461 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-test-event
179 00:19:35.076935 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-test-feedback
180 00:19:35.077414 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-test-raise
181 00:19:35.077889 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-test-reference
182 00:19:35.078355 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-test-runner
183 00:19:35.078820 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-test-set
184 00:19:35.079281 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-test-shell
185 00:19:35.079755 Updating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-add-keys (debian)
186 00:19:35.080308 Updating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-add-sources (debian)
187 00:19:35.080824 Updating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-install-packages (debian)
188 00:19:35.081314 Updating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-installed-packages (debian)
189 00:19:35.081790 Updating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/bin/lava-os-build (debian)
190 00:19:35.082208 Creating /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/environment
191 00:19:35.082562 LAVA metadata
192 00:19:35.082812 - LAVA_JOB_ID=973007
193 00:19:35.083027 - LAVA_DISPATCHER_IP=192.168.6.2
194 00:19:35.083373 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 00:19:35.084334 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 00:19:35.084637 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 00:19:35.084840 skipped lava-vland-overlay
198 00:19:35.085078 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 00:19:35.085329 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 00:19:35.085543 skipped lava-multinode-overlay
201 00:19:35.085781 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 00:19:35.086030 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 00:19:35.086271 Loading test definitions
204 00:19:35.086546 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 00:19:35.086762 Using /lava-973007 at stage 0
206 00:19:35.087814 uuid=973007_1.6.2.4.1 testdef=None
207 00:19:35.088147 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 00:19:35.088412 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 00:19:35.089943 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 00:19:35.090716 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 00:19:35.092727 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 00:19:35.093537 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 00:19:35.095315 runner path: /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/0/tests/0_timesync-off test_uuid 973007_1.6.2.4.1
216 00:19:35.095841 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 00:19:35.096709 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 00:19:35.096930 Using /lava-973007 at stage 0
220 00:19:35.097277 Fetching tests from https://github.com/kernelci/test-definitions.git
221 00:19:35.097561 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/0/tests/1_kselftest-dt'
222 00:19:38.935289 Running '/usr/bin/git checkout kernelci.org
223 00:19:39.382619 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 00:19:39.384102 uuid=973007_1.6.2.4.5 testdef=None
225 00:19:39.384709 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 00:19:39.386163 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 00:19:39.391503 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 00:19:39.393112 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 00:19:39.400187 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 00:19:39.401834 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 00:19:39.408782 runner path: /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/0/tests/1_kselftest-dt test_uuid 973007_1.6.2.4.5
235 00:19:39.409313 BOARD='beaglebone-black'
236 00:19:39.409714 BRANCH='mainline'
237 00:19:39.410105 SKIPFILE='/dev/null'
238 00:19:39.410495 SKIP_INSTALL='True'
239 00:19:39.410880 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc7/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
240 00:19:39.411274 TST_CASENAME=''
241 00:19:39.411660 TST_CMDFILES='dt'
242 00:19:39.412691 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 00:19:39.414230 Creating lava-test-runner.conf files
245 00:19:39.414631 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/973007/lava-overlay-h27hae04/lava-973007/0 for stage 0
246 00:19:39.415267 - 0_timesync-off
247 00:19:39.415722 - 1_kselftest-dt
248 00:19:39.416390 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 00:19:39.416938 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 00:20:02.614142 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 00:20:02.614610 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 00:20:02.614917 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 00:20:02.615234 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 00:20:02.615535 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 00:20:02.985347 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 00:20:02.985828 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 00:20:02.986082 extracting modules file /var/lib/lava/dispatcher/tmp/973007/tftp-deploy-4p76_5io/modules/modules.tar to /var/lib/lava/dispatcher/tmp/973007/extract-nfsrootfs-6zno0km2
258 00:20:03.855380 extracting modules file /var/lib/lava/dispatcher/tmp/973007/tftp-deploy-4p76_5io/modules/modules.tar to /var/lib/lava/dispatcher/tmp/973007/extract-overlay-ramdisk-v268fy2h/ramdisk
259 00:20:04.850027 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 00:20:04.850505 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 00:20:04.850781 [common] Applying overlay to NFS
262 00:20:04.850998 [common] Applying overlay /var/lib/lava/dispatcher/tmp/973007/compress-overlay-9gxp7j0p/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/973007/extract-nfsrootfs-6zno0km2
263 00:20:07.578329 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 00:20:07.578816 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 00:20:07.579094 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 00:20:07.579373 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 00:20:07.579627 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 00:20:07.579884 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 00:20:07.580170 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 00:20:07.580431 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 00:20:07.580683 Building ramdisk /var/lib/lava/dispatcher/tmp/973007/extract-overlay-ramdisk-v268fy2h/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/973007/extract-overlay-ramdisk-v268fy2h/ramdisk
272 00:20:08.616743 >> 79013 blocks
273 00:20:13.672852 Adding RAMdisk u-boot header.
274 00:20:13.673555 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/973007/extract-overlay-ramdisk-v268fy2h/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/973007/extract-overlay-ramdisk-v268fy2h/ramdisk.cpio.gz.uboot
275 00:20:13.854140 output: Image Name:
276 00:20:13.854567 output: Created: Mon Nov 11 00:20:13 2024
277 00:20:13.855002 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 00:20:13.855423 output: Data Size: 15350734 Bytes = 14990.95 KiB = 14.64 MiB
279 00:20:13.855840 output: Load Address: 00000000
280 00:20:13.856312 output: Entry Point: 00000000
281 00:20:13.856724 output:
282 00:20:13.857827 rename /var/lib/lava/dispatcher/tmp/973007/extract-overlay-ramdisk-v268fy2h/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/973007/tftp-deploy-4p76_5io/ramdisk/ramdisk.cpio.gz.uboot
283 00:20:13.858550 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 00:20:13.859105 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 00:20:13.859646 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 00:20:13.860148 No LXC device requested
287 00:20:13.860667 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 00:20:13.861191 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 00:20:13.861698 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 00:20:13.862120 Checking files for TFTP limit of 4294967296 bytes.
291 00:20:13.864813 end: 1 tftp-deploy (duration 00:01:11) [common]
292 00:20:13.865412 start: 2 uboot-action (timeout 00:05:00) [common]
293 00:20:13.865960 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 00:20:13.866472 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 00:20:13.866991 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 00:20:13.867753 substitutions:
297 00:20:13.868212 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 00:20:13.868626 - {DTB_ADDR}: 0x88000000
299 00:20:13.869029 - {DTB}: 973007/tftp-deploy-4p76_5io/dtb/am335x-boneblack.dtb
300 00:20:13.869431 - {INITRD}: 973007/tftp-deploy-4p76_5io/ramdisk/ramdisk.cpio.gz.uboot
301 00:20:13.869829 - {KERNEL_ADDR}: 0x82000000
302 00:20:13.870226 - {KERNEL}: 973007/tftp-deploy-4p76_5io/kernel/zImage
303 00:20:13.870623 - {LAVA_MAC}: None
304 00:20:13.871062 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/973007/extract-nfsrootfs-6zno0km2
305 00:20:13.871467 - {NFS_SERVER_IP}: 192.168.6.2
306 00:20:13.871866 - {PRESEED_CONFIG}: None
307 00:20:13.872299 - {PRESEED_LOCAL}: None
308 00:20:13.872697 - {RAMDISK_ADDR}: 0x83000000
309 00:20:13.873091 - {RAMDISK}: 973007/tftp-deploy-4p76_5io/ramdisk/ramdisk.cpio.gz.uboot
310 00:20:13.873490 - {ROOT_PART}: None
311 00:20:13.873882 - {ROOT}: None
312 00:20:13.874274 - {SERVER_IP}: 192.168.6.2
313 00:20:13.874664 - {TEE_ADDR}: 0x83000000
314 00:20:13.875051 - {TEE}: None
315 00:20:13.875443 Parsed boot commands:
316 00:20:13.875824 - setenv autoload no
317 00:20:13.876286 - setenv initrd_high 0xffffffff
318 00:20:13.876690 - setenv fdt_high 0xffffffff
319 00:20:13.877082 - dhcp
320 00:20:13.877471 - setenv serverip 192.168.6.2
321 00:20:13.877861 - tftp 0x82000000 973007/tftp-deploy-4p76_5io/kernel/zImage
322 00:20:13.878254 - tftp 0x83000000 973007/tftp-deploy-4p76_5io/ramdisk/ramdisk.cpio.gz.uboot
323 00:20:13.878645 - setenv initrd_size ${filesize}
324 00:20:13.879034 - tftp 0x88000000 973007/tftp-deploy-4p76_5io/dtb/am335x-boneblack.dtb
325 00:20:13.879424 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/973007/extract-nfsrootfs-6zno0km2,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 00:20:13.879826 - bootz 0x82000000 0x83000000 0x88000000
327 00:20:13.880374 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 00:20:13.881882 start: 2.3 connect-device (timeout 00:05:00) [common]
330 00:20:13.882311 [common] connect-device Connecting to device using 'telnet conserv3 3001'
331 00:20:13.897991 Setting prompt string to ['lava-test: # ']
332 00:20:13.899471 end: 2.3 connect-device (duration 00:00:00) [common]
333 00:20:13.900117 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 00:20:13.900687 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 00:20:13.901219 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 00:20:13.902386 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-04'
337 00:20:13.941740 >> OK - accepted request
338 00:20:13.943862 Returned 0 in 0 seconds
339 00:20:14.045058 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 00:20:14.046688 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 00:20:14.047255 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 00:20:14.047789 Setting prompt string to ['Hit any key to stop autoboot']
344 00:20:14.048313 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 00:20:14.049865 Trying 192.168.56.22...
346 00:20:14.050353 Connected to conserv3.
347 00:20:14.050772 Escape character is '^]'.
348 00:20:14.051185
349 00:20:14.051611 ser2net port telnet,3001 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 00:20:14.052068
351 00:20:50.865227
352 00:20:50.872100 U-Boot SPL 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
353 00:20:50.872607 Trying to boot from MMC1
354 00:20:51.448012
355 00:20:51.448437
356 00:20:51.453518 U-Boot 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
357 00:20:51.453789
358 00:20:51.454046 CPU : AM335X-GP rev 2.0
359 00:20:51.458458 Model: TI AM335x BeagleBone Black
360 00:20:51.458749 DRAM: 512 MiB
361 00:20:51.542269 Core: 160 devices, 18 uclasses, devicetree: separate
362 00:20:51.556899 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
363 00:20:51.957977 NAND: 0 MiB
364 00:20:51.967804 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
365 00:20:52.042697 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
366 00:20:52.063849 <ethaddr> not set. Validating first E-fuse MAC
367 00:20:52.093600 Net: eth2: ethernet@4a100000, eth3: usb_ether
369 00:20:52.152112 Hit any key to stop autoboot: 2
370 00:20:52.152952 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
371 00:20:52.153535 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
372 00:20:52.154015 Setting prompt string to ['=>']
373 00:20:52.154489 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
374 00:20:52.161963 0
375 00:20:52.162749 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
376 00:20:52.163041 Sending with 10 millisecond of delay
378 00:20:53.297370 => setenv autoload no
379 00:20:53.308110 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
380 00:20:53.312854 setenv autoload no
381 00:20:53.313574 Sending with 10 millisecond of delay
383 00:20:55.110519 => setenv initrd_high 0xffffffff
384 00:20:55.121244 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
385 00:20:55.122044 setenv initrd_high 0xffffffff
386 00:20:55.122740 Sending with 10 millisecond of delay
388 00:20:56.738787 => setenv fdt_high 0xffffffff
389 00:20:56.749575 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
390 00:20:56.750430 setenv fdt_high 0xffffffff
391 00:20:56.751114 Sending with 10 millisecond of delay
393 00:20:57.042793 => dhcp
394 00:20:57.053487 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
395 00:20:57.054251 dhcp
396 00:20:57.056044 link up on port 0, speed 100, full duplex
397 00:20:57.056479 BOOTP broadcast 1
398 00:20:57.133636 DHCP client bound to address 192.168.6.16 (75 ms)
399 00:20:57.134367 Sending with 10 millisecond of delay
401 00:20:58.813778 => setenv serverip 192.168.6.2
402 00:20:58.824415 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
403 00:20:58.825056 setenv serverip 192.168.6.2
404 00:20:58.825600 Sending with 10 millisecond of delay
406 00:21:02.308600 => tftp 0x82000000 973007/tftp-deploy-4p76_5io/kernel/zImage
407 00:21:02.321995 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
408 00:21:02.322969 tftp 0x82000000 973007/tftp-deploy-4p76_5io/kernel/zImage
409 00:21:02.323454 link up on port 0, speed 100, full duplex
410 00:21:02.324298 Using ethernet@4a100000 device
411 00:21:02.329696 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
412 00:21:02.330167 Filename '973007/tftp-deploy-4p76_5io/kernel/zImage'.
413 00:21:02.336749 Load address: 0x82000000
414 00:21:04.600165 Loading: *################################################## 11.5 MiB
415 00:21:04.600721 5.1 MiB/s
416 00:21:04.601028 done
417 00:21:04.604234 Bytes transferred = 12050944 (b7e200 hex)
418 00:21:04.604821 Sending with 10 millisecond of delay
420 00:21:09.053724 => tftp 0x83000000 973007/tftp-deploy-4p76_5io/ramdisk/ramdisk.cpio.gz.uboot
421 00:21:09.064268 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
422 00:21:09.064786 tftp 0x83000000 973007/tftp-deploy-4p76_5io/ramdisk/ramdisk.cpio.gz.uboot
423 00:21:09.065028 link up on port 0, speed 100, full duplex
424 00:21:09.069312 Using ethernet@4a100000 device
425 00:21:09.074996 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
426 00:21:09.078297 Filename '973007/tftp-deploy-4p76_5io/ramdisk/ramdisk.cpio.gz.uboot'.
427 00:21:09.082515 Load address: 0x83000000
428 00:21:11.934827 Loading: *################################################## 14.6 MiB
429 00:21:11.935261 5.1 MiB/s
430 00:21:11.935505 done
431 00:21:11.939082 Bytes transferred = 15350798 (ea3c0e hex)
432 00:21:11.939660 Sending with 10 millisecond of delay
434 00:21:13.798152 => setenv initrd_size ${filesize}
435 00:21:13.808732 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
436 00:21:13.809425 setenv initrd_size ${filesize}
437 00:21:13.809945 Sending with 10 millisecond of delay
439 00:21:17.956567 => tftp 0x88000000 973007/tftp-deploy-4p76_5io/dtb/am335x-boneblack.dtb
440 00:21:17.967401 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:56)
441 00:21:17.968333 tftp 0x88000000 973007/tftp-deploy-4p76_5io/dtb/am335x-boneblack.dtb
442 00:21:17.968785 link up on port 0, speed 100, full duplex
443 00:21:17.972553 Using ethernet@4a100000 device
444 00:21:17.977998 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
445 00:21:17.981367 Filename '973007/tftp-deploy-4p76_5io/dtb/am335x-boneblack.dtb'.
446 00:21:17.985022 Load address: 0x88000000
447 00:21:18.000552 Loading: *################################################## 68.9 KiB
448 00:21:18.005471 4 MiB/s
449 00:21:18.006067 done
450 00:21:18.010108 Bytes transferred = 70568 (113a8 hex)
451 00:21:18.010943 Sending with 10 millisecond of delay
453 00:21:31.190667 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/973007/extract-nfsrootfs-6zno0km2,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
454 00:21:31.202192 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:43)
455 00:21:31.203048 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/973007/extract-nfsrootfs-6zno0km2,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
456 00:21:31.203750 Sending with 10 millisecond of delay
458 00:21:33.542485 => bootz 0x82000000 0x83000000 0x88000000
459 00:21:33.553286 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
460 00:21:33.553841 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:40)
461 00:21:33.554832 bootz 0x82000000 0x83000000 0x88000000
462 00:21:33.555290 Kernel image @ 0x82000000 [ 0x000000 - 0xb7e200 ]
463 00:21:33.555784 ## Loading init Ramdisk from Legacy Image at 83000000 ...
464 00:21:33.560865 Image Name:
465 00:21:33.561331 Created: 2024-11-11 0:20:13 UTC
466 00:21:33.566529 Image Type: ARM Linux RAMDisk Image (uncompressed)
467 00:21:33.572088 Data Size: 15350734 Bytes = 14.6 MiB
468 00:21:33.572563 Load Address: 00000000
469 00:21:33.577644 Entry Point: 00000000
470 00:21:33.752934 Verifying Checksum ... OK
471 00:21:33.753545 ## Flattened Device Tree blob at 88000000
472 00:21:33.759277 Booting using the fdt blob at 0x88000000
473 00:21:33.759815 Working FDT set to 88000000
474 00:21:33.764953 Using Device Tree in place at 88000000, end 880143a7
475 00:21:33.769255 Working FDT set to 88000000
476 00:21:33.782580
477 00:21:33.783140 Starting kernel ...
478 00:21:33.783569
479 00:21:33.784494 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
480 00:21:33.785120 start: 2.4.4 auto-login-action (timeout 00:03:40) [common]
481 00:21:33.785599 Setting prompt string to ['Linux version [0-9]']
482 00:21:33.786058 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
483 00:21:33.786530 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
484 00:21:34.675851 [ 0.000000] Booting Linux on physical CPU 0x0
485 00:21:34.681995 start: 2.4.4.1 login-action (timeout 00:03:39) [common]
486 00:21:34.682684 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
487 00:21:34.683203 Setting prompt string to []
488 00:21:34.683740 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
489 00:21:34.684304 Using line separator: #'\n'#
490 00:21:34.684761 No login prompt set.
491 00:21:34.685242 Parsing kernel messages
492 00:21:34.685682 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
493 00:21:34.686563 [login-action] Waiting for messages, (timeout 00:03:39)
494 00:21:34.687064 Waiting using forced prompt support (timeout 00:01:50)
495 00:21:34.695902 [ 0.000000] Linux version 6.12.0-rc7 (KernelCI@build-j372177-arm-clang-15-multi-v7-defconfig-sckr8) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Sun Nov 10 23:10:32 UTC 2024
496 00:21:34.701664 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
497 00:21:34.707289 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
498 00:21:34.716294 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
499 00:21:34.721923 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
500 00:21:34.727737 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
501 00:21:34.730797 [ 0.000000] Memory policy: Data cache writeback
502 00:21:34.737365 [ 0.000000] efi: UEFI not found.
503 00:21:34.746346 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
504 00:21:34.746980 [ 0.000000] Zone ranges:
505 00:21:34.752075 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
506 00:21:34.757875 [ 0.000000] Normal empty
507 00:21:34.758482 [ 0.000000] HighMem empty
508 00:21:34.763466 [ 0.000000] Movable zone start for each node
509 00:21:34.769184 [ 0.000000] Early memory node ranges
510 00:21:34.774928 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
511 00:21:34.781215 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
512 00:21:34.799420 [ 0.000000] CPU: All CPU(s) started in SVC mode.
513 00:21:34.805033 [ 0.000000] AM335X ES2.0 (sgx neon)
514 00:21:34.816698 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
515 00:21:34.834442 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/973007/extract-nfsrootfs-6zno0km2,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
516 00:21:34.845968 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
517 00:21:34.851694 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
518 00:21:34.857408 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
519 00:21:34.867527 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
520 00:21:34.896698 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
521 00:21:34.902661 <6>[ 0.000000] trace event string verifier disabled
522 00:21:34.903182 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
523 00:21:34.908458 <6>[ 0.000000] rcu: RCU event tracing is enabled.
524 00:21:34.919851 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
525 00:21:34.925613 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
526 00:21:34.932846 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
527 00:21:34.947863 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
528 00:21:34.965600 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
529 00:21:34.972286 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
530 00:21:35.071752 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
531 00:21:35.083176 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
532 00:21:35.090013 <6>[ 0.008338] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
533 00:21:35.103084 <6>[ 0.019193] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
534 00:21:35.110666 <6>[ 0.034232] Console: colour dummy device 80x30
535 00:21:35.116752 Matched prompt #6: WARNING:
536 00:21:35.117307 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
537 00:21:35.122142 <3>[ 0.039132] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
538 00:21:35.127896 <3>[ 0.046208] This ensures that you still see kernel messages. Please
539 00:21:35.130869 <3>[ 0.052941] update your kernel commandline.
540 00:21:35.171657 <6>[ 0.057555] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
541 00:21:35.177308 <6>[ 0.096200] CPU: Testing write buffer coherency: ok
542 00:21:35.183293 <6>[ 0.101573] CPU0: Spectre v2: using BPIALL workaround
543 00:21:35.183865 <6>[ 0.107041] pid_max: default: 32768 minimum: 301
544 00:21:35.194778 <6>[ 0.112235] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
545 00:21:35.201859 <6>[ 0.120062] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
546 00:21:35.208863 <6>[ 0.129526] CPU0: thread -1, cpu 0, socket -1, mpidr 0
547 00:21:35.217296 <6>[ 0.136494] Setting up static identity map for 0x80300000 - 0x803000ac
548 00:21:35.223126 <6>[ 0.146196] rcu: Hierarchical SRCU implementation.
549 00:21:35.229811 <6>[ 0.151485] rcu: Max phase no-delay instances is 1000.
550 00:21:35.239615 <6>[ 0.162854] EFI services will not be available.
551 00:21:35.245372 <6>[ 0.168146] smp: Bringing up secondary CPUs ...
552 00:21:35.251081 <6>[ 0.173203] smp: Brought up 1 node, 1 CPU
553 00:21:35.259383 <6>[ 0.177605] SMP: Total of 1 processors activated (996.14 BogoMIPS).
554 00:21:35.265346 <6>[ 0.184376] CPU: All CPU(s) started in SVC mode.
555 00:21:35.277487 <6>[ 0.189585] Memory: 404432K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50616K reserved, 65536K cma-reserved, 0K highmem)
556 00:21:35.283235 <6>[ 0.205877] devtmpfs: initialized
557 00:21:35.306221 <6>[ 0.223723] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
558 00:21:35.314526 <6>[ 0.232339] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
559 00:21:35.322964 <6>[ 0.242802] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
560 00:21:35.334410 <6>[ 0.255081] pinctrl core: initialized pinctrl subsystem
561 00:21:35.343928 <6>[ 0.265934] DMI not present or invalid.
562 00:21:35.352318 <6>[ 0.271838] NET: Registered PF_NETLINK/PF_ROUTE protocol family
563 00:21:35.361821 <6>[ 0.280855] DMA: preallocated 256 KiB pool for atomic coherent allocations
564 00:21:35.377082 <6>[ 0.292553] thermal_sys: Registered thermal governor 'step_wise'
565 00:21:35.377735 <6>[ 0.292725] cpuidle: using governor menu
566 00:21:35.404698 <6>[ 0.328058] No ATAGs?
567 00:21:35.410748 <6>[ 0.330800] hw-breakpoint: debug architecture 0x4 unsupported.
568 00:21:35.421283 <6>[ 0.342982] Serial: AMBA PL011 UART driver
569 00:21:35.451856 <6>[ 0.375286] iommu: Default domain type: Translated
570 00:21:35.460867 <6>[ 0.380635] iommu: DMA domain TLB invalidation policy: strict mode
571 00:21:35.487727 <5>[ 0.410634] SCSI subsystem initialized
572 00:21:35.493690 <6>[ 0.415556] usbcore: registered new interface driver usbfs
573 00:21:35.499419 <6>[ 0.421627] usbcore: registered new interface driver hub
574 00:21:35.508162 <6>[ 0.427413] usbcore: registered new device driver usb
575 00:21:35.513865 <6>[ 0.433988] pps_core: LinuxPPS API ver. 1 registered
576 00:21:35.524894 <6>[ 0.439377] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
577 00:21:35.525555 <6>[ 0.449108] PTP clock support registered
578 00:21:35.529719 <6>[ 0.453579] EDAC MC: Ver: 3.0.0
579 00:21:35.587005 <6>[ 0.508953] scmi_core: SCMI protocol bus registered
580 00:21:35.592889 <6>[ 0.517155] vgaarb: loaded
581 00:21:35.614931 <6>[ 0.538731] clocksource: Switched to clocksource dmtimer
582 00:21:35.633815 <6>[ 0.557062] NET: Registered PF_INET protocol family
583 00:21:35.646590 <6>[ 0.562760] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
584 00:21:35.652414 <6>[ 0.571792] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
585 00:21:35.663839 <6>[ 0.580726] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
586 00:21:35.669693 <6>[ 0.588991] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
587 00:21:35.681180 <6>[ 0.597261] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
588 00:21:35.687041 <6>[ 0.604978] TCP: Hash tables configured (established 4096 bind 4096)
589 00:21:35.692773 <6>[ 0.611893] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
590 00:21:35.698695 <6>[ 0.618933] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
591 00:21:35.705279 <6>[ 0.626519] NET: Registered PF_UNIX/PF_LOCAL protocol family
592 00:21:35.799319 <6>[ 0.717225] RPC: Registered named UNIX socket transport module.
593 00:21:35.799748 <6>[ 0.723672] RPC: Registered udp transport module.
594 00:21:35.805050 <6>[ 0.728801] RPC: Registered tcp transport module.
595 00:21:35.810847 <6>[ 0.733906] RPC: Registered tcp-with-tls transport module.
596 00:21:35.823858 <6>[ 0.739841] RPC: Registered tcp NFSv4.1 backchannel transport module.
597 00:21:35.824266 <6>[ 0.746747] PCI: CLS 0 bytes, default 64
598 00:21:35.831047 <5>[ 0.752625] Initialise system trusted keyrings
599 00:21:35.853092 <6>[ 0.773691] Trying to unpack rootfs image as initramfs...
600 00:21:35.911836 <6>[ 0.829220] workingset: timestamp_bits=30 max_order=17 bucket_order=0
601 00:21:35.916645 <6>[ 0.836752] squashfs: version 4.0 (2009/01/31) Phillip Lougher
602 00:21:35.965881 <5>[ 0.889462] NFS: Registering the id_resolver key type
603 00:21:35.971677 <5>[ 0.895050] Key type id_resolver registered
604 00:21:35.977489 <5>[ 0.899760] Key type id_legacy registered
605 00:21:35.983254 <6>[ 0.904203] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
606 00:21:35.992836 <6>[ 0.911407] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
607 00:21:36.055461 <5>[ 0.979077] Key type asymmetric registered
608 00:21:36.061317 <5>[ 0.983606] Asymmetric key parser 'x509' registered
609 00:21:36.072822 <6>[ 0.989095] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
610 00:21:36.073197 <6>[ 0.996982] io scheduler mq-deadline registered
611 00:21:36.078612 <6>[ 1.001945] io scheduler kyber registered
612 00:21:36.084232 <6>[ 1.006398] io scheduler bfq registered
613 00:21:36.198101 <6>[ 1.118940] ledtrig-cpu: registered to indicate activity on CPUs
614 00:21:36.487224 <6>[ 1.407069] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
615 00:21:36.529461 <6>[ 1.452792] msm_serial: driver initialized
616 00:21:36.535622 <6>[ 1.457578] SuperH (H)SCI(F) driver initialized
617 00:21:36.541361 <6>[ 1.462944] STMicroelectronics ASC driver initialized
618 00:21:36.546577 <6>[ 1.468552] STM32 USART driver initialized
619 00:21:36.666369 <6>[ 1.589245] brd: module loaded
620 00:21:36.691239 <6>[ 1.614150] loop: module loaded
621 00:21:36.751914 <6>[ 1.674686] CAN device driver interface
622 00:21:36.758377 <6>[ 1.679911] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
623 00:21:36.764213 <6>[ 1.686819] e1000e: Intel(R) PRO/1000 Network Driver
624 00:21:36.770111 <6>[ 1.692268] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
625 00:21:36.775857 <6>[ 1.698715] igb: Intel(R) Gigabit Ethernet Network Driver
626 00:21:36.783170 <6>[ 1.704538] igb: Copyright (c) 2007-2014 Intel Corporation.
627 00:21:36.795859 <6>[ 1.713678] pegasus: Pegasus/Pegasus II USB Ethernet driver
628 00:21:36.801670 <6>[ 1.719834] usbcore: registered new interface driver pegasus
629 00:21:36.807460 <6>[ 1.725956] usbcore: registered new interface driver asix
630 00:21:36.813193 <6>[ 1.731853] usbcore: registered new interface driver ax88179_178a
631 00:21:36.818974 <6>[ 1.738421] usbcore: registered new interface driver cdc_ether
632 00:21:36.824826 <6>[ 1.744752] usbcore: registered new interface driver smsc75xx
633 00:21:36.830513 <6>[ 1.750986] usbcore: registered new interface driver smsc95xx
634 00:21:36.836348 <6>[ 1.757199] usbcore: registered new interface driver net1080
635 00:21:36.842113 <6>[ 1.763340] usbcore: registered new interface driver cdc_subset
636 00:21:36.847928 <6>[ 1.769750] usbcore: registered new interface driver zaurus
637 00:21:36.856224 <6>[ 1.775790] usbcore: registered new interface driver cdc_ncm
638 00:21:36.865309 <6>[ 1.785218] usbcore: registered new interface driver usb-storage
639 00:21:36.874628 <6>[ 1.796253] i2c_dev: i2c /dev entries driver
640 00:21:36.894324 <5>[ 1.814464] cpuidle: enable-method property 'ti,am3352' found operations
641 00:21:36.907828 <6>[ 1.824004] sdhci: Secure Digital Host Controller Interface driver
642 00:21:36.908410 <6>[ 1.830776] sdhci: Copyright(c) Pierre Ossman
643 00:21:36.915098 <6>[ 1.837137] Synopsys Designware Multimedia Card Interface Driver
644 00:21:36.925007 <6>[ 1.845093] sdhci-pltfm: SDHCI platform and OF driver helper
645 00:21:36.937902 <6>[ 1.854926] usbcore: registered new interface driver usbhid
646 00:21:36.938461 <6>[ 1.861051] usbhid: USB HID core driver
647 00:21:36.951662 <6>[ 1.872610] NET: Registered PF_INET6 protocol family
648 00:21:37.396600 <6>[ 2.320162] Segment Routing with IPv6
649 00:21:37.402502 <6>[ 2.324314] In-situ OAM (IOAM) with IPv6
650 00:21:37.409358 <6>[ 2.328855] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
651 00:21:37.416714 <6>[ 2.336181] NET: Registered PF_PACKET protocol family
652 00:21:37.422452 <6>[ 2.341754] can: controller area network core
653 00:21:37.422976 <6>[ 2.346581] NET: Registered PF_CAN protocol family
654 00:21:37.428203 <6>[ 2.351813] can: raw protocol
655 00:21:37.434046 <6>[ 2.355138] can: broadcast manager protocol
656 00:21:37.440930 <6>[ 2.359736] can: netlink gateway - max_hops=1
657 00:21:37.441461 <5>[ 2.365243] Key type dns_resolver registered
658 00:21:37.446759 <6>[ 2.370333] ThumbEE CPU extension supported.
659 00:21:37.452930 <5>[ 2.375025] Registering SWP/SWPB emulation handler
660 00:21:37.461062 <3>[ 2.380722] omap_voltage_late_init: Voltage driver support not added
661 00:21:37.651489 <5>[ 2.572723] Loading compiled-in X.509 certificates
662 00:21:37.777754 <6>[ 2.688365] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
663 00:21:37.784937 <6>[ 2.705103] pinctrl-single 44e10800.pinmux: 142 pins, size 568
664 00:21:37.810903 <3>[ 2.729378] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
665 00:21:38.030540 <3>[ 2.949104] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
666 00:21:38.226812 <6>[ 3.149436] OMAP GPIO hardware version 0.1
667 00:21:38.247715 <6>[ 3.168486] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
668 00:21:38.349925 <4>[ 3.270411] at24 2-0054: supply vcc not found, using dummy regulator
669 00:21:38.385161 <4>[ 3.305623] at24 2-0055: supply vcc not found, using dummy regulator
670 00:21:38.421853 <4>[ 3.342308] at24 2-0056: supply vcc not found, using dummy regulator
671 00:21:38.462415 <4>[ 3.382644] at24 2-0057: supply vcc not found, using dummy regulator
672 00:21:38.500288 <6>[ 3.421569] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
673 00:21:38.558179 <3>[ 3.475446] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
674 00:21:38.582859 <6>[ 3.496669] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
675 00:21:38.604580 <4>[ 3.523731] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
676 00:21:38.620305 <4>[ 3.539609] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
677 00:21:38.709852 <6>[ 3.629618] omap_rng 48310000.rng: Random Number Generator ver. 20
678 00:21:38.734167 <5>[ 3.656678] random: crng init done
679 00:21:38.776348 <6>[ 3.699636] Freeing initrd memory: 14992K
680 00:21:38.786020 <6>[ 3.704273] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
681 00:21:38.843881 <6>[ 3.761198] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
682 00:21:38.849783 <6>[ 3.771559] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
683 00:21:38.857972 <6>[ 3.778900] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
684 00:21:38.869374 <6>[ 3.786364] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
685 00:21:38.880916 <6>[ 3.794500] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
686 00:21:38.888464 <6>[ 3.806142] cpsw-switch 4a100000.switch: Detected MACID = c8:a0:30:c2:c5:7d
687 00:21:38.899389 <5>[ 3.815254] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
688 00:21:38.927824 <3>[ 3.845702] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
689 00:21:38.933673 <6>[ 3.854300] edma 49000000.dma: TI EDMA DMA engine driver
690 00:21:39.006071 <3>[ 3.923675] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
691 00:21:39.021370 <6>[ 3.938194] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
692 00:21:39.034476 <3>[ 3.955435] l3-aon-clkctrl:0000:0: failed to disable
693 00:21:39.089830 <6>[ 4.007495] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
694 00:21:39.095530 <6>[ 4.017017] printk: legacy console [ttyS0] enabled
695 00:21:39.098224 <6>[ 4.017017] printk: legacy console [ttyS0] enabled
696 00:21:39.103752 <6>[ 4.027356] printk: legacy bootconsole [omap8250] disabled
697 00:21:39.112551 <6>[ 4.027356] printk: legacy bootconsole [omap8250] disabled
698 00:21:39.142675 <4>[ 4.059549] tps65217-pmic: Failed to locate of_node [id: -1]
699 00:21:39.146343 <4>[ 4.066962] tps65217-bl: Failed to locate of_node [id: -1]
700 00:21:39.163338 <6>[ 4.087079] tps65217 0-0024: TPS65217 ID 0xe version 1.2
701 00:21:39.181729 <6>[ 4.094110] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
702 00:21:39.193496 <6>[ 4.107822] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
703 00:21:39.199393 <6>[ 4.119791] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
704 00:21:39.222025 <6>[ 4.140165] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
705 00:21:39.227934 <6>[ 4.149334] sdhci-omap 48060000.mmc: Got CD GPIO
706 00:21:39.235961 <4>[ 4.154485] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
707 00:21:39.250661 <4>[ 4.168129] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
708 00:21:39.257332 <4>[ 4.176851] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
709 00:21:39.267024 <4>[ 4.185597] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
710 00:21:39.390583 <6>[ 4.310746] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
711 00:21:39.438300 <6>[ 4.355226] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
712 00:21:39.444930 <6>[ 4.364631] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
713 00:21:39.453986 <6>[ 4.373624] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
714 00:21:39.503696 <6>[ 4.417742] mmc0: new high speed SDHC card at address 0001
715 00:21:39.504155 <6>[ 4.425467] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
716 00:21:39.510895 <6>[ 4.434503] mmcblk0: p1
717 00:21:39.529751 <4>[ 4.446396] mmc1: unexpected status 0x2000980 after switch
718 00:21:39.535546 <6>[ 4.453838] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
719 00:21:39.541186 <4>[ 4.464893] mmc1: unexpected status 0x2000900 after switch
720 00:21:39.551021 <4>[ 4.472632] mmc1: unexpected status 0x2000900 after switch
721 00:21:39.565965 <4>[ 4.484210] mmc1: unexpected status 0x2000900 after switch
722 00:21:39.575845 <6>[ 4.490129] mmc1: new high speed MMC card at address 0001
723 00:21:39.576306 <6>[ 4.497500] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
724 00:21:41.271210 <4>[ 6.187299] mmc1: unexpected status 0x2000980 after switch
725 00:21:41.277536 <4>[ 6.195181] mmc1: unexpected status 0x2000900 after switch
726 00:21:41.284053 <4>[ 6.201582] mmc1: unexpected status 0x2000900 after switch
727 00:21:41.287869 <4>[ 6.208297] mmc1: unexpected status 0x2000900 after switch
728 00:21:41.682136 <6>[ 6.599811] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
729 00:21:41.815440 <5>[ 6.638732] Sending DHCP requests ., OK
730 00:21:41.826750 <6>[ 6.743216] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.16
731 00:21:41.827401 <6>[ 6.751391] IP-Config: Complete:
732 00:21:41.840784 <6>[ 6.754929] device=eth0, hwaddr=c8:a0:30:c2:c5:7d, ipaddr=192.168.6.16, mask=255.255.255.0, gw=192.168.6.1
733 00:21:41.846736 <6>[ 6.765487] host=192.168.6.16, domain=, nis-domain=(none)
734 00:21:41.852273 <6>[ 6.771708] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
735 00:21:41.859036 <6>[ 6.771745] nameserver0=10.255.253.1
736 00:21:41.868103 <6>[ 6.784368] clk: Disabling unused clocks
737 00:21:41.868699 <6>[ 6.789106] PM: genpd: Disabling unused power domains
738 00:21:41.887293 <6>[ 6.806661] Freeing unused kernel image (initmem) memory: 2048K
739 00:21:41.894209 <6>[ 6.816549] Run /init as init process
740 00:21:41.919798 Loading, please wait...
741 00:21:42.020355 <3>[ 6.938841] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
742 00:21:42.032133 Starting systemd-udevd version 252.22-1~deb12u1
743 00:21:42.754665 <3>[ 7.672359] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
744 00:21:43.502769 <3>[ 8.420413] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
745 00:21:44.237072 <3>[ 9.154764] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
746 00:21:44.981408 <3>[ 9.899105] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
747 00:21:45.263195 <4>[ 10.179701] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
748 00:21:45.444395 <4>[ 10.360822] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
749 00:21:45.654238 <6>[ 10.578180] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
750 00:21:45.665179 <6>[ 10.584106] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
751 00:21:45.742160 <3>[ 10.659905] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
752 00:21:45.909115 <6>[ 10.831517] hub 1-0:1.0: USB hub found
753 00:21:45.950883 <6>[ 10.872868] hub 1-0:1.0: 1 port detected
754 00:21:46.089208 <6>[ 11.011371] tda998x 0-0070: found TDA19988
755 00:21:46.561222 <3>[ 11.479040] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
756 00:21:46.809868 <6>[ 11.729620] usb 1-1: new low-speed USB device number 2 using musb-hdrc
757 00:21:46.958213 <3>[ 11.878952] usb 1-1: device descriptor read/64, error -71
758 00:21:47.228390 <3>[ 12.149013] usb 1-1: device descriptor read/64, error -71
759 00:21:47.295955 <3>[ 12.214280] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
760 00:21:47.303728 <3>[ 12.223238] Buffer I/O error on dev mmcblk1, logical block 0, async page read
761 00:21:47.489309 <6>[ 12.409003] usb 1-1: new low-speed USB device number 3 using musb-hdrc
762 00:21:47.678132 <3>[ 12.599008] usb 1-1: device descriptor read/64, error -71
763 00:21:47.928274 <3>[ 12.849010] usb 1-1: device descriptor read/64, error -71
764 00:21:48.103535 <6>[ 13.025413] usb usb1-port1: attempt power cycle
765 00:21:48.289277 <6>[ 13.209086] usb 1-1: new low-speed USB device number 4 using musb-hdrc
766 00:21:48.880662 <6>[ 13.800621] usb 1-1: new low-speed USB device number 5 using musb-hdrc
767 00:21:50.458689 <3>[ 15.376527] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
768 00:21:51.227033 <3>[ 16.144996] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
769 00:21:51.995383 <3>[ 16.913373] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
770 00:21:52.763744 <3>[ 17.681752] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
771 00:21:53.531050 <3>[ 18.450123] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
772 00:21:54.299437 <3>[ 19.218514] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
773 00:21:55.068499 <3>[ 19.986874] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
774 00:21:55.836343 <3>[ 20.755248] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
775 00:21:55.842268 <3>[ 20.764154] Buffer I/O error on dev mmcblk1, logical block 0, async page read
776 00:21:55.849864 <6>[ 20.771836] mmcblk1: unable to read partition table
777 00:21:55.867366 <6>[ 20.789327] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
778 00:21:55.879912 <6>[ 20.801852] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
779 00:21:55.898254 <6>[ 20.818860] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
780 00:21:59.136617 <3>[ 24.053955] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
781 00:21:59.905847 <3>[ 24.823219] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
782 00:22:00.675079 <3>[ 25.592471] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
783 00:22:01.444376 <3>[ 26.361758] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
784 00:22:02.213517 <3>[ 27.130994] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
785 00:22:02.981840 <3>[ 27.900177] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
786 00:22:03.751828 <3>[ 28.669383] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
787 00:22:04.520903 <3>[ 29.438577] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
788 00:22:07.749189 <3>[ 32.667198] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
789 00:22:08.518149 <3>[ 33.436144] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
790 00:22:09.286931 <3>[ 34.205024] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
791 00:22:10.055933 <3>[ 34.973994] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
792 00:22:10.824771 <3>[ 35.742925] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
793 00:22:11.593557 <3>[ 36.511805] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
794 00:22:12.362475 <3>[ 37.280664] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
795 00:22:13.130119 <3>[ 38.049519] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
796 00:22:13.139244 <3>[ 38.058944] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
797 00:22:13.185230 Begin: Loading essential drivers ... done.
798 00:22:13.190661 Begin: Running /scripts/init-premount ... done.
799 00:22:13.196339 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
800 00:22:13.210211 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
801 00:22:13.210539 Device /sys/class/net/eth0 found
802 00:22:13.210764 done.
803 00:22:13.268608 Begin: Waiting up to 180 secs for any network device to become available ... done.
804 00:22:13.337735 IP-Config: eth0 hardware address c8:a0:30:c2:c5:7d mtu 1500 DHCP
805 00:22:13.440267 IP-Config: eth0 guessed broadcast address 192.168.6.255
806 00:22:13.445582 IP-Config: eth0 complete (dhcp from 192.168.6.1):
807 00:22:13.451597 address: 192.168.6.16 broadcast: 192.168.6.255 netmask: 255.255.255.0
808 00:22:13.462500 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
809 00:22:13.462988 rootserver: 192.168.6.1 rootpath:
810 00:22:13.465824 filename :
811 00:22:13.599888 done.
812 00:22:13.607395 Begin: Running /scripts/nfs-bottom ... done.
813 00:22:13.676967 Begin: Running /scripts/init-bottom ... done.
814 00:22:15.138815 <30>[ 40.059306] systemd[1]: System time before build time, advancing clock.
815 00:22:15.335586 <30>[ 40.230030] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
816 00:22:15.344422 <30>[ 40.266946] systemd[1]: Detected architecture arm.
817 00:22:15.358880
818 00:22:15.359496 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
819 00:22:15.360024
820 00:22:15.388157 <30>[ 40.309512] systemd[1]: Hostname set to <debian-bookworm-armhf>.
821 00:22:17.664783 <30>[ 42.584984] systemd[1]: Queued start job for default target graphical.target.
822 00:22:17.681913 <30>[ 42.600098] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
823 00:22:17.689663 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
824 00:22:17.713370 <30>[ 42.631809] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
825 00:22:17.722003 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
826 00:22:17.743824 <30>[ 42.662166] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
827 00:22:17.752257 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
828 00:22:17.772275 <30>[ 42.690808] systemd[1]: Created slice user.slice - User and Session Slice.
829 00:22:17.779084 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
830 00:22:17.807312 <30>[ 42.720167] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
831 00:22:17.813387 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
832 00:22:17.831253 <30>[ 42.749914] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
833 00:22:17.842230 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
834 00:22:17.872261 <30>[ 42.779941] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
835 00:22:17.878756 <30>[ 42.800474] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
836 00:22:17.887267 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
837 00:22:17.910302 <30>[ 42.829227] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
838 00:22:17.918693 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
839 00:22:17.941095 <30>[ 42.859658] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
840 00:22:17.949585 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
841 00:22:17.970903 <30>[ 42.889788] systemd[1]: Reached target paths.target - Path Units.
842 00:22:17.976097 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
843 00:22:18.000637 <30>[ 42.919465] systemd[1]: Reached target remote-fs.target - Remote File Systems.
844 00:22:18.008076 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
845 00:22:18.030448 <30>[ 42.949287] systemd[1]: Reached target slices.target - Slice Units.
846 00:22:18.035969 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
847 00:22:18.060633 <30>[ 42.979471] systemd[1]: Reached target swap.target - Swaps.
848 00:22:18.064727 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
849 00:22:18.090882 <30>[ 43.009526] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
850 00:22:18.099786 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
851 00:22:18.121804 <30>[ 43.040341] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
852 00:22:18.130079 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
853 00:22:18.221886 <30>[ 43.135591] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
854 00:22:18.234824 <30>[ 43.153270] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
855 00:22:18.243252 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
856 00:22:18.273105 <30>[ 43.193233] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
857 00:22:18.285978 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
858 00:22:18.314354 <30>[ 43.231777] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
859 00:22:18.321596 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
860 00:22:18.357444 <30>[ 43.276754] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
861 00:22:18.370894 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
862 00:22:18.392594 <30>[ 43.310737] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
863 00:22:18.402291 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
864 00:22:18.428083 <30>[ 43.340559] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
865 00:22:18.443666 <30>[ 43.357229] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
866 00:22:18.494190 <30>[ 43.414227] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
867 00:22:18.512346 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
868 00:22:18.558125 <30>[ 43.477620] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
869 00:22:18.583337 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
870 00:22:18.655951 <30>[ 43.575359] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
871 00:22:18.687910 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
872 00:22:18.741297 <30>[ 43.660352] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
873 00:22:18.759127 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
874 00:22:18.823560 <30>[ 43.743933] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
875 00:22:18.850927 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
876 00:22:18.903102 <30>[ 43.823037] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
877 00:22:18.928539 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
878 00:22:18.971246 <30>[ 43.889929] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
879 00:22:18.985817 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
880 00:22:19.050145 <30>[ 43.969926] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
881 00:22:19.069283 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
882 00:22:19.122445 <30>[ 44.042216] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
883 00:22:19.149821 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
884 00:22:19.177171 <28>[ 44.091016] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
885 00:22:19.185751 <28>[ 44.104664] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
886 00:22:19.230770 <30>[ 44.149734] systemd[1]: Starting systemd-journald.service - Journal Service...
887 00:22:19.237143 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
888 00:22:19.312465 <30>[ 44.232043] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
889 00:22:19.333064 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
890 00:22:19.391895 <30>[ 44.311606] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
891 00:22:19.434735 Starting [0;1;39msystemd-network-g… units from Kernel command line...
892 00:22:19.485084 <30>[ 44.403210] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
893 00:22:19.534046 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
894 00:22:19.614415 <30>[ 44.533381] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
895 00:22:19.670388 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
896 00:22:19.736879 <30>[ 44.656702] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
897 00:22:19.810169 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
898 00:22:19.831318 <30>[ 44.751071] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
899 00:22:19.858149 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
900 00:22:19.885193 <30>[ 44.803776] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
901 00:22:19.916034 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
902 00:22:20.303049 <30>[ 44.972213] systemd[1]: modprobe@configfs.service: Deactivated successfully.
903 00:22:20.303645 <30>[ 45.009459] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
904 00:22:20.304246 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
905 00:22:20.305533 <30>[ 45.061644] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
906 00:22:20.306069 <30>[ 45.089282] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
907 00:22:20.306535 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
908 00:22:20.306978 <30>[ 45.120495] systemd[1]: Started systemd-journald.service - Journal Service.
909 00:22:20.307418 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
910 00:22:20.307853 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
911 00:22:20.308500 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
912 00:22:20.312584 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
913 00:22:20.341714 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
914 00:22:20.363132 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
915 00:22:20.390725 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
916 00:22:20.413883 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
917 00:22:20.445114 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
918 00:22:20.513643 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
919 00:22:20.555351 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
920 00:22:20.632173 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
921 00:22:20.713970 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
922 00:22:20.792677 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
923 00:22:20.932411 <46>[ 45.852272] systemd-journald[164]: Received client request to flush runtime journal.
924 00:22:20.943971 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
925 00:22:21.092602 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
926 00:22:21.565400 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
927 00:22:21.970853 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
928 00:22:22.022345 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
929 00:22:22.800507 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
930 00:22:22.970197 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
931 00:22:22.991158 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
932 00:22:23.010359 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
933 00:22:23.080595 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
934 00:22:23.123267 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
935 00:22:24.097598 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
936 00:22:24.172515 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
937 00:22:24.471464 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
938 00:22:24.531950 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
939 00:22:24.576637 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
940 00:22:25.903513 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
941 00:22:26.321261 <5>[ 51.241291] cfg80211: Loading compiled-in X.509 certificates for regulatory database
942 00:22:26.692360 <4>[ 51.614533] mmc1: unexpected status 0x2000980 after switch
943 00:22:26.756909 <4>[ 51.679107] mmc1: unexpected status 0x2000900 after switch
944 00:22:26.806819 <4>[ 51.729018] mmc1: unexpected status 0x2000900 after switch
945 00:22:26.899169 <4>[ 51.821589] mmc1: unexpected status 0x2000900 after switch
946 00:22:27.501190 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
947 00:22:28.076593 <5>[ 52.997353] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
948 00:22:28.194665 <5>[ 53.113125] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
949 00:22:28.200422 <4>[ 53.122123] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
950 00:22:28.208175 <6>[ 53.131230] cfg80211: failed to load regulatory.db
951 00:22:28.393320 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
952 00:22:29.511305 <46>[ 54.422123] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
953 00:22:29.643824 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
954 00:22:29.672632 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0<46>[ 54.578260] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
955 00:22:29.673313 m - Network Configuration.
956 00:22:30.000712 <3>[ 54.919170] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
957 00:22:30.763608 <3>[ 55.682066] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
958 00:22:31.511908 <3>[ 56.430479] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
959 00:22:32.252476 <3>[ 57.170992] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
960 00:22:32.988700 <3>[ 57.907097] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
961 00:22:33.735275 <3>[ 58.653446] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
962 00:22:34.480136 <3>[ 59.399295] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
963 00:22:35.240227 <3>[ 60.158952] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
964 00:22:38.312746 <3>[ 63.231848] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
965 00:22:39.046590 <3>[ 63.965822] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
966 00:22:39.112124 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
967 00:22:39.141169 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
968 00:22:39.162229 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
969 00:22:39.184685 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
970 00:22:39.250348 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
971 00:22:39.294930 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
972 00:22:39.376845 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
973 00:22:39.414414 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
974 00:22:39.462018 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
975 00:22:39.491861 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
976 00:22:39.525109 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
977 00:22:39.565811 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
978 00:22:39.593747 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
979 00:22:39.640968 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
980 00:22:39.667773 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
981 00:22:39.701866 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
982 00:22:39.735080 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
983 00:22:39.781860 <3>[ 64.701101] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
984 00:22:39.800165 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
985 00:22:39.821429 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
986 00:22:39.840678 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
987 00:22:39.870830 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
988 00:22:39.890495 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
989 00:22:39.919040 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
990 00:22:39.980242 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
991 00:22:40.050212 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
992 00:22:40.081098 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
993 00:22:40.202082 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
994 00:22:40.274054 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
995 00:22:40.320230 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
996 00:22:40.339817 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
997 00:22:40.529756 <3>[ 65.448937] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
998 00:22:40.630774 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
999 00:22:40.686545 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1000 00:22:40.762494 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1001 00:22:40.780388 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1002 00:22:40.793627 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1003 00:22:41.027720 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1004 00:22:41.264044 <3>[ 66.183171] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1005 00:22:41.390109 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1006 00:22:41.443233 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1007 00:22:41.475150 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1008 00:22:41.565257 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1009 00:22:41.736088 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1010 00:22:41.907688
1011 00:22:41.912494 Debian GNU/Linux 12 debiandebian-bookworm-armhf login: root (automatic login)
1012 00:22:41.912894
1013 00:22:41.998381 <3>[ 66.917364] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1014 00:22:42.360202 Linux debian-bookworm-armhf 6.12.0-rc7 #1 SMP Sun Nov 10 23:10:32 UTC 2024 armv7l
1015 00:22:42.360868
1016 00:22:42.363179 The programs included with the Debian GNU/Linux system are free software;
1017 00:22:42.368978 the exact distribution terms for each program are described in the
1018 00:22:42.374548 individual files in /usr/share/doc/*/copyright.
1019 00:22:42.375495
1020 00:22:42.382669 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1021 00:22:42.383328 permitted by applicable law.
1022 00:22:42.732355 <3>[ 67.651629] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1023 00:22:43.465387 <3>[ 68.385753] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1024 00:22:43.474435 <3>[ 68.395138] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
1025 00:22:47.564850 Unable to match end of the kernel message
1027 00:22:47.565792 Setting prompt string to ['/ #']
1028 00:22:47.566102 end: 2.4.4.1 login-action (duration 00:01:13) [common]
1030 00:22:47.566840 end: 2.4.4 auto-login-action (duration 00:01:14) [common]
1031 00:22:47.567121 start: 2.4.5 expect-shell-connection (timeout 00:02:26) [common]
1032 00:22:47.567345 Setting prompt string to ['/ #']
1033 00:22:47.567564 Forcing a shell prompt, looking for ['/ #']
1035 00:22:47.618160 / #
1036 00:22:47.618869 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1037 00:22:47.619159 Waiting using forced prompt support (timeout 00:02:30)
1038 00:22:47.623505
1039 00:22:47.629482 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1040 00:22:47.629852 start: 2.4.6 export-device-env (timeout 00:02:26) [common]
1041 00:22:47.630114 Sending with 10 millisecond of delay
1043 00:22:52.615909 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/973007/extract-nfsrootfs-6zno0km2'
1044 00:22:52.626824 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/973007/extract-nfsrootfs-6zno0km2'
1045 00:22:52.627836 Sending with 10 millisecond of delay
1047 00:22:54.726936 / # export NFS_SERVER_IP='192.168.6.2'
1048 00:22:54.737992 export NFS_SERVER_IP='192.168.6.2'
1049 00:22:54.739075 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1050 00:22:54.739459 end: 2.4 uboot-commands (duration 00:02:41) [common]
1051 00:22:54.739825 end: 2 uboot-action (duration 00:02:41) [common]
1052 00:22:54.740206 start: 3 lava-test-retry (timeout 00:06:09) [common]
1053 00:22:54.740577 start: 3.1 lava-test-shell (timeout 00:06:09) [common]
1054 00:22:54.740858 Using namespace: common
1056 00:22:54.841716 / # #
1057 00:22:54.842625 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1058 00:22:54.846975 #
1059 00:22:54.853841 Using /lava-973007
1061 00:22:54.954679 / # export SHELL=/bin/bash
1062 00:22:54.960207 export SHELL=/bin/bash
1064 00:22:55.067023 / # . /lava-973007/environment
1065 00:22:55.072869 . /lava-973007/environment
1067 00:22:55.186717 / # /lava-973007/bin/lava-test-runner /lava-973007/0
1068 00:22:55.187643 Test shell timeout: 10s (minimum of the action and connection timeout)
1069 00:22:55.192401 /lava-973007/bin/lava-test-runner /lava-973007/0
1070 00:22:55.597414 + export TESTRUN_ID=0_timesync-off
1071 00:22:55.605171 + TESTRUN_ID=0_timesync-off
1072 00:22:55.605952 + cd /lava-973007/0/tests/0_timesync-off
1073 00:22:55.606530 ++ cat uuid
1074 00:22:55.621984 + UUID=973007_1.6.2.4.1
1075 00:22:55.622742 + set +x
1076 00:22:55.630463 <LAVA_SIGNAL_STARTRUN 0_timesync-off 973007_1.6.2.4.1>
1077 00:22:55.631251 + systemctl stop systemd-timesyncd
1078 00:22:55.632249 Received signal: <STARTRUN> 0_timesync-off 973007_1.6.2.4.1
1079 00:22:55.632962 Starting test lava.0_timesync-off (973007_1.6.2.4.1)
1080 00:22:55.633756 Skipping test definition patterns.
1081 00:22:55.923570 + set +x
1082 00:22:55.924391 <LAVA_SIGNAL_ENDRUN 0_timesync-off 973007_1.6.2.4.1>
1083 00:22:55.925271 Received signal: <ENDRUN> 0_timesync-off 973007_1.6.2.4.1
1084 00:22:55.925947 Ending use of test pattern.
1085 00:22:55.926476 Ending test lava.0_timesync-off (973007_1.6.2.4.1), duration 0.29
1087 00:22:56.110187 + export TESTRUN_ID=1_kselftest-dt
1088 00:22:56.117929 + TESTRUN_ID=1_kselftest-dt
1089 00:22:56.118650 + cd /lava-973007/0/tests/1_kselftest-dt
1090 00:22:56.119308 ++ cat uuid
1091 00:22:56.135508 + UUID=973007_1.6.2.4.5
1092 00:22:56.136186 + set +x
1093 00:22:56.141116 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 973007_1.6.2.4.5>
1094 00:22:56.141722 + cd ./automated/linux/kselftest/
1095 00:22:56.142566 Received signal: <STARTRUN> 1_kselftest-dt 973007_1.6.2.4.5
1096 00:22:56.143126 Starting test lava.1_kselftest-dt (973007_1.6.2.4.5)
1097 00:22:56.143774 Skipping test definition patterns.
1098 00:22:56.167917 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc7/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1099 00:22:56.337192 INFO: install_deps skipped
1100 00:22:56.940084 --2024-11-11 00:22:56-- http://storage.kernelci.org/mainline/master/v6.12-rc7/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
1101 00:22:57.202769 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1102 00:22:57.348801 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1103 00:22:57.492862 HTTP request sent, awaiting response... 200 OK
1104 00:22:57.493466 Length: 2543116 (2.4M) [application/octet-stream]
1105 00:22:57.500083 Saving to: 'kselftest_armhf.tar.gz'
1106 00:22:57.500571
1107 00:22:58.805460
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1108 00:22:58.806123
1109 00:22:59.176680 2024-11-11 00:22:58 (1.86 MB/s) - 'kselftest_armhf.tar.gz' saved [2543116/2543116]
1110 00:22:59.177129
1111 00:23:10.783148 skiplist:
1112 00:23:10.784107 ========================================
1113 00:23:10.788635 ========================================
1114 00:23:10.893939 dt:test_unprobed_devices.sh
1115 00:23:10.926337 ============== Tests to run ===============
1116 00:23:10.934659 dt:test_unprobed_devices.sh
1117 00:23:10.938605 ===========End Tests to run ===============
1118 00:23:10.947394 shardfile-dt pass
1119 00:23:11.179648 <12>[ 96.104584] kselftest: Running tests in dt
1120 00:23:11.209012 TAP version 13
1121 00:23:11.233736 1..1
1122 00:23:11.289734 # timeout set to 45
1123 00:23:11.290335 # selftests: dt: test_unprobed_devices.sh
1124 00:23:12.154399 # TAP version 13
1125 00:23:37.528835 # 1..257
1126 00:23:37.747009 # ok 1 / # SKIP
1127 00:23:37.762315 # ok 2 /clk_mcasp0
1128 00:23:37.837243 # ok 3 /clk_mcasp0_fixed # SKIP
1129 00:23:37.936898 # ok 4 /cpus/cpu@0 # SKIP
1130 00:23:38.020784 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1131 00:23:38.040417 # ok 6 /fixedregulator0
1132 00:23:38.058329 # ok 7 /leds
1133 00:23:38.079566 # ok 8 /ocp
1134 00:23:38.108956 # ok 9 /ocp/interconnect@44c00000
1135 00:23:38.128981 # ok 10 /ocp/interconnect@44c00000/segment@0
1136 00:23:38.153031 # ok 11 /ocp/interconnect@44c00000/segment@100000
1137 00:23:38.181029 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1138 00:23:38.254675 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1139 00:23:38.273297 # ok 14 /ocp/interconnect@44c00000/segment@200000
1140 00:23:38.300149 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1141 00:23:38.405141 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1142 00:23:38.480275 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1143 00:23:38.554496 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1144 00:23:38.632548 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1145 00:23:38.705649 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1146 00:23:38.776675 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1147 00:23:38.845869 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1148 00:23:38.918908 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1149 00:23:38.992256 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1150 00:23:39.064610 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1151 00:23:39.141460 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1152 00:23:39.215124 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1153 00:23:39.286014 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1154 00:23:39.361059 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1155 00:23:39.434754 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1156 00:23:39.506519 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1157 00:23:39.577265 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1158 00:23:39.656745 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1159 00:23:39.738683 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1160 00:23:39.821215 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1161 00:23:39.892747 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1162 00:23:39.972152 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1163 00:23:40.046159 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1164 00:23:40.118342 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1165 00:23:40.189525 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1166 00:23:40.267259 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1167 00:23:40.339380 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1168 00:23:40.417857 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1169 00:23:40.488017 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1170 00:23:40.562784 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1171 00:23:40.640124 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1172 00:23:40.714300 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1173 00:23:40.787414 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1174 00:23:40.857226 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1175 00:23:40.931779 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1176 00:23:41.004639 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1177 00:23:41.079158 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1178 00:23:41.151955 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1179 00:23:41.224887 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1180 00:23:41.584430 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1181 00:23:41.584835 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1182 00:23:41.585062 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1183 00:23:41.585289 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1184 00:23:41.593160 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1185 00:23:41.667224 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1186 00:23:41.745301 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1187 00:23:41.818252 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1188 00:23:41.890999 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1189 00:23:41.963544 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1190 00:23:42.037738 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1191 00:23:42.110761 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1192 00:23:42.183869 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1193 00:23:42.257293 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1194 00:23:42.329025 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1195 00:23:42.403618 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1196 00:23:42.476878 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1197 00:23:42.550595 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1198 00:23:42.624189 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1199 00:23:42.699788 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1200 00:23:42.773406 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1201 00:23:42.846121 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1202 00:23:42.919082 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1203 00:23:42.992605 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1204 00:23:43.066558 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1205 00:23:43.139605 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1206 00:23:43.217562 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1207 00:23:43.285304 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1208 00:23:43.357820 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1209 00:23:43.431150 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1210 00:23:43.506876 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1211 00:23:43.579205 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1212 00:23:43.652009 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1213 00:23:43.725589 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1214 00:23:43.802666 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1215 00:23:43.877047 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1216 00:23:43.947702 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1217 00:23:44.021933 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1218 00:23:44.094422 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1219 00:23:44.168489 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1220 00:23:44.193374 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1221 00:23:44.215306 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1222 00:23:44.237762 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1223 00:23:44.261158 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1224 00:23:44.287390 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1225 00:23:44.312197 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1226 00:23:44.343175 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1227 00:23:44.364272 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1228 00:23:44.473766 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1229 00:23:44.499451 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1230 00:23:44.523884 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1231 00:23:44.548554 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1232 00:23:44.662491 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1233 00:23:44.738643 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1234 00:23:44.812216 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1235 00:23:44.886597 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1236 00:23:44.961116 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1237 00:23:45.035528 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1238 00:23:45.110700 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1239 00:23:45.182830 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1240 00:23:45.256537 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1241 00:23:45.331843 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1242 00:23:45.405905 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1243 00:23:45.484566 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1244 00:23:45.554044 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1245 00:23:45.634492 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1246 00:23:45.706290 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1247 00:23:45.783976 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1248 00:23:45.802977 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1249 00:23:45.875412 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1250 00:23:45.947309 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1251 00:23:46.022687 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1252 00:23:46.045022 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1253 00:23:46.119310 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1254 00:23:46.144444 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1255 00:23:46.216660 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1256 00:23:46.244286 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1257 00:23:46.268209 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1258 00:23:46.295905 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1259 00:23:46.326006 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1260 00:23:46.353256 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1261 00:23:46.374810 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1262 00:23:46.401091 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1263 00:23:46.482607 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1264 00:23:46.500324 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1265 00:23:46.533583 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1266 00:23:46.611556 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1267 00:23:46.686197 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1268 00:23:46.709671 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1269 00:23:46.811855 # not ok 144 /ocp/interconnect@47c00000
1270 00:23:46.892192 # not ok 145 /ocp/interconnect@47c00000/segment@0
1271 00:23:46.911238 # ok 146 /ocp/interconnect@48000000
1272 00:23:46.937915 # ok 147 /ocp/interconnect@48000000/segment@0
1273 00:23:46.963503 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1274 00:23:46.982557 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1275 00:23:47.004961 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1276 00:23:47.033135 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1277 00:23:47.053962 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1278 00:23:47.077189 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1279 00:23:47.099401 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1280 00:23:47.174198 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1281 00:23:47.251593 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1282 00:23:47.273556 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1283 00:23:47.293323 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1284 00:23:47.320732 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1285 00:23:47.344423 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1286 00:23:47.363309 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1287 00:23:47.387870 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1288 00:23:47.415315 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1289 00:23:47.440567 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1290 00:23:47.460283 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1291 00:23:47.488696 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1292 00:23:47.512591 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1293 00:23:47.534443 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1294 00:23:47.555687 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1295 00:23:47.583827 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1296 00:23:47.606264 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1297 00:23:47.627162 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1298 00:23:47.654424 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1299 00:23:47.680492 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1300 00:23:47.702458 # ok 175 /ocp/interconnect@48000000/segment@100000
1301 00:23:47.723131 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1302 00:23:47.752040 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1303 00:23:47.826878 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1304 00:23:47.897406 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1305 00:23:47.969782 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1306 00:23:48.044131 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1307 00:23:48.115136 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1308 00:23:48.197308 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1309 00:23:48.266483 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1310 00:23:48.337254 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1311 00:23:48.359054 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1312 00:23:48.382243 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1313 00:23:48.406326 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1314 00:23:48.433145 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1315 00:23:48.464777 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1316 00:23:48.492935 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1317 00:23:48.514215 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1318 00:23:48.537063 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1319 00:23:48.559716 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1320 00:23:48.583067 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1321 00:23:48.607269 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1322 00:23:48.634803 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1323 00:23:48.657697 # ok 198 /ocp/interconnect@48000000/segment@200000
1324 00:23:48.682240 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1325 00:23:48.755102 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1326 00:23:48.774344 # ok 201 /ocp/interconnect@48000000/segment@300000
1327 00:23:48.798872 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1328 00:23:48.824276 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1329 00:23:48.847477 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1330 00:23:48.870135 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1331 00:23:48.900163 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1332 00:23:48.925493 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1333 00:23:49.014448 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1334 00:23:49.030865 # ok 209 /ocp/interconnect@4a000000
1335 00:23:49.060421 # ok 210 /ocp/interconnect@4a000000/segment@0
1336 00:23:49.082654 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1337 00:23:49.113026 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1338 00:23:49.140690 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1339 00:23:49.165334 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1340 00:23:49.235605 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1341 00:23:49.348972 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1342 00:23:49.419840 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1343 00:23:49.537569 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1344 00:23:49.609248 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1345 00:23:49.681550 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1346 00:23:49.784022 # not ok 221 /ocp/interconnect@4b140000
1347 00:23:49.860848 # not ok 222 /ocp/interconnect@4b140000/segment@0
1348 00:23:49.957579 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1349 00:23:49.980441 # ok 224 /ocp/target-module@40300000
1350 00:23:50.001650 # ok 225 /ocp/target-module@40300000/sram@0
1351 00:23:50.082871 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1352 00:23:50.161627 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1353 00:23:50.181346 # ok 228 /ocp/target-module@47400000
1354 00:23:50.203373 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1355 00:23:50.230299 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1356 00:23:50.252529 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1357 00:23:50.272583 # ok 232 /ocp/target-module@47400000/usb@1400
1358 00:23:50.295705 # ok 233 /ocp/target-module@47400000/usb@1800
1359 00:23:50.319398 # ok 234 /ocp/target-module@47810000
1360 00:23:50.341943 # ok 235 /ocp/target-module@49000000
1361 00:23:50.371865 # ok 236 /ocp/target-module@49000000/dma@0
1362 00:23:50.397410 # ok 237 /ocp/target-module@49800000
1363 00:23:50.414438 # ok 238 /ocp/target-module@49800000/dma@0
1364 00:23:50.437081 # ok 239 /ocp/target-module@49900000
1365 00:23:50.461864 # ok 240 /ocp/target-module@49900000/dma@0
1366 00:23:50.487003 # ok 241 /ocp/target-module@49a00000
1367 00:23:50.509734 # ok 242 /ocp/target-module@49a00000/dma@0
1368 00:23:50.527697 # ok 243 /ocp/target-module@4c000000
1369 00:23:50.602422 # not ok 244 /ocp/target-module@4c000000/emif@0
1370 00:23:50.627725 # ok 245 /ocp/target-module@50000000
1371 00:23:50.650067 # ok 246 /ocp/target-module@53100000
1372 00:23:50.719352 # not ok 247 /ocp/target-module@53100000/sham@0
1373 00:23:50.741299 # ok 248 /ocp/target-module@53500000
1374 00:23:50.822730 # not ok 249 /ocp/target-module@53500000/aes@0
1375 00:23:50.845758 # ok 250 /ocp/target-module@56000000
1376 00:23:50.958467 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1377 00:23:51.024410 # ok 252 /opp-table # SKIP
1378 00:23:51.099445 # ok 253 /soc # SKIP
1379 00:23:51.115486 # ok 254 /sound
1380 00:23:51.140183 # ok 255 /target-module@4b000000
1381 00:23:51.164918 # ok 256 /target-module@4b000000/target-module@140000
1382 00:23:51.185580 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1383 00:23:51.193846 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1384 00:23:51.202234 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1385 00:23:53.577554 dt_test_unprobed_devices_sh_ skip
1386 00:23:53.583039 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1387 00:23:53.588777 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1388 00:23:53.589163 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1389 00:23:53.594384 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1390 00:23:53.599912 dt_test_unprobed_devices_sh_fixedregulator0 pass
1391 00:23:53.605601 dt_test_unprobed_devices_sh_leds pass
1392 00:23:53.605968 dt_test_unprobed_devices_sh_ocp pass
1393 00:23:53.611089 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1394 00:23:53.616964 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1395 00:23:53.622419 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1396 00:23:53.633732 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1397 00:23:53.639189 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1398 00:23:53.644756 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1399 00:23:53.656012 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1400 00:23:53.661964 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1401 00:23:53.672824 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1402 00:23:53.684007 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1403 00:23:53.695547 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1404 00:23:53.701118 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1405 00:23:53.712077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1406 00:23:53.723914 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1407 00:23:53.735107 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1408 00:23:53.746051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1409 00:23:53.751271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1410 00:23:53.762464 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1411 00:23:53.773681 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1412 00:23:53.787731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1413 00:23:53.796146 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1414 00:23:53.801630 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1415 00:23:53.813078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1416 00:23:53.825358 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1417 00:23:53.836252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1418 00:23:53.841598 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1419 00:23:53.852175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1420 00:23:53.863616 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1421 00:23:53.875710 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1422 00:23:53.885698 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1423 00:23:53.891478 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1424 00:23:53.902984 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1425 00:23:53.913591 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1426 00:23:53.924768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1427 00:23:53.936064 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1428 00:23:53.947164 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1429 00:23:53.958523 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1430 00:23:53.969595 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1431 00:23:53.980829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1432 00:23:53.992026 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1433 00:23:54.003207 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1434 00:23:54.014391 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1435 00:23:54.025592 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1436 00:23:54.036796 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1437 00:23:54.047947 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1438 00:23:54.059296 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1439 00:23:54.070664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1440 00:23:54.082011 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1441 00:23:54.093589 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1442 00:23:54.103975 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1443 00:23:54.116935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1444 00:23:54.126400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1445 00:23:54.137525 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1446 00:23:54.148748 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1447 00:23:54.160023 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1448 00:23:54.171904 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1449 00:23:54.178280 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1450 00:23:54.187944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1451 00:23:54.199074 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1452 00:23:54.210265 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1453 00:23:54.221481 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1454 00:23:54.232659 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1455 00:23:54.243884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1456 00:23:54.255338 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1457 00:23:54.266255 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1458 00:23:54.277428 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1459 00:23:54.288669 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1460 00:23:54.299837 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1461 00:23:54.311050 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1462 00:23:54.322649 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1463 00:23:54.333511 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1464 00:23:54.344592 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1465 00:23:54.355816 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1466 00:23:54.367105 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1467 00:23:54.372551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1468 00:23:54.383792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1469 00:23:54.395571 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1470 00:23:54.407926 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1471 00:23:54.417314 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1472 00:23:54.422966 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1473 00:23:54.439731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1474 00:23:54.450961 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1475 00:23:54.456509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1476 00:23:54.473613 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1477 00:23:54.484511 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1478 00:23:54.495711 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1479 00:23:54.502448 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1480 00:23:54.512510 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1481 00:23:54.523734 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1482 00:23:54.529352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1483 00:23:54.540448 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1484 00:23:54.551696 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1485 00:23:54.557260 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1486 00:23:54.568447 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1487 00:23:54.574024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1488 00:23:54.585188 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1489 00:23:54.596370 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1490 00:23:54.607564 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1491 00:23:54.618768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1492 00:23:54.629989 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1493 00:23:54.641229 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1494 00:23:54.652420 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1495 00:23:54.663637 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1496 00:23:54.674810 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1497 00:23:54.686001 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1498 00:23:54.697109 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1499 00:23:54.708285 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1500 00:23:54.725086 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1501 00:23:54.736402 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1502 00:23:54.747627 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1503 00:23:54.758683 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1504 00:23:54.771641 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1505 00:23:54.786694 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1506 00:23:54.798030 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1507 00:23:54.812131 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1508 00:23:54.820415 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1509 00:23:54.825957 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1510 00:23:54.837197 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1511 00:23:54.848690 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1512 00:23:54.854038 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1513 00:23:54.865191 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1514 00:23:54.870771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1515 00:23:54.882011 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1516 00:23:54.887595 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1517 00:23:54.898758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1518 00:23:54.904367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1519 00:23:54.915473 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1520 00:23:54.921132 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1521 00:23:54.932381 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1522 00:23:54.943501 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1523 00:23:54.954731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1524 00:23:54.965977 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1525 00:23:54.977126 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1526 00:23:54.982787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1527 00:23:54.993909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1528 00:23:54.999555 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1529 00:23:55.005167 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1530 00:23:55.010691 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1531 00:23:55.016306 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1532 00:23:55.022156 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1533 00:23:55.035412 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1534 00:23:55.038876 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1535 00:23:55.044453 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1536 00:23:55.055525 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1537 00:23:55.061068 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1538 00:23:55.072310 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1539 00:23:55.077922 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1540 00:23:55.089175 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1541 00:23:55.094744 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1542 00:23:55.105948 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1543 00:23:55.111895 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1544 00:23:55.122673 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1545 00:23:55.128309 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1546 00:23:55.139343 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1547 00:23:55.145008 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1548 00:23:55.156364 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1549 00:23:55.161959 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1550 00:23:55.167534 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1551 00:23:55.178679 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1552 00:23:55.184370 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1553 00:23:55.195466 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1554 00:23:55.201118 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1555 00:23:55.212274 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1556 00:23:55.217893 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1557 00:23:55.229023 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1558 00:23:55.234570 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1559 00:23:55.240174 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1560 00:23:55.251350 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1561 00:23:55.256997 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1562 00:23:55.268150 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1563 00:23:55.279330 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1564 00:23:55.290502 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1565 00:23:55.301703 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1566 00:23:55.312956 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1567 00:23:55.324172 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1568 00:23:55.335351 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1569 00:23:55.346539 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1570 00:23:55.352177 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1571 00:23:55.363337 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1572 00:23:55.369005 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1573 00:23:55.380153 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1574 00:23:55.385779 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1575 00:23:55.396978 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1576 00:23:55.402590 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1577 00:23:55.413818 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1578 00:23:55.419448 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1579 00:23:55.430668 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1580 00:23:55.436236 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1581 00:23:55.447394 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1582 00:23:55.453056 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1583 00:23:55.464300 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1584 00:23:55.470172 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1585 00:23:55.475552 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1586 00:23:55.486681 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1587 00:23:55.492281 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1588 00:23:55.503478 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1589 00:23:55.509128 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1590 00:23:55.520325 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1591 00:23:55.525917 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1592 00:23:55.537112 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1593 00:23:55.542714 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1594 00:23:55.548293 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1595 00:23:55.553890 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1596 00:23:55.565079 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1597 00:23:55.578430 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1598 00:23:55.582952 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1599 00:23:55.587459 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1600 00:23:55.599186 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1601 00:23:55.609914 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1602 00:23:55.621130 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1603 00:23:55.632243 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1604 00:23:55.637913 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1605 00:23:55.643445 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1606 00:23:55.649027 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1607 00:23:55.654610 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1608 00:23:55.660227 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1609 00:23:55.665803 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1610 00:23:55.677029 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1611 00:23:55.682608 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1612 00:23:55.688212 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1613 00:23:55.693784 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1614 00:23:55.699398 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1615 00:23:55.710591 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1616 00:23:55.716203 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1617 00:23:55.721776 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1618 00:23:55.727400 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1619 00:23:55.733064 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1620 00:23:55.738701 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1621 00:23:55.744282 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1622 00:23:55.749877 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1623 00:23:55.755528 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1624 00:23:55.761258 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1625 00:23:55.766736 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1626 00:23:55.772368 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1627 00:23:55.777977 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1628 00:23:55.783554 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1629 00:23:55.789371 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1630 00:23:55.794890 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1631 00:23:55.800503 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1632 00:23:55.806123 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1633 00:23:55.811649 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1634 00:23:55.817366 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1635 00:23:55.822813 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1636 00:23:55.823153 dt_test_unprobed_devices_sh_opp-table skip
1637 00:23:55.828430 dt_test_unprobed_devices_sh_soc skip
1638 00:23:55.834060 dt_test_unprobed_devices_sh_sound pass
1639 00:23:55.839618 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1640 00:23:55.845334 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1641 00:23:55.850773 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1642 00:23:55.854486 dt_test_unprobed_devices_sh fail
1643 00:23:55.930674 + ../../utils/send-to-lava.sh ./output/result.txt
1644 00:23:56.061252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1645 00:23:56.062205 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1647 00:23:56.155467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1648 00:23:56.156139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1650 00:23:56.243075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1651 00:23:56.243722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1653 00:23:56.330973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1654 00:23:56.331605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1656 00:23:56.416234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1657 00:23:56.416873 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1659 00:23:56.506084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1660 00:23:56.506756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1662 00:23:56.590784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1663 00:23:56.591426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1665 00:23:56.678076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1666 00:23:56.678712 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1668 00:23:56.762630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1669 00:23:56.763264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1671 00:23:56.849966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1672 00:23:56.850607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1674 00:23:56.935939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1675 00:23:56.936607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1677 00:23:57.022966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1678 00:23:57.023619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1680 00:23:57.115040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1681 00:23:57.115666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1683 00:23:57.209987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1684 00:23:57.210611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1686 00:23:57.293944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1687 00:23:57.294560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1689 00:23:57.382980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1690 00:23:57.383601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1692 00:23:57.472214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1693 00:23:57.472836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1695 00:23:57.561365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1696 00:23:57.561994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1698 00:23:57.649870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1699 00:23:57.650505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1701 00:23:57.759108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1702 00:23:57.759748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1704 00:23:57.858649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1705 00:23:57.859316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1707 00:23:57.957043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1708 00:23:57.957688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1710 00:23:58.050385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1711 00:23:58.051048 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1713 00:23:58.146079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1714 00:23:58.146719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1716 00:23:58.239896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1717 00:23:58.240675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1719 00:23:58.328292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1720 00:23:58.329091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1722 00:23:58.422563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1723 00:23:58.423239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1725 00:23:58.515812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1726 00:23:58.516887 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1728 00:23:58.608266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1729 00:23:58.609588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1731 00:23:58.710574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1732 00:23:58.711216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1734 00:23:58.823414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1735 00:23:58.824159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1737 00:23:58.929813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1738 00:23:58.930510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1740 00:23:59.033097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1741 00:23:59.033786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1743 00:23:59.131106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1744 00:23:59.132068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1746 00:23:59.224039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1747 00:23:59.224978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1749 00:23:59.325565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1750 00:23:59.326275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1752 00:23:59.417743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1753 00:23:59.418683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1755 00:23:59.527125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1756 00:23:59.527815 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1758 00:23:59.614515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1759 00:23:59.615154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1761 00:23:59.714749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1762 00:23:59.715495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1764 00:23:59.813626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1765 00:23:59.814262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1767 00:23:59.899462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1768 00:23:59.900513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1770 00:23:59.990035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1771 00:23:59.990698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1773 00:24:00.077993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1774 00:24:00.078690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1776 00:24:00.165083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1777 00:24:00.165723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1779 00:24:00.251439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1780 00:24:00.252104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1782 00:24:00.339420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1783 00:24:00.340088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1785 00:24:00.427312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1786 00:24:00.427949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1788 00:24:00.517252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1789 00:24:00.517915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1791 00:24:00.608713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1792 00:24:00.609356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1794 00:24:00.700333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1795 00:24:00.700992 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1797 00:24:00.788715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1798 00:24:00.789361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1800 00:24:00.876944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1801 00:24:00.877596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1803 00:24:00.963963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1804 00:24:00.964656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1806 00:24:01.050771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1807 00:24:01.051391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1809 00:24:01.139334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1810 00:24:01.140017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1812 00:24:01.229810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1813 00:24:01.230450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1815 00:24:01.323779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1816 00:24:01.324447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1818 00:24:01.418765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1819 00:24:01.419392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1821 00:24:01.514889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1822 00:24:01.515534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1824 00:24:01.611250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1825 00:24:01.611910 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1827 00:24:01.703551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1828 00:24:01.704190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1830 00:24:01.794311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1831 00:24:01.795007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1833 00:24:01.886807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1834 00:24:01.887435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1836 00:24:01.975382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1837 00:24:01.976027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1839 00:24:02.064198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1840 00:24:02.064841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1842 00:24:02.153208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1843 00:24:02.153836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1845 00:24:02.243731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1846 00:24:02.244417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1848 00:24:02.336406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1849 00:24:02.337052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1851 00:24:02.426162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1852 00:24:02.426783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1854 00:24:02.513103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1855 00:24:02.513773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1857 00:24:02.605734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1858 00:24:02.606398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1860 00:24:02.696559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1861 00:24:02.697201 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1863 00:24:02.784886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1864 00:24:02.785530 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1866 00:24:02.875413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1867 00:24:02.876063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1869 00:24:02.964801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1870 00:24:02.965423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1872 00:24:03.057789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1873 00:24:03.058414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1875 00:24:03.154227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1876 00:24:03.154843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1878 00:24:03.241704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1879 00:24:03.242325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1881 00:24:03.329710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1882 00:24:03.330325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1884 00:24:03.418759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1885 00:24:03.419428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1887 00:24:03.511543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1888 00:24:03.512312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1890 00:24:03.609568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1891 00:24:03.610699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1893 00:24:03.699888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1894 00:24:03.700658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1896 00:24:03.788487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1897 00:24:03.789416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1899 00:24:03.885746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1900 00:24:03.886419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1902 00:24:03.973820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1903 00:24:03.974700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1905 00:24:04.060095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1906 00:24:04.060956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1908 00:24:04.147556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1909 00:24:04.148415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1911 00:24:04.236140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1912 00:24:04.237009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1914 00:24:04.323063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1915 00:24:04.323700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1917 00:24:04.409200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1918 00:24:04.409850 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1920 00:24:04.501339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1921 00:24:04.502046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1923 00:24:04.599347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1924 00:24:04.600051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1926 00:24:04.688312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1927 00:24:04.688968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1929 00:24:04.781234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1930 00:24:04.781894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1932 00:24:04.874838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1933 00:24:04.875494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1935 00:24:04.964027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1936 00:24:04.964671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1938 00:24:05.053903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1939 00:24:05.054598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1941 00:24:05.141292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1942 00:24:05.141967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1944 00:24:05.228811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1945 00:24:05.229751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1947 00:24:05.325011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1948 00:24:05.325727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1950 00:24:05.415228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1951 00:24:05.415893 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1953 00:24:05.512062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1954 00:24:05.512707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1956 00:24:05.607688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1957 00:24:05.608387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1959 00:24:05.700142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1960 00:24:05.700778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1962 00:24:05.795324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1963 00:24:05.795967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1965 00:24:05.891731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1966 00:24:05.892634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1968 00:24:05.998402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1969 00:24:05.999262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1971 00:24:06.093138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1972 00:24:06.094600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1974 00:24:06.180590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1975 00:24:06.181268 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1977 00:24:06.268364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1978 00:24:06.269233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1980 00:24:06.356402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1981 00:24:06.357265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1983 00:24:06.444545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1984 00:24:06.445402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1986 00:24:06.534311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1987 00:24:06.535197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1989 00:24:06.630543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1990 00:24:06.631189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1992 00:24:06.720153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1993 00:24:06.720793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1995 00:24:06.809351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1996 00:24:06.810020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1998 00:24:06.909184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1999 00:24:06.909839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
2001 00:24:07.013213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
2002 00:24:07.013887 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
2004 00:24:07.119107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
2006 00:24:07.121468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
2007 00:24:07.213572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
2009 00:24:07.216726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2010 00:24:07.301219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2012 00:24:07.303610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2013 00:24:07.392170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2014 00:24:07.392867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2016 00:24:07.484603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2017 00:24:07.485287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2019 00:24:07.581606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2020 00:24:07.582247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2022 00:24:07.674777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2023 00:24:07.675719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2025 00:24:07.764168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2026 00:24:07.765258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2028 00:24:07.859601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2029 00:24:07.860304 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2031 00:24:07.946342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2032 00:24:07.947022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2034 00:24:08.035361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2035 00:24:08.036073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2037 00:24:08.129589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2038 00:24:08.130245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2040 00:24:08.220443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2041 00:24:08.221102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2043 00:24:08.317731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2044 00:24:08.318428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2046 00:24:08.411593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2047 00:24:08.412316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2049 00:24:08.497000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2050 00:24:08.497638 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2052 00:24:08.585033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2053 00:24:08.585706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2055 00:24:08.673117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2056 00:24:08.674205 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2058 00:24:08.761319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2059 00:24:08.761954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2061 00:24:08.847683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2062 00:24:08.848583 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2064 00:24:08.934653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2065 00:24:08.935476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2067 00:24:09.030203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2068 00:24:09.031701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2070 00:24:09.118702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2071 00:24:09.119387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2073 00:24:09.207739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2074 00:24:09.208423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2076 00:24:09.299010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2077 00:24:09.299702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2079 00:24:09.394794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2080 00:24:09.395433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2082 00:24:09.486790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2083 00:24:09.487425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2085 00:24:09.576289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2086 00:24:09.576934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2088 00:24:09.666790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2089 00:24:09.667427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2091 00:24:09.755428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2092 00:24:09.756421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2094 00:24:09.844202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2095 00:24:09.844939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2097 00:24:09.946513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2098 00:24:09.947230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2100 00:24:10.041560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2101 00:24:10.042221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2103 00:24:10.134517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2104 00:24:10.135538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2106 00:24:10.243198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2107 00:24:10.243860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2109 00:24:10.337859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2110 00:24:10.338602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2112 00:24:10.433814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2113 00:24:10.434710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2115 00:24:10.527171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2116 00:24:10.528223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2118 00:24:10.624457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2119 00:24:10.625310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2121 00:24:10.717603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2122 00:24:10.718488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2124 00:24:10.806608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2125 00:24:10.807292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2127 00:24:10.901577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2128 00:24:10.902241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2130 00:24:10.990349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2131 00:24:10.991218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2133 00:24:11.076521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2134 00:24:11.077160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2136 00:24:11.168318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2137 00:24:11.168956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2139 00:24:11.265860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2140 00:24:11.266533 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2142 00:24:11.366534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2143 00:24:11.367340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2145 00:24:11.461200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2146 00:24:11.461970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2148 00:24:11.565425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2149 00:24:11.566061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2151 00:24:11.658210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2152 00:24:11.658837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2154 00:24:11.754027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2155 00:24:11.754653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2157 00:24:11.843137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2158 00:24:11.843798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2160 00:24:11.948608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2161 00:24:11.949291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2163 00:24:12.043948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2164 00:24:12.044604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2166 00:24:12.139768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2167 00:24:12.140426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2169 00:24:12.255973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2170 00:24:12.256655 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2172 00:24:12.359712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2173 00:24:12.360415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2175 00:24:12.459309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2176 00:24:12.459955 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2178 00:24:12.552707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2179 00:24:12.553356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2181 00:24:12.649010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2182 00:24:12.649648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2184 00:24:12.736274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2185 00:24:12.736898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2187 00:24:12.827529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2188 00:24:12.828202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2190 00:24:13.288431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2191 00:24:13.289126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2193 00:24:13.391048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2194 00:24:13.391702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2196 00:24:13.483873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2197 00:24:13.484694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2199 00:24:13.572851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2200 00:24:13.573511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2202 00:24:13.660050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2203 00:24:13.660715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2205 00:24:13.758114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2206 00:24:13.758780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2208 00:24:13.866236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2209 00:24:13.867302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2211 00:24:13.953630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2212 00:24:13.956016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2214 00:24:14.043576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2215 00:24:14.044500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2217 00:24:14.132260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2218 00:24:14.133368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2220 00:24:14.218943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2221 00:24:14.219821 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2223 00:24:14.306994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2224 00:24:14.307656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2226 00:24:14.393923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2227 00:24:14.394585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2229 00:24:14.481145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2230 00:24:14.481820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2232 00:24:14.569818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2233 00:24:14.570507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2235 00:24:14.671278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2236 00:24:14.671973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2238 00:24:14.770438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2239 00:24:14.771141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2241 00:24:14.878022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2242 00:24:14.878853 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2244 00:24:14.970063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2245 00:24:14.970732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2247 00:24:15.064712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2248 00:24:15.065398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2250 00:24:15.167244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2251 00:24:15.167903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2253 00:24:15.262191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2254 00:24:15.263065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2256 00:24:15.359428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2257 00:24:15.360279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2259 00:24:15.460717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2260 00:24:15.461578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2262 00:24:15.561110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2263 00:24:15.561849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2265 00:24:15.702653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2266 00:24:15.703401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2268 00:24:15.795220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2269 00:24:15.796326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2271 00:24:15.891682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2272 00:24:15.892503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2274 00:24:16.007591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2275 00:24:16.008315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2277 00:24:16.111395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2278 00:24:16.112208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2280 00:24:16.214230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2281 00:24:16.214872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2283 00:24:16.325959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2284 00:24:16.326951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2286 00:24:16.425978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2287 00:24:16.426649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2289 00:24:16.540476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2290 00:24:16.541309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2292 00:24:16.653304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2293 00:24:16.653999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2295 00:24:16.768162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2296 00:24:16.768911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2298 00:24:16.878257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2299 00:24:16.878956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2301 00:24:16.990971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2302 00:24:16.991650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2304 00:24:17.084755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2305 00:24:17.085456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2307 00:24:17.173887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2308 00:24:17.174534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2310 00:24:17.262160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2311 00:24:17.262813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2313 00:24:17.350473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2314 00:24:17.351099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2316 00:24:17.440346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2317 00:24:17.440963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2319 00:24:17.529728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2320 00:24:17.530370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2322 00:24:17.621680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2323 00:24:17.622315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2325 00:24:17.713287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2327 00:24:17.716393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2328 00:24:17.807750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2329 00:24:17.808447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2331 00:24:17.903520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2332 00:24:17.904156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2334 00:24:17.993832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2335 00:24:17.994442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2337 00:24:18.089937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2338 00:24:18.090580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2340 00:24:18.177404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2341 00:24:18.178050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2343 00:24:18.269345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2344 00:24:18.269990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2346 00:24:18.362764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2347 00:24:18.363402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2349 00:24:18.449978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2350 00:24:18.450613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2352 00:24:18.537962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2353 00:24:18.538640 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2355 00:24:18.628199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2356 00:24:18.628827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2358 00:24:18.715204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2359 00:24:18.716009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2361 00:24:18.803042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2362 00:24:18.804115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2364 00:24:18.893212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2365 00:24:18.894552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2367 00:24:18.979585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2368 00:24:18.980426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2370 00:24:19.066857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2371 00:24:19.067641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2373 00:24:19.152621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2374 00:24:19.153402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2376 00:24:19.239576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2377 00:24:19.240411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2379 00:24:19.325049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2380 00:24:19.325689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2382 00:24:19.411284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2383 00:24:19.411974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2385 00:24:19.508703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2386 00:24:19.509360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2388 00:24:19.596693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2389 00:24:19.597393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2391 00:24:19.683188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2392 00:24:19.683869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2394 00:24:19.768455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2395 00:24:19.769108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2397 00:24:19.854397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2398 00:24:19.855056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2400 00:24:19.942156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2401 00:24:19.942810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2403 00:24:20.027301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2404 00:24:20.027932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2406 00:24:20.114656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2407 00:24:20.115283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2409 00:24:20.202021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2410 00:24:20.202648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2412 00:24:20.290282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2413 00:24:20.290921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2415 00:24:20.376292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2416 00:24:20.376932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2418 00:24:20.462115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2419 00:24:20.462529 + set +x
2420 00:24:20.463147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2422 00:24:20.470006 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 973007_1.6.2.4.5>
2423 00:24:20.470358 <LAVA_TEST_RUNNER EXIT>
2424 00:24:20.470809 Received signal: <ENDRUN> 1_kselftest-dt 973007_1.6.2.4.5
2425 00:24:20.471086 Ending use of test pattern.
2426 00:24:20.471303 Ending test lava.1_kselftest-dt (973007_1.6.2.4.5), duration 84.33
2428 00:24:20.472183 ok: lava_test_shell seems to have completed
2429 00:24:20.478609 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2430 00:24:20.479761 end: 3.1 lava-test-shell (duration 00:01:26) [common]
2431 00:24:20.480086 end: 3 lava-test-retry (duration 00:01:26) [common]
2432 00:24:20.480398 start: 4 finalize (timeout 00:04:43) [common]
2433 00:24:20.480709 start: 4.1 power-off (timeout 00:00:30) [common]
2434 00:24:20.481262 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-04'
2435 00:24:20.524973 >> OK - accepted request
2436 00:24:20.527471 Returned 0 in 0 seconds
2437 00:24:20.628477 end: 4.1 power-off (duration 00:00:00) [common]
2439 00:24:20.629520 start: 4.2 read-feedback (timeout 00:04:43) [common]
2440 00:24:20.630214 Listened to connection for namespace 'common' for up to 1s
2441 00:24:20.630819 Listened to connection for namespace 'common' for up to 1s
2442 00:24:21.631093 Finalising connection for namespace 'common'
2443 00:24:21.631597 Disconnecting from shell: Finalise
2444 00:24:21.631880 / #
2445 00:24:21.732603 end: 4.2 read-feedback (duration 00:00:01) [common]
2446 00:24:21.733126 end: 4 finalize (duration 00:00:01) [common]
2447 00:24:21.733490 Cleaning after the job
2448 00:24:21.733913 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973007/tftp-deploy-4p76_5io/ramdisk
2449 00:24:21.735433 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973007/tftp-deploy-4p76_5io/kernel
2450 00:24:21.736717 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973007/tftp-deploy-4p76_5io/dtb
2451 00:24:21.737418 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973007/tftp-deploy-4p76_5io/nfsrootfs
2452 00:24:21.755295 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973007/tftp-deploy-4p76_5io/modules
2453 00:24:21.759206 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/973007
2454 00:24:24.694974 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/973007
2455 00:24:24.695540 Job finished correctly