Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 23:05:40.967578 lava-dispatcher, installed at version: 2024.01
2 23:05:40.968375 start: 0 validate
3 23:05:40.968866 Start time: 2024-11-10 23:05:40.968834+00:00 (UTC)
4 23:05:40.969407 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 23:05:40.969969 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 23:05:41.002831 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 23:05:41.003371 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 23:05:41.026826 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 23:05:41.027482 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 23:05:41.051247 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 23:05:41.051778 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 23:05:41.075260 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 23:05:41.075740 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 23:05:41.104708 validate duration: 0.14
16 23:05:41.105635 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:05:41.105989 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:05:41.106297 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:05:41.106880 Not decompressing ramdisk as can be used compressed.
20 23:05:41.107299 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 23:05:41.107579 saving as /var/lib/lava/dispatcher/tmp/972559/tftp-deploy-deppz1es/ramdisk/initrd.cpio.gz
22 23:05:41.107846 total size: 4775763 (4 MB)
23 23:05:41.133720 progress 0 % (0 MB)
24 23:05:41.137384 progress 5 % (0 MB)
25 23:05:41.140676 progress 10 % (0 MB)
26 23:05:41.143958 progress 15 % (0 MB)
27 23:05:41.147613 progress 20 % (0 MB)
28 23:05:41.150761 progress 25 % (1 MB)
29 23:05:41.154011 progress 30 % (1 MB)
30 23:05:41.157574 progress 35 % (1 MB)
31 23:05:41.160838 progress 40 % (1 MB)
32 23:05:41.164141 progress 45 % (2 MB)
33 23:05:41.167354 progress 50 % (2 MB)
34 23:05:41.171176 progress 55 % (2 MB)
35 23:05:41.174485 progress 60 % (2 MB)
36 23:05:41.177684 progress 65 % (2 MB)
37 23:05:41.181387 progress 70 % (3 MB)
38 23:05:41.184556 progress 75 % (3 MB)
39 23:05:41.187819 progress 80 % (3 MB)
40 23:05:41.191122 progress 85 % (3 MB)
41 23:05:41.194696 progress 90 % (4 MB)
42 23:05:41.197695 progress 95 % (4 MB)
43 23:05:41.200657 progress 100 % (4 MB)
44 23:05:41.201352 4 MB downloaded in 0.09 s (48.72 MB/s)
45 23:05:41.201961 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:05:41.202891 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:05:41.203222 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:05:41.203525 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:05:41.204032 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 23:05:41.204307 saving as /var/lib/lava/dispatcher/tmp/972559/tftp-deploy-deppz1es/kernel/zImage
52 23:05:41.204535 total size: 11444736 (10 MB)
53 23:05:41.204765 No compression specified
54 23:05:41.234764 progress 0 % (0 MB)
55 23:05:41.242094 progress 5 % (0 MB)
56 23:05:41.249121 progress 10 % (1 MB)
57 23:05:41.256578 progress 15 % (1 MB)
58 23:05:41.263737 progress 20 % (2 MB)
59 23:05:41.271295 progress 25 % (2 MB)
60 23:05:41.278321 progress 30 % (3 MB)
61 23:05:41.285987 progress 35 % (3 MB)
62 23:05:41.293891 progress 40 % (4 MB)
63 23:05:41.301782 progress 45 % (4 MB)
64 23:05:41.308693 progress 50 % (5 MB)
65 23:05:41.315985 progress 55 % (6 MB)
66 23:05:41.322925 progress 60 % (6 MB)
67 23:05:41.330269 progress 65 % (7 MB)
68 23:05:41.337152 progress 70 % (7 MB)
69 23:05:41.344114 progress 75 % (8 MB)
70 23:05:41.351428 progress 80 % (8 MB)
71 23:05:41.358496 progress 85 % (9 MB)
72 23:05:41.365779 progress 90 % (9 MB)
73 23:05:41.372714 progress 95 % (10 MB)
74 23:05:41.379514 progress 100 % (10 MB)
75 23:05:41.379995 10 MB downloaded in 0.18 s (62.21 MB/s)
76 23:05:41.380465 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:05:41.381273 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:05:41.381547 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:05:41.381826 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:05:41.382304 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 23:05:41.382545 saving as /var/lib/lava/dispatcher/tmp/972559/tftp-deploy-deppz1es/dtb/am335x-boneblack.dtb
83 23:05:41.382752 total size: 70568 (0 MB)
84 23:05:41.382959 No compression specified
85 23:05:41.417707 progress 46 % (0 MB)
86 23:05:41.418572 progress 92 % (0 MB)
87 23:05:41.419250 progress 100 % (0 MB)
88 23:05:41.419632 0 MB downloaded in 0.04 s (1.83 MB/s)
89 23:05:41.420086 end: 1.3.1 http-download (duration 00:00:00) [common]
91 23:05:41.420894 end: 1.3 download-retry (duration 00:00:00) [common]
92 23:05:41.421216 start: 1.4 download-retry (timeout 00:10:00) [common]
93 23:05:41.421534 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 23:05:41.422067 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 23:05:41.422371 saving as /var/lib/lava/dispatcher/tmp/972559/tftp-deploy-deppz1es/nfsrootfs/full.rootfs.tar
96 23:05:41.422596 total size: 117747780 (112 MB)
97 23:05:41.422823 Using unxz to decompress xz
98 23:05:41.454689 progress 0 % (0 MB)
99 23:05:42.183282 progress 5 % (5 MB)
100 23:05:42.933729 progress 10 % (11 MB)
101 23:05:43.867771 progress 15 % (16 MB)
102 23:05:44.591877 progress 20 % (22 MB)
103 23:05:45.214295 progress 25 % (28 MB)
104 23:05:46.066803 progress 30 % (33 MB)
105 23:05:46.869623 progress 35 % (39 MB)
106 23:05:47.196435 progress 40 % (44 MB)
107 23:05:47.543438 progress 45 % (50 MB)
108 23:05:48.196027 progress 50 % (56 MB)
109 23:05:48.998691 progress 55 % (61 MB)
110 23:05:49.722534 progress 60 % (67 MB)
111 23:05:50.431989 progress 65 % (73 MB)
112 23:05:51.189096 progress 70 % (78 MB)
113 23:05:51.943851 progress 75 % (84 MB)
114 23:05:52.673726 progress 80 % (89 MB)
115 23:05:53.379357 progress 85 % (95 MB)
116 23:05:54.154606 progress 90 % (101 MB)
117 23:05:54.905101 progress 95 % (106 MB)
118 23:05:55.713892 progress 100 % (112 MB)
119 23:05:55.726160 112 MB downloaded in 14.30 s (7.85 MB/s)
120 23:05:55.726858 end: 1.4.1 http-download (duration 00:00:14) [common]
122 23:05:55.728512 end: 1.4 download-retry (duration 00:00:14) [common]
123 23:05:55.729045 start: 1.5 download-retry (timeout 00:09:45) [common]
124 23:05:55.729567 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 23:05:55.730418 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 23:05:55.730883 saving as /var/lib/lava/dispatcher/tmp/972559/tftp-deploy-deppz1es/modules/modules.tar
127 23:05:55.731302 total size: 6609076 (6 MB)
128 23:05:55.731730 Using unxz to decompress xz
129 23:05:55.766762 progress 0 % (0 MB)
130 23:05:55.803967 progress 5 % (0 MB)
131 23:05:55.846677 progress 10 % (0 MB)
132 23:05:55.889344 progress 15 % (0 MB)
133 23:05:55.933550 progress 20 % (1 MB)
134 23:05:55.979327 progress 25 % (1 MB)
135 23:05:56.021625 progress 30 % (1 MB)
136 23:05:56.063914 progress 35 % (2 MB)
137 23:05:56.107020 progress 40 % (2 MB)
138 23:05:56.149794 progress 45 % (2 MB)
139 23:05:56.192706 progress 50 % (3 MB)
140 23:05:56.234907 progress 55 % (3 MB)
141 23:05:56.283935 progress 60 % (3 MB)
142 23:05:56.325849 progress 65 % (4 MB)
143 23:05:56.368714 progress 70 % (4 MB)
144 23:05:56.414247 progress 75 % (4 MB)
145 23:05:56.456537 progress 80 % (5 MB)
146 23:05:56.499041 progress 85 % (5 MB)
147 23:05:56.541642 progress 90 % (5 MB)
148 23:05:56.584106 progress 95 % (6 MB)
149 23:05:56.627337 progress 100 % (6 MB)
150 23:05:56.640264 6 MB downloaded in 0.91 s (6.93 MB/s)
151 23:05:56.641148 end: 1.5.1 http-download (duration 00:00:01) [common]
153 23:05:56.642799 end: 1.5 download-retry (duration 00:00:01) [common]
154 23:05:56.643323 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 23:05:56.643839 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 23:06:13.097022 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/972559/extract-nfsrootfs-7pck4o3u
157 23:06:13.097650 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 23:06:13.097986 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 23:06:13.098649 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f
160 23:06:13.099097 makedir: /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin
161 23:06:13.099427 makedir: /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/tests
162 23:06:13.099745 makedir: /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/results
163 23:06:13.100091 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-add-keys
164 23:06:13.100649 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-add-sources
165 23:06:13.101187 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-background-process-start
166 23:06:13.101708 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-background-process-stop
167 23:06:13.102319 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-common-functions
168 23:06:13.102851 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-echo-ipv4
169 23:06:13.103452 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-install-packages
170 23:06:13.103972 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-installed-packages
171 23:06:13.104471 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-os-build
172 23:06:13.104961 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-probe-channel
173 23:06:13.105502 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-probe-ip
174 23:06:13.106075 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-target-ip
175 23:06:13.106590 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-target-mac
176 23:06:13.107091 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-target-storage
177 23:06:13.107606 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-test-case
178 23:06:13.108111 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-test-event
179 23:06:13.108610 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-test-feedback
180 23:06:13.109099 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-test-raise
181 23:06:13.109661 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-test-reference
182 23:06:13.110261 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-test-runner
183 23:06:13.110776 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-test-set
184 23:06:13.111271 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-test-shell
185 23:06:13.111780 Updating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-add-keys (debian)
186 23:06:13.112347 Updating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-add-sources (debian)
187 23:06:13.112879 Updating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-install-packages (debian)
188 23:06:13.113394 Updating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-installed-packages (debian)
189 23:06:13.113949 Updating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/bin/lava-os-build (debian)
190 23:06:13.114435 Creating /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/environment
191 23:06:13.114833 LAVA metadata
192 23:06:13.115100 - LAVA_JOB_ID=972559
193 23:06:13.115316 - LAVA_DISPATCHER_IP=192.168.6.3
194 23:06:13.115707 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 23:06:13.116699 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 23:06:13.117033 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 23:06:13.117243 skipped lava-vland-overlay
198 23:06:13.117487 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 23:06:13.117742 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 23:06:13.117986 skipped lava-multinode-overlay
201 23:06:13.118234 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 23:06:13.118490 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 23:06:13.118747 Loading test definitions
204 23:06:13.119030 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 23:06:13.119276 Using /lava-972559 at stage 0
206 23:06:13.120467 uuid=972559_1.6.2.4.1 testdef=None
207 23:06:13.120802 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 23:06:13.121072 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 23:06:13.122746 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 23:06:13.123558 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 23:06:13.125612 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 23:06:13.126500 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 23:06:13.128411 runner path: /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/0/tests/0_timesync-off test_uuid 972559_1.6.2.4.1
216 23:06:13.129012 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 23:06:13.129880 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 23:06:13.130121 Using /lava-972559 at stage 0
220 23:06:13.130497 Fetching tests from https://github.com/kernelci/test-definitions.git
221 23:06:13.130802 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/0/tests/1_kselftest-dt'
222 23:06:16.605371 Running '/usr/bin/git checkout kernelci.org
223 23:06:17.053558 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 23:06:17.054996 uuid=972559_1.6.2.4.5 testdef=None
225 23:06:17.055332 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 23:06:17.056083 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 23:06:17.059023 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 23:06:17.059837 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 23:06:17.063524 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 23:06:17.064376 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 23:06:17.067950 runner path: /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/0/tests/1_kselftest-dt test_uuid 972559_1.6.2.4.5
235 23:06:17.068252 BOARD='beaglebone-black'
236 23:06:17.068463 BRANCH='mainline'
237 23:06:17.068661 SKIPFILE='/dev/null'
238 23:06:17.068857 SKIP_INSTALL='True'
239 23:06:17.069051 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc7/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 23:06:17.069250 TST_CASENAME=''
241 23:06:17.069447 TST_CMDFILES='dt'
242 23:06:17.070002 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 23:06:17.070794 Creating lava-test-runner.conf files
245 23:06:17.070998 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/972559/lava-overlay-s16c317f/lava-972559/0 for stage 0
246 23:06:17.071344 - 0_timesync-off
247 23:06:17.071580 - 1_kselftest-dt
248 23:06:17.071905 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 23:06:17.072183 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 23:06:40.229016 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 23:06:40.229437 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 23:06:40.229701 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 23:06:40.230006 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 23:06:40.230276 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 23:06:40.621305 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 23:06:40.621784 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 23:06:40.622070 extracting modules file /var/lib/lava/dispatcher/tmp/972559/tftp-deploy-deppz1es/modules/modules.tar to /var/lib/lava/dispatcher/tmp/972559/extract-nfsrootfs-7pck4o3u
258 23:06:41.695010 extracting modules file /var/lib/lava/dispatcher/tmp/972559/tftp-deploy-deppz1es/modules/modules.tar to /var/lib/lava/dispatcher/tmp/972559/extract-overlay-ramdisk-55n3f45u/ramdisk
259 23:06:42.622204 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 23:06:42.622691 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 23:06:42.622976 [common] Applying overlay to NFS
262 23:06:42.623194 [common] Applying overlay /var/lib/lava/dispatcher/tmp/972559/compress-overlay-9q_bun9n/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/972559/extract-nfsrootfs-7pck4o3u
263 23:06:45.349119 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 23:06:45.349600 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 23:06:45.349900 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 23:06:45.350211 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 23:06:45.350473 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 23:06:45.350733 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 23:06:45.350984 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 23:06:45.351239 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 23:06:45.351467 Building ramdisk /var/lib/lava/dispatcher/tmp/972559/extract-overlay-ramdisk-55n3f45u/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/972559/extract-overlay-ramdisk-55n3f45u/ramdisk
272 23:06:46.384772 >> 74902 blocks
273 23:06:50.981626 Adding RAMdisk u-boot header.
274 23:06:50.982321 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/972559/extract-overlay-ramdisk-55n3f45u/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/972559/extract-overlay-ramdisk-55n3f45u/ramdisk.cpio.gz.uboot
275 23:06:51.139718 output: Image Name:
276 23:06:51.140159 output: Created: Sun Nov 10 23:06:50 2024
277 23:06:51.140637 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 23:06:51.141111 output: Data Size: 14791308 Bytes = 14444.64 KiB = 14.11 MiB
279 23:06:51.141577 output: Load Address: 00000000
280 23:06:51.142093 output: Entry Point: 00000000
281 23:06:51.142549 output:
282 23:06:51.143755 rename /var/lib/lava/dispatcher/tmp/972559/extract-overlay-ramdisk-55n3f45u/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/972559/tftp-deploy-deppz1es/ramdisk/ramdisk.cpio.gz.uboot
283 23:06:51.144563 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 23:06:51.145184 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 23:06:51.145782 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
286 23:06:51.146334 No LXC device requested
287 23:06:51.146916 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 23:06:51.147494 start: 1.8 deploy-device-env (timeout 00:08:50) [common]
289 23:06:51.148052 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 23:06:51.148522 Checking files for TFTP limit of 4294967296 bytes.
291 23:06:51.151524 end: 1 tftp-deploy (duration 00:01:10) [common]
292 23:06:51.152180 start: 2 uboot-action (timeout 00:05:00) [common]
293 23:06:51.152780 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 23:06:51.153355 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 23:06:51.153954 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 23:06:51.154822 substitutions:
297 23:06:51.155312 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 23:06:51.155798 - {DTB_ADDR}: 0x88000000
299 23:06:51.156257 - {DTB}: 972559/tftp-deploy-deppz1es/dtb/am335x-boneblack.dtb
300 23:06:51.156712 - {INITRD}: 972559/tftp-deploy-deppz1es/ramdisk/ramdisk.cpio.gz.uboot
301 23:06:51.157167 - {KERNEL_ADDR}: 0x82000000
302 23:06:51.158465 - {KERNEL}: 972559/tftp-deploy-deppz1es/kernel/zImage
303 23:06:51.158964 - {LAVA_MAC}: None
304 23:06:51.159506 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/972559/extract-nfsrootfs-7pck4o3u
305 23:06:51.159967 - {NFS_SERVER_IP}: 192.168.6.3
306 23:06:51.160420 - {PRESEED_CONFIG}: None
307 23:06:51.160884 - {PRESEED_LOCAL}: None
308 23:06:51.161350 - {RAMDISK_ADDR}: 0x83000000
309 23:06:51.162512 - {RAMDISK}: 972559/tftp-deploy-deppz1es/ramdisk/ramdisk.cpio.gz.uboot
310 23:06:51.163109 - {ROOT_PART}: None
311 23:06:51.163603 - {ROOT}: None
312 23:06:51.164076 - {SERVER_IP}: 192.168.6.3
313 23:06:51.164542 - {TEE_ADDR}: 0x83000000
314 23:06:51.164992 - {TEE}: None
315 23:06:51.165436 Parsed boot commands:
316 23:06:51.165903 - setenv autoload no
317 23:06:51.166360 - setenv initrd_high 0xffffffff
318 23:06:51.166808 - setenv fdt_high 0xffffffff
319 23:06:51.167248 - dhcp
320 23:06:51.167687 - setenv serverip 192.168.6.3
321 23:06:51.168128 - tftp 0x82000000 972559/tftp-deploy-deppz1es/kernel/zImage
322 23:06:51.168574 - tftp 0x83000000 972559/tftp-deploy-deppz1es/ramdisk/ramdisk.cpio.gz.uboot
323 23:06:51.169017 - setenv initrd_size ${filesize}
324 23:06:51.169458 - tftp 0x88000000 972559/tftp-deploy-deppz1es/dtb/am335x-boneblack.dtb
325 23:06:51.170314 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/972559/extract-nfsrootfs-7pck4o3u,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 23:06:51.170870 - bootz 0x82000000 0x83000000 0x88000000
327 23:06:51.171551 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 23:06:51.173388 start: 2.3 connect-device (timeout 00:05:00) [common]
330 23:06:51.173980 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 23:06:51.189020 Setting prompt string to ['lava-test: # ']
332 23:06:51.190758 end: 2.3 connect-device (duration 00:00:00) [common]
333 23:06:51.191484 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 23:06:51.192106 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 23:06:51.192774 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 23:06:51.194191 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 23:06:51.233451 >> OK - accepted request
338 23:06:51.235628 Returned 0 in 0 seconds
339 23:06:51.338102 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 23:06:51.339595 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 23:06:51.340053 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 23:06:51.340343 Setting prompt string to ['Hit any key to stop autoboot']
344 23:06:51.340584 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 23:06:51.341542 Trying 192.168.56.22...
346 23:06:51.341835 Connected to conserv3.
347 23:06:51.342076 Escape character is '^]'.
348 23:06:51.342296
349 23:06:51.342510 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 23:06:51.342727
351 23:07:00.341384
352 23:07:00.348251 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 23:07:00.348528 Trying to boot from MMC1
354 23:07:04.400203
355 23:07:04.406631 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
356 23:07:04.407197 Trying to boot from MMC1
357 23:07:07.101158
358 23:07:07.108003 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
359 23:07:07.108523 Trying to boot from MMC1
360 23:07:07.691188
361 23:07:07.691872
362 23:07:07.696638 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 23:07:07.697158
364 23:07:07.697612 CPU : AM335X-GP rev 2.0
365 23:07:07.701921 Model: TI AM335x BeagleBone Black
366 23:07:07.702416 DRAM: 512 MiB
367 23:07:07.781459 Core: 160 devices, 18 uclasses, devicetree: separate
368 23:07:07.795554 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
369 23:07:08.196365 NAND: 0 MiB
370 23:07:08.206486 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
371 23:07:08.303756 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
372 23:07:08.325087 <ethaddr> not set. Validating first E-fuse MAC
373 23:07:08.355425 Net: eth2: ethernet@4a100000, eth3: usb_ether
375 23:07:08.414113 Hit any key to stop autoboot: 2
376 23:07:08.414958 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
377 23:07:08.415606 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
378 23:07:08.416142 Setting prompt string to ['=>']
379 23:07:08.416672 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
380 23:07:08.424053 0
381 23:07:08.425005 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
382 23:07:08.425558 Sending with 10 millisecond of delay
384 23:07:09.560460 => setenv autoload no
385 23:07:09.571351 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
386 23:07:09.576748 setenv autoload no
387 23:07:09.577522 Sending with 10 millisecond of delay
389 23:07:11.374354 => setenv initrd_high 0xffffffff
390 23:07:11.385039 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
391 23:07:11.385664 setenv initrd_high 0xffffffff
392 23:07:11.386931 Sending with 10 millisecond of delay
394 23:07:13.003716 => setenv fdt_high 0xffffffff
395 23:07:13.014561 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
396 23:07:13.015553 setenv fdt_high 0xffffffff
397 23:07:13.016378 Sending with 10 millisecond of delay
399 23:07:13.308376 => dhcp
400 23:07:13.319146 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
401 23:07:13.320062 dhcp
402 23:07:13.320547 link up on port 0, speed 100, full duplex
403 23:07:13.321006 BOOTP broadcast 1
404 23:07:13.573662 BOOTP broadcast 2
405 23:07:14.075589 BOOTP broadcast 3
406 23:07:15.077436 BOOTP broadcast 4
407 23:07:17.079582 BOOTP broadcast 5
408 23:07:17.152623 DHCP client bound to address 192.168.6.8 (3827 ms)
409 23:07:17.153410 Sending with 10 millisecond of delay
411 23:07:18.830580 => setenv serverip 192.168.6.3
412 23:07:18.841396 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
413 23:07:18.842312 setenv serverip 192.168.6.3
414 23:07:18.843103 Sending with 10 millisecond of delay
416 23:07:22.332090 => tftp 0x82000000 972559/tftp-deploy-deppz1es/kernel/zImage
417 23:07:22.342959 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:29)
418 23:07:22.343956 tftp 0x82000000 972559/tftp-deploy-deppz1es/kernel/zImage
419 23:07:22.344433 link up on port 0, speed 100, full duplex
420 23:07:22.348240 Using ethernet@4a100000 device
421 23:07:22.354680 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
422 23:07:22.355245 Filename '972559/tftp-deploy-deppz1es/kernel/zImage'.
423 23:07:22.357246 Load address: 0x82000000
424 23:07:24.417939 Loading: *################################################## 10.9 MiB
425 23:07:24.418608 5.3 MiB/s
426 23:07:24.419078 done
427 23:07:24.422110 Bytes transferred = 11444736 (aea200 hex)
428 23:07:24.422902 Sending with 10 millisecond of delay
430 23:07:28.868472 => tftp 0x83000000 972559/tftp-deploy-deppz1es/ramdisk/ramdisk.cpio.gz.uboot
431 23:07:28.879053 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
432 23:07:28.880001 tftp 0x83000000 972559/tftp-deploy-deppz1es/ramdisk/ramdisk.cpio.gz.uboot
433 23:07:28.880473 link up on port 0, speed 100, full duplex
434 23:07:28.884991 Using ethernet@4a100000 device
435 23:07:28.890480 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
436 23:07:28.894023 Filename '972559/tftp-deploy-deppz1es/ramdisk/ramdisk.cpio.gz.uboot'.
437 23:07:28.899007 Load address: 0x83000000
438 23:07:31.639847 Loading: *################################################## 14.1 MiB
439 23:07:31.640511 5.1 MiB/s
440 23:07:31.640982 done
441 23:07:31.644143 Bytes transferred = 14791372 (e1b2cc hex)
442 23:07:31.644924 Sending with 10 millisecond of delay
444 23:07:33.502168 => setenv initrd_size ${filesize}
445 23:07:33.513013 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
446 23:07:33.513926 setenv initrd_size ${filesize}
447 23:07:33.514698 Sending with 10 millisecond of delay
449 23:07:37.661015 => tftp 0x88000000 972559/tftp-deploy-deppz1es/dtb/am335x-boneblack.dtb
450 23:07:37.671839 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
451 23:07:37.672714 tftp 0x88000000 972559/tftp-deploy-deppz1es/dtb/am335x-boneblack.dtb
452 23:07:37.673153 link up on port 0, speed 100, full duplex
453 23:07:37.676772 Using ethernet@4a100000 device
454 23:07:37.682421 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
455 23:07:37.693538 Filename '972559/tftp-deploy-deppz1es/dtb/am335x-boneblack.dtb'.
456 23:07:37.694055 Load address: 0x88000000
457 23:07:37.704621 Loading: *################################################## 68.9 KiB
458 23:07:37.705090 4.5 MiB/s
459 23:07:37.712898 done
460 23:07:37.713351 Bytes transferred = 70568 (113a8 hex)
461 23:07:37.714025 Sending with 10 millisecond of delay
463 23:07:50.895400 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/972559/extract-nfsrootfs-7pck4o3u,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
464 23:07:50.905938 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
465 23:07:50.906394 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/972559/extract-nfsrootfs-7pck4o3u,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
466 23:07:50.906999 Sending with 10 millisecond of delay
468 23:07:53.251674 => bootz 0x82000000 0x83000000 0x88000000
469 23:07:53.262510 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
470 23:07:53.263078 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
471 23:07:53.264136 bootz 0x82000000 0x83000000 0x88000000
472 23:07:53.264606 Kernel image @ 0x82000000 [ 0x000000 - 0xaea200 ]
473 23:07:53.265137 ## Loading init Ramdisk from Legacy Image at 83000000 ...
474 23:07:53.270203 Image Name:
475 23:07:53.270683 Created: 2024-11-10 23:06:50 UTC
476 23:07:53.273686 Image Type: ARM Linux RAMDisk Image (uncompressed)
477 23:07:53.279079 Data Size: 14791308 Bytes = 14.1 MiB
478 23:07:53.287499 Load Address: 00000000
479 23:07:53.287977 Entry Point: 00000000
480 23:07:53.455662 Verifying Checksum ... OK
481 23:07:53.456038 ## Flattened Device Tree blob at 88000000
482 23:07:53.462168 Booting using the fdt blob at 0x88000000
483 23:07:53.462419 Working FDT set to 88000000
484 23:07:53.467706 Using Device Tree in place at 88000000, end 880143a7
485 23:07:53.471506 Working FDT set to 88000000
486 23:07:53.485801
487 23:07:53.486924 Starting kernel ...
488 23:07:53.487547
489 23:07:53.488564 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
490 23:07:53.489883 start: 2.4.4 auto-login-action (timeout 00:03:58) [common]
491 23:07:53.490363 Setting prompt string to ['Linux version [0-9]']
492 23:07:53.490600 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
493 23:07:53.491021 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
494 23:07:54.326546 [ 0.000000] Booting Linux on physical CPU 0x0
495 23:07:54.332402 start: 2.4.4.1 login-action (timeout 00:03:57) [common]
496 23:07:54.332985 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
497 23:07:54.333501 Setting prompt string to []
498 23:07:54.334102 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
499 23:07:54.334621 Using line separator: #'\n'#
500 23:07:54.335078 No login prompt set.
501 23:07:54.335552 Parsing kernel messages
502 23:07:54.335999 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
503 23:07:54.336878 [login-action] Waiting for messages, (timeout 00:03:57)
504 23:07:54.337366 Waiting using forced prompt support (timeout 00:01:58)
505 23:07:54.349217 [ 0.000000] Linux version 6.12.0-rc7 (KernelCI@build-j372091-arm-gcc-12-multi-v7-defconfig-9fwtl) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Sun Nov 10 22:47:11 UTC 2024
506 23:07:54.354959 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
507 23:07:54.360578 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
508 23:07:54.372041 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
509 23:07:54.377735 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
510 23:07:54.383498 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
511 23:07:54.383986 [ 0.000000] Memory policy: Data cache writeback
512 23:07:54.390196 [ 0.000000] efi: UEFI not found.
513 23:07:54.395678 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
514 23:07:54.401354 [ 0.000000] Zone ranges:
515 23:07:54.407206 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
516 23:07:54.412848 [ 0.000000] Normal empty
517 23:07:54.413330 [ 0.000000] HighMem empty
518 23:07:54.415783 [ 0.000000] Movable zone start for each node
519 23:07:54.421629 [ 0.000000] Early memory node ranges
520 23:07:54.427300 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
521 23:07:54.434488 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
522 23:07:54.460679 [ 0.000000] CPU: All CPU(s) started in SVC mode.
523 23:07:54.466431 [ 0.000000] AM335X ES2.0 (sgx neon)
524 23:07:54.478033 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
525 23:07:54.495686 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/972559/extract-nfsrootfs-7pck4o3u,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
526 23:07:54.507220 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
527 23:07:54.512986 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
528 23:07:54.518655 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
529 23:07:54.528632 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
530 23:07:54.557623 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
531 23:07:54.563587 <6>[ 0.000000] trace event string verifier disabled
532 23:07:54.564080 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
533 23:07:54.571752 <6>[ 0.000000] rcu: RCU event tracing is enabled.
534 23:07:54.577488 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
535 23:07:54.588989 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
536 23:07:54.593789 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
537 23:07:54.608826 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
538 23:07:54.626022 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
539 23:07:54.632760 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
540 23:07:54.725307 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
541 23:07:54.736720 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
542 23:07:54.743480 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
543 23:07:54.756542 <6>[ 0.019143] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
544 23:07:54.763858 <6>[ 0.033957] Console: colour dummy device 80x30
545 23:07:54.770029 Matched prompt #6: WARNING:
546 23:07:54.770550 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
547 23:07:54.775508 <3>[ 0.038857] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
548 23:07:54.781309 <3>[ 0.045926] This ensures that you still see kernel messages. Please
549 23:07:54.784525 <3>[ 0.052653] update your kernel commandline.
550 23:07:54.825141 <6>[ 0.057266] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
551 23:07:54.830829 <6>[ 0.096150] CPU: Testing write buffer coherency: ok
552 23:07:54.836817 <6>[ 0.101516] CPU0: Spectre v2: using BPIALL workaround
553 23:07:54.837300 <6>[ 0.106983] pid_max: default: 32768 minimum: 301
554 23:07:54.848279 <6>[ 0.112176] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
555 23:07:54.855289 <6>[ 0.119995] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
556 23:07:54.862276 <6>[ 0.129353] CPU0: thread -1, cpu 0, socket -1, mpidr 0
557 23:07:54.870671 <6>[ 0.136351] Setting up static identity map for 0x80300000 - 0x803000ac
558 23:07:54.876478 <6>[ 0.145985] rcu: Hierarchical SRCU implementation.
559 23:07:54.883305 <6>[ 0.151264] rcu: Max phase no-delay instances is 1000.
560 23:07:54.892721 <6>[ 0.162399] EFI services will not be available.
561 23:07:54.898446 <6>[ 0.167673] smp: Bringing up secondary CPUs ...
562 23:07:54.904286 <6>[ 0.172721] smp: Brought up 1 node, 1 CPU
563 23:07:54.909950 <6>[ 0.177119] SMP: Total of 1 processors activated (996.14 BogoMIPS).
564 23:07:54.915863 <6>[ 0.183888] CPU: All CPU(s) started in SVC mode.
565 23:07:54.936252 <6>[ 0.189068] Memory: 405996K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
566 23:07:54.936551 <6>[ 0.205343] devtmpfs: initialized
567 23:07:54.958260 <6>[ 0.222298] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
568 23:07:54.969841 <6>[ 0.230877] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
569 23:07:54.974811 <6>[ 0.241332] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
570 23:07:54.986516 <6>[ 0.253681] pinctrl core: initialized pinctrl subsystem
571 23:07:54.995811 <6>[ 0.264312] DMI not present or invalid.
572 23:07:55.004098 <6>[ 0.270183] NET: Registered PF_NETLINK/PF_ROUTE protocol family
573 23:07:55.013621 <6>[ 0.279095] DMA: preallocated 256 KiB pool for atomic coherent allocations
574 23:07:55.028770 <6>[ 0.290647] thermal_sys: Registered thermal governor 'step_wise'
575 23:07:55.029267 <6>[ 0.290807] cpuidle: using governor menu
576 23:07:55.056434 <6>[ 0.326380] No ATAGs?
577 23:07:55.062435 <6>[ 0.329022] hw-breakpoint: debug architecture 0x4 unsupported.
578 23:07:55.072670 <6>[ 0.341017] Serial: AMBA PL011 UART driver
579 23:07:55.104991 <6>[ 0.374952] iommu: Default domain type: Translated
580 23:07:55.114119 <6>[ 0.380296] iommu: DMA domain TLB invalidation policy: strict mode
581 23:07:55.141503 <5>[ 0.410904] SCSI subsystem initialized
582 23:07:55.147371 <6>[ 0.415794] usbcore: registered new interface driver usbfs
583 23:07:55.153123 <6>[ 0.421820] usbcore: registered new interface driver hub
584 23:07:55.161903 <6>[ 0.427597] usbcore: registered new device driver usb
585 23:07:55.167645 <6>[ 0.434096] pps_core: LinuxPPS API ver. 1 registered
586 23:07:55.173372 <6>[ 0.439525] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
587 23:07:55.179308 <6>[ 0.449208] PTP clock support registered
588 23:07:55.184385 <6>[ 0.453663] EDAC MC: Ver: 3.0.0
589 23:07:55.232447 <6>[ 0.499825] scmi_core: SCMI protocol bus registered
590 23:07:55.247795 <6>[ 0.517166] vgaarb: loaded
591 23:07:55.253970 <6>[ 0.521009] clocksource: Switched to clocksource dmtimer
592 23:07:55.296708 <6>[ 0.566418] NET: Registered PF_INET protocol family
593 23:07:55.309221 <6>[ 0.572081] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
594 23:07:55.316409 <6>[ 0.580894] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
595 23:07:55.322151 <6>[ 0.589824] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
596 23:07:55.333676 <6>[ 0.598083] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
597 23:07:55.339534 <6>[ 0.606363] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
598 23:07:55.345402 <6>[ 0.614086] TCP: Hash tables configured (established 4096 bind 4096)
599 23:07:55.356828 <6>[ 0.621010] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
600 23:07:55.362794 <6>[ 0.628022] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
601 23:07:55.368890 <6>[ 0.635629] NET: Registered PF_UNIX/PF_LOCAL protocol family
602 23:07:55.445850 <6>[ 0.710199] RPC: Registered named UNIX socket transport module.
603 23:07:55.446448 <6>[ 0.716629] RPC: Registered udp transport module.
604 23:07:55.451606 <6>[ 0.721759] RPC: Registered tcp transport module.
605 23:07:55.457271 <6>[ 0.726865] RPC: Registered tcp-with-tls transport module.
606 23:07:55.470309 <6>[ 0.732787] RPC: Registered tcp NFSv4.1 backchannel transport module.
607 23:07:55.470838 <6>[ 0.739692] PCI: CLS 0 bytes, default 64
608 23:07:55.477409 <5>[ 0.745473] Initialise system trusted keyrings
609 23:07:55.497761 <6>[ 0.765555] Trying to unpack rootfs image as initramfs...
610 23:07:55.577911 <6>[ 0.841757] workingset: timestamp_bits=30 max_order=17 bucket_order=0
611 23:07:55.582681 <6>[ 0.849253] squashfs: version 4.0 (2009/01/31) Phillip Lougher
612 23:07:55.621701 <5>[ 0.891739] NFS: Registering the id_resolver key type
613 23:07:55.627521 <5>[ 0.897343] Key type id_resolver registered
614 23:07:55.633383 <5>[ 0.902017] Key type id_legacy registered
615 23:07:55.639153 <6>[ 0.906460] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
616 23:07:55.648648 <6>[ 0.913656] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
617 23:07:55.717970 <5>[ 0.987968] Key type asymmetric registered
618 23:07:55.723856 <5>[ 0.992543] Asymmetric key parser 'x509' registered
619 23:07:55.732217 <6>[ 0.997969] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
620 23:07:55.737954 <6>[ 1.005882] io scheduler mq-deadline registered
621 23:07:55.746762 <6>[ 1.010811] io scheduler kyber registered
622 23:07:55.747275 <6>[ 1.015299] io scheduler bfq registered
623 23:07:55.851109 <6>[ 1.117431] ledtrig-cpu: registered to indicate activity on CPUs
624 23:07:56.141778 <6>[ 1.407780] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
625 23:07:56.186944 <6>[ 1.456392] msm_serial: driver initialized
626 23:07:56.192745 <6>[ 1.461392] SuperH (H)SCI(F) driver initialized
627 23:07:56.198644 <6>[ 1.466505] STMicroelectronics ASC driver initialized
628 23:07:56.203852 <6>[ 1.472155] STM32 USART driver initialized
629 23:07:56.302764 <6>[ 1.573044] brd: module loaded
630 23:07:56.362119 <6>[ 1.631963] loop: module loaded
631 23:07:56.391920 <6>[ 1.661233] CAN device driver interface
632 23:07:56.398668 <6>[ 1.666263] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
633 23:07:56.404349 <6>[ 1.673368] e1000e: Intel(R) PRO/1000 Network Driver
634 23:07:56.410258 <6>[ 1.678759] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
635 23:07:56.415925 <6>[ 1.685227] igb: Intel(R) Gigabit Ethernet Network Driver
636 23:07:56.423355 <6>[ 1.691074] igb: Copyright (c) 2007-2014 Intel Corporation.
637 23:07:56.435901 <6>[ 1.700277] pegasus: Pegasus/Pegasus II USB Ethernet driver
638 23:07:56.441894 <6>[ 1.706428] usbcore: registered new interface driver pegasus
639 23:07:56.447621 <6>[ 1.712590] usbcore: registered new interface driver asix
640 23:07:56.453381 <6>[ 1.718442] usbcore: registered new interface driver ax88179_178a
641 23:07:56.459135 <6>[ 1.725033] usbcore: registered new interface driver cdc_ether
642 23:07:56.464925 <6>[ 1.731348] usbcore: registered new interface driver smsc75xx
643 23:07:56.470768 <6>[ 1.737553] usbcore: registered new interface driver smsc95xx
644 23:07:56.476624 <6>[ 1.743790] usbcore: registered new interface driver net1080
645 23:07:56.482268 <6>[ 1.749908] usbcore: registered new interface driver cdc_subset
646 23:07:56.488070 <6>[ 1.756319] usbcore: registered new interface driver zaurus
647 23:07:56.495713 <6>[ 1.762383] usbcore: registered new interface driver cdc_ncm
648 23:07:56.505658 <6>[ 1.771983] usbcore: registered new interface driver usb-storage
649 23:07:56.515020 <6>[ 1.783064] i2c_dev: i2c /dev entries driver
650 23:07:56.538633 <5>[ 1.800747] cpuidle: enable-method property 'ti,am3352' found operations
651 23:07:56.544645 <6>[ 1.810250] sdhci: Secure Digital Host Controller Interface driver
652 23:07:56.552458 <6>[ 1.817010] sdhci: Copyright(c) Pierre Ossman
653 23:07:56.559087 <6>[ 1.823404] Synopsys Designware Multimedia Card Interface Driver
654 23:07:56.564710 <6>[ 1.831248] sdhci-pltfm: SDHCI platform and OF driver helper
655 23:07:56.578377 <6>[ 1.840883] usbcore: registered new interface driver usbhid
656 23:07:56.578909 <6>[ 1.847002] usbhid: USB HID core driver
657 23:07:56.590929 <6>[ 1.858292] NET: Registered PF_INET6 protocol family
658 23:07:57.033584 <6>[ 2.303561] Segment Routing with IPv6
659 23:07:57.039439 <6>[ 2.307709] In-situ OAM (IOAM) with IPv6
660 23:07:57.046157 <6>[ 2.312249] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
661 23:07:57.051945 <6>[ 2.319536] NET: Registered PF_PACKET protocol family
662 23:07:57.057756 <6>[ 2.325094] can: controller area network core
663 23:07:57.063580 <6>[ 2.329918] NET: Registered PF_CAN protocol family
664 23:07:57.064099 <6>[ 2.335155] can: raw protocol
665 23:07:57.069352 <6>[ 2.338480] can: broadcast manager protocol
666 23:07:57.075806 <6>[ 2.343076] can: netlink gateway - max_hops=1
667 23:07:57.081962 <5>[ 2.348579] Key type dns_resolver registered
668 23:07:57.088271 <6>[ 2.353649] ThumbEE CPU extension supported.
669 23:07:57.088810 <5>[ 2.358335] Registering SWP/SWPB emulation handler
670 23:07:57.097909 <3>[ 2.364039] omap_voltage_late_init: Voltage driver support not added
671 23:07:57.303950 <5>[ 2.571568] Loading compiled-in X.509 certificates
672 23:07:57.442124 <6>[ 2.699337] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
673 23:07:57.449294 <6>[ 2.715979] pinctrl-single 44e10800.pinmux: 142 pins, size 568
674 23:07:57.475496 <3>[ 2.739553] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
675 23:07:57.686220 <3>[ 2.950279] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
676 23:07:57.875872 <6>[ 3.144115] OMAP GPIO hardware version 0.1
677 23:07:57.896517 <6>[ 3.162889] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
678 23:07:57.987026 <4>[ 3.253302] at24 2-0054: supply vcc not found, using dummy regulator
679 23:07:58.021287 <4>[ 3.287302] at24 2-0055: supply vcc not found, using dummy regulator
680 23:07:58.062290 <4>[ 3.328347] at24 2-0056: supply vcc not found, using dummy regulator
681 23:07:58.102509 <4>[ 3.368572] at24 2-0057: supply vcc not found, using dummy regulator
682 23:07:58.139659 <6>[ 3.406525] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
683 23:07:58.210122 <3>[ 3.473583] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
684 23:07:58.235266 <6>[ 3.494383] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
685 23:07:58.256899 <4>[ 3.520309] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
686 23:07:58.264720 <4>[ 3.529491] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
687 23:07:58.415156 <6>[ 3.681349] omap_rng 48310000.rng: Random Number Generator ver. 20
688 23:07:58.438425 <5>[ 3.707429] random: crng init done
689 23:07:58.486638 <6>[ 3.751341] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
690 23:07:58.521579 <6>[ 3.789853] Freeing initrd memory: 14448K
691 23:07:58.569865 <6>[ 3.833536] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
692 23:07:58.575663 <6>[ 3.843877] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
693 23:07:58.587351 <6>[ 3.851248] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
694 23:07:58.593157 <6>[ 3.858700] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
695 23:07:58.604621 <6>[ 3.866830] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
696 23:07:58.612033 <6>[ 3.878465] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
697 23:07:58.625182 <5>[ 3.887492] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
698 23:07:58.652845 <3>[ 3.917109] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
699 23:07:58.658620 <6>[ 3.925696] edma 49000000.dma: TI EDMA DMA engine driver
700 23:07:58.729196 <3>[ 3.992840] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
701 23:07:58.743955 <6>[ 4.007153] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
702 23:07:58.755897 <3>[ 4.024200] l3-aon-clkctrl:0000:0: failed to disable
703 23:07:58.804910 <6>[ 4.069198] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
704 23:07:58.810682 <6>[ 4.078705] printk: legacy console [ttyS0] enabled
705 23:07:58.816377 <6>[ 4.078705] printk: legacy console [ttyS0] enabled
706 23:07:58.822143 <6>[ 4.089043] printk: legacy bootconsole [omap8250] disabled
707 23:07:58.828002 <6>[ 4.089043] printk: legacy bootconsole [omap8250] disabled
708 23:07:58.868439 <4>[ 4.131740] tps65217-pmic: Failed to locate of_node [id: -1]
709 23:07:58.872064 <4>[ 4.139134] tps65217-bl: Failed to locate of_node [id: -1]
710 23:07:58.888292 <6>[ 4.158562] tps65217 0-0024: TPS65217 ID 0xe version 1.2
711 23:07:58.906783 <6>[ 4.165479] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
712 23:07:58.918491 <6>[ 4.179167] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
713 23:07:58.923411 <6>[ 4.191072] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
714 23:07:58.946552 <6>[ 4.210755] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
715 23:07:58.952283 <6>[ 4.219990] sdhci-omap 48060000.mmc: Got CD GPIO
716 23:07:58.960323 <4>[ 4.225182] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
717 23:07:58.975229 <4>[ 4.238724] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
718 23:07:58.981502 <4>[ 4.247471] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
719 23:07:58.991299 <4>[ 4.256114] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
720 23:07:59.064432 <6>[ 4.330081] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
721 23:07:59.100779 <6>[ 4.365996] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
722 23:07:59.124216 <6>[ 4.388141] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
723 23:07:59.130880 <6>[ 4.397078] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
724 23:07:59.187111 <6>[ 4.447930] mmc1: new high speed MMC card at address 0001
725 23:07:59.187690 <6>[ 4.455233] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
726 23:07:59.195831 <6>[ 4.464384] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
727 23:07:59.204719 <6>[ 4.472373] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
728 23:07:59.217288 <6>[ 4.480672] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
729 23:07:59.225426 <6>[ 4.488492] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
730 23:07:59.250599 <6>[ 4.511901] mmc0: new high speed SDHC card at address aaaa
731 23:07:59.251167 <6>[ 4.518810] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
732 23:07:59.261386 <6>[ 4.529491] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
733 23:08:01.337907 <6>[ 6.602109] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
734 23:08:01.491152 <5>[ 6.641098] Sending DHCP requests ., OK
735 23:08:01.502439 <6>[ 6.765523] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.8
736 23:08:01.503047 <6>[ 6.773558] IP-Config: Complete:
737 23:08:01.513715 <6>[ 6.777098] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.8, mask=255.255.255.0, gw=192.168.6.1
738 23:08:01.519511 <6>[ 6.787547] host=192.168.6.8, domain=, nis-domain=(none)
739 23:08:01.525051 <6>[ 6.793674] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
740 23:08:01.531856 <6>[ 6.793708] nameserver0=10.255.253.1
741 23:08:01.537748 <6>[ 6.806261] clk: Disabling unused clocks
742 23:08:01.542524 <6>[ 6.810867] PM: genpd: Disabling unused power domains
743 23:08:01.562937 <6>[ 6.829625] Freeing unused kernel image (initmem) memory: 2048K
744 23:08:01.570389 <6>[ 6.839311] Run /init as init process
745 23:08:01.592080 Loading, please wait...
746 23:08:01.668185 Starting systemd-udevd version 252.22-1~deb12u1
747 23:08:04.645046 <4>[ 9.907689] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
748 23:08:04.829881 <4>[ 10.092551] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
749 23:08:04.979962 <6>[ 10.250319] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
750 23:08:04.991017 <6>[ 10.256213] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
751 23:08:05.272835 <6>[ 10.541618] hub 1-0:1.0: USB hub found
752 23:08:05.280416 <6>[ 10.549130] hub 1-0:1.0: 1 port detected
753 23:08:05.437115 <6>[ 10.705411] tda998x 0-0070: found TDA19988
754 23:08:08.409293 Begin: Loading essential drivers ... done.
755 23:08:08.414668 Begin: Running /scripts/init-premount ... done.
756 23:08:08.420197 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
757 23:08:08.428114 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
758 23:08:08.434198 Device /sys/class/net/eth0 found
759 23:08:08.434692 done.
760 23:08:08.511994 Begin: Waiting up to 180 secs for any network device to become available ... done.
761 23:08:08.583701 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
762 23:08:08.691413 IP-Config: eth0 guessed broadcast address 192.168.6.255
763 23:08:08.696989 IP-Config: eth0 complete (dhcp from 192.168.6.1):
764 23:08:08.702615 address: 192.168.6.8 broadcast: 192.168.6.255 netmask: 255.255.255.0
765 23:08:08.713723 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
766 23:08:08.714267 rootserver: 192.168.6.1 rootpath:
767 23:08:08.717389 filename :
768 23:08:08.822709 done.
769 23:08:08.829887 Begin: Running /scripts/nfs-bottom ... done.
770 23:08:08.903426 Begin: Running /scripts/init-bottom ... done.
771 23:08:10.398359 <30>[ 15.664610] systemd[1]: System time before build time, advancing clock.
772 23:08:10.617319 <30>[ 15.857458] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
773 23:08:10.626170 <30>[ 15.894247] systemd[1]: Detected architecture arm.
774 23:08:10.638375
775 23:08:10.638920 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
776 23:08:10.639389
777 23:08:10.664632 <30>[ 15.931463] systemd[1]: Hostname set to <debian-bookworm-armhf>.
778 23:08:12.800602 <30>[ 18.066415] systemd[1]: Queued start job for default target graphical.target.
779 23:08:12.817319 <30>[ 18.081317] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
780 23:08:12.824936 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
781 23:08:12.850939 <30>[ 18.114466] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
782 23:08:12.858413 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
783 23:08:12.879949 <30>[ 18.144017] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
784 23:08:12.888280 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
785 23:08:12.908640 <30>[ 18.172922] systemd[1]: Created slice user.slice - User and Session Slice.
786 23:08:12.915318 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
787 23:08:12.944002 <30>[ 18.202395] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
788 23:08:12.950091 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
789 23:08:12.968082 <30>[ 18.232176] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
790 23:08:12.979096 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
791 23:08:13.008969 <30>[ 18.262222] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
792 23:08:13.015448 <30>[ 18.282731] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
793 23:08:13.024024 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
794 23:08:13.047122 <30>[ 18.311555] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
795 23:08:13.054710 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
796 23:08:13.077928 <30>[ 18.341887] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
797 23:08:13.086257 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
798 23:08:13.107677 <30>[ 18.372044] systemd[1]: Reached target paths.target - Path Units.
799 23:08:13.112810 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
800 23:08:13.137310 <30>[ 18.401676] systemd[1]: Reached target remote-fs.target - Remote File Systems.
801 23:08:13.144763 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
802 23:08:13.167188 <30>[ 18.431596] systemd[1]: Reached target slices.target - Slice Units.
803 23:08:13.173008 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
804 23:08:13.197593 <30>[ 18.461791] systemd[1]: Reached target swap.target - Swaps.
805 23:08:13.201648 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
806 23:08:13.227830 <30>[ 18.491811] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
807 23:08:13.235908 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
808 23:08:13.258689 <30>[ 18.522628] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
809 23:08:13.269147 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
810 23:08:13.346158 <30>[ 18.605409] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
811 23:08:13.358986 <30>[ 18.623035] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
812 23:08:13.367345 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
813 23:08:13.390708 <30>[ 18.653804] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
814 23:08:13.398063 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
815 23:08:13.420014 <30>[ 18.684085] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
816 23:08:13.428267 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
817 23:08:13.453066 <30>[ 18.716016] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
818 23:08:13.458729 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
819 23:08:13.490045 <30>[ 18.752760] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
820 23:08:13.497503 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
821 23:08:13.524717 <30>[ 18.782811] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
822 23:08:13.543309 <30>[ 18.801383] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
823 23:08:13.587734 <30>[ 18.852671] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
824 23:08:13.610914 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
825 23:08:13.669252 <30>[ 18.934114] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
826 23:08:13.691156 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
827 23:08:13.768411 <30>[ 19.032318] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
828 23:08:13.787822 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
829 23:08:13.851081 <30>[ 19.115493] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
830 23:08:13.875466 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
831 23:08:13.929423 <30>[ 19.194254] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
832 23:08:13.956201 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
833 23:08:14.007232 <30>[ 19.272431] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
834 23:08:14.028956 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
835 23:08:14.090268 <30>[ 19.354377] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
836 23:08:14.116664 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
837 23:08:14.166948 <30>[ 19.432836] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
838 23:08:14.188002 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
839 23:08:14.222362 <30>[ 19.487558] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
840 23:08:14.245365 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
841 23:08:14.274607 <28>[ 19.533386] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
842 23:08:14.283096 <28>[ 19.547374] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
843 23:08:14.328414 <30>[ 19.592377] systemd[1]: Starting systemd-journald.service - Journal Service...
844 23:08:14.334901 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
845 23:08:14.377636 <30>[ 19.642524] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
846 23:08:14.396500 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
847 23:08:14.435649 <30>[ 19.700815] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
848 23:08:14.485431 Starting [0;1;39msystemd-network-g… units from Kernel command line...
849 23:08:14.553088 <30>[ 19.816600] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
850 23:08:14.601080 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
851 23:08:14.667897 <30>[ 19.933021] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
852 23:08:14.726122 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
853 23:08:14.790331 <30>[ 20.055510] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
854 23:08:14.846749 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
855 23:08:14.867699 <30>[ 20.132750] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
856 23:08:14.890344 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
857 23:08:14.923455 <30>[ 20.187461] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
858 23:08:14.946181 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
859 23:08:15.118249 <30>[ 20.383871] systemd[1]: modprobe@configfs.service: Deactivated successfully.
860 23:08:15.148199 <30>[ 20.412944] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
861 23:08:15.176167 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
862 23:08:15.197069 <30>[ 20.463886] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
863 23:08:15.237664 <30>[ 20.502737] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
864 23:08:15.266723 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
865 23:08:15.286909 <30>[ 20.552929] systemd[1]: Started systemd-journald.service - Journal Service.
866 23:08:15.305693 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
867 23:08:15.346843 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
868 23:08:15.378163 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
869 23:08:15.410944 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
870 23:08:15.442746 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
871 23:08:15.477326 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
872 23:08:15.499692 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
873 23:08:15.520354 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
874 23:08:15.557074 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
875 23:08:15.616656 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
876 23:08:15.658505 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
877 23:08:15.709561 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
878 23:08:15.800758 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
879 23:08:15.870594 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
880 23:08:16.047202 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
881 23:08:16.058960 <46>[ 21.324214] systemd-journald[164]: Received client request to flush runtime journal.
882 23:08:16.140599 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
883 23:08:16.293060 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
884 23:08:17.319348 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
885 23:08:17.379400 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
886 23:08:17.694087 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
887 23:08:17.920123 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
888 23:08:17.956961 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
889 23:08:17.976065 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
890 23:08:18.058487 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
891 23:08:18.095065 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
892 23:08:19.019204 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
893 23:08:19.077224 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
894 23:08:19.285200 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
895 23:08:19.387477 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
896 23:08:19.447093 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
897 23:08:21.297355 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
898 23:08:21.647182 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
899 23:08:22.136093 <5>[ 27.402395] cfg80211: Loading compiled-in X.509 certificates for regulatory database
900 23:08:22.747534 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
901 23:08:23.714682 <5>[ 28.983278] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
902 23:08:23.824868 <5>[ 29.091871] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
903 23:08:23.852522 <4>[ 29.117791] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
904 23:08:23.857419 <6>[ 29.126903] cfg80211: failed to load regulatory.db
905 23:08:24.437805 <46>[ 29.694279] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
906 23:08:24.566884 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
907 23:08:24.605561 <46>[ 29.865215] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
908 23:08:24.781134 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
909 23:08:33.555731 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
910 23:08:33.581071 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
911 23:08:33.607850 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
912 23:08:33.631321 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
913 23:08:33.706547 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
914 23:08:33.757456 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
915 23:08:33.809699 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
916 23:08:33.862678 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
917 23:08:33.909961 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
918 23:08:33.944233 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
919 23:08:33.971561 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
920 23:08:34.011777 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
921 23:08:34.053330 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
922 23:08:34.083333 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
923 23:08:34.159843 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
924 23:08:34.195026 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
925 23:08:34.223033 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
926 23:08:34.250794 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
927 23:08:34.282064 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
928 23:08:34.306152 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
929 23:08:34.333448 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
930 23:08:34.356190 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
931 23:08:34.378730 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
932 23:08:34.456553 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
933 23:08:34.507140 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
934 23:08:34.595955 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
935 23:08:34.678301 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
936 23:08:34.758385 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
937 23:08:34.796076 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
938 23:08:34.808005 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
939 23:08:35.008241 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
940 23:08:35.067406 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
941 23:08:35.128177 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
942 23:08:35.139544 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
943 23:08:35.177244 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
944 23:08:35.399283 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
945 23:08:35.752297 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
946 23:08:35.805977 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
947 23:08:35.833124 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
948 23:08:35.916795 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
949 23:08:36.084703 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
950 23:08:36.202848
951 23:08:36.205548 Debian GNU/Linux 12 deworm-armhf login: root (automatic login)
952 23:08:36.206357
953 23:08:36.513767 Linux debian-bookworm-armhf 6.12.0-rc7 #1 SMP Sun Nov 10 22:47:11 UTC 2024 armv7l
954 23:08:36.514492
955 23:08:36.519368 The programs included with the Debian GNU/Linux system are free software;
956 23:08:36.522620 the exact distribution terms for each program are described in the
957 23:08:36.528564 individual files in /usr/share/doc/*/copyright.
958 23:08:36.529097
959 23:08:36.533734 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
960 23:08:36.537289 permitted by applicable law.
961 23:08:41.580285 Unable to match end of the kernel message
963 23:08:41.581961 Setting prompt string to ['/ #']
964 23:08:41.582572 end: 2.4.4.1 login-action (duration 00:00:47) [common]
966 23:08:41.584075 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
967 23:08:41.584721 start: 2.4.5 expect-shell-connection (timeout 00:03:10) [common]
968 23:08:41.585237 Setting prompt string to ['/ #']
969 23:08:41.585718 Forcing a shell prompt, looking for ['/ #']
971 23:08:41.636813 / #
972 23:08:41.637546 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
973 23:08:41.638129 Waiting using forced prompt support (timeout 00:02:30)
974 23:08:41.641063
975 23:08:41.644213 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
976 23:08:41.644849 start: 2.4.6 export-device-env (timeout 00:03:10) [common]
977 23:08:41.645398 Sending with 10 millisecond of delay
979 23:08:46.633417 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/972559/extract-nfsrootfs-7pck4o3u'
980 23:08:46.644335 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/972559/extract-nfsrootfs-7pck4o3u'
981 23:08:46.645608 Sending with 10 millisecond of delay
983 23:08:48.742904 / # export NFS_SERVER_IP='192.168.6.3'
984 23:08:48.753880 export NFS_SERVER_IP='192.168.6.3'
985 23:08:48.754819 end: 2.4.6 export-device-env (duration 00:00:07) [common]
986 23:08:48.755495 end: 2.4 uboot-commands (duration 00:01:58) [common]
987 23:08:48.756143 end: 2 uboot-action (duration 00:01:58) [common]
988 23:08:48.756772 start: 3 lava-test-retry (timeout 00:06:52) [common]
989 23:08:48.757411 start: 3.1 lava-test-shell (timeout 00:06:52) [common]
990 23:08:48.757968 Using namespace: common
992 23:08:48.859218 / # #
993 23:08:48.859893 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
994 23:08:48.863685 #
995 23:08:48.871155 Using /lava-972559
997 23:08:48.972370 / # export SHELL=/bin/bash
998 23:08:48.977705 export SHELL=/bin/bash
1000 23:08:49.084143 / # . /lava-972559/environment
1001 23:08:49.089524 . /lava-972559/environment
1003 23:08:49.202742 / # /lava-972559/bin/lava-test-runner /lava-972559/0
1004 23:08:49.203552 Test shell timeout: 10s (minimum of the action and connection timeout)
1005 23:08:49.207210 /lava-972559/bin/lava-test-runner /lava-972559/0
1006 23:08:49.592119 + export TESTRUN_ID=0_timesync-off
1007 23:08:49.598972 + TESTRUN_ID=0_timesync-off
1008 23:08:49.599504 + cd /lava-972559/0/tests/0_timesync-off
1009 23:08:49.599979 ++ cat uuid
1010 23:08:49.633326 + UUID=972559_1.6.2.4.1
1011 23:08:49.634012 + set +x
1012 23:08:49.641134 <LAVA_SIGNAL_STARTRUN 0_timesync-off 972559_1.6.2.4.1>
1013 23:08:49.641954 + systemctl stop systemd-timesyncd
1014 23:08:49.642883 Received signal: <STARTRUN> 0_timesync-off 972559_1.6.2.4.1
1015 23:08:49.643519 Starting test lava.0_timesync-off (972559_1.6.2.4.1)
1016 23:08:49.644146 Skipping test definition patterns.
1017 23:08:49.930049 + set +x
1018 23:08:49.930696 <LAVA_SIGNAL_ENDRUN 0_timesync-off 972559_1.6.2.4.1>
1019 23:08:49.931471 Received signal: <ENDRUN> 0_timesync-off 972559_1.6.2.4.1
1020 23:08:49.932034 Ending use of test pattern.
1021 23:08:49.932564 Ending test lava.0_timesync-off (972559_1.6.2.4.1), duration 0.29
1023 23:08:50.085025 + export TESTRUN_ID=1_kselftest-dt
1024 23:08:50.092330 + TESTRUN_ID=1_kselftest-dt
1025 23:08:50.092901 + cd /lava-972559/0/tests/1_kselftest-dt
1026 23:08:50.093364 ++ cat uuid
1027 23:08:50.120201 + UUID=972559_1.6.2.4.5
1028 23:08:50.120699 + set +x
1029 23:08:50.125797 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 972559_1.6.2.4.5>
1030 23:08:50.126315 + cd ./automated/linux/kselftest/
1031 23:08:50.127032 Received signal: <STARTRUN> 1_kselftest-dt 972559_1.6.2.4.5
1032 23:08:50.127506 Starting test lava.1_kselftest-dt (972559_1.6.2.4.5)
1033 23:08:50.128038 Skipping test definition patterns.
1034 23:08:50.151426 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc7/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1035 23:08:50.250754 INFO: install_deps skipped
1036 23:08:50.915952 --2024-11-10 23:08:50-- http://storage.kernelci.org/mainline/master/v6.12-rc7/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1037 23:08:50.945851 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1038 23:08:51.087871 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1039 23:08:51.227834 HTTP request sent, awaiting response... 200 OK
1040 23:08:51.228381 Length: 4107608 (3.9M) [application/octet-stream]
1041 23:08:51.233322 Saving to: 'kselftest_armhf.tar.gz'
1042 23:08:51.233843
1043 23:08:52.836312
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 180KB/s
kselftest_armhf.tar 4%[ ] 194.76K 346KB/s
kselftest_armhf.tar 19%[==> ] 771.76K 928KB/s
kselftest_armhf.tar 28%[====> ] 1.12M 989KB/s
kselftest_armhf.tar 68%[============> ] 2.67M 1.94MB/s
kselftest_armhf.tar 91%[=================> ] 3.58M 2.25MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 2.44MB/s in 1.6s
1044 23:08:52.836975
1045 23:08:53.442105 2024-11-10 23:08:52 (2.44 MB/s) - 'kselftest_armhf.tar.gz' saved [4107608/4107608]
1046 23:08:53.442552
1047 23:09:07.855638 skiplist:
1048 23:09:07.856278 ========================================
1049 23:09:07.860783 ========================================
1050 23:09:07.960278 dt:test_unprobed_devices.sh
1051 23:09:08.003716 ============== Tests to run ===============
1052 23:09:08.013017 dt:test_unprobed_devices.sh
1053 23:09:08.017031 ===========End Tests to run ===============
1054 23:09:08.024741 shardfile-dt pass
1055 23:09:08.249749 <12>[ 73.520098] kselftest: Running tests in dt
1056 23:09:08.277944 TAP version 13
1057 23:09:08.300597 1..1
1058 23:09:08.355372 # timeout set to 45
1059 23:09:08.355905 # selftests: dt: test_unprobed_devices.sh
1060 23:09:09.138453 # TAP version 13
1061 23:09:34.017290 # 1..257
1062 23:09:34.180701 # ok 1 / # SKIP
1063 23:09:34.202170 # ok 2 /clk_mcasp0
1064 23:09:34.276326 # ok 3 /clk_mcasp0_fixed # SKIP
1065 23:09:34.345266 # ok 4 /cpus/cpu@0 # SKIP
1066 23:09:34.419328 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1067 23:09:34.438237 # ok 6 /fixedregulator0
1068 23:09:34.458748 # ok 7 /leds
1069 23:09:34.483816 # ok 8 /ocp
1070 23:09:34.502797 # ok 9 /ocp/interconnect@44c00000
1071 23:09:34.529673 # ok 10 /ocp/interconnect@44c00000/segment@0
1072 23:09:34.555054 # ok 11 /ocp/interconnect@44c00000/segment@100000
1073 23:09:34.575147 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1074 23:09:34.646156 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1075 23:09:34.665498 # ok 14 /ocp/interconnect@44c00000/segment@200000
1076 23:09:34.691450 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1077 23:09:34.800389 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1078 23:09:34.873566 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1079 23:09:34.939976 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1080 23:09:35.012766 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1081 23:09:35.086206 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1082 23:09:35.156189 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1083 23:09:35.227286 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1084 23:09:35.298698 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1085 23:09:35.370298 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1086 23:09:35.442103 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1087 23:09:35.515872 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1088 23:09:35.586339 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1089 23:09:35.658506 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1090 23:09:35.729679 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1091 23:09:35.799951 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1092 23:09:35.871359 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1093 23:09:35.941631 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1094 23:09:36.019540 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1095 23:09:36.089921 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1096 23:09:36.161767 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1097 23:09:36.232911 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1098 23:09:36.304051 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1099 23:09:36.373147 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1100 23:09:36.445837 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1101 23:09:36.517127 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1102 23:09:36.588845 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1103 23:09:36.661063 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1104 23:09:36.732587 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1105 23:09:36.810738 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1106 23:09:36.878358 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1107 23:09:36.950000 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1108 23:09:37.021428 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1109 23:09:37.091757 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1110 23:09:37.165154 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1111 23:09:37.235690 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1112 23:09:37.308724 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1113 23:09:37.380374 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1114 23:09:37.451413 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1115 23:09:37.524645 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1116 23:09:37.599620 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1117 23:09:37.668239 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1118 23:09:37.738774 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1119 23:09:37.809849 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1120 23:09:37.881415 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1121 23:09:37.954039 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1122 23:09:38.030870 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1123 23:09:38.102941 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1124 23:09:38.174459 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1125 23:09:38.241580 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1126 23:09:38.313956 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1127 23:09:38.385207 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1128 23:09:38.460836 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1129 23:09:38.532498 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1130 23:09:38.604282 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1131 23:09:38.676214 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1132 23:09:38.749430 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1133 23:09:38.821671 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1134 23:09:38.899844 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1135 23:09:38.971703 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1136 23:09:39.043950 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1137 23:09:39.111326 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1138 23:09:39.183730 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1139 23:09:39.256089 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1140 23:09:39.328091 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1141 23:09:39.399237 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1142 23:09:39.470770 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1143 23:09:39.542525 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1144 23:09:39.613519 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1145 23:09:39.684950 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1146 23:09:39.759901 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1147 23:09:39.832303 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1148 23:09:39.903866 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1149 23:09:39.972776 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1150 23:09:40.048118 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1151 23:09:40.124859 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1152 23:09:40.193978 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1153 23:09:40.264274 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1154 23:09:40.340625 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1155 23:09:40.413552 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1156 23:09:40.429840 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1157 23:09:40.453848 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1158 23:09:40.477847 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1159 23:09:40.502571 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1160 23:09:40.526304 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1161 23:09:40.550068 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1162 23:09:40.578727 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1163 23:09:40.601558 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1164 23:09:40.702084 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1165 23:09:40.731268 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1166 23:09:40.753543 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1167 23:09:40.775305 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1168 23:09:40.880718 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1169 23:09:40.955838 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1170 23:09:41.027309 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1171 23:09:41.104133 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1172 23:09:41.175656 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1173 23:09:41.244314 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1174 23:09:41.322054 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1175 23:09:41.389302 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1176 23:09:41.461325 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1177 23:09:41.533770 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1178 23:09:41.605726 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1179 23:09:41.677368 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1180 23:09:41.748223 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1181 23:09:41.825384 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1182 23:09:41.896505 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1183 23:09:41.973756 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1184 23:09:41.994210 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1185 23:09:42.062125 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1186 23:09:42.136928 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1187 23:09:42.209238 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1188 23:09:42.231025 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1189 23:09:42.302252 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1190 23:09:42.325536 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1191 23:09:42.393952 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1192 23:09:42.416922 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1193 23:09:42.440946 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1194 23:09:42.468301 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1195 23:09:42.492048 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1196 23:09:42.510792 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1197 23:09:42.535237 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1198 23:09:42.560852 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1199 23:09:42.635383 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1200 23:09:42.656756 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1201 23:09:42.679795 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1202 23:09:42.753472 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1203 23:09:42.823734 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1204 23:09:42.843751 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1205 23:09:42.944181 # not ok 144 /ocp/interconnect@47c00000
1206 23:09:43.015527 # not ok 145 /ocp/interconnect@47c00000/segment@0
1207 23:09:43.038773 # ok 146 /ocp/interconnect@48000000
1208 23:09:43.059893 # ok 147 /ocp/interconnect@48000000/segment@0
1209 23:09:43.086199 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1210 23:09:43.111377 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1211 23:09:43.136952 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1212 23:09:43.160388 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1213 23:09:43.181207 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1214 23:09:43.207883 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1215 23:09:43.230276 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1216 23:09:43.300897 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1217 23:09:43.368516 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1218 23:09:43.391013 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1219 23:09:43.414230 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1220 23:09:43.440691 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1221 23:09:43.461716 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1222 23:09:43.483425 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1223 23:09:43.511780 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1224 23:09:43.530948 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1225 23:09:43.558678 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1226 23:09:43.581076 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1227 23:09:43.607429 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1228 23:09:43.623868 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1229 23:09:43.653556 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1230 23:09:43.671936 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1231 23:09:43.696532 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1232 23:09:43.719035 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1233 23:09:43.744085 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1234 23:09:43.766185 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1235 23:09:43.790560 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1236 23:09:43.815708 # ok 175 /ocp/interconnect@48000000/segment@100000
1237 23:09:43.840665 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1238 23:09:43.862172 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1239 23:09:43.934081 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1240 23:09:44.010859 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1241 23:09:44.076650 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1242 23:09:44.148229 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1243 23:09:44.218102 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1244 23:09:44.291727 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1245 23:09:44.360942 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1246 23:09:44.434979 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1247 23:09:44.458783 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1248 23:09:44.481540 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1249 23:09:44.504114 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1250 23:09:44.523436 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1251 23:09:44.550646 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1252 23:09:44.573666 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1253 23:09:44.596814 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1254 23:09:44.621022 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1255 23:09:44.643068 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1256 23:09:44.666880 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1257 23:09:44.690046 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1258 23:09:44.714672 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1259 23:09:44.734993 # ok 198 /ocp/interconnect@48000000/segment@200000
1260 23:09:44.760464 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1261 23:09:44.834581 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1262 23:09:44.852508 # ok 201 /ocp/interconnect@48000000/segment@300000
1263 23:09:44.877024 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1264 23:09:44.900728 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1265 23:09:44.929555 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1266 23:09:44.951300 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1267 23:09:44.973211 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1268 23:09:44.994924 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1269 23:09:45.067200 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1270 23:09:45.085357 # ok 209 /ocp/interconnect@4a000000
1271 23:09:45.109211 # ok 210 /ocp/interconnect@4a000000/segment@0
1272 23:09:45.138493 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1273 23:09:45.161840 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1274 23:09:45.183961 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1275 23:09:45.206469 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1276 23:09:45.282011 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1277 23:09:45.389064 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1278 23:09:45.461038 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1279 23:09:45.562571 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1280 23:09:45.629300 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1281 23:09:45.700161 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1282 23:09:45.799293 # not ok 221 /ocp/interconnect@4b140000
1283 23:09:45.871494 # not ok 222 /ocp/interconnect@4b140000/segment@0
1284 23:09:45.947729 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1285 23:09:45.963693 # ok 224 /ocp/target-module@40300000
1286 23:09:45.988832 # ok 225 /ocp/target-module@40300000/sram@0
1287 23:09:46.065612 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1288 23:09:46.132985 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1289 23:09:46.152627 # ok 228 /ocp/target-module@47400000
1290 23:09:46.180037 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1291 23:09:46.204428 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1292 23:09:46.221905 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1293 23:09:46.244718 # ok 232 /ocp/target-module@47400000/usb@1400
1294 23:09:46.265651 # ok 233 /ocp/target-module@47400000/usb@1800
1295 23:09:46.292977 # ok 234 /ocp/target-module@47810000
1296 23:09:46.315091 # ok 235 /ocp/target-module@49000000
1297 23:09:46.337779 # ok 236 /ocp/target-module@49000000/dma@0
1298 23:09:46.355167 # ok 237 /ocp/target-module@49800000
1299 23:09:46.378942 # ok 238 /ocp/target-module@49800000/dma@0
1300 23:09:46.404286 # ok 239 /ocp/target-module@49900000
1301 23:09:46.422555 # ok 240 /ocp/target-module@49900000/dma@0
1302 23:09:46.448333 # ok 241 /ocp/target-module@49a00000
1303 23:09:46.468036 # ok 242 /ocp/target-module@49a00000/dma@0
1304 23:09:46.494279 # ok 243 /ocp/target-module@4c000000
1305 23:09:46.565910 # not ok 244 /ocp/target-module@4c000000/emif@0
1306 23:09:46.587729 # ok 245 /ocp/target-module@50000000
1307 23:09:46.605651 # ok 246 /ocp/target-module@53100000
1308 23:09:46.679377 # not ok 247 /ocp/target-module@53100000/sham@0
1309 23:09:46.698889 # ok 248 /ocp/target-module@53500000
1310 23:09:46.769854 # not ok 249 /ocp/target-module@53500000/aes@0
1311 23:09:46.791347 # ok 250 /ocp/target-module@56000000
1312 23:09:46.899593 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1313 23:09:46.964662 # ok 252 /opp-table # SKIP
1314 23:09:47.034665 # ok 253 /soc # SKIP
1315 23:09:47.056137 # ok 254 /sound
1316 23:09:47.084118 # ok 255 /target-module@4b000000
1317 23:09:47.103148 # ok 256 /target-module@4b000000/target-module@140000
1318 23:09:47.124771 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1319 23:09:47.133068 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1320 23:09:47.140013 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1321 23:09:49.300176 dt_test_unprobed_devices_sh_ skip
1322 23:09:49.305562 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1323 23:09:49.311087 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1324 23:09:49.311654 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1325 23:09:49.316670 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1326 23:09:49.322339 dt_test_unprobed_devices_sh_fixedregulator0 pass
1327 23:09:49.327927 dt_test_unprobed_devices_sh_leds pass
1328 23:09:49.328406 dt_test_unprobed_devices_sh_ocp pass
1329 23:09:49.333443 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1330 23:09:49.339117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1331 23:09:49.344676 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1332 23:09:49.355929 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1333 23:09:49.361536 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1334 23:09:49.367260 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1335 23:09:49.378413 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1336 23:09:49.384070 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1337 23:09:49.395298 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1338 23:09:49.406514 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1339 23:09:49.417715 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1340 23:09:49.423331 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1341 23:09:49.434545 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1342 23:09:49.445769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1343 23:09:49.457003 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1344 23:09:49.468183 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1345 23:09:49.473771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1346 23:09:49.486173 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1347 23:09:49.496235 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1348 23:09:49.507422 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1349 23:09:49.519373 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1350 23:09:49.524181 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1351 23:09:49.535295 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1352 23:09:49.546511 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1353 23:09:49.557738 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1354 23:09:49.563462 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1355 23:09:49.574649 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1356 23:09:49.585770 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1357 23:09:49.597006 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1358 23:09:49.608188 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1359 23:09:49.613778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1360 23:09:49.624987 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1361 23:09:49.636210 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1362 23:09:49.647348 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1363 23:09:49.658526 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1364 23:09:49.669724 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1365 23:09:49.680911 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1366 23:09:49.692096 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1367 23:09:49.703277 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1368 23:09:49.714475 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1369 23:09:49.725675 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1370 23:09:49.736810 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1371 23:09:49.748120 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1372 23:09:49.759257 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1373 23:09:49.770456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1374 23:09:49.781639 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1375 23:09:49.792817 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1376 23:09:49.804041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1377 23:09:49.815243 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1378 23:09:49.826469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1379 23:09:49.837596 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1380 23:09:49.848765 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1381 23:09:49.859973 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1382 23:09:49.871266 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1383 23:09:49.882407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1384 23:09:49.893557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1385 23:09:49.899305 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1386 23:09:49.910376 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1387 23:09:49.921517 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1388 23:09:49.932731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1389 23:09:49.943930 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1390 23:09:49.955141 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1391 23:09:49.966327 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1392 23:09:49.977477 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1393 23:09:49.988669 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1394 23:09:49.999866 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1395 23:09:50.011155 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1396 23:09:50.022260 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1397 23:09:50.033470 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1398 23:09:50.044625 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1399 23:09:50.055813 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1400 23:09:50.067012 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1401 23:09:50.078229 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1402 23:09:50.089401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1403 23:09:50.095060 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1404 23:09:50.106237 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1405 23:09:50.117390 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1406 23:09:50.128572 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1407 23:09:50.139733 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1408 23:09:50.145414 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1409 23:09:50.162313 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1410 23:09:50.173323 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1411 23:09:50.178980 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1412 23:09:50.195708 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1413 23:09:50.206902 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1414 23:09:50.218143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1415 23:09:50.223749 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1416 23:09:50.234903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1417 23:09:50.246152 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1418 23:09:50.251713 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1419 23:09:50.262897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1420 23:09:50.274110 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1421 23:09:50.279733 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1422 23:09:50.290859 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1423 23:09:50.296508 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1424 23:09:50.307665 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1425 23:09:50.318822 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1426 23:09:50.330042 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1427 23:09:50.341286 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1428 23:09:50.352453 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1429 23:09:50.363606 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1430 23:09:50.374823 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1431 23:09:50.385892 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1432 23:09:50.397219 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1433 23:09:50.408287 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1434 23:09:50.419472 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1435 23:09:50.430679 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1436 23:09:50.447464 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1437 23:09:50.458632 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1438 23:09:50.469861 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1439 23:09:50.481280 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1440 23:09:50.492398 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1441 23:09:50.509174 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1442 23:09:50.520391 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1443 23:09:50.531554 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1444 23:09:50.542697 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1445 23:09:50.548343 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1446 23:09:50.559521 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1447 23:09:50.570823 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1448 23:09:50.576407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1449 23:09:50.587457 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1450 23:09:50.593028 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1451 23:09:50.604326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1452 23:09:50.609867 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1453 23:09:50.621038 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1454 23:09:50.626632 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1455 23:09:50.637804 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1456 23:09:50.643400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1457 23:09:50.654585 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1458 23:09:50.665763 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1459 23:09:50.676980 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1460 23:09:50.688191 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1461 23:09:50.699380 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1462 23:09:50.704980 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1463 23:09:50.716176 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1464 23:09:50.721727 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1465 23:09:50.727370 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1466 23:09:50.732977 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1467 23:09:50.738543 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1468 23:09:50.744205 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1469 23:09:50.755331 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1470 23:09:50.760958 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1471 23:09:50.766522 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1472 23:09:50.777714 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1473 23:09:50.783337 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1474 23:09:50.794479 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1475 23:09:50.800117 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1476 23:09:50.811360 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1477 23:09:50.816859 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1478 23:09:50.828076 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1479 23:09:50.833685 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1480 23:09:50.844857 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1481 23:09:50.850480 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1482 23:09:50.861642 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1483 23:09:50.867347 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1484 23:09:50.878435 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1485 23:09:50.884009 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1486 23:09:50.889647 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1487 23:09:50.900879 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1488 23:09:50.906418 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1489 23:09:50.917611 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1490 23:09:50.923206 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1491 23:09:50.934414 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1492 23:09:50.939981 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1493 23:09:50.951244 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1494 23:09:50.956787 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1495 23:09:50.962416 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1496 23:09:50.973560 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1497 23:09:50.979208 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1498 23:09:50.990339 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1499 23:09:51.001493 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1500 23:09:51.012749 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1501 23:09:51.023953 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1502 23:09:51.035138 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1503 23:09:51.046365 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1504 23:09:51.057499 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1505 23:09:51.068734 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1506 23:09:51.074395 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1507 23:09:51.085524 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1508 23:09:51.091093 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1509 23:09:51.102389 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1510 23:09:51.107874 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1511 23:09:51.119078 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1512 23:09:51.124663 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1513 23:09:51.135847 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1514 23:09:51.141439 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1515 23:09:51.152633 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1516 23:09:51.158253 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1517 23:09:51.169439 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1518 23:09:51.175052 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1519 23:09:51.186261 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1520 23:09:51.191790 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1521 23:09:51.197406 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1522 23:09:51.208585 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1523 23:09:51.214176 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1524 23:09:51.225411 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1525 23:09:51.231013 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1526 23:09:51.242182 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1527 23:09:51.247766 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1528 23:09:51.258967 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1529 23:09:51.264608 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1530 23:09:51.270218 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1531 23:09:51.275779 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1532 23:09:51.286940 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1533 23:09:51.298141 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1534 23:09:51.303706 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1535 23:09:51.309408 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1536 23:09:51.320544 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1537 23:09:51.331702 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1538 23:09:51.342889 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1539 23:09:51.354161 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1540 23:09:51.359725 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1541 23:09:51.365455 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1542 23:09:51.370981 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1543 23:09:51.376681 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1544 23:09:51.382160 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1545 23:09:51.387755 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1546 23:09:51.398982 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1547 23:09:51.404459 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1548 23:09:51.411637 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1549 23:09:51.415812 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1550 23:09:51.421467 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1551 23:09:51.432554 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1552 23:09:51.438184 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1553 23:09:51.443805 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1554 23:09:51.449494 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1555 23:09:51.454994 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1556 23:09:51.460605 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1557 23:09:51.466181 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1558 23:09:51.471800 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1559 23:09:51.477512 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1560 23:09:51.483047 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1561 23:09:51.488639 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1562 23:09:51.494203 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1563 23:09:51.499890 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1564 23:09:51.505575 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1565 23:09:51.511057 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1566 23:09:51.516660 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1567 23:09:51.522239 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1568 23:09:51.527861 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1569 23:09:51.533509 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1570 23:09:51.539032 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1571 23:09:51.544625 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1572 23:09:51.545167 dt_test_unprobed_devices_sh_opp-table skip
1573 23:09:51.550231 dt_test_unprobed_devices_sh_soc skip
1574 23:09:51.555822 dt_test_unprobed_devices_sh_sound pass
1575 23:09:51.561466 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1576 23:09:51.567012 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1577 23:09:51.572638 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1578 23:09:51.578229 dt_test_unprobed_devices_sh fail
1579 23:09:51.578803 + ../../utils/send-to-lava.sh ./output/result.txt
1580 23:09:51.583857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1581 23:09:51.584831 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1583 23:09:51.592963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1584 23:09:51.593784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1586 23:09:51.680580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1587 23:09:51.681446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1589 23:09:51.772576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1590 23:09:51.773404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1592 23:09:51.863571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1593 23:09:51.864382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1595 23:09:51.955032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1596 23:09:51.955901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1598 23:09:52.047696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1599 23:09:52.048606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1601 23:09:52.136977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1602 23:09:52.137876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1604 23:09:52.228252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1605 23:09:52.229044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1607 23:09:52.326866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1608 23:09:52.327706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1610 23:09:52.450070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1611 23:09:52.451080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1613 23:09:52.582768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1614 23:09:52.583677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1616 23:09:52.684409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1617 23:09:52.685259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1619 23:09:52.778521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1620 23:09:52.779368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1622 23:09:52.869018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1623 23:09:52.869886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1625 23:09:52.963859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1626 23:09:52.964700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1628 23:09:53.059299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1629 23:09:53.060190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1631 23:09:53.159669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1632 23:09:53.160539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1634 23:09:53.253552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1635 23:09:53.254436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1637 23:09:53.346817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1638 23:09:53.347681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1640 23:09:53.440264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1641 23:09:53.442538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1643 23:09:53.533397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1644 23:09:53.534337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1646 23:09:53.625396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1647 23:09:53.626282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1649 23:09:53.719370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1650 23:09:53.720257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1652 23:09:53.810122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1653 23:09:53.810994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1655 23:09:53.900079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1656 23:09:53.900916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1658 23:09:53.990671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1659 23:09:53.991552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1661 23:09:54.082293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1662 23:09:54.083191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1664 23:09:54.172009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1665 23:09:54.172888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1667 23:09:54.258312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1668 23:09:54.259163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1670 23:09:54.349495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1671 23:09:54.350446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1673 23:09:54.442828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1674 23:09:54.443445 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1676 23:09:54.535049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1677 23:09:54.535940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1679 23:09:54.629639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1680 23:09:54.630588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1682 23:09:54.721084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1683 23:09:54.721965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1685 23:09:54.814557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1686 23:09:54.815411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1688 23:09:54.908521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1689 23:09:54.909391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1691 23:09:55.011339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1692 23:09:55.012199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1694 23:09:55.111200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1695 23:09:55.112067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1697 23:09:55.212113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1698 23:09:55.213014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1700 23:09:55.313446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1701 23:09:55.314351 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1703 23:09:55.405387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1704 23:09:55.406295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1706 23:09:55.499517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1707 23:09:55.500413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1709 23:09:55.601519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1710 23:09:55.602430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1712 23:09:55.693564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1713 23:09:55.694533 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1715 23:09:55.787351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1716 23:09:55.788269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1718 23:09:55.881866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1719 23:09:55.882748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1721 23:09:55.974973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1722 23:09:55.975823 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1724 23:09:56.067675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1725 23:09:56.068599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1727 23:09:56.161219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1728 23:09:56.162113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1730 23:09:56.271894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1731 23:09:56.272815 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1733 23:09:56.378118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1734 23:09:56.379113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1736 23:09:56.469904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1737 23:09:56.470852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1739 23:09:56.561464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1740 23:09:56.562430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1742 23:09:56.653575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1743 23:09:56.654548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1745 23:09:56.744268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1746 23:09:56.745214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1748 23:09:56.837506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1749 23:09:56.838463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1751 23:09:56.931448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1752 23:09:56.932382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1754 23:09:57.024170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1755 23:09:57.025099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1757 23:09:57.126234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1758 23:09:57.127121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1760 23:09:57.217437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1761 23:09:57.218417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1763 23:09:57.310682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1764 23:09:57.311584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1766 23:09:57.401199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1767 23:09:57.402153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1769 23:09:57.494302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1770 23:09:57.495237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1772 23:09:57.584209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1773 23:09:57.585055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1775 23:09:57.685532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1776 23:09:57.687379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1778 23:09:57.786934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1779 23:09:57.787552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1781 23:09:57.879260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1782 23:09:57.880106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1784 23:09:57.970017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1785 23:09:57.970959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1787 23:09:58.061078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1788 23:09:58.062061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1790 23:09:58.152238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1791 23:09:58.153145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1793 23:09:58.244068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1794 23:09:58.244931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1796 23:09:58.335312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1797 23:09:58.336216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1799 23:09:58.427988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1800 23:09:58.428841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1802 23:09:58.521784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1803 23:09:58.522711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1805 23:09:58.612616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1806 23:09:58.613481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1808 23:09:58.704478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1809 23:09:58.705338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1811 23:09:58.796773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1812 23:09:58.797653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1814 23:09:58.889105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1815 23:09:58.889976 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1817 23:09:58.981874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1818 23:09:58.982757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1820 23:09:59.074677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1821 23:09:59.075557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1823 23:09:59.167415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1824 23:09:59.168265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1826 23:09:59.260242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1827 23:09:59.261103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1829 23:09:59.349778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1830 23:09:59.350679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1832 23:09:59.440104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1833 23:09:59.440724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1835 23:09:59.532592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1836 23:09:59.533479 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1838 23:09:59.623209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1839 23:09:59.624021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1841 23:09:59.715389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1842 23:09:59.716251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1844 23:09:59.808332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1845 23:09:59.809152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1847 23:09:59.911416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1848 23:09:59.912241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1850 23:10:00.012723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1851 23:10:00.013547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1853 23:10:00.102279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1854 23:10:00.103122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1856 23:10:00.193355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1857 23:10:00.194215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1859 23:10:00.284185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1860 23:10:00.284995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1862 23:10:00.386197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1863 23:10:00.387109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1865 23:10:00.485308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1866 23:10:00.486226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1868 23:10:00.579754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1869 23:10:00.581941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1871 23:10:00.679890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1872 23:10:00.680902 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1874 23:10:00.780821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1875 23:10:00.781982 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1877 23:10:00.882633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1878 23:10:00.883506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1880 23:10:00.974928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1881 23:10:00.975777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1883 23:10:01.068401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1884 23:10:01.069290 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1886 23:10:01.160372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1887 23:10:01.161315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1889 23:10:01.254195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1890 23:10:01.255112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1892 23:10:01.349218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1893 23:10:01.350192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1895 23:10:01.443337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1896 23:10:01.444249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1898 23:10:01.534927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1899 23:10:01.535837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1901 23:10:01.627823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1902 23:10:01.628668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1904 23:10:01.723348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1905 23:10:01.724196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1907 23:10:01.817385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1908 23:10:01.818262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1910 23:10:01.911817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1911 23:10:01.912650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1913 23:10:02.006118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1914 23:10:02.006954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1916 23:10:02.107301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1917 23:10:02.108154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1919 23:10:02.199945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1920 23:10:02.200810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1922 23:10:02.301469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1923 23:10:02.302441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1925 23:10:02.403276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1926 23:10:02.404151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1928 23:10:02.504319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1929 23:10:02.505217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1931 23:10:02.597435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1932 23:10:02.598350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1934 23:10:02.688570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1935 23:10:02.689407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1937 23:10:02.778829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1938 23:10:02.779645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1940 23:10:02.879338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1942 23:10:02.882478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1943 23:10:02.980621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1945 23:10:02.983826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1946 23:10:03.072837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1948 23:10:03.076021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1949 23:10:03.166266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1950 23:10:03.167093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1952 23:10:03.260345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1953 23:10:03.261260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1955 23:10:03.350372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1956 23:10:03.351235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1958 23:10:03.443089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1959 23:10:03.444001 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1961 23:10:03.534868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1962 23:10:03.535734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1964 23:10:03.630373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1965 23:10:03.631202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1967 23:10:03.720460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1968 23:10:03.721249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1970 23:10:03.813376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1971 23:10:03.814217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1973 23:10:03.914303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1974 23:10:03.915106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1976 23:10:04.015823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1977 23:10:04.016627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1979 23:10:04.116476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1980 23:10:04.117303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1982 23:10:04.221474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1983 23:10:04.222320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1985 23:10:04.312434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1986 23:10:04.313305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1988 23:10:04.405441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1989 23:10:04.406390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1991 23:10:04.508419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1992 23:10:04.509314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1994 23:10:04.610877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
1995 23:10:04.611515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
1997 23:10:04.710173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1998 23:10:04.711072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2000 23:10:04.810703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2001 23:10:04.811586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2003 23:10:04.903856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2004 23:10:04.904788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2006 23:10:04.995855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2007 23:10:04.996793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2009 23:10:05.087554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2010 23:10:05.088446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2012 23:10:05.176540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2013 23:10:05.177350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2015 23:10:05.269862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2016 23:10:05.270720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2018 23:10:05.359784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2019 23:10:05.360708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2021 23:10:05.455058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2022 23:10:05.455938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2024 23:10:05.549316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2025 23:10:05.550270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2027 23:10:05.640579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2028 23:10:05.641514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2030 23:10:05.732626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2031 23:10:05.733542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2033 23:10:05.825753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2034 23:10:05.826677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2036 23:10:05.917877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2037 23:10:05.918760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2039 23:10:06.009118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2040 23:10:06.010158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2042 23:10:06.102258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2043 23:10:06.103161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2045 23:10:06.196794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2046 23:10:06.197708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2048 23:10:06.290123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2049 23:10:06.291021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2051 23:10:06.383190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2052 23:10:06.384049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2054 23:10:06.476177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2055 23:10:06.476849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2057 23:10:06.568439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2058 23:10:06.569102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2060 23:10:06.661188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2061 23:10:06.661825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2063 23:10:06.753047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2064 23:10:06.753689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2066 23:10:06.846579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2067 23:10:06.847217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2069 23:10:06.938469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2070 23:10:06.939406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2072 23:10:07.032323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2073 23:10:07.032938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2075 23:10:07.124879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2076 23:10:07.125641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2078 23:10:07.217714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2079 23:10:07.218531 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2081 23:10:07.308794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2082 23:10:07.309531 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2084 23:10:07.400586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2085 23:10:07.401363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2087 23:10:07.486891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2088 23:10:07.487694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2090 23:10:07.580516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2091 23:10:07.581289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2093 23:10:07.670316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2094 23:10:07.671129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2096 23:10:07.762620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2097 23:10:07.763412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2099 23:10:07.853412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2100 23:10:07.854222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2102 23:10:07.946522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2103 23:10:07.947277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2105 23:10:08.036187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2106 23:10:08.036968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2108 23:10:08.130856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2109 23:10:08.131625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2111 23:10:08.223731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2112 23:10:08.224514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2114 23:10:08.326816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2115 23:10:08.327591 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2117 23:10:08.422354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2118 23:10:08.423000 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2120 23:10:08.513289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2121 23:10:08.513961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2123 23:10:08.607362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2124 23:10:08.607990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2126 23:10:08.699161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2127 23:10:08.699765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2129 23:10:08.792069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2130 23:10:08.792682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2132 23:10:08.883086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2133 23:10:08.883692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2135 23:10:08.977122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2136 23:10:08.977755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2138 23:10:09.067020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2139 23:10:09.068106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2141 23:10:09.158716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2142 23:10:09.159614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2144 23:10:09.250101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2145 23:10:09.250990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2147 23:10:09.341338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2148 23:10:09.342238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2150 23:10:09.433850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2151 23:10:09.434735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2153 23:10:09.525941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2154 23:10:09.526861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2156 23:10:09.615771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2157 23:10:09.616620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2159 23:10:09.705559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2160 23:10:09.706480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2162 23:10:09.795315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2163 23:10:09.796160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2165 23:10:09.886175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2166 23:10:09.887027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2168 23:10:09.977630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2169 23:10:09.978513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2171 23:10:10.068466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2172 23:10:10.069347 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2174 23:10:10.157846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2175 23:10:10.158698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2177 23:10:10.303279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2178 23:10:10.303902 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2180 23:10:10.404539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2181 23:10:10.405423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2183 23:10:10.492279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2184 23:10:10.493189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2186 23:10:10.584480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2187 23:10:10.585393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2189 23:10:10.676671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2190 23:10:10.677552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2192 23:10:10.769452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2193 23:10:10.770473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2195 23:10:10.858773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2196 23:10:10.859650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2198 23:10:10.949655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2199 23:10:10.950590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2201 23:10:11.039157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2202 23:10:11.040072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2204 23:10:11.132800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2205 23:10:11.133725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2207 23:10:11.218958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2208 23:10:11.219811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2210 23:10:11.309867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2211 23:10:11.310724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2213 23:10:11.403012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2214 23:10:11.403918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2216 23:10:11.494551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2217 23:10:11.495467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2219 23:10:11.588709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2220 23:10:11.589616 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2222 23:10:11.678100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2223 23:10:11.679080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2225 23:10:11.769932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2226 23:10:11.770818 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2228 23:10:11.860276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2229 23:10:11.861146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2231 23:10:11.947067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2232 23:10:11.947933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2234 23:10:12.037321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2235 23:10:12.038456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2237 23:10:12.130249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2238 23:10:12.131128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2240 23:10:12.219597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2241 23:10:12.220459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2243 23:10:12.306554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2244 23:10:12.307415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2246 23:10:12.397561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2247 23:10:12.398615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2249 23:10:12.488854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2250 23:10:12.489775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2252 23:10:12.578753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2253 23:10:12.579672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2255 23:10:12.670102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2256 23:10:12.671150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2258 23:10:12.764902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2259 23:10:12.765776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2261 23:10:12.853577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2263 23:10:12.856595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2264 23:10:12.945780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2265 23:10:12.946678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2267 23:10:13.040112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2268 23:10:13.042159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2270 23:10:13.144544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2271 23:10:13.145513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2273 23:10:13.236872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2274 23:10:13.237740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2276 23:10:13.327930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2277 23:10:13.328800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2279 23:10:13.420196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2280 23:10:13.421118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2282 23:10:13.513544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2283 23:10:13.514522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2285 23:10:13.605163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2286 23:10:13.606065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2288 23:10:13.697351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2289 23:10:13.698264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2291 23:10:13.787939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2292 23:10:13.788774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2294 23:10:13.880509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2295 23:10:13.881349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2297 23:10:13.971725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2298 23:10:13.972562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2300 23:10:14.063755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2301 23:10:14.064638 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2303 23:10:14.156053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2304 23:10:14.156887 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2306 23:10:14.248613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2307 23:10:14.249444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2309 23:10:14.339761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2310 23:10:14.340605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2312 23:10:14.433117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2313 23:10:14.434024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2315 23:10:14.523985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2316 23:10:14.524895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2318 23:10:14.615755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2319 23:10:14.616571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2321 23:10:14.706822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2322 23:10:14.707660 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2324 23:10:14.799457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2325 23:10:14.800260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2327 23:10:14.892966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2328 23:10:14.893766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2330 23:10:14.983937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2331 23:10:14.984828 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2333 23:10:15.078804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2334 23:10:15.079678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2336 23:10:15.166186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2337 23:10:15.167025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2339 23:10:15.255558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2340 23:10:15.256429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2342 23:10:15.348051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2343 23:10:15.349024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2345 23:10:15.441173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2346 23:10:15.442068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2348 23:10:15.536127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2349 23:10:15.537013 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2351 23:10:15.637864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2352 23:10:15.638677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2354 23:10:15.724953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2355 23:10:15.725737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2357 23:10:15.730841 + set +x
2358 23:10:15.731337 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 972559_1.6.2.4.5>
2359 23:10:15.732028 Received signal: <ENDRUN> 1_kselftest-dt 972559_1.6.2.4.5
2360 23:10:15.732517 Ending use of test pattern.
2361 23:10:15.732961 Ending test lava.1_kselftest-dt (972559_1.6.2.4.5), duration 85.61
2363 23:10:15.735348 <LAVA_TEST_RUNNER EXIT>
2364 23:10:15.736067 ok: lava_test_shell seems to have completed
2365 23:10:15.750182 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2366 23:10:15.752236 end: 3.1 lava-test-shell (duration 00:01:27) [common]
2367 23:10:15.752835 end: 3 lava-test-retry (duration 00:01:27) [common]
2368 23:10:15.753430 start: 4 finalize (timeout 00:05:25) [common]
2369 23:10:15.754066 start: 4.1 power-off (timeout 00:00:30) [common]
2370 23:10:15.755116 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2371 23:10:15.790324 >> OK - accepted request
2372 23:10:15.792245 Returned 0 in 0 seconds
2373 23:10:15.893442 end: 4.1 power-off (duration 00:00:00) [common]
2375 23:10:15.895229 start: 4.2 read-feedback (timeout 00:05:25) [common]
2376 23:10:15.896435 Listened to connection for namespace 'common' for up to 1s
2377 23:10:15.897337 Listened to connection for namespace 'common' for up to 1s
2378 23:10:16.897117 Finalising connection for namespace 'common'
2379 23:10:16.897617 Disconnecting from shell: Finalise
2380 23:10:16.897957 / #
2381 23:10:16.998592 end: 4.2 read-feedback (duration 00:00:01) [common]
2382 23:10:16.998999 end: 4 finalize (duration 00:00:01) [common]
2383 23:10:16.999337 Cleaning after the job
2384 23:10:16.999677 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972559/tftp-deploy-deppz1es/ramdisk
2385 23:10:17.004156 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972559/tftp-deploy-deppz1es/kernel
2386 23:10:17.007768 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972559/tftp-deploy-deppz1es/dtb
2387 23:10:17.008574 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972559/tftp-deploy-deppz1es/nfsrootfs
2388 23:10:17.135136 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972559/tftp-deploy-deppz1es/modules
2389 23:10:17.143812 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/972559
2390 23:10:20.041708 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/972559
2391 23:10:20.043225 Job finished correctly