Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 00:55:24.404192 lava-dispatcher, installed at version: 2024.01
2 00:55:24.404990 start: 0 validate
3 00:55:24.405456 Start time: 2024-11-11 00:55:24.405427+00:00 (UTC)
4 00:55:24.406003 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:55:24.406547 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:55:24.453957 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:55:24.454529 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 00:55:24.488164 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:55:24.488833 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 00:55:24.523467 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:55:24.523966 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
12 00:55:24.565844 validate duration: 0.16
14 00:55:24.566778 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:55:24.567150 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:55:24.567499 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:55:24.568144 Not decompressing ramdisk as can be used compressed.
18 00:55:24.568627 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 00:55:24.568942 saving as /var/lib/lava/dispatcher/tmp/972757/tftp-deploy-duj6sh0x/ramdisk/rootfs.cpio.gz
20 00:55:24.569253 total size: 47897469 (45 MB)
21 00:55:24.608331 progress 0 % (0 MB)
22 00:55:24.638704 progress 5 % (2 MB)
23 00:55:24.668504 progress 10 % (4 MB)
24 00:55:24.697955 progress 15 % (6 MB)
25 00:55:24.727505 progress 20 % (9 MB)
26 00:55:24.757010 progress 25 % (11 MB)
27 00:55:24.786380 progress 30 % (13 MB)
28 00:55:24.816259 progress 35 % (16 MB)
29 00:55:24.845776 progress 40 % (18 MB)
30 00:55:24.875268 progress 45 % (20 MB)
31 00:55:24.904947 progress 50 % (22 MB)
32 00:55:24.934730 progress 55 % (25 MB)
33 00:55:24.964697 progress 60 % (27 MB)
34 00:55:24.994289 progress 65 % (29 MB)
35 00:55:25.024330 progress 70 % (32 MB)
36 00:55:25.053811 progress 75 % (34 MB)
37 00:55:25.083109 progress 80 % (36 MB)
38 00:55:25.112733 progress 85 % (38 MB)
39 00:55:25.142496 progress 90 % (41 MB)
40 00:55:25.172231 progress 95 % (43 MB)
41 00:55:25.201034 progress 100 % (45 MB)
42 00:55:25.201779 45 MB downloaded in 0.63 s (72.22 MB/s)
43 00:55:25.202325 end: 1.1.1 http-download (duration 00:00:01) [common]
45 00:55:25.203199 end: 1.1 download-retry (duration 00:00:01) [common]
46 00:55:25.203487 start: 1.2 download-retry (timeout 00:09:59) [common]
47 00:55:25.203753 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 00:55:25.204262 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm64/defconfig/clang-16/kernel/Image
49 00:55:25.204517 saving as /var/lib/lava/dispatcher/tmp/972757/tftp-deploy-duj6sh0x/kernel/Image
50 00:55:25.204727 total size: 37812736 (36 MB)
51 00:55:25.204936 No compression specified
52 00:55:25.244650 progress 0 % (0 MB)
53 00:55:25.268360 progress 5 % (1 MB)
54 00:55:25.291482 progress 10 % (3 MB)
55 00:55:25.314760 progress 15 % (5 MB)
56 00:55:25.337499 progress 20 % (7 MB)
57 00:55:25.360522 progress 25 % (9 MB)
58 00:55:25.384165 progress 30 % (10 MB)
59 00:55:25.406953 progress 35 % (12 MB)
60 00:55:25.430918 progress 40 % (14 MB)
61 00:55:25.454084 progress 45 % (16 MB)
62 00:55:25.477653 progress 50 % (18 MB)
63 00:55:25.502831 progress 55 % (19 MB)
64 00:55:25.528287 progress 60 % (21 MB)
65 00:55:25.552191 progress 65 % (23 MB)
66 00:55:25.574761 progress 70 % (25 MB)
67 00:55:25.598160 progress 75 % (27 MB)
68 00:55:25.621357 progress 80 % (28 MB)
69 00:55:25.643753 progress 85 % (30 MB)
70 00:55:25.667190 progress 90 % (32 MB)
71 00:55:25.690035 progress 95 % (34 MB)
72 00:55:25.712321 progress 100 % (36 MB)
73 00:55:25.713070 36 MB downloaded in 0.51 s (70.94 MB/s)
74 00:55:25.713548 end: 1.2.1 http-download (duration 00:00:01) [common]
76 00:55:25.714351 end: 1.2 download-retry (duration 00:00:01) [common]
77 00:55:25.714620 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:55:25.714880 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:55:25.715339 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm64/defconfig/clang-16/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 00:55:25.715602 saving as /var/lib/lava/dispatcher/tmp/972757/tftp-deploy-duj6sh0x/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 00:55:25.715808 total size: 53209 (0 MB)
82 00:55:25.716037 No compression specified
83 00:55:25.754590 progress 61 % (0 MB)
84 00:55:25.755425 progress 100 % (0 MB)
85 00:55:25.755938 0 MB downloaded in 0.04 s (1.26 MB/s)
86 00:55:25.756427 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:55:25.757227 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:55:25.757482 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:55:25.757742 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:55:25.758187 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm64/defconfig/clang-16/modules.tar.xz
92 00:55:25.758422 saving as /var/lib/lava/dispatcher/tmp/972757/tftp-deploy-duj6sh0x/modules/modules.tar
93 00:55:25.758624 total size: 11772052 (11 MB)
94 00:55:25.758833 Using unxz to decompress xz
95 00:55:25.797489 progress 0 % (0 MB)
96 00:55:25.864290 progress 5 % (0 MB)
97 00:55:25.940925 progress 10 % (1 MB)
98 00:55:26.037975 progress 15 % (1 MB)
99 00:55:26.135209 progress 20 % (2 MB)
100 00:55:26.215087 progress 25 % (2 MB)
101 00:55:26.293138 progress 30 % (3 MB)
102 00:55:26.374278 progress 35 % (3 MB)
103 00:55:26.455849 progress 40 % (4 MB)
104 00:55:26.533470 progress 45 % (5 MB)
105 00:55:26.619464 progress 50 % (5 MB)
106 00:55:26.701862 progress 55 % (6 MB)
107 00:55:26.787742 progress 60 % (6 MB)
108 00:55:26.869872 progress 65 % (7 MB)
109 00:55:26.952594 progress 70 % (7 MB)
110 00:55:27.037167 progress 75 % (8 MB)
111 00:55:27.121755 progress 80 % (9 MB)
112 00:55:27.203050 progress 85 % (9 MB)
113 00:55:27.288270 progress 90 % (10 MB)
114 00:55:27.369644 progress 95 % (10 MB)
115 00:55:27.461921 progress 100 % (11 MB)
116 00:55:27.473390 11 MB downloaded in 1.71 s (6.55 MB/s)
117 00:55:27.474188 end: 1.4.1 http-download (duration 00:00:02) [common]
119 00:55:27.475859 end: 1.4 download-retry (duration 00:00:02) [common]
120 00:55:27.476478 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 00:55:27.477033 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 00:55:27.477553 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:55:27.478081 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 00:55:27.479180 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_
125 00:55:27.480144 makedir: /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin
126 00:55:27.480873 makedir: /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/tests
127 00:55:27.481728 makedir: /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/results
128 00:55:27.482447 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-add-keys
129 00:55:27.483516 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-add-sources
130 00:55:27.484618 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-background-process-start
131 00:55:27.485695 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-background-process-stop
132 00:55:27.486791 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-common-functions
133 00:55:27.487822 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-echo-ipv4
134 00:55:27.488964 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-install-packages
135 00:55:27.490053 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-installed-packages
136 00:55:27.491093 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-os-build
137 00:55:27.492222 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-probe-channel
138 00:55:27.493372 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-probe-ip
139 00:55:27.494460 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-target-ip
140 00:55:27.495516 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-target-mac
141 00:55:27.496553 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-target-storage
142 00:55:27.497533 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-test-case
143 00:55:27.498569 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-test-event
144 00:55:27.499663 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-test-feedback
145 00:55:27.500755 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-test-raise
146 00:55:27.501807 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-test-reference
147 00:55:27.502837 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-test-runner
148 00:55:27.503947 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-test-set
149 00:55:27.505108 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-test-shell
150 00:55:27.506254 Updating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-install-packages (oe)
151 00:55:27.507429 Updating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/bin/lava-installed-packages (oe)
152 00:55:27.508511 Creating /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/environment
153 00:55:27.509338 LAVA metadata
154 00:55:27.509835 - LAVA_JOB_ID=972757
155 00:55:27.510263 - LAVA_DISPATCHER_IP=192.168.6.2
156 00:55:27.510967 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 00:55:27.512637 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 00:55:27.513060 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 00:55:27.513282 skipped lava-vland-overlay
160 00:55:27.513531 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 00:55:27.513791 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 00:55:27.514016 skipped lava-multinode-overlay
163 00:55:27.514265 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 00:55:27.514524 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 00:55:27.514811 Loading test definitions
166 00:55:27.515120 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 00:55:27.515351 Using /lava-972757 at stage 0
168 00:55:27.516704 uuid=972757_1.5.2.4.1 testdef=None
169 00:55:27.517095 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 00:55:27.517379 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 00:55:27.519275 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 00:55:27.520193 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 00:55:27.522620 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 00:55:27.523561 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 00:55:27.525926 runner path: /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/0/tests/0_igt-gpu-panfrost test_uuid 972757_1.5.2.4.1
178 00:55:27.526618 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 00:55:27.527472 Creating lava-test-runner.conf files
181 00:55:27.527680 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/972757/lava-overlay-3dey564_/lava-972757/0 for stage 0
182 00:55:27.528092 - 0_igt-gpu-panfrost
183 00:55:27.528506 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 00:55:27.528800 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 00:55:27.555041 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 00:55:27.555527 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 00:55:27.555819 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 00:55:27.556140 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 00:55:27.556438 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 00:55:34.528341 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 00:55:34.528834 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 00:55:34.529110 extracting modules file /var/lib/lava/dispatcher/tmp/972757/tftp-deploy-duj6sh0x/modules/modules.tar to /var/lib/lava/dispatcher/tmp/972757/extract-overlay-ramdisk-m76eh_cy/ramdisk
193 00:55:35.939400 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 00:55:35.939890 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 00:55:35.940210 [common] Applying overlay /var/lib/lava/dispatcher/tmp/972757/compress-overlay-ju7n3aao/overlay-1.5.2.5.tar.gz to ramdisk
196 00:55:35.940445 [common] Applying overlay /var/lib/lava/dispatcher/tmp/972757/compress-overlay-ju7n3aao/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/972757/extract-overlay-ramdisk-m76eh_cy/ramdisk
197 00:55:35.970187 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 00:55:35.970587 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 00:55:35.970879 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 00:55:35.971115 Converting downloaded kernel to a uImage
201 00:55:35.971424 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/972757/tftp-deploy-duj6sh0x/kernel/Image /var/lib/lava/dispatcher/tmp/972757/tftp-deploy-duj6sh0x/kernel/uImage
202 00:55:36.428709 output: Image Name:
203 00:55:36.429127 output: Created: Mon Nov 11 00:55:35 2024
204 00:55:36.429333 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 00:55:36.429536 output: Data Size: 37812736 Bytes = 36926.50 KiB = 36.06 MiB
206 00:55:36.429738 output: Load Address: 01080000
207 00:55:36.429935 output: Entry Point: 01080000
208 00:55:36.430134 output:
209 00:55:36.430464 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 00:55:36.430727 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 00:55:36.430995 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 00:55:36.431248 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 00:55:36.431502 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 00:55:36.431754 Building ramdisk /var/lib/lava/dispatcher/tmp/972757/extract-overlay-ramdisk-m76eh_cy/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/972757/extract-overlay-ramdisk-m76eh_cy/ramdisk
215 00:55:43.158549 >> 509035 blocks
216 00:56:04.252078 Adding RAMdisk u-boot header.
217 00:56:04.252795 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/972757/extract-overlay-ramdisk-m76eh_cy/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/972757/extract-overlay-ramdisk-m76eh_cy/ramdisk.cpio.gz.uboot
218 00:56:04.919575 output: Image Name:
219 00:56:04.919974 output: Created: Mon Nov 11 00:56:04 2024
220 00:56:04.920419 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 00:56:04.920826 output: Data Size: 66431387 Bytes = 64874.40 KiB = 63.35 MiB
222 00:56:04.921220 output: Load Address: 00000000
223 00:56:04.921611 output: Entry Point: 00000000
224 00:56:04.922001 output:
225 00:56:04.923052 rename /var/lib/lava/dispatcher/tmp/972757/extract-overlay-ramdisk-m76eh_cy/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/972757/tftp-deploy-duj6sh0x/ramdisk/ramdisk.cpio.gz.uboot
226 00:56:04.923762 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 00:56:04.924330 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 00:56:04.924853 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 00:56:04.925298 No LXC device requested
230 00:56:04.925790 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 00:56:04.926287 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 00:56:04.926771 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 00:56:04.927174 Checking files for TFTP limit of 4294967296 bytes.
234 00:56:04.929838 end: 1 tftp-deploy (duration 00:00:40) [common]
235 00:56:04.930410 start: 2 uboot-action (timeout 00:05:00) [common]
236 00:56:04.930926 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 00:56:04.931415 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 00:56:04.931909 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 00:56:04.932462 Using kernel file from prepare-kernel: 972757/tftp-deploy-duj6sh0x/kernel/uImage
240 00:56:04.933082 substitutions:
241 00:56:04.933490 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 00:56:04.933891 - {DTB_ADDR}: 0x01070000
243 00:56:04.934284 - {DTB}: 972757/tftp-deploy-duj6sh0x/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 00:56:04.934683 - {INITRD}: 972757/tftp-deploy-duj6sh0x/ramdisk/ramdisk.cpio.gz.uboot
245 00:56:04.935076 - {KERNEL_ADDR}: 0x01080000
246 00:56:04.935466 - {KERNEL}: 972757/tftp-deploy-duj6sh0x/kernel/uImage
247 00:56:04.935860 - {LAVA_MAC}: None
248 00:56:04.936324 - {PRESEED_CONFIG}: None
249 00:56:04.936723 - {PRESEED_LOCAL}: None
250 00:56:04.937111 - {RAMDISK_ADDR}: 0x08000000
251 00:56:04.937498 - {RAMDISK}: 972757/tftp-deploy-duj6sh0x/ramdisk/ramdisk.cpio.gz.uboot
252 00:56:04.937888 - {ROOT_PART}: None
253 00:56:04.938273 - {ROOT}: None
254 00:56:04.938662 - {SERVER_IP}: 192.168.6.2
255 00:56:04.939055 - {TEE_ADDR}: 0x83000000
256 00:56:04.939442 - {TEE}: None
257 00:56:04.939826 Parsed boot commands:
258 00:56:04.940225 - setenv autoload no
259 00:56:04.940613 - setenv initrd_high 0xffffffff
260 00:56:04.940998 - setenv fdt_high 0xffffffff
261 00:56:04.941379 - dhcp
262 00:56:04.941763 - setenv serverip 192.168.6.2
263 00:56:04.942148 - tftpboot 0x01080000 972757/tftp-deploy-duj6sh0x/kernel/uImage
264 00:56:04.942532 - tftpboot 0x08000000 972757/tftp-deploy-duj6sh0x/ramdisk/ramdisk.cpio.gz.uboot
265 00:56:04.942917 - tftpboot 0x01070000 972757/tftp-deploy-duj6sh0x/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 00:56:04.943304 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 00:56:04.943689 - bootm 0x01080000 0x08000000 0x01070000
268 00:56:04.944214 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 00:56:04.945683 start: 2.3 connect-device (timeout 00:05:00) [common]
271 00:56:04.946118 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 00:56:04.961021 Setting prompt string to ['lava-test: # ']
273 00:56:04.962532 end: 2.3 connect-device (duration 00:00:00) [common]
274 00:56:04.963127 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 00:56:04.963662 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 00:56:04.964235 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 00:56:04.965557 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 00:56:05.004523 >> OK - accepted request
279 00:56:05.006642 Returned 0 in 0 seconds
280 00:56:05.107814 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 00:56:05.109499 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 00:56:05.110055 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 00:56:05.110547 Setting prompt string to ['Hit any key to stop autoboot']
285 00:56:05.110986 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 00:56:05.112585 Trying 192.168.56.21...
287 00:56:05.113064 Connected to conserv1.
288 00:56:05.113478 Escape character is '^]'.
289 00:56:05.113887
290 00:56:05.114299 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 00:56:05.114721
292 00:56:12.768113 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 00:56:12.768768 bl2_stage_init 0x01
294 00:56:12.769200 bl2_stage_init 0x81
295 00:56:12.773454 hw id: 0x0000 - pwm id 0x01
296 00:56:12.773983 bl2_stage_init 0xc1
297 00:56:12.779041 bl2_stage_init 0x02
298 00:56:12.779558
299 00:56:12.780006 L0:00000000
300 00:56:12.780414 L1:00000703
301 00:56:12.780817 L2:00008067
302 00:56:12.781200 L3:15000000
303 00:56:12.784643 S1:00000000
304 00:56:12.785124 B2:20282000
305 00:56:12.785514 B1:a0f83180
306 00:56:12.785898
307 00:56:12.786281 TE: 71183
308 00:56:12.786666
309 00:56:12.790293 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 00:56:12.790770
311 00:56:12.795910 Board ID = 1
312 00:56:12.796441 Set cpu clk to 24M
313 00:56:12.796834 Set clk81 to 24M
314 00:56:12.801506 Use GP1_pll as DSU clk.
315 00:56:12.801999 DSU clk: 1200 Mhz
316 00:56:12.802393 CPU clk: 1200 MHz
317 00:56:12.807028 Set clk81 to 166.6M
318 00:56:12.812738 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 00:56:12.813234 board id: 1
320 00:56:12.819665 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 00:56:12.830556 fw parse done
322 00:56:12.836549 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 00:56:12.879642 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 00:56:12.890853 PIEI prepare done
325 00:56:12.891316 fastboot data load
326 00:56:12.891713 fastboot data verify
327 00:56:12.896397 verify result: 266
328 00:56:12.901974 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 00:56:12.902412 LPDDR4 probe
330 00:56:12.902803 ddr clk to 1584MHz
331 00:56:12.909934 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 00:56:12.947700
333 00:56:12.948199 dmc_version 0001
334 00:56:12.954752 Check phy result
335 00:56:12.960730 INFO : End of CA training
336 00:56:12.961181 INFO : End of initialization
337 00:56:12.966327 INFO : Training has run successfully!
338 00:56:12.966765 Check phy result
339 00:56:12.971942 INFO : End of initialization
340 00:56:12.972415 INFO : End of read enable training
341 00:56:12.975265 INFO : End of fine write leveling
342 00:56:12.980851 INFO : End of Write leveling coarse delay
343 00:56:12.986411 INFO : Training has run successfully!
344 00:56:12.986849 Check phy result
345 00:56:12.987237 INFO : End of initialization
346 00:56:12.992059 INFO : End of read dq deskew training
347 00:56:12.997678 INFO : End of MPR read delay center optimization
348 00:56:12.998137 INFO : End of write delay center optimization
349 00:56:13.003264 INFO : End of read delay center optimization
350 00:56:13.008872 INFO : End of max read latency training
351 00:56:13.009316 INFO : Training has run successfully!
352 00:56:13.014462 1D training succeed
353 00:56:13.020351 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 00:56:13.068692 Check phy result
355 00:56:13.069171 INFO : End of initialization
356 00:56:13.095972 INFO : End of 2D read delay Voltage center optimization
357 00:56:13.120109 INFO : End of 2D read delay Voltage center optimization
358 00:56:13.176712 INFO : End of 2D write delay Voltage center optimization
359 00:56:13.230655 INFO : End of 2D write delay Voltage center optimization
360 00:56:13.236330 INFO : Training has run successfully!
361 00:56:13.236767
362 00:56:13.237158 channel==0
363 00:56:13.241838 RxClkDly_Margin_A0==78 ps 8
364 00:56:13.242274 TxDqDly_Margin_A0==98 ps 10
365 00:56:13.245183 RxClkDly_Margin_A1==88 ps 9
366 00:56:13.245612 TxDqDly_Margin_A1==98 ps 10
367 00:56:13.250750 TrainedVREFDQ_A0==74
368 00:56:13.251189 TrainedVREFDQ_A1==74
369 00:56:13.251577 VrefDac_Margin_A0==24
370 00:56:13.256344 DeviceVref_Margin_A0==40
371 00:56:13.256774 VrefDac_Margin_A1==23
372 00:56:13.261971 DeviceVref_Margin_A1==40
373 00:56:13.262406
374 00:56:13.262797
375 00:56:13.263182 channel==1
376 00:56:13.263566 RxClkDly_Margin_A0==78 ps 8
377 00:56:13.267536 TxDqDly_Margin_A0==98 ps 10
378 00:56:13.267976 RxClkDly_Margin_A1==88 ps 9
379 00:56:13.273189 TxDqDly_Margin_A1==88 ps 9
380 00:56:13.273626 TrainedVREFDQ_A0==78
381 00:56:13.274017 TrainedVREFDQ_A1==78
382 00:56:13.278737 VrefDac_Margin_A0==22
383 00:56:13.279164 DeviceVref_Margin_A0==36
384 00:56:13.284341 VrefDac_Margin_A1==22
385 00:56:13.284776 DeviceVref_Margin_A1==36
386 00:56:13.285164
387 00:56:13.289936 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 00:56:13.290368
389 00:56:13.317936 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000017 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
390 00:56:13.323574 2D training succeed
391 00:56:13.329197 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 00:56:13.329635 auto size-- 65535DDR cs0 size: 2048MB
393 00:56:13.334742 DDR cs1 size: 2048MB
394 00:56:13.335170 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 00:56:13.340333 cs0 DataBus test pass
396 00:56:13.340767 cs1 DataBus test pass
397 00:56:13.341155 cs0 AddrBus test pass
398 00:56:13.345934 cs1 AddrBus test pass
399 00:56:13.346366
400 00:56:13.346755 100bdlr_step_size ps== 471
401 00:56:13.347145 result report
402 00:56:13.351569 boot times 0Enable ddr reg access
403 00:56:13.359113 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 00:56:13.372938 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 00:56:14.031664 bl2z: ptr: 05129330, size: 00001e40
406 00:56:14.040289 0.0;M3 CHK:0;cm4_sp_mode 0
407 00:56:14.040952 MVN_1=0x00000000
408 00:56:14.042489 MVN_2=0x00000000
409 00:56:14.051419 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 00:56:14.052039 OPS=0x04
411 00:56:14.052501 ring efuse init
412 00:56:14.057031 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 00:56:14.057566 [0.017355 Inits done]
414 00:56:14.057977 secure task start!
415 00:56:14.064560 high task start!
416 00:56:14.065083 low task start!
417 00:56:14.065481 run into bl31
418 00:56:14.073257 NOTICE: BL31: v1.3(release):4fc40b1
419 00:56:14.081176 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 00:56:14.081874 NOTICE: BL31: G12A normal boot!
421 00:56:14.096594 NOTICE: BL31: BL33 decompress pass
422 00:56:14.101341 ERROR: Error initializing runtime service opteed_fast
423 00:56:16.817848 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 00:56:16.818293 bl2_stage_init 0x01
425 00:56:16.818512 bl2_stage_init 0x81
426 00:56:16.823432 hw id: 0x0000 - pwm id 0x01
427 00:56:16.823753 bl2_stage_init 0xc1
428 00:56:16.829034 bl2_stage_init 0x02
429 00:56:16.829395
430 00:56:16.829609 L0:00000000
431 00:56:16.829812 L1:00000703
432 00:56:16.830010 L2:00008067
433 00:56:16.830209 L3:15000000
434 00:56:16.834602 S1:00000000
435 00:56:16.834877 B2:20282000
436 00:56:16.835082 B1:a0f83180
437 00:56:16.835281
438 00:56:16.835480 TE: 70233
439 00:56:16.835679
440 00:56:16.840124 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 00:56:16.840400
442 00:56:16.845709 Board ID = 1
443 00:56:16.845989 Set cpu clk to 24M
444 00:56:16.846186 Set clk81 to 24M
445 00:56:16.851285 Use GP1_pll as DSU clk.
446 00:56:16.851564 DSU clk: 1200 Mhz
447 00:56:16.851762 CPU clk: 1200 MHz
448 00:56:16.856900 Set clk81 to 166.6M
449 00:56:16.862573 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 00:56:16.862892 board id: 1
451 00:56:16.869911 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 00:56:16.880869 fw parse done
453 00:56:16.886688 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 00:56:16.929823 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 00:56:16.940908 PIEI prepare done
456 00:56:16.941399 fastboot data load
457 00:56:16.941832 fastboot data verify
458 00:56:16.946469 verify result: 266
459 00:56:16.952095 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 00:56:16.952571 LPDDR4 probe
461 00:56:16.952997 ddr clk to 1584MHz
462 00:56:16.960070 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 00:56:16.997814
464 00:56:16.998297 dmc_version 0001
465 00:56:17.004938 Check phy result
466 00:56:17.011152 INFO : End of CA training
467 00:56:17.011628 INFO : End of initialization
468 00:56:17.016438 INFO : Training has run successfully!
469 00:56:17.016930 Check phy result
470 00:56:17.022053 INFO : End of initialization
471 00:56:17.022532 INFO : End of read enable training
472 00:56:17.027765 INFO : End of fine write leveling
473 00:56:17.033278 INFO : End of Write leveling coarse delay
474 00:56:17.033790 INFO : Training has run successfully!
475 00:56:17.034260 Check phy result
476 00:56:17.038889 INFO : End of initialization
477 00:56:17.039371 INFO : End of read dq deskew training
478 00:56:17.044636 INFO : End of MPR read delay center optimization
479 00:56:17.050086 INFO : End of write delay center optimization
480 00:56:17.055732 INFO : End of read delay center optimization
481 00:56:17.056248 INFO : End of max read latency training
482 00:56:17.061287 INFO : Training has run successfully!
483 00:56:17.061756 1D training succeed
484 00:56:17.070449 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 00:56:17.118789 Check phy result
486 00:56:17.119322 INFO : End of initialization
487 00:56:17.146161 INFO : End of 2D read delay Voltage center optimization
488 00:56:17.170292 INFO : End of 2D read delay Voltage center optimization
489 00:56:17.226071 INFO : End of 2D write delay Voltage center optimization
490 00:56:17.281090 INFO : End of 2D write delay Voltage center optimization
491 00:56:17.286491 INFO : Training has run successfully!
492 00:56:17.286991
493 00:56:17.287461 channel==0
494 00:56:17.292103 RxClkDly_Margin_A0==78 ps 8
495 00:56:17.292634 TxDqDly_Margin_A0==98 ps 10
496 00:56:17.297868 RxClkDly_Margin_A1==69 ps 7
497 00:56:17.298427 TxDqDly_Margin_A1==88 ps 9
498 00:56:17.298880 TrainedVREFDQ_A0==74
499 00:56:17.303422 TrainedVREFDQ_A1==74
500 00:56:17.303974 VrefDac_Margin_A0==25
501 00:56:17.304532 DeviceVref_Margin_A0==40
502 00:56:17.308944 VrefDac_Margin_A1==23
503 00:56:17.309415 DeviceVref_Margin_A1==40
504 00:56:17.309850
505 00:56:17.310282
506 00:56:17.310710 channel==1
507 00:56:17.314788 RxClkDly_Margin_A0==88 ps 9
508 00:56:17.315393 TxDqDly_Margin_A0==98 ps 10
509 00:56:17.320287 RxClkDly_Margin_A1==88 ps 9
510 00:56:17.320839 TxDqDly_Margin_A1==88 ps 9
511 00:56:17.325788 TrainedVREFDQ_A0==78
512 00:56:17.326284 TrainedVREFDQ_A1==77
513 00:56:17.326733 VrefDac_Margin_A0==22
514 00:56:17.331356 DeviceVref_Margin_A0==36
515 00:56:17.331886 VrefDac_Margin_A1==22
516 00:56:17.337024 DeviceVref_Margin_A1==37
517 00:56:17.337550
518 00:56:17.338029 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 00:56:17.338479
520 00:56:17.372029 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 00:56:17.372725 2D training succeed
522 00:56:17.376355 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 00:56:17.381839 auto size-- 65535DDR cs0 size: 2048MB
524 00:56:17.382425 DDR cs1 size: 2048MB
525 00:56:17.387693 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 00:56:17.388263 cs0 DataBus test pass
527 00:56:17.393069 cs1 DataBus test pass
528 00:56:17.393622 cs0 AddrBus test pass
529 00:56:17.394081 cs1 AddrBus test pass
530 00:56:17.394517
531 00:56:17.398592 100bdlr_step_size ps== 471
532 00:56:17.399081 result report
533 00:56:17.404280 boot times 0Enable ddr reg access
534 00:56:17.409328 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 00:56:17.424243 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 00:56:18.082663 bl2z: ptr: 05129330, size: 00001e40
537 00:56:18.090731 0.0;M3 CHK:0;cm4_sp_mode 0
538 00:56:18.091242 MVN_1=0x00000000
539 00:56:18.091681 MVN_2=0x00000000
540 00:56:18.102226 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 00:56:18.102735 OPS=0x04
542 00:56:18.103180 ring efuse init
543 00:56:18.107884 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 00:56:18.108419 [0.017354 Inits done]
545 00:56:18.108860 secure task start!
546 00:56:18.115865 high task start!
547 00:56:18.116383 low task start!
548 00:56:18.116820 run into bl31
549 00:56:18.124467 NOTICE: BL31: v1.3(release):4fc40b1
550 00:56:18.132335 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 00:56:18.132848 NOTICE: BL31: G12A normal boot!
552 00:56:18.147874 NOTICE: BL31: BL33 decompress pass
553 00:56:18.153536 ERROR: Error initializing runtime service opteed_fast
554 00:56:19.517974 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 00:56:19.518614 bl2_stage_init 0x01
556 00:56:19.519087 bl2_stage_init 0x81
557 00:56:19.523575 hw id: 0x0000 - pwm id 0x01
558 00:56:19.524120 bl2_stage_init 0xc1
559 00:56:19.524580 bl2_stage_init 0x02
560 00:56:19.525021
561 00:56:19.529268 L0:00000000
562 00:56:19.529770 L1:00000703
563 00:56:19.530217 L2:00008067
564 00:56:19.530654 L3:15000000
565 00:56:19.531086 S1:00000000
566 00:56:19.531867 B2:20282000
567 00:56:19.536244 B1:a0f83180
568 00:56:19.536728
569 00:56:19.537176 TE: 70538
570 00:56:19.537618
571 00:56:19.541790 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 00:56:19.542294
573 00:56:19.542746 Board ID = 1
574 00:56:19.547369 Set cpu clk to 24M
575 00:56:19.547861 Set clk81 to 24M
576 00:56:19.548351 Use GP1_pll as DSU clk.
577 00:56:19.550846 DSU clk: 1200 Mhz
578 00:56:19.551321 CPU clk: 1200 MHz
579 00:56:19.556373 Set clk81 to 166.6M
580 00:56:19.562116 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 00:56:19.562614 board id: 1
582 00:56:19.569175 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 00:56:19.579748 fw parse done
584 00:56:19.585647 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 00:56:19.628487 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 00:56:19.639351 PIEI prepare done
587 00:56:19.639925 fastboot data load
588 00:56:19.640432 fastboot data verify
589 00:56:19.644897 verify result: 266
590 00:56:19.650695 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 00:56:19.651229 LPDDR4 probe
592 00:56:19.651678 ddr clk to 1584MHz
593 00:56:19.658493 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 00:56:19.695821
595 00:56:19.696381 dmc_version 0001
596 00:56:19.702475 Check phy result
597 00:56:19.708460 INFO : End of CA training
598 00:56:19.708951 INFO : End of initialization
599 00:56:19.714026 INFO : Training has run successfully!
600 00:56:19.714517 Check phy result
601 00:56:19.719559 INFO : End of initialization
602 00:56:19.720077 INFO : End of read enable training
603 00:56:19.722857 INFO : End of fine write leveling
604 00:56:19.728458 INFO : End of Write leveling coarse delay
605 00:56:19.734031 INFO : Training has run successfully!
606 00:56:19.734348 Check phy result
607 00:56:19.734578 INFO : End of initialization
608 00:56:19.739589 INFO : End of read dq deskew training
609 00:56:19.742936 INFO : End of MPR read delay center optimization
610 00:56:19.748481 INFO : End of write delay center optimization
611 00:56:19.754098 INFO : End of read delay center optimization
612 00:56:19.754422 INFO : End of max read latency training
613 00:56:19.759664 INFO : Training has run successfully!
614 00:56:19.760199 1D training succeed
615 00:56:19.767913 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 00:56:19.815523 Check phy result
617 00:56:19.815899 INFO : End of initialization
618 00:56:19.837777 INFO : End of 2D read delay Voltage center optimization
619 00:56:19.856971 INFO : End of 2D read delay Voltage center optimization
620 00:56:19.908887 INFO : End of 2D write delay Voltage center optimization
621 00:56:19.958023 INFO : End of 2D write delay Voltage center optimization
622 00:56:19.963562 INFO : Training has run successfully!
623 00:56:19.963845
624 00:56:19.964106 channel==0
625 00:56:19.969199 RxClkDly_Margin_A0==78 ps 8
626 00:56:19.969508 TxDqDly_Margin_A0==88 ps 9
627 00:56:19.974746 RxClkDly_Margin_A1==88 ps 9
628 00:56:19.975008 TxDqDly_Margin_A1==88 ps 9
629 00:56:19.975213 TrainedVREFDQ_A0==74
630 00:56:19.980343 TrainedVREFDQ_A1==74
631 00:56:19.980726 VrefDac_Margin_A0==24
632 00:56:19.981034 DeviceVref_Margin_A0==40
633 00:56:19.985946 VrefDac_Margin_A1==22
634 00:56:19.986331 DeviceVref_Margin_A1==40
635 00:56:19.986560
636 00:56:19.986761
637 00:56:19.986958 channel==1
638 00:56:19.991547 RxClkDly_Margin_A0==78 ps 8
639 00:56:19.992001 TxDqDly_Margin_A0==98 ps 10
640 00:56:19.997246 RxClkDly_Margin_A1==88 ps 9
641 00:56:19.997743 TxDqDly_Margin_A1==88 ps 9
642 00:56:20.002806 TrainedVREFDQ_A0==78
643 00:56:20.003288 TrainedVREFDQ_A1==78
644 00:56:20.003731 VrefDac_Margin_A0==22
645 00:56:20.008374 DeviceVref_Margin_A0==36
646 00:56:20.008845 VrefDac_Margin_A1==22
647 00:56:20.009284 DeviceVref_Margin_A1==36
648 00:56:20.013981
649 00:56:20.014467 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 00:56:20.014915
651 00:56:20.047571 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000016 00000017 00000017 00000018 00000017 00000018 00000019 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
652 00:56:20.048133 2D training succeed
653 00:56:20.053217 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 00:56:20.058797 auto size-- 65535DDR cs0 size: 2048MB
655 00:56:20.059284 DDR cs1 size: 2048MB
656 00:56:20.064382 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 00:56:20.064859 cs0 DataBus test pass
658 00:56:20.069987 cs1 DataBus test pass
659 00:56:20.070463 cs0 AddrBus test pass
660 00:56:20.070902 cs1 AddrBus test pass
661 00:56:20.071338
662 00:56:20.075578 100bdlr_step_size ps== 464
663 00:56:20.076100 result report
664 00:56:20.081233 boot times 0Enable ddr reg access
665 00:56:20.086280 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 00:56:20.100109 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 00:56:20.755628 bl2z: ptr: 05129330, size: 00001e40
668 00:56:20.762754 0.0;M3 CHK:0;cm4_sp_mode 0
669 00:56:20.763290 MVN_1=0x00000000
670 00:56:20.763742 MVN_2=0x00000000
671 00:56:20.774262 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 00:56:20.774778 OPS=0x04
673 00:56:20.775265 ring efuse init
674 00:56:20.779863 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 00:56:20.780400 [0.017318 Inits done]
676 00:56:20.780845 secure task start!
677 00:56:20.787341 high task start!
678 00:56:20.787837 low task start!
679 00:56:20.788324 run into bl31
680 00:56:20.795888 NOTICE: BL31: v1.3(release):4fc40b1
681 00:56:20.803668 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 00:56:20.804207 NOTICE: BL31: G12A normal boot!
683 00:56:20.819311 NOTICE: BL31: BL33 decompress pass
684 00:56:20.825070 ERROR: Error initializing runtime service opteed_fast
685 00:56:21.620443
686 00:56:21.620856
687 00:56:21.625723 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 00:56:21.626138
689 00:56:21.629190 Model: Libre Computer AML-S905D3-CC Solitude
690 00:56:21.776279 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 00:56:21.791659 DRAM: 2 GiB (effective 3.8 GiB)
692 00:56:21.892661 Core: 406 devices, 33 uclasses, devicetree: separate
693 00:56:21.898244 WDT: Not starting watchdog@f0d0
694 00:56:21.923577 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 00:56:21.935780 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 00:56:21.940727 ** Bad device specification mmc 0 **
697 00:56:21.950837 Card did not respond to voltage select! : -110
698 00:56:21.958496 ** Bad device specification mmc 0 **
699 00:56:21.958859 Couldn't find partition mmc 0
700 00:56:21.966853 Card did not respond to voltage select! : -110
701 00:56:21.972468 ** Bad device specification mmc 0 **
702 00:56:21.972798 Couldn't find partition mmc 0
703 00:56:21.977412 Error: could not access storage.
704 00:56:22.273875 Net: eth0: ethernet@ff3f0000
705 00:56:22.274303 starting USB...
706 00:56:22.518517 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 00:56:22.519079 Starting the controller
708 00:56:22.525513 USB XHCI 1.10
709 00:56:24.079761 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 00:56:24.088100 scanning usb for storage devices... 0 Storage Device(s) found
712 00:56:24.139334 Hit any key to stop autoboot: 1
713 00:56:24.140363 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 00:56:24.140745 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 00:56:24.141012 Setting prompt string to ['=>']
716 00:56:24.141266 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 00:56:24.154110 0
718 00:56:24.154770 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 00:56:24.255592 => setenv autoload no
721 00:56:24.256644 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 00:56:24.260746 setenv autoload no
724 00:56:24.362072 => setenv initrd_high 0xffffffff
725 00:56:24.362766 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 00:56:24.367067 setenv initrd_high 0xffffffff
728 00:56:24.468360 => setenv fdt_high 0xffffffff
729 00:56:24.469531 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
730 00:56:24.473741 setenv fdt_high 0xffffffff
732 00:56:24.575653 => dhcp
733 00:56:24.576403 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 00:56:24.580777 dhcp
735 00:56:25.035500 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 00:56:25.035939 Speed: 1000, full duplex
737 00:56:25.036229 BOOTP broadcast 1
738 00:56:25.284364 BOOTP broadcast 2
739 00:56:25.309202 DHCP client bound to address 192.168.6.21 (272 ms)
741 00:56:25.411084 => setenv serverip 192.168.6.2
742 00:56:25.411661 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
743 00:56:25.416064 setenv serverip 192.168.6.2
745 00:56:25.517155 => tftpboot 0x01080000 972757/tftp-deploy-duj6sh0x/kernel/uImage
746 00:56:25.517984 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
747 00:56:25.524583 tftpboot 0x01080000 972757/tftp-deploy-duj6sh0x/kernel/uImage
748 00:56:25.525147 Speed: 1000, full duplex
749 00:56:25.525616 Using ethernet@ff3f0000 device
750 00:56:25.530141 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
751 00:56:25.535514 Filename '972757/tftp-deploy-duj6sh0x/kernel/uImage'.
752 00:56:25.539550 Load address: 0x1080000
753 00:56:28.033459 Loading: *################################################## 36.1 MiB
754 00:56:28.033888 14.4 MiB/s
755 00:56:28.034143 done
756 00:56:28.037918 Bytes transferred = 37812800 (240fa40 hex)
758 00:56:28.139552 => tftpboot 0x08000000 972757/tftp-deploy-duj6sh0x/ramdisk/ramdisk.cpio.gz.uboot
759 00:56:28.140356 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
760 00:56:28.146951 tftpboot 0x08000000 972757/tftp-deploy-duj6sh0x/ramdisk/ramdisk.cpio.gz.uboot
761 00:56:28.147447 Speed: 1000, full duplex
762 00:56:28.147881 Using ethernet@ff3f0000 device
763 00:56:28.152502 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
764 00:56:28.162384 Filename '972757/tftp-deploy-duj6sh0x/ramdisk/ramdisk.cpio.gz.uboot'.
765 00:56:28.162794 Load address: 0x8000000
766 00:56:32.305934 Loading: *################################################# UDP wrong checksum 0000000f 0000d0a7
767 00:56:34.357552 UDP wrong checksum 000000ff 0000b60c
768 00:56:34.404440 UDP wrong checksum 000000ff 000048ff
769 00:56:37.305342 T UDP wrong checksum 0000000f 0000d0a7
770 00:56:47.307255 T T UDP wrong checksum 0000000f 0000d0a7
771 00:56:51.677941 UDP wrong checksum 000000ff 00008619
772 00:56:51.747439 UDP wrong checksum 000000ff 0000210c
773 00:56:54.057700 T UDP wrong checksum 000000ff 0000df63
774 00:56:54.117544 UDP wrong checksum 000000ff 00006a56
775 00:57:07.312307 T T T UDP wrong checksum 0000000f 0000d0a7
776 00:57:27.317129 T T T
777 00:57:27.317526 Retry count exceeded; starting again
779 00:57:27.320449 end: 2.4.3 bootloader-commands (duration 00:01:03) [common]
782 00:57:27.321360 end: 2.4 uboot-commands (duration 00:01:22) [common]
784 00:57:27.322036 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
786 00:57:27.322554 end: 2 uboot-action (duration 00:01:22) [common]
788 00:57:27.323329 Cleaning after the job
789 00:57:27.323630 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972757/tftp-deploy-duj6sh0x/ramdisk
790 00:57:27.324419 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972757/tftp-deploy-duj6sh0x/kernel
791 00:57:27.346656 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972757/tftp-deploy-duj6sh0x/dtb
792 00:57:27.347445 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972757/tftp-deploy-duj6sh0x/modules
793 00:57:27.370350 start: 4.1 power-off (timeout 00:00:30) [common]
794 00:57:27.371119 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
795 00:57:27.405561 >> OK - accepted request
796 00:57:27.407810 Returned 0 in 0 seconds
797 00:57:27.508777 end: 4.1 power-off (duration 00:00:00) [common]
799 00:57:27.510020 start: 4.2 read-feedback (timeout 00:10:00) [common]
800 00:57:27.510824 Listened to connection for namespace 'common' for up to 1s
801 00:57:28.511768 Finalising connection for namespace 'common'
802 00:57:28.512410 Disconnecting from shell: Finalise
803 00:57:28.512774 =>
804 00:57:28.613739 end: 4.2 read-feedback (duration 00:00:01) [common]
805 00:57:28.614646 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/972757
806 00:57:29.349052 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/972757
807 00:57:29.349670 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.