Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 23:29:21.166226 lava-dispatcher, installed at version: 2024.01
2 23:29:21.167015 start: 0 validate
3 23:29:21.167499 Start time: 2024-11-10 23:29:21.167469+00:00 (UTC)
4 23:29:21.168077 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:29:21.168626 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:29:21.210317 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:29:21.210883 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 23:29:21.241349 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:29:21.241984 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 23:29:21.274718 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:29:21.275234 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:29:21.307815 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 23:29:21.308352 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 23:29:21.345990 validate duration: 0.18
16 23:29:21.346855 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:29:21.347179 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:29:21.347490 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:29:21.348069 Not decompressing ramdisk as can be used compressed.
20 23:29:21.348510 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 23:29:21.348788 saving as /var/lib/lava/dispatcher/tmp/972963/tftp-deploy-8lbzh6g8/ramdisk/initrd.cpio.gz
22 23:29:21.349061 total size: 5628182 (5 MB)
23 23:29:21.385787 progress 0 % (0 MB)
24 23:29:21.392779 progress 5 % (0 MB)
25 23:29:21.401047 progress 10 % (0 MB)
26 23:29:21.406269 progress 15 % (0 MB)
27 23:29:21.410483 progress 20 % (1 MB)
28 23:29:21.414347 progress 25 % (1 MB)
29 23:29:21.418569 progress 30 % (1 MB)
30 23:29:21.422802 progress 35 % (1 MB)
31 23:29:21.426694 progress 40 % (2 MB)
32 23:29:21.430711 progress 45 % (2 MB)
33 23:29:21.434634 progress 50 % (2 MB)
34 23:29:21.438927 progress 55 % (2 MB)
35 23:29:21.442979 progress 60 % (3 MB)
36 23:29:21.446691 progress 65 % (3 MB)
37 23:29:21.450734 progress 70 % (3 MB)
38 23:29:21.454411 progress 75 % (4 MB)
39 23:29:21.458506 progress 80 % (4 MB)
40 23:29:21.462355 progress 85 % (4 MB)
41 23:29:21.466524 progress 90 % (4 MB)
42 23:29:21.470598 progress 95 % (5 MB)
43 23:29:21.474121 progress 100 % (5 MB)
44 23:29:21.474821 5 MB downloaded in 0.13 s (42.69 MB/s)
45 23:29:21.475370 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:29:21.476315 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:29:21.476614 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:29:21.476887 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:29:21.477361 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm64/defconfig/gcc-12/kernel/Image
51 23:29:21.477610 saving as /var/lib/lava/dispatcher/tmp/972963/tftp-deploy-8lbzh6g8/kernel/Image
52 23:29:21.477819 total size: 45713920 (43 MB)
53 23:29:21.478033 No compression specified
54 23:29:21.513239 progress 0 % (0 MB)
55 23:29:21.541300 progress 5 % (2 MB)
56 23:29:21.569468 progress 10 % (4 MB)
57 23:29:21.597434 progress 15 % (6 MB)
58 23:29:21.625132 progress 20 % (8 MB)
59 23:29:21.652312 progress 25 % (10 MB)
60 23:29:21.680019 progress 30 % (13 MB)
61 23:29:21.707821 progress 35 % (15 MB)
62 23:29:21.735575 progress 40 % (17 MB)
63 23:29:21.763160 progress 45 % (19 MB)
64 23:29:21.790798 progress 50 % (21 MB)
65 23:29:21.818550 progress 55 % (24 MB)
66 23:29:21.846064 progress 60 % (26 MB)
67 23:29:21.873284 progress 65 % (28 MB)
68 23:29:21.900906 progress 70 % (30 MB)
69 23:29:21.928354 progress 75 % (32 MB)
70 23:29:21.955557 progress 80 % (34 MB)
71 23:29:21.982675 progress 85 % (37 MB)
72 23:29:22.010089 progress 90 % (39 MB)
73 23:29:22.037662 progress 95 % (41 MB)
74 23:29:22.064842 progress 100 % (43 MB)
75 23:29:22.065364 43 MB downloaded in 0.59 s (74.20 MB/s)
76 23:29:22.065838 end: 1.2.1 http-download (duration 00:00:01) [common]
78 23:29:22.066654 end: 1.2 download-retry (duration 00:00:01) [common]
79 23:29:22.066929 start: 1.3 download-retry (timeout 00:09:59) [common]
80 23:29:22.067194 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 23:29:22.067646 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 23:29:22.067886 saving as /var/lib/lava/dispatcher/tmp/972963/tftp-deploy-8lbzh6g8/dtb/meson-g12b-a311d-libretech-cc.dtb
83 23:29:22.068119 total size: 54703 (0 MB)
84 23:29:22.068329 No compression specified
85 23:29:22.106948 progress 59 % (0 MB)
86 23:29:22.107785 progress 100 % (0 MB)
87 23:29:22.108371 0 MB downloaded in 0.04 s (1.30 MB/s)
88 23:29:22.108847 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:29:22.109655 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:29:22.109919 start: 1.4 download-retry (timeout 00:09:59) [common]
92 23:29:22.110181 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 23:29:22.110630 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 23:29:22.110866 saving as /var/lib/lava/dispatcher/tmp/972963/tftp-deploy-8lbzh6g8/nfsrootfs/full.rootfs.tar
95 23:29:22.111069 total size: 107552908 (102 MB)
96 23:29:22.111275 Using unxz to decompress xz
97 23:29:22.141713 progress 0 % (0 MB)
98 23:29:22.778774 progress 5 % (5 MB)
99 23:29:23.503246 progress 10 % (10 MB)
100 23:29:24.219881 progress 15 % (15 MB)
101 23:29:24.969074 progress 20 % (20 MB)
102 23:29:25.538028 progress 25 % (25 MB)
103 23:29:26.158667 progress 30 % (30 MB)
104 23:29:26.889473 progress 35 % (35 MB)
105 23:29:27.239173 progress 40 % (41 MB)
106 23:29:27.667079 progress 45 % (46 MB)
107 23:29:28.350930 progress 50 % (51 MB)
108 23:29:29.022859 progress 55 % (56 MB)
109 23:29:29.767761 progress 60 % (61 MB)
110 23:29:30.512619 progress 65 % (66 MB)
111 23:29:31.242965 progress 70 % (71 MB)
112 23:29:32.008972 progress 75 % (76 MB)
113 23:29:32.680411 progress 80 % (82 MB)
114 23:29:33.376480 progress 85 % (87 MB)
115 23:29:34.098575 progress 90 % (92 MB)
116 23:29:34.802931 progress 95 % (97 MB)
117 23:29:35.541714 progress 100 % (102 MB)
118 23:29:35.553621 102 MB downloaded in 13.44 s (7.63 MB/s)
119 23:29:35.554984 end: 1.4.1 http-download (duration 00:00:13) [common]
121 23:29:35.557085 end: 1.4 download-retry (duration 00:00:13) [common]
122 23:29:35.557921 start: 1.5 download-retry (timeout 00:09:46) [common]
123 23:29:35.558781 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 23:29:35.560155 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm64/defconfig/gcc-12/modules.tar.xz
125 23:29:35.560882 saving as /var/lib/lava/dispatcher/tmp/972963/tftp-deploy-8lbzh6g8/modules/modules.tar
126 23:29:35.561529 total size: 11614384 (11 MB)
127 23:29:35.562195 Using unxz to decompress xz
128 23:29:35.604283 progress 0 % (0 MB)
129 23:29:35.669569 progress 5 % (0 MB)
130 23:29:35.743522 progress 10 % (1 MB)
131 23:29:35.838932 progress 15 % (1 MB)
132 23:29:35.931139 progress 20 % (2 MB)
133 23:29:36.009506 progress 25 % (2 MB)
134 23:29:36.084687 progress 30 % (3 MB)
135 23:29:36.162002 progress 35 % (3 MB)
136 23:29:36.233615 progress 40 % (4 MB)
137 23:29:36.309220 progress 45 % (5 MB)
138 23:29:36.393983 progress 50 % (5 MB)
139 23:29:36.470480 progress 55 % (6 MB)
140 23:29:36.556159 progress 60 % (6 MB)
141 23:29:36.636505 progress 65 % (7 MB)
142 23:29:36.717132 progress 70 % (7 MB)
143 23:29:36.796859 progress 75 % (8 MB)
144 23:29:36.879527 progress 80 % (8 MB)
145 23:29:36.958690 progress 85 % (9 MB)
146 23:29:37.037015 progress 90 % (9 MB)
147 23:29:37.114382 progress 95 % (10 MB)
148 23:29:37.190661 progress 100 % (11 MB)
149 23:29:37.202548 11 MB downloaded in 1.64 s (6.75 MB/s)
150 23:29:37.203125 end: 1.5.1 http-download (duration 00:00:02) [common]
152 23:29:37.203954 end: 1.5 download-retry (duration 00:00:02) [common]
153 23:29:37.204598 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 23:29:37.205179 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 23:29:47.167853 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/972963/extract-nfsrootfs-c3blvzol
156 23:29:47.168468 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 23:29:47.168779 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 23:29:47.169444 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm
159 23:29:47.169914 makedir: /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin
160 23:29:47.170281 makedir: /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/tests
161 23:29:47.170629 makedir: /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/results
162 23:29:47.170986 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-add-keys
163 23:29:47.171577 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-add-sources
164 23:29:47.172155 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-background-process-start
165 23:29:47.172701 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-background-process-stop
166 23:29:47.173264 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-common-functions
167 23:29:47.173795 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-echo-ipv4
168 23:29:47.174328 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-install-packages
169 23:29:47.174857 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-installed-packages
170 23:29:47.175378 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-os-build
171 23:29:47.175896 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-probe-channel
172 23:29:47.176448 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-probe-ip
173 23:29:47.176967 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-target-ip
174 23:29:47.177486 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-target-mac
175 23:29:47.178088 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-target-storage
176 23:29:47.178648 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-test-case
177 23:29:47.179183 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-test-event
178 23:29:47.179704 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-test-feedback
179 23:29:47.180246 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-test-raise
180 23:29:47.180775 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-test-reference
181 23:29:47.181301 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-test-runner
182 23:29:47.181829 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-test-set
183 23:29:47.182374 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-test-shell
184 23:29:47.182916 Updating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-install-packages (oe)
185 23:29:47.183500 Updating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/bin/lava-installed-packages (oe)
186 23:29:47.184001 Creating /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/environment
187 23:29:47.184417 LAVA metadata
188 23:29:47.184694 - LAVA_JOB_ID=972963
189 23:29:47.184925 - LAVA_DISPATCHER_IP=192.168.6.2
190 23:29:47.185302 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 23:29:47.186303 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 23:29:47.186634 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 23:29:47.186858 skipped lava-vland-overlay
194 23:29:47.187113 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 23:29:47.187383 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 23:29:47.187615 skipped lava-multinode-overlay
197 23:29:47.187872 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 23:29:47.188168 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 23:29:47.188441 Loading test definitions
200 23:29:47.188739 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 23:29:47.188974 Using /lava-972963 at stage 0
202 23:29:47.190204 uuid=972963_1.6.2.4.1 testdef=None
203 23:29:47.190520 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 23:29:47.190803 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 23:29:47.192683 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 23:29:47.193507 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 23:29:47.195795 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 23:29:47.196679 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 23:29:47.198885 runner path: /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/0/tests/0_dmesg test_uuid 972963_1.6.2.4.1
212 23:29:47.199471 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 23:29:47.200297 Creating lava-test-runner.conf files
215 23:29:47.200519 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/972963/lava-overlay-dtlb0gxm/lava-972963/0 for stage 0
216 23:29:47.200895 - 0_dmesg
217 23:29:47.201273 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 23:29:47.201572 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 23:29:47.223357 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 23:29:47.223741 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 23:29:47.224069 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 23:29:47.224394 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 23:29:47.224695 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 23:29:47.856538 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 23:29:47.857002 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 23:29:47.857251 extracting modules file /var/lib/lava/dispatcher/tmp/972963/tftp-deploy-8lbzh6g8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/972963/extract-nfsrootfs-c3blvzol
227 23:29:49.213565 extracting modules file /var/lib/lava/dispatcher/tmp/972963/tftp-deploy-8lbzh6g8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/972963/extract-overlay-ramdisk-4it412is/ramdisk
228 23:29:50.618031 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 23:29:50.618528 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
230 23:29:50.618830 [common] Applying overlay to NFS
231 23:29:50.619063 [common] Applying overlay /var/lib/lava/dispatcher/tmp/972963/compress-overlay-w3j_8zmx/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/972963/extract-nfsrootfs-c3blvzol
232 23:29:50.648832 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 23:29:50.649302 start: 1.6.6 prepare-kernel (timeout 00:09:31) [common]
234 23:29:50.649620 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:31) [common]
235 23:29:50.649879 Converting downloaded kernel to a uImage
236 23:29:50.650226 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/972963/tftp-deploy-8lbzh6g8/kernel/Image /var/lib/lava/dispatcher/tmp/972963/tftp-deploy-8lbzh6g8/kernel/uImage
237 23:29:51.123775 output: Image Name:
238 23:29:51.124235 output: Created: Sun Nov 10 23:29:50 2024
239 23:29:51.124484 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 23:29:51.124718 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 23:29:51.124962 output: Load Address: 01080000
242 23:29:51.125192 output: Entry Point: 01080000
243 23:29:51.125412 output:
244 23:29:51.125767 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 23:29:51.126068 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 23:29:51.126376 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 23:29:51.126673 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 23:29:51.126974 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 23:29:51.127255 Building ramdisk /var/lib/lava/dispatcher/tmp/972963/extract-overlay-ramdisk-4it412is/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/972963/extract-overlay-ramdisk-4it412is/ramdisk
250 23:29:53.270594 >> 166829 blocks
251 23:30:01.001726 Adding RAMdisk u-boot header.
252 23:30:01.002343 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/972963/extract-overlay-ramdisk-4it412is/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/972963/extract-overlay-ramdisk-4it412is/ramdisk.cpio.gz.uboot
253 23:30:01.265061 output: Image Name:
254 23:30:01.265466 output: Created: Sun Nov 10 23:30:01 2024
255 23:30:01.265681 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 23:30:01.265887 output: Data Size: 23436103 Bytes = 22886.82 KiB = 22.35 MiB
257 23:30:01.266089 output: Load Address: 00000000
258 23:30:01.266287 output: Entry Point: 00000000
259 23:30:01.266484 output:
260 23:30:01.267198 rename /var/lib/lava/dispatcher/tmp/972963/extract-overlay-ramdisk-4it412is/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/972963/tftp-deploy-8lbzh6g8/ramdisk/ramdisk.cpio.gz.uboot
261 23:30:01.267633 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 23:30:01.267922 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
263 23:30:01.268539 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
264 23:30:01.269080 No LXC device requested
265 23:30:01.269646 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 23:30:01.270211 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
267 23:30:01.270755 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 23:30:01.271210 Checking files for TFTP limit of 4294967296 bytes.
269 23:30:01.274142 end: 1 tftp-deploy (duration 00:00:40) [common]
270 23:30:01.274785 start: 2 uboot-action (timeout 00:05:00) [common]
271 23:30:01.275372 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 23:30:01.275929 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 23:30:01.276530 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 23:30:01.277116 Using kernel file from prepare-kernel: 972963/tftp-deploy-8lbzh6g8/kernel/uImage
275 23:30:01.277812 substitutions:
276 23:30:01.278260 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 23:30:01.278708 - {DTB_ADDR}: 0x01070000
278 23:30:01.279149 - {DTB}: 972963/tftp-deploy-8lbzh6g8/dtb/meson-g12b-a311d-libretech-cc.dtb
279 23:30:01.279591 - {INITRD}: 972963/tftp-deploy-8lbzh6g8/ramdisk/ramdisk.cpio.gz.uboot
280 23:30:01.280061 - {KERNEL_ADDR}: 0x01080000
281 23:30:01.280503 - {KERNEL}: 972963/tftp-deploy-8lbzh6g8/kernel/uImage
282 23:30:01.280940 - {LAVA_MAC}: None
283 23:30:01.281414 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/972963/extract-nfsrootfs-c3blvzol
284 23:30:01.281858 - {NFS_SERVER_IP}: 192.168.6.2
285 23:30:01.282296 - {PRESEED_CONFIG}: None
286 23:30:01.282727 - {PRESEED_LOCAL}: None
287 23:30:01.283153 - {RAMDISK_ADDR}: 0x08000000
288 23:30:01.283578 - {RAMDISK}: 972963/tftp-deploy-8lbzh6g8/ramdisk/ramdisk.cpio.gz.uboot
289 23:30:01.284033 - {ROOT_PART}: None
290 23:30:01.284469 - {ROOT}: None
291 23:30:01.284899 - {SERVER_IP}: 192.168.6.2
292 23:30:01.285329 - {TEE_ADDR}: 0x83000000
293 23:30:01.285753 - {TEE}: None
294 23:30:01.286184 Parsed boot commands:
295 23:30:01.286600 - setenv autoload no
296 23:30:01.287022 - setenv initrd_high 0xffffffff
297 23:30:01.287446 - setenv fdt_high 0xffffffff
298 23:30:01.287868 - dhcp
299 23:30:01.288325 - setenv serverip 192.168.6.2
300 23:30:01.288751 - tftpboot 0x01080000 972963/tftp-deploy-8lbzh6g8/kernel/uImage
301 23:30:01.289179 - tftpboot 0x08000000 972963/tftp-deploy-8lbzh6g8/ramdisk/ramdisk.cpio.gz.uboot
302 23:30:01.289604 - tftpboot 0x01070000 972963/tftp-deploy-8lbzh6g8/dtb/meson-g12b-a311d-libretech-cc.dtb
303 23:30:01.290028 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/972963/extract-nfsrootfs-c3blvzol,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 23:30:01.290466 - bootm 0x01080000 0x08000000 0x01070000
305 23:30:01.291019 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 23:30:01.292699 start: 2.3 connect-device (timeout 00:05:00) [common]
308 23:30:01.293168 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 23:30:01.307723 Setting prompt string to ['lava-test: # ']
310 23:30:01.309392 end: 2.3 connect-device (duration 00:00:00) [common]
311 23:30:01.310046 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 23:30:01.310642 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 23:30:01.311348 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 23:30:01.312652 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 23:30:01.350218 >> OK - accepted request
316 23:30:01.352662 Returned 0 in 0 seconds
317 23:30:01.453884 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 23:30:01.455615 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 23:30:01.456295 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 23:30:01.456874 Setting prompt string to ['Hit any key to stop autoboot']
322 23:30:01.457387 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 23:30:01.459090 Trying 192.168.56.21...
324 23:30:01.459620 Connected to conserv1.
325 23:30:01.460118 Escape character is '^]'.
326 23:30:01.460591
327 23:30:01.461072 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 23:30:01.461538
329 23:30:12.976426 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 23:30:12.977074 bl2_stage_init 0x01
331 23:30:12.977501 bl2_stage_init 0x81
332 23:30:12.981834 hw id: 0x0000 - pwm id 0x01
333 23:30:12.982452 bl2_stage_init 0xc1
334 23:30:12.982919 bl2_stage_init 0x02
335 23:30:12.983343
336 23:30:12.987395 L0:00000000
337 23:30:12.987922 L1:20000703
338 23:30:12.988383 L2:00008067
339 23:30:12.988782 L3:14000000
340 23:30:12.993098 B2:00402000
341 23:30:12.993476 B1:e0f83180
342 23:30:12.993846
343 23:30:12.994178 TE: 58167
344 23:30:12.994405
345 23:30:12.998722 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 23:30:12.999321
347 23:30:12.999776 Board ID = 1
348 23:30:13.004145 Set A53 clk to 24M
349 23:30:13.004630 Set A73 clk to 24M
350 23:30:13.005072 Set clk81 to 24M
351 23:30:13.009848 A53 clk: 1200 MHz
352 23:30:13.010318 A73 clk: 1200 MHz
353 23:30:13.010756 CLK81: 166.6M
354 23:30:13.011190 smccc: 00012abe
355 23:30:13.015429 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 23:30:13.021052 board id: 1
357 23:30:13.026831 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 23:30:13.037404 fw parse done
359 23:30:13.043284 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 23:30:13.086025 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 23:30:13.096833 PIEI prepare done
362 23:30:13.097311 fastboot data load
363 23:30:13.097759 fastboot data verify
364 23:30:13.102603 verify result: 266
365 23:30:13.108116 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 23:30:13.108606 LPDDR4 probe
367 23:30:13.109051 ddr clk to 1584MHz
368 23:30:13.116107 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 23:30:13.153411
370 23:30:13.153956 dmc_version 0001
371 23:30:13.159218 Check phy result
372 23:30:13.165900 INFO : End of CA training
373 23:30:13.166402 INFO : End of initialization
374 23:30:13.171491 INFO : Training has run successfully!
375 23:30:13.171968 Check phy result
376 23:30:13.177064 INFO : End of initialization
377 23:30:13.177536 INFO : End of read enable training
378 23:30:13.182758 INFO : End of fine write leveling
379 23:30:13.188317 INFO : End of Write leveling coarse delay
380 23:30:13.188799 INFO : Training has run successfully!
381 23:30:13.189243 Check phy result
382 23:30:13.193897 INFO : End of initialization
383 23:30:13.194387 INFO : End of read dq deskew training
384 23:30:13.199475 INFO : End of MPR read delay center optimization
385 23:30:13.205072 INFO : End of write delay center optimization
386 23:30:13.210673 INFO : End of read delay center optimization
387 23:30:13.211147 INFO : End of max read latency training
388 23:30:13.216280 INFO : Training has run successfully!
389 23:30:13.216750 1D training succeed
390 23:30:13.225453 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 23:30:13.273122 Check phy result
392 23:30:13.273649 INFO : End of initialization
393 23:30:13.295731 INFO : End of 2D read delay Voltage center optimization
394 23:30:13.315645 INFO : End of 2D read delay Voltage center optimization
395 23:30:13.368002 INFO : End of 2D write delay Voltage center optimization
396 23:30:13.417456 INFO : End of 2D write delay Voltage center optimization
397 23:30:13.422863 INFO : Training has run successfully!
398 23:30:13.423334
399 23:30:13.423780 channel==0
400 23:30:13.428460 RxClkDly_Margin_A0==88 ps 9
401 23:30:13.428931 TxDqDly_Margin_A0==98 ps 10
402 23:30:13.434057 RxClkDly_Margin_A1==88 ps 9
403 23:30:13.434522 TxDqDly_Margin_A1==98 ps 10
404 23:30:13.434968 TrainedVREFDQ_A0==74
405 23:30:13.439665 TrainedVREFDQ_A1==74
406 23:30:13.440172 VrefDac_Margin_A0==24
407 23:30:13.440613 DeviceVref_Margin_A0==40
408 23:30:13.445329 VrefDac_Margin_A1==25
409 23:30:13.445796 DeviceVref_Margin_A1==40
410 23:30:13.446231
411 23:30:13.446668
412 23:30:13.450855 channel==1
413 23:30:13.451321 RxClkDly_Margin_A0==98 ps 10
414 23:30:13.451762 TxDqDly_Margin_A0==98 ps 10
415 23:30:13.456433 RxClkDly_Margin_A1==98 ps 10
416 23:30:13.456902 TxDqDly_Margin_A1==88 ps 9
417 23:30:13.462085 TrainedVREFDQ_A0==77
418 23:30:13.462557 TrainedVREFDQ_A1==77
419 23:30:13.463000 VrefDac_Margin_A0==22
420 23:30:13.467635 DeviceVref_Margin_A0==37
421 23:30:13.468134 VrefDac_Margin_A1==24
422 23:30:13.473318 DeviceVref_Margin_A1==37
423 23:30:13.473778
424 23:30:13.474219 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 23:30:13.478819
426 23:30:13.506910 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 23:30:13.507580 2D training succeed
428 23:30:13.512470 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 23:30:13.518077 auto size-- 65535DDR cs0 size: 2048MB
430 23:30:13.518559 DDR cs1 size: 2048MB
431 23:30:13.523644 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 23:30:13.524163 cs0 DataBus test pass
433 23:30:13.529361 cs1 DataBus test pass
434 23:30:13.529859 cs0 AddrBus test pass
435 23:30:13.530310 cs1 AddrBus test pass
436 23:30:13.530750
437 23:30:13.534862 100bdlr_step_size ps== 420
438 23:30:13.535352 result report
439 23:30:13.540481 boot times 0Enable ddr reg access
440 23:30:13.545176 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 23:30:13.558714 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 23:30:14.133099 0.0;M3 CHK:0;cm4_sp_mode 0
443 23:30:14.133776 MVN_1=0x00000000
444 23:30:14.138593 MVN_2=0x00000000
445 23:30:14.144458 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 23:30:14.144960 OPS=0x10
447 23:30:14.145437 ring efuse init
448 23:30:14.145884 chipver efuse init
449 23:30:14.149997 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 23:30:14.155589 [0.018960 Inits done]
451 23:30:14.156113 secure task start!
452 23:30:14.156567 high task start!
453 23:30:14.160170 low task start!
454 23:30:14.160639 run into bl31
455 23:30:14.166831 NOTICE: BL31: v1.3(release):4fc40b1
456 23:30:14.174624 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 23:30:14.175111 NOTICE: BL31: G12A normal boot!
458 23:30:14.200013 NOTICE: BL31: BL33 decompress pass
459 23:30:14.205652 ERROR: Error initializing runtime service opteed_fast
460 23:30:15.438522
461 23:30:15.438946
462 23:30:15.447029 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 23:30:15.447374
464 23:30:15.447631 Model: Libre Computer AML-A311D-CC Alta
465 23:30:15.655505 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 23:30:15.677798 DRAM: 2 GiB (effective 3.8 GiB)
467 23:30:15.821715 Core: 408 devices, 31 uclasses, devicetree: separate
468 23:30:15.827468 WDT: Not starting watchdog@f0d0
469 23:30:15.859779 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 23:30:15.872250 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 23:30:15.877254 ** Bad device specification mmc 0 **
472 23:30:15.887617 Card did not respond to voltage select! : -110
473 23:30:15.895244 ** Bad device specification mmc 0 **
474 23:30:15.895808 Couldn't find partition mmc 0
475 23:30:15.903642 Card did not respond to voltage select! : -110
476 23:30:15.909111 ** Bad device specification mmc 0 **
477 23:30:15.909601 Couldn't find partition mmc 0
478 23:30:15.914118 Error: could not access storage.
479 23:30:17.176552 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 23:30:17.177237 bl2_stage_init 0x01
481 23:30:17.177719 bl2_stage_init 0x81
482 23:30:17.182093 hw id: 0x0000 - pwm id 0x01
483 23:30:17.182590 bl2_stage_init 0xc1
484 23:30:17.183051 bl2_stage_init 0x02
485 23:30:17.183501
486 23:30:17.187731 L0:00000000
487 23:30:17.188257 L1:20000703
488 23:30:17.188718 L2:00008067
489 23:30:17.189166 L3:14000000
490 23:30:17.190474 B2:00402000
491 23:30:17.190954 B1:e0f83180
492 23:30:17.191402
493 23:30:17.191847 TE: 58124
494 23:30:17.192347
495 23:30:17.201726 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 23:30:17.202250
497 23:30:17.202710 Board ID = 1
498 23:30:17.203158 Set A53 clk to 24M
499 23:30:17.203602 Set A73 clk to 24M
500 23:30:17.207206 Set clk81 to 24M
501 23:30:17.207703 A53 clk: 1200 MHz
502 23:30:17.208200 A73 clk: 1200 MHz
503 23:30:17.212863 CLK81: 166.6M
504 23:30:17.213370 smccc: 00012a92
505 23:30:17.218480 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 23:30:17.218969 board id: 1
507 23:30:17.224030 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 23:30:17.237811 fw parse done
509 23:30:17.243821 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 23:30:17.286410 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 23:30:17.297345 PIEI prepare done
512 23:30:17.297842 fastboot data load
513 23:30:17.298301 fastboot data verify
514 23:30:17.303090 verify result: 266
515 23:30:17.308656 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 23:30:17.309220 LPDDR4 probe
517 23:30:17.309698 ddr clk to 1584MHz
518 23:30:17.316569 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 23:30:17.353835
520 23:30:17.354376 dmc_version 0001
521 23:30:17.360501 Check phy result
522 23:30:17.366376 INFO : End of CA training
523 23:30:17.366949 INFO : End of initialization
524 23:30:17.372043 INFO : Training has run successfully!
525 23:30:17.372588 Check phy result
526 23:30:17.377623 INFO : End of initialization
527 23:30:17.378150 INFO : End of read enable training
528 23:30:17.380902 INFO : End of fine write leveling
529 23:30:17.386389 INFO : End of Write leveling coarse delay
530 23:30:17.392070 INFO : Training has run successfully!
531 23:30:17.392658 Check phy result
532 23:30:17.393134 INFO : End of initialization
533 23:30:17.397632 INFO : End of read dq deskew training
534 23:30:17.403425 INFO : End of MPR read delay center optimization
535 23:30:17.404007 INFO : End of write delay center optimization
536 23:30:17.408982 INFO : End of read delay center optimization
537 23:30:17.416551 INFO : End of max read latency training
538 23:30:17.417207 INFO : Training has run successfully!
539 23:30:17.420100 1D training succeed
540 23:30:17.426036 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 23:30:17.473533 Check phy result
542 23:30:17.474070 INFO : End of initialization
543 23:30:17.495249 INFO : End of 2D read delay Voltage center optimization
544 23:30:17.515264 INFO : End of 2D read delay Voltage center optimization
545 23:30:17.567306 INFO : End of 2D write delay Voltage center optimization
546 23:30:17.616452 INFO : End of 2D write delay Voltage center optimization
547 23:30:17.621951 INFO : Training has run successfully!
548 23:30:17.622451
549 23:30:17.622938 channel==0
550 23:30:17.627649 RxClkDly_Margin_A0==88 ps 9
551 23:30:17.628176 TxDqDly_Margin_A0==98 ps 10
552 23:30:17.630872 RxClkDly_Margin_A1==88 ps 9
553 23:30:17.631353 TxDqDly_Margin_A1==98 ps 10
554 23:30:17.636494 TrainedVREFDQ_A0==74
555 23:30:17.636991 TrainedVREFDQ_A1==74
556 23:30:17.637451 VrefDac_Margin_A0==25
557 23:30:17.642116 DeviceVref_Margin_A0==40
558 23:30:17.642598 VrefDac_Margin_A1==26
559 23:30:17.647697 DeviceVref_Margin_A1==40
560 23:30:17.648204
561 23:30:17.648659
562 23:30:17.649108 channel==1
563 23:30:17.649549 RxClkDly_Margin_A0==98 ps 10
564 23:30:17.653258 TxDqDly_Margin_A0==98 ps 10
565 23:30:17.653750 RxClkDly_Margin_A1==88 ps 9
566 23:30:17.658880 TxDqDly_Margin_A1==98 ps 10
567 23:30:17.659353 TrainedVREFDQ_A0==76
568 23:30:17.659809 TrainedVREFDQ_A1==77
569 23:30:17.664461 VrefDac_Margin_A0==22
570 23:30:17.664933 DeviceVref_Margin_A0==38
571 23:30:17.670102 VrefDac_Margin_A1==24
572 23:30:17.670585 DeviceVref_Margin_A1==37
573 23:30:17.671032
574 23:30:17.675709 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 23:30:17.676259
576 23:30:17.703708 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000016 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
577 23:30:17.709302 2D training succeed
578 23:30:17.714886 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 23:30:17.715387 auto size-- 65535DDR cs0 size: 2048MB
580 23:30:17.720498 DDR cs1 size: 2048MB
581 23:30:17.720981 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 23:30:17.726057 cs0 DataBus test pass
583 23:30:17.726539 cs1 DataBus test pass
584 23:30:17.726999 cs0 AddrBus test pass
585 23:30:17.731684 cs1 AddrBus test pass
586 23:30:17.732221
587 23:30:17.732696 100bdlr_step_size ps== 420
588 23:30:17.733167 result report
589 23:30:17.737300 boot times 0Enable ddr reg access
590 23:30:17.745024 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 23:30:17.757548 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 23:30:18.330560 0.0;M3 CHK:0;cm4_sp_mode 0
593 23:30:18.330990 MVN_1=0x00000000
594 23:30:18.336253 MVN_2=0x00000000
595 23:30:18.342023 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 23:30:18.342391 OPS=0x10
597 23:30:18.342616 ring efuse init
598 23:30:18.342849 chipver efuse init
599 23:30:18.347415 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 23:30:18.353206 [0.018961 Inits done]
601 23:30:18.353712 secure task start!
602 23:30:18.354120 high task start!
603 23:30:18.357665 low task start!
604 23:30:18.357954 run into bl31
605 23:30:18.364304 NOTICE: BL31: v1.3(release):4fc40b1
606 23:30:18.372283 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 23:30:18.372808 NOTICE: BL31: G12A normal boot!
608 23:30:18.397483 NOTICE: BL31: BL33 decompress pass
609 23:30:18.403204 ERROR: Error initializing runtime service opteed_fast
610 23:30:19.636150
611 23:30:19.636544
612 23:30:19.644430 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 23:30:19.644686
614 23:30:19.644909 Model: Libre Computer AML-A311D-CC Alta
615 23:30:19.852837 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 23:30:19.876257 DRAM: 2 GiB (effective 3.8 GiB)
617 23:30:20.019131 Core: 408 devices, 31 uclasses, devicetree: separate
618 23:30:20.025136 WDT: Not starting watchdog@f0d0
619 23:30:20.057360 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 23:30:20.069816 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 23:30:20.074839 ** Bad device specification mmc 0 **
622 23:30:20.085108 Card did not respond to voltage select! : -110
623 23:30:20.092829 ** Bad device specification mmc 0 **
624 23:30:20.093319 Couldn't find partition mmc 0
625 23:30:20.101094 Card did not respond to voltage select! : -110
626 23:30:20.106604 ** Bad device specification mmc 0 **
627 23:30:20.107089 Couldn't find partition mmc 0
628 23:30:20.111265 Error: could not access storage.
629 23:30:20.454296 Net: eth0: ethernet@ff3f0000
630 23:30:20.454935 starting USB...
631 23:30:20.705974 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 23:30:20.706618 Starting the controller
633 23:30:20.712989 USB XHCI 1.10
634 23:30:22.426813 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 23:30:22.427501 bl2_stage_init 0x01
636 23:30:22.428024 bl2_stage_init 0x81
637 23:30:22.432349 hw id: 0x0000 - pwm id 0x01
638 23:30:22.432855 bl2_stage_init 0xc1
639 23:30:22.433318 bl2_stage_init 0x02
640 23:30:22.433772
641 23:30:22.438028 L0:00000000
642 23:30:22.438523 L1:20000703
643 23:30:22.438977 L2:00008067
644 23:30:22.439432 L3:14000000
645 23:30:22.440853 B2:00402000
646 23:30:22.441343 B1:e0f83180
647 23:30:22.441797
648 23:30:22.442251 TE: 58159
649 23:30:22.442702
650 23:30:22.452016 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 23:30:22.452528
652 23:30:22.452988 Board ID = 1
653 23:30:22.453438 Set A53 clk to 24M
654 23:30:22.453884 Set A73 clk to 24M
655 23:30:22.457469 Set clk81 to 24M
656 23:30:22.457966 A53 clk: 1200 MHz
657 23:30:22.458418 A73 clk: 1200 MHz
658 23:30:22.461100 CLK81: 166.6M
659 23:30:22.461590 smccc: 00012ab5
660 23:30:22.466723 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 23:30:22.472362 board id: 1
662 23:30:22.477366 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 23:30:22.488093 fw parse done
664 23:30:22.494071 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 23:30:22.535739 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 23:30:22.547731 PIEI prepare done
667 23:30:22.548293 fastboot data load
668 23:30:22.548766 fastboot data verify
669 23:30:22.553176 verify result: 266
670 23:30:22.558794 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 23:30:22.559316 LPDDR4 probe
672 23:30:22.559783 ddr clk to 1584MHz
673 23:30:22.566833 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 23:30:22.604030
675 23:30:22.604576 dmc_version 0001
676 23:30:22.610810 Check phy result
677 23:30:22.616564 INFO : End of CA training
678 23:30:22.617068 INFO : End of initialization
679 23:30:22.622143 INFO : Training has run successfully!
680 23:30:22.622646 Check phy result
681 23:30:22.627769 INFO : End of initialization
682 23:30:22.628310 INFO : End of read enable training
683 23:30:22.633415 INFO : End of fine write leveling
684 23:30:22.639008 INFO : End of Write leveling coarse delay
685 23:30:22.639523 INFO : Training has run successfully!
686 23:30:22.640018 Check phy result
687 23:30:22.644567 INFO : End of initialization
688 23:30:22.645074 INFO : End of read dq deskew training
689 23:30:22.650165 INFO : End of MPR read delay center optimization
690 23:30:22.655708 INFO : End of write delay center optimization
691 23:30:22.661341 INFO : End of read delay center optimization
692 23:30:22.661847 INFO : End of max read latency training
693 23:30:22.666951 INFO : Training has run successfully!
694 23:30:22.667456 1D training succeed
695 23:30:22.676208 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 23:30:22.723852 Check phy result
697 23:30:22.724409 INFO : End of initialization
698 23:30:22.745524 INFO : End of 2D read delay Voltage center optimization
699 23:30:22.765857 INFO : End of 2D read delay Voltage center optimization
700 23:30:22.817079 INFO : End of 2D write delay Voltage center optimization
701 23:30:22.867340 INFO : End of 2D write delay Voltage center optimization
702 23:30:22.872909 INFO : Training has run successfully!
703 23:30:22.873423
704 23:30:22.873902 channel==0
705 23:30:22.878367 RxClkDly_Margin_A0==88 ps 9
706 23:30:22.878873 TxDqDly_Margin_A0==98 ps 10
707 23:30:22.884057 RxClkDly_Margin_A1==88 ps 9
708 23:30:22.884569 TxDqDly_Margin_A1==98 ps 10
709 23:30:22.885031 TrainedVREFDQ_A0==74
710 23:30:22.889529 TrainedVREFDQ_A1==75
711 23:30:22.890037 VrefDac_Margin_A0==24
712 23:30:22.890493 DeviceVref_Margin_A0==40
713 23:30:22.895291 VrefDac_Margin_A1==25
714 23:30:22.895795 DeviceVref_Margin_A1==39
715 23:30:22.896283
716 23:30:22.896738
717 23:30:22.900812 channel==1
718 23:30:22.901313 RxClkDly_Margin_A0==98 ps 10
719 23:30:22.901772 TxDqDly_Margin_A0==88 ps 9
720 23:30:22.906337 RxClkDly_Margin_A1==88 ps 9
721 23:30:22.906842 TxDqDly_Margin_A1==88 ps 9
722 23:30:22.912011 TrainedVREFDQ_A0==76
723 23:30:22.912524 TrainedVREFDQ_A1==77
724 23:30:22.912984 VrefDac_Margin_A0==22
725 23:30:22.917602 DeviceVref_Margin_A0==38
726 23:30:22.918103 VrefDac_Margin_A1==24
727 23:30:22.923271 DeviceVref_Margin_A1==37
728 23:30:22.923775
729 23:30:22.924270 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 23:30:22.924722
731 23:30:22.956787 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
732 23:30:22.957349 2D training succeed
733 23:30:22.962415 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 23:30:22.967836 auto size-- 65535DDR cs0 size: 2048MB
735 23:30:22.968366 DDR cs1 size: 2048MB
736 23:30:22.973481 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 23:30:22.973988 cs0 DataBus test pass
738 23:30:22.979018 cs1 DataBus test pass
739 23:30:22.979515 cs0 AddrBus test pass
740 23:30:22.979968 cs1 AddrBus test pass
741 23:30:22.980454
742 23:30:22.984706 100bdlr_step_size ps== 420
743 23:30:22.985219 result report
744 23:30:22.990246 boot times 0Enable ddr reg access
745 23:30:22.995527 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 23:30:23.008945 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 23:30:23.582575 0.0;M3 CHK:0;cm4_sp_mode 0
748 23:30:23.583213 MVN_1=0x00000000
749 23:30:23.588082 MVN_2=0x00000000
750 23:30:23.593812 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 23:30:23.594370 OPS=0x10
752 23:30:23.594817 ring efuse init
753 23:30:23.595251 chipver efuse init
754 23:30:23.599393 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 23:30:23.604963 [0.018961 Inits done]
756 23:30:23.605446 secure task start!
757 23:30:23.605884 high task start!
758 23:30:23.609551 low task start!
759 23:30:23.610023 run into bl31
760 23:30:23.616222 NOTICE: BL31: v1.3(release):4fc40b1
761 23:30:23.623031 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 23:30:23.623512 NOTICE: BL31: G12A normal boot!
763 23:30:23.649441 NOTICE: BL31: BL33 decompress pass
764 23:30:23.655093 ERROR: Error initializing runtime service opteed_fast
765 23:30:24.888059
766 23:30:24.888695
767 23:30:24.896395 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 23:30:24.896889
769 23:30:24.897352 Model: Libre Computer AML-A311D-CC Alta
770 23:30:25.104829 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 23:30:25.128206 DRAM: 2 GiB (effective 3.8 GiB)
772 23:30:25.271229 Core: 408 devices, 31 uclasses, devicetree: separate
773 23:30:25.277072 WDT: Not starting watchdog@f0d0
774 23:30:25.309349 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 23:30:25.321793 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 23:30:25.326741 ** Bad device specification mmc 0 **
777 23:30:25.337070 Card did not respond to voltage select! : -110
778 23:30:25.344768 ** Bad device specification mmc 0 **
779 23:30:25.345258 Couldn't find partition mmc 0
780 23:30:25.353078 Card did not respond to voltage select! : -110
781 23:30:25.358589 ** Bad device specification mmc 0 **
782 23:30:25.359071 Couldn't find partition mmc 0
783 23:30:25.363642 Error: could not access storage.
784 23:30:25.706232 Net: eth0: ethernet@ff3f0000
785 23:30:25.706850 starting USB...
786 23:30:25.957979 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 23:30:25.958547 Starting the controller
788 23:30:25.964893 USB XHCI 1.10
789 23:30:28.128333 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 23:30:28.128971 bl2_stage_init 0x01
791 23:30:28.129410 bl2_stage_init 0x81
792 23:30:28.133958 hw id: 0x0000 - pwm id 0x01
793 23:30:28.134460 bl2_stage_init 0xc1
794 23:30:28.134884 bl2_stage_init 0x02
795 23:30:28.135297
796 23:30:28.139575 L0:00000000
797 23:30:28.140099 L1:20000703
798 23:30:28.140523 L2:00008067
799 23:30:28.140930 L3:14000000
800 23:30:28.142504 B2:00402000
801 23:30:28.142980 B1:e0f83180
802 23:30:28.143394
803 23:30:28.143807 TE: 58167
804 23:30:28.144263
805 23:30:28.153495 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 23:30:28.154060
807 23:30:28.154495 Board ID = 1
808 23:30:28.154913 Set A53 clk to 24M
809 23:30:28.155320 Set A73 clk to 24M
810 23:30:28.159144 Set clk81 to 24M
811 23:30:28.159632 A53 clk: 1200 MHz
812 23:30:28.160089 A73 clk: 1200 MHz
813 23:30:28.162656 CLK81: 166.6M
814 23:30:28.163133 smccc: 00012abe
815 23:30:28.168214 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 23:30:28.173757 board id: 1
817 23:30:28.178833 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 23:30:28.189539 fw parse done
819 23:30:28.195498 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 23:30:28.238104 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 23:30:28.249088 PIEI prepare done
822 23:30:28.249587 fastboot data load
823 23:30:28.250010 fastboot data verify
824 23:30:28.254662 verify result: 266
825 23:30:28.260283 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 23:30:28.260789 LPDDR4 probe
827 23:30:28.261209 ddr clk to 1584MHz
828 23:30:28.267346 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 23:30:28.305672
830 23:30:28.306233 dmc_version 0001
831 23:30:28.312284 Check phy result
832 23:30:28.318005 INFO : End of CA training
833 23:30:28.318326 INFO : End of initialization
834 23:30:28.323606 INFO : Training has run successfully!
835 23:30:28.323975 Check phy result
836 23:30:28.329139 INFO : End of initialization
837 23:30:28.329452 INFO : End of read enable training
838 23:30:28.332447 INFO : End of fine write leveling
839 23:30:28.337976 INFO : End of Write leveling coarse delay
840 23:30:28.343581 INFO : Training has run successfully!
841 23:30:28.344054 Check phy result
842 23:30:28.344323 INFO : End of initialization
843 23:30:28.349155 INFO : End of read dq deskew training
844 23:30:28.354786 INFO : End of MPR read delay center optimization
845 23:30:28.355094 INFO : End of write delay center optimization
846 23:30:28.360410 INFO : End of read delay center optimization
847 23:30:28.365971 INFO : End of max read latency training
848 23:30:28.366419 INFO : Training has run successfully!
849 23:30:28.371562 1D training succeed
850 23:30:28.377581 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 23:30:28.425165 Check phy result
852 23:30:28.425584 INFO : End of initialization
853 23:30:28.445983 INFO : End of 2D read delay Voltage center optimization
854 23:30:28.467202 INFO : End of 2D read delay Voltage center optimization
855 23:30:28.519233 INFO : End of 2D write delay Voltage center optimization
856 23:30:28.568687 INFO : End of 2D write delay Voltage center optimization
857 23:30:28.574269 INFO : Training has run successfully!
858 23:30:28.574655
859 23:30:28.574895 channel==0
860 23:30:28.579801 RxClkDly_Margin_A0==88 ps 9
861 23:30:28.580196 TxDqDly_Margin_A0==98 ps 10
862 23:30:28.583117 RxClkDly_Margin_A1==88 ps 9
863 23:30:28.583456 TxDqDly_Margin_A1==98 ps 10
864 23:30:28.588733 TrainedVREFDQ_A0==74
865 23:30:28.589099 TrainedVREFDQ_A1==74
866 23:30:28.589340 VrefDac_Margin_A0==25
867 23:30:28.594244 DeviceVref_Margin_A0==40
868 23:30:28.594613 VrefDac_Margin_A1==25
869 23:30:28.599925 DeviceVref_Margin_A1==40
870 23:30:28.600320
871 23:30:28.600552
872 23:30:28.600775 channel==1
873 23:30:28.600997 RxClkDly_Margin_A0==98 ps 10
874 23:30:28.603351 TxDqDly_Margin_A0==98 ps 10
875 23:30:28.609004 RxClkDly_Margin_A1==98 ps 10
876 23:30:28.609370 TxDqDly_Margin_A1==88 ps 9
877 23:30:28.609589 TrainedVREFDQ_A0==77
878 23:30:28.614585 TrainedVREFDQ_A1==77
879 23:30:28.614951 VrefDac_Margin_A0==22
880 23:30:28.620089 DeviceVref_Margin_A0==37
881 23:30:28.620447 VrefDac_Margin_A1==22
882 23:30:28.620686 DeviceVref_Margin_A1==37
883 23:30:28.620921
884 23:30:28.629057 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 23:30:28.629441
886 23:30:28.657078 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
887 23:30:28.657484 2D training succeed
888 23:30:28.668204 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 23:30:28.668533 auto size-- 65535DDR cs0 size: 2048MB
890 23:30:28.668765 DDR cs1 size: 2048MB
891 23:30:28.673871 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 23:30:28.674366 cs0 DataBus test pass
893 23:30:28.679418 cs1 DataBus test pass
894 23:30:28.679889 cs0 AddrBus test pass
895 23:30:28.685111 cs1 AddrBus test pass
896 23:30:28.685761
897 23:30:28.686170 100bdlr_step_size ps== 420
898 23:30:28.686574 result report
899 23:30:28.690641 boot times 0Enable ddr reg access
900 23:30:28.697204 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 23:30:28.710582 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 23:30:29.284438 0.0;M3 CHK:0;cm4_sp_mode 0
903 23:30:29.285079 MVN_1=0x00000000
904 23:30:29.289877 MVN_2=0x00000000
905 23:30:29.295613 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 23:30:29.296152 OPS=0x10
907 23:30:29.296584 ring efuse init
908 23:30:29.296997 chipver efuse init
909 23:30:29.303760 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 23:30:29.304300 [0.018961 Inits done]
911 23:30:29.311385 secure task start!
912 23:30:29.311867 high task start!
913 23:30:29.312323 low task start!
914 23:30:29.312736 run into bl31
915 23:30:29.318045 NOTICE: BL31: v1.3(release):4fc40b1
916 23:30:29.325876 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 23:30:29.326369 NOTICE: BL31: G12A normal boot!
918 23:30:29.351383 NOTICE: BL31: BL33 decompress pass
919 23:30:29.356982 ERROR: Error initializing runtime service opteed_fast
920 23:30:30.589745
921 23:30:30.590166
922 23:30:30.597421 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 23:30:30.597753
924 23:30:30.597983 Model: Libre Computer AML-A311D-CC Alta
925 23:30:30.806770 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 23:30:30.830072 DRAM: 2 GiB (effective 3.8 GiB)
927 23:30:30.973110 Core: 408 devices, 31 uclasses, devicetree: separate
928 23:30:30.978939 WDT: Not starting watchdog@f0d0
929 23:30:31.011290 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 23:30:31.023573 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 23:30:31.028646 ** Bad device specification mmc 0 **
932 23:30:31.038966 Card did not respond to voltage select! : -110
933 23:30:31.046650 ** Bad device specification mmc 0 **
934 23:30:31.047136 Couldn't find partition mmc 0
935 23:30:31.054972 Card did not respond to voltage select! : -110
936 23:30:31.060505 ** Bad device specification mmc 0 **
937 23:30:31.061010 Couldn't find partition mmc 0
938 23:30:31.065398 Error: could not access storage.
939 23:30:31.408015 Net: eth0: ethernet@ff3f0000
940 23:30:31.408650 starting USB...
941 23:30:31.659754 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 23:30:31.660428 Starting the controller
943 23:30:31.666673 USB XHCI 1.10
944 23:30:33.528216 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
945 23:30:33.528679 bl2_stage_init 0x81
946 23:30:33.533670 hw id: 0x0000 - pwm id 0x01
947 23:30:33.534138 bl2_stage_init 0xc1
948 23:30:33.534502 bl2_stage_init 0x02
949 23:30:33.534853
950 23:30:33.539277 L0:00000000
951 23:30:33.539608 L1:20000703
952 23:30:33.539838 L2:00008067
953 23:30:33.540101 L3:14000000
954 23:30:33.540325 B2:00402000
955 23:30:33.542050 B1:e0f83180
956 23:30:33.542464
957 23:30:33.542814 TE: 58150
958 23:30:33.543160
959 23:30:33.553168 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
960 23:30:33.553666
961 23:30:33.554009 Board ID = 1
962 23:30:33.554338 Set A53 clk to 24M
963 23:30:33.554664 Set A73 clk to 24M
964 23:30:33.558756 Set clk81 to 24M
965 23:30:33.559174 A53 clk: 1200 MHz
966 23:30:33.559425 A73 clk: 1200 MHz
967 23:30:33.564336 CLK81: 166.6M
968 23:30:33.564645 smccc: 00012aac
969 23:30:33.570068 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
970 23:30:33.570435 board id: 1
971 23:30:33.575587 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
972 23:30:33.589271 fw parse done
973 23:30:33.595205 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
974 23:30:33.637937 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
975 23:30:33.648811 PIEI prepare done
976 23:30:33.649294 fastboot data load
977 23:30:33.649696 fastboot data verify
978 23:30:33.654639 verify result: 266
979 23:30:33.660261 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
980 23:30:33.660738 LPDDR4 probe
981 23:30:33.661135 ddr clk to 1584MHz
982 23:30:33.667537 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
983 23:30:33.705491
984 23:30:33.706007 dmc_version 0001
985 23:30:33.712329 Check phy result
986 23:30:33.718130 INFO : End of CA training
987 23:30:33.718590 INFO : End of initialization
988 23:30:33.723617 INFO : Training has run successfully!
989 23:30:33.724146 Check phy result
990 23:30:33.729405 INFO : End of initialization
991 23:30:33.729882 INFO : End of read enable training
992 23:30:33.734916 INFO : End of fine write leveling
993 23:30:33.740571 INFO : End of Write leveling coarse delay
994 23:30:33.741042 INFO : Training has run successfully!
995 23:30:33.741459 Check phy result
996 23:30:33.746013 INFO : End of initialization
997 23:30:33.746479 INFO : End of read dq deskew training
998 23:30:33.751676 INFO : End of MPR read delay center optimization
999 23:30:33.757325 INFO : End of write delay center optimization
1000 23:30:33.762849 INFO : End of read delay center optimization
1001 23:30:33.763319 INFO : End of max read latency training
1002 23:30:33.768504 INFO : Training has run successfully!
1003 23:30:33.768979 1D training succeed
1004 23:30:33.777542 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 23:30:33.825254 Check phy result
1006 23:30:33.825788 INFO : End of initialization
1007 23:30:33.846865 INFO : End of 2D read delay Voltage center optimization
1008 23:30:33.867172 INFO : End of 2D read delay Voltage center optimization
1009 23:30:33.919128 INFO : End of 2D write delay Voltage center optimization
1010 23:30:33.968475 INFO : End of 2D write delay Voltage center optimization
1011 23:30:33.974005 INFO : Training has run successfully!
1012 23:30:33.974348
1013 23:30:33.974575 channel==0
1014 23:30:33.979629 RxClkDly_Margin_A0==88 ps 9
1015 23:30:33.979946 TxDqDly_Margin_A0==98 ps 10
1016 23:30:33.982931 RxClkDly_Margin_A1==88 ps 9
1017 23:30:33.983230 TxDqDly_Margin_A1==98 ps 10
1018 23:30:33.988474 TrainedVREFDQ_A0==74
1019 23:30:33.988920 TrainedVREFDQ_A1==74
1020 23:30:33.993987 VrefDac_Margin_A0==25
1021 23:30:33.994294 DeviceVref_Margin_A0==40
1022 23:30:33.994513 VrefDac_Margin_A1==25
1023 23:30:33.999641 DeviceVref_Margin_A1==40
1024 23:30:34.000100
1025 23:30:34.000631
1026 23:30:34.001061 channel==1
1027 23:30:34.001479 RxClkDly_Margin_A0==98 ps 10
1028 23:30:34.005250 TxDqDly_Margin_A0==98 ps 10
1029 23:30:34.005714 RxClkDly_Margin_A1==88 ps 9
1030 23:30:34.010867 TxDqDly_Margin_A1==88 ps 9
1031 23:30:34.011328 TrainedVREFDQ_A0==77
1032 23:30:34.011751 TrainedVREFDQ_A1==77
1033 23:30:34.016446 VrefDac_Margin_A0==22
1034 23:30:34.016995 DeviceVref_Margin_A0==37
1035 23:30:34.022022 VrefDac_Margin_A1==24
1036 23:30:34.022573 DeviceVref_Margin_A1==37
1037 23:30:34.023003
1038 23:30:34.027722 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1039 23:30:34.028311
1040 23:30:34.055700 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1041 23:30:34.061292 2D training succeed
1042 23:30:34.066893 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1043 23:30:34.067389 auto size-- 65535DDR cs0 size: 2048MB
1044 23:30:34.072349 DDR cs1 size: 2048MB
1045 23:30:34.072895 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1046 23:30:34.077922 cs0 DataBus test pass
1047 23:30:34.078408 cs1 DataBus test pass
1048 23:30:34.078840 cs0 AddrBus test pass
1049 23:30:34.083544 cs1 AddrBus test pass
1050 23:30:34.084118
1051 23:30:34.084565 100bdlr_step_size ps== 420
1052 23:30:34.084993 result report
1053 23:30:34.089155 boot times 0Enable ddr reg access
1054 23:30:34.097514 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1055 23:30:34.110443 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1056 23:30:34.684167 0.0;M3 CHK:0;cm4_sp_mode 0
1057 23:30:34.684827 MVN_1=0x00000000
1058 23:30:34.689583 MVN_2=0x00000000
1059 23:30:34.695358 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1060 23:30:34.695933 OPS=0x10
1061 23:30:34.696413 ring efuse init
1062 23:30:34.696840 chipver efuse init
1063 23:30:34.700947 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1064 23:30:34.706478 [0.018961 Inits done]
1065 23:30:34.706977 secure task start!
1066 23:30:34.707401 high task start!
1067 23:30:34.711053 low task start!
1068 23:30:34.711521 run into bl31
1069 23:30:34.717727 NOTICE: BL31: v1.3(release):4fc40b1
1070 23:30:34.725761 NOTICE: BL31: Built : 15:58:17, May 22 2019
1071 23:30:34.726238 NOTICE: BL31: G12A normal boot!
1072 23:30:34.750974 NOTICE: BL31: BL33 decompress pass
1073 23:30:34.755769 ERROR: Error initializing runtime service opteed_fast
1074 23:30:35.989534
1075 23:30:35.989936
1076 23:30:35.997873 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1077 23:30:35.998165
1078 23:30:35.998383 Model: Libre Computer AML-A311D-CC Alta
1079 23:30:36.206355 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1080 23:30:36.229728 DRAM: 2 GiB (effective 3.8 GiB)
1081 23:30:36.372783 Core: 408 devices, 31 uclasses, devicetree: separate
1082 23:30:36.378508 WDT: Not starting watchdog@f0d0
1083 23:30:36.411004 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1084 23:30:36.423499 Loading Environment from FAT... Card did not respond to voltage select! : -110
1085 23:30:36.428432 ** Bad device specification mmc 0 **
1086 23:30:36.438776 Card did not respond to voltage select! : -110
1087 23:30:36.446433 ** Bad device specification mmc 0 **
1088 23:30:36.446928 Couldn't find partition mmc 0
1089 23:30:36.454736 Card did not respond to voltage select! : -110
1090 23:30:36.460322 ** Bad device specification mmc 0 **
1091 23:30:36.460809 Couldn't find partition mmc 0
1092 23:30:36.465373 Error: could not access storage.
1093 23:30:36.808771 Net: eth0: ethernet@ff3f0000
1094 23:30:36.809367 starting USB...
1095 23:30:37.060702 Bus usb@ff500000: Register 3000140 NbrPorts 3
1096 23:30:37.061295 Starting the controller
1097 23:30:37.067590 USB XHCI 1.10
1098 23:30:38.621491 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1099 23:30:38.629941 scanning usb for storage devices... 0 Storage Device(s) found
1101 23:30:38.681580 Hit any key to stop autoboot: 1
1102 23:30:38.682383 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1103 23:30:38.683041 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1104 23:30:38.683511 Setting prompt string to ['=>']
1105 23:30:38.684026 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1106 23:30:38.697268 0
1107 23:30:38.698137 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1108 23:30:38.698624 Sending with 10 millisecond of delay
1110 23:30:39.833355 => setenv autoload no
1111 23:30:39.844172 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1112 23:30:39.849067 setenv autoload no
1113 23:30:39.849834 Sending with 10 millisecond of delay
1115 23:30:41.647464 => setenv initrd_high 0xffffffff
1116 23:30:41.658050 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1117 23:30:41.658681 setenv initrd_high 0xffffffff
1118 23:30:41.659223 Sending with 10 millisecond of delay
1120 23:30:43.276490 => setenv fdt_high 0xffffffff
1121 23:30:43.287801 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1122 23:30:43.289103 setenv fdt_high 0xffffffff
1123 23:30:43.290206 Sending with 10 millisecond of delay
1125 23:30:43.582820 => dhcp
1126 23:30:43.593896 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1127 23:30:43.594519 dhcp
1128 23:30:43.594795 Speed: 1000, full duplex
1129 23:30:43.595018 BOOTP broadcast 1
1130 23:30:43.597402 DHCP client bound to address 192.168.6.27 (4 ms)
1131 23:30:43.598422 Sending with 10 millisecond of delay
1133 23:30:45.276203 => setenv serverip 192.168.6.2
1134 23:30:45.287151 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1135 23:30:45.288474 setenv serverip 192.168.6.2
1136 23:30:45.289440 Sending with 10 millisecond of delay
1138 23:30:49.028838 => tftpboot 0x01080000 972963/tftp-deploy-8lbzh6g8/kernel/uImage
1139 23:30:49.039893 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1140 23:30:49.041045 tftpboot 0x01080000 972963/tftp-deploy-8lbzh6g8/kernel/uImage
1141 23:30:49.041668 Speed: 1000, full duplex
1142 23:30:49.042225 Using ethernet@ff3f0000 device
1143 23:30:49.042869 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1144 23:30:49.048026 Filename '972963/tftp-deploy-8lbzh6g8/kernel/uImage'.
1145 23:30:49.051796 Load address: 0x1080000
1146 23:30:52.336057 Loading: *################################################## 43.6 MiB
1147 23:30:52.336725 13.3 MiB/s
1148 23:30:52.337211 done
1149 23:30:52.340058 Bytes transferred = 45713984 (2b98a40 hex)
1150 23:30:52.340897 Sending with 10 millisecond of delay
1152 23:30:57.029491 => tftpboot 0x08000000 972963/tftp-deploy-8lbzh6g8/ramdisk/ramdisk.cpio.gz.uboot
1153 23:30:57.040341 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1154 23:30:57.041209 tftpboot 0x08000000 972963/tftp-deploy-8lbzh6g8/ramdisk/ramdisk.cpio.gz.uboot
1155 23:30:57.041714 Speed: 1000, full duplex
1156 23:30:57.042183 Using ethernet@ff3f0000 device
1157 23:30:57.043183 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1158 23:30:57.055040 Filename '972963/tftp-deploy-8lbzh6g8/ramdisk/ramdisk.cpio.gz.uboot'.
1159 23:30:57.055634 Load address: 0x8000000
1160 23:31:03.794759 Loading: *########T ######################################### UDP wrong checksum 00000005 0000bb52
1161 23:31:08.795310 T UDP wrong checksum 00000005 0000bb52
1162 23:31:12.266184 UDP wrong checksum 000000ff 00000bc5
1163 23:31:12.327459 UDP wrong checksum 000000ff 00009cb7
1164 23:31:15.417889 T UDP wrong checksum 000000ff 0000353e
1165 23:31:15.445170 UDP wrong checksum 000000ff 0000cc30
1166 23:31:18.798756 T UDP wrong checksum 00000005 0000bb52
1167 23:31:38.800034 T T T UDP wrong checksum 00000005 0000bb52
1168 23:31:44.367437 T T UDP wrong checksum 000000ff 0000f858
1169 23:31:44.424316 UDP wrong checksum 000000ff 0000924b
1170 23:31:48.627452 UDP wrong checksum 000000ff 00006ca5
1171 23:31:48.670277 UDP wrong checksum 000000ff 0000f797
1172 23:31:53.806689 T
1173 23:31:53.807366 Retry count exceeded; starting again
1175 23:31:53.808910 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1178 23:31:53.810898 end: 2.4 uboot-commands (duration 00:01:53) [common]
1180 23:31:53.812486 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1182 23:31:53.813629 end: 2 uboot-action (duration 00:01:53) [common]
1184 23:31:53.815436 Cleaning after the job
1185 23:31:53.816104 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972963/tftp-deploy-8lbzh6g8/ramdisk
1186 23:31:53.817498 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972963/tftp-deploy-8lbzh6g8/kernel
1187 23:31:53.847480 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972963/tftp-deploy-8lbzh6g8/dtb
1188 23:31:53.849099 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972963/tftp-deploy-8lbzh6g8/nfsrootfs
1189 23:31:53.905673 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972963/tftp-deploy-8lbzh6g8/modules
1190 23:31:53.924162 start: 4.1 power-off (timeout 00:00:30) [common]
1191 23:31:53.924804 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1192 23:31:53.957597 >> OK - accepted request
1193 23:31:53.959697 Returned 0 in 0 seconds
1194 23:31:54.060664 end: 4.1 power-off (duration 00:00:00) [common]
1196 23:31:54.061956 start: 4.2 read-feedback (timeout 00:10:00) [common]
1197 23:31:54.062628 Listened to connection for namespace 'common' for up to 1s
1198 23:31:55.063473 Finalising connection for namespace 'common'
1199 23:31:55.064319 Disconnecting from shell: Finalise
1200 23:31:55.064894 =>
1201 23:31:55.166224 end: 4.2 read-feedback (duration 00:00:01) [common]
1202 23:31:55.166990 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/972963
1203 23:31:57.073012 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/972963
1204 23:31:57.073583 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.