Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:14:45.255206 lava-dispatcher, installed at version: 2024.01
2 01:14:45.255998 start: 0 validate
3 01:14:45.256464 Start time: 2024-11-11 01:14:45.256435+00:00 (UTC)
4 01:14:45.256992 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:14:45.257519 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 01:14:45.295406 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:14:45.295943 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:14:45.323210 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:14:45.323813 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 01:14:45.352706 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:14:45.353165 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 01:14:45.386614 validate duration: 0.13
14 01:14:45.387462 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:14:45.387777 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:14:45.388429 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:14:45.389141 Not decompressing ramdisk as can be used compressed.
18 01:14:45.389700 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 01:14:45.390098 saving as /var/lib/lava/dispatcher/tmp/972904/tftp-deploy-xrha8t4f/ramdisk/rootfs.cpio.gz
20 01:14:45.390533 total size: 47897469 (45 MB)
21 01:14:45.427131 progress 0 % (0 MB)
22 01:14:45.458602 progress 5 % (2 MB)
23 01:14:45.489778 progress 10 % (4 MB)
24 01:14:45.519879 progress 15 % (6 MB)
25 01:14:45.551019 progress 20 % (9 MB)
26 01:14:45.581751 progress 25 % (11 MB)
27 01:14:45.611652 progress 30 % (13 MB)
28 01:14:45.642684 progress 35 % (16 MB)
29 01:14:45.672758 progress 40 % (18 MB)
30 01:14:45.703579 progress 45 % (20 MB)
31 01:14:45.733660 progress 50 % (22 MB)
32 01:14:45.764323 progress 55 % (25 MB)
33 01:14:45.795095 progress 60 % (27 MB)
34 01:14:45.825154 progress 65 % (29 MB)
35 01:14:45.856225 progress 70 % (32 MB)
36 01:14:45.886599 progress 75 % (34 MB)
37 01:14:45.917451 progress 80 % (36 MB)
38 01:14:45.948358 progress 85 % (38 MB)
39 01:14:45.978968 progress 90 % (41 MB)
40 01:14:46.009842 progress 95 % (43 MB)
41 01:14:46.039506 progress 100 % (45 MB)
42 01:14:46.040294 45 MB downloaded in 0.65 s (70.30 MB/s)
43 01:14:46.040876 end: 1.1.1 http-download (duration 00:00:01) [common]
45 01:14:46.041785 end: 1.1 download-retry (duration 00:00:01) [common]
46 01:14:46.042092 start: 1.2 download-retry (timeout 00:09:59) [common]
47 01:14:46.042388 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 01:14:46.042874 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm64/defconfig/gcc-12/kernel/Image
49 01:14:46.043125 saving as /var/lib/lava/dispatcher/tmp/972904/tftp-deploy-xrha8t4f/kernel/Image
50 01:14:46.043343 total size: 45713920 (43 MB)
51 01:14:46.043562 No compression specified
52 01:14:46.081206 progress 0 % (0 MB)
53 01:14:46.109504 progress 5 % (2 MB)
54 01:14:46.137679 progress 10 % (4 MB)
55 01:14:46.166524 progress 15 % (6 MB)
56 01:14:46.196027 progress 20 % (8 MB)
57 01:14:46.224078 progress 25 % (10 MB)
58 01:14:46.252733 progress 30 % (13 MB)
59 01:14:46.281119 progress 35 % (15 MB)
60 01:14:46.309789 progress 40 % (17 MB)
61 01:14:46.337327 progress 45 % (19 MB)
62 01:14:46.365208 progress 50 % (21 MB)
63 01:14:46.393681 progress 55 % (24 MB)
64 01:14:46.421616 progress 60 % (26 MB)
65 01:14:46.449198 progress 65 % (28 MB)
66 01:14:46.477096 progress 70 % (30 MB)
67 01:14:46.505366 progress 75 % (32 MB)
68 01:14:46.533940 progress 80 % (34 MB)
69 01:14:46.562231 progress 85 % (37 MB)
70 01:14:46.589977 progress 90 % (39 MB)
71 01:14:46.618129 progress 95 % (41 MB)
72 01:14:46.645491 progress 100 % (43 MB)
73 01:14:46.646006 43 MB downloaded in 0.60 s (72.34 MB/s)
74 01:14:46.646508 end: 1.2.1 http-download (duration 00:00:01) [common]
76 01:14:46.647353 end: 1.2 download-retry (duration 00:00:01) [common]
77 01:14:46.647644 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:14:46.647918 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:14:46.648423 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 01:14:46.648681 saving as /var/lib/lava/dispatcher/tmp/972904/tftp-deploy-xrha8t4f/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 01:14:46.648898 total size: 53209 (0 MB)
82 01:14:46.649117 No compression specified
83 01:14:46.691159 progress 61 % (0 MB)
84 01:14:46.692036 progress 100 % (0 MB)
85 01:14:46.692599 0 MB downloaded in 0.04 s (1.16 MB/s)
86 01:14:46.693077 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:14:46.693912 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:14:46.694185 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:14:46.694454 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:14:46.694908 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm64/defconfig/gcc-12/modules.tar.xz
92 01:14:46.695157 saving as /var/lib/lava/dispatcher/tmp/972904/tftp-deploy-xrha8t4f/modules/modules.tar
93 01:14:46.695367 total size: 11614384 (11 MB)
94 01:14:46.695582 Using unxz to decompress xz
95 01:14:46.727628 progress 0 % (0 MB)
96 01:14:46.793291 progress 5 % (0 MB)
97 01:14:46.866612 progress 10 % (1 MB)
98 01:14:46.960868 progress 15 % (1 MB)
99 01:14:47.052410 progress 20 % (2 MB)
100 01:14:47.131116 progress 25 % (2 MB)
101 01:14:47.206144 progress 30 % (3 MB)
102 01:14:47.283743 progress 35 % (3 MB)
103 01:14:47.355573 progress 40 % (4 MB)
104 01:14:47.430691 progress 45 % (5 MB)
105 01:14:47.514320 progress 50 % (5 MB)
106 01:14:47.591643 progress 55 % (6 MB)
107 01:14:47.675957 progress 60 % (6 MB)
108 01:14:47.756192 progress 65 % (7 MB)
109 01:14:47.835717 progress 70 % (7 MB)
110 01:14:47.913377 progress 75 % (8 MB)
111 01:14:47.996159 progress 80 % (8 MB)
112 01:14:48.075571 progress 85 % (9 MB)
113 01:14:48.153263 progress 90 % (9 MB)
114 01:14:48.230215 progress 95 % (10 MB)
115 01:14:48.306476 progress 100 % (11 MB)
116 01:14:48.318391 11 MB downloaded in 1.62 s (6.82 MB/s)
117 01:14:48.318962 end: 1.4.1 http-download (duration 00:00:02) [common]
119 01:14:48.319782 end: 1.4 download-retry (duration 00:00:02) [common]
120 01:14:48.320173 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 01:14:48.320706 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 01:14:48.321217 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:14:48.321716 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 01:14:48.322666 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr
125 01:14:48.323484 makedir: /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin
126 01:14:48.324152 makedir: /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/tests
127 01:14:48.324764 makedir: /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/results
128 01:14:48.325367 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-add-keys
129 01:14:48.326292 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-add-sources
130 01:14:48.327193 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-background-process-start
131 01:14:48.328137 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-background-process-stop
132 01:14:48.329109 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-common-functions
133 01:14:48.329988 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-echo-ipv4
134 01:14:48.330887 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-install-packages
135 01:14:48.331768 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-installed-packages
136 01:14:48.332670 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-os-build
137 01:14:48.333535 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-probe-channel
138 01:14:48.334495 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-probe-ip
139 01:14:48.335364 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-target-ip
140 01:14:48.336256 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-target-mac
141 01:14:48.337127 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-target-storage
142 01:14:48.338031 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-test-case
143 01:14:48.338965 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-test-event
144 01:14:48.339838 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-test-feedback
145 01:14:48.340762 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-test-raise
146 01:14:48.341648 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-test-reference
147 01:14:48.342526 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-test-runner
148 01:14:48.343391 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-test-set
149 01:14:48.344313 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-test-shell
150 01:14:48.345251 Updating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-install-packages (oe)
151 01:14:48.346268 Updating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/bin/lava-installed-packages (oe)
152 01:14:48.347095 Creating /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/environment
153 01:14:48.347830 LAVA metadata
154 01:14:48.348370 - LAVA_JOB_ID=972904
155 01:14:48.348802 - LAVA_DISPATCHER_IP=192.168.6.2
156 01:14:48.349486 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 01:14:48.351291 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 01:14:48.351876 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 01:14:48.352325 skipped lava-vland-overlay
160 01:14:48.352816 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 01:14:48.353324 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 01:14:48.353747 skipped lava-multinode-overlay
163 01:14:48.354228 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 01:14:48.354723 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 01:14:48.355192 Loading test definitions
166 01:14:48.355730 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 01:14:48.356196 Using /lava-972904 at stage 0
168 01:14:48.358303 uuid=972904_1.5.2.4.1 testdef=None
169 01:14:48.358875 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 01:14:48.359397 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 01:14:48.361705 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 01:14:48.362532 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 01:14:48.364741 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 01:14:48.365597 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 01:14:48.367662 runner path: /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/0/tests/0_igt-gpu-panfrost test_uuid 972904_1.5.2.4.1
178 01:14:48.368273 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 01:14:48.369089 Creating lava-test-runner.conf files
181 01:14:48.369298 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/972904/lava-overlay-vz0jcgpr/lava-972904/0 for stage 0
182 01:14:48.369646 - 0_igt-gpu-panfrost
183 01:14:48.370012 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 01:14:48.370344 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 01:14:48.394222 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 01:14:48.394671 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 01:14:48.394935 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 01:14:48.395204 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 01:14:48.395469 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 01:14:55.216943 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 01:14:55.217673 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 01:14:55.218136 extracting modules file /var/lib/lava/dispatcher/tmp/972904/tftp-deploy-xrha8t4f/modules/modules.tar to /var/lib/lava/dispatcher/tmp/972904/extract-overlay-ramdisk-pdek95rf/ramdisk
193 01:14:56.620831 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 01:14:56.621305 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 01:14:56.621580 [common] Applying overlay /var/lib/lava/dispatcher/tmp/972904/compress-overlay-m1y65ac_/overlay-1.5.2.5.tar.gz to ramdisk
196 01:14:56.621793 [common] Applying overlay /var/lib/lava/dispatcher/tmp/972904/compress-overlay-m1y65ac_/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/972904/extract-overlay-ramdisk-pdek95rf/ramdisk
197 01:14:56.651309 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 01:14:56.651671 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 01:14:56.651941 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 01:14:56.652191 Converting downloaded kernel to a uImage
201 01:14:56.652490 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/972904/tftp-deploy-xrha8t4f/kernel/Image /var/lib/lava/dispatcher/tmp/972904/tftp-deploy-xrha8t4f/kernel/uImage
202 01:14:57.126959 output: Image Name:
203 01:14:57.127380 output: Created: Mon Nov 11 01:14:56 2024
204 01:14:57.127587 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 01:14:57.127791 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 01:14:57.128031 output: Load Address: 01080000
207 01:14:57.128240 output: Entry Point: 01080000
208 01:14:57.128443 output:
209 01:14:57.128778 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 01:14:57.129041 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 01:14:57.129307 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 01:14:57.129559 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 01:14:57.129814 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 01:14:57.130069 Building ramdisk /var/lib/lava/dispatcher/tmp/972904/extract-overlay-ramdisk-pdek95rf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/972904/extract-overlay-ramdisk-pdek95rf/ramdisk
215 01:15:03.755451 >> 502416 blocks
216 01:15:24.462797 Adding RAMdisk u-boot header.
217 01:15:24.463264 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/972904/extract-overlay-ramdisk-pdek95rf/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/972904/extract-overlay-ramdisk-pdek95rf/ramdisk.cpio.gz.uboot
218 01:15:25.147164 output: Image Name:
219 01:15:25.147794 output: Created: Mon Nov 11 01:15:24 2024
220 01:15:25.148280 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 01:15:25.148697 output: Data Size: 65715581 Bytes = 64175.37 KiB = 62.67 MiB
222 01:15:25.149102 output: Load Address: 00000000
223 01:15:25.149505 output: Entry Point: 00000000
224 01:15:25.149904 output:
225 01:15:25.150928 rename /var/lib/lava/dispatcher/tmp/972904/extract-overlay-ramdisk-pdek95rf/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/972904/tftp-deploy-xrha8t4f/ramdisk/ramdisk.cpio.gz.uboot
226 01:15:25.151654 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 01:15:25.152240 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 01:15:25.152783 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 01:15:25.153244 No LXC device requested
230 01:15:25.153755 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 01:15:25.154273 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 01:15:25.154776 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 01:15:25.155192 Checking files for TFTP limit of 4294967296 bytes.
234 01:15:25.157894 end: 1 tftp-deploy (duration 00:00:40) [common]
235 01:15:25.158472 start: 2 uboot-action (timeout 00:05:00) [common]
236 01:15:25.159009 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 01:15:25.159515 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 01:15:25.160054 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 01:15:25.160596 Using kernel file from prepare-kernel: 972904/tftp-deploy-xrha8t4f/kernel/uImage
240 01:15:25.161233 substitutions:
241 01:15:25.161652 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 01:15:25.162060 - {DTB_ADDR}: 0x01070000
243 01:15:25.162461 - {DTB}: 972904/tftp-deploy-xrha8t4f/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 01:15:25.162863 - {INITRD}: 972904/tftp-deploy-xrha8t4f/ramdisk/ramdisk.cpio.gz.uboot
245 01:15:25.163260 - {KERNEL_ADDR}: 0x01080000
246 01:15:25.163650 - {KERNEL}: 972904/tftp-deploy-xrha8t4f/kernel/uImage
247 01:15:25.164068 - {LAVA_MAC}: None
248 01:15:25.164510 - {PRESEED_CONFIG}: None
249 01:15:25.164910 - {PRESEED_LOCAL}: None
250 01:15:25.165303 - {RAMDISK_ADDR}: 0x08000000
251 01:15:25.165695 - {RAMDISK}: 972904/tftp-deploy-xrha8t4f/ramdisk/ramdisk.cpio.gz.uboot
252 01:15:25.166095 - {ROOT_PART}: None
253 01:15:25.166485 - {ROOT}: None
254 01:15:25.166879 - {SERVER_IP}: 192.168.6.2
255 01:15:25.167273 - {TEE_ADDR}: 0x83000000
256 01:15:25.167664 - {TEE}: None
257 01:15:25.168084 Parsed boot commands:
258 01:15:25.168471 - setenv autoload no
259 01:15:25.168863 - setenv initrd_high 0xffffffff
260 01:15:25.169250 - setenv fdt_high 0xffffffff
261 01:15:25.169637 - dhcp
262 01:15:25.170024 - setenv serverip 192.168.6.2
263 01:15:25.170412 - tftpboot 0x01080000 972904/tftp-deploy-xrha8t4f/kernel/uImage
264 01:15:25.170801 - tftpboot 0x08000000 972904/tftp-deploy-xrha8t4f/ramdisk/ramdisk.cpio.gz.uboot
265 01:15:25.171190 - tftpboot 0x01070000 972904/tftp-deploy-xrha8t4f/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 01:15:25.171578 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 01:15:25.171969 - bootm 0x01080000 0x08000000 0x01070000
268 01:15:25.172504 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 01:15:25.173981 start: 2.3 connect-device (timeout 00:05:00) [common]
271 01:15:25.174431 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 01:15:25.189201 Setting prompt string to ['lava-test: # ']
273 01:15:25.190682 end: 2.3 connect-device (duration 00:00:00) [common]
274 01:15:25.191291 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 01:15:25.191833 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 01:15:25.192420 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 01:15:25.193575 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 01:15:25.231213 >> OK - accepted request
279 01:15:25.233539 Returned 0 in 0 seconds
280 01:15:25.334629 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 01:15:25.336312 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 01:15:25.336892 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 01:15:25.337395 Setting prompt string to ['Hit any key to stop autoboot']
285 01:15:25.337844 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 01:15:25.339458 Trying 192.168.56.21...
287 01:15:25.339937 Connected to conserv1.
288 01:15:25.340517 Escape character is '^]'.
289 01:15:25.340950
290 01:15:25.341386 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 01:15:25.341820
292 01:15:32.655880 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 01:15:32.656577 bl2_stage_init 0x01
294 01:15:32.657004 bl2_stage_init 0x81
295 01:15:32.661408 hw id: 0x0000 - pwm id 0x01
296 01:15:32.661865 bl2_stage_init 0xc1
297 01:15:32.667025 bl2_stage_init 0x02
298 01:15:32.667464
299 01:15:32.667874 L0:00000000
300 01:15:32.668312 L1:00000703
301 01:15:32.668710 L2:00008067
302 01:15:32.669100 L3:15000000
303 01:15:32.672552 S1:00000000
304 01:15:32.672986 B2:20282000
305 01:15:32.673385 B1:a0f83180
306 01:15:32.673775
307 01:15:32.674166 TE: 72012
308 01:15:32.674558
309 01:15:32.678155 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 01:15:32.678585
311 01:15:32.683693 Board ID = 1
312 01:15:32.684140 Set cpu clk to 24M
313 01:15:32.684536 Set clk81 to 24M
314 01:15:32.689347 Use GP1_pll as DSU clk.
315 01:15:32.689775 DSU clk: 1200 Mhz
316 01:15:32.690173 CPU clk: 1200 MHz
317 01:15:32.694941 Set clk81 to 166.6M
318 01:15:32.700559 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 01:15:32.700985 board id: 1
320 01:15:32.707837 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 01:15:32.718692 fw parse done
322 01:15:32.724671 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 01:15:32.767881 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 01:15:32.778895 PIEI prepare done
325 01:15:32.779321 fastboot data load
326 01:15:32.779724 fastboot data verify
327 01:15:32.784414 verify result: 266
328 01:15:32.790026 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 01:15:32.790450 LPDDR4 probe
330 01:15:32.790846 ddr clk to 1584MHz
331 01:15:32.798028 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 01:15:32.835735
333 01:15:32.836196 dmc_version 0001
334 01:15:32.842796 Check phy result
335 01:15:32.848779 INFO : End of CA training
336 01:15:32.849220 INFO : End of initialization
337 01:15:32.854411 INFO : Training has run successfully!
338 01:15:32.854834 Check phy result
339 01:15:32.860002 INFO : End of initialization
340 01:15:32.860428 INFO : End of read enable training
341 01:15:32.865589 INFO : End of fine write leveling
342 01:15:32.871194 INFO : End of Write leveling coarse delay
343 01:15:32.871625 INFO : Training has run successfully!
344 01:15:32.872060 Check phy result
345 01:15:32.876782 INFO : End of initialization
346 01:15:32.877216 INFO : End of read dq deskew training
347 01:15:32.882380 INFO : End of MPR read delay center optimization
348 01:15:32.887959 INFO : End of write delay center optimization
349 01:15:32.893575 INFO : End of read delay center optimization
350 01:15:32.894010 INFO : End of max read latency training
351 01:15:32.899190 INFO : Training has run successfully!
352 01:15:32.899623 1D training succeed
353 01:15:32.908391 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 01:15:32.956720 Check phy result
355 01:15:32.957156 INFO : End of initialization
356 01:15:32.984117 INFO : End of 2D read delay Voltage center optimization
357 01:15:33.008247 INFO : End of 2D read delay Voltage center optimization
358 01:15:33.065019 INFO : End of 2D write delay Voltage center optimization
359 01:15:33.118945 INFO : End of 2D write delay Voltage center optimization
360 01:15:33.124431 INFO : Training has run successfully!
361 01:15:33.124858
362 01:15:33.125258 channel==0
363 01:15:33.130042 RxClkDly_Margin_A0==78 ps 8
364 01:15:33.130462 TxDqDly_Margin_A0==98 ps 10
365 01:15:33.133313 RxClkDly_Margin_A1==88 ps 9
366 01:15:33.133731 TxDqDly_Margin_A1==88 ps 9
367 01:15:33.138860 TrainedVREFDQ_A0==74
368 01:15:33.139282 TrainedVREFDQ_A1==74
369 01:15:33.139681 VrefDac_Margin_A0==24
370 01:15:33.144475 DeviceVref_Margin_A0==40
371 01:15:33.144895 VrefDac_Margin_A1==22
372 01:15:33.150082 DeviceVref_Margin_A1==40
373 01:15:33.150504
374 01:15:33.150908
375 01:15:33.151305 channel==1
376 01:15:33.151696 RxClkDly_Margin_A0==78 ps 8
377 01:15:33.155690 TxDqDly_Margin_A0==98 ps 10
378 01:15:33.156157 RxClkDly_Margin_A1==78 ps 8
379 01:15:33.161290 TxDqDly_Margin_A1==88 ps 9
380 01:15:33.161714 TrainedVREFDQ_A0==78
381 01:15:33.162113 TrainedVREFDQ_A1==75
382 01:15:33.166928 VrefDac_Margin_A0==22
383 01:15:33.167346 DeviceVref_Margin_A0==36
384 01:15:33.172380 VrefDac_Margin_A1==22
385 01:15:33.172798 DeviceVref_Margin_A1==39
386 01:15:33.173194
387 01:15:33.178064 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 01:15:33.178489
389 01:15:33.206096 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 01:15:33.211648 2D training succeed
391 01:15:33.217120 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 01:15:33.217554 auto size-- 65535DDR cs0 size: 2048MB
393 01:15:33.222703 DDR cs1 size: 2048MB
394 01:15:33.223121 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 01:15:33.228361 cs0 DataBus test pass
396 01:15:33.228777 cs1 DataBus test pass
397 01:15:33.229169 cs0 AddrBus test pass
398 01:15:33.233924 cs1 AddrBus test pass
399 01:15:33.234345
400 01:15:33.234744 100bdlr_step_size ps== 471
401 01:15:33.235145 result report
402 01:15:33.239529 boot times 0Enable ddr reg access
403 01:15:33.247069 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 01:15:33.260928 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 01:15:33.919961 bl2z: ptr: 05129330, size: 00001e40
406 01:15:33.927836 0.0;M3 CHK:0;cm4_sp_mode 0
407 01:15:33.928320 MVN_1=0x00000000
408 01:15:33.928736 MVN_2=0x00000000
409 01:15:33.939326 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 01:15:33.939775 OPS=0x04
411 01:15:33.940233 ring efuse init
412 01:15:33.942205 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 01:15:33.948633 [0.017354 Inits done]
414 01:15:33.949064 secure task start!
415 01:15:33.949469 high task start!
416 01:15:33.949870 low task start!
417 01:15:33.952907 run into bl31
418 01:15:33.961537 NOTICE: BL31: v1.3(release):4fc40b1
419 01:15:33.969359 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 01:15:33.969794 NOTICE: BL31: G12A normal boot!
421 01:15:33.984968 NOTICE: BL31: BL33 decompress pass
422 01:15:33.990669 ERROR: Error initializing runtime service opteed_fast
423 01:15:36.705429 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 01:15:36.706064 bl2_stage_init 0x01
425 01:15:36.706493 bl2_stage_init 0x81
426 01:15:36.710986 hw id: 0x0000 - pwm id 0x01
427 01:15:36.711452 bl2_stage_init 0xc1
428 01:15:36.716605 bl2_stage_init 0x02
429 01:15:36.717093
430 01:15:36.717486 L0:00000000
431 01:15:36.717869 L1:00000703
432 01:15:36.718250 L2:00008067
433 01:15:36.718632 L3:15000000
434 01:15:36.722181 S1:00000000
435 01:15:36.722592 B2:20282000
436 01:15:36.722977 B1:a0f83180
437 01:15:36.723378
438 01:15:36.723761 TE: 70454
439 01:15:36.724207
440 01:15:36.727763 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 01:15:36.728232
442 01:15:36.733378 Board ID = 1
443 01:15:36.733788 Set cpu clk to 24M
444 01:15:36.734174 Set clk81 to 24M
445 01:15:36.738947 Use GP1_pll as DSU clk.
446 01:15:36.739355 DSU clk: 1200 Mhz
447 01:15:36.739737 CPU clk: 1200 MHz
448 01:15:36.744580 Set clk81 to 166.6M
449 01:15:36.750152 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 01:15:36.750563 board id: 1
451 01:15:36.757349 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 01:15:36.768096 fw parse done
453 01:15:36.773963 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 01:15:36.816643 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 01:15:36.827529 PIEI prepare done
456 01:15:36.827945 fastboot data load
457 01:15:36.828373 fastboot data verify
458 01:15:36.833218 verify result: 266
459 01:15:36.838727 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 01:15:36.839135 LPDDR4 probe
461 01:15:36.839518 ddr clk to 1584MHz
462 01:15:36.846742 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 01:15:36.884008
464 01:15:36.884476 dmc_version 0001
465 01:15:36.890666 Check phy result
466 01:15:36.896646 INFO : End of CA training
467 01:15:36.897077 INFO : End of initialization
468 01:15:36.902240 INFO : Training has run successfully!
469 01:15:36.902657 Check phy result
470 01:15:36.907789 INFO : End of initialization
471 01:15:36.908238 INFO : End of read enable training
472 01:15:36.913402 INFO : End of fine write leveling
473 01:15:36.918987 INFO : End of Write leveling coarse delay
474 01:15:36.919402 INFO : Training has run successfully!
475 01:15:36.919795 Check phy result
476 01:15:36.924619 INFO : End of initialization
477 01:15:36.925039 INFO : End of read dq deskew training
478 01:15:36.930231 INFO : End of MPR read delay center optimization
479 01:15:36.935797 INFO : End of write delay center optimization
480 01:15:36.941371 INFO : End of read delay center optimization
481 01:15:36.941780 INFO : End of max read latency training
482 01:15:36.946996 INFO : Training has run successfully!
483 01:15:36.947408 1D training succeed
484 01:15:36.956160 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 01:15:37.003783 Check phy result
486 01:15:37.004252 INFO : End of initialization
487 01:15:37.026164 INFO : End of 2D read delay Voltage center optimization
488 01:15:37.045278 INFO : End of 2D read delay Voltage center optimization
489 01:15:37.097134 INFO : End of 2D write delay Voltage center optimization
490 01:15:37.146357 INFO : End of 2D write delay Voltage center optimization
491 01:15:37.151886 INFO : Training has run successfully!
492 01:15:37.152345
493 01:15:37.152741 channel==0
494 01:15:37.157497 RxClkDly_Margin_A0==78 ps 8
495 01:15:37.157914 TxDqDly_Margin_A0==98 ps 10
496 01:15:37.163065 RxClkDly_Margin_A1==88 ps 9
497 01:15:37.163474 TxDqDly_Margin_A1==98 ps 10
498 01:15:37.163866 TrainedVREFDQ_A0==75
499 01:15:37.168658 TrainedVREFDQ_A1==74
500 01:15:37.169075 VrefDac_Margin_A0==24
501 01:15:37.169464 DeviceVref_Margin_A0==39
502 01:15:37.174341 VrefDac_Margin_A1==22
503 01:15:37.174768 DeviceVref_Margin_A1==40
504 01:15:37.175159
505 01:15:37.175546
506 01:15:37.179866 channel==1
507 01:15:37.180319 RxClkDly_Margin_A0==88 ps 9
508 01:15:37.180727 TxDqDly_Margin_A0==98 ps 10
509 01:15:37.185509 RxClkDly_Margin_A1==88 ps 9
510 01:15:37.185931 TxDqDly_Margin_A1==88 ps 9
511 01:15:37.191078 TrainedVREFDQ_A0==78
512 01:15:37.191494 TrainedVREFDQ_A1==75
513 01:15:37.191883 VrefDac_Margin_A0==23
514 01:15:37.196672 DeviceVref_Margin_A0==36
515 01:15:37.197081 VrefDac_Margin_A1==22
516 01:15:37.202316 DeviceVref_Margin_A1==39
517 01:15:37.202722
518 01:15:37.203111 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 01:15:37.203495
520 01:15:37.235940 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
521 01:15:37.236414 2D training succeed
522 01:15:37.241538 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 01:15:37.247144 auto size-- 65535DDR cs0 size: 2048MB
524 01:15:37.247559 DDR cs1 size: 2048MB
525 01:15:37.252685 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 01:15:37.253105 cs0 DataBus test pass
527 01:15:37.258274 cs1 DataBus test pass
528 01:15:37.258685 cs0 AddrBus test pass
529 01:15:37.259070 cs1 AddrBus test pass
530 01:15:37.259451
531 01:15:37.263902 100bdlr_step_size ps== 478
532 01:15:37.264360 result report
533 01:15:37.269492 boot times 0Enable ddr reg access
534 01:15:37.274745 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 01:15:37.288548 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 01:15:37.943154 bl2z: ptr: 05129330, size: 00001e40
537 01:15:37.951320 0.0;M3 CHK:0;cm4_sp_mode 0
538 01:15:37.951812 MVN_1=0x00000000
539 01:15:37.952262 MVN_2=0x00000000
540 01:15:37.962727 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 01:15:37.963213 OPS=0x04
542 01:15:37.963625 ring efuse init
543 01:15:37.968465 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 01:15:37.968941 [0.017319 Inits done]
545 01:15:37.969347 secure task start!
546 01:15:37.976326 high task start!
547 01:15:37.976785 low task start!
548 01:15:37.977188 run into bl31
549 01:15:37.984914 NOTICE: BL31: v1.3(release):4fc40b1
550 01:15:37.992729 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 01:15:37.993202 NOTICE: BL31: G12A normal boot!
552 01:15:38.008323 NOTICE: BL31: BL33 decompress pass
553 01:15:38.013965 ERROR: Error initializing runtime service opteed_fast
554 01:15:39.403211 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 01:15:39.403823 bl2_stage_init 0x01
556 01:15:39.404301 bl2_stage_init 0x81
557 01:15:39.408950 hw id: 0x0000 - pwm id 0x01
558 01:15:39.409426 bl2_stage_init 0xc1
559 01:15:39.414329 bl2_stage_init 0x02
560 01:15:39.414818
561 01:15:39.415234 L0:00000000
562 01:15:39.415632 L1:00000703
563 01:15:39.416066 L2:00008067
564 01:15:39.416469 L3:15000000
565 01:15:39.420091 S1:00000000
566 01:15:39.420566 B2:20282000
567 01:15:39.420972 B1:a0f83180
568 01:15:39.421369
569 01:15:39.421763 TE: 69095
570 01:15:39.422159
571 01:15:39.425592 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 01:15:39.426055
573 01:15:39.431200 Board ID = 1
574 01:15:39.431667 Set cpu clk to 24M
575 01:15:39.432109 Set clk81 to 24M
576 01:15:39.434534 Use GP1_pll as DSU clk.
577 01:15:39.434988 DSU clk: 1200 Mhz
578 01:15:39.440095 CPU clk: 1200 MHz
579 01:15:39.440557 Set clk81 to 166.6M
580 01:15:39.445717 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 01:15:39.446177 board id: 1
582 01:15:39.455008 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 01:15:39.465740 fw parse done
584 01:15:39.471699 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 01:15:39.514388 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 01:15:39.525340 PIEI prepare done
587 01:15:39.525838 fastboot data load
588 01:15:39.526252 fastboot data verify
589 01:15:39.530944 verify result: 266
590 01:15:39.536542 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 01:15:39.537038 LPDDR4 probe
592 01:15:39.537449 ddr clk to 1584MHz
593 01:15:39.544457 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 01:15:39.581792
595 01:15:39.582318 dmc_version 0001
596 01:15:39.588532 Check phy result
597 01:15:39.594348 INFO : End of CA training
598 01:15:39.594818 INFO : End of initialization
599 01:15:39.600027 INFO : Training has run successfully!
600 01:15:39.600506 Check phy result
601 01:15:39.605627 INFO : End of initialization
602 01:15:39.606098 INFO : End of read enable training
603 01:15:39.608870 INFO : End of fine write leveling
604 01:15:39.614421 INFO : End of Write leveling coarse delay
605 01:15:39.620045 INFO : Training has run successfully!
606 01:15:39.620519 Check phy result
607 01:15:39.620928 INFO : End of initialization
608 01:15:39.625625 INFO : End of read dq deskew training
609 01:15:39.631255 INFO : End of MPR read delay center optimization
610 01:15:39.631734 INFO : End of write delay center optimization
611 01:15:39.636852 INFO : End of read delay center optimization
612 01:15:39.642420 INFO : End of max read latency training
613 01:15:39.642891 INFO : Training has run successfully!
614 01:15:39.648078 1D training succeed
615 01:15:39.653941 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 01:15:39.701478 Check phy result
617 01:15:39.701948 INFO : End of initialization
618 01:15:39.723901 INFO : End of 2D read delay Voltage center optimization
619 01:15:39.742968 INFO : End of 2D read delay Voltage center optimization
620 01:15:39.794919 INFO : End of 2D write delay Voltage center optimization
621 01:15:39.844131 INFO : End of 2D write delay Voltage center optimization
622 01:15:39.849698 INFO : Training has run successfully!
623 01:15:39.850148
624 01:15:39.850557 channel==0
625 01:15:39.855271 RxClkDly_Margin_A0==88 ps 9
626 01:15:39.855717 TxDqDly_Margin_A0==98 ps 10
627 01:15:39.860858 RxClkDly_Margin_A1==88 ps 9
628 01:15:39.861310 TxDqDly_Margin_A1==88 ps 9
629 01:15:39.861715 TrainedVREFDQ_A0==74
630 01:15:39.866465 TrainedVREFDQ_A1==74
631 01:15:39.866914 VrefDac_Margin_A0==22
632 01:15:39.867316 DeviceVref_Margin_A0==40
633 01:15:39.872088 VrefDac_Margin_A1==23
634 01:15:39.872536 DeviceVref_Margin_A1==40
635 01:15:39.872938
636 01:15:39.873331
637 01:15:39.873723 channel==1
638 01:15:39.877631 RxClkDly_Margin_A0==78 ps 8
639 01:15:39.878084 TxDqDly_Margin_A0==98 ps 10
640 01:15:39.883233 RxClkDly_Margin_A1==78 ps 8
641 01:15:39.883684 TxDqDly_Margin_A1==88 ps 9
642 01:15:39.888888 TrainedVREFDQ_A0==78
643 01:15:39.889371 TrainedVREFDQ_A1==75
644 01:15:39.889775 VrefDac_Margin_A0==22
645 01:15:39.894438 DeviceVref_Margin_A0==36
646 01:15:39.894884 VrefDac_Margin_A1==22
647 01:15:39.899917 DeviceVref_Margin_A1==38
648 01:15:39.900392
649 01:15:39.900800 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 01:15:39.901196
651 01:15:39.933515 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000017 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
652 01:15:39.933994 2D training succeed
653 01:15:39.939165 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 01:15:39.944784 auto size-- 65535DDR cs0 size: 2048MB
655 01:15:39.945235 DDR cs1 size: 2048MB
656 01:15:39.950334 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 01:15:39.950780 cs0 DataBus test pass
658 01:15:39.955931 cs1 DataBus test pass
659 01:15:39.956429 cs0 AddrBus test pass
660 01:15:39.956834 cs1 AddrBus test pass
661 01:15:39.957228
662 01:15:39.961556 100bdlr_step_size ps== 478
663 01:15:39.962017 result report
664 01:15:39.967129 boot times 0Enable ddr reg access
665 01:15:39.972308 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 01:15:39.986095 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 01:15:40.640271 bl2z: ptr: 05129330, size: 00001e40
668 01:15:40.647298 0.0;M3 CHK:0;cm4_sp_mode 0
669 01:15:40.647822 MVN_1=0x00000000
670 01:15:40.648378 MVN_2=0x00000000
671 01:15:40.658795 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 01:15:40.659296 OPS=0x04
673 01:15:40.659759 ring efuse init
674 01:15:40.661779 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 01:15:40.667904 [0.017310 Inits done]
676 01:15:40.668415 secure task start!
677 01:15:40.668864 high task start!
678 01:15:40.669308 low task start!
679 01:15:40.672216 run into bl31
680 01:15:40.680802 NOTICE: BL31: v1.3(release):4fc40b1
681 01:15:40.688608 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 01:15:40.689097 NOTICE: BL31: G12A normal boot!
683 01:15:40.704084 NOTICE: BL31: BL33 decompress pass
684 01:15:40.709746 ERROR: Error initializing runtime service opteed_fast
685 01:15:41.504086
686 01:15:41.504707
687 01:15:41.509390 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 01:15:41.509876
689 01:15:41.512865 Model: Libre Computer AML-S905D3-CC Solitude
690 01:15:41.659751 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 01:15:41.675067 DRAM: 2 GiB (effective 3.8 GiB)
692 01:15:41.776061 Core: 406 devices, 33 uclasses, devicetree: separate
693 01:15:41.781923 WDT: Not starting watchdog@f0d0
694 01:15:41.807020 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 01:15:41.819155 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 01:15:41.824242 ** Bad device specification mmc 0 **
697 01:15:41.834252 Card did not respond to voltage select! : -110
698 01:15:41.841844 ** Bad device specification mmc 0 **
699 01:15:41.842293 Couldn't find partition mmc 0
700 01:15:41.850203 Card did not respond to voltage select! : -110
701 01:15:41.855695 ** Bad device specification mmc 0 **
702 01:15:41.856171 Couldn't find partition mmc 0
703 01:15:41.860767 Error: could not access storage.
704 01:15:42.158235 Net: eth0: ethernet@ff3f0000
705 01:15:42.158830 starting USB...
706 01:15:42.402964 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 01:15:42.403536 Starting the controller
708 01:15:42.409898 USB XHCI 1.10
709 01:15:43.963700 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 01:15:43.971964 scanning usb for storage devices... 0 Storage Device(s) found
712 01:15:44.023439 Hit any key to stop autoboot: 1
713 01:15:44.024432 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 01:15:44.025256 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 01:15:44.025885 Setting prompt string to ['=>']
716 01:15:44.026513 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 01:15:44.038035 0
718 01:15:44.038960 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 01:15:44.140174 => setenv autoload no
721 01:15:44.141120 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 01:15:44.146019 setenv autoload no
724 01:15:44.247836 => setenv initrd_high 0xffffffff
725 01:15:44.248569 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 01:15:44.253495 setenv initrd_high 0xffffffff
728 01:15:44.359602 => setenv fdt_high 0xffffffff
729 01:15:44.360884 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 01:15:44.365153 setenv fdt_high 0xffffffff
732 01:15:44.467014 => dhcp
733 01:15:44.467965 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 01:15:44.473010 dhcp
735 01:15:45.078604 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 01:15:45.079208 Speed: 1000, full duplex
737 01:15:45.079631 BOOTP broadcast 1
738 01:15:45.087029 DHCP client bound to address 192.168.6.21 (8 ms)
740 01:15:45.188593 => setenv serverip 192.168.6.2
741 01:15:45.189573 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
742 01:15:45.194043 setenv serverip 192.168.6.2
744 01:15:45.295551 => tftpboot 0x01080000 972904/tftp-deploy-xrha8t4f/kernel/uImage
745 01:15:45.296638 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
746 01:15:45.303179 tftpboot 0x01080000 972904/tftp-deploy-xrha8t4f/kernel/uImage
747 01:15:45.303711 Speed: 1000, full duplex
748 01:15:45.304171 Using ethernet@ff3f0000 device
749 01:15:45.308770 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 01:15:45.314415 Filename '972904/tftp-deploy-xrha8t4f/kernel/uImage'.
751 01:15:45.317756 Load address: 0x1080000
752 01:15:45.322709 Loading: * UDP wrong checksum 00000005 0000532a
753 01:15:48.228229 ################################################## 43.6 MiB
754 01:15:48.228897 15 MiB/s
755 01:15:48.229343 done
756 01:15:48.233086 Bytes transferred = 45713984 (2b98a40 hex)
758 01:15:48.334611 => tftpboot 0x08000000 972904/tftp-deploy-xrha8t4f/ramdisk/ramdisk.cpio.gz.uboot
759 01:15:48.335276 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
760 01:15:48.342092 tftpboot 0x08000000 972904/tftp-deploy-xrha8t4f/ramdisk/ramdisk.cpio.gz.uboot
761 01:15:48.342594 Speed: 1000, full duplex
762 01:15:48.343025 Using ethernet@ff3f0000 device
763 01:15:48.347554 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
764 01:15:48.357264 Filename '972904/tftp-deploy-xrha8t4f/ramdisk/ramdisk.cpio.gz.uboot'.
765 01:15:48.357682 Load address: 0x8000000
766 01:15:58.592796 Loading: *######################T ########################### UDP wrong checksum 0000000f 0000ab60
767 01:16:03.593301 T UDP wrong checksum 0000000f 0000ab60
768 01:16:13.595298 T T UDP wrong checksum 0000000f 0000ab60
769 01:16:30.582941 T T T UDP wrong checksum 000000ff 0000c269
770 01:16:30.620817 UDP wrong checksum 000000ff 00005e5c
771 01:16:33.599456 T UDP wrong checksum 0000000f 0000ab60
772 01:16:48.603030 T T
773 01:16:48.603655 Retry count exceeded; starting again
775 01:16:48.605119 end: 2.4.3 bootloader-commands (duration 00:01:05) [common]
778 01:16:48.606923 end: 2.4 uboot-commands (duration 00:01:23) [common]
780 01:16:48.608373 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
782 01:16:48.609396 end: 2 uboot-action (duration 00:01:23) [common]
784 01:16:48.610942 Cleaning after the job
785 01:16:48.611483 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972904/tftp-deploy-xrha8t4f/ramdisk
786 01:16:48.612779 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972904/tftp-deploy-xrha8t4f/kernel
787 01:16:48.657410 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972904/tftp-deploy-xrha8t4f/dtb
788 01:16:48.658184 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972904/tftp-deploy-xrha8t4f/modules
789 01:16:48.679393 start: 4.1 power-off (timeout 00:00:30) [common]
790 01:16:48.680045 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
791 01:16:48.710861 >> OK - accepted request
792 01:16:48.712949 Returned 0 in 0 seconds
793 01:16:48.813917 end: 4.1 power-off (duration 00:00:00) [common]
795 01:16:48.814823 start: 4.2 read-feedback (timeout 00:10:00) [common]
796 01:16:48.815468 Listened to connection for namespace 'common' for up to 1s
797 01:16:49.816441 Finalising connection for namespace 'common'
798 01:16:49.817186 Disconnecting from shell: Finalise
799 01:16:49.817696 =>
800 01:16:49.918672 end: 4.2 read-feedback (duration 00:00:01) [common]
801 01:16:49.919306 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/972904
802 01:16:50.566217 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/972904
803 01:16:50.566833 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.