Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 8
- Errors: 0
- Boot result: PASS
- Kernel Errors: 6
1 01:07:24.913785 lava-dispatcher, installed at version: 2024.01
2 01:07:24.914587 start: 0 validate
3 01:07:24.915059 Start time: 2024-11-11 01:07:24.915029+00:00 (UTC)
4 01:07:24.915594 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:07:24.916170 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:07:24.958684 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:07:24.959212 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:07:24.989008 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:07:24.989604 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:07:25.022984 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:07:25.023469 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:07:25.058199 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:07:25.058685 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 01:07:25.101120 validate duration: 0.19
16 01:07:25.102569 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:07:25.103157 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:07:25.103735 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:07:25.104693 Not decompressing ramdisk as can be used compressed.
20 01:07:25.105450 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:07:25.105952 saving as /var/lib/lava/dispatcher/tmp/972876/tftp-deploy-rkkyrml0/ramdisk/initrd.cpio.gz
22 01:07:25.106439 total size: 5628169 (5 MB)
23 01:07:25.148449 progress 0 % (0 MB)
24 01:07:25.156333 progress 5 % (0 MB)
25 01:07:25.164517 progress 10 % (0 MB)
26 01:07:25.171666 progress 15 % (0 MB)
27 01:07:25.175934 progress 20 % (1 MB)
28 01:07:25.179577 progress 25 % (1 MB)
29 01:07:25.183629 progress 30 % (1 MB)
30 01:07:25.187676 progress 35 % (1 MB)
31 01:07:25.191302 progress 40 % (2 MB)
32 01:07:25.195412 progress 45 % (2 MB)
33 01:07:25.199047 progress 50 % (2 MB)
34 01:07:25.203480 progress 55 % (2 MB)
35 01:07:25.207690 progress 60 % (3 MB)
36 01:07:25.211332 progress 65 % (3 MB)
37 01:07:25.215382 progress 70 % (3 MB)
38 01:07:25.219022 progress 75 % (4 MB)
39 01:07:25.223145 progress 80 % (4 MB)
40 01:07:25.226823 progress 85 % (4 MB)
41 01:07:25.230848 progress 90 % (4 MB)
42 01:07:25.234625 progress 95 % (5 MB)
43 01:07:25.237928 progress 100 % (5 MB)
44 01:07:25.238583 5 MB downloaded in 0.13 s (40.62 MB/s)
45 01:07:25.239131 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:07:25.240051 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:07:25.240357 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:07:25.240630 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:07:25.241099 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm64/defconfig/gcc-12/kernel/Image
51 01:07:25.241352 saving as /var/lib/lava/dispatcher/tmp/972876/tftp-deploy-rkkyrml0/kernel/Image
52 01:07:25.241562 total size: 45713920 (43 MB)
53 01:07:25.241773 No compression specified
54 01:07:25.279634 progress 0 % (0 MB)
55 01:07:25.308067 progress 5 % (2 MB)
56 01:07:25.336162 progress 10 % (4 MB)
57 01:07:25.364143 progress 15 % (6 MB)
58 01:07:25.392343 progress 20 % (8 MB)
59 01:07:25.420579 progress 25 % (10 MB)
60 01:07:25.448372 progress 30 % (13 MB)
61 01:07:25.476228 progress 35 % (15 MB)
62 01:07:25.504411 progress 40 % (17 MB)
63 01:07:25.531844 progress 45 % (19 MB)
64 01:07:25.559884 progress 50 % (21 MB)
65 01:07:25.588146 progress 55 % (24 MB)
66 01:07:25.615859 progress 60 % (26 MB)
67 01:07:25.643200 progress 65 % (28 MB)
68 01:07:25.670760 progress 70 % (30 MB)
69 01:07:25.698790 progress 75 % (32 MB)
70 01:07:25.726349 progress 80 % (34 MB)
71 01:07:25.753573 progress 85 % (37 MB)
72 01:07:25.781218 progress 90 % (39 MB)
73 01:07:25.809223 progress 95 % (41 MB)
74 01:07:25.836418 progress 100 % (43 MB)
75 01:07:25.836972 43 MB downloaded in 0.60 s (73.22 MB/s)
76 01:07:25.837456 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:07:25.838277 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:07:25.838553 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:07:25.838819 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:07:25.839281 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:07:25.839527 saving as /var/lib/lava/dispatcher/tmp/972876/tftp-deploy-rkkyrml0/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:07:25.839739 total size: 54703 (0 MB)
84 01:07:25.839948 No compression specified
85 01:07:25.882281 progress 59 % (0 MB)
86 01:07:25.883152 progress 100 % (0 MB)
87 01:07:25.883702 0 MB downloaded in 0.04 s (1.19 MB/s)
88 01:07:25.884194 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:07:25.885027 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:07:25.885291 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:07:25.885553 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:07:25.886002 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:07:25.886249 saving as /var/lib/lava/dispatcher/tmp/972876/tftp-deploy-rkkyrml0/nfsrootfs/full.rootfs.tar
95 01:07:25.886454 total size: 120894716 (115 MB)
96 01:07:25.886662 Using unxz to decompress xz
97 01:07:25.925520 progress 0 % (0 MB)
98 01:07:26.719748 progress 5 % (5 MB)
99 01:07:27.565544 progress 10 % (11 MB)
100 01:07:28.360773 progress 15 % (17 MB)
101 01:07:29.101546 progress 20 % (23 MB)
102 01:07:29.696816 progress 25 % (28 MB)
103 01:07:30.525069 progress 30 % (34 MB)
104 01:07:31.326570 progress 35 % (40 MB)
105 01:07:31.699697 progress 40 % (46 MB)
106 01:07:32.080082 progress 45 % (51 MB)
107 01:07:32.807153 progress 50 % (57 MB)
108 01:07:33.689841 progress 55 % (63 MB)
109 01:07:34.464479 progress 60 % (69 MB)
110 01:07:35.216204 progress 65 % (74 MB)
111 01:07:35.987588 progress 70 % (80 MB)
112 01:07:36.810688 progress 75 % (86 MB)
113 01:07:37.592266 progress 80 % (92 MB)
114 01:07:38.344626 progress 85 % (98 MB)
115 01:07:39.188235 progress 90 % (103 MB)
116 01:07:39.956203 progress 95 % (109 MB)
117 01:07:40.779930 progress 100 % (115 MB)
118 01:07:40.793238 115 MB downloaded in 14.91 s (7.73 MB/s)
119 01:07:40.794184 end: 1.4.1 http-download (duration 00:00:15) [common]
121 01:07:40.795965 end: 1.4 download-retry (duration 00:00:15) [common]
122 01:07:40.796614 start: 1.5 download-retry (timeout 00:09:44) [common]
123 01:07:40.797201 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 01:07:40.798254 downloading http://storage.kernelci.org/mainline/master/v6.12-rc7/arm64/defconfig/gcc-12/modules.tar.xz
125 01:07:40.798783 saving as /var/lib/lava/dispatcher/tmp/972876/tftp-deploy-rkkyrml0/modules/modules.tar
126 01:07:40.799242 total size: 11614384 (11 MB)
127 01:07:40.799713 Using unxz to decompress xz
128 01:07:40.847241 progress 0 % (0 MB)
129 01:07:40.915637 progress 5 % (0 MB)
130 01:07:40.989020 progress 10 % (1 MB)
131 01:07:41.086413 progress 15 % (1 MB)
132 01:07:41.177513 progress 20 % (2 MB)
133 01:07:41.258426 progress 25 % (2 MB)
134 01:07:41.333655 progress 30 % (3 MB)
135 01:07:41.411565 progress 35 % (3 MB)
136 01:07:41.483356 progress 40 % (4 MB)
137 01:07:41.558702 progress 45 % (5 MB)
138 01:07:41.641983 progress 50 % (5 MB)
139 01:07:41.718040 progress 55 % (6 MB)
140 01:07:41.801876 progress 60 % (6 MB)
141 01:07:41.881832 progress 65 % (7 MB)
142 01:07:41.961586 progress 70 % (7 MB)
143 01:07:42.039260 progress 75 % (8 MB)
144 01:07:42.122924 progress 80 % (8 MB)
145 01:07:42.215948 progress 85 % (9 MB)
146 01:07:42.296296 progress 90 % (9 MB)
147 01:07:42.374598 progress 95 % (10 MB)
148 01:07:42.452227 progress 100 % (11 MB)
149 01:07:42.464678 11 MB downloaded in 1.67 s (6.65 MB/s)
150 01:07:42.465605 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:07:42.467253 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:07:42.467804 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 01:07:42.468407 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 01:07:58.621386 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/972876/extract-nfsrootfs-5olb0djb
156 01:07:58.621998 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 01:07:58.622287 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 01:07:58.622881 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni
159 01:07:58.623331 makedir: /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin
160 01:07:58.623665 makedir: /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/tests
161 01:07:58.624021 makedir: /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/results
162 01:07:58.624363 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-add-keys
163 01:07:58.624920 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-add-sources
164 01:07:58.625461 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-background-process-start
165 01:07:58.625972 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-background-process-stop
166 01:07:58.626507 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-common-functions
167 01:07:58.627014 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-echo-ipv4
168 01:07:58.627511 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-install-packages
169 01:07:58.628022 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-installed-packages
170 01:07:58.628518 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-os-build
171 01:07:58.629007 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-probe-channel
172 01:07:58.629509 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-probe-ip
173 01:07:58.630045 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-target-ip
174 01:07:58.630532 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-target-mac
175 01:07:58.631011 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-target-storage
176 01:07:58.631498 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-test-case
177 01:07:58.632022 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-test-event
178 01:07:58.632552 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-test-feedback
179 01:07:58.633053 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-test-raise
180 01:07:58.633554 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-test-reference
181 01:07:58.634052 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-test-runner
182 01:07:58.634610 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-test-set
183 01:07:58.635099 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-test-shell
184 01:07:58.635597 Updating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-add-keys (debian)
185 01:07:58.636170 Updating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-add-sources (debian)
186 01:07:58.636697 Updating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-install-packages (debian)
187 01:07:58.637202 Updating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-installed-packages (debian)
188 01:07:58.637715 Updating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/bin/lava-os-build (debian)
189 01:07:58.638155 Creating /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/environment
190 01:07:58.638536 LAVA metadata
191 01:07:58.638796 - LAVA_JOB_ID=972876
192 01:07:58.639010 - LAVA_DISPATCHER_IP=192.168.6.2
193 01:07:58.639368 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 01:07:58.640426 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 01:07:58.640744 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 01:07:58.640950 skipped lava-vland-overlay
197 01:07:58.641187 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 01:07:58.641436 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 01:07:58.641648 skipped lava-multinode-overlay
200 01:07:58.641887 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 01:07:58.642136 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 01:07:58.642382 Loading test definitions
203 01:07:58.642653 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 01:07:58.642870 Using /lava-972876 at stage 0
205 01:07:58.643939 uuid=972876_1.6.2.4.1 testdef=None
206 01:07:58.644301 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 01:07:58.644566 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 01:07:58.646131 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 01:07:58.646911 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 01:07:58.648847 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 01:07:58.649659 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 01:07:58.651476 runner path: /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/0/tests/0_timesync-off test_uuid 972876_1.6.2.4.1
215 01:07:58.652045 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 01:07:58.652846 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 01:07:58.653067 Using /lava-972876 at stage 0
219 01:07:58.653415 Fetching tests from https://github.com/kernelci/test-definitions.git
220 01:07:58.653705 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/0/tests/1_kselftest-alsa'
221 01:08:02.066110 Running '/usr/bin/git checkout kernelci.org
222 01:08:02.175121 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 01:08:02.178273 uuid=972876_1.6.2.4.5 testdef=None
224 01:08:02.179072 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 01:08:02.181024 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
227 01:08:02.188033 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 01:08:02.190094 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
230 01:08:02.199460 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 01:08:02.201627 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
233 01:08:02.210799 runner path: /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/0/tests/1_kselftest-alsa test_uuid 972876_1.6.2.4.5
234 01:08:02.211481 BOARD='meson-g12b-a311d-libretech-cc'
235 01:08:02.212053 BRANCH='mainline'
236 01:08:02.212585 SKIPFILE='/dev/null'
237 01:08:02.213100 SKIP_INSTALL='True'
238 01:08:02.213608 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc7/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 01:08:02.214122 TST_CASENAME=''
240 01:08:02.214627 TST_CMDFILES='alsa'
241 01:08:02.215913 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 01:08:02.217953 Creating lava-test-runner.conf files
244 01:08:02.218479 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/972876/lava-overlay-5s_5dyni/lava-972876/0 for stage 0
245 01:08:02.219477 - 0_timesync-off
246 01:08:02.220130 - 1_kselftest-alsa
247 01:08:02.220981 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 01:08:02.221697 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
249 01:08:25.542876 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 01:08:25.543333 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
251 01:08:25.543598 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 01:08:25.543869 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 01:08:25.544162 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
254 01:08:26.153350 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 01:08:26.153830 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
256 01:08:26.154083 extracting modules file /var/lib/lava/dispatcher/tmp/972876/tftp-deploy-rkkyrml0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/972876/extract-nfsrootfs-5olb0djb
257 01:08:27.507318 extracting modules file /var/lib/lava/dispatcher/tmp/972876/tftp-deploy-rkkyrml0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/972876/extract-overlay-ramdisk-f1zag27t/ramdisk
258 01:08:29.060536 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 01:08:29.061039 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
260 01:08:29.061350 [common] Applying overlay to NFS
261 01:08:29.061673 [common] Applying overlay /var/lib/lava/dispatcher/tmp/972876/compress-overlay-85evv58q/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/972876/extract-nfsrootfs-5olb0djb
262 01:08:31.832992 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 01:08:31.833481 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 01:08:31.833759 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 01:08:31.833994 Converting downloaded kernel to a uImage
266 01:08:31.834324 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/972876/tftp-deploy-rkkyrml0/kernel/Image /var/lib/lava/dispatcher/tmp/972876/tftp-deploy-rkkyrml0/kernel/uImage
267 01:08:32.313078 output: Image Name:
268 01:08:32.313506 output: Created: Mon Nov 11 01:08:31 2024
269 01:08:32.313716 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 01:08:32.313921 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 01:08:32.314123 output: Load Address: 01080000
272 01:08:32.314323 output: Entry Point: 01080000
273 01:08:32.314520 output:
274 01:08:32.314855 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 01:08:32.315126 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 01:08:32.315395 start: 1.6.7 configure-preseed-file (timeout 00:08:53) [common]
277 01:08:32.315647 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 01:08:32.315904 start: 1.6.8 compress-ramdisk (timeout 00:08:53) [common]
279 01:08:32.316256 Building ramdisk /var/lib/lava/dispatcher/tmp/972876/extract-overlay-ramdisk-f1zag27t/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/972876/extract-overlay-ramdisk-f1zag27t/ramdisk
280 01:08:34.521341 >> 166829 blocks
281 01:08:42.262187 Adding RAMdisk u-boot header.
282 01:08:42.262853 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/972876/extract-overlay-ramdisk-f1zag27t/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/972876/extract-overlay-ramdisk-f1zag27t/ramdisk.cpio.gz.uboot
283 01:08:42.507374 output: Image Name:
284 01:08:42.507805 output: Created: Mon Nov 11 01:08:42 2024
285 01:08:42.508135 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 01:08:42.508601 output: Data Size: 23432716 Bytes = 22883.51 KiB = 22.35 MiB
287 01:08:42.509066 output: Load Address: 00000000
288 01:08:42.509505 output: Entry Point: 00000000
289 01:08:42.509945 output:
290 01:08:42.511088 rename /var/lib/lava/dispatcher/tmp/972876/extract-overlay-ramdisk-f1zag27t/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/972876/tftp-deploy-rkkyrml0/ramdisk/ramdisk.cpio.gz.uboot
291 01:08:42.511864 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 01:08:42.512510 end: 1.6 prepare-tftp-overlay (duration 00:01:00) [common]
293 01:08:42.513128 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:43) [common]
294 01:08:42.513619 No LXC device requested
295 01:08:42.514165 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 01:08:42.514720 start: 1.8 deploy-device-env (timeout 00:08:43) [common]
297 01:08:42.515259 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 01:08:42.515709 Checking files for TFTP limit of 4294967296 bytes.
299 01:08:42.518670 end: 1 tftp-deploy (duration 00:01:17) [common]
300 01:08:42.519299 start: 2 uboot-action (timeout 00:05:00) [common]
301 01:08:42.519872 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 01:08:42.520461 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 01:08:42.521011 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 01:08:42.521588 Using kernel file from prepare-kernel: 972876/tftp-deploy-rkkyrml0/kernel/uImage
305 01:08:42.522276 substitutions:
306 01:08:42.522724 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 01:08:42.523167 - {DTB_ADDR}: 0x01070000
308 01:08:42.523609 - {DTB}: 972876/tftp-deploy-rkkyrml0/dtb/meson-g12b-a311d-libretech-cc.dtb
309 01:08:42.524086 - {INITRD}: 972876/tftp-deploy-rkkyrml0/ramdisk/ramdisk.cpio.gz.uboot
310 01:08:42.524532 - {KERNEL_ADDR}: 0x01080000
311 01:08:42.524967 - {KERNEL}: 972876/tftp-deploy-rkkyrml0/kernel/uImage
312 01:08:42.525397 - {LAVA_MAC}: None
313 01:08:42.525872 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/972876/extract-nfsrootfs-5olb0djb
314 01:08:42.526308 - {NFS_SERVER_IP}: 192.168.6.2
315 01:08:42.526738 - {PRESEED_CONFIG}: None
316 01:08:42.527169 - {PRESEED_LOCAL}: None
317 01:08:42.527601 - {RAMDISK_ADDR}: 0x08000000
318 01:08:42.528054 - {RAMDISK}: 972876/tftp-deploy-rkkyrml0/ramdisk/ramdisk.cpio.gz.uboot
319 01:08:42.528492 - {ROOT_PART}: None
320 01:08:42.528921 - {ROOT}: None
321 01:08:42.529349 - {SERVER_IP}: 192.168.6.2
322 01:08:42.529774 - {TEE_ADDR}: 0x83000000
323 01:08:42.530199 - {TEE}: None
324 01:08:42.530623 Parsed boot commands:
325 01:08:42.531037 - setenv autoload no
326 01:08:42.531461 - setenv initrd_high 0xffffffff
327 01:08:42.531882 - setenv fdt_high 0xffffffff
328 01:08:42.532337 - dhcp
329 01:08:42.532761 - setenv serverip 192.168.6.2
330 01:08:42.533188 - tftpboot 0x01080000 972876/tftp-deploy-rkkyrml0/kernel/uImage
331 01:08:42.533619 - tftpboot 0x08000000 972876/tftp-deploy-rkkyrml0/ramdisk/ramdisk.cpio.gz.uboot
332 01:08:42.534046 - tftpboot 0x01070000 972876/tftp-deploy-rkkyrml0/dtb/meson-g12b-a311d-libretech-cc.dtb
333 01:08:42.534475 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/972876/extract-nfsrootfs-5olb0djb,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 01:08:42.534917 - bootm 0x01080000 0x08000000 0x01070000
335 01:08:42.535467 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 01:08:42.537140 start: 2.3 connect-device (timeout 00:05:00) [common]
338 01:08:42.537601 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 01:08:42.553445 Setting prompt string to ['lava-test: # ']
340 01:08:42.555100 end: 2.3 connect-device (duration 00:00:00) [common]
341 01:08:42.555770 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 01:08:42.556442 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 01:08:42.557051 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 01:08:42.558574 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 01:08:42.652348 >> OK - accepted request
346 01:08:42.655683 Returned 0 in 0 seconds
347 01:08:42.756941 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 01:08:42.758663 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 01:08:42.759281 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 01:08:42.759845 Setting prompt string to ['Hit any key to stop autoboot']
352 01:08:42.760406 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 01:08:42.762127 Trying 192.168.56.21...
354 01:08:42.762647 Connected to conserv1.
355 01:08:42.763120 Escape character is '^]'.
356 01:08:42.763589
357 01:08:42.764091 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 01:08:42.764571
359 01:08:53.665626 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 01:08:53.666310 bl2_stage_init 0x01
361 01:08:53.666809 bl2_stage_init 0x81
362 01:08:53.671144 hw id: 0x0000 - pwm id 0x01
363 01:08:53.671724 bl2_stage_init 0xc1
364 01:08:53.672250 bl2_stage_init 0x02
365 01:08:53.672709
366 01:08:53.676784 L0:00000000
367 01:08:53.677305 L1:20000703
368 01:08:53.677762 L2:00008067
369 01:08:53.678203 L3:14000000
370 01:08:53.682279 B2:00402000
371 01:08:53.682777 B1:e0f83180
372 01:08:53.683231
373 01:08:53.683663 TE: 58159
374 01:08:53.684131
375 01:08:53.687897 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 01:08:53.688410
377 01:08:53.688846 Board ID = 1
378 01:08:53.693504 Set A53 clk to 24M
379 01:08:53.693974 Set A73 clk to 24M
380 01:08:53.694403 Set clk81 to 24M
381 01:08:53.699009 A53 clk: 1200 MHz
382 01:08:53.699476 A73 clk: 1200 MHz
383 01:08:53.699904 CLK81: 166.6M
384 01:08:53.700359 smccc: 00012ab4
385 01:08:53.704622 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 01:08:53.710248 board id: 1
387 01:08:53.716119 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 01:08:53.726839 fw parse done
389 01:08:53.732814 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 01:08:53.775386 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 01:08:53.786258 PIEI prepare done
392 01:08:53.786746 fastboot data load
393 01:08:53.787185 fastboot data verify
394 01:08:53.792084 verify result: 266
395 01:08:53.797579 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 01:08:53.798097 LPDDR4 probe
397 01:08:53.798532 ddr clk to 1584MHz
398 01:08:53.805600 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 01:08:53.842869
400 01:08:53.843447 dmc_version 0001
401 01:08:53.849584 Check phy result
402 01:08:53.855425 INFO : End of CA training
403 01:08:53.856025 INFO : End of initialization
404 01:08:53.861097 INFO : Training has run successfully!
405 01:08:53.861685 Check phy result
406 01:08:53.866626 INFO : End of initialization
407 01:08:53.867213 INFO : End of read enable training
408 01:08:53.872286 INFO : End of fine write leveling
409 01:08:53.877831 INFO : End of Write leveling coarse delay
410 01:08:53.878414 INFO : Training has run successfully!
411 01:08:53.878888 Check phy result
412 01:08:53.883472 INFO : End of initialization
413 01:08:53.884084 INFO : End of read dq deskew training
414 01:08:53.889084 INFO : End of MPR read delay center optimization
415 01:08:53.894620 INFO : End of write delay center optimization
416 01:08:53.900314 INFO : End of read delay center optimization
417 01:08:53.900895 INFO : End of max read latency training
418 01:08:53.905893 INFO : Training has run successfully!
419 01:08:53.906482 1D training succeed
420 01:08:53.915011 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 01:08:53.962605 Check phy result
422 01:08:53.963182 INFO : End of initialization
423 01:08:53.984343 INFO : End of 2D read delay Voltage center optimization
424 01:08:54.004278 INFO : End of 2D read delay Voltage center optimization
425 01:08:54.056210 INFO : End of 2D write delay Voltage center optimization
426 01:08:54.105455 INFO : End of 2D write delay Voltage center optimization
427 01:08:54.111029 INFO : Training has run successfully!
428 01:08:54.111565
429 01:08:54.112086 channel==0
430 01:08:54.116647 RxClkDly_Margin_A0==88 ps 9
431 01:08:54.117172 TxDqDly_Margin_A0==98 ps 10
432 01:08:54.119965 RxClkDly_Margin_A1==88 ps 9
433 01:08:54.120523 TxDqDly_Margin_A1==98 ps 10
434 01:08:54.125487 TrainedVREFDQ_A0==74
435 01:08:54.126012 TrainedVREFDQ_A1==74
436 01:08:54.126474 VrefDac_Margin_A0==25
437 01:08:54.131248 DeviceVref_Margin_A0==40
438 01:08:54.131776 VrefDac_Margin_A1==25
439 01:08:54.136790 DeviceVref_Margin_A1==40
440 01:08:54.137318
441 01:08:54.137776
442 01:08:54.138225 channel==1
443 01:08:54.138667 RxClkDly_Margin_A0==88 ps 9
444 01:08:54.140286 TxDqDly_Margin_A0==98 ps 10
445 01:08:54.145615 RxClkDly_Margin_A1==98 ps 10
446 01:08:54.146148 TxDqDly_Margin_A1==88 ps 9
447 01:08:54.146605 TrainedVREFDQ_A0==77
448 01:08:54.151303 TrainedVREFDQ_A1==77
449 01:08:54.151833 VrefDac_Margin_A0==22
450 01:08:54.156921 DeviceVref_Margin_A0==37
451 01:08:54.157469 VrefDac_Margin_A1==22
452 01:08:54.157930 DeviceVref_Margin_A1==37
453 01:08:54.158377
454 01:08:54.165938 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 01:08:54.166473
456 01:08:54.191698 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
457 01:08:54.197437 2D training succeed
458 01:08:54.200920 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 01:08:54.206390 auto size-- 65535DDR cs0 size: 2048MB
460 01:08:54.206916 DDR cs1 size: 2048MB
461 01:08:54.212055 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 01:08:54.212587 cs0 DataBus test pass
463 01:08:54.217593 cs1 DataBus test pass
464 01:08:54.218122 cs0 AddrBus test pass
465 01:08:54.218577 cs1 AddrBus test pass
466 01:08:54.219021
467 01:08:54.223192 100bdlr_step_size ps== 420
468 01:08:54.223732 result report
469 01:08:54.228786 boot times 0Enable ddr reg access
470 01:08:54.234372 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 01:08:54.247291 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 01:08:54.819268 0.0;M3 CHK:0;cm4_sp_mode 0
473 01:08:54.819884 MVN_1=0x00000000
474 01:08:54.824732 MVN_2=0x00000000
475 01:08:54.830477 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 01:08:54.830976 OPS=0x10
477 01:08:54.831434 ring efuse init
478 01:08:54.831908 chipver efuse init
479 01:08:54.838716 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 01:08:54.839234 [0.018961 Inits done]
481 01:08:54.846278 secure task start!
482 01:08:54.846780 high task start!
483 01:08:54.847233 low task start!
484 01:08:54.847680 run into bl31
485 01:08:54.852976 NOTICE: BL31: v1.3(release):4fc40b1
486 01:08:54.860743 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 01:08:54.861242 NOTICE: BL31: G12A normal boot!
488 01:08:54.886168 NOTICE: BL31: BL33 decompress pass
489 01:08:54.891773 ERROR: Error initializing runtime service opteed_fast
490 01:08:56.124782
491 01:08:56.125460
492 01:08:56.133137 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 01:08:56.133700
494 01:08:56.134180 Model: Libre Computer AML-A311D-CC Alta
495 01:08:56.341495 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 01:08:56.364849 DRAM: 2 GiB (effective 3.8 GiB)
497 01:08:56.507887 Core: 408 devices, 31 uclasses, devicetree: separate
498 01:08:56.513745 WDT: Not starting watchdog@f0d0
499 01:08:56.546033 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 01:08:56.558454 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 01:08:56.563482 ** Bad device specification mmc 0 **
502 01:08:56.573789 Card did not respond to voltage select! : -110
503 01:08:56.581428 ** Bad device specification mmc 0 **
504 01:08:56.581924 Couldn't find partition mmc 0
505 01:08:56.589772 Card did not respond to voltage select! : -110
506 01:08:56.595367 ** Bad device specification mmc 0 **
507 01:08:56.595858 Couldn't find partition mmc 0
508 01:08:56.600433 Error: could not access storage.
509 01:08:57.865831 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 01:08:57.866503 bl2_stage_init 0x01
511 01:08:57.866979 bl2_stage_init 0x81
512 01:08:57.871442 hw id: 0x0000 - pwm id 0x01
513 01:08:57.871936 bl2_stage_init 0xc1
514 01:08:57.872444 bl2_stage_init 0x02
515 01:08:57.872896
516 01:08:57.876940 L0:00000000
517 01:08:57.877419 L1:20000703
518 01:08:57.877868 L2:00008067
519 01:08:57.878308 L3:14000000
520 01:08:57.882553 B2:00402000
521 01:08:57.883032 B1:e0f83180
522 01:08:57.883474
523 01:08:57.883919 TE: 58124
524 01:08:57.884402
525 01:08:57.888181 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 01:08:57.888666
527 01:08:57.889115 Board ID = 1
528 01:08:57.893741 Set A53 clk to 24M
529 01:08:57.894221 Set A73 clk to 24M
530 01:08:57.894669 Set clk81 to 24M
531 01:08:57.899431 A53 clk: 1200 MHz
532 01:08:57.899905 A73 clk: 1200 MHz
533 01:08:57.900398 CLK81: 166.6M
534 01:08:57.900840 smccc: 00012a91
535 01:08:57.904965 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 01:08:57.910601 board id: 1
537 01:08:57.916538 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 01:08:57.927082 fw parse done
539 01:08:57.933055 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 01:08:57.975724 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 01:08:57.986607 PIEI prepare done
542 01:08:57.987090 fastboot data load
543 01:08:57.987545 fastboot data verify
544 01:08:57.992183 verify result: 266
545 01:08:57.997798 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 01:08:57.998271 LPDDR4 probe
547 01:08:57.998718 ddr clk to 1584MHz
548 01:08:58.005815 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 01:08:58.043031
550 01:08:58.043546 dmc_version 0001
551 01:08:58.049705 Check phy result
552 01:08:58.055618 INFO : End of CA training
553 01:08:58.056127 INFO : End of initialization
554 01:08:58.061165 INFO : Training has run successfully!
555 01:08:58.061640 Check phy result
556 01:08:58.066747 INFO : End of initialization
557 01:08:58.067235 INFO : End of read enable training
558 01:08:58.072487 INFO : End of fine write leveling
559 01:08:58.078006 INFO : End of Write leveling coarse delay
560 01:08:58.078487 INFO : Training has run successfully!
561 01:08:58.078936 Check phy result
562 01:08:58.083598 INFO : End of initialization
563 01:08:58.084110 INFO : End of read dq deskew training
564 01:08:58.089161 INFO : End of MPR read delay center optimization
565 01:08:58.094777 INFO : End of write delay center optimization
566 01:08:58.100482 INFO : End of read delay center optimization
567 01:08:58.100953 INFO : End of max read latency training
568 01:08:58.106031 INFO : Training has run successfully!
569 01:08:58.106523 1D training succeed
570 01:08:58.115161 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 01:08:58.162796 Check phy result
572 01:08:58.163313 INFO : End of initialization
573 01:08:58.184494 INFO : End of 2D read delay Voltage center optimization
574 01:08:58.204714 INFO : End of 2D read delay Voltage center optimization
575 01:08:58.256789 INFO : End of 2D write delay Voltage center optimization
576 01:08:58.306192 INFO : End of 2D write delay Voltage center optimization
577 01:08:58.311796 INFO : Training has run successfully!
578 01:08:58.312356
579 01:08:58.312815 channel==0
580 01:08:58.317337 RxClkDly_Margin_A0==88 ps 9
581 01:08:58.317835 TxDqDly_Margin_A0==98 ps 10
582 01:08:58.322968 RxClkDly_Margin_A1==88 ps 9
583 01:08:58.323475 TxDqDly_Margin_A1==98 ps 10
584 01:08:58.323931 TrainedVREFDQ_A0==74
585 01:08:58.328600 TrainedVREFDQ_A1==74
586 01:08:58.329112 VrefDac_Margin_A0==25
587 01:08:58.329559 DeviceVref_Margin_A0==40
588 01:08:58.334118 VrefDac_Margin_A1==25
589 01:08:58.334616 DeviceVref_Margin_A1==40
590 01:08:58.335066
591 01:08:58.335516
592 01:08:58.339742 channel==1
593 01:08:58.340294 RxClkDly_Margin_A0==98 ps 10
594 01:08:58.340751 TxDqDly_Margin_A0==98 ps 10
595 01:08:58.345430 RxClkDly_Margin_A1==88 ps 9
596 01:08:58.345943 TxDqDly_Margin_A1==88 ps 9
597 01:08:58.350933 TrainedVREFDQ_A0==76
598 01:08:58.351461 TrainedVREFDQ_A1==77
599 01:08:58.351913 VrefDac_Margin_A0==22
600 01:08:58.356733 DeviceVref_Margin_A0==38
601 01:08:58.357242 VrefDac_Margin_A1==24
602 01:08:58.362225 DeviceVref_Margin_A1==37
603 01:08:58.362721
604 01:08:58.363173 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 01:08:58.363620
606 01:08:58.395718 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
607 01:08:58.396295 2D training succeed
608 01:08:58.401306 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 01:08:58.406839 auto size-- 65535DDR cs0 size: 2048MB
610 01:08:58.407324 DDR cs1 size: 2048MB
611 01:08:58.412612 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 01:08:58.413212 cs0 DataBus test pass
613 01:08:58.418180 cs1 DataBus test pass
614 01:08:58.418783 cs0 AddrBus test pass
615 01:08:58.419239 cs1 AddrBus test pass
616 01:08:58.419688
617 01:08:58.423731 100bdlr_step_size ps== 420
618 01:08:58.424261 result report
619 01:08:58.429292 boot times 0Enable ddr reg access
620 01:08:58.434629 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 01:08:58.448149 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 01:08:59.021890 0.0;M3 CHK:0;cm4_sp_mode 0
623 01:08:59.022495 MVN_1=0x00000000
624 01:08:59.027364 MVN_2=0x00000000
625 01:08:59.033109 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 01:08:59.033650 OPS=0x10
627 01:08:59.034105 ring efuse init
628 01:08:59.034577 chipver efuse init
629 01:08:59.038767 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 01:08:59.044300 [0.018961 Inits done]
631 01:08:59.044773 secure task start!
632 01:08:59.045203 high task start!
633 01:08:59.048866 low task start!
634 01:08:59.049329 run into bl31
635 01:08:59.055651 NOTICE: BL31: v1.3(release):4fc40b1
636 01:08:59.063362 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 01:08:59.063834 NOTICE: BL31: G12A normal boot!
638 01:08:59.088804 NOTICE: BL31: BL33 decompress pass
639 01:08:59.094461 ERROR: Error initializing runtime service opteed_fast
640 01:09:00.327492
641 01:09:00.327929
642 01:09:00.335918 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 01:09:00.336224
644 01:09:00.336474 Model: Libre Computer AML-A311D-CC Alta
645 01:09:00.544273 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 01:09:00.567720 DRAM: 2 GiB (effective 3.8 GiB)
647 01:09:00.710661 Core: 408 devices, 31 uclasses, devicetree: separate
648 01:09:00.716534 WDT: Not starting watchdog@f0d0
649 01:09:00.748781 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 01:09:00.761157 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 01:09:00.766183 ** Bad device specification mmc 0 **
652 01:09:00.776498 Card did not respond to voltage select! : -110
653 01:09:00.784171 ** Bad device specification mmc 0 **
654 01:09:00.784440 Couldn't find partition mmc 0
655 01:09:00.792480 Card did not respond to voltage select! : -110
656 01:09:00.797998 ** Bad device specification mmc 0 **
657 01:09:00.798265 Couldn't find partition mmc 0
658 01:09:00.803074 Error: could not access storage.
659 01:09:01.146897 Net: eth0: ethernet@ff3f0000
660 01:09:01.147336 starting USB...
661 01:09:01.398637 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 01:09:01.399283 Starting the controller
663 01:09:01.405511 USB XHCI 1.10
664 01:09:03.116219 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 01:09:03.116680 bl2_stage_init 0x01
666 01:09:03.116918 bl2_stage_init 0x81
667 01:09:03.121826 hw id: 0x0000 - pwm id 0x01
668 01:09:03.122278 bl2_stage_init 0xc1
669 01:09:03.122626 bl2_stage_init 0x02
670 01:09:03.122971
671 01:09:03.127358 L0:00000000
672 01:09:03.127794 L1:20000703
673 01:09:03.128194 L2:00008067
674 01:09:03.128435 L3:14000000
675 01:09:03.133068 B2:00402000
676 01:09:03.133520 B1:e0f83180
677 01:09:03.133874
678 01:09:03.134217 TE: 58159
679 01:09:03.134533
680 01:09:03.138654 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 01:09:03.138949
682 01:09:03.139161 Board ID = 1
683 01:09:03.144210 Set A53 clk to 24M
684 01:09:03.144615 Set A73 clk to 24M
685 01:09:03.144940 Set clk81 to 24M
686 01:09:03.149841 A53 clk: 1200 MHz
687 01:09:03.150238 A73 clk: 1200 MHz
688 01:09:03.150552 CLK81: 166.6M
689 01:09:03.150785 smccc: 00012ab5
690 01:09:03.155343 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 01:09:03.161028 board id: 1
692 01:09:03.166905 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 01:09:03.177419 fw parse done
694 01:09:03.183371 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 01:09:03.226046 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 01:09:03.236953 PIEI prepare done
697 01:09:03.237435 fastboot data load
698 01:09:03.237894 fastboot data verify
699 01:09:03.242631 verify result: 266
700 01:09:03.248214 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 01:09:03.248685 LPDDR4 probe
702 01:09:03.249132 ddr clk to 1584MHz
703 01:09:03.256209 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 01:09:03.293465
705 01:09:03.293944 dmc_version 0001
706 01:09:03.300205 Check phy result
707 01:09:03.306083 INFO : End of CA training
708 01:09:03.306549 INFO : End of initialization
709 01:09:03.311647 INFO : Training has run successfully!
710 01:09:03.312164 Check phy result
711 01:09:03.317245 INFO : End of initialization
712 01:09:03.317719 INFO : End of read enable training
713 01:09:03.322831 INFO : End of fine write leveling
714 01:09:03.328462 INFO : End of Write leveling coarse delay
715 01:09:03.328927 INFO : Training has run successfully!
716 01:09:03.329371 Check phy result
717 01:09:03.334042 INFO : End of initialization
718 01:09:03.334510 INFO : End of read dq deskew training
719 01:09:03.339635 INFO : End of MPR read delay center optimization
720 01:09:03.345248 INFO : End of write delay center optimization
721 01:09:03.350838 INFO : End of read delay center optimization
722 01:09:03.351311 INFO : End of max read latency training
723 01:09:03.356458 INFO : Training has run successfully!
724 01:09:03.356938 1D training succeed
725 01:09:03.365655 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 01:09:03.413208 Check phy result
727 01:09:03.413712 INFO : End of initialization
728 01:09:03.435071 INFO : End of 2D read delay Voltage center optimization
729 01:09:03.455197 INFO : End of 2D read delay Voltage center optimization
730 01:09:03.507287 INFO : End of 2D write delay Voltage center optimization
731 01:09:03.556721 INFO : End of 2D write delay Voltage center optimization
732 01:09:03.562182 INFO : Training has run successfully!
733 01:09:03.562664
734 01:09:03.563113 channel==0
735 01:09:03.567910 RxClkDly_Margin_A0==88 ps 9
736 01:09:03.568460 TxDqDly_Margin_A0==98 ps 10
737 01:09:03.571033 RxClkDly_Margin_A1==88 ps 9
738 01:09:03.571507 TxDqDly_Margin_A1==98 ps 10
739 01:09:03.576558 TrainedVREFDQ_A0==74
740 01:09:03.577035 TrainedVREFDQ_A1==74
741 01:09:03.582187 VrefDac_Margin_A0==25
742 01:09:03.582658 DeviceVref_Margin_A0==40
743 01:09:03.583106 VrefDac_Margin_A1==25
744 01:09:03.587731 DeviceVref_Margin_A1==40
745 01:09:03.588231
746 01:09:03.588685
747 01:09:03.589128 channel==1
748 01:09:03.589565 RxClkDly_Margin_A0==98 ps 10
749 01:09:03.593320 TxDqDly_Margin_A0==98 ps 10
750 01:09:03.593800 RxClkDly_Margin_A1==98 ps 10
751 01:09:03.599060 TxDqDly_Margin_A1==88 ps 9
752 01:09:03.599549 TrainedVREFDQ_A0==77
753 01:09:03.600026 TrainedVREFDQ_A1==77
754 01:09:03.604668 VrefDac_Margin_A0==22
755 01:09:03.605137 DeviceVref_Margin_A0==37
756 01:09:03.610232 VrefDac_Margin_A1==24
757 01:09:03.610703 DeviceVref_Margin_A1==37
758 01:09:03.611143
759 01:09:03.615772 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 01:09:03.616273
761 01:09:03.643764 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
762 01:09:03.649373 2D training succeed
763 01:09:03.654939 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 01:09:03.655413 auto size-- 65535DDR cs0 size: 2048MB
765 01:09:03.660579 DDR cs1 size: 2048MB
766 01:09:03.661048 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 01:09:03.666254 cs0 DataBus test pass
768 01:09:03.666725 cs1 DataBus test pass
769 01:09:03.667166 cs0 AddrBus test pass
770 01:09:03.671775 cs1 AddrBus test pass
771 01:09:03.672285
772 01:09:03.672733 100bdlr_step_size ps== 420
773 01:09:03.673187 result report
774 01:09:03.677370 boot times 0Enable ddr reg access
775 01:09:03.685203 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 01:09:03.698681 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 01:09:04.272591 0.0;M3 CHK:0;cm4_sp_mode 0
778 01:09:04.273223 MVN_1=0x00000000
779 01:09:04.277930 MVN_2=0x00000000
780 01:09:04.283728 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 01:09:04.284344 OPS=0x10
782 01:09:04.284790 ring efuse init
783 01:09:04.285216 chipver efuse init
784 01:09:04.289282 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 01:09:04.294805 [0.018960 Inits done]
786 01:09:04.295262 secure task start!
787 01:09:04.295693 high task start!
788 01:09:04.299541 low task start!
789 01:09:04.300029 run into bl31
790 01:09:04.306087 NOTICE: BL31: v1.3(release):4fc40b1
791 01:09:04.313916 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 01:09:04.314384 NOTICE: BL31: G12A normal boot!
793 01:09:04.339188 NOTICE: BL31: BL33 decompress pass
794 01:09:04.345005 ERROR: Error initializing runtime service opteed_fast
795 01:09:05.578071
796 01:09:05.578749
797 01:09:05.586250 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 01:09:05.586742
799 01:09:05.587200 Model: Libre Computer AML-A311D-CC Alta
800 01:09:05.794762 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 01:09:05.818087 DRAM: 2 GiB (effective 3.8 GiB)
802 01:09:05.961018 Core: 408 devices, 31 uclasses, devicetree: separate
803 01:09:05.966935 WDT: Not starting watchdog@f0d0
804 01:09:05.999184 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 01:09:06.011681 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 01:09:06.016735 ** Bad device specification mmc 0 **
807 01:09:06.026949 Card did not respond to voltage select! : -110
808 01:09:06.034591 ** Bad device specification mmc 0 **
809 01:09:06.035081 Couldn't find partition mmc 0
810 01:09:06.043049 Card did not respond to voltage select! : -110
811 01:09:06.048457 ** Bad device specification mmc 0 **
812 01:09:06.048941 Couldn't find partition mmc 0
813 01:09:06.053568 Error: could not access storage.
814 01:09:06.397137 Net: eth0: ethernet@ff3f0000
815 01:09:06.397702 starting USB...
816 01:09:06.649042 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 01:09:06.649670 Starting the controller
818 01:09:06.655921 USB XHCI 1.10
819 01:09:08.816402 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 01:09:08.817030 bl2_stage_init 0x01
821 01:09:08.817499 bl2_stage_init 0x81
822 01:09:08.821919 hw id: 0x0000 - pwm id 0x01
823 01:09:08.822406 bl2_stage_init 0xc1
824 01:09:08.822859 bl2_stage_init 0x02
825 01:09:08.823304
826 01:09:08.827534 L0:00000000
827 01:09:08.828042 L1:20000703
828 01:09:08.828494 L2:00008067
829 01:09:08.828936 L3:14000000
830 01:09:08.833240 B2:00402000
831 01:09:08.833718 B1:e0f83180
832 01:09:08.834163
833 01:09:08.834607 TE: 58159
834 01:09:08.835053
835 01:09:08.838732 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 01:09:08.839208
837 01:09:08.839652 Board ID = 1
838 01:09:08.844362 Set A53 clk to 24M
839 01:09:08.844832 Set A73 clk to 24M
840 01:09:08.845271 Set clk81 to 24M
841 01:09:08.849860 A53 clk: 1200 MHz
842 01:09:08.850330 A73 clk: 1200 MHz
843 01:09:08.850776 CLK81: 166.6M
844 01:09:08.851211 smccc: 00012ab4
845 01:09:08.855541 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 01:09:08.861221 board id: 1
847 01:09:08.867086 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 01:09:08.877484 fw parse done
849 01:09:08.883486 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 01:09:08.926167 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 01:09:08.937066 PIEI prepare done
852 01:09:08.937537 fastboot data load
853 01:09:08.937983 fastboot data verify
854 01:09:08.942633 verify result: 266
855 01:09:08.948223 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 01:09:08.948697 LPDDR4 probe
857 01:09:08.949142 ddr clk to 1584MHz
858 01:09:08.956246 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 01:09:08.993431
860 01:09:08.993907 dmc_version 0001
861 01:09:09.000196 Check phy result
862 01:09:09.006096 INFO : End of CA training
863 01:09:09.006563 INFO : End of initialization
864 01:09:09.011581 INFO : Training has run successfully!
865 01:09:09.012091 Check phy result
866 01:09:09.017214 INFO : End of initialization
867 01:09:09.017683 INFO : End of read enable training
868 01:09:09.022800 INFO : End of fine write leveling
869 01:09:09.028409 INFO : End of Write leveling coarse delay
870 01:09:09.028897 INFO : Training has run successfully!
871 01:09:09.029347 Check phy result
872 01:09:09.034068 INFO : End of initialization
873 01:09:09.034541 INFO : End of read dq deskew training
874 01:09:09.039539 INFO : End of MPR read delay center optimization
875 01:09:09.045225 INFO : End of write delay center optimization
876 01:09:09.050794 INFO : End of read delay center optimization
877 01:09:09.051276 INFO : End of max read latency training
878 01:09:09.056407 INFO : Training has run successfully!
879 01:09:09.056883 1D training succeed
880 01:09:09.065581 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 01:09:09.113241 Check phy result
882 01:09:09.113714 INFO : End of initialization
883 01:09:09.134954 INFO : End of 2D read delay Voltage center optimization
884 01:09:09.155196 INFO : End of 2D read delay Voltage center optimization
885 01:09:09.207248 INFO : End of 2D write delay Voltage center optimization
886 01:09:09.256662 INFO : End of 2D write delay Voltage center optimization
887 01:09:09.262234 INFO : Training has run successfully!
888 01:09:09.262701
889 01:09:09.263148 channel==0
890 01:09:09.267815 RxClkDly_Margin_A0==88 ps 9
891 01:09:09.268333 TxDqDly_Margin_A0==98 ps 10
892 01:09:09.273384 RxClkDly_Margin_A1==88 ps 9
893 01:09:09.273851 TxDqDly_Margin_A1==98 ps 10
894 01:09:09.274318 TrainedVREFDQ_A0==74
895 01:09:09.278994 TrainedVREFDQ_A1==74
896 01:09:09.279502 VrefDac_Margin_A0==25
897 01:09:09.279946 DeviceVref_Margin_A0==40
898 01:09:09.284612 VrefDac_Margin_A1==25
899 01:09:09.285109 DeviceVref_Margin_A1==40
900 01:09:09.285538
901 01:09:09.285962
902 01:09:09.290225 channel==1
903 01:09:09.290681 RxClkDly_Margin_A0==98 ps 10
904 01:09:09.291106 TxDqDly_Margin_A0==88 ps 9
905 01:09:09.295801 RxClkDly_Margin_A1==98 ps 10
906 01:09:09.296290 TxDqDly_Margin_A1==88 ps 9
907 01:09:09.301402 TrainedVREFDQ_A0==74
908 01:09:09.301881 TrainedVREFDQ_A1==77
909 01:09:09.302310 VrefDac_Margin_A0==22
910 01:09:09.307018 DeviceVref_Margin_A0==40
911 01:09:09.307471 VrefDac_Margin_A1==22
912 01:09:09.312594 DeviceVref_Margin_A1==37
913 01:09:09.313047
914 01:09:09.313477 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 01:09:09.313904
916 01:09:09.346216 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
917 01:09:09.346706 2D training succeed
918 01:09:09.351811 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 01:09:09.357409 auto size-- 65535DDR cs0 size: 2048MB
920 01:09:09.357871 DDR cs1 size: 2048MB
921 01:09:09.363045 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 01:09:09.363501 cs0 DataBus test pass
923 01:09:09.368599 cs1 DataBus test pass
924 01:09:09.369053 cs0 AddrBus test pass
925 01:09:09.369480 cs1 AddrBus test pass
926 01:09:09.369899
927 01:09:09.374212 100bdlr_step_size ps== 420
928 01:09:09.374679 result report
929 01:09:09.379824 boot times 0Enable ddr reg access
930 01:09:09.385325 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 01:09:09.398615 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 01:09:09.972448 0.0;M3 CHK:0;cm4_sp_mode 0
933 01:09:09.973092 MVN_1=0x00000000
934 01:09:09.977760 MVN_2=0x00000000
935 01:09:09.983512 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 01:09:09.984031 OPS=0x10
937 01:09:09.984494 ring efuse init
938 01:09:09.984935 chipver efuse init
939 01:09:09.989213 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 01:09:09.994705 [0.018961 Inits done]
941 01:09:09.995174 secure task start!
942 01:09:09.995614 high task start!
943 01:09:09.999325 low task start!
944 01:09:09.999791 run into bl31
945 01:09:10.005913 NOTICE: BL31: v1.3(release):4fc40b1
946 01:09:10.013720 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 01:09:10.014196 NOTICE: BL31: G12A normal boot!
948 01:09:10.039223 NOTICE: BL31: BL33 decompress pass
949 01:09:10.044816 ERROR: Error initializing runtime service opteed_fast
950 01:09:11.277779
951 01:09:11.278378
952 01:09:11.286071 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 01:09:11.286557
954 01:09:11.287023 Model: Libre Computer AML-A311D-CC Alta
955 01:09:11.494762 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 01:09:11.517942 DRAM: 2 GiB (effective 3.8 GiB)
957 01:09:11.660901 Core: 408 devices, 31 uclasses, devicetree: separate
958 01:09:11.666770 WDT: Not starting watchdog@f0d0
959 01:09:11.698983 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 01:09:11.711482 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 01:09:11.716501 ** Bad device specification mmc 0 **
962 01:09:11.726781 Card did not respond to voltage select! : -110
963 01:09:11.734539 ** Bad device specification mmc 0 **
964 01:09:11.735007 Couldn't find partition mmc 0
965 01:09:11.742768 Card did not respond to voltage select! : -110
966 01:09:11.748327 ** Bad device specification mmc 0 **
967 01:09:11.748796 Couldn't find partition mmc 0
968 01:09:11.753400 Error: could not access storage.
969 01:09:12.095852 Net: eth0: ethernet@ff3f0000
970 01:09:12.096437 starting USB...
971 01:09:12.347678 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 01:09:12.348241 Starting the controller
973 01:09:12.354636 USB XHCI 1.10
974 01:09:14.216145 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 01:09:14.216741 bl2_stage_init 0x01
976 01:09:14.217195 bl2_stage_init 0x81
977 01:09:14.221796 hw id: 0x0000 - pwm id 0x01
978 01:09:14.222272 bl2_stage_init 0xc1
979 01:09:14.222717 bl2_stage_init 0x02
980 01:09:14.223158
981 01:09:14.227343 L0:00000000
982 01:09:14.227813 L1:20000703
983 01:09:14.228321 L2:00008067
984 01:09:14.228769 L3:14000000
985 01:09:14.230253 B2:00402000
986 01:09:14.230723 B1:e0f83180
987 01:09:14.231168
988 01:09:14.231610 TE: 58167
989 01:09:14.232086
990 01:09:14.241357 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 01:09:14.241832
992 01:09:14.242276 Board ID = 1
993 01:09:14.242714 Set A53 clk to 24M
994 01:09:14.243147 Set A73 clk to 24M
995 01:09:14.247061 Set clk81 to 24M
996 01:09:14.247527 A53 clk: 1200 MHz
997 01:09:14.247969 A73 clk: 1200 MHz
998 01:09:14.252646 CLK81: 166.6M
999 01:09:14.253117 smccc: 00012abd
1000 01:09:14.258215 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 01:09:14.258683 board id: 1
1002 01:09:14.266895 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 01:09:14.278427 fw parse done
1004 01:09:14.283673 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 01:09:14.325992 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 01:09:14.337136 PIEI prepare done
1007 01:09:14.337593 fastboot data load
1008 01:09:14.338026 fastboot data verify
1009 01:09:14.342470 verify result: 266
1010 01:09:14.348086 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 01:09:14.348550 LPDDR4 probe
1012 01:09:14.348977 ddr clk to 1584MHz
1013 01:09:14.356057 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 01:09:14.393293
1015 01:09:14.393774 dmc_version 0001
1016 01:09:14.399962 Check phy result
1017 01:09:14.405830 INFO : End of CA training
1018 01:09:14.406290 INFO : End of initialization
1019 01:09:14.411443 INFO : Training has run successfully!
1020 01:09:14.411903 Check phy result
1021 01:09:14.417144 INFO : End of initialization
1022 01:09:14.417689 INFO : End of read enable training
1023 01:09:14.422715 INFO : End of fine write leveling
1024 01:09:14.428318 INFO : End of Write leveling coarse delay
1025 01:09:14.428790 INFO : Training has run successfully!
1026 01:09:14.429238 Check phy result
1027 01:09:14.433866 INFO : End of initialization
1028 01:09:14.434335 INFO : End of read dq deskew training
1029 01:09:14.439467 INFO : End of MPR read delay center optimization
1030 01:09:14.445036 INFO : End of write delay center optimization
1031 01:09:14.450710 INFO : End of read delay center optimization
1032 01:09:14.451177 INFO : End of max read latency training
1033 01:09:14.456237 INFO : Training has run successfully!
1034 01:09:14.456710 1D training succeed
1035 01:09:14.465388 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 01:09:14.513057 Check phy result
1037 01:09:14.513557 INFO : End of initialization
1038 01:09:14.534611 INFO : End of 2D read delay Voltage center optimization
1039 01:09:14.554729 INFO : End of 2D read delay Voltage center optimization
1040 01:09:14.606603 INFO : End of 2D write delay Voltage center optimization
1041 01:09:14.655892 INFO : End of 2D write delay Voltage center optimization
1042 01:09:14.661429 INFO : Training has run successfully!
1043 01:09:14.661902
1044 01:09:14.662355 channel==0
1045 01:09:14.667013 RxClkDly_Margin_A0==88 ps 9
1046 01:09:14.667482 TxDqDly_Margin_A0==98 ps 10
1047 01:09:14.672611 RxClkDly_Margin_A1==88 ps 9
1048 01:09:14.673088 TxDqDly_Margin_A1==98 ps 10
1049 01:09:14.673535 TrainedVREFDQ_A0==74
1050 01:09:14.678200 TrainedVREFDQ_A1==74
1051 01:09:14.678672 VrefDac_Margin_A0==25
1052 01:09:14.679115 DeviceVref_Margin_A0==40
1053 01:09:14.683923 VrefDac_Margin_A1==25
1054 01:09:14.684423 DeviceVref_Margin_A1==40
1055 01:09:14.684864
1056 01:09:14.685303
1057 01:09:14.689421 channel==1
1058 01:09:14.689890 RxClkDly_Margin_A0==98 ps 10
1059 01:09:14.690329 TxDqDly_Margin_A0==98 ps 10
1060 01:09:14.695016 RxClkDly_Margin_A1==88 ps 9
1061 01:09:14.695487 TxDqDly_Margin_A1==88 ps 9
1062 01:09:14.700626 TrainedVREFDQ_A0==77
1063 01:09:14.701096 TrainedVREFDQ_A1==77
1064 01:09:14.701539 VrefDac_Margin_A0==22
1065 01:09:14.706212 DeviceVref_Margin_A0==37
1066 01:09:14.706677 VrefDac_Margin_A1==24
1067 01:09:14.711874 DeviceVref_Margin_A1==37
1068 01:09:14.712369
1069 01:09:14.712812 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 01:09:14.713247
1071 01:09:14.745413 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1072 01:09:14.745910 2D training succeed
1073 01:09:14.751006 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 01:09:14.756630 auto size-- 65535DDR cs0 size: 2048MB
1075 01:09:14.757097 DDR cs1 size: 2048MB
1076 01:09:14.762210 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 01:09:14.762675 cs0 DataBus test pass
1078 01:09:14.767881 cs1 DataBus test pass
1079 01:09:14.768384 cs0 AddrBus test pass
1080 01:09:14.768827 cs1 AddrBus test pass
1081 01:09:14.769268
1082 01:09:14.773406 100bdlr_step_size ps== 420
1083 01:09:14.773887 result report
1084 01:09:14.778999 boot times 0Enable ddr reg access
1085 01:09:14.784357 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 01:09:14.797825 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 01:09:15.369950 0.0;M3 CHK:0;cm4_sp_mode 0
1088 01:09:15.370487 MVN_1=0x00000000
1089 01:09:15.375372 MVN_2=0x00000000
1090 01:09:15.381139 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 01:09:15.381621 OPS=0x10
1092 01:09:15.382073 ring efuse init
1093 01:09:15.382515 chipver efuse init
1094 01:09:15.386729 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 01:09:15.392338 [0.018961 Inits done]
1096 01:09:15.392807 secure task start!
1097 01:09:15.393251 high task start!
1098 01:09:15.396903 low task start!
1099 01:09:15.397370 run into bl31
1100 01:09:15.403509 NOTICE: BL31: v1.3(release):4fc40b1
1101 01:09:15.411306 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 01:09:15.411791 NOTICE: BL31: G12A normal boot!
1103 01:09:15.437382 NOTICE: BL31: BL33 decompress pass
1104 01:09:15.443046 ERROR: Error initializing runtime service opteed_fast
1105 01:09:16.676025
1106 01:09:16.676723
1107 01:09:16.684266 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 01:09:16.684810
1109 01:09:16.685271 Model: Libre Computer AML-A311D-CC Alta
1110 01:09:16.892693 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 01:09:16.916086 DRAM: 2 GiB (effective 3.8 GiB)
1112 01:09:17.059182 Core: 408 devices, 31 uclasses, devicetree: separate
1113 01:09:17.064902 WDT: Not starting watchdog@f0d0
1114 01:09:17.097242 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 01:09:17.109640 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 01:09:17.113675 ** Bad device specification mmc 0 **
1117 01:09:17.124947 Card did not respond to voltage select! : -110
1118 01:09:17.132599 ** Bad device specification mmc 0 **
1119 01:09:17.133071 Couldn't find partition mmc 0
1120 01:09:17.140967 Card did not respond to voltage select! : -110
1121 01:09:17.146467 ** Bad device specification mmc 0 **
1122 01:09:17.146935 Couldn't find partition mmc 0
1123 01:09:17.151521 Error: could not access storage.
1124 01:09:17.495039 Net: eth0: ethernet@ff3f0000
1125 01:09:17.495645 starting USB...
1126 01:09:17.746796 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 01:09:17.747338 Starting the controller
1128 01:09:17.753794 USB XHCI 1.10
1129 01:09:19.307921 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 01:09:19.316330 scanning usb for storage devices... 0 Storage Device(s) found
1132 01:09:19.367945 Hit any key to stop autoboot: 1
1133 01:09:19.368755 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 01:09:19.369370 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 01:09:19.369872 Setting prompt string to ['=>']
1136 01:09:19.370378 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 01:09:19.383853 0
1138 01:09:19.384788 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 01:09:19.385319 Sending with 10 millisecond of delay
1141 01:09:20.520073 => setenv autoload no
1142 01:09:20.530912 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 01:09:20.536337 setenv autoload no
1144 01:09:20.537137 Sending with 10 millisecond of delay
1146 01:09:22.334866 => setenv initrd_high 0xffffffff
1147 01:09:22.345710 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 01:09:22.346629 setenv initrd_high 0xffffffff
1149 01:09:22.347353 Sending with 10 millisecond of delay
1151 01:09:23.964102 => setenv fdt_high 0xffffffff
1152 01:09:23.974865 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1153 01:09:23.975677 setenv fdt_high 0xffffffff
1154 01:09:23.976429 Sending with 10 millisecond of delay
1156 01:09:24.268297 => dhcp
1157 01:09:24.278996 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 01:09:24.279789 dhcp
1159 01:09:24.280288 Speed: 1000, full duplex
1160 01:09:24.280704 BOOTP broadcast 1
1161 01:09:24.287691 DHCP client bound to address 192.168.6.27 (9 ms)
1162 01:09:24.288430 Sending with 10 millisecond of delay
1164 01:09:25.964649 => setenv serverip 192.168.6.2
1165 01:09:25.975439 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1166 01:09:25.976349 setenv serverip 192.168.6.2
1167 01:09:25.977037 Sending with 10 millisecond of delay
1169 01:09:29.700079 => tftpboot 0x01080000 972876/tftp-deploy-rkkyrml0/kernel/uImage
1170 01:09:29.710878 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1171 01:09:29.711678 tftpboot 0x01080000 972876/tftp-deploy-rkkyrml0/kernel/uImage
1172 01:09:29.712156 Speed: 1000, full duplex
1173 01:09:29.712571 Using ethernet@ff3f0000 device
1174 01:09:29.713607 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 01:09:29.719226 Filename '972876/tftp-deploy-rkkyrml0/kernel/uImage'.
1176 01:09:29.723102 Load address: 0x1080000
1177 01:09:31.658189 Loading: *################################## UDP wrong checksum 000000ff 000089ec
1178 01:09:31.717958 ## UDP wrong checksum 000000ff 00001adf
1179 01:09:32.489647 ############## 43.6 MiB
1180 01:09:32.490286 15.7 MiB/s
1181 01:09:32.490721 done
1182 01:09:32.493239 Bytes transferred = 45713984 (2b98a40 hex)
1183 01:09:32.493985 Sending with 10 millisecond of delay
1185 01:09:37.180097 => tftpboot 0x08000000 972876/tftp-deploy-rkkyrml0/ramdisk/ramdisk.cpio.gz.uboot
1186 01:09:37.190897 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1187 01:09:37.191778 tftpboot 0x08000000 972876/tftp-deploy-rkkyrml0/ramdisk/ramdisk.cpio.gz.uboot
1188 01:09:37.192258 Speed: 1000, full duplex
1189 01:09:37.192656 Using ethernet@ff3f0000 device
1190 01:09:37.193358 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1191 01:09:37.205125 Filename '972876/tftp-deploy-rkkyrml0/ramdisk/ramdisk.cpio.gz.uboot'.
1192 01:09:37.205561 Load address: 0x8000000
1193 01:09:43.976340 Loading: *#####################T ############################# 22.3 MiB
1194 01:09:43.977003 3.3 MiB/s
1195 01:09:43.977479 done
1196 01:09:43.980724 Bytes transferred = 23432780 (1658e4c hex)
1197 01:09:43.981539 Sending with 10 millisecond of delay
1199 01:09:49.150389 => tftpboot 0x01070000 972876/tftp-deploy-rkkyrml0/dtb/meson-g12b-a311d-libretech-cc.dtb
1200 01:09:49.161210 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:53)
1201 01:09:49.162092 tftpboot 0x01070000 972876/tftp-deploy-rkkyrml0/dtb/meson-g12b-a311d-libretech-cc.dtb
1202 01:09:49.162603 Speed: 1000, full duplex
1203 01:09:49.163068 Using ethernet@ff3f0000 device
1204 01:09:49.166105 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1205 01:09:49.173570 Filename '972876/tftp-deploy-rkkyrml0/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1206 01:09:49.184748 Load address: 0x1070000
1207 01:09:49.192399 Loading: *################################################## 53.4 KiB
1208 01:09:49.199900 3.1 MiB/s
1209 01:09:49.200445 done
1210 01:09:49.200901 Bytes transferred = 54703 (d5af hex)
1211 01:09:49.201627 Sending with 10 millisecond of delay
1213 01:10:02.499477 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/972876/extract-nfsrootfs-5olb0djb,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1214 01:10:02.510403 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:40)
1215 01:10:02.511377 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/972876/extract-nfsrootfs-5olb0djb,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1216 01:10:02.512146 Sending with 10 millisecond of delay
1218 01:10:04.851151 => bootm 0x01080000 0x08000000 0x01070000
1219 01:10:04.861716 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1220 01:10:04.862113 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:38)
1221 01:10:04.862738 bootm 0x01080000 0x08000000 0x01070000
1222 01:10:04.863074 ## Booting kernel from Legacy Image at 01080000 ...
1223 01:10:04.866521 Image Name:
1224 01:10:04.872055 Image Type: AArch64 Linux Kernel Image (uncompressed)
1225 01:10:04.872389 Data Size: 45713920 Bytes = 43.6 MiB
1226 01:10:04.877503 Load Address: 01080000
1227 01:10:04.877806 Entry Point: 01080000
1228 01:10:05.073035 Verifying Checksum ... OK
1229 01:10:05.073686 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1230 01:10:05.078346 Image Name:
1231 01:10:05.083956 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1232 01:10:05.084563 Data Size: 23432716 Bytes = 22.3 MiB
1233 01:10:05.089375 Load Address: 00000000
1234 01:10:05.089910 Entry Point: 00000000
1235 01:10:05.191623 Verifying Checksum ... OK
1236 01:10:05.192330 ## Flattened Device Tree blob at 01070000
1237 01:10:05.197069 Booting using the fdt blob at 0x1070000
1238 01:10:05.197596 Working FDT set to 1070000
1239 01:10:05.201539 Loading Kernel Image
1240 01:10:05.352381 Loading Ramdisk to 7e9a7000, end 7ffffe0c ... OK
1241 01:10:05.358060 Loading Device Tree to 000000007e996000, end 000000007e9a65ae ... OK
1242 01:10:05.358591 Working FDT set to 7e996000
1243 01:10:05.363941
1244 01:10:05.364502 Starting kernel ...
1245 01:10:05.364958
1246 01:10:05.365899 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1247 01:10:05.366528 start: 2.4.4 auto-login-action (timeout 00:03:37) [common]
1248 01:10:05.367035 Setting prompt string to ['Linux version [0-9]']
1249 01:10:05.367534 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1250 01:10:05.368073 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1251 01:10:05.400889 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1252 01:10:05.401983 start: 2.4.4.1 login-action (timeout 00:03:37) [common]
1253 01:10:05.402561 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1254 01:10:05.403071 Setting prompt string to []
1255 01:10:05.403605 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1256 01:10:05.404138 Using line separator: #'\n'#
1257 01:10:05.404594 No login prompt set.
1258 01:10:05.405075 Parsing kernel messages
1259 01:10:05.405511 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1260 01:10:05.406534 [login-action] Waiting for messages, (timeout 00:03:37)
1261 01:10:05.407170 Waiting using forced prompt support (timeout 00:01:49)
1262 01:10:05.420862 [ 0.000000] Linux version 6.12.0-rc7 (KernelCI@build-j372199-arm64-gcc-12-defconfig-psj5g) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Sun Nov 10 23:05:43 UTC 2024
1263 01:10:05.421512 [ 0.000000] KASLR disabled due to lack of seed
1264 01:10:05.426437 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1265 01:10:05.431935 [ 0.000000] efi: UEFI not found.
1266 01:10:05.437419 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1267 01:10:05.448425 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1268 01:10:05.454006 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1269 01:10:05.465104 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1270 01:10:05.476088 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1271 01:10:05.487131 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1272 01:10:05.492725 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1273 01:10:05.498250 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1274 01:10:05.503756 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1275 01:10:05.509257 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1276 01:10:05.514848 [ 0.000000] Zone ranges:
1277 01:10:05.520334 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1278 01:10:05.520873 [ 0.000000] DMA32 empty
1279 01:10:05.525938 [ 0.000000] Normal empty
1280 01:10:05.531343 [ 0.000000] Movable zone start for each node
1281 01:10:05.531882 [ 0.000000] Early memory node ranges
1282 01:10:05.536884 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1283 01:10:05.542405 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1284 01:10:05.553329 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1285 01:10:05.558602 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1286 01:10:05.582719 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1287 01:10:05.588247 [ 0.000000] psci: probing for conduit method from DT.
1288 01:10:05.588568 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1289 01:10:05.597484 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1290 01:10:05.598084 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1291 01:10:05.603027 [ 0.000000] psci: SMC Calling Convention v1.1
1292 01:10:05.608496 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1293 01:10:05.612067 [ 0.000000] Detected VIPT I-cache on CPU0
1294 01:10:05.617660 [ 0.000000] CPU features: detected: ARM erratum 845719
1295 01:10:05.623156 [ 0.000000] alternatives: applying boot alternatives
1296 01:10:05.645123 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/972876/extract-nfsrootfs-5olb0djb,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1297 01:10:05.656233 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1298 01:10:05.661736 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1299 01:10:05.667248 <6>[ 0.000000] Fallback order for Node 0: 0
1300 01:10:05.672771 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1301 01:10:05.678318 <6>[ 0.000000] Policy zone: DMA
1302 01:10:05.683706 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1303 01:10:05.689209 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1304 01:10:05.694721 <6>[ 0.000000] software IO TLB: area num 8.
1305 01:10:05.702141 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1306 01:10:05.748723 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1307 01:10:05.754215 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1308 01:10:05.757848 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1309 01:10:05.763202 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1310 01:10:05.768746 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1311 01:10:05.774266 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1312 01:10:05.785276 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1313 01:10:05.790892 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1314 01:10:05.796306 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1315 01:10:05.807359 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1316 01:10:05.812917 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1317 01:10:05.818379 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1318 01:10:05.823918 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1319 01:10:05.830348 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1320 01:10:05.842991 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1321 01:10:05.854009 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1322 01:10:05.859568 <6>[ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1323 01:10:05.865077 <6>[ 0.008798] Console: colour dummy device 80x25
1324 01:10:05.876155 <6>[ 0.012941] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1325 01:10:05.881621 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1326 01:10:05.887138 <6>[ 0.028190] LSM: initializing lsm=capability
1327 01:10:05.892743 <6>[ 0.032729] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1328 01:10:05.898192 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1329 01:10:05.903726 <6>[ 0.052301] rcu: Hierarchical SRCU implementation.
1330 01:10:05.909237 <6>[ 0.053214] rcu: Max phase no-delay instances is 1000.
1331 01:10:05.920256 <6>[ 0.058875] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1332 01:10:05.928718 <6>[ 0.071569] EFI services will not be available.
1333 01:10:05.929062 <6>[ 0.075219] smp: Bringing up secondary CPUs ...
1334 01:10:05.948903 <6>[ 0.077131] Detected VIPT I-cache on CPU1
1335 01:10:05.954381 <6>[ 0.077250] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1336 01:10:05.959920 <6>[ 0.078581] CPU features: detected: Spectre-v2
1337 01:10:05.965760 <6>[ 0.078596] CPU features: detected: Spectre-v4
1338 01:10:05.971022 <6>[ 0.078601] CPU features: detected: Spectre-BHB
1339 01:10:05.976471 <6>[ 0.078607] CPU features: detected: ARM erratum 858921
1340 01:10:05.982071 <6>[ 0.078615] Detected VIPT I-cache on CPU2
1341 01:10:05.987581 <6>[ 0.078689] arch_timer: Enabling local workaround for ARM erratum 858921
1342 01:10:05.993036 <6>[ 0.078707] arch_timer: CPU2: Trapping CNTVCT access
1343 01:10:05.998566 <6>[ 0.078717] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1344 01:10:06.004105 <6>[ 0.083567] Detected VIPT I-cache on CPU3
1345 01:10:06.009653 <6>[ 0.083613] arch_timer: Enabling local workaround for ARM erratum 858921
1346 01:10:06.015193 <6>[ 0.083623] arch_timer: CPU3: Trapping CNTVCT access
1347 01:10:06.020633 <6>[ 0.083630] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1348 01:10:06.026212 <6>[ 0.087606] Detected VIPT I-cache on CPU4
1349 01:10:06.031758 <6>[ 0.087653] arch_timer: Enabling local workaround for ARM erratum 858921
1350 01:10:06.037179 <6>[ 0.087663] arch_timer: CPU4: Trapping CNTVCT access
1351 01:10:06.048217 <6>[ 0.087670] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1352 01:10:06.048532 <6>[ 0.099544] Detected VIPT I-cache on CPU5
1353 01:10:06.059260 <6>[ 0.099592] arch_timer: Enabling local workaround for ARM erratum 858921
1354 01:10:06.059589 <6>[ 0.099602] arch_timer: CPU5: Trapping CNTVCT access
1355 01:10:06.070332 <6>[ 0.099609] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1356 01:10:06.070630 <6>[ 0.099724] smp: Brought up 1 node, 6 CPUs
1357 01:10:06.075886 <6>[ 0.220961] SMP: Total of 6 processors activated.
1358 01:10:06.081365 <6>[ 0.225862] CPU: All CPU(s) started at EL2
1359 01:10:06.086968 <6>[ 0.230204] CPU features: detected: 32-bit EL0 Support
1360 01:10:06.092458 <6>[ 0.235522] CPU features: detected: 32-bit EL1 Support
1361 01:10:06.097980 <6>[ 0.240868] CPU features: detected: CRC32 instructions
1362 01:10:06.103402 <6>[ 0.246269] alternatives: applying system-wide alternatives
1363 01:10:06.121412 <6>[ 0.253448] Memory: 3557436K/4012396K available (17280K kernel code, 4898K rwdata, 11876K rodata, 10432K init, 742K bss, 187796K reserved, 262144K cma-reserved)
1364 01:10:06.122027 <6>[ 0.267803] devtmpfs: initialized
1365 01:10:06.132534 <6>[ 0.276955] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1366 01:10:06.138078 <6>[ 0.281313] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1367 01:10:06.143552 <6>[ 0.292105] 21392 pages in range for non-PLT usage
1368 01:10:06.149082 <6>[ 0.292115] 512912 pages in range for PLT usage
1369 01:10:06.154548 <6>[ 0.293674] pinctrl core: initialized pinctrl subsystem
1370 01:10:06.160119 <6>[ 0.305727] DMI not present or invalid.
1371 01:10:06.165564 <6>[ 0.310043] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1372 01:10:06.171067 <6>[ 0.314791] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1373 01:10:06.182119 <6>[ 0.321565] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1374 01:10:06.187648 <6>[ 0.329664] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1375 01:10:06.193276 <6>[ 0.337145] audit: initializing netlink subsys (disabled)
1376 01:10:06.204277 <5>[ 0.342880] audit: type=2000 audit(0.264:1): state=initialized audit_enabled=0 res=1
1377 01:10:06.209818 <6>[ 0.344310] thermal_sys: Registered thermal governor 'step_wise'
1378 01:10:06.215325 <6>[ 0.350649] thermal_sys: Registered thermal governor 'power_allocator'
1379 01:10:06.220917 <6>[ 0.356909] cpuidle: using governor menu
1380 01:10:06.226450 <6>[ 0.367948] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1381 01:10:06.231933 <6>[ 0.374826] ASID allocator initialised with 65536 entries
1382 01:10:06.240232 <6>[ 0.382385] Serial: AMBA PL011 UART driver
1383 01:10:06.248058 <6>[ 0.392937] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1384 01:10:06.263036 <6>[ 0.408334] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1385 01:10:06.272289 <6>[ 0.410996] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1386 01:10:06.277509 <6>[ 0.424110] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1387 01:10:06.288576 <6>[ 0.427375] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1388 01:10:06.294084 <6>[ 0.435797] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1389 01:10:06.305109 <6>[ 0.443423] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1390 01:10:06.310612 <6>[ 0.456994] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1391 01:10:06.316119 <6>[ 0.459243] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1392 01:10:06.327260 <6>[ 0.465724] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1393 01:10:06.332721 <6>[ 0.472702] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1394 01:10:06.338240 <6>[ 0.479171] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1395 01:10:06.343727 <6>[ 0.486157] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1396 01:10:06.349253 <6>[ 0.492626] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1397 01:10:06.360313 <6>[ 0.499611] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1398 01:10:06.360857 <6>[ 0.507630] ACPI: Interpreter disabled.
1399 01:10:06.365811 <6>[ 0.512984] iommu: Default domain type: Translated
1400 01:10:06.371337 <6>[ 0.515145] iommu: DMA domain TLB invalidation policy: strict mode
1401 01:10:06.376965 <5>[ 0.521830] SCSI subsystem initialized
1402 01:10:06.382378 <6>[ 0.525717] usbcore: registered new interface driver usbfs
1403 01:10:06.388016 <6>[ 0.531202] usbcore: registered new interface driver hub
1404 01:10:06.393386 <6>[ 0.536726] usbcore: registered new device driver usb
1405 01:10:06.399015 <6>[ 0.542983] pps_core: LinuxPPS API ver. 1 registered
1406 01:10:06.410565 <6>[ 0.547138] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1407 01:10:06.411119 <6>[ 0.556457] PTP clock support registered
1408 01:10:06.415607 <6>[ 0.560695] EDAC MC: Ver: 3.0.0
1409 01:10:06.421019 <6>[ 0.564344] scmi_core: SCMI protocol bus registered
1410 01:10:06.427056 <6>[ 0.570010] FPGA manager framework
1411 01:10:06.432168 <6>[ 0.572735] Advanced Linux Sound Architecture Driver Initialized.
1412 01:10:06.432645 <6>[ 0.579671] vgaarb: loaded
1413 01:10:06.437612 <6>[ 0.582211] clocksource: Switched to clocksource arch_sys_counter
1414 01:10:06.443141 <5>[ 0.588368] VFS: Disk quotas dquot_6.6.0
1415 01:10:06.448651 <6>[ 0.592353] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1416 01:10:06.454177 <6>[ 0.599561] pnp: PnP ACPI: disabled
1417 01:10:06.459689 <6>[ 0.608061] NET: Registered PF_INET protocol family
1418 01:10:06.465249 <6>[ 0.608384] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1419 01:10:06.476300 <6>[ 0.618555] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1420 01:10:06.481771 <6>[ 0.624556] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1421 01:10:06.492836 <6>[ 0.632449] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1422 01:10:06.498332 <6>[ 0.640689] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1423 01:10:06.509399 <6>[ 0.648479] TCP: Hash tables configured (established 32768 bind 32768)
1424 01:10:06.515006 <6>[ 0.654960] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1425 01:10:06.520802 <6>[ 0.661806] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1426 01:10:06.526099 <6>[ 0.669240] NET: Registered PF_UNIX/PF_LOCAL protocol family
1427 01:10:06.531562 <6>[ 0.675337] RPC: Registered named UNIX socket transport module.
1428 01:10:06.537178 <6>[ 0.681096] RPC: Registered udp transport module.
1429 01:10:06.542561 <6>[ 0.686001] RPC: Registered tcp transport module.
1430 01:10:06.548151 <6>[ 0.690915] RPC: Registered tcp-with-tls transport module.
1431 01:10:06.553810 <6>[ 0.696608] RPC: Registered tcp NFSv4.1 backchannel transport module.
1432 01:10:06.559089 <6>[ 0.703256] PCI: CLS 0 bytes, default 64
1433 01:10:06.564949 <6>[ 0.707574] Unpacking initramfs...
1434 01:10:06.570503 <6>[ 0.716859] kvm [1]: nv: 554 coarse grained trap handlers
1435 01:10:06.575898 <6>[ 0.717169] kvm [1]: IPA Size Limit: 40 bits
1436 01:10:06.576263 <6>[ 0.722827] kvm [1]: vgic interrupt IRQ9
1437 01:10:06.581449 <6>[ 0.725532] kvm [1]: Hyp nVHE mode initialized successfully
1438 01:10:06.587015 <5>[ 0.732758] Initialise system trusted keyrings
1439 01:10:06.592432 <6>[ 0.736133] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1440 01:10:06.598023 <6>[ 0.742850] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1441 01:10:06.603482 <5>[ 0.748896] NFS: Registering the id_resolver key type
1442 01:10:06.609465 <5>[ 0.753925] Key type id_resolver registered
1443 01:10:06.614533 <5>[ 0.758289] Key type id_legacy registered
1444 01:10:06.620132 <6>[ 0.762542] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1445 01:10:06.631240 <6>[ 0.769415] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1446 01:10:06.635617 <6>[ 0.777193] 9p: Installing v9fs 9p2000 file system support
1447 01:10:06.673252 <5>[ 0.823893] Key type asymmetric registered
1448 01:10:06.678734 <5>[ 0.823935] Asymmetric key parser 'x509' registered
1449 01:10:06.689762 <6>[ 0.827793] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1450 01:10:06.690284 <6>[ 0.835317] io scheduler mq-deadline registered
1451 01:10:06.695241 <6>[ 0.840057] io scheduler kyber registered
1452 01:10:06.700757 <6>[ 0.844319] io scheduler bfq registered
1453 01:10:06.706242 <6>[ 0.850219] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1454 01:10:06.723254 <6>[ 0.870275] ledtrig-cpu: registered to indicate activity on CPUs
1455 01:10:06.755638 <6>[ 0.901396] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1456 01:10:06.774803 <6>[ 0.914347] Serial: 8250/16550 driver, 4 ports<6>[ 0.918928] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1457 01:10:06.778161 <6>[ 0.928548] printk: legacy console [ttyAML0] enabled
1458 01:10:06.783765 <6>[ 0.928548] printk: legacy console [ttyAML0] enabled
1459 01:10:06.789277 <6>[ 0.933355] printk: legacy bootconsole [meson0] disabled
1460 01:10:06.795075 <6>[ 0.933355] printk: legacy bootconsole [meson0] disabled
1461 01:10:06.798300 <6>[ 0.947064] msm_serial: driver initialized
1462 01:10:06.803811 <6>[ 0.949260] SuperH (H)SCI(F) driver initialized
1463 01:10:06.809400 <6>[ 0.953815] STM32 USART driver initialized
1464 01:10:06.815062 <5>[ 0.960014] random: crng init done
1465 01:10:06.815554 <6>[ 0.965562] loop: module loaded
1466 01:10:06.818448 <6>[ 0.966850] megasas: 07.727.03.00-rc1
1467 01:10:06.825207 <6>[ 0.975938] tun: Universal TUN/TAP device driver, 1.6
1468 01:10:06.830790 <6>[ 0.977138] thunder_xcv, ver 1.0
1469 01:10:06.836368 <6>[ 0.979119] thunder_bgx, ver 1.0
1470 01:10:06.836951 <6>[ 0.982575] nicpf, ver 1.0
1471 01:10:06.847409 <6>[ 0.987147] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1472 01:10:06.853015 <6>[ 0.992960] hns3: Copyright (c) 2017 Huawei Corporation.
1473 01:10:06.853529 <6>[ 0.998560] hclge is initializing
1474 01:10:06.858526 <6>[ 1.002077] e1000: Intel(R) PRO/1000 Network Driver
1475 01:10:06.864158 <6>[ 1.007171] e1000: Copyright (c) 1999-2006 Intel Corporation.
1476 01:10:06.869576 <6>[ 1.013192] e1000e: Intel(R) PRO/1000 Network Driver
1477 01:10:06.875146 <6>[ 1.018349] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1478 01:10:06.880663 <6>[ 1.024534] igb: Intel(R) Gigabit Ethernet Network Driver
1479 01:10:06.886287 <6>[ 1.030134] igb: Copyright (c) 2007-2014 Intel Corporation.
1480 01:10:06.891776 <6>[ 1.035965] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1481 01:10:06.902883 <6>[ 1.042442] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1482 01:10:06.903393 <6>[ 1.049204] sky2: driver version 1.30
1483 01:10:06.908561 <6>[ 1.054329] VFIO - User Level meta-driver version: 0.3
1484 01:10:06.914092 <6>[ 1.061792] usbcore: registered new interface driver usb-storage
1485 01:10:06.920725 <6>[ 1.067946] i2c_dev: i2c /dev entries driver
1486 01:10:06.933985 <6>[ 1.079021] sdhci: Secure Digital Host Controller Interface driver
1487 01:10:06.934565 <6>[ 1.079821] sdhci: Copyright(c) Pierre Ossman
1488 01:10:06.945088 <6>[ 1.085539] Synopsys Designware Multimedia Card Interface Driver
1489 01:10:06.950608 <6>[ 1.092073] sdhci-pltfm: SDHCI platform and OF driver helper
1490 01:10:06.951099 <6>[ 1.099740] meson-sm: secure-monitor enabled
1491 01:10:06.963536 <6>[ 1.102200] usbcore: registered new interface driver usbhid
1492 01:10:06.964068 <6>[ 1.106875] usbhid: USB HID core driver
1493 01:10:06.971096 <6>[ 1.121702] NET: Registered PF_PACKET protocol family
1494 01:10:06.976616 <6>[ 1.121794] 9pnet: Installing 9P2000 support
1495 01:10:06.984060 <5>[ 1.125968] Key type dns_resolver registered
1496 01:10:06.989211 <6>[ 1.137536] registered taskstats version 1
1497 01:10:06.994735 <5>[ 1.137691] Loading compiled-in X.509 certificates
1498 01:10:06.998405 <6>[ 1.146370] Demotion targets for Node 0: null
1499 01:10:07.027476 <6>[ 1.178080] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1500 01:10:07.032962 <6>[ 1.178120] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1501 01:10:07.043964 <4>[ 1.187356] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1502 01:10:07.049573 <4>[ 1.190863] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1503 01:10:07.055151 <6>[ 1.198402] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1504 01:10:07.060971 <6>[ 1.207703] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1505 01:10:07.071740 <6>[ 1.211179] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1506 01:10:07.082828 <6>[ 1.219154] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1507 01:10:07.088467 <6>[ 1.228689] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1508 01:10:07.093896 <6>[ 1.234906] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1509 01:10:07.099456 <6>[ 1.240529] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1510 01:10:07.105074 <6>[ 1.248415] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1511 01:10:07.110545 <6>[ 1.255665] hub 1-0:1.0: USB hub found
1512 01:10:07.116142 <6>[ 1.259191] hub 1-0:1.0: 2 ports detected
1513 01:10:07.121636 <6>[ 1.265236] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1514 01:10:07.127214 <6>[ 1.272189] hub 2-0:1.0: USB hub found
1515 01:10:07.132290 <6>[ 1.275733] hub 2-0:1.0: 1 port detected
1516 01:10:07.158735 <6>[ 1.306853] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1517 01:10:07.176330 <6>[ 1.323714] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1518 01:10:07.209884 <6>[ 1.357887] Trying to probe devices needed for running init ...
1519 01:10:07.367808 <6>[ 1.514230] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1520 01:10:07.508452 <6>[ 1.653581] mmc0: new ultra high speed SDR104 SDXC card at address e624
1521 01:10:07.514911 <6>[ 1.655587] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1522 01:10:07.515353 <6>[ 1.661610] mmcblk0: p1
1523 01:10:07.517812 <6>[ 1.668735] Freeing initrd memory: 22880K
1524 01:10:07.552860 <6>[ 1.703498] hub 1-1:1.0: USB hub found
1525 01:10:07.558572 <6>[ 1.703801] hub 1-1:1.0: 4 ports detected
1526 01:10:07.623939 <6>[ 1.770360] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1527 01:10:07.665469 <6>[ 1.816148] hub 2-1:1.0: USB hub found
1528 01:10:07.671321 <6>[ 1.816977] hub 2-1:1.0: 4 ports detected
1529 01:10:19.495629 <6>[ 13.646271] clk: Disabling unused clocks
1530 01:10:19.501073 <6>[ 13.646439] PM: genpd: Disabling unused power domains
1531 01:10:19.508424 <6>[ 13.650134] ALSA device list:
1532 01:10:19.508925 <6>[ 13.653339] No soundcards found.
1533 01:10:19.514969 <6>[ 13.665804] Freeing unused kernel memory: 10432K
1534 01:10:19.520305 <6>[ 13.665907] Run /init as init process
1535 01:10:19.526174 Loading, please wait...
1536 01:10:19.557944 Starting systemd-udevd version 252.22-1~deb12u1
1537 01:10:20.018331 <6>[ 14.167981] mc: Linux media interface: v0.10
1538 01:10:20.050109 <6>[ 14.200786] meson-vrtc ff8000a8.rtc: registered as rtc0
1539 01:10:20.061003 <6>[ 14.200860] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1540 01:10:20.066561 <6>[ 14.201840] videodev: Linux video capture interface: v2.00
1541 01:10:20.074695 <4>[ 14.209663] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1542 01:10:20.081239 <6>[ 14.232090] panfrost ffe40000.gpu: clock rate = 24000000
1543 01:10:20.092303 <3>[ 14.232916] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1544 01:10:20.097917 <6>[ 14.241143] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1545 01:10:20.108988 <6>[ 14.248476] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1546 01:10:20.114519 <6>[ 14.254627] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1547 01:10:20.120066 <6>[ 14.255159] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1548 01:10:20.125717 <6>[ 14.255482] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1549 01:10:20.131262 <6>[ 14.261368] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1550 01:10:20.142344 <6>[ 14.270545] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1551 01:10:20.147859 <6>[ 14.286254] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1552 01:10:20.158966 <6>[ 14.288920] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1553 01:10:20.164594 <6>[ 14.296281] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1554 01:10:20.170073 <6>[ 14.308360] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1555 01:10:20.181121 <6>[ 14.313781] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1556 01:10:20.186789 <6>[ 14.313788] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1557 01:10:20.192242 <6>[ 14.335793] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1558 01:10:20.203335 <3>[ 14.335918] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1559 01:10:20.208917 <6>[ 14.341291] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1560 01:10:20.214578 <6>[ 14.356433] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1561 01:10:20.227774 <6>[ 14.372971] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1562 01:10:20.233293 <6>[ 14.373520] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1563 01:10:20.238872 <6>[ 14.378458] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1564 01:10:20.246130 <6>[ 14.379612] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1565 01:10:20.257220 <4>[ 14.402130] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1566 01:10:20.262883 <6>[ 14.409765] Registered IR keymap rc-empty
1567 01:10:20.268297 <6>[ 14.414663] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1568 01:10:20.279365 <6>[ 14.418305] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1569 01:10:20.288999 <6>[ 14.430582] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1570 01:10:20.298858 <6>[ 14.449539] rc rc0: sw decoder init
1571 01:10:20.305411 <6>[ 14.449612] meson-ir ff808000.ir: receiver initialized
1572 01:10:20.316520 <6>[ 14.459773] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1573 01:10:20.327628 <6>[ 14.461849] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1574 01:10:20.333157 <6>[ 14.461946] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1575 01:10:20.338801 <6>[ 14.462916] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1576 01:10:20.349892 <6>[ 14.489034] usbcore: registered new device driver onboard-usb-dev
1577 01:10:20.355354 <3>[ 14.489074] meson-drm ff900000.vpu: DSI transceiver device is disabled
1578 01:10:20.360080 <6>[ 14.502210] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1579 01:10:20.540413 <6>[ 14.666981] Console: switching to colour frame buffer device 128x48
1580 01:10:20.545342 <6>[ 14.686480] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1581 01:10:20.768791 <6>[ 14.919547] hub 1-1:1.0: USB hub found
1582 01:10:20.773539 <6>[ 14.919839] hub 1-1:1.0: 4 ports detected
1583 01:10:20.917050 <4>[ 15.062233] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1584 01:10:20.922570 <3>[ 15.064590] onboard-usb-dev 1-1: Failed to suspend device, error -32
1585 01:10:20.928609 <3>[ 15.071025] onboard-usb-dev 1-1: can't set config #1, error -71
1586 01:10:20.945033 <4>[ 15.090265] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1587 01:10:20.950549 <3>[ 15.092600] onboard-usb-dev 1-1: Failed to suspend device, error -32
1588 01:10:20.956668 <6>[ 15.092640] onboard-usb-dev 1-1: USB disconnect, device number 2
1589 01:10:21.108337 <6>[ 15.255470] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1590 01:10:21.242708 <6>[ 15.390239] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1591 01:10:21.440967 <6>[ 15.591585] hub 1-1:1.0: USB hub found
1592 01:10:21.445672 <6>[ 15.591929] hub 1-1:1.0: 4 ports detected
1593 01:10:21.459412 Begin: Loading essential drivers ... done.
1594 01:10:21.465062 Begin: Running /scripts/init-premount ... done.
1595 01:10:21.470510 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1596 01:10:21.479599 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1597 01:10:21.485081 Device /sys/class/net/end0 found
1598 01:10:21.485555 done.
1599 01:10:21.490562 Begin: Waiting up to 180 secs for any network device to become available ... done.
1600 01:10:21.526421 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.668642] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1601 01:10:21.526955
1602 01:10:21.614854 <6>[ 15.758336] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=35)
1603 01:10:21.629101 <6>[ 15.774354] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1604 01:10:21.634636 <6>[ 15.776542] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1605 01:10:21.643243 <6>[ 15.783891] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1606 01:10:22.263561 <4>[ 16.414216] rc rc0: two consecutive events of type space
1607 01:10:23.551073 IP-Config: no response after 2 secs - giving up
1608 01:10:23.601672 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1609 01:10:24.600116 <6>[ 18.745688] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1610 01:10:25.814903 IP-Config: end0 guessed broadcast address 192.168.6.255
1611 01:10:25.820265 IP-Config: end0 complete (dhcp from 192.168.6.1):
1612 01:10:25.825850 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1613 01:10:25.836925 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1614 01:10:25.837462 rootserver: 192.168.6.1 rootpath:
1615 01:10:25.839439 filename :
1616 01:10:25.970919 done.
1617 01:10:25.982306 Begin: Running /scripts/nfs-bottom ... done.
1618 01:10:25.993380 Begin: Running /scripts/init-bottom ... done.
1619 01:10:26.300151 <30>[ 20.447453] systemd[1]: System time before build time, advancing clock.
1620 01:10:26.358253 <6>[ 20.509050] NET: Registered PF_INET6 protocol family
1621 01:10:26.363756 <6>[ 20.510527] Segment Routing with IPv6
1622 01:10:26.368073 <6>[ 20.512557] In-situ OAM (IOAM) with IPv6
1623 01:10:26.444728 <30>[ 20.564492] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1624 01:10:26.448237 <30>[ 20.591888] systemd[1]: Detected architecture arm64.
1625 01:10:26.448535
1626 01:10:26.453332 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1627 01:10:26.453611
1628 01:10:26.463796 <30>[ 20.611852] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1629 01:10:27.126358 <30>[ 21.273052] systemd[1]: Queued start job for default target graphical.target.
1630 01:10:27.177513 <30>[ 21.322804] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1631 01:10:27.184094 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1632 01:10:27.202935 <30>[ 21.348175] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1633 01:10:27.210561 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1634 01:10:27.223287 <30>[ 21.368436] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1635 01:10:27.232342 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1636 01:10:27.243360 <30>[ 21.387780] systemd[1]: Created slice user.slice - User and Session Slice.
1637 01:10:27.248459 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1638 01:10:27.271220 <30>[ 21.410797] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1639 01:10:27.274812 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1640 01:10:27.293635 <30>[ 21.438740] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1641 01:10:27.302685 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1642 01:10:27.322733 <30>[ 21.458608] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1643 01:10:27.333751 <30>[ 21.472788] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1644 01:10:27.341374 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1645 01:10:27.348291 <30>[ 21.494461] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1646 01:10:27.356497 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1647 01:10:27.373509 <30>[ 21.518517] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1648 01:10:27.381822 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1649 01:10:27.393449 <30>[ 21.538575] systemd[1]: Reached target paths.target - Path Units.
1650 01:10:27.397549 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1651 01:10:27.409362 <30>[ 21.554493] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1652 01:10:27.415572 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1653 01:10:27.421082 <30>[ 21.570458] systemd[1]: Reached target slices.target - Slice Units.
1654 01:10:27.429759 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1655 01:10:27.441380 <30>[ 21.586515] systemd[1]: Reached target swap.target - Swaps.
1656 01:10:27.444504 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1657 01:10:27.457351 <30>[ 21.602505] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1658 01:10:27.465250 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1659 01:10:27.481731 <30>[ 21.626849] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1660 01:10:27.490108 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1661 01:10:27.503282 <30>[ 21.648406] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1662 01:10:27.511087 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1663 01:10:27.522714 <30>[ 21.667875] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1664 01:10:27.535780 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1665 01:10:27.541310 <30>[ 21.687191] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1666 01:10:27.548443 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1667 01:10:27.566977 <30>[ 21.712055] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1668 01:10:27.575075 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1669 01:10:27.587976 <30>[ 21.733131] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1670 01:10:27.593548 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1671 01:10:27.608039 <30>[ 21.751024] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1672 01:10:27.613433 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1673 01:10:27.669379 <30>[ 21.814562] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1674 01:10:27.675164 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1675 01:10:27.687675 <30>[ 21.832881] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1676 01:10:27.694298 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1677 01:10:27.713509 <30>[ 21.858647] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1678 01:10:27.720282 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1679 01:10:27.743938 <30>[ 21.882923] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1680 01:10:27.752265 <30>[ 21.898598] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1681 01:10:27.761187 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1682 01:10:27.782159 <30>[ 21.927315] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1683 01:10:27.789222 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1684 01:10:27.810307 <30>[ 21.955466] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1685 01:10:27.817200 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1686 01:10:27.833817 <6>[ 21.978964] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1687 01:10:27.842770 <30>[ 21.983596] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1688 01:10:27.848939 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1689 01:10:27.866235 <30>[ 22.011370] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1690 01:10:27.873631 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1691 01:10:27.909713 <30>[ 22.054882] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1692 01:10:27.916283 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1693 01:10:27.930659 <30>[ 22.075799] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1694 01:10:27.936281 <6>[ 22.079677] fuse: init (API version 7.41)
1695 01:10:27.939738 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1696 01:10:27.961678 <30>[ 22.106845] systemd[1]: Starting systemd-journald.service - Journal Service...
1697 01:10:27.967193 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1698 01:10:27.987298 <30>[ 22.132484] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1699 01:10:27.994005 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1700 01:10:28.014267 <30>[ 22.159392] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1701 01:10:28.023367 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1702 01:10:28.037482 <30>[ 22.182721] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1703 01:10:28.045308 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1704 01:10:28.097691 <30>[ 22.242860] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1705 01:10:28.104780 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1706 01:10:28.125464 <30>[ 22.270690] systemd[1]: Started systemd-journald.service - Journal Service.
1707 01:10:28.131346 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1708 01:10:28.144213 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1709 01:10:28.161320 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1710 01:10:28.177350 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1711 01:10:28.194181 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1712 01:10:28.207174 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1713 01:10:28.218931 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1714 01:10:28.229330 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1715 01:10:28.241396 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1716 01:10:28.253238 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1717 01:10:28.265134 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1718 01:10:28.277128 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1719 01:10:28.289204 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1720 01:10:28.301116 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1721 01:10:28.313643 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1722 01:10:28.359758 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1723 01:10:28.369919 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1724 01:10:28.386165 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1725 01:10:28.405213 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1726 01:10:28.427193 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1727 01:10:28.433683 <46>[ 22.577323] systemd-journald[233]: Received client request to flush runtime journal.
1728 01:10:28.453211 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1729 01:10:28.514269 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1730 01:10:28.525277 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1731 01:10:28.537045 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1732 01:10:28.549318 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1733 01:10:28.561157 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1734 01:10:28.663747 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1735 01:10:28.716394 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1736 01:10:28.736917 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1737 01:10:28.800386 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1738 01:10:28.817268 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1739 01:10:28.832273 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1740 01:10:28.880283 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1741 01:10:28.901022 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1742 01:10:29.132685 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1743 01:10:29.149496 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1744 01:10:29.199833 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1745 01:10:29.217250 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1746 01:10:29.231314 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1747 01:10:29.285371 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1748 01:10:29.303413 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1749 01:10:29.367361 <5>[ 23.513653] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1750 01:10:29.403088 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1751 01:10:29.408599 <5>[ 23.553732] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1752 01:10:29.417645 <5>[ 23.557353] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1753 01:10:29.423166 <4>[ 23.565250] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1754 01:10:29.429513 <6>[ 23.573176] cfg80211: failed to load regulatory.db
1755 01:10:29.444887 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1756 01:10:29.456622 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1757 01:10:29.481889 <46>[ 23.618114] systemd-journald[233]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1758 01:10:29.496963 <46>[ 23.632534] systemd-journald[233]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1759 01:10:29.511885 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1760 01:10:29.529520 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1761 01:10:29.549327 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1762 01:10:29.556841 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1763 01:10:29.626473 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1764 01:10:29.643190 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1765 01:10:29.653467 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1766 01:10:29.693195 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1767 01:10:29.699446 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1768 01:10:29.711774 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1769 01:10:29.775419 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1770 01:10:29.793924 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1771 01:10:29.862712 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1772 01:10:29.869031 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1773 01:10:29.886404 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1774 01:10:29.898672 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1775 01:10:29.952077 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1776 01:10:29.964816 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1777 01:10:29.984919 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1778 01:10:30.032527 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1779 01:10:30.046187 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1780 01:10:30.058182 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1781 01:10:30.070451 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1782 01:10:30.086132 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1783 01:10:30.098834 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1784 01:10:30.116395 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1785 01:10:30.138569 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1786 01:10:30.144841 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1787 01:10:30.157025 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1788 01:10:30.169072 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1789 01:10:30.209241 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1790 01:10:30.282938 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1791 01:10:30.354929
1792 01:10:30.355624 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1793 01:10:30.356193
1794 01:10:30.361322 debian-bookworm-arm64 login: root (automatic login)
1795 01:10:30.361922
1796 01:10:30.496044 Linux debian-bookworm-arm64 6.12.0-rc7 #1 SMP PREEMPT Sun Nov 10 23:05:43 UTC 2024 aarch64
1797 01:10:30.496720
1798 01:10:30.501520 The programs included with the Debian GNU/Linux system are free software;
1799 01:10:30.510498 the exact distribution terms for each program are described in the
1800 01:10:30.511116 individual files in /usr/share/doc/*/copyright.
1801 01:10:30.511649
1802 01:10:30.516082 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1803 01:10:30.520619 permitted by applicable law.
1804 01:10:31.235648 Matched prompt #10: / #
1806 01:10:31.237453 Setting prompt string to ['/ #']
1807 01:10:31.238061 end: 2.4.4.1 login-action (duration 00:00:26) [common]
1809 01:10:31.239664 end: 2.4.4 auto-login-action (duration 00:00:26) [common]
1810 01:10:31.240290 start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
1811 01:10:31.240773 Setting prompt string to ['/ #']
1812 01:10:31.241215 Forcing a shell prompt, looking for ['/ #']
1814 01:10:31.292306 / #
1815 01:10:31.293082 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1816 01:10:31.293570 Waiting using forced prompt support (timeout 00:02:30)
1817 01:10:31.298123
1818 01:10:31.298997 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1819 01:10:31.299603 start: 2.4.6 export-device-env (timeout 00:03:11) [common]
1820 01:10:31.300175 Sending with 10 millisecond of delay
1822 01:10:36.287753 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/972876/extract-nfsrootfs-5olb0djb'
1823 01:10:36.298751 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/972876/extract-nfsrootfs-5olb0djb'
1824 01:10:36.299517 Sending with 10 millisecond of delay
1826 01:10:38.398603 / # export NFS_SERVER_IP='192.168.6.2'
1827 01:10:38.409669 export NFS_SERVER_IP='192.168.6.2'
1828 01:10:38.410695 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1829 01:10:38.411332 end: 2.4 uboot-commands (duration 00:01:56) [common]
1830 01:10:38.411947 end: 2 uboot-action (duration 00:01:56) [common]
1831 01:10:38.412686 start: 3 lava-test-retry (timeout 00:06:47) [common]
1832 01:10:38.413384 start: 3.1 lava-test-shell (timeout 00:06:47) [common]
1833 01:10:38.413922 Using namespace: common
1835 01:10:38.515468 / # #
1836 01:10:38.516542 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1837 01:10:38.521230 #
1838 01:10:38.522130 Using /lava-972876
1840 01:10:38.623492 / # export SHELL=/bin/bash
1841 01:10:38.629231 export SHELL=/bin/bash
1843 01:10:38.730976 / # . /lava-972876/environment
1844 01:10:38.734991 . /lava-972876/environment
1846 01:10:38.839881 / # /lava-972876/bin/lava-test-runner /lava-972876/0
1847 01:10:38.840738 Test shell timeout: 10s (minimum of the action and connection timeout)
1848 01:10:38.844872 /lava-972876/bin/lava-test-runner /lava-972876/0
1849 01:10:39.046037 + export TESTRUN_ID=0_timesync-off
1850 01:10:39.052584 + TESTRUN_ID=0_timesync-off
1851 01:10:39.053132 + cd /lava-972876/0/tests/0_timesync-off
1852 01:10:39.053593 ++ cat uuid
1853 01:10:39.057995 + UUID=972876_1.6.2.4.1
1854 01:10:39.058527 + set +x
1855 01:10:39.065854 <LAVA_SIGNAL_STARTRUN 0_timesync-off 972876_1.6.2.4.1>
1856 01:10:39.066396 + systemctl stop systemd-timesyncd
1857 01:10:39.067171 Received signal: <STARTRUN> 0_timesync-off 972876_1.6.2.4.1
1858 01:10:39.067689 Starting test lava.0_timesync-off (972876_1.6.2.4.1)
1859 01:10:39.068445 Skipping test definition patterns.
1860 01:10:39.104498 + set +x
1861 01:10:39.105083 <LAVA_SIGNAL_ENDRUN 0_timesync-off 972876_1.6.2.4.1>
1862 01:10:39.105804 Received signal: <ENDRUN> 0_timesync-off 972876_1.6.2.4.1
1863 01:10:39.106325 Ending use of test pattern.
1864 01:10:39.106769 Ending test lava.0_timesync-off (972876_1.6.2.4.1), duration 0.04
1866 01:10:39.182648 + export TESTRUN_ID=1_kselftest-alsa
1867 01:10:39.190243 + TESTRUN_ID=1_kselftest-alsa
1868 01:10:39.190786 + cd /lava-972876/0/tests/1_kselftest-alsa
1869 01:10:39.191264 ++ cat uuid
1870 01:10:39.195893 + UUID=972876_1.6.2.4.5
1871 01:10:39.196586 + set +x
1872 01:10:39.202652 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 972876_1.6.2.4.5>
1873 01:10:39.203200 + cd ./automated/linux/kselftest/
1874 01:10:39.203924 Received signal: <STARTRUN> 1_kselftest-alsa 972876_1.6.2.4.5
1875 01:10:39.204433 Starting test lava.1_kselftest-alsa (972876_1.6.2.4.5)
1876 01:10:39.204974 Skipping test definition patterns.
1877 01:10:39.227300 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc7/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1878 01:10:39.269390 INFO: install_deps skipped
1879 01:10:39.375273 --2024-11-11 01:10:39-- http://storage.kernelci.org/mainline/master/v6.12-rc7/arm64/defconfig/gcc-12/kselftest.tar.xz
1880 01:10:39.403634 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1881 01:10:39.544914 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1882 01:10:39.683846 HTTP request sent, awaiting response... 200 OK
1883 01:10:39.684509 Length: 6928740 (6.6M) [application/octet-stream]
1884 01:10:39.689211 Saving to: 'kselftest_armhf.tar.gz'
1885 01:10:39.689716
1886 01:10:40.964617
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 47.54K 172KB/s
kselftest_armhf.tar 3%[ ] 218.67K 394KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.05MB/s
kselftest_armhf.tar 41%[=======> ] 2.74M 2.43MB/s
kselftest_armhf.tar 100%[===================>] 6.61M 5.18MB/s in 1.3s
1887 01:10:40.965342
1888 01:10:41.052918 2024-11-11 01:10:40 (5.18 MB/s) - 'kselftest_armhf.tar.gz' saved [6928740/6928740]
1889 01:10:41.053716
1890 01:10:50.558989 skiplist:
1891 01:10:50.559673 ========================================
1892 01:10:50.564599 ========================================
1893 01:10:50.599949 alsa:mixer-test
1894 01:10:50.600559 alsa:pcm-test
1895 01:10:50.601012 alsa:test-pcmtest-driver
1896 01:10:50.604138 alsa:utimer-test
1897 01:10:50.615384 ============== Tests to run ===============
1898 01:10:50.615902 alsa:mixer-test
1899 01:10:50.620993 alsa:pcm-test
1900 01:10:50.621494 alsa:test-pcmtest-driver
1901 01:10:50.621934 alsa:utimer-test
1902 01:10:50.628294 ===========End Tests to run ===============
1903 01:10:50.628798 shardfile-alsa pass
1904 01:10:50.739451 <12>[ 44.887945] kselftest: Running tests in alsa
1905 01:10:50.745481 TAP version 13
1906 01:10:50.755629 1..4
1907 01:10:50.773832 # timeout set to 45
1908 01:10:50.774371 # selftests: alsa: mixer-test
1909 01:10:50.946922 # TAP version 13
1910 01:10:50.947579 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1911 01:10:50.952273 # 1..427
1912 01:10:50.952747 # ok 1 get_value.LCALTA.60
1913 01:10:50.953188 # # LCALTA.60 TDMOUT_A SRC SEL
1914 01:10:50.957813 # ok 2 name.LCALTA.60
1915 01:10:50.958281 # ok 3 write_default.LCALTA.60
1916 01:10:50.961354 # ok 4 write_valid.LCALTA.60
1917 01:10:50.966902 # ok 5 write_invalid.LCALTA.60
1918 01:10:50.967364 # ok 6 event_missing.LCALTA.60
1919 01:10:50.972544 # ok 7 event_spurious.LCALTA.60
1920 01:10:50.973011 # ok 8 get_value.LCALTA.59
1921 01:10:50.978052 # # LCALTA.59 TDMOUT_B SRC SEL
1922 01:10:50.978514 # ok 9 name.LCALTA.59
1923 01:10:50.978945 # ok 10 write_default.LCALTA.59
1924 01:10:50.981671 # ok 11 write_valid.LCALTA.59
1925 01:10:50.987180 # ok 12 write_invalid.LCALTA.59
1926 01:10:50.987663 # ok 13 event_missing.LCALTA.59
1927 01:10:50.992801 # ok 14 event_spurious.LCALTA.59
1928 01:10:50.993351 # ok 15 get_value.LCALTA.58
1929 01:10:50.998248 # # LCALTA.58 TDMOUT_C SRC SEL
1930 01:10:50.998925 # ok 16 name.LCALTA.58
1931 01:10:51.001862 # ok 17 write_default.LCALTA.58
1932 01:10:51.007367 # ok 18 write_valid.LCALTA.58
1933 01:10:51.007872 # ok 19 write_invalid.LCALTA.58
1934 01:10:51.013389 # ok 20 event_missing.LCALTA.58
1935 01:10:51.013990 # ok 21 event_spurious.LCALTA.58
1936 01:10:51.018484 # ok 22 get_value.LCALTA.57
1937 01:10:51.019040 # # LCALTA.57 TDMIN_A SRC SEL
1938 01:10:51.019513 # ok 23 name.LCALTA.57
1939 01:10:51.024305 # ok 24 write_default.LCALTA.57
1940 01:10:51.024979 # ok 25 write_valid.LCALTA.57
1941 01:10:51.029678 # ok 26 write_invalid.LCALTA.57
1942 01:10:51.030211 # ok 27 event_missing.LCALTA.57
1943 01:10:51.035189 # ok 28 event_spurious.LCALTA.57
1944 01:10:51.035699 # ok 29 get_value.LCALTA.56
1945 01:10:51.040700 # # LCALTA.56 TDMIN_B SRC SEL
1946 01:10:51.041214 # ok 30 name.LCALTA.56
1947 01:10:51.046251 # ok 31 write_default.LCALTA.56
1948 01:10:51.046795 # ok 32 write_valid.LCALTA.56
1949 01:10:51.051817 # ok 33 write_invalid.LCALTA.56
1950 01:10:51.052379 # ok 34 event_missing.LCALTA.56
1951 01:10:51.068405 # ok 35 event_spuriou<3>[ 45.204461] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1952 01:10:51.069004 s.LCALTA.56
1953 01:10:51.073892 # ok 36 get_value.LCALTA.55
1954 01:10:51.074395 # # LCALTA.55 TDMIN_C SRC SEL
1955 01:10:51.074833 # ok 37 name.LCALTA.55
1956 01:10:51.079376 # ok 38 write_default.LCALTA.55
1957 01:10:51.079864 # ok 39 write_valid.LCALTA.55
1958 01:10:51.085014 # ok 40 write_invalid.LCALTA.55
1959 01:10:51.085498 # ok 41 event_missing.LCALTA.55
1960 01:10:51.090485 # ok 42 event_spurious.LCALTA.55
1961 01:10:51.090981 # ok 43 get_value.LCALTA.54
1962 01:10:51.096068 # # LCALTA.54 ACODEC Left DAC Sel
1963 01:10:51.096545 # ok 44 name.LCALTA.54
1964 01:10:51.101557 # ok 45 write_default.LCALTA.54
1965 01:10:51.102060 # ok 46 write_valid.LCALTA.54
1966 01:10:51.107155 # ok 47 write_invalid.LCALTA.54
1967 01:10:51.107644 # ok 48 event_missing.LCALTA.54
1968 01:10:51.112693 # ok 49 event_spurious.LCALTA.54
1969 01:10:51.113185 # ok 50 get_value.LCALTA.53
1970 01:10:51.118279 # # LCALTA.53 ACODEC Right DAC Sel
1971 01:10:51.118781 # ok 51 name.LCALTA.53
1972 01:10:51.123823 # ok 52 write_default.LCALTA.53
1973 01:10:51.124359 # ok 53 write_valid.LCALTA.53
1974 01:10:51.129403 # ok 54 write_invalid.LCALTA.53
1975 01:10:51.129903 # ok 55 event_missing.LCALTA.53
1976 01:10:51.134947 # ok 56 event_spurious.LCALTA.53
1977 01:10:51.135445 # ok 57 get_value.LCALTA.52
1978 01:10:51.140452 # # LCALTA.52 TOACODEC OUT EN Switch
1979 01:10:51.140948 # ok 58 name.LCALTA.52
1980 01:10:51.146057 # ok 59 write_default.LCALTA.52
1981 01:10:51.146550 # ok 60 write_valid.LCALTA.52
1982 01:10:51.151551 # ok 61 write_invalid.LCALTA.52
1983 01:10:51.152093 # ok 62 event_missing.LCALTA.52
1984 01:10:51.157119 # ok 63 event_spurious.LCALTA.52
1985 01:10:51.157618 # ok 64 get_value.LCALTA.51
1986 01:10:51.162681 # # LCALTA.51 TOACODEC SRC
1987 01:10:51.163193 # ok 65 name.LCALTA.51
1988 01:10:51.168240 # ok 66 write_default.LCALTA.51
1989 01:10:51.168749 # ok 67 write_valid.LCALTA.51
1990 01:10:51.173726 # ok 68 write_invalid.LCALTA.51
1991 01:10:51.174323 # ok 69 event_missing.LCALTA.51
1992 01:10:51.179333 # ok 70 event_spurious.LCALTA.51
1993 01:10:51.179933 # ok 71 get_value.LCALTA.50
1994 01:10:51.184821 # # LCALTA.50 TOHDMITX SPDIF SRC
1995 01:10:51.185414 # ok 72 name.LCALTA.50
1996 01:10:51.190489 # ok 73 write_default.LCALTA.50
1997 01:10:51.191106 # ok 74 write_valid.LCALTA.50
1998 01:10:51.196081 # ok 75 write_invalid.LCALTA.50
1999 01:10:51.196711 # ok 76 event_missing.LCALTA.50
2000 01:10:51.201476 # ok 77 event_spurious.LCALTA.50
2001 01:10:51.202069 # ok 78 get_value.LCALTA.49
2002 01:10:51.207148 # # LCALTA.49 TOHDMITX Switch
2003 01:10:51.207805 # ok 79 name.LCALTA.49
2004 01:10:51.208386 # ok 80 write_default.LCALTA.49
2005 01:10:51.212559 # ok 81 write_valid.LCALTA.49
2006 01:10:51.213135 # ok 82 write_invalid.LCALTA.49
2007 01:10:51.218164 # ok 83 event_missing.LCALTA.49
2008 01:10:51.218764 # ok 84 event_spurious.LCALTA.49
2009 01:10:51.223659 # ok 85 get_value.LCALTA.48
2010 01:10:51.224243 # # LCALTA.48 TOHDMITX I2S SRC
2011 01:10:51.229203 # ok 86 name.LCALTA.48
2012 01:10:51.229701 # ok 87 write_default.LCALTA.48
2013 01:10:51.234744 # ok 88 write_valid.LCALTA.48
2014 01:10:51.235319 # ok 89 write_invalid.LCALTA.48
2015 01:10:51.240350 # ok 90 event_missing.LCALTA.48
2016 01:10:51.241003 # ok 91 event_spurious.LCALTA.48
2017 01:10:51.245889 # ok 92 get_value.LCALTA.47
2018 01:10:51.246482 # # LCALTA.47 TODDR_C SRC SEL
2019 01:10:51.251424 # ok 93 name.LCALTA.47
2020 01:10:51.251924 # ok 94 write_default.LCALTA.47
2021 01:10:51.256994 # ok 95 write_valid.LCALTA.47
2022 01:10:51.257623 # ok 96 write_invalid.LCALTA.47
2023 01:10:51.262514 # ok 97 event_missing.LCALTA.47
2024 01:10:51.263188 # ok 98 event_spurious.LCALTA.47
2025 01:10:51.268136 # ok 99 get_value.LCALTA.46
2026 01:10:51.268700 # # LCALTA.46 TODDR_B SRC SEL
2027 01:10:51.273573 # ok 100 name.LCALTA.46
2028 01:10:51.274098 # ok 101 write_default.LCALTA.46
2029 01:10:51.279124 # ok 102 write_valid.LCALTA.46
2030 01:10:51.279631 # ok 103 write_invalid.LCALTA.46
2031 01:10:51.284688 # ok 104 event_missing.LCALTA.46
2032 01:10:51.285220 # ok 105 event_spurious.LCALTA.46
2033 01:10:51.290240 # ok 106 get_value.LCALTA.45
2034 01:10:51.290765 # # LCALTA.45 TODDR_A SRC SEL
2035 01:10:51.295846 # ok 107 name.LCALTA.45
2036 01:10:51.296437 # ok 108 write_default.LCALTA.45
2037 01:10:51.301335 # ok 109 write_valid.LCALTA.45
2038 01:10:51.301872 # ok 110 write_invalid.LCALTA.45
2039 01:10:51.306879 # ok 111 event_missing.LCALTA.45
2040 01:10:51.307416 # ok 112 event_spurious.LCALTA.45
2041 01:10:51.312418 # ok 113 get_value.LCALTA.44
2042 01:10:51.312932 # # LCALTA.44 FRDDR_C SINK 3 SEL
2043 01:10:51.318008 # ok 114 name.LCALTA.44
2044 01:10:51.318549 # ok 115 write_default.LCALTA.44
2045 01:10:51.323531 # ok 116 write_valid.LCALTA.44
2046 01:10:51.324095 # ok 117 write_invalid.LCALTA.44
2047 01:10:51.329115 # ok 118 event_missing.LCALTA.44
2048 01:10:51.329643 # ok 119 event_spurious.LCALTA.44
2049 01:10:51.334609 # ok 120 get_value.LCALTA.43
2050 01:10:51.335135 # # LCALTA.43 FRDDR_C SINK 2 SEL
2051 01:10:51.340182 # ok 121 name.LCALTA.43
2052 01:10:51.340711 # ok 122 write_default.LCALTA.43
2053 01:10:51.345682 # ok 123 write_valid.LCALTA.43
2054 01:10:51.346199 # ok 124 write_invalid.LCALTA.43
2055 01:10:51.351225 # ok 125 event_missing.LCALTA.43
2056 01:10:51.351732 # ok 126 event_spurious.LCALTA.43
2057 01:10:51.356776 # ok 127 get_value.LCALTA.42
2058 01:10:51.357278 # # LCALTA.42 FRDDR_C SINK 1 SEL
2059 01:10:51.362355 # ok 128 name.LCALTA.42
2060 01:10:51.362886 # ok 129 write_default.LCALTA.42
2061 01:10:51.367875 # ok 130 write_valid.LCALTA.42
2062 01:10:51.368425 # ok 131 write_invalid.LCALTA.42
2063 01:10:51.373433 # ok 132 event_missing.LCALTA.42
2064 01:10:51.373936 # ok 133 event_spurious.LCALTA.42
2065 01:10:51.379005 # ok 134 get_value.LCALTA.41
2066 01:10:51.379528 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
2067 01:10:51.384568 # ok 135 name.LCALTA.41
2068 01:10:51.385095 # ok 136 write_default.LCALTA.41
2069 01:10:51.390134 # ok 137 write_valid.LCALTA.41
2070 01:10:51.390655 # ok 138 write_invalid.LCALTA.41
2071 01:10:51.395638 # ok 139 event_missing.LCALTA.41
2072 01:10:51.396194 # ok 140 event_spurious.LCALTA.41
2073 01:10:51.401167 # ok 141 get_value.LCALTA.40
2074 01:10:51.401680 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
2075 01:10:51.406719 # ok 142 name.LCALTA.40
2076 01:10:51.407235 # ok 143 write_default.LCALTA.40
2077 01:10:51.412350 # ok 144 write_valid.LCALTA.40
2078 01:10:51.412919 # ok 145 write_invalid.LCALTA.40
2079 01:10:51.417840 # ok 146 event_missing.LCALTA.40
2080 01:10:51.423422 # ok 147 event_spurious.LCALTA.40
2081 01:10:51.423955 # ok 148 get_value.LCALTA.39
2082 01:10:51.428903 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
2083 01:10:51.429419 # ok 149 name.LCALTA.39
2084 01:10:51.434434 # ok 150 write_default.LCALTA.39
2085 01:10:51.434940 # ok 151 write_valid.LCALTA.39
2086 01:10:51.440017 # ok 152 write_invalid.LCALTA.39
2087 01:10:51.440536 # ok 153 event_missing.LCALTA.39
2088 01:10:51.445569 # ok 154 event_spurious.LCALTA.39
2089 01:10:51.446077 # ok 155 get_value.LCALTA.38
2090 01:10:51.451113 # # LCALTA.38 FRDDR_B SINK 3 SEL
2091 01:10:51.451620 # ok 156 name.LCALTA.38
2092 01:10:51.456622 # ok 157 write_default.LCALTA.38
2093 01:10:51.457131 # ok 158 write_valid.LCALTA.38
2094 01:10:51.462178 # ok 159 write_invalid.LCALTA.38
2095 01:10:51.462674 # ok 160 event_missing.LCALTA.38
2096 01:10:51.467720 # ok 161 event_spurious.LCALTA.38
2097 01:10:51.468255 # ok 162 get_value.LCALTA.37
2098 01:10:51.473246 # # LCALTA.37 FRDDR_B SINK 2 SEL
2099 01:10:51.473740 # ok 163 name.LCALTA.37
2100 01:10:51.478806 # ok 164 write_default.LCALTA.37
2101 01:10:51.479302 # ok 165 write_valid.LCALTA.37
2102 01:10:51.484372 # ok 166 write_invalid.LCALTA.37
2103 01:10:51.484871 # ok 167 event_missing.LCALTA.37
2104 01:10:51.489871 # ok 168 event_spurious.LCALTA.37
2105 01:10:51.490373 # ok 169 get_value.LCALTA.36
2106 01:10:51.495434 # # LCALTA.36 FRDDR_B SINK 1 SEL
2107 01:10:51.495934 # ok 170 name.LCALTA.36
2108 01:10:51.500984 # ok 171 write_default.LCALTA.36
2109 01:10:51.501495 # ok 172 write_valid.LCALTA.36
2110 01:10:51.506560 # ok 173 write_invalid.LCALTA.36
2111 01:10:51.507073 # ok 174 event_missing.LCALTA.36
2112 01:10:51.512163 # ok 175 event_spurious.LCALTA.36
2113 01:10:51.512678 # ok 176 get_value.LCALTA.35
2114 01:10:51.517662 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
2115 01:10:51.518169 # ok 177 name.LCALTA.35
2116 01:10:51.523192 # ok 178 write_default.LCALTA.35
2117 01:10:51.523720 # ok 179 write_valid.LCALTA.35
2118 01:10:51.528741 # ok 180 write_invalid.LCALTA.35
2119 01:10:51.529255 # ok 181 event_missing.LCALTA.35
2120 01:10:51.534286 # ok 182 event_spurious.LCALTA.35
2121 01:10:51.534819 # ok 183 get_value.LCALTA.34
2122 01:10:51.539847 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
2123 01:10:51.540415 # ok 184 name.LCALTA.34
2124 01:10:51.545413 # ok 185 write_default.LCALTA.34
2125 01:10:51.545937 # ok 186 write_valid.LCALTA.34
2126 01:10:51.550949 # ok 187 write_invalid.LCALTA.34
2127 01:10:51.551468 # ok 188 event_missing.LCALTA.34
2128 01:10:51.556454 # ok 189 event_spurious.LCALTA.34
2129 01:10:51.556958 # ok 190 get_value.LCALTA.33
2130 01:10:51.562035 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
2131 01:10:51.562545 # ok 191 name.LCALTA.33
2132 01:10:51.567612 # ok 192 write_default.LCALTA.33
2133 01:10:51.568180 # ok 193 write_valid.LCALTA.33
2134 01:10:51.573160 # ok 194 write_invalid.LCALTA.33
2135 01:10:51.573696 # ok 195 event_missing.LCALTA.33
2136 01:10:51.578668 # ok 196 event_spurious.LCALTA.33
2137 01:10:51.584287 # ok 197 get_value.LCALTA.32
2138 01:10:51.584827 # # LCALTA.32 FRDDR_A SINK 3 SEL
2139 01:10:51.585276 # ok 198 name.LCALTA.32
2140 01:10:51.589810 # ok 199 write_default.LCALTA.32
2141 01:10:51.590338 # ok 200 write_valid.LCALTA.32
2142 01:10:51.595314 # ok 201 write_invalid.LCALTA.32
2143 01:10:51.600873 # ok 202 event_missing.LCALTA.32
2144 01:10:51.601421 # ok 203 event_spurious.LCALTA.32
2145 01:10:51.606428 # ok 204 get_value.LCALTA.31
2146 01:10:51.606966 # # LCALTA.31 FRDDR_A SINK 2 SEL
2147 01:10:51.607419 # ok 205 name.LCALTA.31
2148 01:10:51.611960 # ok 206 write_default.LCALTA.31
2149 01:10:51.612525 # ok 207 write_valid.LCALTA.31
2150 01:10:51.617472 # ok 208 write_invalid.LCALTA.31
2151 01:10:51.623010 # ok 209 event_missing.LCALTA.31
2152 01:10:51.623511 # ok 210 event_spurious.LCALTA.31
2153 01:10:51.628577 # ok 211 get_value.LCALTA.30
2154 01:10:51.629083 # # LCALTA.30 FRDDR_A SINK 1 SEL
2155 01:10:51.629529 # ok 212 name.LCALTA.30
2156 01:10:51.634118 # ok 213 write_default.LCALTA.30
2157 01:10:51.639656 # ok 214 write_valid.LCALTA.30
2158 01:10:51.640188 # ok 215 write_invalid.LCALTA.30
2159 01:10:51.645218 # ok 216 event_missing.LCALTA.30
2160 01:10:51.645718 # ok 217 event_spurious.LCALTA.30
2161 01:10:51.650738 # ok 218 get_value.LCALTA.29
2162 01:10:51.651239 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2163 01:10:51.656302 # ok 219 name.LCALTA.29
2164 01:10:51.656801 # ok 220 write_default.LCALTA.29
2165 01:10:51.661839 # ok 221 write_valid.LCALTA.29
2166 01:10:51.662341 # ok 222 write_invalid.LCALTA.29
2167 01:10:51.667437 # ok 223 event_missing.LCALTA.29
2168 01:10:51.667939 # ok 224 event_spurious.LCALTA.29
2169 01:10:51.672936 # ok 225 get_value.LCALTA.28
2170 01:10:51.673432 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2171 01:10:51.678487 # ok 226 name.LCALTA.28
2172 01:10:51.678982 # ok 227 write_default.LCALTA.28
2173 01:10:51.684070 # ok 228 write_valid.LCALTA.28
2174 01:10:51.684573 # ok 229 write_invalid.LCALTA.28
2175 01:10:51.689554 # ok 230 event_missing.LCALTA.28
2176 01:10:51.690052 # ok 231 event_spurious.LCALTA.28
2177 01:10:51.695121 # ok 232 get_value.LCALTA.27
2178 01:10:51.695618 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2179 01:10:51.700688 # ok 233 name.LCALTA.27
2180 01:10:51.701188 # ok 234 write_default.LCALTA.27
2181 01:10:51.706216 # ok 235 write_valid.LCALTA.27
2182 01:10:51.706717 # ok 236 write_invalid.LCALTA.27
2183 01:10:51.711751 # ok 237 event_missing.LCALTA.27
2184 01:10:51.712285 # ok 238 event_spurious.LCALTA.27
2185 01:10:51.717285 # ok 239 get_value.LCALTA.26
2186 01:10:51.717778 # # LCALTA.26 ELD
2187 01:10:51.722833 # ok 240 name.LCALTA.26
2188 01:10:51.723327 # # ELD is not writeable
2189 01:10:51.728412 # ok 241 # SKIP write_default.LCALTA.26
2190 01:10:51.728919 # # ELD is not writeable
2191 01:10:51.733981 # ok 242 # SKIP write_valid.LCALTA.26
2192 01:10:51.734517 # # ELD is not writeable
2193 01:10:51.739525 # ok 243 # SKIP write_invalid.LCALTA.26
2194 01:10:51.740062 # ok 244 event_missing.LCALTA.26
2195 01:10:51.745056 # ok 245 event_spurious.LCALTA.26
2196 01:10:51.745559 # ok 246 get_value.LCALTA.25
2197 01:10:51.750589 # # LCALTA.25 IEC958 Playback Default
2198 01:10:51.751095 # ok 247 name.LCALTA.25
2199 01:10:51.756168 # ok 248 write_default.LCALTA.25
2200 01:10:51.756674 # ok 249 # SKIP write_valid.LCALTA.25
2201 01:10:51.761697 # ok 250 # SKIP write_invalid.LCALTA.25
2202 01:10:51.767237 # ok 251 event_missing.LCALTA.25
2203 01:10:51.767745 # ok 252 event_spurious.LCALTA.25
2204 01:10:51.772772 # ok 253 get_value.LCALTA.24
2205 01:10:51.773274 # # LCALTA.24 IEC958 Playback Mask
2206 01:10:51.778314 # ok 254 name.LCALTA.24
2207 01:10:51.778814 # # IEC958 Playback Mask is not writeable
2208 01:10:51.783880 # ok 255 # SKIP write_default.LCALTA.24
2209 01:10:51.789418 # # IEC958 Playback Mask is not writeable
2210 01:10:51.789923 # ok 256 # SKIP write_valid.LCALTA.24
2211 01:10:51.794952 # # IEC958 Playback Mask is not writeable
2212 01:10:51.795455 # ok 257 # SKIP write_invalid.LCALTA.24
2213 01:10:51.800520 # ok 258 event_missing.LCALTA.24
2214 01:10:51.806071 # ok 259 event_spurious.LCALTA.24
2215 01:10:51.806602 # ok 260 get_value.LCALTA.23
2216 01:10:51.811600 # # LCALTA.23 Playback Channel Map
2217 01:10:51.812132 # ok 261 name.LCALTA.23
2218 01:10:51.817130 # # Playback Channel Map is not writeable
2219 01:10:51.817629 # ok 262 # SKIP write_default.LCALTA.23
2220 01:10:51.822680 # # Playback Channel Map is not writeable
2221 01:10:51.828267 # ok 263 # SKIP write_valid.LCALTA.23
2222 01:10:51.828775 # # Playback Channel Map is not writeable
2223 01:10:51.833778 # ok 264 # SKIP write_invalid.LCALTA.23
2224 01:10:51.834275 # ok 265 event_missing.LCALTA.23
2225 01:10:51.839304 # ok 266 event_spurious.LCALTA.23
2226 01:10:51.839803 # ok 267 get_value.LCALTA.22
2227 01:10:51.844916 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2228 01:10:51.845424 # ok 268 name.LCALTA.22
2229 01:10:51.850462 # ok 269 write_default.LCALTA.22
2230 01:10:51.855971 # ok 270 write_valid.LCALTA.22
2231 01:10:51.856516 # ok 271 write_invalid.LCALTA.22
2232 01:10:51.861564 # ok 272 event_missing.LCALTA.22
2233 01:10:51.862071 # ok 273 event_spurious.LCALTA.22
2234 01:10:51.867096 # ok 274 get_value.LCALTA.21
2235 01:10:51.867600 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2236 01:10:51.872637 # ok 275 name.LCALTA.21
2237 01:10:51.873170 # ok 276 write_default.LCALTA.21
2238 01:10:51.878208 # ok 277 write_valid.LCALTA.21
2239 01:10:51.878720 # ok 278 write_invalid.LCALTA.21
2240 01:10:51.883716 # ok 279 event_missing.LCALTA.21
2241 01:10:51.884259 # ok 280 event_spurious.LCALTA.21
2242 01:10:51.889293 # ok 281 get_value.LCALTA.20
2243 01:10:51.889795 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2244 01:10:51.894812 # ok 282 name.LCALTA.20
2245 01:10:51.895315 # ok 283 write_default.LCALTA.20
2246 01:10:51.900361 # ok 284 write_valid.LCALTA.20
2247 01:10:51.900868 # ok 285 write_invalid.LCALTA.20
2248 01:10:51.905927 # ok 286 event_missing.LCALTA.20
2249 01:10:51.906432 # ok 287 event_spurious.LCALTA.20
2250 01:10:51.911460 # ok 288 get_value.LCALTA.19
2251 01:10:51.911970 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2252 01:10:51.916977 # ok 289 name.LCALTA.19
2253 01:10:51.917477 # ok 290 write_default.LCALTA.19
2254 01:10:51.922537 # ok 291 write_valid.LCALTA.19
2255 01:10:51.923038 # ok 292 write_invalid.LCALTA.19
2256 01:10:51.928112 # ok 293 event_missing.LCALTA.19
2257 01:10:51.928625 # ok 294 event_spurious.LCALTA.19
2258 01:10:51.933626 # ok 295 get_value.LCALTA.18
2259 01:10:51.934132 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2260 01:10:51.939219 # ok 296 name.LCALTA.18
2261 01:10:51.939725 # ok 297 write_default.LCALTA.18
2262 01:10:51.944754 # ok 298 write_valid.LCALTA.18
2263 01:10:51.945260 # ok 299 write_invalid.LCALTA.18
2264 01:10:51.950285 # ok 300 event_missing.LCALTA.18
2265 01:10:51.950790 # ok 301 event_spurious.LCALTA.18
2266 01:10:51.955811 # ok 302 get_value.LCALTA.17
2267 01:10:51.961371 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2268 01:10:51.961875 # ok 303 name.LCALTA.17
2269 01:10:51.966905 # ok 304 write_default.LCALTA.17
2270 01:10:51.967409 # ok 305 write_valid.LCALTA.17
2271 01:10:51.972457 # ok 306 write_invalid.LCALTA.17
2272 01:10:51.972964 # ok 307 event_missing.LCALTA.17
2273 01:10:51.978053 # ok 308 event_spurious.LCALTA.17
2274 01:10:51.978577 # ok 309 get_value.LCALTA.16
2275 01:10:51.983598 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2276 01:10:51.984158 # ok 310 name.LCALTA.16
2277 01:10:51.989198 # ok 311 write_default.LCALTA.16
2278 01:10:51.989695 # ok 312 write_valid.LCALTA.16
2279 01:10:51.994640 # ok 313 write_invalid.LCALTA.16
2280 01:10:51.995140 # ok 314 event_missing.LCALTA.16
2281 01:10:52.000286 # ok 315 event_spurious.LCALTA.16
2282 01:10:52.000793 # ok 316 get_value.LCALTA.15
2283 01:10:52.005769 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2284 01:10:52.006278 # ok 317 name.LCALTA.15
2285 01:10:52.011316 # ok 318 write_default.LCALTA.15
2286 01:10:52.011822 # ok 319 write_valid.LCALTA.15
2287 01:10:52.016823 # ok 320 write_invalid.LCALTA.15
2288 01:10:52.017330 # ok 321 event_missing.LCALTA.15
2289 01:10:52.022389 # ok 322 event_spurious.LCALTA.15
2290 01:10:52.022903 # ok 323 get_value.LCALTA.14
2291 01:10:52.028016 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2292 01:10:52.028576 # ok 324 name.LCALTA.14
2293 01:10:52.033523 # ok 325 write_default.LCALTA.14
2294 01:10:52.034041 # ok 326 write_valid.LCALTA.14
2295 01:10:52.039045 # ok 327 write_invalid.LCALTA.14
2296 01:10:52.039568 # ok 328 event_missing.LCALTA.14
2297 01:10:52.044581 # ok 329 event_spurious.LCALTA.14
2298 01:10:52.045089 # ok 330 get_value.LCALTA.13
2299 01:10:52.050237 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2300 01:10:52.050743 # ok 331 name.LCALTA.13
2301 01:10:52.055686 # ok 332 write_default.LCALTA.13
2302 01:10:52.056230 # ok 333 write_valid.LCALTA.13
2303 01:10:52.061239 # ok 334 write_invalid.LCALTA.13
2304 01:10:52.061738 # ok 335 event_missing.LCALTA.13
2305 01:10:52.066786 # ok 336 event_spurious.LCALTA.13
2306 01:10:52.072346 # ok 337 get_value.LCALTA.12
2307 01:10:52.072847 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2308 01:10:52.077885 # ok 338 name.LCALTA.12
2309 01:10:52.078403 # ok 339 write_default.LCALTA.12
2310 01:10:52.083390 # ok 340 write_valid.LCALTA.12
2311 01:10:52.083895 # ok 341 write_invalid.LCALTA.12
2312 01:10:52.088965 # ok 342 event_missing.LCALTA.12
2313 01:10:52.089469 # ok 343 event_spurious.LCALTA.12
2314 01:10:52.094488 # ok 344 get_value.LCALTA.11
2315 01:10:52.094989 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2316 01:10:52.100066 # ok 345 name.LCALTA.11
2317 01:10:52.100576 # ok 346 write_default.LCALTA.11
2318 01:10:52.105600 # ok 347 write_valid.LCALTA.11
2319 01:10:52.106102 # ok 348 write_invalid.LCALTA.11
2320 01:10:52.111222 # ok 349 event_missing.LCALTA.11
2321 01:10:52.111727 # ok 350 event_spurious.LCALTA.11
2322 01:10:52.116677 # ok 351 get_value.LCALTA.10
2323 01:10:52.117181 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2324 01:10:52.122258 # ok 352 name.LCALTA.10
2325 01:10:52.122763 # ok 353 write_default.LCALTA.10
2326 01:10:52.127762 # ok 354 write_valid.LCALTA.10
2327 01:10:52.128297 # ok 355 write_invalid.LCALTA.10
2328 01:10:52.133340 # ok 356 event_missing.LCALTA.10
2329 01:10:52.133839 # ok 357 event_spurious.LCALTA.10
2330 01:10:52.138888 # ok 358 get_value.LCALTA.9
2331 01:10:52.139398 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2332 01:10:52.144404 # ok 359 name.LCALTA.9
2333 01:10:52.144907 # ok 360 write_default.LCALTA.9
2334 01:10:52.149949 # ok 361 write_valid.LCALTA.9
2335 01:10:52.150455 # ok 362 write_invalid.LCALTA.9
2336 01:10:52.155497 # ok 363 event_missing.LCALTA.9
2337 01:10:52.156043 # ok 364 event_spurious.LCALTA.9
2338 01:10:52.161025 # ok 365 get_value.LCALTA.8
2339 01:10:52.161523 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2340 01:10:52.166610 # ok 366 name.LCALTA.8
2341 01:10:52.167110 # ok 367 write_default.LCALTA.8
2342 01:10:52.172291 # ok 368 write_valid.LCALTA.8
2343 01:10:52.172799 # ok 369 write_invalid.LCALTA.8
2344 01:10:52.177693 # ok 370 event_missing.LCALTA.8
2345 01:10:52.178193 # ok 371 event_spurious.LCALTA.8
2346 01:10:52.183250 # ok 372 get_value.LCALTA.7
2347 01:10:52.183752 # # LCALTA.7 ACODEC Unmute Ramp Switch
2348 01:10:52.188791 # ok 373 name.LCALTA.7
2349 01:10:52.189297 # ok 374 write_default.LCALTA.7
2350 01:10:52.194344 # ok 375 write_valid.LCALTA.7
2351 01:10:52.194856 # ok 376 write_invalid.LCALTA.7
2352 01:10:52.199877 # ok 377 event_missing.LCALTA.7
2353 01:10:52.200419 # ok 378 event_spurious.LCALTA.7
2354 01:10:52.205451 # ok 379 get_value.LCALTA.6
2355 01:10:52.205960 # # LCALTA.6 ACODEC Mute Ramp Switch
2356 01:10:52.210974 # ok 380 name.LCALTA.6
2357 01:10:52.211485 # ok 381 write_default.LCALTA.6
2358 01:10:52.216551 # ok 382 write_valid.LCALTA.6
2359 01:10:52.217083 # ok 383 write_invalid.LCALTA.6
2360 01:10:52.222106 # ok 384 event_missing.LCALTA.6
2361 01:10:52.222632 # ok 385 event_spurious.LCALTA.6
2362 01:10:52.227622 # ok 386 get_value.LCALTA.5
2363 01:10:52.228165 # # LCALTA.5 ACODEC Volume Ramp Switch
2364 01:10:52.233242 # ok 387 name.LCALTA.5
2365 01:10:52.233763 # ok 388 write_default.LCALTA.5
2366 01:10:52.238710 # ok 389 write_valid.LCALTA.5
2367 01:10:52.239210 # ok 390 write_invalid.LCALTA.5
2368 01:10:52.244290 # ok 391 event_missing.LCALTA.5
2369 01:10:52.244797 # ok 392 event_spurious.LCALTA.5
2370 01:10:52.249819 # ok 393 get_value.LCALTA.4
2371 01:10:52.250320 # # LCALTA.4 ACODEC Ramp Rate
2372 01:10:52.255344 # ok 394 name.LCALTA.4
2373 01:10:52.255847 # ok 395 write_default.LCALTA.4
2374 01:10:52.260881 # ok 396 write_valid.LCALTA.4
2375 01:10:52.261387 # ok 397 write_invalid.LCALTA.4
2376 01:10:52.266469 # ok 398 event_missing.LCALTA.4
2377 01:10:52.266988 # ok 399 event_spurious.LCALTA.4
2378 01:10:52.272048 # ok 400 get_value.LCALTA.3
2379 01:10:52.272559 # # LCALTA.3 ACODEC Playback Volume
2380 01:10:52.277528 # ok 401 name.LCALTA.3
2381 01:10:52.278034 # ok 402 write_default.LCALTA.3
2382 01:10:52.283084 # ok 403 write_valid.LCALTA.3
2383 01:10:52.283595 # ok 404 write_invalid.LCALTA.3
2384 01:10:52.288639 # ok 405 event_missing.LCALTA.3
2385 01:10:52.289144 # ok 406 event_spurious.LCALTA.3
2386 01:10:52.294234 # ok 407 get_value.LCALTA.2
2387 01:10:52.294738 # # LCALTA.2 ACODEC Playback Switch
2388 01:10:52.299722 # ok 408 name.LCALTA.2
2389 01:10:52.300256 # ok 409 write_default.LCALTA.2
2390 01:10:52.305270 # ok 410 write_valid.LCALTA.2
2391 01:10:52.305771 # ok 411 write_invalid.LCALTA.2
2392 01:10:52.310834 # ok 412 event_missing.LCALTA.2
2393 01:10:52.311333 # ok 413 event_spurious.LCALTA.2
2394 01:10:52.316356 # ok 414 get_value.LCALTA.1
2395 01:10:52.316863 # # LCALTA.1 ACODEC Playback Channel Mode
2396 01:10:52.321893 # ok 415 name.LCALTA.1
2397 01:10:52.322394 # ok 416 write_default.LCALTA.1
2398 01:10:52.327462 # ok 417 write_valid.LCALTA.1
2399 01:10:52.327966 # ok 418 write_invalid.LCALTA.1
2400 01:10:52.333018 # ok 419 event_missing.LCALTA.1
2401 01:10:52.333523 # ok 420 event_spurious.LCALTA.1
2402 01:10:52.338562 # ok 421 get_value.LCALTA.0
2403 01:10:52.339067 # # LCALTA.0 TOACODEC Lane Select
2404 01:10:52.344149 # ok 422 name.LCALTA.0
2405 01:10:52.344668 # ok 423 write_default.LCALTA.0
2406 01:10:52.350732 # ok 424 write_valid.LCALTA.0
2407 01:10:52.351321 # ok 425 write_invalid.LCALTA.0
2408 01:10:52.355285 # ok 426 event_missing.LCALTA.0
2409 01:10:52.355885 # ok 427 event_spurious.LCALTA.0
2410 01:10:52.360772 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2411 01:10:52.366328 ok 1 selftests: alsa: mixer-test
2412 01:10:52.366911 # timeout set to 45
2413 01:10:52.367390 # selftests: alsa: pcm-test
2414 01:10:52.371936 # TAP version 13
2415 01:10:52.372542 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2416 01:10:52.377433 # # LCALTA.0 - fe.dai-link-0 (*)
2417 01:10:52.378026 # # LCALTA.0 - fe.dai-link-1 (*)
2418 01:10:52.382978 # # LCALTA.0 - fe.dai-link-2 (*)
2419 01:10:52.383567 # # LCALTA.0 - fe.dai-link-3 (*)
2420 01:10:52.388575 # # LCALTA.0 - fe.dai-link-4 (*)
2421 01:10:52.394120 # # LCALTA.0 - fe.dai-link-5 (*)
2422 01:10:52.394733 # 1..42
2423 01:10:52.399636 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2424 01:10:52.400271 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2425 01:10:52.405261 # # snd_pcm_hw_params: Invalid argument
2426 01:10:52.410679 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2427 01:10:52.416331 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2428 01:10:52.416921 # # snd_pcm_hw_params: Invalid argument
2429 01:10:52.427290 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2430 01:10:52.427905 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2431 01:10:52.432883 # # snd_pcm_hw_params: Invalid argument
2432 01:10:52.438442 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2433 01:10:52.443963 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2434 01:10:52.444537 # # snd_pcm_hw_params: Invalid argument
2435 01:10:52.449522 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2436 01:10:52.455118 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2437 01:10:52.460623 # # snd_pcm_hw_params: Invalid argument
2438 01:10:52.466175 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2439 01:10:52.471767 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2440 01:10:52.472425 # # snd_pcm_hw_params: Invalid argument
2441 01:10:52.477304 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2442 01:10:52.482792 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2443 01:10:52.488355 # # snd_pcm_hw_params: Invalid argument
2444 01:10:52.493890 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2445 01:10:52.494477 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2446 01:10:52.499439 # # snd_pcm_hw_params: Invalid argument
2447 01:10:52.505079 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2448 01:10:52.510604 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2449 01:10:52.516197 # # snd_pcm_hw_params: Invalid argument
2450 01:10:52.521754 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2451 01:10:52.522431 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2452 01:10:52.527323 # # snd_pcm_hw_params: Invalid argument
2453 01:10:52.532722 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2454 01:10:52.538401 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2455 01:10:52.539040 # # snd_pcm_hw_params: Invalid argument
2456 01:10:52.549380 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2457 01:10:52.549956 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2458 01:10:52.554988 # # snd_pcm_hw_params: Invalid argument
2459 01:10:52.560451 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2460 01:10:52.566014 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2461 01:10:52.566620 # # snd_pcm_hw_params: Invalid argument
2462 01:10:52.571595 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2463 01:10:52.577174 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2464 01:10:52.582655 # # snd_pcm_hw_params: Invalid argument
2465 01:10:52.588222 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2466 01:10:52.593710 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2467 01:10:52.594251 # # snd_pcm_hw_params: Invalid argument
2468 01:10:52.599269 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2469 01:10:52.604770 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2470 01:10:52.610315 # # snd_pcm_hw_params: Invalid argument
2471 01:10:52.615868 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2472 01:10:52.621404 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2473 01:10:52.621908 # # snd_pcm_hw_params: Invalid argument
2474 01:10:52.626962 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2475 01:10:52.632517 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2476 01:10:52.638045 # # snd_pcm_hw_params: Invalid argument
2477 01:10:52.643584 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2478 01:10:52.644118 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2479 01:10:52.649160 # # snd_pcm_hw_params: Invalid argument
2480 01:10:52.654677 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2481 01:10:52.660281 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2482 01:10:52.665795 # # snd_pcm_hw_params: Invalid argument
2483 01:10:52.671345 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2484 01:10:52.671843 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2485 01:10:52.676921 # # snd_pcm_hw_params: Invalid argument
2486 01:10:52.682425 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2487 01:10:52.688002 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2488 01:10:52.693563 # # snd_pcm_hw_params: Invalid argument
2489 01:10:52.699076 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2490 01:10:52.699589 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2491 01:10:52.704624 # # snd_pcm_hw_params: Invalid argument
2492 01:10:52.710170 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2493 01:10:52.715719 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2494 01:10:52.716259 # # snd_pcm_hw_params: Invalid argument
2495 01:10:52.726737 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2496 01:10:52.727268 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2497 01:10:52.732383 # # snd_pcm_hw_params: Invalid argument
2498 01:10:52.737962 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2499 01:10:52.743531 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2500 01:10:52.744233 # # snd_pcm_hw_params: Invalid argument
2501 01:10:52.754536 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2502 01:10:52.755136 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2503 01:10:52.760143 # # snd_pcm_hw_params: Invalid argument
2504 01:10:52.765629 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2505 01:10:52.771164 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2506 01:10:52.771696 # # snd_pcm_hw_params: Invalid argument
2507 01:10:52.776725 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2508 01:10:52.782278 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2509 01:10:52.787838 # # snd_pcm_hw_params: Invalid argument
2510 01:10:52.793372 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2511 01:10:52.798938 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2512 01:10:52.799504 # # snd_pcm_hw_params: Invalid argument
2513 01:10:52.804486 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2514 01:10:52.810055 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2515 01:10:52.815636 # # snd_pcm_hw_params: Invalid argument
2516 01:10:52.821174 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2517 01:10:52.826670 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2518 01:10:52.827227 # # snd_pcm_hw_params: Invalid argument
2519 01:10:52.832277 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2520 01:10:52.837745 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2521 01:10:52.843328 # # snd_pcm_hw_params: Invalid argument
2522 01:10:52.848852 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2523 01:10:52.854395 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2524 01:10:52.854954 # # snd_pcm_hw_params: Invalid argument
2525 01:10:52.860003 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2526 01:10:52.865487 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2527 01:10:52.871083 # # snd_pcm_hw_params: Invalid argument
2528 01:10:52.876601 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2529 01:10:52.882158 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2530 01:10:52.882717 # # snd_pcm_hw_params: Invalid argument
2531 01:10:52.887722 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2532 01:10:52.893252 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2533 01:10:52.898808 # # snd_pcm_hw_params: Invalid argument
2534 01:10:52.904367 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2535 01:10:52.909921 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2536 01:10:52.910490 # # snd_pcm_hw_params: Invalid argument
2537 01:10:52.915447 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2538 01:10:52.920990 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2539 01:10:52.926508 # # snd_pcm_hw_params: Invalid argument
2540 01:10:52.932071 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2541 01:10:52.937606 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2542 01:10:52.938145 # # snd_pcm_hw_params: Invalid argument
2543 01:10:52.943144 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2544 01:10:52.948692 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2545 01:10:52.954216 # # snd_pcm_hw_params: Invalid argument
2546 01:10:52.959776 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2547 01:10:52.965325 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2548 01:10:52.965863 # # snd_pcm_hw_params: Invalid argument
2549 01:10:52.970905 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2550 01:10:52.976420 ok 2 selftests: alsa: pcm-test
2551 01:10:52.976955 # timeout set to 45
2552 01:10:52.981955 # selftests: alsa: test-pcmtest-driver
2553 01:10:52.982501 # TAP version 13
2554 01:10:52.982972 # 1..5
2555 01:10:52.987494 # # Starting 5 tests from 1 test cases.
2556 01:10:52.988041 # # RUN pcmtest.playback ...
2557 01:10:52.993082 # # SKIP Can't read patterns. Probably, module isn't loaded
2558 01:10:52.998607 # # OK pcmtest.playback
2559 01:10:53.004188 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2560 01:10:53.009698 # # RUN pcmtest.capture ...
2561 01:10:53.015519 # # SKIP Can't read patterns. Probably, module isn't loaded
2562 01:10:53.020865 # # OK pcmtest.capture
2563 01:10:53.026376 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2564 01:10:53.032037 # # RUN pcmtest.ni_capture ...
2565 01:10:53.037461 # # SKIP Can't read patterns. Probably, module isn't loaded
2566 01:10:53.038033 # # OK pcmtest.ni_capture
2567 01:10:53.048643 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2568 01:10:53.049317 # # RUN pcmtest.ni_playback ...
2569 01:10:53.054159 # # SKIP Can't read patterns. Probably, module isn't loaded
2570 01:10:53.059589 # # OK pcmtest.ni_playback
2571 01:10:53.065149 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2572 01:10:53.070675 # # RUN pcmtest.reset_ioctl ...
2573 01:10:53.076318 # # SKIP Can't read patterns. Probably, module isn't loaded
2574 01:10:53.081775 # # OK pcmtest.reset_ioctl
2575 01:10:53.087400 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2576 01:10:53.092882 # # PASSED: 5 / 5 tests passed.
2577 01:10:53.098425 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2578 01:10:53.098928 ok 3 selftests: alsa: test-pcmtest-driver
2579 01:10:53.103964 # timeout set to 45
2580 01:10:53.104498 # selftests: alsa: utimer-test
2581 01:10:53.104940 # TAP version 13
2582 01:10:53.105373 # 1..2
2583 01:10:53.109523 # # Starting 2 tests from 2 test cases.
2584 01:10:53.115069 # # RUN global.wrong_timers_test ...
2585 01:10:53.120606 # # OK global.wrong_timers_test
2586 01:10:53.121110 # ok 1 global.wrong_timers_test
2587 01:10:53.126150 # # RUN timer_f.utimer ...
2588 01:10:53.137361 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2589 01:10:53.137897 # # utimer: Test terminated by assertion
2590 01:10:53.142807 # # FAIL timer_f.utimer
2591 01:10:53.143326 # not ok 2 timer_f.utimer
2592 01:10:53.148405 # # FAILED: 1 / 2 tests passed.
2593 01:10:53.156235 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2594 01:10:53.156747 not ok 4 selftests: alsa: utimer-test # exit=1
2595 01:10:53.664634 alsa_mixer-test_get_value_LCALTA_60 pass
2596 01:10:53.670072 alsa_mixer-test_name_LCALTA_60 pass
2597 01:10:53.670574 alsa_mixer-test_write_default_LCALTA_60 pass
2598 01:10:53.675577 alsa_mixer-test_write_valid_LCALTA_60 pass
2599 01:10:53.681118 alsa_mixer-test_write_invalid_LCALTA_60 pass
2600 01:10:53.686639 alsa_mixer-test_event_missing_LCALTA_60 pass
2601 01:10:53.687124 alsa_mixer-test_event_spurious_LCALTA_60 pass
2602 01:10:53.692207 alsa_mixer-test_get_value_LCALTA_59 pass
2603 01:10:53.697758 alsa_mixer-test_name_LCALTA_59 pass
2604 01:10:53.698243 alsa_mixer-test_write_default_LCALTA_59 pass
2605 01:10:53.703298 alsa_mixer-test_write_valid_LCALTA_59 pass
2606 01:10:53.708810 alsa_mixer-test_write_invalid_LCALTA_59 pass
2607 01:10:53.709297 alsa_mixer-test_event_missing_LCALTA_59 pass
2608 01:10:53.714383 alsa_mixer-test_event_spurious_LCALTA_59 pass
2609 01:10:53.719929 alsa_mixer-test_get_value_LCALTA_58 pass
2610 01:10:53.720439 alsa_mixer-test_name_LCALTA_58 pass
2611 01:10:53.725480 alsa_mixer-test_write_default_LCALTA_58 pass
2612 01:10:53.731042 alsa_mixer-test_write_valid_LCALTA_58 pass
2613 01:10:53.731518 alsa_mixer-test_write_invalid_LCALTA_58 pass
2614 01:10:53.736554 alsa_mixer-test_event_missing_LCALTA_58 pass
2615 01:10:53.742131 alsa_mixer-test_event_spurious_LCALTA_58 pass
2616 01:10:53.747660 alsa_mixer-test_get_value_LCALTA_57 pass
2617 01:10:53.748173 alsa_mixer-test_name_LCALTA_57 pass
2618 01:10:53.753338 alsa_mixer-test_write_default_LCALTA_57 pass
2619 01:10:53.758873 alsa_mixer-test_write_valid_LCALTA_57 pass
2620 01:10:53.759372 alsa_mixer-test_write_invalid_LCALTA_57 pass
2621 01:10:53.764459 alsa_mixer-test_event_missing_LCALTA_57 pass
2622 01:10:53.769962 alsa_mixer-test_event_spurious_LCALTA_57 pass
2623 01:10:53.770465 alsa_mixer-test_get_value_LCALTA_56 pass
2624 01:10:53.775532 alsa_mixer-test_name_LCALTA_56 pass
2625 01:10:53.781075 alsa_mixer-test_write_default_LCALTA_56 pass
2626 01:10:53.781570 alsa_mixer-test_write_valid_LCALTA_56 pass
2627 01:10:53.786589 alsa_mixer-test_write_invalid_LCALTA_56 pass
2628 01:10:53.792156 alsa_mixer-test_event_missing_LCALTA_56 pass
2629 01:10:53.797680 alsa_mixer-test_event_spurious_LCALTA_56 pass
2630 01:10:53.798176 alsa_mixer-test_get_value_LCALTA_55 pass
2631 01:10:53.803209 alsa_mixer-test_name_LCALTA_55 pass
2632 01:10:53.808818 alsa_mixer-test_write_default_LCALTA_55 pass
2633 01:10:53.809331 alsa_mixer-test_write_valid_LCALTA_55 pass
2634 01:10:53.814342 alsa_mixer-test_write_invalid_LCALTA_55 pass
2635 01:10:53.819884 alsa_mixer-test_event_missing_LCALTA_55 pass
2636 01:10:53.820408 alsa_mixer-test_event_spurious_LCALTA_55 pass
2637 01:10:53.825430 alsa_mixer-test_get_value_LCALTA_54 pass
2638 01:10:53.830982 alsa_mixer-test_name_LCALTA_54 pass
2639 01:10:53.831473 alsa_mixer-test_write_default_LCALTA_54 pass
2640 01:10:53.836519 alsa_mixer-test_write_valid_LCALTA_54 pass
2641 01:10:53.842066 alsa_mixer-test_write_invalid_LCALTA_54 pass
2642 01:10:53.842559 alsa_mixer-test_event_missing_LCALTA_54 pass
2643 01:10:53.847604 alsa_mixer-test_event_spurious_LCALTA_54 pass
2644 01:10:53.853153 alsa_mixer-test_get_value_LCALTA_53 pass
2645 01:10:53.853648 alsa_mixer-test_name_LCALTA_53 pass
2646 01:10:53.858891 alsa_mixer-test_write_default_LCALTA_53 pass
2647 01:10:53.864303 alsa_mixer-test_write_valid_LCALTA_53 pass
2648 01:10:53.869798 alsa_mixer-test_write_invalid_LCALTA_53 pass
2649 01:10:53.870291 alsa_mixer-test_event_missing_LCALTA_53 pass
2650 01:10:53.875364 alsa_mixer-test_event_spurious_LCALTA_53 pass
2651 01:10:53.880910 alsa_mixer-test_get_value_LCALTA_52 pass
2652 01:10:53.881399 alsa_mixer-test_name_LCALTA_52 pass
2653 01:10:53.886510 alsa_mixer-test_write_default_LCALTA_52 pass
2654 01:10:53.892045 alsa_mixer-test_write_valid_LCALTA_52 pass
2655 01:10:53.892537 alsa_mixer-test_write_invalid_LCALTA_52 pass
2656 01:10:53.897563 alsa_mixer-test_event_missing_LCALTA_52 pass
2657 01:10:53.903102 alsa_mixer-test_event_spurious_LCALTA_52 pass
2658 01:10:53.903597 alsa_mixer-test_get_value_LCALTA_51 pass
2659 01:10:53.908630 alsa_mixer-test_name_LCALTA_51 pass
2660 01:10:53.914178 alsa_mixer-test_write_default_LCALTA_51 pass
2661 01:10:53.914687 alsa_mixer-test_write_valid_LCALTA_51 pass
2662 01:10:53.919743 alsa_mixer-test_write_invalid_LCALTA_51 pass
2663 01:10:53.925286 alsa_mixer-test_event_missing_LCALTA_51 pass
2664 01:10:53.930832 alsa_mixer-test_event_spurious_LCALTA_51 pass
2665 01:10:53.931322 alsa_mixer-test_get_value_LCALTA_50 pass
2666 01:10:53.936351 alsa_mixer-test_name_LCALTA_50 pass
2667 01:10:53.941937 alsa_mixer-test_write_default_LCALTA_50 pass
2668 01:10:53.942440 alsa_mixer-test_write_valid_LCALTA_50 pass
2669 01:10:53.947507 alsa_mixer-test_write_invalid_LCALTA_50 pass
2670 01:10:53.952999 alsa_mixer-test_event_missing_LCALTA_50 pass
2671 01:10:53.953492 alsa_mixer-test_event_spurious_LCALTA_50 pass
2672 01:10:53.958558 alsa_mixer-test_get_value_LCALTA_49 pass
2673 01:10:53.964114 alsa_mixer-test_name_LCALTA_49 pass
2674 01:10:53.964612 alsa_mixer-test_write_default_LCALTA_49 pass
2675 01:10:53.969628 alsa_mixer-test_write_valid_LCALTA_49 pass
2676 01:10:53.975167 alsa_mixer-test_write_invalid_LCALTA_49 pass
2677 01:10:53.980744 alsa_mixer-test_event_missing_LCALTA_49 pass
2678 01:10:53.981251 alsa_mixer-test_event_spurious_LCALTA_49 pass
2679 01:10:53.986302 alsa_mixer-test_get_value_LCALTA_48 pass
2680 01:10:53.986804 alsa_mixer-test_name_LCALTA_48 pass
2681 01:10:53.991848 alsa_mixer-test_write_default_LCALTA_48 pass
2682 01:10:53.997490 alsa_mixer-test_write_valid_LCALTA_48 pass
2683 01:10:54.002915 alsa_mixer-test_write_invalid_LCALTA_48 pass
2684 01:10:54.003414 alsa_mixer-test_event_missing_LCALTA_48 pass
2685 01:10:54.008536 alsa_mixer-test_event_spurious_LCALTA_48 pass
2686 01:10:54.014005 alsa_mixer-test_get_value_LCALTA_47 pass
2687 01:10:54.014498 alsa_mixer-test_name_LCALTA_47 pass
2688 01:10:54.019573 alsa_mixer-test_write_default_LCALTA_47 pass
2689 01:10:54.025144 alsa_mixer-test_write_valid_LCALTA_47 pass
2690 01:10:54.025656 alsa_mixer-test_write_invalid_LCALTA_47 pass
2691 01:10:54.030659 alsa_mixer-test_event_missing_LCALTA_47 pass
2692 01:10:54.036273 alsa_mixer-test_event_spurious_LCALTA_47 pass
2693 01:10:54.041779 alsa_mixer-test_get_value_LCALTA_46 pass
2694 01:10:54.042276 alsa_mixer-test_name_LCALTA_46 pass
2695 01:10:54.047289 alsa_mixer-test_write_default_LCALTA_46 pass
2696 01:10:54.052832 alsa_mixer-test_write_valid_LCALTA_46 pass
2697 01:10:54.053328 alsa_mixer-test_write_invalid_LCALTA_46 pass
2698 01:10:54.058491 alsa_mixer-test_event_missing_LCALTA_46 pass
2699 01:10:54.063950 alsa_mixer-test_event_spurious_LCALTA_46 pass
2700 01:10:54.064470 alsa_mixer-test_get_value_LCALTA_45 pass
2701 01:10:54.069507 alsa_mixer-test_name_LCALTA_45 pass
2702 01:10:54.075029 alsa_mixer-test_write_default_LCALTA_45 pass
2703 01:10:54.075531 alsa_mixer-test_write_valid_LCALTA_45 pass
2704 01:10:54.080611 alsa_mixer-test_write_invalid_LCALTA_45 pass
2705 01:10:54.086153 alsa_mixer-test_event_missing_LCALTA_45 pass
2706 01:10:54.086654 alsa_mixer-test_event_spurious_LCALTA_45 pass
2707 01:10:54.091688 alsa_mixer-test_get_value_LCALTA_44 pass
2708 01:10:54.097233 alsa_mixer-test_name_LCALTA_44 pass
2709 01:10:54.097731 alsa_mixer-test_write_default_LCALTA_44 pass
2710 01:10:54.102770 alsa_mixer-test_write_valid_LCALTA_44 pass
2711 01:10:54.108317 alsa_mixer-test_write_invalid_LCALTA_44 pass
2712 01:10:54.113848 alsa_mixer-test_event_missing_LCALTA_44 pass
2713 01:10:54.114342 alsa_mixer-test_event_spurious_LCALTA_44 pass
2714 01:10:54.119502 alsa_mixer-test_get_value_LCALTA_43 pass
2715 01:10:54.124963 alsa_mixer-test_name_LCALTA_43 pass
2716 01:10:54.125456 alsa_mixer-test_write_default_LCALTA_43 pass
2717 01:10:54.130513 alsa_mixer-test_write_valid_LCALTA_43 pass
2718 01:10:54.136078 alsa_mixer-test_write_invalid_LCALTA_43 pass
2719 01:10:54.136576 alsa_mixer-test_event_missing_LCALTA_43 pass
2720 01:10:54.141608 alsa_mixer-test_event_spurious_LCALTA_43 pass
2721 01:10:54.147135 alsa_mixer-test_get_value_LCALTA_42 pass
2722 01:10:54.147637 alsa_mixer-test_name_LCALTA_42 pass
2723 01:10:54.152669 alsa_mixer-test_write_default_LCALTA_42 pass
2724 01:10:54.158221 alsa_mixer-test_write_valid_LCALTA_42 pass
2725 01:10:54.158717 alsa_mixer-test_write_invalid_LCALTA_42 pass
2726 01:10:54.163765 alsa_mixer-test_event_missing_LCALTA_42 pass
2727 01:10:54.169346 alsa_mixer-test_event_spurious_LCALTA_42 pass
2728 01:10:54.174872 alsa_mixer-test_get_value_LCALTA_41 pass
2729 01:10:54.175365 alsa_mixer-test_name_LCALTA_41 pass
2730 01:10:54.180515 alsa_mixer-test_write_default_LCALTA_41 pass
2731 01:10:54.185972 alsa_mixer-test_write_valid_LCALTA_41 pass
2732 01:10:54.186462 alsa_mixer-test_write_invalid_LCALTA_41 pass
2733 01:10:54.191536 alsa_mixer-test_event_missing_LCALTA_41 pass
2734 01:10:54.197087 alsa_mixer-test_event_spurious_LCALTA_41 pass
2735 01:10:54.197603 alsa_mixer-test_get_value_LCALTA_40 pass
2736 01:10:54.202627 alsa_mixer-test_name_LCALTA_40 pass
2737 01:10:54.208162 alsa_mixer-test_write_default_LCALTA_40 pass
2738 01:10:54.208659 alsa_mixer-test_write_valid_LCALTA_40 pass
2739 01:10:54.213681 alsa_mixer-test_write_invalid_LCALTA_40 pass
2740 01:10:54.219285 alsa_mixer-test_event_missing_LCALTA_40 pass
2741 01:10:54.224839 alsa_mixer-test_event_spurious_LCALTA_40 pass
2742 01:10:54.225368 alsa_mixer-test_get_value_LCALTA_39 pass
2743 01:10:54.230369 alsa_mixer-test_name_LCALTA_39 pass
2744 01:10:54.235915 alsa_mixer-test_write_default_LCALTA_39 pass
2745 01:10:54.236456 alsa_mixer-test_write_valid_LCALTA_39 pass
2746 01:10:54.241528 alsa_mixer-test_write_invalid_LCALTA_39 pass
2747 01:10:54.246997 alsa_mixer-test_event_missing_LCALTA_39 pass
2748 01:10:54.247484 alsa_mixer-test_event_spurious_LCALTA_39 pass
2749 01:10:54.252532 alsa_mixer-test_get_value_LCALTA_38 pass
2750 01:10:54.258090 alsa_mixer-test_name_LCALTA_38 pass
2751 01:10:54.258581 alsa_mixer-test_write_default_LCALTA_38 pass
2752 01:10:54.263636 alsa_mixer-test_write_valid_LCALTA_38 pass
2753 01:10:54.269159 alsa_mixer-test_write_invalid_LCALTA_38 pass
2754 01:10:54.269653 alsa_mixer-test_event_missing_LCALTA_38 pass
2755 01:10:54.274715 alsa_mixer-test_event_spurious_LCALTA_38 pass
2756 01:10:54.280307 alsa_mixer-test_get_value_LCALTA_37 pass
2757 01:10:54.280824 alsa_mixer-test_name_LCALTA_37 pass
2758 01:10:54.285838 alsa_mixer-test_write_default_LCALTA_37 pass
2759 01:10:54.291384 alsa_mixer-test_write_valid_LCALTA_37 pass
2760 01:10:54.296923 alsa_mixer-test_write_invalid_LCALTA_37 pass
2761 01:10:54.297426 alsa_mixer-test_event_missing_LCALTA_37 pass
2762 01:10:54.302559 alsa_mixer-test_event_spurious_LCALTA_37 pass
2763 01:10:54.308036 alsa_mixer-test_get_value_LCALTA_36 pass
2764 01:10:54.308546 alsa_mixer-test_name_LCALTA_36 pass
2765 01:10:54.313558 alsa_mixer-test_write_default_LCALTA_36 pass
2766 01:10:54.319102 alsa_mixer-test_write_valid_LCALTA_36 pass
2767 01:10:54.319595 alsa_mixer-test_write_invalid_LCALTA_36 pass
2768 01:10:54.324647 alsa_mixer-test_event_missing_LCALTA_36 pass
2769 01:10:54.330186 alsa_mixer-test_event_spurious_LCALTA_36 pass
2770 01:10:54.330678 alsa_mixer-test_get_value_LCALTA_35 pass
2771 01:10:54.335716 alsa_mixer-test_name_LCALTA_35 pass
2772 01:10:54.341301 alsa_mixer-test_write_default_LCALTA_35 pass
2773 01:10:54.341804 alsa_mixer-test_write_valid_LCALTA_35 pass
2774 01:10:54.346829 alsa_mixer-test_write_invalid_LCALTA_35 pass
2775 01:10:54.352378 alsa_mixer-test_event_missing_LCALTA_35 pass
2776 01:10:54.357941 alsa_mixer-test_event_spurious_LCALTA_35 pass
2777 01:10:54.358449 alsa_mixer-test_get_value_LCALTA_34 pass
2778 01:10:54.363525 alsa_mixer-test_name_LCALTA_34 pass
2779 01:10:54.369019 alsa_mixer-test_write_default_LCALTA_34 pass
2780 01:10:54.369517 alsa_mixer-test_write_valid_LCALTA_34 pass
2781 01:10:54.374549 alsa_mixer-test_write_invalid_LCALTA_34 pass
2782 01:10:54.380129 alsa_mixer-test_event_missing_LCALTA_34 pass
2783 01:10:54.380633 alsa_mixer-test_event_spurious_LCALTA_34 pass
2784 01:10:54.385636 alsa_mixer-test_get_value_LCALTA_33 pass
2785 01:10:54.391190 alsa_mixer-test_name_LCALTA_33 pass
2786 01:10:54.391685 alsa_mixer-test_write_default_LCALTA_33 pass
2787 01:10:54.396719 alsa_mixer-test_write_valid_LCALTA_33 pass
2788 01:10:54.402252 alsa_mixer-test_write_invalid_LCALTA_33 pass
2789 01:10:54.407817 alsa_mixer-test_event_missing_LCALTA_33 pass
2790 01:10:54.408372 alsa_mixer-test_event_spurious_LCALTA_33 pass
2791 01:10:54.413380 alsa_mixer-test_get_value_LCALTA_32 pass
2792 01:10:54.413887 alsa_mixer-test_name_LCALTA_32 pass
2793 01:10:54.418951 alsa_mixer-test_write_default_LCALTA_32 pass
2794 01:10:54.424516 alsa_mixer-test_write_valid_LCALTA_32 pass
2795 01:10:54.429979 alsa_mixer-test_write_invalid_LCALTA_32 pass
2796 01:10:54.430470 alsa_mixer-test_event_missing_LCALTA_32 pass
2797 01:10:54.435529 alsa_mixer-test_event_spurious_LCALTA_32 pass
2798 01:10:54.441083 alsa_mixer-test_get_value_LCALTA_31 pass
2799 01:10:54.441577 alsa_mixer-test_name_LCALTA_31 pass
2800 01:10:54.446623 alsa_mixer-test_write_default_LCALTA_31 pass
2801 01:10:54.452206 alsa_mixer-test_write_valid_LCALTA_31 pass
2802 01:10:54.452695 alsa_mixer-test_write_invalid_LCALTA_31 pass
2803 01:10:54.457740 alsa_mixer-test_event_missing_LCALTA_31 pass
2804 01:10:54.463254 alsa_mixer-test_event_spurious_LCALTA_31 pass
2805 01:10:54.468807 alsa_mixer-test_get_value_LCALTA_30 pass
2806 01:10:54.469297 alsa_mixer-test_name_LCALTA_30 pass
2807 01:10:54.474364 alsa_mixer-test_write_default_LCALTA_30 pass
2808 01:10:54.479896 alsa_mixer-test_write_valid_LCALTA_30 pass
2809 01:10:54.480422 alsa_mixer-test_write_invalid_LCALTA_30 pass
2810 01:10:54.485512 alsa_mixer-test_event_missing_LCALTA_30 pass
2811 01:10:54.491015 alsa_mixer-test_event_spurious_LCALTA_30 pass
2812 01:10:54.491513 alsa_mixer-test_get_value_LCALTA_29 pass
2813 01:10:54.496545 alsa_mixer-test_name_LCALTA_29 pass
2814 01:10:54.502144 alsa_mixer-test_write_default_LCALTA_29 pass
2815 01:10:54.502658 alsa_mixer-test_write_valid_LCALTA_29 pass
2816 01:10:54.507677 alsa_mixer-test_write_invalid_LCALTA_29 pass
2817 01:10:54.513252 alsa_mixer-test_event_missing_LCALTA_29 pass
2818 01:10:54.513751 alsa_mixer-test_event_spurious_LCALTA_29 pass
2819 01:10:54.518797 alsa_mixer-test_get_value_LCALTA_28 pass
2820 01:10:54.524345 alsa_mixer-test_name_LCALTA_28 pass
2821 01:10:54.524844 alsa_mixer-test_write_default_LCALTA_28 pass
2822 01:10:54.529889 alsa_mixer-test_write_valid_LCALTA_28 pass
2823 01:10:54.535400 alsa_mixer-test_write_invalid_LCALTA_28 pass
2824 01:10:54.540968 alsa_mixer-test_event_missing_LCALTA_28 pass
2825 01:10:54.541479 alsa_mixer-test_event_spurious_LCALTA_28 pass
2826 01:10:54.546538 alsa_mixer-test_get_value_LCALTA_27 pass
2827 01:10:54.552081 alsa_mixer-test_name_LCALTA_27 pass
2828 01:10:54.552583 alsa_mixer-test_write_default_LCALTA_27 pass
2829 01:10:54.557591 alsa_mixer-test_write_valid_LCALTA_27 pass
2830 01:10:54.563163 alsa_mixer-test_write_invalid_LCALTA_27 pass
2831 01:10:54.563665 alsa_mixer-test_event_missing_LCALTA_27 pass
2832 01:10:54.568730 alsa_mixer-test_event_spurious_LCALTA_27 pass
2833 01:10:54.574243 alsa_mixer-test_get_value_LCALTA_26 pass
2834 01:10:54.574734 alsa_mixer-test_name_LCALTA_26 pass
2835 01:10:54.579801 alsa_mixer-test_write_default_LCALTA_26 skip
2836 01:10:54.585332 alsa_mixer-test_write_valid_LCALTA_26 skip
2837 01:10:54.585824 alsa_mixer-test_write_invalid_LCALTA_26 skip
2838 01:10:54.590871 alsa_mixer-test_event_missing_LCALTA_26 pass
2839 01:10:54.596382 alsa_mixer-test_event_spurious_LCALTA_26 pass
2840 01:10:54.601955 alsa_mixer-test_get_value_LCALTA_25 pass
2841 01:10:54.602447 alsa_mixer-test_name_LCALTA_25 pass
2842 01:10:54.607527 alsa_mixer-test_write_default_LCALTA_25 pass
2843 01:10:54.613049 alsa_mixer-test_write_valid_LCALTA_25 skip
2844 01:10:54.613536 alsa_mixer-test_write_invalid_LCALTA_25 skip
2845 01:10:54.618594 alsa_mixer-test_event_missing_LCALTA_25 pass
2846 01:10:54.624168 alsa_mixer-test_event_spurious_LCALTA_25 pass
2847 01:10:54.624655 alsa_mixer-test_get_value_LCALTA_24 pass
2848 01:10:54.629691 alsa_mixer-test_name_LCALTA_24 pass
2849 01:10:54.635207 alsa_mixer-test_write_default_LCALTA_24 skip
2850 01:10:54.635695 alsa_mixer-test_write_valid_LCALTA_24 skip
2851 01:10:54.640783 alsa_mixer-test_write_invalid_LCALTA_24 skip
2852 01:10:54.646304 alsa_mixer-test_event_missing_LCALTA_24 pass
2853 01:10:54.651858 alsa_mixer-test_event_spurious_LCALTA_24 pass
2854 01:10:54.652381 alsa_mixer-test_get_value_LCALTA_23 pass
2855 01:10:54.657383 alsa_mixer-test_name_LCALTA_23 pass
2856 01:10:54.662953 alsa_mixer-test_write_default_LCALTA_23 skip
2857 01:10:54.663444 alsa_mixer-test_write_valid_LCALTA_23 skip
2858 01:10:54.668541 alsa_mixer-test_write_invalid_LCALTA_23 skip
2859 01:10:54.674088 alsa_mixer-test_event_missing_LCALTA_23 pass
2860 01:10:54.674585 alsa_mixer-test_event_spurious_LCALTA_23 pass
2861 01:10:54.679619 alsa_mixer-test_get_value_LCALTA_22 pass
2862 01:10:54.685159 alsa_mixer-test_name_LCALTA_22 pass
2863 01:10:54.685654 alsa_mixer-test_write_default_LCALTA_22 pass
2864 01:10:54.690689 alsa_mixer-test_write_valid_LCALTA_22 pass
2865 01:10:54.696287 alsa_mixer-test_write_invalid_LCALTA_22 pass
2866 01:10:54.696775 alsa_mixer-test_event_missing_LCALTA_22 pass
2867 01:10:54.701819 alsa_mixer-test_event_spurious_LCALTA_22 pass
2868 01:10:54.707355 alsa_mixer-test_get_value_LCALTA_21 pass
2869 01:10:54.707849 alsa_mixer-test_name_LCALTA_21 pass
2870 01:10:54.712904 alsa_mixer-test_write_default_LCALTA_21 pass
2871 01:10:54.718467 alsa_mixer-test_write_valid_LCALTA_21 pass
2872 01:10:54.724031 alsa_mixer-test_write_invalid_LCALTA_21 pass
2873 01:10:54.724530 alsa_mixer-test_event_missing_LCALTA_21 pass
2874 01:10:54.729546 alsa_mixer-test_event_spurious_LCALTA_21 pass
2875 01:10:54.735075 alsa_mixer-test_get_value_LCALTA_20 pass
2876 01:10:54.735572 alsa_mixer-test_name_LCALTA_20 pass
2877 01:10:54.740664 alsa_mixer-test_write_default_LCALTA_20 pass
2878 01:10:54.746175 alsa_mixer-test_write_valid_LCALTA_20 pass
2879 01:10:54.746674 alsa_mixer-test_write_invalid_LCALTA_20 pass
2880 01:10:54.751720 alsa_mixer-test_event_missing_LCALTA_20 pass
2881 01:10:54.757293 alsa_mixer-test_event_spurious_LCALTA_20 pass
2882 01:10:54.757790 alsa_mixer-test_get_value_LCALTA_19 pass
2883 01:10:54.762820 alsa_mixer-test_name_LCALTA_19 pass
2884 01:10:54.768358 alsa_mixer-test_write_default_LCALTA_19 pass
2885 01:10:54.768853 alsa_mixer-test_write_valid_LCALTA_19 pass
2886 01:10:54.773908 alsa_mixer-test_write_invalid_LCALTA_19 pass
2887 01:10:54.779455 alsa_mixer-test_event_missing_LCALTA_19 pass
2888 01:10:54.785002 alsa_mixer-test_event_spurious_LCALTA_19 pass
2889 01:10:54.785499 alsa_mixer-test_get_value_LCALTA_18 pass
2890 01:10:54.790548 alsa_mixer-test_name_LCALTA_18 pass
2891 01:10:54.796114 alsa_mixer-test_write_default_LCALTA_18 pass
2892 01:10:54.796619 alsa_mixer-test_write_valid_LCALTA_18 pass
2893 01:10:54.801663 alsa_mixer-test_write_invalid_LCALTA_18 pass
2894 01:10:54.807204 alsa_mixer-test_event_missing_LCALTA_18 pass
2895 01:10:54.807704 alsa_mixer-test_event_spurious_LCALTA_18 pass
2896 01:10:54.812746 alsa_mixer-test_get_value_LCALTA_17 pass
2897 01:10:54.818282 alsa_mixer-test_name_LCALTA_17 pass
2898 01:10:54.818797 alsa_mixer-test_write_default_LCALTA_17 pass
2899 01:10:54.823819 alsa_mixer-test_write_valid_LCALTA_17 pass
2900 01:10:54.829396 alsa_mixer-test_write_invalid_LCALTA_17 pass
2901 01:10:54.834915 alsa_mixer-test_event_missing_LCALTA_17 pass
2902 01:10:54.835413 alsa_mixer-test_event_spurious_LCALTA_17 pass
2903 01:10:54.840456 alsa_mixer-test_get_value_LCALTA_16 pass
2904 01:10:54.840953 alsa_mixer-test_name_LCALTA_16 pass
2905 01:10:54.846005 alsa_mixer-test_write_default_LCALTA_16 pass
2906 01:10:54.851566 alsa_mixer-test_write_valid_LCALTA_16 pass
2907 01:10:54.857143 alsa_mixer-test_write_invalid_LCALTA_16 pass
2908 01:10:54.857660 alsa_mixer-test_event_missing_LCALTA_16 pass
2909 01:10:54.862696 alsa_mixer-test_event_spurious_LCALTA_16 pass
2910 01:10:54.868260 alsa_mixer-test_get_value_LCALTA_15 pass
2911 01:10:54.868766 alsa_mixer-test_name_LCALTA_15 pass
2912 01:10:54.873750 alsa_mixer-test_write_default_LCALTA_15 pass
2913 01:10:54.879322 alsa_mixer-test_write_valid_LCALTA_15 pass
2914 01:10:54.879818 alsa_mixer-test_write_invalid_LCALTA_15 pass
2915 01:10:54.884836 alsa_mixer-test_event_missing_LCALTA_15 pass
2916 01:10:54.890379 alsa_mixer-test_event_spurious_LCALTA_15 pass
2917 01:10:54.895940 alsa_mixer-test_get_value_LCALTA_14 pass
2918 01:10:54.896467 alsa_mixer-test_name_LCALTA_14 pass
2919 01:10:54.901499 alsa_mixer-test_write_default_LCALTA_14 pass
2920 01:10:54.907025 alsa_mixer-test_write_valid_LCALTA_14 pass
2921 01:10:54.907522 alsa_mixer-test_write_invalid_LCALTA_14 pass
2922 01:10:54.912582 alsa_mixer-test_event_missing_LCALTA_14 pass
2923 01:10:54.918152 alsa_mixer-test_event_spurious_LCALTA_14 pass
2924 01:10:54.918647 alsa_mixer-test_get_value_LCALTA_13 pass
2925 01:10:54.923680 alsa_mixer-test_name_LCALTA_13 pass
2926 01:10:54.929252 alsa_mixer-test_write_default_LCALTA_13 pass
2927 01:10:54.929764 alsa_mixer-test_write_valid_LCALTA_13 pass
2928 01:10:54.934803 alsa_mixer-test_write_invalid_LCALTA_13 pass
2929 01:10:54.940360 alsa_mixer-test_event_missing_LCALTA_13 pass
2930 01:10:54.940873 alsa_mixer-test_event_spurious_LCALTA_13 pass
2931 01:10:54.945868 alsa_mixer-test_get_value_LCALTA_12 pass
2932 01:10:54.951415 alsa_mixer-test_name_LCALTA_12 pass
2933 01:10:54.951918 alsa_mixer-test_write_default_LCALTA_12 pass
2934 01:10:54.956967 alsa_mixer-test_write_valid_LCALTA_12 pass
2935 01:10:54.962518 alsa_mixer-test_write_invalid_LCALTA_12 pass
2936 01:10:54.968085 alsa_mixer-test_event_missing_LCALTA_12 pass
2937 01:10:54.968601 alsa_mixer-test_event_spurious_LCALTA_12 pass
2938 01:10:54.973590 alsa_mixer-test_get_value_LCALTA_11 pass
2939 01:10:54.979170 alsa_mixer-test_name_LCALTA_11 pass
2940 01:10:54.979680 alsa_mixer-test_write_default_LCALTA_11 pass
2941 01:10:54.984711 alsa_mixer-test_write_valid_LCALTA_11 pass
2942 01:10:54.990246 alsa_mixer-test_write_invalid_LCALTA_11 pass
2943 01:10:54.990762 alsa_mixer-test_event_missing_LCALTA_11 pass
2944 01:10:54.995810 alsa_mixer-test_event_spurious_LCALTA_11 pass
2945 01:10:55.001349 alsa_mixer-test_get_value_LCALTA_10 pass
2946 01:10:55.001866 alsa_mixer-test_name_LCALTA_10 pass
2947 01:10:55.006895 alsa_mixer-test_write_default_LCALTA_10 pass
2948 01:10:55.012436 alsa_mixer-test_write_valid_LCALTA_10 pass
2949 01:10:55.012950 alsa_mixer-test_write_invalid_LCALTA_10 pass
2950 01:10:55.017998 alsa_mixer-test_event_missing_LCALTA_10 pass
2951 01:10:55.023543 alsa_mixer-test_event_spurious_LCALTA_10 pass
2952 01:10:55.029153 alsa_mixer-test_get_value_LCALTA_9 pass
2953 01:10:55.029728 alsa_mixer-test_name_LCALTA_9 pass
2954 01:10:55.034741 alsa_mixer-test_write_default_LCALTA_9 pass
2955 01:10:55.040277 alsa_mixer-test_write_valid_LCALTA_9 pass
2956 01:10:55.040793 alsa_mixer-test_write_invalid_LCALTA_9 pass
2957 01:10:55.045713 alsa_mixer-test_event_missing_LCALTA_9 pass
2958 01:10:55.051214 alsa_mixer-test_event_spurious_LCALTA_9 pass
2959 01:10:55.051769 alsa_mixer-test_get_value_LCALTA_8 pass
2960 01:10:55.056742 alsa_mixer-test_name_LCALTA_8 pass
2961 01:10:55.062333 alsa_mixer-test_write_default_LCALTA_8 pass
2962 01:10:55.062888 alsa_mixer-test_write_valid_LCALTA_8 pass
2963 01:10:55.067852 alsa_mixer-test_write_invalid_LCALTA_8 pass
2964 01:10:55.073355 alsa_mixer-test_event_missing_LCALTA_8 pass
2965 01:10:55.073826 alsa_mixer-test_event_spurious_LCALTA_8 pass
2966 01:10:55.078886 alsa_mixer-test_get_value_LCALTA_7 pass
2967 01:10:55.084534 alsa_mixer-test_name_LCALTA_7 pass
2968 01:10:55.085007 alsa_mixer-test_write_default_LCALTA_7 pass
2969 01:10:55.089979 alsa_mixer-test_write_valid_LCALTA_7 pass
2970 01:10:55.095543 alsa_mixer-test_write_invalid_LCALTA_7 pass
2971 01:10:55.096033 alsa_mixer-test_event_missing_LCALTA_7 pass
2972 01:10:55.101093 alsa_mixer-test_event_spurious_LCALTA_7 pass
2973 01:10:55.106653 alsa_mixer-test_get_value_LCALTA_6 pass
2974 01:10:55.107120 alsa_mixer-test_name_LCALTA_6 pass
2975 01:10:55.112191 alsa_mixer-test_write_default_LCALTA_6 pass
2976 01:10:55.117709 alsa_mixer-test_write_valid_LCALTA_6 pass
2977 01:10:55.118165 alsa_mixer-test_write_invalid_LCALTA_6 pass
2978 01:10:55.123284 alsa_mixer-test_event_missing_LCALTA_6 pass
2979 01:10:55.128827 alsa_mixer-test_event_spurious_LCALTA_6 pass
2980 01:10:55.129300 alsa_mixer-test_get_value_LCALTA_5 pass
2981 01:10:55.134359 alsa_mixer-test_name_LCALTA_5 pass
2982 01:10:55.139913 alsa_mixer-test_write_default_LCALTA_5 pass
2983 01:10:55.140438 alsa_mixer-test_write_valid_LCALTA_5 pass
2984 01:10:55.145544 alsa_mixer-test_write_invalid_LCALTA_5 pass
2985 01:10:55.151015 alsa_mixer-test_event_missing_LCALTA_5 pass
2986 01:10:55.151480 alsa_mixer-test_event_spurious_LCALTA_5 pass
2987 01:10:55.156572 alsa_mixer-test_get_value_LCALTA_4 pass
2988 01:10:55.162059 alsa_mixer-test_name_LCALTA_4 pass
2989 01:10:55.162519 alsa_mixer-test_write_default_LCALTA_4 pass
2990 01:10:55.167638 alsa_mixer-test_write_valid_LCALTA_4 pass
2991 01:10:55.173196 alsa_mixer-test_write_invalid_LCALTA_4 pass
2992 01:10:55.173681 alsa_mixer-test_event_missing_LCALTA_4 pass
2993 01:10:55.178746 alsa_mixer-test_event_spurious_LCALTA_4 pass
2994 01:10:55.184292 alsa_mixer-test_get_value_LCALTA_3 pass
2995 01:10:55.184757 alsa_mixer-test_name_LCALTA_3 pass
2996 01:10:55.189842 alsa_mixer-test_write_default_LCALTA_3 pass
2997 01:10:55.195393 alsa_mixer-test_write_valid_LCALTA_3 pass
2998 01:10:55.195850 alsa_mixer-test_write_invalid_LCALTA_3 pass
2999 01:10:55.200913 alsa_mixer-test_event_missing_LCALTA_3 pass
3000 01:10:55.206559 alsa_mixer-test_event_spurious_LCALTA_3 pass
3001 01:10:55.207015 alsa_mixer-test_get_value_LCALTA_2 pass
3002 01:10:55.212033 alsa_mixer-test_name_LCALTA_2 pass
3003 01:10:55.217585 alsa_mixer-test_write_default_LCALTA_2 pass
3004 01:10:55.218042 alsa_mixer-test_write_valid_LCALTA_2 pass
3005 01:10:55.223133 alsa_mixer-test_write_invalid_LCALTA_2 pass
3006 01:10:55.228676 alsa_mixer-test_event_missing_LCALTA_2 pass
3007 01:10:55.234222 alsa_mixer-test_event_spurious_LCALTA_2 pass
3008 01:10:55.234708 alsa_mixer-test_get_value_LCALTA_1 pass
3009 01:10:55.239751 alsa_mixer-test_name_LCALTA_1 pass
3010 01:10:55.240256 alsa_mixer-test_write_default_LCALTA_1 pass
3011 01:10:55.245328 alsa_mixer-test_write_valid_LCALTA_1 pass
3012 01:10:55.250850 alsa_mixer-test_write_invalid_LCALTA_1 pass
3013 01:10:55.256426 alsa_mixer-test_event_missing_LCALTA_1 pass
3014 01:10:55.256949 alsa_mixer-test_event_spurious_LCALTA_1 pass
3015 01:10:55.261953 alsa_mixer-test_get_value_LCALTA_0 pass
3016 01:10:55.262427 alsa_mixer-test_name_LCALTA_0 pass
3017 01:10:55.267564 alsa_mixer-test_write_default_LCALTA_0 pass
3018 01:10:55.273060 alsa_mixer-test_write_valid_LCALTA_0 pass
3019 01:10:55.278602 alsa_mixer-test_write_invalid_LCALTA_0 pass
3020 01:10:55.279068 alsa_mixer-test_event_missing_LCALTA_0 pass
3021 01:10:55.284175 alsa_mixer-test_event_spurious_LCALTA_0 pass
3022 01:10:55.284636 alsa_mixer-test pass
3023 01:10:55.289712 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
3024 01:10:55.295239 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
3025 01:10:55.300783 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
3026 01:10:55.306304 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
3027 01:10:55.306778 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
3028 01:10:55.311853 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
3029 01:10:55.317424 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
3030 01:10:55.323000 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
3031 01:10:55.328579 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
3032 01:10:55.334097 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
3033 01:10:55.334585 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
3034 01:10:55.339742 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
3035 01:10:55.345165 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
3036 01:10:55.350734 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
3037 01:10:55.356293 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
3038 01:10:55.361852 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
3039 01:10:55.362387 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
3040 01:10:55.367337 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
3041 01:10:55.372893 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
3042 01:10:55.378458 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
3043 01:10:55.384073 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
3044 01:10:55.389609 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
3045 01:10:55.390152 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
3046 01:10:55.395088 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
3047 01:10:55.400667 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
3048 01:10:55.406213 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
3049 01:10:55.411866 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
3050 01:10:55.417445 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
3051 01:10:55.418074 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
3052 01:10:55.422884 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
3053 01:10:55.428339 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
3054 01:10:55.433896 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
3055 01:10:55.439432 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
3056 01:10:55.445033 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
3057 01:10:55.450623 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
3058 01:10:55.451243 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
3059 01:10:55.456143 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
3060 01:10:55.461677 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
3061 01:10:55.467200 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
3062 01:10:55.472739 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
3063 01:10:55.478272 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
3064 01:10:55.478823 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
3065 01:10:55.483846 alsa_pcm-test pass
3066 01:10:55.489487 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3067 01:10:55.500510 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3068 01:10:55.506025 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3069 01:10:55.517177 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3070 01:10:55.522700 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3071 01:10:55.528285 alsa_test-pcmtest-driver pass
3072 01:10:55.533811 alsa_utimer-test_global_wrong_timers_test pass
3073 01:10:55.534435 alsa_utimer-test_timer_f_utimer fail
3074 01:10:55.539343 alsa_utimer-test fail
3075 01:10:55.540021 + ../../utils/send-to-lava.sh ./output/result.txt
3076 01:10:55.544911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
3077 01:10:55.545964 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
3079 01:10:55.555919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
3080 01:10:55.556858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
3082 01:10:55.561766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
3083 01:10:55.562643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
3085 01:10:55.585463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
3086 01:10:55.586483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
3088 01:10:55.633700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
3089 01:10:55.634666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
3091 01:10:55.690236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
3092 01:10:55.691134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
3094 01:10:55.740609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
3095 01:10:55.741522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
3097 01:10:55.786170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
3098 01:10:55.787099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
3100 01:10:55.831972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
3101 01:10:55.832966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
3103 01:10:55.882406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
3104 01:10:55.883428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
3106 01:10:55.935817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
3107 01:10:55.936871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
3109 01:10:55.985900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
3110 01:10:55.986835 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
3112 01:10:56.037415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
3113 01:10:56.038360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
3115 01:10:56.083055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
3116 01:10:56.083910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
3118 01:10:56.133861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
3119 01:10:56.134695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
3121 01:10:56.185393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
3122 01:10:56.186361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
3124 01:10:56.236149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
3125 01:10:56.237110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
3127 01:10:56.281746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
3128 01:10:56.282629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
3130 01:10:56.341246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
3131 01:10:56.342209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
3133 01:10:56.394528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
3134 01:10:56.395410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
3136 01:10:56.442608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
3137 01:10:56.443494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
3139 01:10:56.490388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
3140 01:10:56.491308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
3142 01:10:56.541718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
3143 01:10:56.542685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
3145 01:10:56.592862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
3146 01:10:56.593851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
3148 01:10:56.645834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
3149 01:10:56.646691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
3151 01:10:56.705055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
3152 01:10:56.706044 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
3154 01:10:56.758531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3155 01:10:56.759427 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3157 01:10:56.812185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3158 01:10:56.813092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3160 01:10:56.863918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3161 01:10:56.864869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3163 01:10:56.909014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3164 01:10:56.909990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3166 01:10:56.955437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3167 01:10:56.956404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3169 01:10:57.006204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3170 01:10:57.007068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3172 01:10:57.064662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3173 01:10:57.065614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3175 01:10:57.111910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3176 01:10:57.112859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3178 01:10:57.171309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3179 01:10:57.172285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3181 01:10:57.228451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3182 01:10:57.229318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3184 01:10:57.279727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3185 01:10:57.280643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3187 01:10:57.330445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3188 01:10:57.331340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3190 01:10:57.375680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3191 01:10:57.376593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3193 01:10:57.440132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3194 01:10:57.441016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3196 01:10:57.484944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3197 01:10:57.485811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3199 01:10:57.543332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3200 01:10:57.544241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3202 01:10:57.598277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3203 01:10:57.599159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3205 01:10:57.646555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3206 01:10:57.647426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3208 01:10:57.689380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3209 01:10:57.690209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3211 01:10:57.762860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3212 01:10:57.763797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3214 01:10:57.816174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3215 01:10:57.817104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3217 01:10:57.872286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3218 01:10:57.872972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3220 01:10:57.931131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3221 01:10:57.932089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3223 01:10:57.987438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3224 01:10:57.988350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3226 01:10:58.043758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3227 01:10:58.044719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3229 01:10:58.097991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3230 01:10:58.098920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3232 01:10:58.147584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3233 01:10:58.148585 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3235 01:10:58.204358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3236 01:10:58.205263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3238 01:10:58.266796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3239 01:10:58.267689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3241 01:10:58.316198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3242 01:10:58.317108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3244 01:10:58.376132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3245 01:10:58.377075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3247 01:10:58.448385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3248 01:10:58.449399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3250 01:10:58.501120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3251 01:10:58.502066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3253 01:10:58.547767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3254 01:10:58.548786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3256 01:10:58.606982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3257 01:10:58.607888 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3259 01:10:58.665937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3260 01:10:58.666948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3262 01:10:58.715705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3263 01:10:58.716701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3265 01:10:58.765209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3266 01:10:58.766142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3268 01:10:58.833623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3269 01:10:58.834426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3271 01:10:58.885392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3272 01:10:58.886048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3274 01:10:58.940314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3275 01:10:58.940957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3277 01:10:59.004074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3278 01:10:59.004715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3280 01:10:59.065341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3281 01:10:59.065986 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3283 01:10:59.113911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3284 01:10:59.114846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3286 01:10:59.176623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3287 01:10:59.177547 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3289 01:10:59.241560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3290 01:10:59.242417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3292 01:10:59.304675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3293 01:10:59.305528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3295 01:10:59.354218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3296 01:10:59.355027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3298 01:10:59.405331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3299 01:10:59.406130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3301 01:10:59.464237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3302 01:10:59.465123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3304 01:10:59.515253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3305 01:10:59.516111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3307 01:10:59.571445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3308 01:10:59.572371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3310 01:10:59.622957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3311 01:10:59.623839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3313 01:10:59.667976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3314 01:10:59.668807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3316 01:10:59.713006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3317 01:10:59.713806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3319 01:10:59.763925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3320 01:10:59.764815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3322 01:10:59.813820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3323 01:10:59.814642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3325 01:10:59.857845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3326 01:10:59.858671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3328 01:10:59.905284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3329 01:10:59.906091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3331 01:10:59.950493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3332 01:10:59.951301 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3334 01:10:59.993628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3335 01:10:59.994425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3337 01:11:00.051512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3338 01:11:00.052461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3340 01:11:00.101908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3341 01:11:00.102795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3343 01:11:00.155366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3344 01:11:00.156179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3346 01:11:00.206563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3347 01:11:00.207357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3349 01:11:00.257972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3350 01:11:00.258753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3352 01:11:00.314999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3353 01:11:00.315798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3355 01:11:00.363564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3356 01:11:00.364442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3358 01:11:00.409048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3359 01:11:00.410021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3361 01:11:00.454957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3362 01:11:00.455843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3364 01:11:00.499620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3365 01:11:00.500512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3367 01:11:00.558573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3368 01:11:00.559406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3370 01:11:00.609736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3371 01:11:00.610626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3373 01:11:00.661569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3374 01:11:00.662449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3376 01:11:00.706227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3377 01:11:00.707108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3379 01:11:00.764266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3380 01:11:00.765159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3382 01:11:00.817096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3383 01:11:00.817976 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3385 01:11:00.873925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3386 01:11:00.874794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3388 01:11:00.919141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3389 01:11:00.920004 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3391 01:11:00.967814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3392 01:11:00.968677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3394 01:11:01.020458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3395 01:11:01.021310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3397 01:11:01.075271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3398 01:11:01.076099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3400 01:11:01.122149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3401 01:11:01.122980 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3403 01:11:01.179327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3404 01:11:01.180075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3406 01:11:01.241492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3407 01:11:01.242330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3409 01:11:01.286804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3410 01:11:01.287592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3412 01:11:01.335470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3413 01:11:01.336307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3415 01:11:01.388446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3416 01:11:01.389204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3418 01:11:01.441627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3419 01:11:01.442476 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3421 01:11:01.497357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3422 01:11:01.498186 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3424 01:11:01.552470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3425 01:11:01.553324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3427 01:11:01.603664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3428 01:11:01.604560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3430 01:11:01.648432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3431 01:11:01.649199 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3433 01:11:01.696825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3434 01:11:01.697620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3436 01:11:01.751858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3437 01:11:01.752735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3439 01:11:01.800267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3440 01:11:01.801050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3442 01:11:01.857165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3443 01:11:01.857944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3445 01:11:01.902561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3446 01:11:01.903370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3448 01:11:01.950713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3449 01:11:01.951536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3451 01:11:02.004509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3452 01:11:02.005309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3454 01:11:02.078439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3455 01:11:02.079221 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3457 01:11:02.122330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3458 01:11:02.123154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3460 01:11:02.168239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3461 01:11:02.169024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3463 01:11:02.218221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3464 01:11:02.218999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3466 01:11:02.281051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3467 01:11:02.281806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3469 01:11:02.327157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3470 01:11:02.327935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3472 01:11:02.372723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3473 01:11:02.373447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3475 01:11:02.426709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3476 01:11:02.427538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3478 01:11:02.475485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3479 01:11:02.476356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3481 01:11:02.527833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3482 01:11:02.528705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3484 01:11:02.581238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3485 01:11:02.582046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3487 01:11:02.629125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3488 01:11:02.629942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3490 01:11:02.686496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3491 01:11:02.687285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3493 01:11:02.739299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3494 01:11:02.740108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3496 01:11:02.784183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3497 01:11:02.784893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3499 01:11:02.827021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3500 01:11:02.827791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3502 01:11:02.870829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3503 01:11:02.871575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3505 01:11:02.917735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3506 01:11:02.918496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3508 01:11:02.963639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3509 01:11:02.964478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3511 01:11:03.010912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3512 01:11:03.011692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3514 01:11:03.071969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3515 01:11:03.072964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3517 01:11:03.127256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3518 01:11:03.128075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3520 01:11:03.182345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3521 01:11:03.183070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3523 01:11:03.236906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3524 01:11:03.237680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3526 01:11:03.289844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3527 01:11:03.290591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3529 01:11:03.343885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3530 01:11:03.344706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3532 01:11:03.397610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3533 01:11:03.398341 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3535 01:11:03.451502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3536 01:11:03.452358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3538 01:11:03.497322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3539 01:11:03.498061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3541 01:11:03.541049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3542 01:11:03.541855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3544 01:11:03.584220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3545 01:11:03.584994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3547 01:11:03.643931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3548 01:11:03.644739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3550 01:11:03.696507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3551 01:11:03.697224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3553 01:11:03.749462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3554 01:11:03.750249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3556 01:11:03.801483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3557 01:11:03.802196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3559 01:11:03.854996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3560 01:11:03.855777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3562 01:11:03.905268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3563 01:11:03.905989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3565 01:11:03.954705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3566 01:11:03.955497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3568 01:11:04.005764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3569 01:11:04.006573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3571 01:11:04.060058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3572 01:11:04.060890 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3574 01:11:04.114967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3575 01:11:04.115784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3577 01:11:04.166783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3578 01:11:04.167702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3580 01:11:04.212797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3581 01:11:04.213633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3583 01:11:04.258549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3584 01:11:04.259292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3586 01:11:04.309034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3587 01:11:04.309755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3589 01:11:04.357471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3590 01:11:04.358207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3592 01:11:04.412938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3593 01:11:04.414035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3595 01:11:04.468565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3596 01:11:04.469349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3598 01:11:04.516742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3599 01:11:04.517567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3601 01:11:04.569269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3602 01:11:04.570063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3604 01:11:04.624968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3605 01:11:04.625781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3607 01:11:04.677286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3608 01:11:04.678107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3610 01:11:04.727645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3611 01:11:04.728504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3613 01:11:04.780060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3614 01:11:04.780898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3616 01:11:04.825592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3617 01:11:04.826408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3619 01:11:04.879122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3620 01:11:04.879928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3622 01:11:04.935823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3623 01:11:04.936667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3625 01:11:04.987938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3626 01:11:04.988934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3628 01:11:05.033578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3629 01:11:05.034489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3631 01:11:05.090220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3632 01:11:05.091206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3634 01:11:05.140037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3635 01:11:05.140838 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3637 01:11:05.184796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3638 01:11:05.185555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3640 01:11:05.231411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3641 01:11:05.232184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3643 01:11:05.284264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3644 01:11:05.284998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3646 01:11:05.333582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3647 01:11:05.334332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3649 01:11:05.383335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3650 01:11:05.384068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3652 01:11:05.431495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3653 01:11:05.432354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3655 01:11:05.484089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3656 01:11:05.484894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3658 01:11:05.534766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3659 01:11:05.535599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3661 01:11:05.588040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3662 01:11:05.588825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3664 01:11:05.634039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3665 01:11:05.634873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3667 01:11:05.686306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3668 01:11:05.687027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3670 01:11:05.732860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3671 01:11:05.733634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3673 01:11:05.787405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3674 01:11:05.788130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3676 01:11:05.834243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3677 01:11:05.835106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3679 01:11:05.887201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3680 01:11:05.888035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3682 01:11:05.932762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3683 01:11:05.933526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3685 01:11:05.982615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3686 01:11:05.983332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3688 01:11:06.029046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3689 01:11:06.029855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3691 01:11:06.078609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3692 01:11:06.079354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3694 01:11:06.135178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3695 01:11:06.136018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3697 01:11:06.184388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3698 01:11:06.185127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3700 01:11:06.240086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3701 01:11:06.240878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3703 01:11:06.285822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3704 01:11:06.286570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3706 01:11:06.339435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3707 01:11:06.340208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3709 01:11:06.384376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3710 01:11:06.385218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3712 01:11:06.440551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3713 01:11:06.441358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3715 01:11:06.488127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3716 01:11:06.488895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3718 01:11:06.541268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3719 01:11:06.542111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3721 01:11:06.584256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3722 01:11:06.585045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3724 01:11:06.638686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3725 01:11:06.639457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3727 01:11:06.691136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3728 01:11:06.691850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3730 01:11:06.747725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3731 01:11:06.748526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3733 01:11:06.808575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3734 01:11:06.809294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3736 01:11:06.854046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3737 01:11:06.854814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3739 01:11:06.920502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3740 01:11:06.921234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3742 01:11:06.982457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3743 01:11:06.983234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3745 01:11:07.027721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3746 01:11:07.028580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3748 01:11:07.081699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3749 01:11:07.082441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3751 01:11:07.127126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3752 01:11:07.127899 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3754 01:11:07.173941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3755 01:11:07.174674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3757 01:11:07.227975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3758 01:11:07.228782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3760 01:11:07.284633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3761 01:11:07.285344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3763 01:11:07.333432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3764 01:11:07.334207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3766 01:11:07.391291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3767 01:11:07.392157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3769 01:11:07.443059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3770 01:11:07.443914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3772 01:11:07.490126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3773 01:11:07.490933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3775 01:11:07.541315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3776 01:11:07.542069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3778 01:11:07.585760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3779 01:11:07.586518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3781 01:11:07.629749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3782 01:11:07.630462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3784 01:11:07.676098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3785 01:11:07.676837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3787 01:11:07.733538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3788 01:11:07.734268 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3790 01:11:07.784523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3791 01:11:07.785255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3793 01:11:07.828171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3794 01:11:07.828894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3796 01:11:07.875887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3797 01:11:07.876801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3799 01:11:07.928945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3800 01:11:07.929795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3802 01:11:07.984013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3803 01:11:07.984880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3805 01:11:08.044168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3806 01:11:08.045059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3808 01:11:08.105394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3809 01:11:08.106264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3811 01:11:08.161907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3812 01:11:08.162755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3814 01:11:08.212785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3815 01:11:08.213640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3817 01:11:08.258718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3818 01:11:08.259556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3820 01:11:08.310075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3821 01:11:08.310921 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3823 01:11:08.365881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3824 01:11:08.366737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3826 01:11:08.418450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3827 01:11:08.419318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3829 01:11:08.478401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3830 01:11:08.479241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3832 01:11:08.523482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3833 01:11:08.524386 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3835 01:11:08.568254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3836 01:11:08.569105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3838 01:11:08.613818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3839 01:11:08.614655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3841 01:11:08.669946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3842 01:11:08.670777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3844 01:11:08.721201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3845 01:11:08.722027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3847 01:11:08.774246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3848 01:11:08.775056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3850 01:11:08.829863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3851 01:11:08.830671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3853 01:11:08.875693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3854 01:11:08.876556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3856 01:11:08.928550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3857 01:11:08.929361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3859 01:11:08.973523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3860 01:11:08.974339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3862 01:11:09.026962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3863 01:11:09.027784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3865 01:11:09.069681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3866 01:11:09.070565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3868 01:11:09.123353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3869 01:11:09.124168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3871 01:11:09.169521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3872 01:11:09.170333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3874 01:11:09.216348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3875 01:11:09.217159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3877 01:11:09.262031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3878 01:11:09.262842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3880 01:11:09.307156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3881 01:11:09.307962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3883 01:11:09.361378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3884 01:11:09.362206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3886 01:11:09.416250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3887 01:11:09.417096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3889 01:11:09.465823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3890 01:11:09.466635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3892 01:11:09.523318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3893 01:11:09.524157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3895 01:11:09.573957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3896 01:11:09.574801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3898 01:11:09.628189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3899 01:11:09.629007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3901 01:11:09.672418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3902 01:11:09.673237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3904 01:11:09.731130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3905 01:11:09.731935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3907 01:11:09.781182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3908 01:11:09.781987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3910 01:11:09.834007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3911 01:11:09.834811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3913 01:11:09.880409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3914 01:11:09.881218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3916 01:11:09.930167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3917 01:11:09.930969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3919 01:11:09.981898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3920 01:11:09.982710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3922 01:11:10.025985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3923 01:11:10.026819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3925 01:11:10.081111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3926 01:11:10.081950 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3928 01:11:10.138903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3929 01:11:10.139743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3931 01:11:10.191053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3932 01:11:10.191940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3934 01:11:10.235030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3935 01:11:10.235850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3937 01:11:10.293997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3938 01:11:10.294814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3940 01:11:10.343139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3941 01:11:10.343937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3943 01:11:10.393703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3944 01:11:10.394518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3946 01:11:10.446722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3947 01:11:10.447578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3949 01:11:10.491325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3950 01:11:10.492128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3952 01:11:10.542711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3953 01:11:10.543547 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3955 01:11:10.589592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3956 01:11:10.590426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3958 01:11:10.634676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3959 01:11:10.635500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3961 01:11:10.684289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3962 01:11:10.685106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3964 01:11:10.730255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3965 01:11:10.731061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3967 01:11:10.782001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3968 01:11:10.782834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3970 01:11:10.915345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3971 01:11:10.916214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3973 01:11:10.973708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3974 01:11:10.974493 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3976 01:11:11.021647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3977 01:11:11.022428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3979 01:11:11.072412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3980 01:11:11.073222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3982 01:11:11.118127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3983 01:11:11.118907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3985 01:11:11.163221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3986 01:11:11.164023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3988 01:11:11.215003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3989 01:11:11.215776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3991 01:11:11.266741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3992 01:11:11.267521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3994 01:11:11.313347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3995 01:11:11.314131 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3997 01:11:11.366011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3998 01:11:11.366797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
4000 01:11:11.419971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
4001 01:11:11.420827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
4003 01:11:11.465104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
4004 01:11:11.465898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
4006 01:11:11.509115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
4007 01:11:11.509925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
4009 01:11:11.554532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
4010 01:11:11.555362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
4012 01:11:11.609061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
4013 01:11:11.609879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
4015 01:11:11.654892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
4016 01:11:11.655671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
4018 01:11:11.700913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
4019 01:11:11.701686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
4021 01:11:11.749083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
4022 01:11:11.749854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
4024 01:11:11.808893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
4025 01:11:11.809666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
4027 01:11:11.861993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
4028 01:11:11.862763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
4030 01:11:11.907354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
4031 01:11:11.908126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
4033 01:11:11.961478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
4034 01:11:11.962248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
4036 01:11:12.006683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
4037 01:11:12.007459 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
4039 01:11:12.051888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
4040 01:11:12.052742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
4042 01:11:12.112566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
4043 01:11:12.113408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
4045 01:11:12.166821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
4046 01:11:12.167628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
4048 01:11:12.220563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
4049 01:11:12.221350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
4051 01:11:12.268572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
4052 01:11:12.269365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
4054 01:11:12.326063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
4055 01:11:12.326906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
4057 01:11:12.371186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
4058 01:11:12.372060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
4060 01:11:12.422471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
4061 01:11:12.423352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
4063 01:11:12.467781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
4064 01:11:12.468682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
4066 01:11:12.524372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
4067 01:11:12.525224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
4069 01:11:12.570470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
4070 01:11:12.571320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
4072 01:11:12.617281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
4073 01:11:12.618101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
4075 01:11:12.662325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
4076 01:11:12.663154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
4078 01:11:12.714356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
4079 01:11:12.715171 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
4081 01:11:12.762126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
4082 01:11:12.762977 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
4084 01:11:12.808517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
4085 01:11:12.809353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
4087 01:11:12.853268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
4088 01:11:12.854082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
4090 01:11:12.906903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
4091 01:11:12.907757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
4093 01:11:12.958197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
4094 01:11:12.959055 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
4096 01:11:13.011418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
4097 01:11:13.012301 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
4099 01:11:13.056593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
4100 01:11:13.057426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
4102 01:11:13.104097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
4103 01:11:13.104951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
4105 01:11:13.151500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
4106 01:11:13.152382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
4108 01:11:13.206896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
4109 01:11:13.207758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
4111 01:11:13.250668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
4112 01:11:13.251504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
4114 01:11:13.309287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
4115 01:11:13.310124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
4117 01:11:13.361711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
4118 01:11:13.362517 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
4120 01:11:13.409729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
4121 01:11:13.410554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
4123 01:11:13.473365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
4124 01:11:13.474180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
4126 01:11:13.526884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
4127 01:11:13.527706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
4129 01:11:13.572391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
4130 01:11:13.573216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
4132 01:11:13.629599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
4133 01:11:13.630406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
4135 01:11:13.682640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
4136 01:11:13.683441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
4138 01:11:13.738172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
4139 01:11:13.738964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
4141 01:11:13.787756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
4142 01:11:13.788590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
4144 01:11:13.833132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
4145 01:11:13.833916 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
4147 01:11:13.879519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
4148 01:11:13.880352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
4150 01:11:13.931285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
4151 01:11:13.932106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
4153 01:11:13.980760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
4154 01:11:13.981595 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4156 01:11:14.034913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4157 01:11:14.035750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4159 01:11:14.085938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4160 01:11:14.086760 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4162 01:11:14.137008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4163 01:11:14.137883 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4165 01:11:14.188612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4166 01:11:14.189501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4168 01:11:14.241043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4169 01:11:14.241927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4171 01:11:14.296834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4172 01:11:14.297716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4174 01:11:14.354793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4175 01:11:14.355674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4177 01:11:14.405188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4178 01:11:14.406303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4180 01:11:14.452537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4181 01:11:14.453498 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4183 01:11:14.508698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4184 01:11:14.509706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4186 01:11:14.555839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4187 01:11:14.556865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4189 01:11:14.610710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4190 01:11:14.611635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4192 01:11:14.658100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4193 01:11:14.658995 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4195 01:11:14.726151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4196 01:11:14.727051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4198 01:11:14.775514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4199 01:11:14.776439 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4201 01:11:14.820284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4202 01:11:14.821176 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4204 01:11:14.874641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4205 01:11:14.875552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4207 01:11:14.925540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4208 01:11:14.926440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4210 01:11:14.985649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4211 01:11:14.986533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4213 01:11:15.030483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4214 01:11:15.031358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4216 01:11:15.079603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4217 01:11:15.080523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4219 01:11:15.126818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4220 01:11:15.127709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4222 01:11:15.175610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4223 01:11:15.176552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4225 01:11:15.222041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4226 01:11:15.222956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4228 01:11:15.268449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4229 01:11:15.269297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4231 01:11:15.317428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4232 01:11:15.318236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4234 01:11:15.377027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4235 01:11:15.377816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4237 01:11:15.422586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4238 01:11:15.423388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4240 01:11:15.469729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4241 01:11:15.470522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4243 01:11:15.515673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4244 01:11:15.516580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4246 01:11:15.569284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4247 01:11:15.570183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4249 01:11:15.615034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4250 01:11:15.615862 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4252 01:11:15.668413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4253 01:11:15.669264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4255 01:11:15.716089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4256 01:11:15.716909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4258 01:11:15.761645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4259 01:11:15.762463 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4261 01:11:15.811420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4262 01:11:15.812385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4264 01:11:15.863591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4265 01:11:15.864539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4267 01:11:15.924236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4268 01:11:15.925126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4270 01:11:15.973994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4271 01:11:15.974822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4273 01:11:16.026175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4274 01:11:16.027002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4276 01:11:16.075720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4277 01:11:16.076593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4279 01:11:16.130146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4280 01:11:16.130999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4282 01:11:16.183129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4283 01:11:16.184020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4285 01:11:16.240351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4286 01:11:16.241245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4288 01:11:16.297455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4289 01:11:16.298323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4291 01:11:16.350873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4292 01:11:16.351710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4294 01:11:16.404733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4295 01:11:16.405569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4297 01:11:16.460055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4298 01:11:16.460915 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4300 01:11:16.501578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4301 01:11:16.502422 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4303 01:11:16.558067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4304 01:11:16.558931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4306 01:11:16.617125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4307 01:11:16.617978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4309 01:11:16.669011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4310 01:11:16.669833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4312 01:11:16.721041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4313 01:11:16.721912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4315 01:11:16.779742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4316 01:11:16.780649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4318 01:11:16.835101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4319 01:11:16.835965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4321 01:11:16.886870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4322 01:11:16.887738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4324 01:11:16.938456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4325 01:11:16.939291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4327 01:11:16.985443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4328 01:11:16.986268 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4330 01:11:17.033069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4331 01:11:17.033909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4333 01:11:17.091889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4334 01:11:17.092766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4336 01:11:17.143525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4337 01:11:17.144386 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4339 01:11:17.196450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4340 01:11:17.197323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4342 01:11:17.245008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4343 01:11:17.245848 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4345 01:11:17.293615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4346 01:11:17.294438 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4348 01:11:17.338974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4349 01:11:17.339800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4351 01:11:17.399016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4352 01:11:17.399840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4354 01:11:17.449752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4355 01:11:17.450571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4357 01:11:17.502306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4358 01:11:17.503180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4360 01:11:17.550488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4362 01:11:17.553415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4363 01:11:17.610614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4364 01:11:17.611459 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4366 01:11:17.659416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4367 01:11:17.660318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4369 01:11:17.716344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4370 01:11:17.717185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4372 01:11:17.765160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4373 01:11:17.766026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4375 01:11:17.810893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4376 01:11:17.811744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4378 01:11:17.856079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4379 01:11:17.856925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4381 01:11:17.912845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4382 01:11:17.913697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4384 01:11:17.966352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4385 01:11:17.967213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4387 01:11:18.012256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4388 01:11:18.013115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4390 01:11:18.064638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4391 01:11:18.065501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4393 01:11:18.113957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4394 01:11:18.114817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4396 01:11:18.161197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4397 01:11:18.162048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4399 01:11:18.214441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4400 01:11:18.215327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4402 01:11:18.264520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4403 01:11:18.265385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4405 01:11:18.317635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4406 01:11:18.318490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4408 01:11:18.368218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4409 01:11:18.369079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4411 01:11:18.425234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4412 01:11:18.426098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4414 01:11:18.483450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4415 01:11:18.484342 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4417 01:11:18.532918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4418 01:11:18.533782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4420 01:11:18.578918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4421 01:11:18.579769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4423 01:11:18.631536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4424 01:11:18.632510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4426 01:11:18.683025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4427 01:11:18.683969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4429 01:11:18.743341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4430 01:11:18.744481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4432 01:11:18.811350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4433 01:11:18.812232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4435 01:11:18.868878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4436 01:11:18.869743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4438 01:11:18.930904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4439 01:11:18.931791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4441 01:11:18.985588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4442 01:11:18.986502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4444 01:11:19.043402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4445 01:11:19.044344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4447 01:11:19.099593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4448 01:11:19.100570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4450 01:11:19.149702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4451 01:11:19.150604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4453 01:11:19.202619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4454 01:11:19.203536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4456 01:11:19.250455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4457 01:11:19.251372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4459 01:11:19.306891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4460 01:11:19.307758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4462 01:11:19.360340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4463 01:11:19.361263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4465 01:11:19.412580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4466 01:11:19.413500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4468 01:11:19.465584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4469 01:11:19.466481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4471 01:11:19.512353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4472 01:11:19.513266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4474 01:11:19.570348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4475 01:11:19.571263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4477 01:11:19.624794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4478 01:11:19.625678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4480 01:11:19.678883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4481 01:11:19.679772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4483 01:11:19.735974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4484 01:11:19.736885 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4486 01:11:19.790992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4487 01:11:19.791684 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4489 01:11:19.847451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4490 01:11:19.848170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4492 01:11:19.909199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4493 01:11:19.909914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4495 01:11:19.963850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4496 01:11:19.964536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4498 01:11:20.013995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4499 01:11:20.014659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4501 01:11:20.059697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4502 01:11:20.060363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4504 01:11:20.111862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4505 01:11:20.112540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4507 01:11:20.157439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4508 01:11:20.158085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4510 01:11:20.212223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4511 01:11:20.212851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4513 01:11:20.268491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4514 01:11:20.269093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4516 01:11:20.316829 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4518 01:11:20.322122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4519 01:11:20.322415 + set +x
4520 01:11:20.328022 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 972876_1.6.2.4.5>
4521 01:11:20.328308 <LAVA_TEST_RUNNER EXIT>
4522 01:11:20.328750 Received signal: <ENDRUN> 1_kselftest-alsa 972876_1.6.2.4.5
4523 01:11:20.329018 Ending use of test pattern.
4524 01:11:20.329250 Ending test lava.1_kselftest-alsa (972876_1.6.2.4.5), duration 41.12
4526 01:11:20.330098 ok: lava_test_shell seems to have completed
4527 01:11:20.341870 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4528 01:11:20.342812 end: 3.1 lava-test-shell (duration 00:00:42) [common]
4529 01:11:20.343150 end: 3 lava-test-retry (duration 00:00:42) [common]
4530 01:11:20.343468 start: 4 finalize (timeout 00:06:05) [common]
4531 01:11:20.343794 start: 4.1 power-off (timeout 00:00:30) [common]
4532 01:11:20.344348 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4533 01:11:20.376608 >> OK - accepted request
4534 01:11:20.378436 Returned 0 in 0 seconds
4535 01:11:20.479345 end: 4.1 power-off (duration 00:00:00) [common]
4537 01:11:20.480946 start: 4.2 read-feedback (timeout 00:06:05) [common]
4538 01:11:20.482420 Listened to connection for namespace 'common' for up to 1s
4539 01:11:21.482902 Finalising connection for namespace 'common'
4540 01:11:21.483429 Disconnecting from shell: Finalise
4541 01:11:21.483775 / #
4542 01:11:21.584544 end: 4.2 read-feedback (duration 00:00:01) [common]
4543 01:11:21.585082 end: 4 finalize (duration 00:00:01) [common]
4544 01:11:21.585537 Cleaning after the job
4545 01:11:21.585906 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972876/tftp-deploy-rkkyrml0/ramdisk
4546 01:11:21.594352 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972876/tftp-deploy-rkkyrml0/kernel
4547 01:11:21.621802 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972876/tftp-deploy-rkkyrml0/dtb
4548 01:11:21.622778 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972876/tftp-deploy-rkkyrml0/nfsrootfs
4549 01:11:21.804851 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/972876/tftp-deploy-rkkyrml0/modules
4550 01:11:21.826281 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/972876
4551 01:11:26.082267 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/972876
4552 01:11:26.082900 Job finished correctly