Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 16
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 08:43:36.803775 lava-dispatcher, installed at version: 2024.01
2 08:43:36.804113 start: 0 validate
3 08:43:36.804279 Start time: 2024-08-30 08:43:36.804272+00:00 (UTC)
4 08:43:36.804460 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 08:43:37.088427 Validating that http://storage.kernelci.org/next/master/next-20240830/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
6 08:43:37.231219 Validating that http://storage.kernelci.org/next/master/next-20240830/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
7 08:43:37.374212 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 08:43:37.516484 Validating that http://storage.kernelci.org/next/master/next-20240830/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
9 08:43:37.664116 validate duration: 0.86
11 08:43:37.664790 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 08:43:37.665022 start: 1.1 download-retry (timeout 00:10:00) [common]
13 08:43:37.665234 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 08:43:37.665694 Not decompressing ramdisk as can be used compressed.
15 08:43:37.665985 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 08:43:37.666158 saving as /var/lib/lava/dispatcher/tmp/676553/tftp-deploy-sxbex86h/ramdisk/initrd.cpio.gz
17 08:43:37.666313 total size: 4775763 (4 MB)
18 08:43:37.947905 progress 0 % (0 MB)
19 08:43:38.366137 progress 5 % (0 MB)
20 08:43:38.505367 progress 10 % (0 MB)
21 08:43:38.508955 progress 15 % (0 MB)
22 08:43:38.645012 progress 20 % (0 MB)
23 08:43:38.648334 progress 25 % (1 MB)
24 08:43:38.651501 progress 30 % (1 MB)
25 08:43:38.687654 progress 35 % (1 MB)
26 08:43:38.784309 progress 40 % (1 MB)
27 08:43:38.787882 progress 45 % (2 MB)
28 08:43:38.791349 progress 50 % (2 MB)
29 08:43:38.795214 progress 55 % (2 MB)
30 08:43:38.798583 progress 60 % (2 MB)
31 08:43:38.801649 progress 65 % (2 MB)
32 08:43:38.827985 progress 70 % (3 MB)
33 08:43:38.831369 progress 75 % (3 MB)
34 08:43:38.923635 progress 80 % (3 MB)
35 08:43:38.927199 progress 85 % (3 MB)
36 08:43:38.931055 progress 90 % (4 MB)
37 08:43:38.934471 progress 95 % (4 MB)
38 08:43:38.937607 progress 100 % (4 MB)
39 08:43:38.938137 4 MB downloaded in 1.27 s (3.58 MB/s)
40 08:43:38.938525 end: 1.1.1 http-download (duration 00:00:01) [common]
42 08:43:38.939114 end: 1.1 download-retry (duration 00:00:01) [common]
43 08:43:38.939314 start: 1.2 download-retry (timeout 00:09:59) [common]
44 08:43:38.939502 start: 1.2.1 http-download (timeout 00:09:59) [common]
45 08:43:38.939901 downloading http://storage.kernelci.org/next/master/next-20240830/arm/multi_v7_defconfig/gcc-12/kernel/zImage
46 08:43:38.940064 saving as /var/lib/lava/dispatcher/tmp/676553/tftp-deploy-sxbex86h/kernel/zImage
47 08:43:38.940210 total size: 11420160 (10 MB)
48 08:43:38.940379 No compression specified
49 08:43:39.082083 progress 0 % (0 MB)
50 08:43:39.090193 progress 5 % (0 MB)
51 08:43:39.098084 progress 10 % (1 MB)
52 08:43:39.106531 progress 15 % (1 MB)
53 08:43:39.114419 progress 20 % (2 MB)
54 08:43:39.122403 progress 25 % (2 MB)
55 08:43:39.225935 progress 30 % (3 MB)
56 08:43:39.233863 progress 35 % (3 MB)
57 08:43:39.241991 progress 40 % (4 MB)
58 08:43:39.249788 progress 45 % (4 MB)
59 08:43:39.262288 progress 50 % (5 MB)
60 08:43:39.365650 progress 55 % (6 MB)
61 08:43:39.377724 progress 60 % (6 MB)
62 08:43:39.385645 progress 65 % (7 MB)
63 08:43:39.393508 progress 70 % (7 MB)
64 08:43:39.401707 progress 75 % (8 MB)
65 08:43:39.502390 progress 80 % (8 MB)
66 08:43:39.515729 progress 85 % (9 MB)
67 08:43:39.523691 progress 90 % (9 MB)
68 08:43:39.531980 progress 95 % (10 MB)
69 08:43:39.650826 progress 100 % (10 MB)
70 08:43:39.651399 10 MB downloaded in 0.71 s (15.31 MB/s)
71 08:43:39.651755 end: 1.2.1 http-download (duration 00:00:01) [common]
73 08:43:39.652313 end: 1.2 download-retry (duration 00:00:01) [common]
74 08:43:39.652520 start: 1.3 download-retry (timeout 00:09:58) [common]
75 08:43:39.652711 start: 1.3.1 http-download (timeout 00:09:58) [common]
76 08:43:39.653085 downloading http://storage.kernelci.org/next/master/next-20240830/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
77 08:43:39.653249 saving as /var/lib/lava/dispatcher/tmp/676553/tftp-deploy-sxbex86h/dtb/am335x-boneblack.dtb
78 08:43:39.653394 total size: 70568 (0 MB)
79 08:43:39.653535 No compression specified
80 08:43:39.795806 progress 46 % (0 MB)
81 08:43:39.796530 progress 92 % (0 MB)
82 08:43:39.797133 progress 100 % (0 MB)
83 08:43:39.797407 0 MB downloaded in 0.14 s (0.47 MB/s)
84 08:43:39.797769 end: 1.3.1 http-download (duration 00:00:00) [common]
86 08:43:39.798323 end: 1.3 download-retry (duration 00:00:00) [common]
87 08:43:39.798518 start: 1.4 download-retry (timeout 00:09:58) [common]
88 08:43:39.798707 start: 1.4.1 http-download (timeout 00:09:58) [common]
89 08:43:39.799075 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 08:43:39.799235 saving as /var/lib/lava/dispatcher/tmp/676553/tftp-deploy-sxbex86h/nfsrootfs/full.rootfs.tar
91 08:43:39.799385 total size: 117747780 (112 MB)
92 08:43:39.799534 Using unxz to decompress xz
93 08:43:39.942074 progress 0 % (0 MB)
94 08:43:40.303941 progress 5 % (5 MB)
95 08:43:40.675166 progress 10 % (11 MB)
96 08:43:41.042315 progress 15 % (16 MB)
97 08:43:41.414746 progress 20 % (22 MB)
98 08:43:41.794112 progress 25 % (28 MB)
99 08:43:42.186817 progress 30 % (33 MB)
100 08:43:42.562555 progress 35 % (39 MB)
101 08:43:42.881384 progress 40 % (44 MB)
102 08:43:43.178530 progress 45 % (50 MB)
103 08:43:43.562344 progress 50 % (56 MB)
104 08:43:43.948795 progress 55 % (61 MB)
105 08:43:44.315891 progress 60 % (67 MB)
106 08:43:44.678199 progress 65 % (73 MB)
107 08:43:45.049597 progress 70 % (78 MB)
108 08:43:45.423141 progress 75 % (84 MB)
109 08:43:45.782515 progress 80 % (89 MB)
110 08:43:46.141840 progress 85 % (95 MB)
111 08:43:46.507751 progress 90 % (101 MB)
112 08:43:46.858777 progress 95 % (106 MB)
113 08:43:47.232361 progress 100 % (112 MB)
114 08:43:47.238452 112 MB downloaded in 7.44 s (15.10 MB/s)
115 08:43:47.238848 end: 1.4.1 http-download (duration 00:00:07) [common]
117 08:43:47.239444 end: 1.4 download-retry (duration 00:00:07) [common]
118 08:43:47.239614 start: 1.5 download-retry (timeout 00:09:50) [common]
119 08:43:47.239764 start: 1.5.1 http-download (timeout 00:09:50) [common]
120 08:43:47.240074 downloading http://storage.kernelci.org/next/master/next-20240830/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
121 08:43:47.240204 saving as /var/lib/lava/dispatcher/tmp/676553/tftp-deploy-sxbex86h/modules/modules.tar
122 08:43:47.240313 total size: 6641408 (6 MB)
123 08:43:47.240424 Using unxz to decompress xz
124 08:43:47.381703 progress 0 % (0 MB)
125 08:43:47.400283 progress 5 % (0 MB)
126 08:43:47.420877 progress 10 % (0 MB)
127 08:43:47.442219 progress 15 % (0 MB)
128 08:43:47.463316 progress 20 % (1 MB)
129 08:43:47.483977 progress 25 % (1 MB)
130 08:43:47.505882 progress 30 % (1 MB)
131 08:43:47.526877 progress 35 % (2 MB)
132 08:43:47.550102 progress 40 % (2 MB)
133 08:43:47.571564 progress 45 % (2 MB)
134 08:43:47.592631 progress 50 % (3 MB)
135 08:43:47.613548 progress 55 % (3 MB)
136 08:43:47.635471 progress 60 % (3 MB)
137 08:43:47.656445 progress 65 % (4 MB)
138 08:43:47.677137 progress 70 % (4 MB)
139 08:43:47.701578 progress 75 % (4 MB)
140 08:43:47.723425 progress 80 % (5 MB)
141 08:43:47.745683 progress 85 % (5 MB)
142 08:43:47.766126 progress 90 % (5 MB)
143 08:43:47.787883 progress 95 % (6 MB)
144 08:43:47.825326 progress 100 % (6 MB)
145 08:43:47.829017 6 MB downloaded in 0.59 s (10.76 MB/s)
146 08:43:47.829412 end: 1.5.1 http-download (duration 00:00:01) [common]
148 08:43:47.829912 end: 1.5 download-retry (duration 00:00:01) [common]
149 08:43:47.830069 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
150 08:43:47.830220 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
151 08:43:53.043578 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/676553/extract-nfsrootfs-k84pdatq
152 08:43:53.043898 end: 1.6.1 extract-nfsrootfs (duration 00:00:05) [common]
153 08:43:53.043989 start: 1.6.2 lava-overlay (timeout 00:09:45) [common]
154 08:43:53.044220 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1
155 08:43:53.044366 makedir: /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin
156 08:43:53.044476 makedir: /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/tests
157 08:43:53.044576 makedir: /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/results
158 08:43:53.044676 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-add-keys
159 08:43:53.044829 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-add-sources
160 08:43:53.044962 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-background-process-start
161 08:43:53.045094 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-background-process-stop
162 08:43:53.045239 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-common-functions
163 08:43:53.045373 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-echo-ipv4
164 08:43:53.045504 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-install-packages
165 08:43:53.045653 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-installed-packages
166 08:43:53.045792 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-os-build
167 08:43:53.045921 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-probe-channel
168 08:43:53.046057 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-probe-ip
169 08:43:53.046193 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-target-ip
170 08:43:53.046322 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-target-mac
171 08:43:53.046456 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-target-storage
172 08:43:53.046591 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-test-case
173 08:43:53.046720 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-test-event
174 08:43:53.046848 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-test-feedback
175 08:43:53.046977 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-test-raise
176 08:43:53.047111 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-test-reference
177 08:43:53.047242 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-test-runner
178 08:43:53.047371 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-test-set
179 08:43:53.047501 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-test-shell
180 08:43:53.047636 Updating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-add-keys (debian)
181 08:43:53.047803 Updating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-add-sources (debian)
182 08:43:53.047955 Updating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-install-packages (debian)
183 08:43:53.048107 Updating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-installed-packages (debian)
184 08:43:53.048253 Updating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/bin/lava-os-build (debian)
185 08:43:53.048380 Creating /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/environment
186 08:43:53.048481 LAVA metadata
187 08:43:53.048553 - LAVA_JOB_ID=676553
188 08:43:53.048606 - LAVA_DISPATCHER_IP=192.168.56.193
189 08:43:53.048723 start: 1.6.2.1 ssh-authorize (timeout 00:09:45) [common]
190 08:43:53.049028 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 08:43:53.049111 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:45) [common]
192 08:43:53.049171 skipped lava-vland-overlay
193 08:43:53.049232 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 08:43:53.049297 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:45) [common]
195 08:43:53.049349 skipped lava-multinode-overlay
196 08:43:53.049408 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 08:43:53.049473 start: 1.6.2.4 test-definition (timeout 00:09:45) [common]
198 08:43:53.049535 Loading test definitions
199 08:43:53.050199 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:45) [common]
200 08:43:53.050264 Using /lava-676553 at stage 0
201 08:43:53.050673 uuid=676553_1.6.2.4.1 testdef=None
202 08:43:53.050757 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 08:43:53.050825 start: 1.6.2.4.2 test-overlay (timeout 00:09:45) [common]
204 08:43:53.051290 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 08:43:53.051498 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:45) [common]
207 08:43:53.052072 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 08:43:53.052287 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:45) [common]
210 08:43:53.058880 runner path: /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/0/tests/0_timesync-off test_uuid 676553_1.6.2.4.1
211 08:43:53.059087 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 08:43:53.059291 start: 1.6.2.4.5 git-repo-action (timeout 00:09:45) [common]
214 08:43:53.059350 Using /lava-676553 at stage 0
215 08:43:53.059443 Fetching tests from https://github.com/kernelci/test-definitions.git
216 08:43:53.059524 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/0/tests/1_kselftest-dt'
217 08:43:55.054961 Running '/usr/bin/git checkout kernelci.org
218 08:43:55.113796 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 08:43:55.114526 uuid=676553_1.6.2.4.5 testdef=None
220 08:43:55.114738 end: 1.6.2.4.5 git-repo-action (duration 00:00:02) [common]
222 08:43:55.115146 start: 1.6.2.4.6 test-overlay (timeout 00:09:43) [common]
223 08:43:55.116315 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 08:43:55.116529 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:43) [common]
226 08:43:55.117545 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 08:43:55.117795 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:43) [common]
229 08:43:55.118767 runner path: /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/0/tests/1_kselftest-dt test_uuid 676553_1.6.2.4.5
230 08:43:55.118856 BOARD='beaglebone-black'
231 08:43:55.118907 BRANCH='next'
232 08:43:55.118954 SKIPFILE='/dev/null'
233 08:43:55.119006 SKIP_INSTALL='True'
234 08:43:55.119052 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20240830/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
235 08:43:55.119100 TST_CASENAME=''
236 08:43:55.119148 TST_CMDFILES='dt'
237 08:43:55.119318 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 08:43:55.119508 Creating lava-test-runner.conf files
240 08:43:55.119560 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/676553/lava-overlay-a6iaime1/lava-676553/0 for stage 0
241 08:43:55.119660 - 0_timesync-off
242 08:43:55.119718 - 1_kselftest-dt
243 08:43:55.119810 end: 1.6.2.4 test-definition (duration 00:00:02) [common]
244 08:43:55.119885 start: 1.6.2.5 compress-overlay (timeout 00:09:43) [common]
245 08:44:03.238107 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 08:44:03.238268 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
247 08:44:03.238342 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 08:44:03.238419 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
249 08:44:03.238489 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
250 08:44:03.368122 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 08:44:03.368418 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
252 08:44:03.368568 extracting modules file /var/lib/lava/dispatcher/tmp/676553/tftp-deploy-sxbex86h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/676553/extract-nfsrootfs-k84pdatq
253 08:44:03.656040 extracting modules file /var/lib/lava/dispatcher/tmp/676553/tftp-deploy-sxbex86h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/676553/extract-overlay-ramdisk-g19kbrlm/ramdisk
254 08:44:03.955361 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 08:44:03.955563 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
256 08:44:03.955652 [common] Applying overlay to NFS
257 08:44:03.955707 [common] Applying overlay /var/lib/lava/dispatcher/tmp/676553/compress-overlay-ejfp92jc/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/676553/extract-nfsrootfs-k84pdatq
258 08:44:04.957380 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 08:44:04.957563 start: 1.6.6 prepare-kernel (timeout 00:09:33) [common]
260 08:44:04.957663 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:33) [common]
261 08:44:04.957745 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 08:44:04.957810 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 08:44:04.957876 start: 1.6.7 configure-preseed-file (timeout 00:09:33) [common]
264 08:44:04.957941 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 08:44:04.958006 start: 1.6.8 compress-ramdisk (timeout 00:09:33) [common]
266 08:44:04.958064 Building ramdisk /var/lib/lava/dispatcher/tmp/676553/extract-overlay-ramdisk-g19kbrlm/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/676553/extract-overlay-ramdisk-g19kbrlm/ramdisk
267 08:44:05.252474 >> 75138 blocks
268 08:44:07.025999 Adding RAMdisk u-boot header.
269 08:44:07.026226 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/676553/extract-overlay-ramdisk-g19kbrlm/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/676553/extract-overlay-ramdisk-g19kbrlm/ramdisk.cpio.gz.uboot
270 08:44:07.125443 output: Image Name:
271 08:44:07.125712 output: Created: Fri Aug 30 08:44:07 2024
272 08:44:07.125842 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 08:44:07.125954 output: Data Size: 14839645 Bytes = 14491.84 KiB = 14.15 MiB
274 08:44:07.126093 output: Load Address: 00000000
275 08:44:07.126214 output: Entry Point: 00000000
276 08:44:07.126319 output:
277 08:44:07.126591 rename /var/lib/lava/dispatcher/tmp/676553/extract-overlay-ramdisk-g19kbrlm/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/676553/tftp-deploy-sxbex86h/ramdisk/ramdisk.cpio.gz.uboot
278 08:44:07.126815 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
279 08:44:07.126975 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
280 08:44:07.127125 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:31) [common]
281 08:44:07.127271 No LXC device requested
282 08:44:07.127407 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 08:44:07.127548 start: 1.8 deploy-device-env (timeout 00:09:31) [common]
284 08:44:07.127684 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 08:44:07.127798 Checking files for TFTP limit of 4294967296 bytes.
286 08:44:07.128699 end: 1 tftp-deploy (duration 00:00:29) [common]
287 08:44:07.128886 start: 2 uboot-action (timeout 00:05:00) [common]
288 08:44:07.129036 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 08:44:07.129174 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 08:44:07.129316 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 08:44:07.129557 substitutions:
292 08:44:07.129695 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 08:44:07.129804 - {DTB_ADDR}: 0x88000000
294 08:44:07.129909 - {DTB}: 676553/tftp-deploy-sxbex86h/dtb/am335x-boneblack.dtb
295 08:44:07.130013 - {INITRD}: 676553/tftp-deploy-sxbex86h/ramdisk/ramdisk.cpio.gz.uboot
296 08:44:07.130119 - {KERNEL_ADDR}: 0x82000000
297 08:44:07.130224 - {KERNEL}: 676553/tftp-deploy-sxbex86h/kernel/zImage
298 08:44:07.130329 - {LAVA_MAC}: None
299 08:44:07.130456 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/676553/extract-nfsrootfs-k84pdatq
300 08:44:07.130565 - {NFS_SERVER_IP}: 192.168.56.193
301 08:44:07.130669 - {PRESEED_CONFIG}: None
302 08:44:07.130773 - {PRESEED_LOCAL}: None
303 08:44:07.130878 - {RAMDISK_ADDR}: 0x83000000
304 08:44:07.130981 - {RAMDISK}: 676553/tftp-deploy-sxbex86h/ramdisk/ramdisk.cpio.gz.uboot
305 08:44:07.131086 - {ROOT_PART}: None
306 08:44:07.131190 - {ROOT}: None
307 08:44:07.131293 - {SERVER_IP}: 192.168.56.193
308 08:44:07.131396 - {TEE_ADDR}: 0x83000000
309 08:44:07.131500 - {TEE}: None
310 08:44:07.131604 Parsed boot commands:
311 08:44:07.131707 - setenv autoload no
312 08:44:07.131811 - setenv initrd_high 0xffffffff
313 08:44:07.131915 - setenv fdt_high 0xffffffff
314 08:44:07.132017 - dhcp
315 08:44:07.132119 - setenv serverip 192.168.56.193
316 08:44:07.132220 - tftp 0x82000000 676553/tftp-deploy-sxbex86h/kernel/zImage
317 08:44:07.132323 - tftp 0x83000000 676553/tftp-deploy-sxbex86h/ramdisk/ramdisk.cpio.gz.uboot
318 08:44:07.132428 - setenv initrd_size ${filesize}
319 08:44:07.132530 - tftp 0x88000000 676553/tftp-deploy-sxbex86h/dtb/am335x-boneblack.dtb
320 08:44:07.132633 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/676553/extract-nfsrootfs-k84pdatq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 08:44:07.132742 - bootz 0x82000000 0x83000000 0x88000000
322 08:44:07.132896 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 08:44:07.133303 start: 2.3 connect-device (timeout 00:05:00) [common]
325 08:44:07.133426 [common] connect-device Connecting to device using 'telnet conserv3 3002'
326 08:44:07.142162 Setting prompt string to ['lava-test: # ']
327 08:44:07.142955 end: 2.3 connect-device (duration 00:00:00) [common]
328 08:44:07.143181 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 08:44:07.143346 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 08:44:07.143503 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 08:44:07.144003 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
332 08:44:07.163180 >> OK - accepted request
333 08:44:07.164986 Returned 0 in 0 seconds
334 08:44:07.265477 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
336 08:44:07.266084 end: 2.4.1 reset-device (duration 00:00:00) [common]
337 08:44:07.266259 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
338 08:44:07.266436 Setting prompt string to ['Hit any key to stop autoboot']
339 08:44:07.266582 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
340 08:44:07.267185 Trying 192.168.56.22...
341 08:44:07.267336 Connected to conserv3.
342 08:44:07.267458 Escape character is '^]'.
343 08:44:07.267577
344 08:44:07.267713 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
345 08:44:07.267863
346 08:44:16.479242
347 08:44:16.486262 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
348 08:44:16.486480 Trying to boot from MMC1
349 08:44:20.543025
350 08:44:20.550123 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
351 08:44:20.550353 Trying to boot from MMC1
352 08:44:23.232981
353 08:44:23.239888 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
354 08:44:23.240067 Trying to boot from MMC1
355 08:44:23.823442
356 08:44:23.823721
357 08:44:23.828911 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
358 08:44:23.829088
359 08:44:23.829247 CPU : AM335X-GP rev 2.0
360 08:44:23.833285 Model: TI AM335x BeagleBone Black
361 08:44:23.833456 DRAM: 512 MiB
362 08:44:23.913788 Core: 160 devices, 18 uclasses, devicetree: separate
363 08:44:23.928088 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
364 08:44:24.328604 NAND: 0 MiB
365 08:44:24.338815 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
366 08:44:24.435293 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
367 08:44:24.457706 <ethaddr> not set. Validating first E-fuse MAC
368 08:44:24.488537 Net: eth2: ethernet@4a100000, eth3: usb_ether
370 08:44:24.546875 Hit any key to stop autoboot: 2
371 08:44:24.547282 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
372 08:44:24.547532 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
373 08:44:24.547697 Setting prompt string to ['=>']
374 08:44:24.547877 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
375 08:44:24.556641 0
376 08:44:24.557098 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
377 08:44:24.557279 Sending with 10 millisecond of delay
379 08:44:25.691206 => setenv autoload no
380 08:44:25.701609 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
381 08:44:25.703181 setenv autoload no
382 08:44:25.703548 Sending with 10 millisecond of delay
384 08:44:27.500178 => setenv initrd_high 0xffffffff
385 08:44:27.510493 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
386 08:44:27.510777 setenv initrd_high 0xffffffff
387 08:44:27.511050 Sending with 10 millisecond of delay
389 08:44:29.126339 => setenv fdt_high 0xffffffff
390 08:44:29.136705 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
391 08:44:29.137038 setenv fdt_high 0xffffffff
392 08:44:29.137380 Sending with 10 millisecond of delay
394 08:44:29.428542 => dhcp
395 08:44:29.438880 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
396 08:44:29.439183 dhcp
397 08:44:29.441380 link up on port 0, speed 100, full duplex
398 08:44:29.441547 BOOTP broadcast 1
399 08:44:29.693838 BOOTP broadcast 2
400 08:44:30.195793 BOOTP broadcast 3
401 08:44:31.198121 BOOTP broadcast 4
402 08:44:31.222256 *** Unhandled DHCP Option in OFFER/ACK: 42
403 08:44:31.260969 *** Unhandled DHCP Option in OFFER/ACK: 42
404 08:44:31.267478 DHCP client bound to address 192.168.56.5 (1822 ms)
405 08:44:31.268106 Sending with 10 millisecond of delay
407 08:44:33.139391 => setenv serverip 192.168.56.193
408 08:44:33.150192 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
409 08:44:33.150838 setenv serverip 192.168.56.193
410 08:44:33.151267 Sending with 10 millisecond of delay
412 08:44:36.645685 => tftp 0x82000000 676553/tftp-deploy-sxbex86h/kernel/zImage
413 08:44:36.656163 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:30)
414 08:44:36.656652 tftp 0x82000000 676553/tftp-deploy-sxbex86h/kernel/zImage
415 08:44:36.656829 link up on port 0, speed 100, full duplex
416 08:44:36.660650 Using ethernet@4a100000 device
417 08:44:36.666782 TFTP from server 192.168.56.193; our IP address is 192.168.56.5
418 08:44:36.673654 Filename '676553/tftp-deploy-sxbex86h/kernel/zImage'.
419 08:44:36.673896 Load address: 0x82000000
420 08:44:38.576903 Loading: *################################################## 10.9 MiB
421 08:44:38.577197 5.7 MiB/s
422 08:44:38.577412 done
423 08:44:38.581302 Bytes transferred = 11420160 (ae4200 hex)
424 08:44:38.581738 Sending with 10 millisecond of delay
426 08:44:43.024612 => tftp 0x83000000 676553/tftp-deploy-sxbex86h/ramdisk/ramdisk.cpio.gz.uboot
427 08:44:43.035005 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
428 08:44:43.035455 tftp 0x83000000 676553/tftp-deploy-sxbex86h/ramdisk/ramdisk.cpio.gz.uboot
429 08:44:43.035646 link up on port 0, speed 100, full duplex
430 08:44:43.039894 Using ethernet@4a100000 device
431 08:44:43.045532 TFTP from server 192.168.56.193; our IP address is 192.168.56.5
432 08:44:43.054278 Filename '676553/tftp-deploy-sxbex86h/ramdisk/ramdisk.cpio.gz.uboot'.
433 08:44:43.054482 Load address: 0x83000000
434 08:44:45.508279 Loading: *################################################## 14.2 MiB
435 08:44:45.508581 5.8 MiB/s
436 08:44:45.508740 done
437 08:44:45.512615 Bytes transferred = 14839709 (e26f9d hex)
438 08:44:45.513049 Sending with 10 millisecond of delay
440 08:44:47.368710 => setenv initrd_size ${filesize}
441 08:44:47.379110 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
442 08:44:47.379538 setenv initrd_size ${filesize}
443 08:44:47.379928 Sending with 10 millisecond of delay
445 08:44:51.522571 => tftp 0x88000000 676553/tftp-deploy-sxbex86h/dtb/am335x-boneblack.dtb
446 08:44:51.532990 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
447 08:44:51.533443 tftp 0x88000000 676553/tftp-deploy-sxbex86h/dtb/am335x-boneblack.dtb
448 08:44:51.533653 link up on port 0, speed 100, full duplex
449 08:44:51.537548 Using ethernet@4a100000 device
450 08:44:51.542979 TFTP from server 192.168.56.193; our IP address is 192.168.56.5
451 08:44:51.554723 Filename '676553/tftp-deploy-sxbex86h/dtb/am335x-boneblack.dtb'.
452 08:44:51.554985 Load address: 0x88000000
453 08:44:51.565896 Loading: *################################################## 68.9 KiB
454 08:44:51.566115 5.2 MiB/s
455 08:44:51.566270 done
456 08:44:51.571343 Bytes transferred = 70568 (113a8 hex)
457 08:44:51.571722 Sending with 10 millisecond of delay
459 08:45:04.985210 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/676553/extract-nfsrootfs-k84pdatq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
460 08:45:04.995612 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
461 08:45:04.996067 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/676553/extract-nfsrootfs-k84pdatq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
462 08:45:04.996477 Sending with 10 millisecond of delay
464 08:45:07.332981 => bootz 0x82000000 0x83000000 0x88000000
465 08:45:07.343378 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
466 08:45:07.343622 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
467 08:45:07.344058 bootz 0x82000000 0x83000000 0x88000000
468 08:45:07.344234 Kernel image @ 0x82000000 [ 0x000000 - 0xae4200 ]
469 08:45:07.345253 ## Loading init Ramdisk from Legacy Image at 83000000 ...
470 08:45:07.351041 Image Name:
471 08:45:07.351231 Created: 2024-08-30 8:44:07 UTC
472 08:45:07.356608 Image Type: ARM Linux RAMDisk Image (uncompressed)
473 08:45:07.362228 Data Size: 14839645 Bytes = 14.2 MiB
474 08:45:07.362425 Load Address: 00000000
475 08:45:07.368343 Entry Point: 00000000
476 08:45:07.537222 Verifying Checksum ... OK
477 08:45:07.537475 ## Flattened Device Tree blob at 88000000
478 08:45:07.543696 Booting using the fdt blob at 0x88000000
479 08:45:07.543887 Working FDT set to 88000000
480 08:45:07.549343 Using Device Tree in place at 88000000, end 880143a7
481 08:45:07.553819 Working FDT set to 88000000
482 08:45:07.567053
483 08:45:07.567248 Starting kernel ...
484 08:45:07.567394
485 08:45:07.567863 end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
486 08:45:07.568107 start: 2.4.4 auto-login-action (timeout 00:04:00) [common]
487 08:45:07.568296 Setting prompt string to ['Linux version [0-9]']
488 08:45:07.568479 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
489 08:45:07.568663 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
490 08:45:08.408320 [ 0.000000] Booting Linux on physical CPU 0x0
491 08:45:08.414318 start: 2.4.4.1 login-action (timeout 00:03:59) [common]
492 08:45:08.414573 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
493 08:45:08.414766 Setting prompt string to []
494 08:45:08.414970 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
495 08:45:08.415160 Using line separator: #'\n'#
496 08:45:08.415320 No login prompt set.
497 08:45:08.415487 Parsing kernel messages
498 08:45:08.415631 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
499 08:45:08.415942 [login-action] Waiting for messages, (timeout 00:03:59)
500 08:45:08.416112 Waiting using forced prompt support (timeout 00:01:59)
501 08:45:08.434152 [ 0.000000] Linux version 6.11.0-rc5-next-20240830 (KernelCI@build-j301620-arm-gcc-12-multi-v7-defconfig-nc68q) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Fri Aug 30 08:10:02 UTC 2024
502 08:45:08.439916 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
503 08:45:08.445451 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
504 08:45:08.451135 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
505 08:45:08.456999 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
506 08:45:08.462960 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
507 08:45:08.468320 [ 0.000000] Memory policy: Data cache writeback
508 08:45:08.475121 [ 0.000000] efi: UEFI not found.
509 08:45:08.484005 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
510 08:45:08.484205 [ 0.000000] Zone ranges:
511 08:45:08.489624 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
512 08:45:08.495301 [ 0.000000] Normal empty
513 08:45:08.495498 [ 0.000000] HighMem empty
514 08:45:08.501128 [ 0.000000] Movable zone start for each node
515 08:45:08.506797 [ 0.000000] Early memory node ranges
516 08:45:08.512414 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
517 08:45:08.518467 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
518 08:45:08.543784 [ 0.000000] CPU: All CPU(s) started in SVC mode.
519 08:45:08.549411 [ 0.000000] AM335X ES2.0 (sgx neon)
520 08:45:08.561142 [ 0.000000] percpu: Embedded 17 pages/cpu s40524 r8192 d20916 u69632
521 08:45:08.581699 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/676553/extract-nfsrootfs-k84pdatq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
522 08:45:08.587514 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
523 08:45:08.598967 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
524 08:45:08.604723 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
525 08:45:08.612305 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
526 08:45:08.641422 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
527 08:45:08.647357 <6>[ 0.000000] trace event string verifier disabled
528 08:45:08.647689 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
529 08:45:08.653098 <6>[ 0.000000] rcu: RCU event tracing is enabled.
530 08:45:08.664488 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
531 08:45:08.670177 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
532 08:45:08.676556 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
533 08:45:08.692404 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
534 08:45:08.709623 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
535 08:45:08.716278 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
536 08:45:08.807613 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
537 08:45:08.816269 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
538 08:45:08.828582 <6>[ 0.008339] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
539 08:45:08.836755 <6>[ 0.019135] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
540 08:45:08.846051 <6>[ 0.033914] Console: colour dummy device 80x30
541 08:45:08.852032 Matched prompt #6: WARNING:
542 08:45:08.852116 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
543 08:45:08.857608 <3>[ 0.038816] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
544 08:45:08.863374 <3>[ 0.045884] This ensures that you still see kernel messages. Please
545 08:45:08.866677 <3>[ 0.052611] update your kernel commandline.
546 08:45:08.907456 <6>[ 0.057221] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
547 08:45:08.913086 <6>[ 0.096134] CPU: Testing write buffer coherency: ok
548 08:45:08.918997 <6>[ 0.101505] CPU0: Spectre v2: using BPIALL workaround
549 08:45:08.919066 <6>[ 0.106970] pid_max: default: 32768 minimum: 301
550 08:45:08.930595 <6>[ 0.112162] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
551 08:45:08.937574 <6>[ 0.119989] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
552 08:45:08.944705 <6>[ 0.129367] CPU0: thread -1, cpu 0, socket -1, mpidr 0
553 08:45:08.952944 <6>[ 0.136352] Setting up static identity map for 0x80300000 - 0x803000ac
554 08:45:08.958754 <6>[ 0.146009] rcu: Hierarchical SRCU implementation.
555 08:45:08.966576 <6>[ 0.151290] rcu: Max phase no-delay instances is 1000.
556 08:45:08.974851 <6>[ 0.162351] EFI services will not be available.
557 08:45:08.980663 <6>[ 0.167625] smp: Bringing up secondary CPUs ...
558 08:45:08.986390 <6>[ 0.172670] smp: Brought up 1 node, 1 CPU
559 08:45:08.992243 <6>[ 0.177069] SMP: Total of 1 processors activated (996.14 BogoMIPS).
560 08:45:08.998111 <6>[ 0.183842] CPU: All CPU(s) started in SVC mode.
561 08:45:09.018509 <6>[ 0.189025] Memory: 405968K/522240K available (16384K kernel code, 2529K rwdata, 6772K rodata, 2048K init, 432K bss, 49084K reserved, 65536K cma-reserved, 0K highmem)
562 08:45:09.018720 <6>[ 0.205317] devtmpfs: initialized
563 08:45:09.041143 <6>[ 0.222700] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
564 08:45:09.049299 <6>[ 0.231281] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
565 08:45:09.058626 <6>[ 0.241742] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
566 08:45:09.069369 <6>[ 0.254085] pinctrl core: initialized pinctrl subsystem
567 08:45:09.078630 <6>[ 0.264729] DMI not present or invalid.
568 08:45:09.086939 <6>[ 0.270575] NET: Registered PF_NETLINK/PF_ROUTE protocol family
569 08:45:09.096486 <6>[ 0.279526] DMA: preallocated 256 KiB pool for atomic coherent allocations
570 08:45:09.111542 <6>[ 0.291043] thermal_sys: Registered thermal governor 'step_wise'
571 08:45:09.111749 <6>[ 0.291203] cpuidle: using governor menu
572 08:45:09.139293 <6>[ 0.326911] No ATAGs?
573 08:45:09.145555 <6>[ 0.329643] hw-breakpoint: debug architecture 0x4 unsupported.
574 08:45:09.155660 <6>[ 0.341561] Serial: AMBA PL011 UART driver
575 08:45:09.187682 <6>[ 0.375299] iommu: Default domain type: Translated
576 08:45:09.196880 <6>[ 0.380639] iommu: DMA domain TLB invalidation policy: strict mode
577 08:45:09.223343 <5>[ 0.410457] SCSI subsystem initialized
578 08:45:09.229281 <6>[ 0.415344] usbcore: registered new interface driver usbfs
579 08:45:09.235115 <6>[ 0.421402] usbcore: registered new interface driver hub
580 08:45:09.241864 <6>[ 0.427181] usbcore: registered new device driver usb
581 08:45:09.247757 <6>[ 0.433700] pps_core: LinuxPPS API ver. 1 registered
582 08:45:09.259122 <6>[ 0.439087] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
583 08:45:09.266306 <6>[ 0.448817] PTP clock support registered
584 08:45:09.266525 <6>[ 0.453276] EDAC MC: Ver: 3.0.0
585 08:45:09.314050 <6>[ 0.499179] scmi_core: SCMI protocol bus registered
586 08:45:09.329346 <6>[ 0.516638] vgaarb: loaded
587 08:45:09.351018 <6>[ 0.538691] clocksource: Switched to clocksource dmtimer
588 08:45:09.369392 <6>[ 0.556765] NET: Registered PF_INET protocol family
589 08:45:09.382122 <6>[ 0.562462] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
590 08:45:09.389227 <6>[ 0.571336] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
591 08:45:09.400578 <6>[ 0.580268] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
592 08:45:09.406619 <6>[ 0.588509] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
593 08:45:09.412590 <6>[ 0.596794] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
594 08:45:09.418108 <6>[ 0.604512] TCP: Hash tables configured (established 4096 bind 4096)
595 08:45:09.429645 <6>[ 0.611429] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
596 08:45:09.435397 <6>[ 0.618444] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
597 08:45:09.441685 <6>[ 0.626065] NET: Registered PF_UNIX/PF_LOCAL protocol family
598 08:45:09.527768 <6>[ 0.709696] RPC: Registered named UNIX socket transport module.
599 08:45:09.528051 <6>[ 0.716079] RPC: Registered udp transport module.
600 08:45:09.533515 <6>[ 0.721231] RPC: Registered tcp transport module.
601 08:45:09.542029 <6>[ 0.726336] RPC: Registered tcp-with-tls transport module.
602 08:45:09.547797 <6>[ 0.732268] RPC: Registered tcp NFSv4.1 backchannel transport module.
603 08:45:09.555168 <6>[ 0.739193] PCI: CLS 0 bytes, default 64
604 08:45:09.557314 <5>[ 0.744986] Initialise system trusted keyrings
605 08:45:09.580395 <6>[ 0.765067] Trying to unpack rootfs image as initramfs...
606 08:45:09.658119 <6>[ 0.839663] workingset: timestamp_bits=30 max_order=17 bucket_order=0
607 08:45:09.662816 <6>[ 0.847155] squashfs: version 4.0 (2009/01/31) Phillip Lougher
608 08:45:09.701632 <5>[ 0.889450] NFS: Registering the id_resolver key type
609 08:45:09.707434 <5>[ 0.895041] Key type id_resolver registered
610 08:45:09.713231 <5>[ 0.899714] Key type id_legacy registered
611 08:45:09.718950 <6>[ 0.904164] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
612 08:45:09.728695 <6>[ 0.911357] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
613 08:45:09.814105 <5>[ 1.001959] Key type asymmetric registered
614 08:45:09.820004 <5>[ 1.006483] Asymmetric key parser 'x509' registered
615 08:45:09.831522 <6>[ 1.011977] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
616 08:45:09.831764 <6>[ 1.019894] io scheduler mq-deadline registered
617 08:45:09.837340 <6>[ 1.024824] io scheduler kyber registered
618 08:45:09.842944 <6>[ 1.029296] io scheduler bfq registered
619 08:45:10.247246 <6>[ 1.431120] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
620 08:45:10.305532 <6>[ 1.492986] msm_serial: driver initialized
621 08:45:10.311556 <6>[ 1.497769] SuperH (H)SCI(F) driver initialized
622 08:45:10.317476 <6>[ 1.503096] STMicroelectronics ASC driver initialized
623 08:45:10.322686 <6>[ 1.508765] STM32 USART driver initialized
624 08:45:10.496687 <6>[ 1.683609] brd: module loaded
625 08:45:10.525951 <6>[ 1.712754] loop: module loaded
626 08:45:10.556250 <4>[ 1.739616] SPI driver spidev has no spi_device_id for elgin,jg10309-01
627 08:45:10.567122 <6>[ 1.753951] CAN device driver interface
628 08:45:10.573651 <6>[ 1.759127] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
629 08:45:10.579450 <6>[ 1.766021] e1000e: Intel(R) PRO/1000 Network Driver
630 08:45:10.585270 <6>[ 1.771471] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
631 08:45:10.591057 <6>[ 1.777902] igb: Intel(R) Gigabit Ethernet Network Driver
632 08:45:10.599289 <6>[ 1.783770] igb: Copyright (c) 2007-2014 Intel Corporation.
633 08:45:10.611150 <6>[ 1.792891] pegasus: Pegasus/Pegasus II USB Ethernet driver
634 08:45:10.616777 <6>[ 1.799047] usbcore: registered new interface driver pegasus
635 08:45:10.622624 <6>[ 1.805185] usbcore: registered new interface driver asix
636 08:45:10.628349 <6>[ 1.811071] usbcore: registered new interface driver ax88179_178a
637 08:45:10.634193 <6>[ 1.817638] usbcore: registered new interface driver cdc_ether
638 08:45:10.639995 <6>[ 1.823975] usbcore: registered new interface driver smsc75xx
639 08:45:10.645721 <6>[ 1.830206] usbcore: registered new interface driver smsc95xx
640 08:45:10.651476 <6>[ 1.836416] usbcore: registered new interface driver net1080
641 08:45:10.657267 <6>[ 1.842558] usbcore: registered new interface driver cdc_subset
642 08:45:10.663057 <6>[ 1.848965] usbcore: registered new interface driver zaurus
643 08:45:10.670662 <6>[ 1.855040] usbcore: registered new interface driver cdc_ncm
644 08:45:10.680438 <6>[ 1.864410] usbcore: registered new interface driver usb-storage
645 08:45:10.965438 <6>[ 2.151134] i2c_dev: i2c /dev entries driver
646 08:45:11.025872 <5>[ 2.205382] cpuidle: enable-method property 'ti,am3352' found operations
647 08:45:11.031443 <6>[ 2.214907] sdhci: Secure Digital Host Controller Interface driver
648 08:45:11.039353 <6>[ 2.221691] sdhci: Copyright(c) Pierre Ossman
649 08:45:11.046477 <6>[ 2.228016] Synopsys Designware Multimedia Card Interface Driver
650 08:45:11.051511 <6>[ 2.235849] sdhci-pltfm: SDHCI platform and OF driver helper
651 08:45:11.165238 <6>[ 2.349187] ledtrig-cpu: registered to indicate activity on CPUs
652 08:45:11.199353 <6>[ 2.379543] usbcore: registered new interface driver usbhid
653 08:45:11.199590 <6>[ 2.385575] usbhid: USB HID core driver
654 08:45:11.229895 <6>[ 2.414906] NET: Registered PF_INET6 protocol family
655 08:45:11.272421 <6>[ 2.460078] Segment Routing with IPv6
656 08:45:11.278085 <6>[ 2.464223] In-situ OAM (IOAM) with IPv6
657 08:45:11.285082 <6>[ 2.468623] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
658 08:45:11.292574 <6>[ 2.476007] NET: Registered PF_PACKET protocol family
659 08:45:11.298408 <6>[ 2.481588] can: controller area network core
660 08:45:11.298621 <6>[ 2.486416] NET: Registered PF_CAN protocol family
661 08:45:11.304174 <6>[ 2.491642] can: raw protocol
662 08:45:11.309739 <6>[ 2.494968] can: broadcast manager protocol
663 08:45:11.316696 <6>[ 2.499577] can: netlink gateway - max_hops=1
664 08:45:11.316910 <5>[ 2.505073] Key type dns_resolver registered
665 08:45:11.322554 <6>[ 2.510144] ThumbEE CPU extension supported.
666 08:45:11.328782 <5>[ 2.514832] Registering SWP/SWPB emulation handler
667 08:45:11.336869 <3>[ 2.520524] omap_voltage_late_init: Voltage driver support not added
668 08:45:11.538652 <5>[ 2.723979] Loading compiled-in X.509 certificates
669 08:45:11.662801 <6>[ 2.837436] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
670 08:45:11.669856 <6>[ 2.854087] pinctrl-single 44e10800.pinmux: 142 pins, size 568
671 08:45:11.695917 <3>[ 2.877635] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
672 08:45:11.895697 <3>[ 3.078197] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
673 08:45:12.103994 <6>[ 3.290015] OMAP GPIO hardware version 0.1
674 08:45:12.124426 <6>[ 3.308511] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
675 08:45:12.206675 <4>[ 3.390450] at24 2-0054: supply vcc not found, using dummy regulator
676 08:45:12.252302 <4>[ 3.435862] at24 2-0055: supply vcc not found, using dummy regulator
677 08:45:12.289987 <4>[ 3.473670] at24 2-0056: supply vcc not found, using dummy regulator
678 08:45:12.330333 <4>[ 3.513901] at24 2-0057: supply vcc not found, using dummy regulator
679 08:45:12.367039 <6>[ 3.551486] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
680 08:45:12.420943 <3>[ 3.601313] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
681 08:45:12.445352 <6>[ 3.622099] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
682 08:45:12.466060 <4>[ 3.648545] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
683 08:45:12.486974 <4>[ 3.669419] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
684 08:45:12.565866 <6>[ 3.749529] omap_rng 48310000.rng: Random Number Generator ver. 20
685 08:45:12.589051 <5>[ 3.775735] random: crng init done
686 08:45:12.625933 <6>[ 3.811816] Freeing initrd memory: 14492K
687 08:45:12.646402 <6>[ 3.828748] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
688 08:45:12.699516 <6>[ 3.881107] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
689 08:45:12.705291 <6>[ 3.891284] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
690 08:45:12.713722 <6>[ 3.898548] cpsw-switch 4a100000.switch: ALE Table size 1024
691 08:45:12.719454 <6>[ 3.904959] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
692 08:45:12.736787 <6>[ 3.913088] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
693 08:45:12.744319 <6>[ 3.924736] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
694 08:45:12.753886 <5>[ 3.933774] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
695 08:45:12.781414 <3>[ 3.963377] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
696 08:45:12.786113 <6>[ 3.971953] edma 49000000.dma: TI EDMA DMA engine driver
697 08:45:12.857869 <3>[ 4.039086] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
698 08:45:12.872460 <6>[ 4.053300] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
699 08:45:12.890935 <3>[ 4.076008] l3-aon-clkctrl:0000:0: failed to disable
700 08:45:12.932043 <6>[ 4.113635] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
701 08:45:12.937897 <6>[ 4.123141] printk: legacy console [ttyS0] enabled
702 08:45:12.940486 <6>[ 4.123141] printk: legacy console [ttyS0] enabled
703 08:45:12.946184 <6>[ 4.133491] printk: legacy bootconsole [omap8250] disabled
704 08:45:12.954710 <6>[ 4.133491] printk: legacy bootconsole [omap8250] disabled
705 08:45:13.008510 <4>[ 4.189396] tps65217-pmic: Failed to locate of_node [id: -1]
706 08:45:13.012139 <4>[ 4.196774] tps65217-bl: Failed to locate of_node [id: -1]
707 08:45:13.028431 <6>[ 4.216333] tps65217 0-0024: TPS65217 ID 0xe version 1.2
708 08:45:13.046842 <6>[ 4.223260] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
709 08:45:13.058544 <6>[ 4.236960] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
710 08:45:13.064454 <6>[ 4.248855] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
711 08:45:13.086649 <6>[ 4.268536] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
712 08:45:13.092414 <6>[ 4.277711] sdhci-omap 48060000.mmc: Got CD GPIO
713 08:45:13.100476 <4>[ 4.282867] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
714 08:45:13.114942 <4>[ 4.296173] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
715 08:45:13.121455 <4>[ 4.304852] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
716 08:45:13.131393 <4>[ 4.313626] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
717 08:45:13.230141 <6>[ 4.413083] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
718 08:45:13.277810 <6>[ 4.459367] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
719 08:45:13.284127 <6>[ 4.467870] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
720 08:45:13.293332 <6>[ 4.476659] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
721 08:45:13.367759 <6>[ 4.552192] mmc1: new high speed MMC card at address 0001
722 08:45:13.375804 <6>[ 4.561136] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
723 08:45:13.385842 <6>[ 4.570664] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
724 08:45:13.396848 <6>[ 4.578374] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
725 08:45:13.404652 <6>[ 4.589640] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
726 08:45:13.424701 <6>[ 4.606290] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
727 08:45:13.431176 <6>[ 4.613295] mmc0: new high speed SDHC card at address aaaa
728 08:45:13.433747 <6>[ 4.620249] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
729 08:45:13.445427 <6>[ 4.630936] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
730 08:45:15.507841 <6>[ 6.689728] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
731 08:45:23.241319 <5>[ 6.728709] Sending DHCP requests ..., OK
732 08:45:23.252651 <6>[ 14.433311] IP-Config: Got DHCP answer from 192.168.56.254, my address is 192.168.56.5
733 08:45:23.253031 <6>[ 14.441724] IP-Config: Complete:
734 08:45:23.263843 <6>[ 14.445262] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.56.5, mask=255.255.255.0, gw=192.168.56.254
735 08:45:23.274830 <6>[ 14.456044] host=192.168.56.5, domain=mayfield.sirena.org.uk, nis-domain=(none)
736 08:45:23.280911 <6>[ 14.464174] bootserver=192.168.56.254, rootserver=192.168.56.193, rootpath=
737 08:45:23.286577 <6>[ 14.464209] nameserver0=192.168.56.254
738 08:45:23.293092 <6>[ 14.476570] ntpserver0=50.205.244.22, ntpserver1=85.199.214.99
739 08:45:23.299640 <6>[ 14.484269] clk: Disabling unused clocks
740 08:45:23.303205 <6>[ 14.488999] PM: genpd: Disabling unused power domains
741 08:45:23.323662 <6>[ 14.508174] Freeing unused kernel image (initmem) memory: 2048K
742 08:45:23.330597 <6>[ 14.517994] Run /init as init process
743 08:45:23.353898 Loading, please wait...
744 08:45:23.429692 Starting systemd-udevd version 252.22-1~deb12u1
745 08:45:26.379638 <4>[ 17.560555] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
746 08:45:26.619286 <4>[ 17.800196] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
747 08:45:26.799328 <6>[ 17.987681] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
748 08:45:26.810691 <6>[ 17.993507] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
749 08:45:26.990863 <6>[ 18.177826] hub 1-0:1.0: USB hub found
750 08:45:27.011734 <6>[ 18.198886] hub 1-0:1.0: 1 port detected
751 08:45:27.195645 <6>[ 18.382123] tda998x 0-0070: found TDA19988
752 08:45:30.132552 Begin: Loading essential drivers ... done.
753 08:45:30.138131 Begin: Running /scripts/init-premount ... done.
754 08:45:30.143794 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
755 08:45:30.157732 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
756 08:45:30.158157 Device /sys/class/net/eth0 found
757 08:45:30.158336 done.
758 08:45:30.215122 Begin: Waiting up to 180 secs for any network device to become available ... done.
759 08:45:30.284346 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
760 08:45:30.383876 IP-Config: eth0 complete (dhcp from 192.168.56.254):
761 08:45:30.395149 address: 192.168.56.5 broadcast: 192.168.56.255 netmask: 255.255.255.0
762 08:45:30.400698 gateway: 192.168.56.254 dns0 : 192.168.56.254 dns1 : 0.0.0.0
763 08:45:30.406256 domain : mayfield.sirena.org.uk
764 08:45:30.411821 rootserver: 192.168.56.254 rootpath:
765 08:45:30.412178 filename :
766 08:45:30.505239 done.
767 08:45:30.516497 Begin: Running /scripts/nfs-bottom ... done.
768 08:45:30.579745 Begin: Running /scripts/init-bottom ... done.
769 08:45:32.088732 <30>[ 23.272457] systemd[1]: System time before build time, advancing clock.
770 08:45:32.289853 <30>[ 23.447743] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
771 08:45:32.298877 <30>[ 23.484678] systemd[1]: Detected architecture arm.
772 08:45:32.312014
773 08:45:32.312247 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
774 08:45:32.312412
775 08:45:32.344230 <30>[ 23.528613] systemd[1]: Hostname set to <debian-bookworm-armhf>.
776 08:45:34.618719 <30>[ 25.801742] systemd[1]: Queued start job for default target graphical.target.
777 08:45:34.635069 <30>[ 25.816371] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
778 08:45:34.643319 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
779 08:45:34.681874 <30>[ 25.864552] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
780 08:45:34.695127 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
781 08:45:34.733299 <30>[ 25.915015] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
782 08:45:34.746145 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
783 08:45:34.778382 <30>[ 25.960553] systemd[1]: Created slice user.slice - User and Session Slice.
784 08:45:34.785162 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
785 08:45:34.825747 <30>[ 26.000912] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
786 08:45:34.831834 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
787 08:45:34.870191 <30>[ 26.051183] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
788 08:45:34.882714 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
789 08:45:34.926113 <30>[ 26.099470] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
790 08:45:34.939954 <30>[ 26.121673] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
791 08:45:34.945715 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
792 08:45:34.977006 <30>[ 26.159245] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
793 08:45:34.985098 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
794 08:45:35.017839 <30>[ 26.199558] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
795 08:45:35.026451 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
796 08:45:35.057635 <30>[ 26.239727] systemd[1]: Reached target paths.target - Path Units.
797 08:45:35.062638 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
798 08:45:35.097108 <30>[ 26.279370] systemd[1]: Reached target remote-fs.target - Remote File Systems.
799 08:45:35.104524 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
800 08:45:35.137093 <30>[ 26.319210] systemd[1]: Reached target slices.target - Slice Units.
801 08:45:35.142918 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
802 08:45:35.178946 <30>[ 26.360126] systemd[1]: Reached target swap.target - Swaps.
803 08:45:35.182852 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
804 08:45:35.217920 <30>[ 26.399433] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
805 08:45:35.225548 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
806 08:45:35.258764 <30>[ 26.440251] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
807 08:45:35.267034 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
808 08:45:35.355987 <30>[ 26.533036] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
809 08:45:35.368917 <30>[ 26.550792] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
810 08:45:35.377202 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
811 08:45:35.410514 <30>[ 26.591102] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
812 08:45:35.417840 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
813 08:45:35.456517 <30>[ 26.637605] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
814 08:45:35.464530 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
815 08:45:35.502839 <30>[ 26.683437] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
816 08:45:35.508499 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
817 08:45:35.549541 <30>[ 26.732184] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
818 08:45:35.562589 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
819 08:45:35.605208 <30>[ 26.780625] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
820 08:45:35.621406 <30>[ 26.797312] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
821 08:45:35.667182 <30>[ 26.849298] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
822 08:45:35.674584 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
823 08:45:35.750871 <30>[ 26.933451] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
824 08:45:35.769922 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
825 08:45:35.840143 <30>[ 27.021260] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
826 08:45:35.867403 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
827 08:45:35.928315 <30>[ 27.110395] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
828 08:45:35.948111 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
829 08:45:36.008002 <30>[ 27.190254] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
830 08:45:36.019772 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
831 08:45:36.089679 <30>[ 27.272639] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
832 08:45:36.116171 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
833 08:45:36.178398 <30>[ 27.360080] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
834 08:45:36.207997 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
835 08:45:36.270181 <30>[ 27.453172] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
836 08:45:36.287254 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
837 08:45:36.348379 <30>[ 27.531329] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
838 08:45:36.373938 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
839 08:45:36.414006 <28>[ 27.590954] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
840 08:45:36.422473 <28>[ 27.604574] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
841 08:45:36.467852 <30>[ 27.649717] systemd[1]: Starting systemd-journald.service - Journal Service...
842 08:45:36.474213 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
843 08:45:36.516613 <30>[ 27.700228] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
844 08:45:36.538060 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
845 08:45:36.611225 <30>[ 27.794224] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
846 08:45:36.657867 Starting [0;1;39msystemd-network-g… units from Kernel command line...
847 08:45:36.733028 <30>[ 27.914535] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
848 08:45:36.792822 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
849 08:45:36.888390 <30>[ 28.070654] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
850 08:45:36.928964 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
851 08:45:37.010605 <30>[ 28.193721] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
852 08:45:37.038081 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
853 08:45:37.068707 <30>[ 28.251631] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
854 08:45:37.096808 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
855 08:45:37.130547 <30>[ 28.312504] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
856 08:45:37.177116 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
857 08:45:37.339742 <30>[ 28.523012] systemd[1]: modprobe@configfs.service: Deactivated successfully.
858 08:45:37.377398 <30>[ 28.559326] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
859 08:45:37.386569 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
860 08:45:37.408287 <30>[ 28.590489] systemd[1]: Started systemd-journald.service - Journal Service.
861 08:45:37.415466 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
862 08:45:37.443951 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
863 08:45:37.482583 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
864 08:45:37.530954 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
865 08:45:37.577174 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
866 08:45:37.611900 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
867 08:45:37.659554 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
868 08:45:37.690582 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
869 08:45:37.729480 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
870 08:45:37.766985 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
871 08:45:37.836648 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
872 08:45:37.897501 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
873 08:45:37.972528 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
874 08:45:38.058848 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
875 08:45:38.108358 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
876 08:45:38.263604 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
877 08:45:38.298752 <46>[ 29.481568] systemd-journald[164]: Received client request to flush runtime journal.
878 08:45:38.440192 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
879 08:45:38.511178 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
880 08:45:39.318288 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
881 08:45:39.368276 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
882 08:45:40.059853 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
883 08:45:40.229232 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
884 08:45:40.266779 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
885 08:45:40.296745 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
886 08:45:40.382770 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
887 08:45:40.439747 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
888 08:45:41.331376 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
889 08:45:41.463389 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
890 08:45:41.996871 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
891 08:45:43.239470 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
892 08:45:43.981903 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
893 08:45:44.280837 <5>[ 35.464328] cfg80211: Loading compiled-in X.509 certificates for regulatory database
894 08:45:45.618939 <5>[ 36.804544] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
895 08:45:45.705186 <5>[ 36.886979] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
896 08:45:45.714380 <4>[ 36.895893] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
897 08:45:45.718477 <6>[ 36.905013] cfg80211: failed to load regulatory.db
898 08:45:46.664192 [[0m[0;31m* [0m] Job systemd-networkd.service/start running (12s / 1min 36s)
899 08:45:46.947197 M
[K[[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
900 08:45:54.105279 [K[[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
901 08:45:54.138409 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
902 08:45:54.171258 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
903 08:45:54.247089 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
904 08:45:54.329964 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
905 08:45:54.405446 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
906 08:45:54.453693 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
907 08:45:54.530616 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
908 08:45:54.587592 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
909 08:45:54.644055 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
910 08:45:54.704690 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
911 08:45:54.757846 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
912 08:45:54.794626 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
913 08:45:54.926275 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
914 08:45:55.221381 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
915 08:45:55.260145 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
916 08:45:55.305346 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
917 08:45:55.349110 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
918 08:45:55.439831 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
919 08:45:55.487942 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
920 08:45:55.593982 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
921 08:45:55.645493 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
922 08:45:55.701401 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
923 08:45:55.742202 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
924 08:45:55.783044 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
925 08:45:55.819522 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
926 08:45:55.863387 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
927 08:45:55.942098 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
928 08:45:56.030285 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
929 08:45:56.176796 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
930 08:45:56.266178 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
931 08:45:56.319322 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
932 08:45:56.377635 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
933 08:45:56.403150 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
934 08:45:56.562877 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
935 08:45:56.625822 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
936 08:45:56.656499 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
937 08:45:56.686771 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
938 08:45:56.718380 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
939 08:45:56.911406 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
940 08:45:57.087197 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
941 08:45:57.486216 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
942 08:45:57.788204 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
943 08:45:57.846919 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
944 08:45:57.892283 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
945 08:45:57.989680 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
946 08:45:58.153994 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
947 08:45:58.309178
948 08:45:58.312404 Debian GNU/Linux 12 worm-armhf login: root (automatic login)
949 08:45:58.312510
950 08:45:58.606692 Linux debian-bookworm-armhf 6.11.0-rc5-next-20240830 #1 SMP Fri Aug 30 08:10:02 UTC 2024 armv7l
951 08:45:58.606871
952 08:45:58.612299 The programs included with the Debian GNU/Linux system are free software;
953 08:45:58.617941 the exact distribution terms for each program are described in the
954 08:45:58.623531 individual files in /usr/share/doc/*/copyright.
955 08:45:58.623658
956 08:45:58.629110 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
957 08:45:58.632819 permitted by applicable law.
958 08:46:03.599583 Unable to match end of the kernel message
960 08:46:03.599980 Setting prompt string to ['/ #']
961 08:46:03.600100 end: 2.4.4.1 login-action (duration 00:00:55) [common]
963 08:46:03.600324 end: 2.4.4 auto-login-action (duration 00:00:56) [common]
964 08:46:03.600421 start: 2.4.5 expect-shell-connection (timeout 00:03:04) [common]
965 08:46:03.600494 Setting prompt string to ['/ #']
966 08:46:03.600560 Forcing a shell prompt, looking for ['/ #']
968 08:46:03.650790 / #
969 08:46:03.651052 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
970 08:46:03.651141 Waiting using forced prompt support (timeout 00:02:30)
971 08:46:03.655750
972 08:46:03.665138 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
973 08:46:03.665297 start: 2.4.6 export-device-env (timeout 00:03:03) [common]
974 08:46:03.665394 Sending with 10 millisecond of delay
976 08:46:08.651757 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/676553/extract-nfsrootfs-k84pdatq'
977 08:46:08.662207 export NFS_ROOTFS='/var/lib<46>[ 56.498273] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
978 08:46:08.662439 /<46>[ 56.546012] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
979 08:46:08.662565 lava/dispatcher/tmp/676553/extract-nfsrootfs-k84pdatq'
980 08:46:08.662878 Sending with 10 millisecond of delay
982 08:46:10.941700 / # export NFS_SERVER_IP='192.168.56.193'
983 08:46:10.952495 export NFS_SERVER_IP='192.168.56.193'
984 08:46:10.953068 end: 2.4.6 export-device-env (duration 00:00:07) [common]
985 08:46:10.953261 end: 2.4 uboot-commands (duration 00:02:04) [common]
986 08:46:10.953438 end: 2 uboot-action (duration 00:02:04) [common]
987 08:46:10.953619 start: 3 lava-test-retry (timeout 00:07:27) [common]
988 08:46:10.953820 start: 3.1 lava-test-shell (timeout 00:07:27) [common]
989 08:46:10.953999 Using namespace: common
991 08:46:11.054842 / # #
992 08:46:11.055313 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
993 08:46:11.059939 #
994 08:46:11.065539 Using /lava-676553
996 08:46:11.166831 / # export SHELL=/bin/bash
997 08:46:11.171888 export SHELL=/bin/bash
999 08:46:11.279944 / # . /lava-676553/environment
1000 08:46:11.284995 . /lava-676553/environment
1002 08:46:11.398860 / # /lava-676553/bin/lava-test-runner /lava-676553/0
1003 08:46:11.399284 Test shell timeout: 10s (minimum of the action and connection timeout)
1004 08:46:11.403719 /lava-676553/bin/lava-test-runner /lava-676553/0
1005 08:46:11.771118 + export TESTRUN_ID=0_timesync-off
1006 08:46:11.778889 + TESTRUN_ID=0_timesync-off
1007 08:46:11.779067 + cd /lava-676553/0/tests/0_timesync-off
1008 08:46:11.779192 ++ cat uuid
1009 08:46:11.793154 + UUID=676553_1.6.2.4.1
1010 08:46:11.793345 + set +x
1011 08:46:11.801809 <LAVA_SIGNAL_STARTRUN 0_timesync-off 676553_1.6.2.4.1>
1012 08:46:11.802046 + systemctl stop systemd-timesyncd
1013 08:46:11.802435 Received signal: <STARTRUN> 0_timesync-off 676553_1.6.2.4.1
1014 08:46:11.802599 Starting test lava.0_timesync-off (676553_1.6.2.4.1)
1015 08:46:11.802799 Skipping test definition patterns.
1016 08:46:12.101369 + set +x
1017 08:46:12.101632 <LAVA_SIGNAL_ENDRUN 0_timesync-off 676553_1.6.2.4.1>
1018 08:46:12.102004 Received signal: <ENDRUN> 0_timesync-off 676553_1.6.2.4.1
1019 08:46:12.102175 Ending use of test pattern.
1020 08:46:12.102291 Ending test lava.0_timesync-off (676553_1.6.2.4.1), duration 0.30
1022 08:46:12.278669 + export TESTRUN_ID=1_kselftest-dt
1023 08:46:12.287087 + TESTRUN_ID=1_kselftest-dt
1024 08:46:12.287384 + cd /lava-676553/0/tests/1_kselftest-dt
1025 08:46:12.287511 ++ cat uuid
1026 08:46:12.303167 + UUID=676553_1.6.2.4.5
1027 08:46:12.303495 + set +x
1028 08:46:12.308623 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 676553_1.6.2.4.5>
1029 08:46:12.308868 + cd ./automated/linux/kselftest/
1030 08:46:12.309194 Received signal: <STARTRUN> 1_kselftest-dt 676553_1.6.2.4.5
1031 08:46:12.309321 Starting test lava.1_kselftest-dt (676553_1.6.2.4.5)
1032 08:46:12.309505 Skipping test definition patterns.
1033 08:46:12.334045 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20240830/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1034 08:46:12.428450 INFO: install_deps skipped
1035 08:46:13.080591 --2024-08-30 08:46:13-- http://storage.kernelci.org/next/master/next-20240830/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1036 08:46:13.116201 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1037 08:46:13.257909 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1038 08:46:13.398161 HTTP request sent, awaiting response... 200 OK
1039 08:46:13.398435 Length: 4009156 (3.8M) [application/octet-stream]
1040 08:46:13.403822 Saving to: 'kselftest_armhf.tar.gz'
1041 08:46:13.404036
1042 08:46:15.068105
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 180KB/s
kselftest_armhf.tar 5%[> ] 218.67K 388KB/s
kselftest_armhf.tar 22%[===> ] 888.48K 1.04MB/s
kselftest_armhf.tar 32%[=====> ] 1.22M 1.05MB/s
kselftest_armhf.tar 81%[===============> ] 3.11M 2.14MB/s
kselftest_armhf.tar 100%[===================>] 3.82M 2.31MB/s
kselftest_armhf.tar 100%[===================>] 3.82M 2.31MB/s in 1.7s
1043 08:46:15.068409
1044 08:46:15.558931 2024-08-30 08:46:15 (2.31 MB/s) - 'kselftest_armhf.tar.gz' saved [4009156/4009156]
1045 08:46:15.559236
1046 08:46:32.899955 skiplist:
1047 08:46:32.900140 ========================================
1048 08:46:32.904732 ========================================
1049 08:46:32.984430 dt:test_unprobed_devices.sh
1050 08:46:33.013032 ============== Tests to run ===============
1051 08:46:33.020872 dt:test_unprobed_devices.sh
1052 08:46:33.023862 ===========End Tests to run ===============
1053 08:46:33.033275 shardfile-dt pass
1054 08:46:33.251900 <12>[ 84.441197] kselftest: Running tests in dt
1055 08:46:33.281467 TAP version 13
1056 08:46:33.302136 1..1
1057 08:46:33.355187 # timeout set to 45
1058 08:46:33.355425 # selftests: dt: test_unprobed_devices.sh
1059 08:46:34.170413 # TAP version 13
1060 08:46:46.306152 # 1..260
1061 08:46:46.476874 # ok 1 / # SKIP
1062 08:46:46.499478 # ok 2 /clk_mcasp0
1063 08:46:46.568783 # ok 3 /clk_mcasp0_fixed # SKIP
1064 08:46:46.638214 # ok 4 /cpus/cpu@0 # SKIP
1065 08:46:46.707713 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1066 08:46:46.732305 # ok 6 /fixedregulator0
1067 08:46:46.751751 # ok 7 /leds
1068 08:46:46.768216 # ok 8 /ocp
1069 08:46:46.792472 # ok 9 /ocp/interconnect@44c00000
1070 08:46:46.818926 # ok 10 /ocp/interconnect@44c00000/segment@0
1071 08:46:46.836500 # ok 11 /ocp/interconnect@44c00000/segment@100000
1072 08:46:46.865903 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1073 08:46:46.931753 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1074 08:46:46.956014 # ok 14 /ocp/interconnect@44c00000/segment@200000
1075 08:46:46.980565 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1076 08:46:47.082524 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1077 08:46:47.150235 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1078 08:46:47.222128 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1079 08:46:47.292300 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1080 08:46:47.363611 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1081 08:46:47.432367 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1082 08:46:47.501880 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1083 08:46:47.571195 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1084 08:46:47.640615 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1085 08:46:47.711420 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1086 08:46:47.781340 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1087 08:46:47.853713 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1088 08:46:47.925311 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1089 08:46:47.994694 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1090 08:46:48.064749 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1091 08:46:48.135740 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1092 08:46:48.205269 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1093 08:46:48.282374 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1094 08:46:48.352489 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1095 08:46:48.423575 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1096 08:46:48.489593 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1097 08:46:48.560952 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1098 08:46:48.632420 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1099 08:46:48.704802 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1100 08:46:48.779682 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1101 08:46:48.852925 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1102 08:46:48.920031 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1103 08:46:48.991730 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1104 08:46:49.063479 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1105 08:46:49.134503 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1106 08:46:49.209106 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1107 08:46:49.281928 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1108 08:46:49.353395 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1109 08:46:49.424551 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1110 08:46:49.491901 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1111 08:46:49.563074 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1112 08:46:49.637093 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1113 08:46:49.707969 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1114 08:46:49.778881 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1115 08:46:49.849987 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1116 08:46:49.924741 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1117 08:46:49.993246 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1118 08:46:50.063276 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1119 08:46:50.133771 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1120 08:46:50.205180 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1121 08:46:50.279919 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1122 08:46:50.351310 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1123 08:46:50.415860 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1124 08:46:50.491025 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1125 08:46:50.569956 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1126 08:46:50.643613 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1127 08:46:50.720638 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1128 08:46:50.796196 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1129 08:46:50.872629 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1130 08:46:50.949676 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1131 08:46:51.032890 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1132 08:46:51.101802 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1133 08:46:51.178321 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1134 08:46:51.254674 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1135 08:46:51.331034 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1136 08:46:51.407539 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1137 08:46:51.483738 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1138 08:46:51.559528 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1139 08:46:51.638872 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1140 08:46:51.714945 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1141 08:46:51.788681 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1142 08:46:51.865497 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1143 08:46:51.944051 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1144 08:46:52.015723 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1145 08:46:52.093238 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1146 08:46:52.169799 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1147 08:46:52.247025 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1148 08:46:52.324461 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1149 08:46:52.395473 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1150 08:46:52.471446 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1151 08:46:52.545188 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1152 08:46:52.623952 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1153 08:46:52.698060 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1154 08:46:52.772139 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1155 08:46:52.792852 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1156 08:46:52.821128 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1157 08:46:52.845106 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1158 08:46:52.865446 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1159 08:46:52.889601 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1160 08:46:52.913903 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1161 08:46:52.938026 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1162 08:46:52.960858 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1163 08:46:53.077940 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1164 08:46:53.099159 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1165 08:46:53.128005 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1166 08:46:53.153300 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1167 08:46:53.264097 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1168 08:46:53.340591 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1169 08:46:53.422158 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1170 08:46:53.501607 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1171 08:46:53.573725 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1172 08:46:53.649847 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1173 08:46:53.727124 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1174 08:46:53.803279 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1175 08:46:53.878607 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1176 08:46:53.950871 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1177 08:46:54.028222 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1178 08:46:54.103403 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1179 08:46:54.179123 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1180 08:46:54.258916 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1181 08:46:54.335459 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1182 08:46:54.411917 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1183 08:46:54.434565 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1184 08:46:54.510054 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1185 08:46:54.585646 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1186 08:46:54.662081 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1187 08:46:54.684861 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1188 08:46:54.760007 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1189 08:46:54.783113 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1190 08:46:54.857110 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1191 08:46:54.880960 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1192 08:46:54.906887 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1193 08:46:54.930046 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1194 08:46:54.956151 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1195 08:46:54.978804 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1196 08:46:55.005020 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1197 08:46:55.031376 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1198 08:46:55.109113 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1199 08:46:55.131306 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1200 08:46:55.155690 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1201 08:46:55.231914 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1202 08:46:55.308587 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1203 08:46:55.330880 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1204 08:46:55.408141 # not ok 144 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/adc
1205 08:46:55.483824 # not ok 145 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/tsc
1206 08:46:55.588609 # not ok 146 /ocp/interconnect@47c00000
1207 08:46:55.668391 # not ok 147 /ocp/interconnect@47c00000/segment@0
1208 08:46:55.689273 # ok 148 /ocp/interconnect@48000000
1209 08:46:55.710464 # ok 149 /ocp/interconnect@48000000/segment@0
1210 08:46:55.735496 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@22000
1211 08:46:55.760294 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@24000
1212 08:46:55.784967 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@2a000
1213 08:46:55.809246 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@30000
1214 08:46:55.834469 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@38000
1215 08:46:55.858603 # ok 155 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1216 08:46:55.881553 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@3c000
1217 08:46:55.960899 # not ok 157 /ocp/interconnect@48000000/segment@0/target-module@40000
1218 08:46:56.034678 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1219 08:46:56.056416 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@42000
1220 08:46:56.081395 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1221 08:46:56.109600 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@44000
1222 08:46:56.132464 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1223 08:46:56.153297 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@46000
1224 08:46:56.177302 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1225 08:46:56.199418 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@48000
1226 08:46:56.228327 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1227 08:46:56.251605 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4a000
1228 08:46:56.274989 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1229 08:46:56.299265 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@4c000
1230 08:46:56.326768 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1231 08:46:56.344968 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@60000
1232 08:46:56.369043 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1233 08:46:56.397485 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@80000
1234 08:46:56.420525 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@c8000
1235 08:46:56.442621 # ok 175 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1236 08:46:56.467163 # ok 176 /ocp/interconnect@48000000/segment@0/target-module@ca000
1237 08:46:56.492486 # ok 177 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1238 08:46:56.515318 # ok 178 /ocp/interconnect@48000000/segment@100000
1239 08:46:56.536566 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1240 08:46:56.563052 # ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1241 08:46:56.638930 # not ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1242 08:46:56.714385 # ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1243 08:46:56.783261 # not ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1244 08:46:56.858234 # ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1245 08:46:56.924612 # not ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1246 08:46:57.002809 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1247 08:46:57.080671 # not ok 187 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1248 08:46:57.155930 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1249 08:46:57.180422 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1250 08:46:57.202173 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1251 08:46:57.224132 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1252 08:46:57.248931 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1253 08:46:57.272937 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1254 08:46:57.302307 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1255 08:46:57.321343 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1256 08:46:57.351534 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1257 08:46:57.372278 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1258 08:46:57.399881 # ok 198 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1259 08:46:57.422130 # ok 199 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1260 08:46:57.445838 # ok 200 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1261 08:46:57.467072 # ok 201 /ocp/interconnect@48000000/segment@200000
1262 08:46:57.492765 # ok 202 /ocp/interconnect@48000000/segment@200000/target-module@0
1263 08:46:57.575267 # ok 203 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1264 08:46:57.600480 # ok 204 /ocp/interconnect@48000000/segment@300000
1265 08:46:57.621181 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@0
1266 08:46:57.649128 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@10000
1267 08:46:57.671880 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1268 08:46:57.699196 # ok 208 /ocp/interconnect@48000000/segment@300000/target-module@2000
1269 08:46:57.721819 # ok 209 /ocp/interconnect@48000000/segment@300000/target-module@4000
1270 08:46:57.742692 # ok 210 /ocp/interconnect@48000000/segment@300000/target-module@e000
1271 08:46:57.820018 # not ok 211 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1272 08:46:57.843204 # ok 212 /ocp/interconnect@4a000000
1273 08:46:57.861059 # ok 213 /ocp/interconnect@4a000000/segment@0
1274 08:46:57.891833 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@100000
1275 08:46:57.913240 # ok 215 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1276 08:46:57.938925 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1277 08:46:57.960394 # ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000
1278 08:46:58.040280 # not ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1279 08:46:58.153925 # ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1280 08:46:58.226625 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1281 08:46:58.339870 # ok 221 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1282 08:46:58.411324 # not ok 222 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1283 08:46:58.484796 # not ok 223 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1284 08:46:58.587617 # not ok 224 /ocp/interconnect@4b140000
1285 08:46:58.661094 # not ok 225 /ocp/interconnect@4b140000/segment@0
1286 08:46:58.740437 # ok 226 /ocp/interrupt-controller@48200000 # SKIP
1287 08:46:58.758238 # ok 227 /ocp/target-module@40300000
1288 08:46:58.781558 # ok 228 /ocp/target-module@40300000/sram@0
1289 08:46:58.861691 # ok 229 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1290 08:46:58.936013 # ok 230 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1291 08:46:58.950837 # ok 231 /ocp/target-module@47400000
1292 08:46:58.979505 # ok 232 /ocp/target-module@47400000/dma-controller@2000
1293 08:46:59.000274 # ok 233 /ocp/target-module@47400000/usb-phy@1300
1294 08:46:59.027193 # ok 234 /ocp/target-module@47400000/usb-phy@1b00
1295 08:46:59.049854 # ok 235 /ocp/target-module@47400000/usb@1400
1296 08:46:59.068002 # ok 236 /ocp/target-module@47400000/usb@1800
1297 08:46:59.090785 # ok 237 /ocp/target-module@47810000
1298 08:46:59.118312 # ok 238 /ocp/target-module@49000000
1299 08:46:59.139428 # ok 239 /ocp/target-module@49000000/dma@0
1300 08:46:59.160917 # ok 240 /ocp/target-module@49800000
1301 08:46:59.185400 # ok 241 /ocp/target-module@49800000/dma@0
1302 08:46:59.208914 # ok 242 /ocp/target-module@49900000
1303 08:46:59.230870 # ok 243 /ocp/target-module@49900000/dma@0
1304 08:46:59.258138 # ok 244 /ocp/target-module@49a00000
1305 08:46:59.282888 # ok 245 /ocp/target-module@49a00000/dma@0
1306 08:46:59.298302 # ok 246 /ocp/target-module@4c000000
1307 08:46:59.379500 # not ok 247 /ocp/target-module@4c000000/emif@0
1308 08:46:59.401444 # ok 248 /ocp/target-module@50000000
1309 08:46:59.423921 # ok 249 /ocp/target-module@53100000
1310 08:46:59.504935 # not ok 250 /ocp/target-module@53100000/sham@0
1311 08:46:59.520854 # ok 251 /ocp/target-module@53500000
1312 08:46:59.600191 # not ok 252 /ocp/target-module@53500000/aes@0
1313 08:46:59.625360 # ok 253 /ocp/target-module@56000000
1314 08:46:59.726006 # ok 254 /ocp/target-module@56000000/gpu@0 # SKIP
1315 08:46:59.800509 # ok 255 /opp-table # SKIP
1316 08:46:59.869344 # ok 256 /soc # SKIP
1317 08:46:59.891917 # ok 257 /sound
1318 08:46:59.916437 # ok 258 /target-module@4b000000
1319 08:46:59.940952 # ok 259 /target-module@4b000000/target-module@140000
1320 08:46:59.962849 # ok 260 /target-module@4b000000/target-module@140000/pmu@0
1321 08:46:59.971154 # # Totals: pass:118 fail:29 xfail:0 xpass:0 skip:113 error:0
1322 08:46:59.979041 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1323 08:47:02.362264 dt_test_unprobed_devices_sh_ skip
1324 08:47:02.367818 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1325 08:47:02.373519 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1326 08:47:02.373794 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1327 08:47:02.379022 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1328 08:47:02.384745 dt_test_unprobed_devices_sh_fixedregulator0 pass
1329 08:47:02.390216 dt_test_unprobed_devices_sh_leds pass
1330 08:47:02.390434 dt_test_unprobed_devices_sh_ocp pass
1331 08:47:02.395996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1332 08:47:02.401873 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1333 08:47:02.407407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1334 08:47:02.418732 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1335 08:47:02.424268 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1336 08:47:02.429881 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1337 08:47:02.441014 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1338 08:47:02.446676 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1339 08:47:02.458028 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1340 08:47:02.469058 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1341 08:47:02.480363 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1342 08:47:02.485737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1343 08:47:02.496867 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1344 08:47:02.508066 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1345 08:47:02.519364 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1346 08:47:02.530455 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1347 08:47:02.536280 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1348 08:47:02.547521 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1349 08:47:02.558650 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1350 08:47:02.570014 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1351 08:47:02.581111 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1352 08:47:02.586712 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1353 08:47:02.598079 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1354 08:47:02.609099 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1355 08:47:02.620299 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1356 08:47:02.625532 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1357 08:47:02.636787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1358 08:47:02.647967 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1359 08:47:02.658989 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1360 08:47:02.670354 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1361 08:47:02.676140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1362 08:47:02.687465 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1363 08:47:02.698692 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1364 08:47:02.709869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1365 08:47:02.721113 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1366 08:47:02.732145 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1367 08:47:02.743408 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1368 08:47:02.754398 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1369 08:47:02.765459 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1370 08:47:02.776652 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1371 08:47:02.787824 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1372 08:47:02.798931 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1373 08:47:02.810129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1374 08:47:02.821761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1375 08:47:02.832965 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1376 08:47:02.844125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1377 08:47:02.855251 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1378 08:47:02.866527 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1379 08:47:02.877719 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1380 08:47:02.888868 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1381 08:47:02.900109 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1382 08:47:02.910813 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1383 08:47:02.922182 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1384 08:47:02.933440 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1385 08:47:02.944570 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1386 08:47:02.956067 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1387 08:47:02.961670 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1388 08:47:02.972849 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1389 08:47:02.984061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1390 08:47:02.995254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1391 08:47:03.006411 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1392 08:47:03.017646 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1393 08:47:03.028728 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1394 08:47:03.040047 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1395 08:47:03.050751 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1396 08:47:03.061948 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1397 08:47:03.073421 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1398 08:47:03.084358 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1399 08:47:03.095531 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1400 08:47:03.107126 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1401 08:47:03.118316 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1402 08:47:03.129515 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1403 08:47:03.140925 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1404 08:47:03.151884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1405 08:47:03.157490 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1406 08:47:03.168642 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1407 08:47:03.179975 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1408 08:47:03.190650 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1409 08:47:03.201785 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1410 08:47:03.207374 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1411 08:47:03.224275 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1412 08:47:03.235459 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1413 08:47:03.241405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1414 08:47:03.258220 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1415 08:47:03.269392 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1416 08:47:03.280603 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1417 08:47:03.286229 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1418 08:47:03.297402 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1419 08:47:03.308491 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1420 08:47:03.314163 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1421 08:47:03.325075 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1422 08:47:03.336252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1423 08:47:03.341935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1424 08:47:03.352977 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1425 08:47:03.358473 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1426 08:47:03.369990 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1427 08:47:03.381333 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1428 08:47:03.392501 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1429 08:47:03.403609 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1430 08:47:03.414857 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1431 08:47:03.426178 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1432 08:47:03.437252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1433 08:47:03.448348 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1434 08:47:03.459583 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1435 08:47:03.470372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1436 08:47:03.481696 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1437 08:47:03.492895 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1438 08:47:03.509715 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1439 08:47:03.521189 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1440 08:47:03.532376 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1441 08:47:03.543615 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1442 08:47:03.554813 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1443 08:47:03.571520 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1444 08:47:03.582719 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1445 08:47:03.593957 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1446 08:47:03.604956 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1447 08:47:03.610240 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1448 08:47:03.621413 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1449 08:47:03.632754 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1450 08:47:03.638228 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1451 08:47:03.649417 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1452 08:47:03.655002 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1453 08:47:03.666250 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1454 08:47:03.671885 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1455 08:47:03.682959 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1456 08:47:03.688721 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1457 08:47:03.699829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1458 08:47:03.705723 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1459 08:47:03.716616 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1460 08:47:03.727830 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1461 08:47:03.739187 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1462 08:47:03.750107 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1463 08:47:03.761280 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1464 08:47:03.766867 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1465 08:47:03.778051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1466 08:47:03.783721 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc fail
1467 08:47:03.794836 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc fail
1468 08:47:03.800480 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1469 08:47:03.806108 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1470 08:47:03.811684 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1471 08:47:03.817236 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1472 08:47:03.828490 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1473 08:47:03.834090 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1474 08:47:03.839737 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1475 08:47:03.851076 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1476 08:47:03.856438 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1477 08:47:03.867863 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1478 08:47:03.873326 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1479 08:47:03.884484 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1480 08:47:03.890115 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1481 08:47:03.901384 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1482 08:47:03.906938 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1483 08:47:03.912506 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1484 08:47:03.923752 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1485 08:47:03.929431 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1486 08:47:03.940782 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1487 08:47:03.946279 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1488 08:47:03.957406 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1489 08:47:03.963067 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1490 08:47:03.974178 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1491 08:47:03.979849 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1492 08:47:03.991051 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1493 08:47:03.996670 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1494 08:47:04.007772 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1495 08:47:04.013426 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 pass
1496 08:47:04.018962 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1497 08:47:04.030203 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1498 08:47:04.035845 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1499 08:47:04.046941 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1500 08:47:04.052546 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1501 08:47:04.064024 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1502 08:47:04.069887 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1503 08:47:04.081051 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1504 08:47:04.092178 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1505 08:47:04.103432 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1506 08:47:04.114779 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1507 08:47:04.125480 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1508 08:47:04.136816 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1509 08:47:04.148287 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1510 08:47:04.159410 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1511 08:47:04.165023 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1512 08:47:04.176188 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1513 08:47:04.181941 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1514 08:47:04.192991 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1515 08:47:04.198290 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1516 08:47:04.209321 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1517 08:47:04.214851 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1518 08:47:04.226042 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1519 08:47:04.231753 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1520 08:47:04.242892 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1521 08:47:04.248483 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1522 08:47:04.259685 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1523 08:47:04.265345 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1524 08:47:04.270873 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1525 08:47:04.282077 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1526 08:47:04.287598 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1527 08:47:04.293261 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1528 08:47:04.304515 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1529 08:47:04.315815 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1530 08:47:04.321333 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1531 08:47:04.326808 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1532 08:47:04.337948 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1533 08:47:04.349325 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1534 08:47:04.349587 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1535 08:47:04.360397 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1536 08:47:04.365990 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1537 08:47:04.377279 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1538 08:47:04.382842 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1539 08:47:04.394085 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1540 08:47:04.399602 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1541 08:47:04.410947 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1542 08:47:04.421975 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1543 08:47:04.433223 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1544 08:47:04.438807 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1545 08:47:04.450075 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1546 08:47:04.455722 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1547 08:47:04.461231 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1548 08:47:04.466883 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1549 08:47:04.472452 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1550 08:47:04.478060 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1551 08:47:04.483659 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1552 08:47:04.494829 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1553 08:47:04.500612 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1554 08:47:04.506080 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1555 08:47:04.511708 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1556 08:47:04.517351 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1557 08:47:04.522914 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1558 08:47:04.534077 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1559 08:47:04.534313 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1560 08:47:04.539671 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1561 08:47:04.545234 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1562 08:47:04.550938 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1563 08:47:04.556538 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1564 08:47:04.562082 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1565 08:47:04.567660 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1566 08:47:04.573399 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1567 08:47:04.578862 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1568 08:47:04.584447 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1569 08:47:04.595650 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1570 08:47:04.595883 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1571 08:47:04.601280 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1572 08:47:04.606899 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1573 08:47:04.612463 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1574 08:47:04.618097 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1575 08:47:04.623658 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1576 08:47:04.629301 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1577 08:47:04.634886 dt_test_unprobed_devices_sh_opp-table skip
1578 08:47:04.640500 dt_test_unprobed_devices_sh_soc skip
1579 08:47:04.640729 dt_test_unprobed_devices_sh_sound pass
1580 08:47:04.646064 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1581 08:47:04.651801 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1582 08:47:04.662868 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1583 08:47:04.663110 dt_test_unprobed_devices_sh fail
1584 08:47:04.668632 + ../../utils/send-to-lava.sh ./output/result.txt
1585 08:47:04.674120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1586 08:47:04.674588 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1588 08:47:04.681898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1589 08:47:04.682336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1591 08:47:04.734179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1592 08:47:04.734621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1594 08:47:04.824302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1595 08:47:04.824736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1597 08:47:04.913741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1598 08:47:04.914182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1600 08:47:05.005554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1601 08:47:05.006085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1603 08:47:05.099106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1604 08:47:05.099554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1606 08:47:05.187483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1607 08:47:05.187940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1609 08:47:05.277057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1610 08:47:05.277502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1612 08:47:05.365177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1613 08:47:05.365629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1615 08:47:05.455207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1616 08:47:05.455666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1618 08:47:05.546334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1619 08:47:05.546788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1621 08:47:05.638527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1622 08:47:05.638971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1624 08:47:05.728472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1625 08:47:05.728915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1627 08:47:05.817819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1628 08:47:05.818282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1630 08:47:05.903714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1631 08:47:05.904163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1633 08:47:05.991108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1634 08:47:05.991554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1636 08:47:06.082789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1637 08:47:06.083243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1639 08:47:06.171775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1640 08:47:06.172217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1642 08:47:06.264495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1643 08:47:06.264940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1645 08:47:06.359595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1646 08:47:06.360040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1648 08:47:06.449800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1649 08:47:06.450249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1651 08:47:06.541391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1652 08:47:06.541854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1654 08:47:06.631420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1655 08:47:06.631860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1657 08:47:06.722374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1658 08:47:06.722814 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1660 08:47:06.814026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1661 08:47:06.814481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1663 08:47:06.898239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1664 08:47:06.898678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1666 08:47:06.990469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1667 08:47:06.990913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1669 08:47:07.081989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1670 08:47:07.082433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1672 08:47:07.172858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1673 08:47:07.173296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1675 08:47:07.262421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1676 08:47:07.262836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1678 08:47:07.352936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1679 08:47:07.353376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1681 08:47:07.437772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1682 08:47:07.438368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1684 08:47:07.530806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1685 08:47:07.531167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1687 08:47:07.623075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1688 08:47:07.623434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1690 08:47:07.715155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1691 08:47:07.715539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1693 08:47:07.802804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1694 08:47:07.803191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1696 08:47:07.895395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1697 08:47:07.895798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1699 08:47:07.988779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1700 08:47:07.989226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1702 08:47:08.081917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1703 08:47:08.082359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1705 08:47:08.172633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1706 08:47:08.173073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1708 08:47:08.264527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1709 08:47:08.265037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1711 08:47:08.354826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1712 08:47:08.355277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1714 08:47:08.448278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1715 08:47:08.448716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1717 08:47:08.540530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1718 08:47:08.540970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1720 08:47:08.632170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1721 08:47:08.632614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1723 08:47:08.723000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1724 08:47:08.723444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1726 08:47:08.814393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1727 08:47:08.814837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1729 08:47:08.900920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1730 08:47:08.901361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1732 08:47:08.993627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1733 08:47:08.994076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1735 08:47:09.085515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1736 08:47:09.086014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1738 08:47:09.172682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1739 08:47:09.173129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1741 08:47:09.263771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1742 08:47:09.264307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1744 08:47:09.395767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1745 08:47:09.396220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1747 08:47:09.497361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1748 08:47:09.497827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1750 08:47:09.584714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1751 08:47:09.585156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1753 08:47:09.676519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1754 08:47:09.677037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1756 08:47:09.797324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1757 08:47:09.797750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1759 08:47:09.890094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1760 08:47:09.890518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1762 08:47:09.983501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1763 08:47:09.983923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1765 08:47:10.073925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1766 08:47:10.074355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1768 08:47:10.164365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1769 08:47:10.164807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1771 08:47:10.250177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1772 08:47:10.250602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1774 08:47:10.340600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1775 08:47:10.341016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1777 08:47:10.430955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1778 08:47:10.431380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1780 08:47:10.520572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1781 08:47:10.520990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1783 08:47:10.606807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1784 08:47:10.607230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1786 08:47:10.692454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1787 08:47:10.692872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1789 08:47:10.783546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1790 08:47:10.783981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1792 08:47:10.867537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1793 08:47:10.867954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1795 08:47:10.958564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1796 08:47:10.958988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1798 08:47:11.048959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1799 08:47:11.049389 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1801 08:47:11.139141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1802 08:47:11.139560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1804 08:47:11.229019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1805 08:47:11.229433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1807 08:47:11.322261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1808 08:47:11.322680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1810 08:47:11.412725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1811 08:47:11.413151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1813 08:47:11.502754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1814 08:47:11.503164 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1816 08:47:11.592143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1817 08:47:11.592577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1819 08:47:11.684452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1820 08:47:11.684886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1822 08:47:11.775044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1823 08:47:11.775487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1825 08:47:11.858837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1826 08:47:11.859253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1828 08:47:11.948005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1829 08:47:11.948436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1831 08:47:12.034807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1832 08:47:12.035268 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1834 08:47:12.118116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1835 08:47:12.118553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1837 08:47:12.210483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1838 08:47:12.210927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1840 08:47:12.301455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1841 08:47:12.301904 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1843 08:47:12.395398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1844 08:47:12.395817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1846 08:47:12.702770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1847 08:47:12.703023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1848 08:47:12.703364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1850 08:47:12.703729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1852 08:47:12.706249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1853 08:47:12.706621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1855 08:47:12.762374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1856 08:47:12.762809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1858 08:47:12.853534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1859 08:47:12.853980 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1861 08:47:12.945029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1862 08:47:12.945470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1864 08:47:13.036430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1865 08:47:13.036853 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1867 08:47:13.129349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1868 08:47:13.129808 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1870 08:47:13.221109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1871 08:47:13.221541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1873 08:47:13.311889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1874 08:47:13.312348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1876 08:47:13.405093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1877 08:47:13.405523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1879 08:47:13.495913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1880 08:47:13.496370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1882 08:47:13.586809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1883 08:47:13.587297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1885 08:47:13.677178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1886 08:47:13.677623 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1888 08:47:13.767497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1889 08:47:13.767946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1891 08:47:13.852206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1892 08:47:13.852631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1894 08:47:13.943483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1895 08:47:13.943919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1897 08:47:14.036510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1898 08:47:14.036946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1900 08:47:14.123098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1901 08:47:14.123533 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1903 08:47:14.214317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1904 08:47:14.214748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1906 08:47:14.307486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1907 08:47:14.307905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1909 08:47:14.402924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1910 08:47:14.403359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1912 08:47:14.494289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1913 08:47:14.494717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1915 08:47:14.585638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1916 08:47:14.586068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1918 08:47:14.672003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1919 08:47:14.672424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1921 08:47:14.763985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1922 08:47:14.764441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1924 08:47:14.855337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1925 08:47:14.855780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1927 08:47:14.942227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1928 08:47:14.942666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1930 08:47:15.033998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1931 08:47:15.034423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1933 08:47:15.125746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1934 08:47:15.126185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1936 08:47:15.213389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1937 08:47:15.213831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1939 08:47:15.304634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1940 08:47:15.305069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1942 08:47:15.395054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1943 08:47:15.395514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1945 08:47:15.480515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1947 08:47:15.483579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1948 08:47:15.572528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1950 08:47:15.575664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1951 08:47:15.664518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1953 08:47:15.667643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1954 08:47:15.752463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1955 08:47:15.752912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1957 08:47:15.843468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1958 08:47:15.843894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1960 08:47:15.933218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1961 08:47:15.933658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1963 08:47:16.020894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1964 08:47:16.021317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1966 08:47:16.109496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1967 08:47:16.109954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1969 08:47:16.202300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1970 08:47:16.202727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1972 08:47:16.293511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1973 08:47:16.293952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1975 08:47:16.379309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1976 08:47:16.379728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1978 08:47:16.473055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1979 08:47:16.473481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1981 08:47:16.563955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1982 08:47:16.564393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1984 08:47:16.648362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1985 08:47:16.648781 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1987 08:47:16.740452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1988 08:47:16.740854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1990 08:47:16.829585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1991 08:47:16.830035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1993 08:47:16.919656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1994 08:47:16.920079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1996 08:47:17.012697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1997 08:47:17.013101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1999 08:47:17.104977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2000 08:47:17.105408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2002 08:47:17.187768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2003 08:47:17.188196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2005 08:47:17.279652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2006 08:47:17.280143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2008 08:47:17.370694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2009 08:47:17.371148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2011 08:47:17.460860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2012 08:47:17.461289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2014 08:47:17.548368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2015 08:47:17.548782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2017 08:47:17.640112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail>
2018 08:47:17.640573 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail
2020 08:47:17.730475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail>
2021 08:47:17.730963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail
2023 08:47:17.814513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2024 08:47:17.815005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2026 08:47:17.905490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2027 08:47:17.906009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2029 08:47:17.995843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2030 08:47:17.996330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2032 08:47:18.085855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2033 08:47:18.086355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2035 08:47:18.179858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2036 08:47:18.180346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2038 08:47:18.271155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2039 08:47:18.271662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2041 08:47:18.361650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2042 08:47:18.362150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2044 08:47:18.447439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2045 08:47:18.447934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2047 08:47:18.537122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2048 08:47:18.537630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2050 08:47:18.629048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2051 08:47:18.629538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2053 08:47:18.716972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2054 08:47:18.717465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2056 08:47:18.808296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2057 08:47:18.808796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2059 08:47:18.901691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2060 08:47:18.902177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2062 08:47:18.989114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2063 08:47:18.989631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2065 08:47:19.079932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2066 08:47:19.080416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2068 08:47:19.168168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2069 08:47:19.168659 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2071 08:47:19.261138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2072 08:47:19.261690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2074 08:47:19.349800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2075 08:47:19.350317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2077 08:47:19.439717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2078 08:47:19.440206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2080 08:47:19.529368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2081 08:47:19.529975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2083 08:47:19.650963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2084 08:47:19.651303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2086 08:47:19.741087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2087 08:47:19.741594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2089 08:47:19.833311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2090 08:47:19.833852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2092 08:47:19.918075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2093 08:47:19.918582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2095 08:47:20.008639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2096 08:47:20.009128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2098 08:47:20.099130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2099 08:47:20.099648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2101 08:47:20.191155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2102 08:47:20.191644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2104 08:47:20.275206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass>
2105 08:47:20.275702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass
2107 08:47:20.365467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2108 08:47:20.366021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2110 08:47:20.456390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2111 08:47:20.456901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2113 08:47:20.546163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2114 08:47:20.546665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2116 08:47:20.637315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2117 08:47:20.637843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2119 08:47:20.723854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2120 08:47:20.724357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2122 08:47:20.816222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2123 08:47:20.816723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2125 08:47:20.901733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2126 08:47:20.902205 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2128 08:47:20.996170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2129 08:47:20.996663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2131 08:47:21.086574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2132 08:47:21.087084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2134 08:47:21.176259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2135 08:47:21.176742 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2137 08:47:21.269282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2138 08:47:21.269819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2140 08:47:21.357250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2141 08:47:21.357757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2143 08:47:21.443178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2144 08:47:21.443667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2146 08:47:21.531040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2147 08:47:21.531528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2149 08:47:21.622615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2150 08:47:21.623097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2152 08:47:21.707879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2153 08:47:21.708368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2155 08:47:21.799025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2156 08:47:21.799534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2158 08:47:21.889130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2159 08:47:21.889636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2161 08:47:21.980801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2162 08:47:21.981291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2164 08:47:22.071626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2165 08:47:22.072105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2167 08:47:22.161345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2168 08:47:22.161907 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2170 08:47:22.249962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2171 08:47:22.250456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2173 08:47:22.340392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2174 08:47:22.340870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2176 08:47:22.429582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2177 08:47:22.430091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2179 08:47:22.519607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2180 08:47:22.520085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2182 08:47:22.611779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2183 08:47:22.612266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2185 08:47:22.699867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2186 08:47:22.700345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2188 08:47:22.788179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2189 08:47:22.788676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2191 08:47:22.879471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2192 08:47:22.879950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2194 08:47:22.969445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2195 08:47:22.969966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2197 08:47:23.060597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2198 08:47:23.061103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2200 08:47:23.153994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2201 08:47:23.154466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2203 08:47:23.247304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2204 08:47:23.247802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2206 08:47:23.338916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2207 08:47:23.339414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2209 08:47:23.429292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2210 08:47:23.429944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2212 08:47:23.519928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2213 08:47:23.520423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2215 08:47:23.610029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2216 08:47:23.610519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2218 08:47:23.695980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2219 08:47:23.696459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2221 08:47:23.777855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2222 08:47:23.778343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2224 08:47:23.869636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2225 08:47:23.870123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2227 08:47:23.958133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2228 08:47:23.958619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2230 08:47:24.050379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2231 08:47:24.050867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2233 08:47:24.143069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2234 08:47:24.143562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2236 08:47:24.231156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2237 08:47:24.231644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2239 08:47:24.321741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2240 08:47:24.322234 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2242 08:47:24.413988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2243 08:47:24.414478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2245 08:47:24.501446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2246 08:47:24.501951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2248 08:47:24.589323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2249 08:47:24.589823 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2251 08:47:24.679564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2252 08:47:24.680053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2254 08:47:24.770558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2255 08:47:24.771041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2257 08:47:24.856357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2258 08:47:24.856828 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2260 08:47:24.951063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2261 08:47:24.951547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2263 08:47:25.035919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2264 08:47:25.036398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2266 08:47:25.124929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2267 08:47:25.125395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2269 08:47:25.216915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2270 08:47:25.217400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2272 08:47:25.310205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2273 08:47:25.310726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2275 08:47:25.398065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2277 08:47:25.401288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2278 08:47:25.489822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2279 08:47:25.490318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2281 08:47:25.577294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2282 08:47:25.577785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2284 08:47:25.665887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2285 08:47:25.666371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2287 08:47:25.757678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2288 08:47:25.758174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2290 08:47:25.845439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2291 08:47:25.845947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2293 08:47:25.935265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2294 08:47:25.935758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2296 08:47:26.023209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2297 08:47:26.023706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2299 08:47:26.112226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2300 08:47:26.112718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2302 08:47:26.196421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2303 08:47:26.196903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2305 08:47:26.284992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2306 08:47:26.285483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2308 08:47:26.371772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2309 08:47:26.372253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2311 08:47:26.461254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2312 08:47:26.461743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2314 08:47:26.546457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2315 08:47:26.546947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2317 08:47:26.635379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2318 08:47:26.635860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2320 08:47:26.725487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2321 08:47:26.726003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2323 08:47:26.813819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2324 08:47:26.814309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2326 08:47:26.904576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2327 08:47:26.905065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2329 08:47:26.996342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2330 08:47:26.996823 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2332 08:47:27.085677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2333 08:47:27.086170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2335 08:47:27.175399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2336 08:47:27.175910 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2338 08:47:27.265232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2339 08:47:27.265725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2341 08:47:27.353746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2342 08:47:27.354237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2344 08:47:27.443283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2345 08:47:27.443767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2347 08:47:27.536325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2348 08:47:27.536807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2350 08:47:27.623594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2351 08:47:27.624110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2353 08:47:27.712453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2354 08:47:27.712944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2356 08:47:27.803042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2357 08:47:27.803525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2359 08:47:27.895689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2360 08:47:27.896172 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2362 08:47:27.989952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2363 08:47:27.990438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2365 08:47:28.080124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2366 08:47:28.080596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2368 08:47:28.169918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2369 08:47:28.170205 + set +x
2370 08:47:28.170574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2372 08:47:28.179255 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 676553_1.6.2.4.5>
2373 08:47:28.179483 <LAVA_TEST_RUNNER EXIT>
2374 08:47:28.179841 Received signal: <ENDRUN> 1_kselftest-dt 676553_1.6.2.4.5
2375 08:47:28.180007 Ending use of test pattern.
2376 08:47:28.180150 Ending test lava.1_kselftest-dt (676553_1.6.2.4.5), duration 75.87
2378 08:47:28.180684 ok: lava_test_shell seems to have completed
2379 08:47:28.184644 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2380 08:47:28.185432 end: 3.1 lava-test-shell (duration 00:01:17) [common]
2381 08:47:28.185654 end: 3 lava-test-retry (duration 00:01:17) [common]
2382 08:47:28.185864 start: 4 finalize (timeout 00:06:09) [common]
2383 08:47:28.186067 start: 4.1 power-off (timeout 00:00:30) [common]
2384 08:47:28.186430 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2385 08:47:28.206476 >> OK - accepted request
2386 08:47:28.208376 Returned 0 in 0 seconds
2387 08:47:28.309213 end: 4.1 power-off (duration 00:00:00) [common]
2389 08:47:28.309976 start: 4.2 read-feedback (timeout 00:06:09) [common]
2390 08:47:28.310558 Listened to connection for namespace 'common' for up to 1s
2391 08:47:29.311424 Finalising connection for namespace 'common'
2392 08:47:29.311781 Disconnecting from shell: Finalise
2393 08:47:29.311987 / #
2394 08:47:29.412500 end: 4.2 read-feedback (duration 00:00:01) [common]
2395 08:47:29.412867 end: 4 finalize (duration 00:00:01) [common]
2396 08:47:29.413131 Cleaning after the job
2397 08:47:29.413369 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676553/tftp-deploy-sxbex86h/ramdisk
2398 08:47:29.421150 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676553/tftp-deploy-sxbex86h/kernel
2399 08:47:29.427263 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676553/tftp-deploy-sxbex86h/dtb
2400 08:47:29.427765 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676553/tftp-deploy-sxbex86h/nfsrootfs
2401 08:47:29.539738 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676553/tftp-deploy-sxbex86h/modules
2402 08:47:29.545735 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/676553
2403 08:47:30.500931 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/676553
2404 08:47:30.501147 Job finished correctly