Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 08:30:35.207548 lava-dispatcher, installed at version: 2024.01
2 08:30:35.208367 start: 0 validate
3 08:30:35.208857 Start time: 2024-08-30 08:30:35.208827+00:00 (UTC)
4 08:30:35.209402 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:30:35.209950 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 08:30:35.246824 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:30:35.247473 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240830%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 08:30:35.275571 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:30:35.276242 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240830%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 08:30:36.327122 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:30:36.327666 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240830%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 08:30:36.369430 validate duration: 1.16
14 08:30:36.370278 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 08:30:36.370618 start: 1.1 download-retry (timeout 00:10:00) [common]
16 08:30:36.370926 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 08:30:36.371499 Not decompressing ramdisk as can be used compressed.
18 08:30:36.371957 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 08:30:36.372235 saving as /var/lib/lava/dispatcher/tmp/676515/tftp-deploy-l232m17b/ramdisk/rootfs.cpio.gz
20 08:30:36.372499 total size: 8181887 (7 MB)
21 08:30:36.411723 progress 0 % (0 MB)
22 08:30:36.422901 progress 5 % (0 MB)
23 08:30:36.433359 progress 10 % (0 MB)
24 08:30:36.440499 progress 15 % (1 MB)
25 08:30:36.445957 progress 20 % (1 MB)
26 08:30:36.451839 progress 25 % (1 MB)
27 08:30:36.457207 progress 30 % (2 MB)
28 08:30:36.462963 progress 35 % (2 MB)
29 08:30:36.468372 progress 40 % (3 MB)
30 08:30:36.474102 progress 45 % (3 MB)
31 08:30:36.479472 progress 50 % (3 MB)
32 08:30:36.485219 progress 55 % (4 MB)
33 08:30:36.490571 progress 60 % (4 MB)
34 08:30:36.496387 progress 65 % (5 MB)
35 08:30:36.501739 progress 70 % (5 MB)
36 08:30:36.507640 progress 75 % (5 MB)
37 08:30:36.512989 progress 80 % (6 MB)
38 08:30:36.518709 progress 85 % (6 MB)
39 08:30:36.524030 progress 90 % (7 MB)
40 08:30:36.529816 progress 95 % (7 MB)
41 08:30:36.534845 progress 100 % (7 MB)
42 08:30:36.535503 7 MB downloaded in 0.16 s (47.88 MB/s)
43 08:30:36.536081 end: 1.1.1 http-download (duration 00:00:00) [common]
45 08:30:36.537000 end: 1.1 download-retry (duration 00:00:00) [common]
46 08:30:36.537306 start: 1.2 download-retry (timeout 00:10:00) [common]
47 08:30:36.537592 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 08:30:36.538081 downloading http://storage.kernelci.org/next/master/next-20240830/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/kernel/Image
49 08:30:36.538334 saving as /var/lib/lava/dispatcher/tmp/676515/tftp-deploy-l232m17b/kernel/Image
50 08:30:36.538551 total size: 47280640 (45 MB)
51 08:30:36.538771 No compression specified
52 08:30:36.571818 progress 0 % (0 MB)
53 08:30:36.601422 progress 5 % (2 MB)
54 08:30:36.631009 progress 10 % (4 MB)
55 08:30:36.660013 progress 15 % (6 MB)
56 08:30:36.689582 progress 20 % (9 MB)
57 08:30:36.718930 progress 25 % (11 MB)
58 08:30:36.748489 progress 30 % (13 MB)
59 08:30:36.778232 progress 35 % (15 MB)
60 08:30:36.807765 progress 40 % (18 MB)
61 08:30:36.836968 progress 45 % (20 MB)
62 08:30:36.865776 progress 50 % (22 MB)
63 08:30:36.894853 progress 55 % (24 MB)
64 08:30:36.924309 progress 60 % (27 MB)
65 08:30:36.953540 progress 65 % (29 MB)
66 08:30:36.982723 progress 70 % (31 MB)
67 08:30:37.011676 progress 75 % (33 MB)
68 08:30:37.040620 progress 80 % (36 MB)
69 08:30:37.069651 progress 85 % (38 MB)
70 08:30:37.098230 progress 90 % (40 MB)
71 08:30:37.127168 progress 95 % (42 MB)
72 08:30:37.155629 progress 100 % (45 MB)
73 08:30:37.156441 45 MB downloaded in 0.62 s (72.98 MB/s)
74 08:30:37.156938 end: 1.2.1 http-download (duration 00:00:01) [common]
76 08:30:37.157766 end: 1.2 download-retry (duration 00:00:01) [common]
77 08:30:37.158044 start: 1.3 download-retry (timeout 00:09:59) [common]
78 08:30:37.158310 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 08:30:37.158782 downloading http://storage.kernelci.org/next/master/next-20240830/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 08:30:37.159062 saving as /var/lib/lava/dispatcher/tmp/676515/tftp-deploy-l232m17b/dtb/meson-g12b-a311d-libretech-cc.dtb
81 08:30:37.159272 total size: 54667 (0 MB)
82 08:30:37.159483 No compression specified
83 08:30:37.200724 progress 59 % (0 MB)
84 08:30:37.201583 progress 100 % (0 MB)
85 08:30:37.202145 0 MB downloaded in 0.04 s (1.22 MB/s)
86 08:30:37.202611 end: 1.3.1 http-download (duration 00:00:00) [common]
88 08:30:37.203439 end: 1.3 download-retry (duration 00:00:00) [common]
89 08:30:37.203704 start: 1.4 download-retry (timeout 00:09:59) [common]
90 08:30:37.203971 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 08:30:37.204487 downloading http://storage.kernelci.org/next/master/next-20240830/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/modules.tar.xz
92 08:30:37.204730 saving as /var/lib/lava/dispatcher/tmp/676515/tftp-deploy-l232m17b/modules/modules.tar
93 08:30:37.204937 total size: 11541008 (11 MB)
94 08:30:37.205149 Using unxz to decompress xz
95 08:30:37.239437 progress 0 % (0 MB)
96 08:30:37.305461 progress 5 % (0 MB)
97 08:30:37.390296 progress 10 % (1 MB)
98 08:30:37.472906 progress 15 % (1 MB)
99 08:30:37.558866 progress 20 % (2 MB)
100 08:30:37.637240 progress 25 % (2 MB)
101 08:30:37.711343 progress 30 % (3 MB)
102 08:30:37.788226 progress 35 % (3 MB)
103 08:30:37.864495 progress 40 % (4 MB)
104 08:30:37.946833 progress 45 % (4 MB)
105 08:30:38.026372 progress 50 % (5 MB)
106 08:30:38.106702 progress 55 % (6 MB)
107 08:30:38.186331 progress 60 % (6 MB)
108 08:30:38.266711 progress 65 % (7 MB)
109 08:30:38.347148 progress 70 % (7 MB)
110 08:30:38.430771 progress 75 % (8 MB)
111 08:30:38.521883 progress 80 % (8 MB)
112 08:30:38.621622 progress 85 % (9 MB)
113 08:30:38.692179 progress 90 % (9 MB)
114 08:30:38.771866 progress 95 % (10 MB)
115 08:30:38.847952 progress 100 % (11 MB)
116 08:30:38.860064 11 MB downloaded in 1.66 s (6.65 MB/s)
117 08:30:38.861052 end: 1.4.1 http-download (duration 00:00:02) [common]
119 08:30:38.862657 end: 1.4 download-retry (duration 00:00:02) [common]
120 08:30:38.863177 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 08:30:38.863692 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 08:30:38.864214 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 08:30:38.864717 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 08:30:38.865696 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1
125 08:30:38.866562 makedir: /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin
126 08:30:38.867241 makedir: /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/tests
127 08:30:38.867865 makedir: /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/results
128 08:30:38.868515 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-add-keys
129 08:30:38.869471 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-add-sources
130 08:30:38.870415 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-background-process-start
131 08:30:38.871382 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-background-process-stop
132 08:30:38.872434 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-common-functions
133 08:30:38.873378 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-echo-ipv4
134 08:30:38.874304 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-install-packages
135 08:30:38.875253 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-installed-packages
136 08:30:38.876207 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-os-build
137 08:30:38.877138 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-probe-channel
138 08:30:38.878077 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-probe-ip
139 08:30:38.879015 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-target-ip
140 08:30:38.879948 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-target-mac
141 08:30:38.880936 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-target-storage
142 08:30:38.881883 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-test-case
143 08:30:38.882818 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-test-event
144 08:30:38.883724 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-test-feedback
145 08:30:38.884701 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-test-raise
146 08:30:38.885614 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-test-reference
147 08:30:38.886521 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-test-runner
148 08:30:38.887416 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-test-set
149 08:30:38.888383 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-test-shell
150 08:30:38.889331 Updating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-install-packages (oe)
151 08:30:38.890375 Updating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/bin/lava-installed-packages (oe)
152 08:30:38.891261 Creating /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/environment
153 08:30:38.892029 LAVA metadata
154 08:30:38.892525 - LAVA_JOB_ID=676515
155 08:30:38.892951 - LAVA_DISPATCHER_IP=192.168.6.2
156 08:30:38.893633 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 08:30:38.895679 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 08:30:38.896328 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 08:30:38.896747 skipped lava-vland-overlay
160 08:30:38.897238 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 08:30:38.897746 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 08:30:38.898177 skipped lava-multinode-overlay
163 08:30:38.898661 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 08:30:38.899166 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 08:30:38.899646 Loading test definitions
166 08:30:38.900221 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 08:30:38.900667 Using /lava-676515 at stage 0
168 08:30:38.902951 uuid=676515_1.5.2.4.1 testdef=None
169 08:30:38.903537 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 08:30:38.904086 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 08:30:38.907528 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 08:30:38.909134 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 08:30:38.913520 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 08:30:38.915186 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 08:30:38.917981 runner path: /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/0/tests/0_dmesg test_uuid 676515_1.5.2.4.1
178 08:30:38.918597 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 08:30:38.919384 Creating lava-test-runner.conf files
181 08:30:38.919591 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/676515/lava-overlay-7o17rsx1/lava-676515/0 for stage 0
182 08:30:38.919957 - 0_dmesg
183 08:30:38.920355 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 08:30:38.920642 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 08:30:38.944676 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 08:30:38.945122 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 08:30:38.945391 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 08:30:38.945664 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 08:30:38.945932 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 08:30:39.875969 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 08:30:39.876731 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 08:30:39.877203 extracting modules file /var/lib/lava/dispatcher/tmp/676515/tftp-deploy-l232m17b/modules/modules.tar to /var/lib/lava/dispatcher/tmp/676515/extract-overlay-ramdisk-9bpe32d9/ramdisk
193 08:30:41.241816 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 08:30:41.242299 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 08:30:41.242579 [common] Applying overlay /var/lib/lava/dispatcher/tmp/676515/compress-overlay-xb3ghuxc/overlay-1.5.2.5.tar.gz to ramdisk
196 08:30:41.242793 [common] Applying overlay /var/lib/lava/dispatcher/tmp/676515/compress-overlay-xb3ghuxc/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/676515/extract-overlay-ramdisk-9bpe32d9/ramdisk
197 08:30:41.273271 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 08:30:41.273709 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 08:30:41.273981 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 08:30:41.274213 Converting downloaded kernel to a uImage
201 08:30:41.274520 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/676515/tftp-deploy-l232m17b/kernel/Image /var/lib/lava/dispatcher/tmp/676515/tftp-deploy-l232m17b/kernel/uImage
202 08:30:41.789447 output: Image Name:
203 08:30:41.789868 output: Created: Fri Aug 30 08:30:41 2024
204 08:30:41.790077 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 08:30:41.790281 output: Data Size: 47280640 Bytes = 46172.50 KiB = 45.09 MiB
206 08:30:41.790481 output: Load Address: 01080000
207 08:30:41.790676 output: Entry Point: 01080000
208 08:30:41.790873 output:
209 08:30:41.791204 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 08:30:41.791470 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 08:30:41.791738 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 08:30:41.792025 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 08:30:41.792295 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 08:30:41.792553 Building ramdisk /var/lib/lava/dispatcher/tmp/676515/extract-overlay-ramdisk-9bpe32d9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/676515/extract-overlay-ramdisk-9bpe32d9/ramdisk
215 08:30:44.164851 >> 180822 blocks
216 08:30:52.582050 Adding RAMdisk u-boot header.
217 08:30:52.582490 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/676515/extract-overlay-ramdisk-9bpe32d9/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/676515/extract-overlay-ramdisk-9bpe32d9/ramdisk.cpio.gz.uboot
218 08:30:52.873322 output: Image Name:
219 08:30:52.873991 output: Created: Fri Aug 30 08:30:52 2024
220 08:30:52.874463 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 08:30:52.874925 output: Data Size: 25953635 Bytes = 25345.35 KiB = 24.75 MiB
222 08:30:52.875378 output: Load Address: 00000000
223 08:30:52.875823 output: Entry Point: 00000000
224 08:30:52.876332 output:
225 08:30:52.877479 rename /var/lib/lava/dispatcher/tmp/676515/extract-overlay-ramdisk-9bpe32d9/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/676515/tftp-deploy-l232m17b/ramdisk/ramdisk.cpio.gz.uboot
226 08:30:52.878256 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 08:30:52.878864 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 08:30:52.879452 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 08:30:52.879959 No LXC device requested
230 08:30:52.880572 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 08:30:52.881151 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 08:30:52.881711 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 08:30:52.882177 Checking files for TFTP limit of 4294967296 bytes.
234 08:30:52.885128 end: 1 tftp-deploy (duration 00:00:17) [common]
235 08:30:52.885765 start: 2 uboot-action (timeout 00:05:00) [common]
236 08:30:52.886360 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 08:30:52.886924 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 08:30:52.887495 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 08:30:52.888120 Using kernel file from prepare-kernel: 676515/tftp-deploy-l232m17b/kernel/uImage
240 08:30:52.888836 substitutions:
241 08:30:52.889307 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 08:30:52.889763 - {DTB_ADDR}: 0x01070000
243 08:30:52.890210 - {DTB}: 676515/tftp-deploy-l232m17b/dtb/meson-g12b-a311d-libretech-cc.dtb
244 08:30:52.890659 - {INITRD}: 676515/tftp-deploy-l232m17b/ramdisk/ramdisk.cpio.gz.uboot
245 08:30:52.891101 - {KERNEL_ADDR}: 0x01080000
246 08:30:52.891536 - {KERNEL}: 676515/tftp-deploy-l232m17b/kernel/uImage
247 08:30:52.891976 - {LAVA_MAC}: None
248 08:30:52.892492 - {PRESEED_CONFIG}: None
249 08:30:52.892941 - {PRESEED_LOCAL}: None
250 08:30:52.893382 - {RAMDISK_ADDR}: 0x08000000
251 08:30:52.893816 - {RAMDISK}: 676515/tftp-deploy-l232m17b/ramdisk/ramdisk.cpio.gz.uboot
252 08:30:52.894258 - {ROOT_PART}: None
253 08:30:52.894695 - {ROOT}: None
254 08:30:52.895133 - {SERVER_IP}: 192.168.6.2
255 08:30:52.895573 - {TEE_ADDR}: 0x83000000
256 08:30:52.896031 - {TEE}: None
257 08:30:52.896478 Parsed boot commands:
258 08:30:52.896902 - setenv autoload no
259 08:30:52.897338 - setenv initrd_high 0xffffffff
260 08:30:52.897772 - setenv fdt_high 0xffffffff
261 08:30:52.898206 - dhcp
262 08:30:52.898638 - setenv serverip 192.168.6.2
263 08:30:52.899072 - tftpboot 0x01080000 676515/tftp-deploy-l232m17b/kernel/uImage
264 08:30:52.899508 - tftpboot 0x08000000 676515/tftp-deploy-l232m17b/ramdisk/ramdisk.cpio.gz.uboot
265 08:30:52.899941 - tftpboot 0x01070000 676515/tftp-deploy-l232m17b/dtb/meson-g12b-a311d-libretech-cc.dtb
266 08:30:52.900401 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 08:30:52.900845 - bootm 0x01080000 0x08000000 0x01070000
268 08:30:52.901402 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 08:30:52.903066 start: 2.3 connect-device (timeout 00:05:00) [common]
271 08:30:52.903565 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 08:30:52.918774 Setting prompt string to ['lava-test: # ']
273 08:30:52.920394 end: 2.3 connect-device (duration 00:00:00) [common]
274 08:30:52.921105 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 08:30:52.921746 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 08:30:52.922451 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 08:30:52.923767 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 08:30:52.960953 >> OK - accepted request
279 08:30:52.962966 Returned 0 in 0 seconds
280 08:30:53.064182 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 08:30:53.065971 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 08:30:53.066598 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 08:30:53.067149 Setting prompt string to ['Hit any key to stop autoboot']
285 08:30:53.067651 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 08:30:53.069404 Trying 192.168.56.21...
287 08:30:53.069923 Connected to conserv1.
288 08:30:53.070386 Escape character is '^]'.
289 08:30:53.070848
290 08:30:53.071317 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 08:30:53.071789
292 08:31:03.686560 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
293 08:31:03.687008 bl2_stage_init 0x81
294 08:31:03.692161 hw id: 0x0000 - pwm id 0x01
295 08:31:03.692545 bl2_stage_init 0xc1
296 08:31:03.692761 bl2_stage_init 0x02
297 08:31:03.692966
298 08:31:03.697568 L0:00000000
299 08:31:03.698031 L1:20000703
300 08:31:03.698448 L2:00008067
301 08:31:03.698842 L3:14000000
302 08:31:03.699231 B2:00402000
303 08:31:03.703222 B1:e0f83180
304 08:31:03.703784
305 08:31:03.704275 TE: 58150
306 08:31:03.704722
307 08:31:03.708778 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
308 08:31:03.709115
309 08:31:03.709325 Board ID = 1
310 08:31:03.714537 Set A53 clk to 24M
311 08:31:03.715139 Set A73 clk to 24M
312 08:31:03.715633 Set clk81 to 24M
313 08:31:03.720115 A53 clk: 1200 MHz
314 08:31:03.720639 A73 clk: 1200 MHz
315 08:31:03.721077 CLK81: 166.6M
316 08:31:03.721473 smccc: 00012aac
317 08:31:03.725677 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
318 08:31:03.731272 board id: 1
319 08:31:03.737111 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
320 08:31:03.747540 fw parse done
321 08:31:03.753523 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
322 08:31:03.796208 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
323 08:31:03.807051 PIEI prepare done
324 08:31:03.807565 fastboot data load
325 08:31:03.808037 fastboot data verify
326 08:31:03.812815 verify result: 266
327 08:31:03.818409 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
328 08:31:03.818967 LPDDR4 probe
329 08:31:03.819431 ddr clk to 1584MHz
330 08:31:03.826437 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
331 08:31:03.863680
332 08:31:03.864349 dmc_version 0001
333 08:31:03.870362 Check phy result
334 08:31:03.876307 INFO : End of CA training
335 08:31:03.876855 INFO : End of initialization
336 08:31:03.881893 INFO : Training has run successfully!
337 08:31:03.882454 Check phy result
338 08:31:03.887462 INFO : End of initialization
339 08:31:03.888017 INFO : End of read enable training
340 08:31:03.893033 INFO : End of fine write leveling
341 08:31:03.898649 INFO : End of Write leveling coarse delay
342 08:31:03.899197 INFO : Training has run successfully!
343 08:31:03.899658 Check phy result
344 08:31:03.904280 INFO : End of initialization
345 08:31:03.904873 INFO : End of read dq deskew training
346 08:31:03.909886 INFO : End of MPR read delay center optimization
347 08:31:03.915469 INFO : End of write delay center optimization
348 08:31:03.921562 INFO : End of read delay center optimization
349 08:31:03.921952 INFO : End of max read latency training
350 08:31:03.926667 INFO : Training has run successfully!
351 08:31:03.927326 1D training succeed
352 08:31:03.935799 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
353 08:31:03.983477 Check phy result
354 08:31:03.984241 INFO : End of initialization
355 08:31:04.005204 INFO : End of 2D read delay Voltage center optimization
356 08:31:04.025302 INFO : End of 2D read delay Voltage center optimization
357 08:31:04.076495 INFO : End of 2D write delay Voltage center optimization
358 08:31:04.126928 INFO : End of 2D write delay Voltage center optimization
359 08:31:04.133532 INFO : Training has run successfully!
360 08:31:04.133923
361 08:31:04.134327 channel==0
362 08:31:04.138550 RxClkDly_Margin_A0==88 ps 9
363 08:31:04.139618 TxDqDly_Margin_A0==98 ps 10
364 08:31:04.141306 RxClkDly_Margin_A1==88 ps 9
365 08:31:04.141905 TxDqDly_Margin_A1==98 ps 10
366 08:31:04.147282 TrainedVREFDQ_A0==74
367 08:31:04.148034 TrainedVREFDQ_A1==74
368 08:31:04.148496 VrefDac_Margin_A0==25
369 08:31:04.152638 DeviceVref_Margin_A0==40
370 08:31:04.153437 VrefDac_Margin_A1==25
371 08:31:04.158228 DeviceVref_Margin_A1==40
372 08:31:04.159078
373 08:31:04.159714
374 08:31:04.160636 channel==1
375 08:31:04.161156 RxClkDly_Margin_A0==98 ps 10
376 08:31:04.163750 TxDqDly_Margin_A0==98 ps 10
377 08:31:04.164166 RxClkDly_Margin_A1==98 ps 10
378 08:31:04.169434 TxDqDly_Margin_A1==98 ps 10
379 08:31:04.169859 TrainedVREFDQ_A0==77
380 08:31:04.170135 TrainedVREFDQ_A1==77
381 08:31:04.175146 VrefDac_Margin_A0==22
382 08:31:04.175563 DeviceVref_Margin_A0==37
383 08:31:04.180416 VrefDac_Margin_A1==24
384 08:31:04.181023 DeviceVref_Margin_A1==37
385 08:31:04.181435
386 08:31:04.186115 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
387 08:31:04.186693
388 08:31:04.214168 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
389 08:31:04.219731 2D training succeed
390 08:31:04.225387 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
391 08:31:04.225861 auto size-- 65535DDR cs0 size: 2048MB
392 08:31:04.231014 DDR cs1 size: 2048MB
393 08:31:04.231491 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
394 08:31:04.236586 cs0 DataBus test pass
395 08:31:04.237039 cs1 DataBus test pass
396 08:31:04.237441 cs0 AddrBus test pass
397 08:31:04.241957 cs1 AddrBus test pass
398 08:31:04.242449
399 08:31:04.242857 100bdlr_step_size ps== 420
400 08:31:04.243267 result report
401 08:31:04.252451 boot times 0Enable ddr reg access
402 08:31:04.255483 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
403 08:31:04.269341 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
404 08:31:04.842474 0.0;M3 CHK:0;cm4_sp_mode 0
405 08:31:04.843120 MVN_1=0x00000000
406 08:31:04.847955 MVN_2=0x00000000
407 08:31:04.853672 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
408 08:31:04.854139 OPS=0x10
409 08:31:04.854561 ring efuse init
410 08:31:04.854987 chipver efuse init
411 08:31:04.861930 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
412 08:31:04.862469 [0.018961 Inits done]
413 08:31:04.871448 secure task start!
414 08:31:04.871926 high task start!
415 08:31:04.872381 low task start!
416 08:31:04.872791 run into bl31
417 08:31:04.876284 NOTICE: BL31: v1.3(release):4fc40b1
418 08:31:04.884088 NOTICE: BL31: Built : 15:58:17, May 22 2019
419 08:31:04.884586 NOTICE: BL31: G12A normal boot!
420 08:31:04.909409 NOTICE: BL31: BL33 decompress pass
421 08:31:04.914906 ERROR: Error initializing runtime service opteed_fast
422 08:31:06.147908
423 08:31:06.148371
424 08:31:06.156333 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
425 08:31:06.156759
426 08:31:06.157084 Model: Libre Computer AML-A311D-CC Alta
427 08:31:06.364964 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
428 08:31:06.388097 DRAM: 2 GiB (effective 3.8 GiB)
429 08:31:06.531326 Core: 408 devices, 31 uclasses, devicetree: separate
430 08:31:06.537074 WDT: Not starting watchdog@f0d0
431 08:31:06.569480 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
432 08:31:06.581749 Loading Environment from FAT... Card did not respond to voltage select! : -110
433 08:31:06.585690 ** Bad device specification mmc 0 **
434 08:31:06.597032 Card did not respond to voltage select! : -110
435 08:31:06.604646 ** Bad device specification mmc 0 **
436 08:31:06.604976 Couldn't find partition mmc 0
437 08:31:06.613023 Card did not respond to voltage select! : -110
438 08:31:06.618490 ** Bad device specification mmc 0 **
439 08:31:06.618916 Couldn't find partition mmc 0
440 08:31:06.623523 Error: could not access storage.
441 08:31:07.886770 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
442 08:31:07.887203 bl2_stage_init 0x81
443 08:31:07.892325 hw id: 0x0000 - pwm id 0x01
444 08:31:07.892768 bl2_stage_init 0xc1
445 08:31:07.893106 bl2_stage_init 0x02
446 08:31:07.893344
447 08:31:07.897879 L0:00000000
448 08:31:07.898173 L1:20000703
449 08:31:07.898386 L2:00008067
450 08:31:07.898590 L3:14000000
451 08:31:07.898803 B2:00402000
452 08:31:07.900684 B1:e0f83180
453 08:31:07.901067
454 08:31:07.901390 TE: 58150
455 08:31:07.901709
456 08:31:07.911882 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
457 08:31:07.912216
458 08:31:07.912448 Board ID = 1
459 08:31:07.912655 Set A53 clk to 24M
460 08:31:07.912857 Set A73 clk to 24M
461 08:31:07.917549 Set clk81 to 24M
462 08:31:07.917853 A53 clk: 1200 MHz
463 08:31:07.918065 A73 clk: 1200 MHz
464 08:31:07.923077 CLK81: 166.6M
465 08:31:07.923362 smccc: 00012aab
466 08:31:07.928666 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
467 08:31:07.928953 board id: 1
468 08:31:07.937270 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
469 08:31:07.947962 fw parse done
470 08:31:07.953905 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
471 08:31:07.996621 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
472 08:31:08.007421 PIEI prepare done
473 08:31:08.007704 fastboot data load
474 08:31:08.007910 fastboot data verify
475 08:31:08.013019 verify result: 266
476 08:31:08.018606 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
477 08:31:08.018909 LPDDR4 probe
478 08:31:08.019122 ddr clk to 1584MHz
479 08:31:08.026634 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
480 08:31:08.063825
481 08:31:08.064359 dmc_version 0001
482 08:31:08.070688 Check phy result
483 08:31:08.076463 INFO : End of CA training
484 08:31:08.076802 INFO : End of initialization
485 08:31:08.082055 INFO : Training has run successfully!
486 08:31:08.082572 Check phy result
487 08:31:08.087677 INFO : End of initialization
488 08:31:08.087961 INFO : End of read enable training
489 08:31:08.093333 INFO : End of fine write leveling
490 08:31:08.098964 INFO : End of Write leveling coarse delay
491 08:31:08.099549 INFO : Training has run successfully!
492 08:31:08.100060 Check phy result
493 08:31:08.104520 INFO : End of initialization
494 08:31:08.104818 INFO : End of read dq deskew training
495 08:31:08.110079 INFO : End of MPR read delay center optimization
496 08:31:08.115691 INFO : End of write delay center optimization
497 08:31:08.121241 INFO : End of read delay center optimization
498 08:31:08.121604 INFO : End of max read latency training
499 08:31:08.126796 INFO : Training has run successfully!
500 08:31:08.127150 1D training succeed
501 08:31:08.136015 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 08:31:08.183872 Check phy result
503 08:31:08.184777 INFO : End of initialization
504 08:31:08.205397 INFO : End of 2D read delay Voltage center optimization
505 08:31:08.224704 INFO : End of 2D read delay Voltage center optimization
506 08:31:08.276440 INFO : End of 2D write delay Voltage center optimization
507 08:31:08.325672 INFO : End of 2D write delay Voltage center optimization
508 08:31:08.331237 INFO : Training has run successfully!
509 08:31:08.331590
510 08:31:08.331814 channel==0
511 08:31:08.336724 RxClkDly_Margin_A0==88 ps 9
512 08:31:08.337073 TxDqDly_Margin_A0==98 ps 10
513 08:31:08.342429 RxClkDly_Margin_A1==88 ps 9
514 08:31:08.343264 TxDqDly_Margin_A1==98 ps 10
515 08:31:08.343965 TrainedVREFDQ_A0==74
516 08:31:08.348016 TrainedVREFDQ_A1==74
517 08:31:08.348632 VrefDac_Margin_A0==25
518 08:31:08.349164 DeviceVref_Margin_A0==40
519 08:31:08.353563 VrefDac_Margin_A1==25
520 08:31:08.353931 DeviceVref_Margin_A1==40
521 08:31:08.354474
522 08:31:08.355015
523 08:31:08.359253 channel==1
524 08:31:08.359599 RxClkDly_Margin_A0==88 ps 9
525 08:31:08.359824 TxDqDly_Margin_A0==98 ps 10
526 08:31:08.364718 RxClkDly_Margin_A1==88 ps 9
527 08:31:08.365063 TxDqDly_Margin_A1==88 ps 9
528 08:31:08.370343 TrainedVREFDQ_A0==77
529 08:31:08.370694 TrainedVREFDQ_A1==77
530 08:31:08.370924 VrefDac_Margin_A0==23
531 08:31:08.375949 DeviceVref_Margin_A0==37
532 08:31:08.376318 VrefDac_Margin_A1==24
533 08:31:08.381548 DeviceVref_Margin_A1==37
534 08:31:08.381910
535 08:31:08.382140 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
536 08:31:08.382356
537 08:31:08.415147 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
538 08:31:08.415553 2D training succeed
539 08:31:08.420718 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
540 08:31:08.426373 auto size-- 65535DDR cs0 size: 2048MB
541 08:31:08.426733 DDR cs1 size: 2048MB
542 08:31:08.431893 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
543 08:31:08.432281 cs0 DataBus test pass
544 08:31:08.437571 cs1 DataBus test pass
545 08:31:08.437923 cs0 AddrBus test pass
546 08:31:08.438154 cs1 AddrBus test pass
547 08:31:08.438369
548 08:31:08.443139 100bdlr_step_size ps== 420
549 08:31:08.443500 result report
550 08:31:08.448714 boot times 0Enable ddr reg access
551 08:31:08.454004 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
552 08:31:08.467421 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
553 08:31:09.039585 0.0;M3 CHK:0;cm4_sp_mode 0
554 08:31:09.040032 MVN_1=0x00000000
555 08:31:09.045086 MVN_2=0x00000000
556 08:31:09.050859 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
557 08:31:09.051439 OPS=0x10
558 08:31:09.051956 ring efuse init
559 08:31:09.052489 chipver efuse init
560 08:31:09.056434 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
561 08:31:09.062039 [0.018961 Inits done]
562 08:31:09.062354 secure task start!
563 08:31:09.062580 high task start!
564 08:31:09.066650 low task start!
565 08:31:09.067185 run into bl31
566 08:31:09.073220 NOTICE: BL31: v1.3(release):4fc40b1
567 08:31:09.081073 NOTICE: BL31: Built : 15:58:17, May 22 2019
568 08:31:09.081611 NOTICE: BL31: G12A normal boot!
569 08:31:09.106487 NOTICE: BL31: BL33 decompress pass
570 08:31:09.111674 ERROR: Error initializing runtime service opteed_fast
571 08:31:10.345367
572 08:31:10.346005
573 08:31:10.353568 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
574 08:31:10.354116
575 08:31:10.354556 Model: Libre Computer AML-A311D-CC Alta
576 08:31:10.561991 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
577 08:31:10.584520 DRAM: 2 GiB (effective 3.8 GiB)
578 08:31:10.728381 Core: 408 devices, 31 uclasses, devicetree: separate
579 08:31:10.734201 WDT: Not starting watchdog@f0d0
580 08:31:10.766409 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
581 08:31:10.779014 Loading Environment from FAT... Card did not respond to voltage select! : -110
582 08:31:10.783928 ** Bad device specification mmc 0 **
583 08:31:10.794122 Card did not respond to voltage select! : -110
584 08:31:10.801860 ** Bad device specification mmc 0 **
585 08:31:10.802388 Couldn't find partition mmc 0
586 08:31:10.810155 Card did not respond to voltage select! : -110
587 08:31:10.815678 ** Bad device specification mmc 0 **
588 08:31:10.816242 Couldn't find partition mmc 0
589 08:31:10.820738 Error: could not access storage.
590 08:31:11.162472 Net: eth0: ethernet@ff3f0000
591 08:31:11.163091 starting USB...
592 08:31:11.415034 Bus usb@ff500000: Register 3000140 NbrPorts 3
593 08:31:11.415647 Starting the controller
594 08:31:11.422112 USB XHCI 1.10
595 08:31:13.136691 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
596 08:31:13.137138 bl2_stage_init 0x81
597 08:31:13.142122 hw id: 0x0000 - pwm id 0x01
598 08:31:13.142527 bl2_stage_init 0xc1
599 08:31:13.142853 bl2_stage_init 0x02
600 08:31:13.143169
601 08:31:13.147823 L0:00000000
602 08:31:13.148128 L1:20000703
603 08:31:13.148344 L2:00008067
604 08:31:13.148549 L3:14000000
605 08:31:13.148751 B2:00402000
606 08:31:13.153334 B1:e0f83180
607 08:31:13.153728
608 08:31:13.154049 TE: 58150
609 08:31:13.154360
610 08:31:13.158953 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
611 08:31:13.159339
612 08:31:13.159655 Board ID = 1
613 08:31:13.164620 Set A53 clk to 24M
614 08:31:13.164996 Set A73 clk to 24M
615 08:31:13.165311 Set clk81 to 24M
616 08:31:13.170097 A53 clk: 1200 MHz
617 08:31:13.170374 A73 clk: 1200 MHz
618 08:31:13.170585 CLK81: 166.6M
619 08:31:13.170789 smccc: 00012aab
620 08:31:13.175722 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
621 08:31:13.181331 board id: 1
622 08:31:13.187187 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
623 08:31:13.197844 fw parse done
624 08:31:13.203917 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
625 08:31:13.246396 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
626 08:31:13.257344 PIEI prepare done
627 08:31:13.257695 fastboot data load
628 08:31:13.258003 fastboot data verify
629 08:31:13.262873 verify result: 266
630 08:31:13.268469 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
631 08:31:13.268850 LPDDR4 probe
632 08:31:13.269173 ddr clk to 1584MHz
633 08:31:13.276471 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
634 08:31:13.313748
635 08:31:13.314103 dmc_version 0001
636 08:31:13.320477 Check phy result
637 08:31:13.326383 INFO : End of CA training
638 08:31:13.326760 INFO : End of initialization
639 08:31:13.331881 INFO : Training has run successfully!
640 08:31:13.332173 Check phy result
641 08:31:13.337484 INFO : End of initialization
642 08:31:13.337759 INFO : End of read enable training
643 08:31:13.340831 INFO : End of fine write leveling
644 08:31:13.346372 INFO : End of Write leveling coarse delay
645 08:31:13.352026 INFO : Training has run successfully!
646 08:31:13.352309 Check phy result
647 08:31:13.352519 INFO : End of initialization
648 08:31:13.357537 INFO : End of read dq deskew training
649 08:31:13.363110 INFO : End of MPR read delay center optimization
650 08:31:13.363491 INFO : End of write delay center optimization
651 08:31:13.368795 INFO : End of read delay center optimization
652 08:31:13.374412 INFO : End of max read latency training
653 08:31:13.374785 INFO : Training has run successfully!
654 08:31:13.380046 1D training succeed
655 08:31:13.385945 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
656 08:31:13.432642 Check phy result
657 08:31:13.433024 INFO : End of initialization
658 08:31:13.455057 INFO : End of 2D read delay Voltage center optimization
659 08:31:13.474348 INFO : End of 2D read delay Voltage center optimization
660 08:31:13.525890 INFO : End of 2D write delay Voltage center optimization
661 08:31:13.576013 INFO : End of 2D write delay Voltage center optimization
662 08:31:13.581503 INFO : Training has run successfully!
663 08:31:13.581811
664 08:31:13.582026 channel==0
665 08:31:13.587133 RxClkDly_Margin_A0==88 ps 9
666 08:31:13.587635 TxDqDly_Margin_A0==98 ps 10
667 08:31:13.592792 RxClkDly_Margin_A1==88 ps 9
668 08:31:13.593553 TxDqDly_Margin_A1==88 ps 9
669 08:31:13.594140 TrainedVREFDQ_A0==74
670 08:31:13.598388 TrainedVREFDQ_A1==74
671 08:31:13.599046 VrefDac_Margin_A0==25
672 08:31:13.599629 DeviceVref_Margin_A0==40
673 08:31:13.603921 VrefDac_Margin_A1==25
674 08:31:13.604615 DeviceVref_Margin_A1==40
675 08:31:13.605175
676 08:31:13.605721
677 08:31:13.606262 channel==1
678 08:31:13.609561 RxClkDly_Margin_A0==98 ps 10
679 08:31:13.610202 TxDqDly_Margin_A0==98 ps 10
680 08:31:13.615091 RxClkDly_Margin_A1==88 ps 9
681 08:31:13.615747 TxDqDly_Margin_A1==98 ps 10
682 08:31:13.620682 TrainedVREFDQ_A0==77
683 08:31:13.621343 TrainedVREFDQ_A1==77
684 08:31:13.621917 VrefDac_Margin_A0==23
685 08:31:13.626384 DeviceVref_Margin_A0==37
686 08:31:13.626978 VrefDac_Margin_A1==24
687 08:31:13.631867 DeviceVref_Margin_A1==37
688 08:31:13.632488
689 08:31:13.633050 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
690 08:31:13.633592
691 08:31:13.665495 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
692 08:31:13.666151 2D training succeed
693 08:31:13.671152 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
694 08:31:13.676673 auto size-- 65535DDR cs0 size: 2048MB
695 08:31:13.677270 DDR cs1 size: 2048MB
696 08:31:13.682382 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
697 08:31:13.682970 cs0 DataBus test pass
698 08:31:13.687919 cs1 DataBus test pass
699 08:31:13.688545 cs0 AddrBus test pass
700 08:31:13.689087 cs1 AddrBus test pass
701 08:31:13.689621
702 08:31:13.693493 100bdlr_step_size ps== 420
703 08:31:13.694088 result report
704 08:31:13.699088 boot times 0Enable ddr reg access
705 08:31:13.703883 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
706 08:31:13.717999 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
707 08:31:14.291870 0.0;M3 CHK:0;cm4_sp_mode 0
708 08:31:14.292509 MVN_1=0x00000000
709 08:31:14.297320 MVN_2=0x00000000
710 08:31:14.303021 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
711 08:31:14.303616 OPS=0x10
712 08:31:14.304105 ring efuse init
713 08:31:14.304550 chipver efuse init
714 08:31:14.311133 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
715 08:31:14.311718 [0.018961 Inits done]
716 08:31:14.318446 secure task start!
717 08:31:14.318988 high task start!
718 08:31:14.319431 low task start!
719 08:31:14.319862 run into bl31
720 08:31:14.325297 NOTICE: BL31: v1.3(release):4fc40b1
721 08:31:14.332377 NOTICE: BL31: Built : 15:58:17, May 22 2019
722 08:31:14.332918 NOTICE: BL31: G12A normal boot!
723 08:31:14.358522 NOTICE: BL31: BL33 decompress pass
724 08:31:14.364046 ERROR: Error initializing runtime service opteed_fast
725 08:31:15.597041
726 08:31:15.597689
727 08:31:15.604932 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
728 08:31:15.605468
729 08:31:15.605938 Model: Libre Computer AML-A311D-CC Alta
730 08:31:15.813119 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
731 08:31:15.836407 DRAM: 2 GiB (effective 3.8 GiB)
732 08:31:15.980321 Core: 408 devices, 31 uclasses, devicetree: separate
733 08:31:15.985517 WDT: Not starting watchdog@f0d0
734 08:31:16.018396 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
735 08:31:16.030816 Loading Environment from FAT... Card did not respond to voltage select! : -110
736 08:31:16.034949 ** Bad device specification mmc 0 **
737 08:31:16.046158 Card did not respond to voltage select! : -110
738 08:31:16.053180 ** Bad device specification mmc 0 **
739 08:31:16.053699 Couldn't find partition mmc 0
740 08:31:16.062167 Card did not respond to voltage select! : -110
741 08:31:16.067723 ** Bad device specification mmc 0 **
742 08:31:16.068286 Couldn't find partition mmc 0
743 08:31:16.071859 Error: could not access storage.
744 08:31:16.415790 Net: eth0: ethernet@ff3f0000
745 08:31:16.416441 starting USB...
746 08:31:16.668143 Bus usb@ff500000: Register 3000140 NbrPorts 3
747 08:31:16.668773 Starting the controller
748 08:31:16.674186 USB XHCI 1.10
749 08:31:18.878197 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
750 08:31:18.878575 bl2_stage_init 0x01
751 08:31:18.878791 bl2_stage_init 0x81
752 08:31:18.883806 hw id: 0x0000 - pwm id 0x01
753 08:31:18.884198 bl2_stage_init 0xc1
754 08:31:18.884502 bl2_stage_init 0x02
755 08:31:18.884799
756 08:31:18.889359 L0:00000000
757 08:31:18.889709 L1:20000703
758 08:31:18.889935 L2:00008067
759 08:31:18.890137 L3:14000000
760 08:31:18.894860 B2:00402000
761 08:31:18.895212 B1:e0f83180
762 08:31:18.895508
763 08:31:18.895801 TE: 58159
764 08:31:18.896118
765 08:31:18.900707 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
766 08:31:18.901068
767 08:31:18.901300 Board ID = 1
768 08:31:18.906187 Set A53 clk to 24M
769 08:31:18.906454 Set A73 clk to 24M
770 08:31:18.906662 Set clk81 to 24M
771 08:31:18.911863 A53 clk: 1200 MHz
772 08:31:18.912234 A73 clk: 1200 MHz
773 08:31:18.912568 CLK81: 166.6M
774 08:31:18.912880 smccc: 00012ab5
775 08:31:18.917358 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
776 08:31:18.922969 board id: 1
777 08:31:18.928131 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
778 08:31:18.939402 fw parse done
779 08:31:18.944497 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
780 08:31:18.987062 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
781 08:31:18.998904 PIEI prepare done
782 08:31:18.999173 fastboot data load
783 08:31:18.999390 fastboot data verify
784 08:31:19.004523 verify result: 266
785 08:31:19.010078 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
786 08:31:19.010443 LPDDR4 probe
787 08:31:19.010760 ddr clk to 1584MHz
788 08:31:19.017808 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
789 08:31:19.054450
790 08:31:19.054730 dmc_version 0001
791 08:31:19.061383 Check phy result
792 08:31:19.068014 INFO : End of CA training
793 08:31:19.068291 INFO : End of initialization
794 08:31:19.073563 INFO : Training has run successfully!
795 08:31:19.073833 Check phy result
796 08:31:19.079112 INFO : End of initialization
797 08:31:19.079372 INFO : End of read enable training
798 08:31:19.082462 INFO : End of fine write leveling
799 08:31:19.088333 INFO : End of Write leveling coarse delay
800 08:31:19.093733 INFO : Training has run successfully!
801 08:31:19.093998 Check phy result
802 08:31:19.094204 INFO : End of initialization
803 08:31:19.099296 INFO : End of read dq deskew training
804 08:31:19.104870 INFO : End of MPR read delay center optimization
805 08:31:19.105373 INFO : End of write delay center optimization
806 08:31:19.110503 INFO : End of read delay center optimization
807 08:31:19.116156 INFO : End of max read latency training
808 08:31:19.116598 INFO : Training has run successfully!
809 08:31:19.121818 1D training succeed
810 08:31:19.127363 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
811 08:31:19.174973 Check phy result
812 08:31:19.175427 INFO : End of initialization
813 08:31:19.196504 INFO : End of 2D read delay Voltage center optimization
814 08:31:19.215457 INFO : End of 2D read delay Voltage center optimization
815 08:31:19.267684 INFO : End of 2D write delay Voltage center optimization
816 08:31:19.317601 INFO : End of 2D write delay Voltage center optimization
817 08:31:19.323165 INFO : Training has run successfully!
818 08:31:19.323670
819 08:31:19.324185 channel==0
820 08:31:19.329023 RxClkDly_Margin_A0==88 ps 9
821 08:31:19.329513 TxDqDly_Margin_A0==98 ps 10
822 08:31:19.332173 RxClkDly_Margin_A1==88 ps 9
823 08:31:19.332613 TxDqDly_Margin_A1==98 ps 10
824 08:31:19.337620 TrainedVREFDQ_A0==74
825 08:31:19.338055 TrainedVREFDQ_A1==74
826 08:31:19.338454 VrefDac_Margin_A0==25
827 08:31:19.343266 DeviceVref_Margin_A0==40
828 08:31:19.343692 VrefDac_Margin_A1==25
829 08:31:19.348850 DeviceVref_Margin_A1==40
830 08:31:19.349274
831 08:31:19.349667
832 08:31:19.350054 channel==1
833 08:31:19.350434 RxClkDly_Margin_A0==88 ps 9
834 08:31:19.354465 TxDqDly_Margin_A0==98 ps 10
835 08:31:19.354914 RxClkDly_Margin_A1==88 ps 9
836 08:31:19.360083 TxDqDly_Margin_A1==88 ps 9
837 08:31:19.360513 TrainedVREFDQ_A0==77
838 08:31:19.360905 TrainedVREFDQ_A1==77
839 08:31:19.365627 VrefDac_Margin_A0==23
840 08:31:19.366069 DeviceVref_Margin_A0==37
841 08:31:19.371231 VrefDac_Margin_A1==24
842 08:31:19.371659 DeviceVref_Margin_A1==37
843 08:31:19.372090
844 08:31:19.376942 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
845 08:31:19.377374
846 08:31:19.404869 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
847 08:31:19.410436 2D training succeed
848 08:31:19.416102 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
849 08:31:19.416543 auto size-- 65535DDR cs0 size: 2048MB
850 08:31:19.421647 DDR cs1 size: 2048MB
851 08:31:19.422080 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
852 08:31:19.427234 cs0 DataBus test pass
853 08:31:19.427660 cs1 DataBus test pass
854 08:31:19.428081 cs0 AddrBus test pass
855 08:31:19.432835 cs1 AddrBus test pass
856 08:31:19.433272
857 08:31:19.433666 100bdlr_step_size ps== 420
858 08:31:19.434064 result report
859 08:31:19.438445 boot times 0Enable ddr reg access
860 08:31:19.445198 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
861 08:31:19.459360 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
862 08:31:20.033347 0.0;M3 CHK:0;cm4_sp_mode 0
863 08:31:20.033753 MVN_1=0x00000000
864 08:31:20.038687 MVN_2=0x00000000
865 08:31:20.044471 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
866 08:31:20.044909 OPS=0x10
867 08:31:20.045153 ring efuse init
868 08:31:20.045358 chipver efuse init
869 08:31:20.050071 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
870 08:31:20.055695 [0.018961 Inits done]
871 08:31:20.056148 secure task start!
872 08:31:20.056484 high task start!
873 08:31:20.059558 low task start!
874 08:31:20.059960 run into bl31
875 08:31:20.067306 NOTICE: BL31: v1.3(release):4fc40b1
876 08:31:20.074718 NOTICE: BL31: Built : 15:58:17, May 22 2019
877 08:31:20.075056 NOTICE: BL31: G12A normal boot!
878 08:31:20.100191 NOTICE: BL31: BL33 decompress pass
879 08:31:20.104855 ERROR: Error initializing runtime service opteed_fast
880 08:31:21.338567
881 08:31:21.338980
882 08:31:21.347064 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
883 08:31:21.347553
884 08:31:21.347807 Model: Libre Computer AML-A311D-CC Alta
885 08:31:21.554516 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
886 08:31:21.578866 DRAM: 2 GiB (effective 3.8 GiB)
887 08:31:21.721866 Core: 408 devices, 31 uclasses, devicetree: separate
888 08:31:21.727724 WDT: Not starting watchdog@f0d0
889 08:31:21.760065 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
890 08:31:21.772553 Loading Environment from FAT... Card did not respond to voltage select! : -110
891 08:31:21.777573 ** Bad device specification mmc 0 **
892 08:31:21.787883 Card did not respond to voltage select! : -110
893 08:31:21.795515 ** Bad device specification mmc 0 **
894 08:31:21.796101 Couldn't find partition mmc 0
895 08:31:21.803870 Card did not respond to voltage select! : -110
896 08:31:21.809374 ** Bad device specification mmc 0 **
897 08:31:21.809918 Couldn't find partition mmc 0
898 08:31:21.814457 Error: could not access storage.
899 08:31:22.156837 Net: eth0: ethernet@ff3f0000
900 08:31:22.157473 starting USB...
901 08:31:22.408792 Bus usb@ff500000: Register 3000140 NbrPorts 3
902 08:31:22.409386 Starting the controller
903 08:31:22.415818 USB XHCI 1.10
904 08:31:23.969776 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
905 08:31:23.977883 scanning usb for storage devices... 0 Storage Device(s) found
907 08:31:24.028893 Hit any key to stop autoboot: 1
908 08:31:24.029823 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
909 08:31:24.030541 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
910 08:31:24.031086 Setting prompt string to ['=>']
911 08:31:24.031630 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
912 08:31:24.035542 0
913 08:31:24.036527 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
914 08:31:24.037093 Sending with 10 millisecond of delay
916 08:31:25.171845 => setenv autoload no
917 08:31:25.182757 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:28)
918 08:31:25.188223 setenv autoload no
919 08:31:25.189006 Sending with 10 millisecond of delay
921 08:31:26.985980 => setenv initrd_high 0xffffffff
922 08:31:26.996822 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
923 08:31:26.997750 setenv initrd_high 0xffffffff
924 08:31:26.998519 Sending with 10 millisecond of delay
926 08:31:28.615004 => setenv fdt_high 0xffffffff
927 08:31:28.625851 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
928 08:31:28.626790 setenv fdt_high 0xffffffff
929 08:31:28.627559 Sending with 10 millisecond of delay
931 08:31:28.919435 => dhcp
932 08:31:28.929953 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
933 08:31:28.930469 dhcp
934 08:31:28.930707 Speed: 1000, full duplex
935 08:31:28.930957 BOOTP broadcast 1
936 08:31:29.178524 BOOTP broadcast 2
937 08:31:29.679368 BOOTP broadcast 3
938 08:31:29.693727 DHCP client bound to address 192.168.6.33 (764 ms)
939 08:31:29.694299 Sending with 10 millisecond of delay
941 08:31:31.370507 => setenv serverip 192.168.6.2
942 08:31:31.381369 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
943 08:31:31.382335 setenv serverip 192.168.6.2
944 08:31:31.383086 Sending with 10 millisecond of delay
946 08:31:35.108735 => tftpboot 0x01080000 676515/tftp-deploy-l232m17b/kernel/uImage
947 08:31:35.119486 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
948 08:31:35.120167 tftpboot 0x01080000 676515/tftp-deploy-l232m17b/kernel/uImage
949 08:31:35.120434 Speed: 1000, full duplex
950 08:31:35.120658 Using ethernet@ff3f0000 device
951 08:31:35.122147 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
952 08:31:35.127444 Filename '676515/tftp-deploy-l232m17b/kernel/uImage'.
953 08:31:35.131423 Load address: 0x1080000
954 08:31:38.205643 Loading: *################################################## 45.1 MiB
955 08:31:38.206289 14.7 MiB/s
956 08:31:38.206767 done
957 08:31:38.209148 Bytes transferred = 47280704 (2d17240 hex)
958 08:31:38.209975 Sending with 10 millisecond of delay
960 08:31:42.906035 => tftpboot 0x08000000 676515/tftp-deploy-l232m17b/ramdisk/ramdisk.cpio.gz.uboot
961 08:31:42.916864 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
962 08:31:42.917744 tftpboot 0x08000000 676515/tftp-deploy-l232m17b/ramdisk/ramdisk.cpio.gz.uboot
963 08:31:42.918193 Speed: 1000, full duplex
964 08:31:42.918607 Using ethernet@ff3f0000 device
965 08:31:42.919900 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
966 08:31:42.931132 Filename '676515/tftp-deploy-l232m17b/ramdisk/ramdisk.cpio.gz.uboot'.
967 08:31:42.931634 Load address: 0x8000000
968 08:31:47.714962 Loading: *########### UDP wrong checksum 000000ff 0000b021
969 08:31:47.740150 UDP wrong checksum 000000ff 00003514
970 08:31:49.202554 T ########################## UDP wrong checksum 000000ff 00004d75
971 08:31:49.215432 UDP wrong checksum 000000ff 0000ea67
972 08:31:49.638243 ############ UDP wrong checksum 00000005 0000e9bd
973 08:31:51.111665 UDP wrong checksum 00000005 00004c8a
974 08:31:54.638500 T UDP wrong checksum 00000005 0000e9bd
975 08:32:04.640685 T T UDP wrong checksum 00000005 0000e9bd
976 08:32:24.644831 T T T T UDP wrong checksum 00000005 0000e9bd
977 08:32:28.307710 UDP wrong checksum 000000ff 00004942
978 08:32:28.325875 UDP wrong checksum 000000ff 0000d034
979 08:32:39.428413 T T UDP wrong checksum 000000ff 000082f3
980 08:32:39.470895 UDP wrong checksum 000000ff 000013e6
981 08:32:39.648727
982 08:32:39.649178 Retry count exceeded; starting again
984 08:32:39.650127 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
987 08:32:39.651153 end: 2.4 uboot-commands (duration 00:01:47) [common]
989 08:32:39.651934 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
991 08:32:39.652811 end: 2 uboot-action (duration 00:01:47) [common]
993 08:32:39.653755 Cleaning after the job
994 08:32:39.654123 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676515/tftp-deploy-l232m17b/ramdisk
995 08:32:39.654943 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676515/tftp-deploy-l232m17b/kernel
996 08:32:39.659221 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676515/tftp-deploy-l232m17b/dtb
997 08:32:39.660246 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676515/tftp-deploy-l232m17b/modules
998 08:32:39.663643 start: 4.1 power-off (timeout 00:00:30) [common]
999 08:32:39.664330 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1000 08:32:39.698605 >> OK - accepted request
1001 08:32:39.700773 Returned 0 in 0 seconds
1002 08:32:39.801781 end: 4.1 power-off (duration 00:00:00) [common]
1004 08:32:39.802866 start: 4.2 read-feedback (timeout 00:10:00) [common]
1005 08:32:39.803574 Listened to connection for namespace 'common' for up to 1s
1006 08:32:40.804545 Finalising connection for namespace 'common'
1007 08:32:40.805290 Disconnecting from shell: Finalise
1008 08:32:40.805821 =>
1009 08:32:40.906800 end: 4.2 read-feedback (duration 00:00:01) [common]
1010 08:32:40.907521 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/676515
1011 08:32:41.198979 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/676515
1012 08:32:41.199617 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.