Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 08:29:55.195929 lava-dispatcher, installed at version: 2024.01
2 08:29:55.196750 start: 0 validate
3 08:29:55.197248 Start time: 2024-08-30 08:29:55.197218+00:00 (UTC)
4 08:29:55.197805 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:29:55.198349 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 08:29:55.241267 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:29:55.241883 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240830%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 08:29:55.275604 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:29:55.276336 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240830%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 08:29:56.322500 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:29:56.323240 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240830%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 08:29:56.367552 validate duration: 1.17
14 08:29:56.368435 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 08:29:56.368769 start: 1.1 download-retry (timeout 00:10:00) [common]
16 08:29:56.369078 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 08:29:56.369679 Not decompressing ramdisk as can be used compressed.
18 08:29:56.370114 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 08:29:56.370389 saving as /var/lib/lava/dispatcher/tmp/676506/tftp-deploy-px8nqb_r/ramdisk/rootfs.cpio.gz
20 08:29:56.370663 total size: 8181887 (7 MB)
21 08:29:56.408161 progress 0 % (0 MB)
22 08:29:56.418912 progress 5 % (0 MB)
23 08:29:56.428599 progress 10 % (0 MB)
24 08:29:56.434277 progress 15 % (1 MB)
25 08:29:56.439492 progress 20 % (1 MB)
26 08:29:56.445180 progress 25 % (1 MB)
27 08:29:56.450389 progress 30 % (2 MB)
28 08:29:56.455938 progress 35 % (2 MB)
29 08:29:56.461132 progress 40 % (3 MB)
30 08:29:56.466703 progress 45 % (3 MB)
31 08:29:56.471873 progress 50 % (3 MB)
32 08:29:56.477688 progress 55 % (4 MB)
33 08:29:56.483488 progress 60 % (4 MB)
34 08:29:56.489110 progress 65 % (5 MB)
35 08:29:56.494227 progress 70 % (5 MB)
36 08:29:56.499718 progress 75 % (5 MB)
37 08:29:56.504874 progress 80 % (6 MB)
38 08:29:56.510380 progress 85 % (6 MB)
39 08:29:56.515379 progress 90 % (7 MB)
40 08:29:56.520586 progress 95 % (7 MB)
41 08:29:56.525329 progress 100 % (7 MB)
42 08:29:56.525989 7 MB downloaded in 0.16 s (50.24 MB/s)
43 08:29:56.526536 end: 1.1.1 http-download (duration 00:00:00) [common]
45 08:29:56.527416 end: 1.1 download-retry (duration 00:00:00) [common]
46 08:29:56.527716 start: 1.2 download-retry (timeout 00:10:00) [common]
47 08:29:56.528017 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 08:29:56.528507 downloading http://storage.kernelci.org/next/master/next-20240830/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/kernel/Image
49 08:29:56.528764 saving as /var/lib/lava/dispatcher/tmp/676506/tftp-deploy-px8nqb_r/kernel/Image
50 08:29:56.528975 total size: 47280640 (45 MB)
51 08:29:56.529182 No compression specified
52 08:29:56.567676 progress 0 % (0 MB)
53 08:29:56.597885 progress 5 % (2 MB)
54 08:29:56.628729 progress 10 % (4 MB)
55 08:29:56.658314 progress 15 % (6 MB)
56 08:29:56.688105 progress 20 % (9 MB)
57 08:29:56.718752 progress 25 % (11 MB)
58 08:29:56.748530 progress 30 % (13 MB)
59 08:29:56.778645 progress 35 % (15 MB)
60 08:29:56.807863 progress 40 % (18 MB)
61 08:29:56.837509 progress 45 % (20 MB)
62 08:29:56.866875 progress 50 % (22 MB)
63 08:29:56.896601 progress 55 % (24 MB)
64 08:29:56.926556 progress 60 % (27 MB)
65 08:29:56.956269 progress 65 % (29 MB)
66 08:29:56.985890 progress 70 % (31 MB)
67 08:29:57.015009 progress 75 % (33 MB)
68 08:29:57.044193 progress 80 % (36 MB)
69 08:29:57.073920 progress 85 % (38 MB)
70 08:29:57.103140 progress 90 % (40 MB)
71 08:29:57.132323 progress 95 % (42 MB)
72 08:29:57.160316 progress 100 % (45 MB)
73 08:29:57.161084 45 MB downloaded in 0.63 s (71.33 MB/s)
74 08:29:57.161593 end: 1.2.1 http-download (duration 00:00:01) [common]
76 08:29:57.162424 end: 1.2 download-retry (duration 00:00:01) [common]
77 08:29:57.162706 start: 1.3 download-retry (timeout 00:09:59) [common]
78 08:29:57.162970 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 08:29:57.163467 downloading http://storage.kernelci.org/next/master/next-20240830/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 08:29:57.163741 saving as /var/lib/lava/dispatcher/tmp/676506/tftp-deploy-px8nqb_r/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 08:29:57.163949 total size: 53173 (0 MB)
82 08:29:57.164207 No compression specified
83 08:29:57.208395 progress 61 % (0 MB)
84 08:29:57.209279 progress 100 % (0 MB)
85 08:29:57.209852 0 MB downloaded in 0.05 s (1.11 MB/s)
86 08:29:57.210330 end: 1.3.1 http-download (duration 00:00:00) [common]
88 08:29:57.211137 end: 1.3 download-retry (duration 00:00:00) [common]
89 08:29:57.211402 start: 1.4 download-retry (timeout 00:09:59) [common]
90 08:29:57.211666 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 08:29:57.212164 downloading http://storage.kernelci.org/next/master/next-20240830/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/modules.tar.xz
92 08:29:57.212419 saving as /var/lib/lava/dispatcher/tmp/676506/tftp-deploy-px8nqb_r/modules/modules.tar
93 08:29:57.212624 total size: 11541008 (11 MB)
94 08:29:57.212835 Using unxz to decompress xz
95 08:29:57.247921 progress 0 % (0 MB)
96 08:29:57.324770 progress 5 % (0 MB)
97 08:29:57.409203 progress 10 % (1 MB)
98 08:29:57.503824 progress 15 % (1 MB)
99 08:29:57.616457 progress 20 % (2 MB)
100 08:29:57.731758 progress 25 % (2 MB)
101 08:29:57.850368 progress 30 % (3 MB)
102 08:29:57.982250 progress 35 % (3 MB)
103 08:29:58.073929 progress 40 % (4 MB)
104 08:29:58.155620 progress 45 % (4 MB)
105 08:29:58.236248 progress 50 % (5 MB)
106 08:29:58.315251 progress 55 % (6 MB)
107 08:29:58.393398 progress 60 % (6 MB)
108 08:29:58.472450 progress 65 % (7 MB)
109 08:29:58.551865 progress 70 % (7 MB)
110 08:29:58.634184 progress 75 % (8 MB)
111 08:29:58.726360 progress 80 % (8 MB)
112 08:29:58.824776 progress 85 % (9 MB)
113 08:29:58.894250 progress 90 % (9 MB)
114 08:29:58.973281 progress 95 % (10 MB)
115 08:29:59.049218 progress 100 % (11 MB)
116 08:29:59.060806 11 MB downloaded in 1.85 s (5.96 MB/s)
117 08:29:59.061708 end: 1.4.1 http-download (duration 00:00:02) [common]
119 08:29:59.063399 end: 1.4 download-retry (duration 00:00:02) [common]
120 08:29:59.063928 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 08:29:59.064502 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 08:29:59.064994 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 08:29:59.065492 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 08:29:59.066461 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r
125 08:29:59.067303 makedir: /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin
126 08:29:59.067943 makedir: /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/tests
127 08:29:59.068608 makedir: /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/results
128 08:29:59.069247 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-add-keys
129 08:29:59.070265 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-add-sources
130 08:29:59.071208 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-background-process-start
131 08:29:59.072180 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-background-process-stop
132 08:29:59.073185 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-common-functions
133 08:29:59.074109 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-echo-ipv4
134 08:29:59.075017 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-install-packages
135 08:29:59.075903 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-installed-packages
136 08:29:59.076836 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-os-build
137 08:29:59.077715 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-probe-channel
138 08:29:59.078677 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-probe-ip
139 08:29:59.079583 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-target-ip
140 08:29:59.080530 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-target-mac
141 08:29:59.081429 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-target-storage
142 08:29:59.082396 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-test-case
143 08:29:59.083303 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-test-event
144 08:29:59.084226 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-test-feedback
145 08:29:59.085236 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-test-raise
146 08:29:59.086224 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-test-reference
147 08:29:59.087124 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-test-runner
148 08:29:59.088042 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-test-set
149 08:29:59.088970 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-test-shell
150 08:29:59.089871 Updating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-install-packages (oe)
151 08:29:59.090837 Updating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/bin/lava-installed-packages (oe)
152 08:29:59.091661 Creating /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/environment
153 08:29:59.092405 LAVA metadata
154 08:29:59.092881 - LAVA_JOB_ID=676506
155 08:29:59.093334 - LAVA_DISPATCHER_IP=192.168.6.2
156 08:29:59.094041 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 08:29:59.095926 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 08:29:59.096563 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 08:29:59.096971 skipped lava-vland-overlay
160 08:29:59.097451 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 08:29:59.097949 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 08:29:59.098371 skipped lava-multinode-overlay
163 08:29:59.098850 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 08:29:59.099348 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 08:29:59.099829 Loading test definitions
166 08:29:59.100415 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 08:29:59.100856 Using /lava-676506 at stage 0
168 08:29:59.103139 uuid=676506_1.5.2.4.1 testdef=None
169 08:29:59.103725 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 08:29:59.104276 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 08:29:59.107680 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 08:29:59.108735 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 08:29:59.111153 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 08:29:59.112017 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 08:29:59.114295 runner path: /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/0/tests/0_dmesg test_uuid 676506_1.5.2.4.1
178 08:29:59.114912 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 08:29:59.115685 Creating lava-test-runner.conf files
181 08:29:59.115889 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/676506/lava-overlay-nhth7k0r/lava-676506/0 for stage 0
182 08:29:59.116274 - 0_dmesg
183 08:29:59.116634 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 08:29:59.116914 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 08:29:59.142210 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 08:29:59.142659 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 08:29:59.142953 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 08:29:59.143228 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 08:29:59.143493 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 08:30:00.133936 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 08:30:00.134654 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 08:30:00.135134 extracting modules file /var/lib/lava/dispatcher/tmp/676506/tftp-deploy-px8nqb_r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/676506/extract-overlay-ramdisk-arjza4sz/ramdisk
193 08:30:01.481900 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 08:30:01.482365 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 08:30:01.482641 [common] Applying overlay /var/lib/lava/dispatcher/tmp/676506/compress-overlay-dnqn2vpg/overlay-1.5.2.5.tar.gz to ramdisk
196 08:30:01.482854 [common] Applying overlay /var/lib/lava/dispatcher/tmp/676506/compress-overlay-dnqn2vpg/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/676506/extract-overlay-ramdisk-arjza4sz/ramdisk
197 08:30:01.512848 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 08:30:01.513269 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 08:30:01.513548 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 08:30:01.513781 Converting downloaded kernel to a uImage
201 08:30:01.514097 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/676506/tftp-deploy-px8nqb_r/kernel/Image /var/lib/lava/dispatcher/tmp/676506/tftp-deploy-px8nqb_r/kernel/uImage
202 08:30:02.028478 output: Image Name:
203 08:30:02.028893 output: Created: Fri Aug 30 08:30:01 2024
204 08:30:02.029102 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 08:30:02.029306 output: Data Size: 47280640 Bytes = 46172.50 KiB = 45.09 MiB
206 08:30:02.029506 output: Load Address: 01080000
207 08:30:02.029706 output: Entry Point: 01080000
208 08:30:02.029901 output:
209 08:30:02.030230 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 08:30:02.030498 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 08:30:02.030769 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 08:30:02.031023 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 08:30:02.031279 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 08:30:02.031535 Building ramdisk /var/lib/lava/dispatcher/tmp/676506/extract-overlay-ramdisk-arjza4sz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/676506/extract-overlay-ramdisk-arjza4sz/ramdisk
215 08:30:04.369194 >> 180822 blocks
216 08:30:12.726926 Adding RAMdisk u-boot header.
217 08:30:12.727642 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/676506/extract-overlay-ramdisk-arjza4sz/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/676506/extract-overlay-ramdisk-arjza4sz/ramdisk.cpio.gz.uboot
218 08:30:13.025570 output: Image Name:
219 08:30:13.025986 output: Created: Fri Aug 30 08:30:12 2024
220 08:30:13.026193 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 08:30:13.026393 output: Data Size: 25953159 Bytes = 25344.88 KiB = 24.75 MiB
222 08:30:13.026592 output: Load Address: 00000000
223 08:30:13.026787 output: Entry Point: 00000000
224 08:30:13.026979 output:
225 08:30:13.027577 rename /var/lib/lava/dispatcher/tmp/676506/extract-overlay-ramdisk-arjza4sz/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/676506/tftp-deploy-px8nqb_r/ramdisk/ramdisk.cpio.gz.uboot
226 08:30:13.028020 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 08:30:13.028634 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 08:30:13.029220 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 08:30:13.029716 No LXC device requested
230 08:30:13.030265 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 08:30:13.030819 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 08:30:13.031358 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 08:30:13.031807 Checking files for TFTP limit of 4294967296 bytes.
234 08:30:13.034760 end: 1 tftp-deploy (duration 00:00:17) [common]
235 08:30:13.035375 start: 2 uboot-action (timeout 00:05:00) [common]
236 08:30:13.035941 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 08:30:13.036523 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 08:30:13.037085 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 08:30:13.037657 Using kernel file from prepare-kernel: 676506/tftp-deploy-px8nqb_r/kernel/uImage
240 08:30:13.038313 substitutions:
241 08:30:13.038761 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 08:30:13.039204 - {DTB_ADDR}: 0x01070000
243 08:30:13.039639 - {DTB}: 676506/tftp-deploy-px8nqb_r/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 08:30:13.040107 - {INITRD}: 676506/tftp-deploy-px8nqb_r/ramdisk/ramdisk.cpio.gz.uboot
245 08:30:13.040545 - {KERNEL_ADDR}: 0x01080000
246 08:30:13.040975 - {KERNEL}: 676506/tftp-deploy-px8nqb_r/kernel/uImage
247 08:30:13.041406 - {LAVA_MAC}: None
248 08:30:13.041877 - {PRESEED_CONFIG}: None
249 08:30:13.042308 - {PRESEED_LOCAL}: None
250 08:30:13.042732 - {RAMDISK_ADDR}: 0x08000000
251 08:30:13.043158 - {RAMDISK}: 676506/tftp-deploy-px8nqb_r/ramdisk/ramdisk.cpio.gz.uboot
252 08:30:13.043589 - {ROOT_PART}: None
253 08:30:13.044038 - {ROOT}: None
254 08:30:13.044466 - {SERVER_IP}: 192.168.6.2
255 08:30:13.044898 - {TEE_ADDR}: 0x83000000
256 08:30:13.045320 - {TEE}: None
257 08:30:13.045743 Parsed boot commands:
258 08:30:13.046155 - setenv autoload no
259 08:30:13.046576 - setenv initrd_high 0xffffffff
260 08:30:13.046998 - setenv fdt_high 0xffffffff
261 08:30:13.047420 - dhcp
262 08:30:13.047843 - setenv serverip 192.168.6.2
263 08:30:13.048288 - tftpboot 0x01080000 676506/tftp-deploy-px8nqb_r/kernel/uImage
264 08:30:13.048716 - tftpboot 0x08000000 676506/tftp-deploy-px8nqb_r/ramdisk/ramdisk.cpio.gz.uboot
265 08:30:13.049139 - tftpboot 0x01070000 676506/tftp-deploy-px8nqb_r/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 08:30:13.049562 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 08:30:13.049992 - bootm 0x01080000 0x08000000 0x01070000
268 08:30:13.050527 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 08:30:13.052163 start: 2.3 connect-device (timeout 00:05:00) [common]
271 08:30:13.052646 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 08:30:13.068676 Setting prompt string to ['lava-test: # ']
273 08:30:13.070254 end: 2.3 connect-device (duration 00:00:00) [common]
274 08:30:13.070901 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 08:30:13.071489 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 08:30:13.072274 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 08:30:13.073724 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 08:30:13.113930 >> OK - accepted request
279 08:30:13.116173 Returned 0 in 0 seconds
280 08:30:13.217077 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 08:30:13.218812 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 08:30:13.219427 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 08:30:13.220046 Setting prompt string to ['Hit any key to stop autoboot']
285 08:30:13.220549 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 08:30:13.222238 Trying 192.168.56.21...
287 08:30:13.222752 Connected to conserv1.
288 08:30:13.223210 Escape character is '^]'.
289 08:30:13.223666
290 08:30:13.224166 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 08:30:13.224632
292 08:30:21.494891 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 08:30:21.495568 bl2_stage_init 0x01
294 08:30:21.496097 bl2_stage_init 0x81
295 08:30:21.500401 hw id: 0x0000 - pwm id 0x01
296 08:30:21.500902 bl2_stage_init 0xc1
297 08:30:21.504839 bl2_stage_init 0x02
298 08:30:21.505341
299 08:30:21.505795 L0:00000000
300 08:30:21.506231 L1:00000703
301 08:30:21.506661 L2:00008067
302 08:30:21.510361 L3:15000000
303 08:30:21.510835 S1:00000000
304 08:30:21.511273 B2:20282000
305 08:30:21.511703 B1:a0f83180
306 08:30:21.512169
307 08:30:21.512605 TE: 70896
308 08:30:21.516058
309 08:30:21.521449 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 08:30:21.521925
311 08:30:21.522361 Board ID = 1
312 08:30:21.522791 Set cpu clk to 24M
313 08:30:21.523216 Set clk81 to 24M
314 08:30:21.527208 Use GP1_pll as DSU clk.
315 08:30:21.527727 DSU clk: 1200 Mhz
316 08:30:21.528204 CPU clk: 1200 MHz
317 08:30:21.532744 Set clk81 to 166.6M
318 08:30:21.538505 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 08:30:21.538975 board id: 1
320 08:30:21.546589 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 08:30:21.557486 fw parse done
322 08:30:21.563461 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 08:30:21.606613 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 08:30:21.617722 PIEI prepare done
325 08:30:21.618197 fastboot data load
326 08:30:21.618638 fastboot data verify
327 08:30:21.623281 verify result: 266
328 08:30:21.629034 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 08:30:21.629581 LPDDR4 probe
330 08:30:21.630015 ddr clk to 1584MHz
331 08:30:21.636906 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 08:30:21.674605
333 08:30:21.675077 dmc_version 0001
334 08:30:21.681646 Check phy result
335 08:30:21.687605 INFO : End of CA training
336 08:30:21.688104 INFO : End of initialization
337 08:30:21.693245 INFO : Training has run successfully!
338 08:30:21.693706 Check phy result
339 08:30:21.698845 INFO : End of initialization
340 08:30:21.699301 INFO : End of read enable training
341 08:30:21.704406 INFO : End of fine write leveling
342 08:30:21.710022 INFO : End of Write leveling coarse delay
343 08:30:21.710483 INFO : Training has run successfully!
344 08:30:21.710914 Check phy result
345 08:30:21.715604 INFO : End of initialization
346 08:30:21.716093 INFO : End of read dq deskew training
347 08:30:21.721218 INFO : End of MPR read delay center optimization
348 08:30:21.726831 INFO : End of write delay center optimization
349 08:30:21.732479 INFO : End of read delay center optimization
350 08:30:21.732964 INFO : End of max read latency training
351 08:30:21.738019 INFO : Training has run successfully!
352 08:30:21.738481 1D training succeed
353 08:30:21.747246 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 08:30:21.795560 Check phy result
355 08:30:21.796054 INFO : End of initialization
356 08:30:21.822925 INFO : End of 2D read delay Voltage center optimization
357 08:30:21.847160 INFO : End of 2D read delay Voltage center optimization
358 08:30:21.903863 INFO : End of 2D write delay Voltage center optimization
359 08:30:21.957868 INFO : End of 2D write delay Voltage center optimization
360 08:30:21.963453 INFO : Training has run successfully!
361 08:30:21.964074
362 08:30:21.964545 channel==0
363 08:30:21.969138 RxClkDly_Margin_A0==78 ps 8
364 08:30:21.969717 TxDqDly_Margin_A0==98 ps 10
365 08:30:21.974643 RxClkDly_Margin_A1==88 ps 9
366 08:30:21.975218 TxDqDly_Margin_A1==98 ps 10
367 08:30:21.975671 TrainedVREFDQ_A0==74
368 08:30:21.980252 TrainedVREFDQ_A1==74
369 08:30:21.980833 VrefDac_Margin_A0==24
370 08:30:21.981282 DeviceVref_Margin_A0==40
371 08:30:21.985852 VrefDac_Margin_A1==23
372 08:30:21.986417 DeviceVref_Margin_A1==40
373 08:30:21.986867
374 08:30:21.987306
375 08:30:21.991434 channel==1
376 08:30:21.992020 RxClkDly_Margin_A0==88 ps 9
377 08:30:21.992484 TxDqDly_Margin_A0==98 ps 10
378 08:30:21.997096 RxClkDly_Margin_A1==88 ps 9
379 08:30:21.997674 TxDqDly_Margin_A1==78 ps 8
380 08:30:22.002629 TrainedVREFDQ_A0==75
381 08:30:22.003194 TrainedVREFDQ_A1==75
382 08:30:22.003638 VrefDac_Margin_A0==23
383 08:30:22.008275 DeviceVref_Margin_A0==39
384 08:30:22.008831 VrefDac_Margin_A1==23
385 08:30:22.013850 DeviceVref_Margin_A1==38
386 08:30:22.014409
387 08:30:22.014878 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 08:30:22.015346
389 08:30:22.044362 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000015 00000018 00000015 00000015 00000017 00000018 0000001a 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
390 08:30:22.050002 2D training succeed
391 08:30:22.055568 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 08:30:22.056167 auto size-- 65535DDR cs0 size: 2048MB
393 08:30:22.061189 DDR cs1 size: 2048MB
394 08:30:22.061772 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 08:30:22.066771 cs0 DataBus test pass
396 08:30:22.067330 cs1 DataBus test pass
397 08:30:22.072411 cs0 AddrBus test pass
398 08:30:22.072981 cs1 AddrBus test pass
399 08:30:22.073423
400 08:30:22.073896 100bdlr_step_size ps== 471
401 08:30:22.077994 result report
402 08:30:22.078543 boot times 0Enable ddr reg access
403 08:30:22.086376 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 08:30:22.100174 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 08:30:22.760376 bl2z: ptr: 05129330, size: 00001e40
406 08:30:22.768281 0.0;M3 CHK:0;cm4_sp_mode 0
407 08:30:22.768866 MVN_1=0x00000000
408 08:30:22.769348 MVN_2=0x00000000
409 08:30:22.779719 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 08:30:22.780320 OPS=0x04
411 08:30:22.780794 ring efuse init
412 08:30:22.785383 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 08:30:22.785929 [0.017354 Inits done]
414 08:30:22.786391 secure task start!
415 08:30:22.792759 high task start!
416 08:30:22.793293 low task start!
417 08:30:22.793751 run into bl31
418 08:30:22.801384 NOTICE: BL31: v1.3(release):4fc40b1
419 08:30:22.809269 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 08:30:22.809819 NOTICE: BL31: G12A normal boot!
421 08:30:22.824757 NOTICE: BL31: BL33 decompress pass
422 08:30:22.830438 ERROR: Error initializing runtime service opteed_fast
423 08:30:24.072270 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 08:30:24.072932 bl2_stage_init 0x01
425 08:30:24.073418 bl2_stage_init 0x81
426 08:30:24.077929 hw id: 0x0000 - pwm id 0x01
427 08:30:24.078491 bl2_stage_init 0xc1
428 08:30:24.083465 bl2_stage_init 0x02
429 08:30:24.084085
430 08:30:24.084541 L0:00000000
431 08:30:24.084972 L1:00000703
432 08:30:24.085399 L2:00008067
433 08:30:24.085823 L3:15000000
434 08:30:24.089041 S1:00000000
435 08:30:24.089561 B2:20282000
436 08:30:24.089996 B1:a0f83180
437 08:30:24.090423
438 08:30:24.090849 TE: 69772
439 08:30:24.091277
440 08:30:24.094605 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 08:30:24.095121
442 08:30:24.100266 Board ID = 1
443 08:30:24.100798 Set cpu clk to 24M
444 08:30:24.101241 Set clk81 to 24M
445 08:30:24.105859 Use GP1_pll as DSU clk.
446 08:30:24.106396 DSU clk: 1200 Mhz
447 08:30:24.106829 CPU clk: 1200 MHz
448 08:30:24.111426 Set clk81 to 166.6M
449 08:30:24.117033 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 08:30:24.117558 board id: 1
451 08:30:24.124362 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 08:30:24.135171 fw parse done
453 08:30:24.141162 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 08:30:24.184326 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 08:30:24.195448 PIEI prepare done
456 08:30:24.196086 fastboot data load
457 08:30:24.196550 fastboot data verify
458 08:30:24.201051 verify result: 266
459 08:30:24.206637 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 08:30:24.207172 LPDDR4 probe
461 08:30:24.207603 ddr clk to 1584MHz
462 08:30:25.571603 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 08:30:25.572107 bl2_stage_init 0x01
464 08:30:25.572347 bl2_stage_init 0x81
465 08:30:25.577215 hw id: 0x0000 - pwm id 0x01
466 08:30:25.577535 bl2_stage_init 0xc1
467 08:30:25.582834 bl2_stage_init 0x02
468 08:30:25.583190
469 08:30:25.583408 L0:00000000
470 08:30:25.583642 L1:00000703
471 08:30:25.583861 L2:00008067
472 08:30:25.584121 L3:15000000
473 08:30:25.588409 S1:00000000
474 08:30:25.589184 B2:20282000
475 08:30:25.590868 B1:a0f83180
476 08:30:25.591266
477 08:30:25.591475 TE: 68119
478 08:30:25.591676
479 08:30:25.593982 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 08:30:25.594536
481 08:30:25.599512 Board ID = 1
482 08:30:25.600022 Set cpu clk to 24M
483 08:30:25.600486 Set clk81 to 24M
484 08:30:25.605125 Use GP1_pll as DSU clk.
485 08:30:25.605618 DSU clk: 1200 Mhz
486 08:30:25.606078 CPU clk: 1200 MHz
487 08:30:25.610729 Set clk81 to 166.6M
488 08:30:25.616333 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 08:30:25.616838 board id: 1
490 08:30:25.623508 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 08:30:25.634278 fw parse done
492 08:30:25.640264 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 08:30:25.682894 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 08:30:25.693855 PIEI prepare done
495 08:30:25.694374 fastboot data load
496 08:30:25.694853 fastboot data verify
497 08:30:25.699515 verify result: 266
498 08:30:25.705033 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 08:30:25.705549 LPDDR4 probe
500 08:30:25.706008 ddr clk to 1584MHz
501 08:30:25.713010 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 08:30:25.750323
503 08:30:25.750955 dmc_version 0001
504 08:30:25.756964 Check phy result
505 08:30:25.762857 INFO : End of CA training
506 08:30:25.763361 INFO : End of initialization
507 08:30:25.768509 INFO : Training has run successfully!
508 08:30:25.769008 Check phy result
509 08:30:25.774073 INFO : End of initialization
510 08:30:25.774577 INFO : End of read enable training
511 08:30:25.777401 INFO : End of fine write leveling
512 08:30:25.782997 INFO : End of Write leveling coarse delay
513 08:30:25.788616 INFO : Training has run successfully!
514 08:30:25.789135 Check phy result
515 08:30:25.789599 INFO : End of initialization
516 08:30:25.794164 INFO : End of read dq deskew training
517 08:30:25.799723 INFO : End of MPR read delay center optimization
518 08:30:25.800285 INFO : End of write delay center optimization
519 08:30:25.805335 INFO : End of read delay center optimization
520 08:30:25.810918 INFO : End of max read latency training
521 08:30:25.811417 INFO : Training has run successfully!
522 08:30:25.816533 1D training succeed
523 08:30:25.822412 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 08:30:25.870017 Check phy result
525 08:30:25.870604 INFO : End of initialization
526 08:30:25.892337 INFO : End of 2D read delay Voltage center optimization
527 08:30:25.911556 INFO : End of 2D read delay Voltage center optimization
528 08:30:25.963421 INFO : End of 2D write delay Voltage center optimization
529 08:30:26.012779 INFO : End of 2D write delay Voltage center optimization
530 08:30:26.018120 INFO : Training has run successfully!
531 08:30:26.018637
532 08:30:26.019107 channel==0
533 08:30:26.023736 RxClkDly_Margin_A0==78 ps 8
534 08:30:26.024307 TxDqDly_Margin_A0==98 ps 10
535 08:30:26.029389 RxClkDly_Margin_A1==88 ps 9
536 08:30:26.029894 TxDqDly_Margin_A1==88 ps 9
537 08:30:26.030349 TrainedVREFDQ_A0==74
538 08:30:26.034974 TrainedVREFDQ_A1==74
539 08:30:26.035475 VrefDac_Margin_A0==24
540 08:30:26.035931 DeviceVref_Margin_A0==40
541 08:30:26.040557 VrefDac_Margin_A1==23
542 08:30:26.041061 DeviceVref_Margin_A1==40
543 08:30:26.041517
544 08:30:26.041968
545 08:30:26.042417 channel==1
546 08:30:26.046179 RxClkDly_Margin_A0==78 ps 8
547 08:30:26.046747 TxDqDly_Margin_A0==88 ps 9
548 08:30:26.051774 RxClkDly_Margin_A1==78 ps 8
549 08:30:26.052317 TxDqDly_Margin_A1==78 ps 8
550 08:30:26.057373 TrainedVREFDQ_A0==75
551 08:30:26.057879 TrainedVREFDQ_A1==75
552 08:30:26.058337 VrefDac_Margin_A0==22
553 08:30:26.062959 DeviceVref_Margin_A0==39
554 08:30:26.063469 VrefDac_Margin_A1==22
555 08:30:26.063926 DeviceVref_Margin_A1==39
556 08:30:26.068557
557 08:30:26.069071 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 08:30:26.069524
559 08:30:26.102181 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000062
560 08:30:26.102735 2D training succeed
561 08:30:26.107789 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 08:30:26.113385 auto size-- 65535DDR cs0 size: 2048MB
563 08:30:26.113888 DDR cs1 size: 2048MB
564 08:30:26.118952 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 08:30:26.119453 cs0 DataBus test pass
566 08:30:26.124543 cs1 DataBus test pass
567 08:30:26.125046 cs0 AddrBus test pass
568 08:30:26.125502 cs1 AddrBus test pass
569 08:30:26.125946
570 08:30:26.130161 100bdlr_step_size ps== 478
571 08:30:26.130680 result report
572 08:30:26.135777 boot times 0Enable ddr reg access
573 08:30:26.140834 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 08:30:26.154670 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 08:30:26.810044 bl2z: ptr: 05129330, size: 00001e40
576 08:30:26.816395 0.0;M3 CHK:0;cm4_sp_mode 0
577 08:30:26.816933 MVN_1=0x00000000
578 08:30:26.817401 MVN_2=0x00000000
579 08:30:26.827900 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 08:30:26.828461 OPS=0x04
581 08:30:26.828931 ring efuse init
582 08:30:26.833609 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 08:30:26.834127 [0.017319 Inits done]
584 08:30:26.834589 secure task start!
585 08:30:26.841531 high task start!
586 08:30:26.842035 low task start!
587 08:30:26.842489 run into bl31
588 08:30:26.850024 NOTICE: BL31: v1.3(release):4fc40b1
589 08:30:26.857972 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 08:30:26.858495 NOTICE: BL31: G12A normal boot!
591 08:30:26.873340 NOTICE: BL31: BL33 decompress pass
592 08:30:26.879092 ERROR: Error initializing runtime service opteed_fast
593 08:30:28.122122 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 08:30:28.122550 bl2_stage_init 0x01
595 08:30:28.122773 bl2_stage_init 0x81
596 08:30:28.127659 hw id: 0x0000 - pwm id 0x01
597 08:30:28.128032 bl2_stage_init 0xc1
598 08:30:28.132957 bl2_stage_init 0x02
599 08:30:28.133278
600 08:30:28.133499 L0:00000000
601 08:30:28.133700 L1:00000703
602 08:30:28.133898 L2:00008067
603 08:30:28.134095 L3:15000000
604 08:30:28.138534 S1:00000000
605 08:30:28.138857 B2:20282000
606 08:30:28.139068 B1:a0f83180
607 08:30:28.139268
608 08:30:28.139466 TE: 69498
609 08:30:28.139664
610 08:30:28.144122 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 08:30:28.149713
612 08:30:28.150166 Board ID = 1
613 08:30:28.150519 Set cpu clk to 24M
614 08:30:28.150851 Set clk81 to 24M
615 08:30:28.153244 Use GP1_pll as DSU clk.
616 08:30:28.153708 DSU clk: 1200 Mhz
617 08:30:28.158918 CPU clk: 1200 MHz
618 08:30:28.159390 Set clk81 to 166.6M
619 08:30:28.164409 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 08:30:28.164741 board id: 1
621 08:30:28.174020 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 08:30:28.184676 fw parse done
623 08:30:28.190698 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 08:30:28.233241 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 08:30:28.244216 PIEI prepare done
626 08:30:28.244578 fastboot data load
627 08:30:28.244820 fastboot data verify
628 08:30:28.249863 verify result: 266
629 08:30:28.255338 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 08:30:28.255802 LPDDR4 probe
631 08:30:28.256105 ddr clk to 1584MHz
632 08:30:28.263349 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 08:30:28.300636
634 08:30:28.301018 dmc_version 0001
635 08:30:28.307295 Check phy result
636 08:30:28.313159 INFO : End of CA training
637 08:30:28.313620 INFO : End of initialization
638 08:30:28.318855 INFO : Training has run successfully!
639 08:30:28.319196 Check phy result
640 08:30:28.324384 INFO : End of initialization
641 08:30:28.324850 INFO : End of read enable training
642 08:30:28.330069 INFO : End of fine write leveling
643 08:30:28.335617 INFO : End of Write leveling coarse delay
644 08:30:28.335954 INFO : Training has run successfully!
645 08:30:28.336213 Check phy result
646 08:30:28.341213 INFO : End of initialization
647 08:30:28.341539 INFO : End of read dq deskew training
648 08:30:28.346886 INFO : End of MPR read delay center optimization
649 08:30:28.352405 INFO : End of write delay center optimization
650 08:30:28.358068 INFO : End of read delay center optimization
651 08:30:28.358409 INFO : End of max read latency training
652 08:30:28.363640 INFO : Training has run successfully!
653 08:30:28.364173 1D training succeed
654 08:30:28.372798 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 08:30:28.420409 Check phy result
656 08:30:28.420781 INFO : End of initialization
657 08:30:28.442786 INFO : End of 2D read delay Voltage center optimization
658 08:30:28.462039 INFO : End of 2D read delay Voltage center optimization
659 08:30:28.513829 INFO : End of 2D write delay Voltage center optimization
660 08:30:28.563082 INFO : End of 2D write delay Voltage center optimization
661 08:30:28.568565 INFO : Training has run successfully!
662 08:30:28.568893
663 08:30:28.569116 channel==0
664 08:30:28.574114 RxClkDly_Margin_A0==88 ps 9
665 08:30:28.574568 TxDqDly_Margin_A0==98 ps 10
666 08:30:28.579852 RxClkDly_Margin_A1==88 ps 9
667 08:30:28.580347 TxDqDly_Margin_A1==88 ps 9
668 08:30:28.580707 TrainedVREFDQ_A0==74
669 08:30:28.585407 TrainedVREFDQ_A1==74
670 08:30:28.585728 VrefDac_Margin_A0==24
671 08:30:28.585948 DeviceVref_Margin_A0==40
672 08:30:28.590987 VrefDac_Margin_A1==23
673 08:30:28.591308 DeviceVref_Margin_A1==40
674 08:30:28.591526
675 08:30:28.591736
676 08:30:28.591940 channel==1
677 08:30:28.596583 RxClkDly_Margin_A0==78 ps 8
678 08:30:28.597046 TxDqDly_Margin_A0==98 ps 10
679 08:30:28.602333 RxClkDly_Margin_A1==78 ps 8
680 08:30:28.602810 TxDqDly_Margin_A1==78 ps 8
681 08:30:28.607857 TrainedVREFDQ_A0==78
682 08:30:28.608352 TrainedVREFDQ_A1==75
683 08:30:28.608727 VrefDac_Margin_A0==22
684 08:30:28.613382 DeviceVref_Margin_A0==36
685 08:30:28.613717 VrefDac_Margin_A1==22
686 08:30:28.618976 DeviceVref_Margin_A1==39
687 08:30:28.619455
688 08:30:28.619825 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 08:30:28.620112
690 08:30:28.652558 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000014 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
691 08:30:28.652945 2D training succeed
692 08:30:28.658190 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 08:30:28.663643 auto size-- 65535DDR cs0 size: 2048MB
694 08:30:28.664128 DDR cs1 size: 2048MB
695 08:30:28.669296 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 08:30:28.669638 cs0 DataBus test pass
697 08:30:28.674873 cs1 DataBus test pass
698 08:30:28.675340 cs0 AddrBus test pass
699 08:30:28.675673 cs1 AddrBus test pass
700 08:30:28.676004
701 08:30:28.680487 100bdlr_step_size ps== 478
702 08:30:28.680821 result report
703 08:30:28.686039 boot times 0Enable ddr reg access
704 08:30:28.691239 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 08:30:28.705037 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 08:30:29.360124 bl2z: ptr: 05129330, size: 00001e40
707 08:30:29.365918 0.0;M3 CHK:0;cm4_sp_mode 0
708 08:30:29.366530 MVN_1=0x00000000
709 08:30:29.366995 MVN_2=0x00000000
710 08:30:29.377211 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 08:30:29.377798 OPS=0x04
712 08:30:29.378268 ring efuse init
713 08:30:29.382880 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 08:30:29.383449 [0.017319 Inits done]
715 08:30:29.383901 secure task start!
716 08:30:29.390189 high task start!
717 08:30:29.390729 low task start!
718 08:30:29.391165 run into bl31
719 08:30:29.398890 NOTICE: BL31: v1.3(release):4fc40b1
720 08:30:29.406616 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 08:30:29.407183 NOTICE: BL31: G12A normal boot!
722 08:30:29.422318 NOTICE: BL31: BL33 decompress pass
723 08:30:29.427904 ERROR: Error initializing runtime service opteed_fast
724 08:30:30.223302
725 08:30:30.223710
726 08:30:30.228652 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 08:30:30.228985
728 08:30:30.232166 Model: Libre Computer AML-S905D3-CC Solitude
729 08:30:30.378306 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 08:30:30.394571 DRAM: 2 GiB (effective 3.8 GiB)
731 08:30:30.495537 Core: 406 devices, 33 uclasses, devicetree: separate
732 08:30:30.501402 WDT: Not starting watchdog@f0d0
733 08:30:30.526509 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 08:30:30.538790 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 08:30:30.543818 ** Bad device specification mmc 0 **
736 08:30:30.553859 Card did not respond to voltage select! : -110
737 08:30:30.561502 ** Bad device specification mmc 0 **
738 08:30:30.562061 Couldn't find partition mmc 0
739 08:30:30.569828 Card did not respond to voltage select! : -110
740 08:30:30.575346 ** Bad device specification mmc 0 **
741 08:30:30.575898 Couldn't find partition mmc 0
742 08:30:30.580459 Error: could not access storage.
743 08:30:30.876758 Net: eth0: ethernet@ff3f0000
744 08:30:30.877431 starting USB...
745 08:30:31.121460 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 08:30:31.122051 Starting the controller
747 08:30:31.127456 USB XHCI 1.10
748 08:30:32.688099 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 08:30:32.690049 scanning usb for storage devices... 0 Storage Device(s) found
751 08:30:32.741014 Hit any key to stop autoboot: 1
752 08:30:32.741534 end: 2.4.2 bootloader-interrupt (duration 00:00:20) [common]
753 08:30:32.741912 start: 2.4.3 bootloader-commands (timeout 00:04:40) [common]
754 08:30:32.742190 Setting prompt string to ['=>']
755 08:30:32.742472 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:40)
756 08:30:32.756041 0
757 08:30:32.758354 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 08:30:32.859490 => setenv autoload no
760 08:30:32.861447 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
761 08:30:32.865547 setenv autoload no
763 08:30:32.968139 => setenv initrd_high 0xffffffff
764 08:30:32.968973 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
765 08:30:32.973165 setenv initrd_high 0xffffffff
767 08:30:33.075673 => setenv fdt_high 0xffffffff
768 08:30:33.076535 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
769 08:30:33.080774 setenv fdt_high 0xffffffff
771 08:30:33.183211 => dhcp
772 08:30:33.184048 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
773 08:30:33.188066 dhcp
774 08:30:34.194063 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
775 08:30:34.194631 Speed: 1000, full duplex
776 08:30:34.195055 BOOTP broadcast 1
777 08:30:34.442459 BOOTP broadcast 2
778 08:30:34.943393 BOOTP broadcast 3
779 08:30:35.944561 BOOTP broadcast 4
780 08:30:37.945552 BOOTP broadcast 5
781 08:30:37.958089 DHCP client bound to address 192.168.6.12 (3763 ms)
783 08:30:38.059365 => setenv serverip 192.168.6.2
784 08:30:38.060104 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
785 08:30:38.064547 setenv serverip 192.168.6.2
787 08:30:38.165724 => tftpboot 0x01080000 676506/tftp-deploy-px8nqb_r/kernel/uImage
788 08:30:38.166471 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
789 08:30:38.173060 tftpboot 0x01080000 676506/tftp-deploy-px8nqb_r/kernel/uImage
790 08:30:38.173416 Speed: 1000, full duplex
791 08:30:38.173630 Using ethernet@ff3f0000 device
792 08:30:38.178495 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
793 08:30:38.184091 Filename '676506/tftp-deploy-px8nqb_r/kernel/uImage'.
794 08:30:38.187963 Load address: 0x1080000
795 08:30:41.244428 Loading: *################################################## 45.1 MiB
796 08:30:41.245055 14.7 MiB/s
797 08:30:41.245509 done
798 08:30:41.248692 Bytes transferred = 47280704 (2d17240 hex)
800 08:30:41.350317 => tftpboot 0x08000000 676506/tftp-deploy-px8nqb_r/ramdisk/ramdisk.cpio.gz.uboot
801 08:30:41.351141 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
802 08:30:41.358024 tftpboot 0x08000000 676506/tftp-deploy-px8nqb_r/ramdisk/ramdisk.cpio.gz.uboot
803 08:30:41.358610 Speed: 1000, full duplex
804 08:30:41.359010 Using ethernet@ff3f0000 device
805 08:30:41.363260 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
806 08:30:41.373285 Filename '676506/tftp-deploy-px8nqb_r/ramdisk/ramdisk.cpio.gz.uboot'.
807 08:30:41.373912 Load address: 0x8000000
808 08:30:43.060243 Loading: *################################################# UDP wrong checksum 00000005 000001c4
809 08:30:48.060384 T UDP wrong checksum 00000005 000001c4
810 08:30:58.062313 T T UDP wrong checksum 00000005 000001c4
811 08:31:18.065635 T T T T UDP wrong checksum 00000005 000001c4
812 08:31:38.070550 T T T
813 08:31:38.070954 Retry count exceeded; starting again
815 08:31:38.071845 end: 2.4.3 bootloader-commands (duration 00:01:05) [common]
818 08:31:38.073877 end: 2.4 uboot-commands (duration 00:01:25) [common]
820 08:31:38.075441 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
822 08:31:38.076798 end: 2 uboot-action (duration 00:01:25) [common]
824 08:31:38.078538 Cleaning after the job
825 08:31:38.079149 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676506/tftp-deploy-px8nqb_r/ramdisk
826 08:31:38.080553 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676506/tftp-deploy-px8nqb_r/kernel
827 08:31:38.091840 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676506/tftp-deploy-px8nqb_r/dtb
828 08:31:38.092708 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676506/tftp-deploy-px8nqb_r/modules
829 08:31:38.096884 start: 4.1 power-off (timeout 00:00:30) [common]
830 08:31:38.097536 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
831 08:31:38.127474 >> OK - accepted request
832 08:31:38.130200 Returned 0 in 0 seconds
833 08:31:38.231165 end: 4.1 power-off (duration 00:00:00) [common]
835 08:31:38.233094 start: 4.2 read-feedback (timeout 00:10:00) [common]
836 08:31:38.234316 Listened to connection for namespace 'common' for up to 1s
837 08:31:39.235109 Finalising connection for namespace 'common'
838 08:31:39.235913 Disconnecting from shell: Finalise
839 08:31:39.236535 =>
840 08:31:39.337981 end: 4.2 read-feedback (duration 00:00:01) [common]
841 08:31:39.338733 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/676506
842 08:31:39.612204 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/676506
843 08:31:39.612865 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.