Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 08:57:36.440272 lava-dispatcher, installed at version: 2024.01
2 08:57:36.441130 start: 0 validate
3 08:57:36.441623 Start time: 2024-08-30 08:57:36.441591+00:00 (UTC)
4 08:57:36.442225 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:57:36.442851 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 08:57:36.480626 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:57:36.481181 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240830%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 08:57:37.513052 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:57:37.513711 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240830%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 08:57:47.611577 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:57:47.612132 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240830%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 08:57:48.654611 validate duration: 12.21
14 08:57:48.655560 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 08:57:48.655968 start: 1.1 download-retry (timeout 00:10:00) [common]
16 08:57:48.656342 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 08:57:48.656975 Not decompressing ramdisk as can be used compressed.
18 08:57:48.657470 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 08:57:48.657768 saving as /var/lib/lava/dispatcher/tmp/676617/tftp-deploy-fmowiw3v/ramdisk/rootfs.cpio.gz
20 08:57:48.658046 total size: 8181887 (7 MB)
21 08:57:48.701861 progress 0 % (0 MB)
22 08:57:48.713666 progress 5 % (0 MB)
23 08:57:48.724208 progress 10 % (0 MB)
24 08:57:48.730154 progress 15 % (1 MB)
25 08:57:48.735529 progress 20 % (1 MB)
26 08:57:48.741206 progress 25 % (1 MB)
27 08:57:48.746383 progress 30 % (2 MB)
28 08:57:48.752105 progress 35 % (2 MB)
29 08:57:48.757286 progress 40 % (3 MB)
30 08:57:48.762871 progress 45 % (3 MB)
31 08:57:48.768030 progress 50 % (3 MB)
32 08:57:48.773615 progress 55 % (4 MB)
33 08:57:48.778794 progress 60 % (4 MB)
34 08:57:48.784836 progress 65 % (5 MB)
35 08:57:48.791706 progress 70 % (5 MB)
36 08:57:48.797255 progress 75 % (5 MB)
37 08:57:48.802403 progress 80 % (6 MB)
38 08:57:48.807820 progress 85 % (6 MB)
39 08:57:48.812747 progress 90 % (7 MB)
40 08:57:48.817876 progress 95 % (7 MB)
41 08:57:48.822678 progress 100 % (7 MB)
42 08:57:48.823348 7 MB downloaded in 0.17 s (47.21 MB/s)
43 08:57:48.823913 end: 1.1.1 http-download (duration 00:00:00) [common]
45 08:57:48.824843 end: 1.1 download-retry (duration 00:00:00) [common]
46 08:57:48.825135 start: 1.2 download-retry (timeout 00:10:00) [common]
47 08:57:48.825410 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 08:57:48.825958 downloading http://storage.kernelci.org/next/master/next-20240830/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 08:57:48.826237 saving as /var/lib/lava/dispatcher/tmp/676617/tftp-deploy-fmowiw3v/kernel/Image
50 08:57:48.826448 total size: 64508416 (61 MB)
51 08:57:48.826659 No compression specified
52 08:57:48.866276 progress 0 % (0 MB)
53 08:57:48.903722 progress 5 % (3 MB)
54 08:57:48.940768 progress 10 % (6 MB)
55 08:57:48.978428 progress 15 % (9 MB)
56 08:57:49.015711 progress 20 % (12 MB)
57 08:57:49.053618 progress 25 % (15 MB)
58 08:57:49.092288 progress 30 % (18 MB)
59 08:57:49.132116 progress 35 % (21 MB)
60 08:57:49.170534 progress 40 % (24 MB)
61 08:57:49.209401 progress 45 % (27 MB)
62 08:57:49.248285 progress 50 % (30 MB)
63 08:57:49.286411 progress 55 % (33 MB)
64 08:57:49.324874 progress 60 % (36 MB)
65 08:57:49.362564 progress 65 % (40 MB)
66 08:57:49.400448 progress 70 % (43 MB)
67 08:57:49.438841 progress 75 % (46 MB)
68 08:57:49.476991 progress 80 % (49 MB)
69 08:57:49.515813 progress 85 % (52 MB)
70 08:57:49.555722 progress 90 % (55 MB)
71 08:57:49.594602 progress 95 % (58 MB)
72 08:57:49.632057 progress 100 % (61 MB)
73 08:57:49.632788 61 MB downloaded in 0.81 s (76.30 MB/s)
74 08:57:49.633302 end: 1.2.1 http-download (duration 00:00:01) [common]
76 08:57:49.634134 end: 1.2 download-retry (duration 00:00:01) [common]
77 08:57:49.634420 start: 1.3 download-retry (timeout 00:09:59) [common]
78 08:57:49.634730 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 08:57:49.635221 downloading http://storage.kernelci.org/next/master/next-20240830/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 08:57:49.635505 saving as /var/lib/lava/dispatcher/tmp/676617/tftp-deploy-fmowiw3v/dtb/meson-g12b-a311d-libretech-cc.dtb
81 08:57:49.635743 total size: 54667 (0 MB)
82 08:57:49.635963 No compression specified
83 08:57:49.680098 progress 59 % (0 MB)
84 08:57:49.680968 progress 100 % (0 MB)
85 08:57:49.681549 0 MB downloaded in 0.05 s (1.14 MB/s)
86 08:57:49.682042 end: 1.3.1 http-download (duration 00:00:00) [common]
88 08:57:49.682903 end: 1.3 download-retry (duration 00:00:00) [common]
89 08:57:49.683191 start: 1.4 download-retry (timeout 00:09:59) [common]
90 08:57:49.683483 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 08:57:49.684006 downloading http://storage.kernelci.org/next/master/next-20240830/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 08:57:49.684309 saving as /var/lib/lava/dispatcher/tmp/676617/tftp-deploy-fmowiw3v/modules/modules.tar
93 08:57:49.684546 total size: 16681104 (15 MB)
94 08:57:49.684775 Using unxz to decompress xz
95 08:57:49.738418 progress 0 % (0 MB)
96 08:57:49.873738 progress 5 % (0 MB)
97 08:57:49.991258 progress 10 % (1 MB)
98 08:57:50.119901 progress 15 % (2 MB)
99 08:57:50.255737 progress 20 % (3 MB)
100 08:57:50.382807 progress 25 % (4 MB)
101 08:57:50.501412 progress 30 % (4 MB)
102 08:57:50.628960 progress 35 % (5 MB)
103 08:57:50.747471 progress 40 % (6 MB)
104 08:57:50.867784 progress 45 % (7 MB)
105 08:57:50.987339 progress 50 % (7 MB)
106 08:57:51.109377 progress 55 % (8 MB)
107 08:57:51.233657 progress 60 % (9 MB)
108 08:57:51.355835 progress 65 % (10 MB)
109 08:57:51.480325 progress 70 % (11 MB)
110 08:57:51.614249 progress 75 % (11 MB)
111 08:57:51.747652 progress 80 % (12 MB)
112 08:57:51.856302 progress 85 % (13 MB)
113 08:57:51.993641 progress 90 % (14 MB)
114 08:57:52.109075 progress 95 % (15 MB)
115 08:57:52.233302 progress 100 % (15 MB)
116 08:57:52.248875 15 MB downloaded in 2.56 s (6.20 MB/s)
117 08:57:52.249761 end: 1.4.1 http-download (duration 00:00:03) [common]
119 08:57:52.250917 end: 1.4 download-retry (duration 00:00:03) [common]
120 08:57:52.251307 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 08:57:52.251670 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 08:57:52.252053 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 08:57:52.252426 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 08:57:52.253183 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb
125 08:57:52.253839 makedir: /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin
126 08:57:52.254471 makedir: /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/tests
127 08:57:52.254989 makedir: /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/results
128 08:57:52.255456 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-add-keys
129 08:57:52.256203 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-add-sources
130 08:57:52.256927 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-background-process-start
131 08:57:52.257637 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-background-process-stop
132 08:57:52.258409 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-common-functions
133 08:57:52.259092 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-echo-ipv4
134 08:57:52.259824 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-install-packages
135 08:57:52.260593 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-installed-packages
136 08:57:52.261253 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-os-build
137 08:57:52.261944 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-probe-channel
138 08:57:52.262647 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-probe-ip
139 08:57:52.263374 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-target-ip
140 08:57:52.264237 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-target-mac
141 08:57:52.265037 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-target-storage
142 08:57:52.265785 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-test-case
143 08:57:52.266575 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-test-event
144 08:57:52.267270 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-test-feedback
145 08:57:52.267954 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-test-raise
146 08:57:52.268678 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-test-reference
147 08:57:52.269399 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-test-runner
148 08:57:52.270078 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-test-set
149 08:57:52.270742 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-test-shell
150 08:57:52.271453 Updating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-install-packages (oe)
151 08:57:52.272314 Updating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/bin/lava-installed-packages (oe)
152 08:57:52.273041 Creating /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/environment
153 08:57:52.273908 LAVA metadata
154 08:57:52.274316 - LAVA_JOB_ID=676617
155 08:57:52.274631 - LAVA_DISPATCHER_IP=192.168.6.2
156 08:57:52.275160 start: 1.5.2.1 ssh-authorize (timeout 00:09:56) [common]
157 08:57:52.276780 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 08:57:52.277260 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:56) [common]
159 08:57:52.277537 skipped lava-vland-overlay
160 08:57:52.277856 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 08:57:52.278222 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:56) [common]
162 08:57:52.278547 skipped lava-multinode-overlay
163 08:57:52.278914 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 08:57:52.279294 start: 1.5.2.4 test-definition (timeout 00:09:56) [common]
165 08:57:52.279641 Loading test definitions
166 08:57:52.280059 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:56) [common]
167 08:57:52.280401 Using /lava-676617 at stage 0
168 08:57:52.281960 uuid=676617_1.5.2.4.1 testdef=None
169 08:57:52.282402 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 08:57:52.282765 start: 1.5.2.4.2 test-overlay (timeout 00:09:56) [common]
171 08:57:52.285281 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 08:57:52.286334 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:56) [common]
174 08:57:52.290104 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 08:57:52.291223 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:56) [common]
177 08:57:52.294276 runner path: /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/0/tests/0_dmesg test_uuid 676617_1.5.2.4.1
178 08:57:52.295086 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 08:57:52.296066 Creating lava-test-runner.conf files
181 08:57:52.296350 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/676617/lava-overlay-k1gjshxb/lava-676617/0 for stage 0
182 08:57:52.296836 - 0_dmesg
183 08:57:52.297316 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 08:57:52.297691 start: 1.5.2.5 compress-overlay (timeout 00:09:56) [common]
185 08:57:52.328443 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 08:57:52.328949 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:56) [common]
187 08:57:52.329247 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 08:57:52.329543 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 08:57:52.329837 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
190 08:57:53.340596 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 08:57:53.341081 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
192 08:57:53.341356 extracting modules file /var/lib/lava/dispatcher/tmp/676617/tftp-deploy-fmowiw3v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/676617/extract-overlay-ramdisk-grs3wvf6/ramdisk
193 08:57:55.109340 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 08:57:55.109845 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 08:57:55.110136 [common] Applying overlay /var/lib/lava/dispatcher/tmp/676617/compress-overlay-djef31u3/overlay-1.5.2.5.tar.gz to ramdisk
196 08:57:55.110361 [common] Applying overlay /var/lib/lava/dispatcher/tmp/676617/compress-overlay-djef31u3/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/676617/extract-overlay-ramdisk-grs3wvf6/ramdisk
197 08:57:55.141831 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 08:57:55.142289 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 08:57:55.142561 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 08:57:55.142790 Converting downloaded kernel to a uImage
201 08:57:55.143099 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/676617/tftp-deploy-fmowiw3v/kernel/Image /var/lib/lava/dispatcher/tmp/676617/tftp-deploy-fmowiw3v/kernel/uImage
202 08:57:55.920733 output: Image Name:
203 08:57:55.921153 output: Created: Fri Aug 30 08:57:55 2024
204 08:57:55.921364 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 08:57:55.921569 output: Data Size: 64508416 Bytes = 62996.50 KiB = 61.52 MiB
206 08:57:55.921769 output: Load Address: 01080000
207 08:57:55.921966 output: Entry Point: 01080000
208 08:57:55.922162 output:
209 08:57:55.922493 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 08:57:55.922758 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 08:57:55.923025 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 08:57:55.923277 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 08:57:55.923530 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 08:57:55.923781 Building ramdisk /var/lib/lava/dispatcher/tmp/676617/extract-overlay-ramdisk-grs3wvf6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/676617/extract-overlay-ramdisk-grs3wvf6/ramdisk
215 08:57:59.672568 >> 260178 blocks
216 08:58:11.063190 Adding RAMdisk u-boot header.
217 08:58:11.063748 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/676617/extract-overlay-ramdisk-grs3wvf6/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/676617/extract-overlay-ramdisk-grs3wvf6/ramdisk.cpio.gz.uboot
218 08:58:11.422264 output: Image Name:
219 08:58:11.422690 output: Created: Fri Aug 30 08:58:11 2024
220 08:58:11.422899 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 08:58:11.423103 output: Data Size: 34504909 Bytes = 33696.20 KiB = 32.91 MiB
222 08:58:11.423302 output: Load Address: 00000000
223 08:58:11.423501 output: Entry Point: 00000000
224 08:58:11.423695 output:
225 08:58:11.424483 rename /var/lib/lava/dispatcher/tmp/676617/extract-overlay-ramdisk-grs3wvf6/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/676617/tftp-deploy-fmowiw3v/ramdisk/ramdisk.cpio.gz.uboot
226 08:58:11.425217 end: 1.5.8 compress-ramdisk (duration 00:00:16) [common]
227 08:58:11.425758 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
228 08:58:11.426323 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
229 08:58:11.426775 No LXC device requested
230 08:58:11.427266 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 08:58:11.427764 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
232 08:58:11.428290 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 08:58:11.428700 Checking files for TFTP limit of 4294967296 bytes.
234 08:58:11.431334 end: 1 tftp-deploy (duration 00:00:23) [common]
235 08:58:11.431918 start: 2 uboot-action (timeout 00:05:00) [common]
236 08:58:11.432473 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 08:58:11.432970 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 08:58:11.433461 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 08:58:11.433992 Using kernel file from prepare-kernel: 676617/tftp-deploy-fmowiw3v/kernel/uImage
240 08:58:11.434592 substitutions:
241 08:58:11.434996 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 08:58:11.435393 - {DTB_ADDR}: 0x01070000
243 08:58:11.435785 - {DTB}: 676617/tftp-deploy-fmowiw3v/dtb/meson-g12b-a311d-libretech-cc.dtb
244 08:58:11.436213 - {INITRD}: 676617/tftp-deploy-fmowiw3v/ramdisk/ramdisk.cpio.gz.uboot
245 08:58:11.436611 - {KERNEL_ADDR}: 0x01080000
246 08:58:11.437002 - {KERNEL}: 676617/tftp-deploy-fmowiw3v/kernel/uImage
247 08:58:11.437393 - {LAVA_MAC}: None
248 08:58:11.437820 - {PRESEED_CONFIG}: None
249 08:58:11.438211 - {PRESEED_LOCAL}: None
250 08:58:11.438599 - {RAMDISK_ADDR}: 0x08000000
251 08:58:11.438981 - {RAMDISK}: 676617/tftp-deploy-fmowiw3v/ramdisk/ramdisk.cpio.gz.uboot
252 08:58:11.439371 - {ROOT_PART}: None
253 08:58:11.439755 - {ROOT}: None
254 08:58:11.440167 - {SERVER_IP}: 192.168.6.2
255 08:58:11.440558 - {TEE_ADDR}: 0x83000000
256 08:58:11.440944 - {TEE}: None
257 08:58:11.441328 Parsed boot commands:
258 08:58:11.441702 - setenv autoload no
259 08:58:11.442084 - setenv initrd_high 0xffffffff
260 08:58:11.442464 - setenv fdt_high 0xffffffff
261 08:58:11.442845 - dhcp
262 08:58:11.443229 - setenv serverip 192.168.6.2
263 08:58:11.443611 - tftpboot 0x01080000 676617/tftp-deploy-fmowiw3v/kernel/uImage
264 08:58:11.444014 - tftpboot 0x08000000 676617/tftp-deploy-fmowiw3v/ramdisk/ramdisk.cpio.gz.uboot
265 08:58:11.444405 - tftpboot 0x01070000 676617/tftp-deploy-fmowiw3v/dtb/meson-g12b-a311d-libretech-cc.dtb
266 08:58:11.444788 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 08:58:11.445177 - bootm 0x01080000 0x08000000 0x01070000
268 08:58:11.445669 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 08:58:11.447134 start: 2.3 connect-device (timeout 00:05:00) [common]
271 08:58:11.447573 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 08:58:11.462409 Setting prompt string to ['lava-test: # ']
273 08:58:11.463924 end: 2.3 connect-device (duration 00:00:00) [common]
274 08:58:11.464567 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 08:58:11.465103 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 08:58:11.465627 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 08:58:11.466914 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 08:58:11.501104 >> OK - accepted request
279 08:58:11.502998 Returned 0 in 0 seconds
280 08:58:11.603760 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 08:58:11.605018 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 08:58:11.605381 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 08:58:11.605706 Setting prompt string to ['Hit any key to stop autoboot']
285 08:58:11.605989 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 08:58:11.606986 Trying 192.168.56.21...
287 08:58:11.607278 Connected to conserv1.
288 08:58:11.607534 Escape character is '^]'.
289 08:58:11.607786
290 08:58:11.608060 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 08:58:11.608315
292 08:58:22.534996 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 08:58:22.535619 bl2_stage_init 0x01
294 08:58:22.536149 bl2_stage_init 0x81
295 08:58:22.540534 hw id: 0x0000 - pwm id 0x01
296 08:58:22.541078 bl2_stage_init 0xc1
297 08:58:22.541504 bl2_stage_init 0x02
298 08:58:22.541938
299 08:58:22.545997 L0:00000000
300 08:58:22.546435 L1:20000703
301 08:58:22.546834 L2:00008067
302 08:58:22.547218 L3:14000000
303 08:58:22.551607 B2:00402000
304 08:58:22.552056 B1:e0f83180
305 08:58:22.552447
306 08:58:22.552831 TE: 58124
307 08:58:22.553217
308 08:58:22.557186 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 08:58:22.557601
310 08:58:22.558038 Board ID = 1
311 08:58:22.562817 Set A53 clk to 24M
312 08:58:22.563245 Set A73 clk to 24M
313 08:58:22.563629 Set clk81 to 24M
314 08:58:22.568378 A53 clk: 1200 MHz
315 08:58:22.568800 A73 clk: 1200 MHz
316 08:58:22.569185 CLK81: 166.6M
317 08:58:22.569569 smccc: 00012a92
318 08:58:22.573968 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 08:58:22.579571 board id: 1
320 08:58:22.585539 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 08:58:22.596251 fw parse done
322 08:58:22.602109 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 08:58:22.644423 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 08:58:22.655593 PIEI prepare done
325 08:58:22.656046 fastboot data load
326 08:58:22.656441 fastboot data verify
327 08:58:22.661231 verify result: 266
328 08:58:22.666830 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 08:58:22.667251 LPDDR4 probe
330 08:58:22.667653 ddr clk to 1584MHz
331 08:58:22.674000 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 08:58:22.711313
333 08:58:22.711768 dmc_version 0001
334 08:58:22.717974 Check phy result
335 08:58:22.724630 INFO : End of CA training
336 08:58:22.725063 INFO : End of initialization
337 08:58:22.730253 INFO : Training has run successfully!
338 08:58:22.730676 Check phy result
339 08:58:22.735872 INFO : End of initialization
340 08:58:22.736316 INFO : End of read enable training
341 08:58:22.739256 INFO : End of fine write leveling
342 08:58:22.744868 INFO : End of Write leveling coarse delay
343 08:58:22.750467 INFO : Training has run successfully!
344 08:58:22.750887 Check phy result
345 08:58:22.751277 INFO : End of initialization
346 08:58:22.756069 INFO : End of read dq deskew training
347 08:58:22.761667 INFO : End of MPR read delay center optimization
348 08:58:22.762138 INFO : End of write delay center optimization
349 08:58:22.767265 INFO : End of read delay center optimization
350 08:58:22.772885 INFO : End of max read latency training
351 08:58:22.773313 INFO : Training has run successfully!
352 08:58:22.778459 1D training succeed
353 08:58:22.783391 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 08:58:22.830848 Check phy result
355 08:58:22.831288 INFO : End of initialization
356 08:58:22.853649 INFO : End of 2D read delay Voltage center optimization
357 08:58:22.874435 INFO : End of 2D read delay Voltage center optimization
358 08:58:22.925676 INFO : End of 2D write delay Voltage center optimization
359 08:58:22.976058 INFO : End of 2D write delay Voltage center optimization
360 08:58:22.981605 INFO : Training has run successfully!
361 08:58:22.982032
362 08:58:22.982429 channel==0
363 08:58:22.987281 RxClkDly_Margin_A0==88 ps 9
364 08:58:22.987718 TxDqDly_Margin_A0==98 ps 10
365 08:58:22.992807 RxClkDly_Margin_A1==88 ps 9
366 08:58:22.993225 TxDqDly_Margin_A1==98 ps 10
367 08:58:22.993618 TrainedVREFDQ_A0==74
368 08:58:22.998429 TrainedVREFDQ_A1==74
369 08:58:22.998847 VrefDac_Margin_A0==24
370 08:58:22.999234 DeviceVref_Margin_A0==40
371 08:58:23.004068 VrefDac_Margin_A1==25
372 08:58:23.004488 DeviceVref_Margin_A1==40
373 08:58:23.004880
374 08:58:23.005268
375 08:58:23.009614 channel==1
376 08:58:23.010035 RxClkDly_Margin_A0==98 ps 10
377 08:58:23.010422 TxDqDly_Margin_A0==98 ps 10
378 08:58:23.015285 RxClkDly_Margin_A1==98 ps 10
379 08:58:23.015711 TxDqDly_Margin_A1==88 ps 9
380 08:58:23.020792 TrainedVREFDQ_A0==77
381 08:58:23.021212 TrainedVREFDQ_A1==77
382 08:58:23.021600 VrefDac_Margin_A0==22
383 08:58:23.026443 DeviceVref_Margin_A0==37
384 08:58:23.026861 VrefDac_Margin_A1==23
385 08:58:23.032035 DeviceVref_Margin_A1==37
386 08:58:23.032485
387 08:58:23.032890 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 08:58:23.037632
389 08:58:23.065620 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 08:58:23.066165 2D training succeed
391 08:58:23.071311 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 08:58:23.076814 auto size-- 65535DDR cs0 size: 2048MB
393 08:58:23.077237 DDR cs1 size: 2048MB
394 08:58:23.082411 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 08:58:23.082828 cs0 DataBus test pass
396 08:58:23.088029 cs1 DataBus test pass
397 08:58:23.088449 cs0 AddrBus test pass
398 08:58:23.088837 cs1 AddrBus test pass
399 08:58:23.089220
400 08:58:23.093601 100bdlr_step_size ps== 420
401 08:58:23.094030 result report
402 08:58:23.099300 boot times 0Enable ddr reg access
403 08:58:23.104193 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 08:58:23.117802 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 08:58:23.691334 0.0;M3 CHK:0;cm4_sp_mode 0
406 08:58:23.691933 MVN_1=0x00000000
407 08:58:23.696726 MVN_2=0x00000000
408 08:58:23.702538 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 08:58:23.702967 OPS=0x10
410 08:58:23.703363 ring efuse init
411 08:58:23.703751 chipver efuse init
412 08:58:23.710736 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 08:58:23.711173 [0.018961 Inits done]
414 08:58:23.717516 secure task start!
415 08:58:23.717983 high task start!
416 08:58:23.718376 low task start!
417 08:58:23.718763 run into bl31
418 08:58:23.724864 NOTICE: BL31: v1.3(release):4fc40b1
419 08:58:23.732177 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 08:58:23.732659 NOTICE: BL31: G12A normal boot!
421 08:58:23.758069 NOTICE: BL31: BL33 decompress pass
422 08:58:23.762952 ERROR: Error initializing runtime service opteed_fast
423 08:58:24.996446
424 08:58:24.997076
425 08:58:25.004302 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 08:58:25.004935
427 08:58:25.005485 Model: Libre Computer AML-A311D-CC Alta
428 08:58:25.212415 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 08:58:25.235850 DRAM: 2 GiB (effective 3.8 GiB)
430 08:58:25.379739 Core: 408 devices, 31 uclasses, devicetree: separate
431 08:58:25.384710 WDT: Not starting watchdog@f0d0
432 08:58:25.417832 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 08:58:25.430329 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 08:58:25.435069 ** Bad device specification mmc 0 **
435 08:58:25.445824 Card did not respond to voltage select! : -110
436 08:58:25.452388 ** Bad device specification mmc 0 **
437 08:58:25.453073 Couldn't find partition mmc 0
438 08:58:25.461652 Card did not respond to voltage select! : -110
439 08:58:25.467222 ** Bad device specification mmc 0 **
440 08:58:25.467818 Couldn't find partition mmc 0
441 08:58:25.472079 Error: could not access storage.
442 08:58:26.734963 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 08:58:26.735596 bl2_stage_init 0x01
444 08:58:26.736062 bl2_stage_init 0x81
445 08:58:26.740522 hw id: 0x0000 - pwm id 0x01
446 08:58:26.740991 bl2_stage_init 0xc1
447 08:58:26.741405 bl2_stage_init 0x02
448 08:58:26.741809
449 08:58:26.746144 L0:00000000
450 08:58:26.746606 L1:20000703
451 08:58:26.747018 L2:00008067
452 08:58:26.747419 L3:14000000
453 08:58:26.751745 B2:00402000
454 08:58:26.752225 B1:e0f83180
455 08:58:26.752632
456 08:58:26.753033 TE: 58124
457 08:58:26.753447
458 08:58:26.757376 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 08:58:26.757842
460 08:58:26.758255 Board ID = 1
461 08:58:26.762960 Set A53 clk to 24M
462 08:58:26.763412 Set A73 clk to 24M
463 08:58:26.763823 Set clk81 to 24M
464 08:58:26.768550 A53 clk: 1200 MHz
465 08:58:26.769011 A73 clk: 1200 MHz
466 08:58:26.769419 CLK81: 166.6M
467 08:58:26.769818 smccc: 00012a92
468 08:58:26.774139 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 08:58:26.779752 board id: 1
470 08:58:26.784630 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 08:58:26.796253 fw parse done
472 08:58:26.801752 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 08:58:26.844818 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 08:58:26.855856 PIEI prepare done
475 08:58:26.856649 fastboot data load
476 08:58:26.857160 fastboot data verify
477 08:58:26.861497 verify result: 266
478 08:58:26.867053 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 08:58:26.867567 LPDDR4 probe
480 08:58:26.868115 ddr clk to 1584MHz
481 08:58:26.875115 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 08:58:26.911558
483 08:58:26.912174 dmc_version 0001
484 08:58:26.918566 Check phy result
485 08:58:26.924854 INFO : End of CA training
486 08:58:26.925407 INFO : End of initialization
487 08:58:26.930474 INFO : Training has run successfully!
488 08:58:26.931012 Check phy result
489 08:58:26.936043 INFO : End of initialization
490 08:58:26.936606 INFO : End of read enable training
491 08:58:26.941695 INFO : End of fine write leveling
492 08:58:26.947310 INFO : End of Write leveling coarse delay
493 08:58:26.947963 INFO : Training has run successfully!
494 08:58:26.948488 Check phy result
495 08:58:26.952853 INFO : End of initialization
496 08:58:26.953425 INFO : End of read dq deskew training
497 08:58:26.958463 INFO : End of MPR read delay center optimization
498 08:58:26.964160 INFO : End of write delay center optimization
499 08:58:26.969670 INFO : End of read delay center optimization
500 08:58:26.970287 INFO : End of max read latency training
501 08:58:26.975386 INFO : Training has run successfully!
502 08:58:26.975948 1D training succeed
503 08:58:26.984507 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 08:58:27.032295 Check phy result
505 08:58:27.032937 INFO : End of initialization
506 08:58:27.054118 INFO : End of 2D read delay Voltage center optimization
507 08:58:27.074825 INFO : End of 2D read delay Voltage center optimization
508 08:58:27.127406 INFO : End of 2D write delay Voltage center optimization
509 08:58:27.176465 INFO : End of 2D write delay Voltage center optimization
510 08:58:27.182016 INFO : Training has run successfully!
511 08:58:27.182532
512 08:58:27.182955 channel==0
513 08:58:27.187533 RxClkDly_Margin_A0==88 ps 9
514 08:58:27.188073 TxDqDly_Margin_A0==98 ps 10
515 08:58:27.193134 RxClkDly_Margin_A1==88 ps 9
516 08:58:27.193657 TxDqDly_Margin_A1==98 ps 10
517 08:58:27.194085 TrainedVREFDQ_A0==74
518 08:58:27.198814 TrainedVREFDQ_A1==74
519 08:58:27.199348 VrefDac_Margin_A0==24
520 08:58:27.199763 DeviceVref_Margin_A0==40
521 08:58:27.204340 VrefDac_Margin_A1==25
522 08:58:27.204858 DeviceVref_Margin_A1==40
523 08:58:27.205273
524 08:58:27.205677
525 08:58:27.210038 channel==1
526 08:58:27.210552 RxClkDly_Margin_A0==98 ps 10
527 08:58:27.210970 TxDqDly_Margin_A0==98 ps 10
528 08:58:27.215560 RxClkDly_Margin_A1==88 ps 9
529 08:58:27.216110 TxDqDly_Margin_A1==88 ps 9
530 08:58:27.221146 TrainedVREFDQ_A0==77
531 08:58:27.221656 TrainedVREFDQ_A1==77
532 08:58:27.222076 VrefDac_Margin_A0==22
533 08:58:27.226750 DeviceVref_Margin_A0==37
534 08:58:27.227248 VrefDac_Margin_A1==24
535 08:58:27.232347 DeviceVref_Margin_A1==37
536 08:58:27.232850
537 08:58:27.233270 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 08:58:27.233676
539 08:58:27.265931 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
540 08:58:27.266510 2D training succeed
541 08:58:27.271538 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 08:58:27.277159 auto size-- 65535DDR cs0 size: 2048MB
543 08:58:27.277665 DDR cs1 size: 2048MB
544 08:58:27.282743 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 08:58:27.283245 cs0 DataBus test pass
546 08:58:27.288343 cs1 DataBus test pass
547 08:58:27.288849 cs0 AddrBus test pass
548 08:58:27.289259 cs1 AddrBus test pass
549 08:58:27.289659
550 08:58:27.294006 100bdlr_step_size ps== 420
551 08:58:27.294514 result report
552 08:58:27.299504 boot times 0Enable ddr reg access
553 08:58:27.304094 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 08:58:27.317334 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 08:58:27.967552 0.0;M3 CHK:0;cm4_sp_mode 0
556 08:58:27.968026 MVN_1=0x00000000
557 08:58:27.968288 MVN_2=0x00000000
558 08:58:27.968536 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 08:58:27.968774 OPS=0x10
560 08:58:27.969000 ring efuse init
561 08:58:27.969225 chipver efuse init
562 08:58:27.969427 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 08:58:27.969630 [0.018961 Inits done]
564 08:58:27.969826 secure task start!
565 08:58:27.970023 high task start!
566 08:58:27.970253 low task start!
567 08:58:27.970460 run into bl31
568 08:58:27.970654 NOTICE: BL31: v1.3(release):4fc40b1
569 08:58:27.970851 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 08:58:27.971048 NOTICE: BL31: G12A normal boot!
571 08:58:27.971243 NOTICE: BL31: BL33 decompress pass
572 08:58:27.981636 ERROR: Error initializing runtime service opteed_fast
573 08:58:29.198071
574 08:58:29.198696
575 08:58:29.205631 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 08:58:29.206124
577 08:58:29.206530 Model: Libre Computer AML-A311D-CC Alta
578 08:58:29.413492 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 08:58:29.436720 DRAM: 2 GiB (effective 3.8 GiB)
580 08:58:29.580757 Core: 408 devices, 31 uclasses, devicetree: separate
581 08:58:29.585709 WDT: Not starting watchdog@f0d0
582 08:58:29.618825 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 08:58:29.631183 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 08:58:29.635340 ** Bad device specification mmc 0 **
585 08:58:29.646463 Card did not respond to voltage select! : -110
586 08:58:29.653429 ** Bad device specification mmc 0 **
587 08:58:29.653950 Couldn't find partition mmc 0
588 08:58:29.662467 Card did not respond to voltage select! : -110
589 08:58:29.668063 ** Bad device specification mmc 0 **
590 08:58:29.668583 Couldn't find partition mmc 0
591 08:58:29.672239 Error: could not access storage.
592 08:58:30.014657 Net: eth0: ethernet@ff3f0000
593 08:58:30.015281 starting USB...
594 08:58:30.267384 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 08:58:30.268093 Starting the controller
596 08:58:30.273479 USB XHCI 1.10
597 08:58:31.985640 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 08:58:31.986271 bl2_stage_init 0x01
599 08:58:31.986697 bl2_stage_init 0x81
600 08:58:31.991212 hw id: 0x0000 - pwm id 0x01
601 08:58:31.991669 bl2_stage_init 0xc1
602 08:58:31.992125 bl2_stage_init 0x02
603 08:58:31.992540
604 08:58:31.996650 L0:00000000
605 08:58:31.997100 L1:20000703
606 08:58:31.997508 L2:00008067
607 08:58:31.997906 L3:14000000
608 08:58:31.999736 B2:00402000
609 08:58:32.000198 B1:e0f83180
610 08:58:32.000602
611 08:58:32.000998 TE: 58124
612 08:58:32.001393
613 08:58:32.010575 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 08:58:32.011023
615 08:58:32.011432 Board ID = 1
616 08:58:32.011830 Set A53 clk to 24M
617 08:58:32.012258 Set A73 clk to 24M
618 08:58:32.016204 Set clk81 to 24M
619 08:58:32.016651 A53 clk: 1200 MHz
620 08:58:32.017055 A73 clk: 1200 MHz
621 08:58:32.020078 CLK81: 166.6M
622 08:58:32.020520 smccc: 00012a92
623 08:58:32.025591 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 08:58:32.031212 board id: 1
625 08:58:32.035288 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 08:58:32.046756 fw parse done
627 08:58:32.052713 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 08:58:32.095158 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 08:58:32.106308 PIEI prepare done
630 08:58:32.106783 fastboot data load
631 08:58:32.107195 fastboot data verify
632 08:58:32.111851 verify result: 266
633 08:58:32.117444 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 08:58:32.117903 LPDDR4 probe
635 08:58:32.118308 ddr clk to 1584MHz
636 08:58:32.124936 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 08:58:32.161747
638 08:58:32.162220 dmc_version 0001
639 08:58:32.168431 Check phy result
640 08:58:32.175268 INFO : End of CA training
641 08:58:32.175726 INFO : End of initialization
642 08:58:32.180858 INFO : Training has run successfully!
643 08:58:32.181315 Check phy result
644 08:58:32.186467 INFO : End of initialization
645 08:58:32.186925 INFO : End of read enable training
646 08:58:32.192072 INFO : End of fine write leveling
647 08:58:32.197650 INFO : End of Write leveling coarse delay
648 08:58:32.198105 INFO : Training has run successfully!
649 08:58:32.198512 Check phy result
650 08:58:32.203256 INFO : End of initialization
651 08:58:32.203713 INFO : End of read dq deskew training
652 08:58:32.208829 INFO : End of MPR read delay center optimization
653 08:58:32.214472 INFO : End of write delay center optimization
654 08:58:32.220082 INFO : End of read delay center optimization
655 08:58:32.220547 INFO : End of max read latency training
656 08:58:32.225677 INFO : Training has run successfully!
657 08:58:32.226136 1D training succeed
658 08:58:32.234818 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 08:58:32.281481 Check phy result
660 08:58:32.281962 INFO : End of initialization
661 08:58:32.303247 INFO : End of 2D read delay Voltage center optimization
662 08:58:32.324081 INFO : End of 2D read delay Voltage center optimization
663 08:58:32.375548 INFO : End of 2D write delay Voltage center optimization
664 08:58:32.425809 INFO : End of 2D write delay Voltage center optimization
665 08:58:32.431554 INFO : Training has run successfully!
666 08:58:32.432052
667 08:58:32.432475 channel==0
668 08:58:32.436974 RxClkDly_Margin_A0==88 ps 9
669 08:58:32.437427 TxDqDly_Margin_A0==98 ps 10
670 08:58:32.442582 RxClkDly_Margin_A1==88 ps 9
671 08:58:32.443033 TxDqDly_Margin_A1==98 ps 10
672 08:58:32.443445 TrainedVREFDQ_A0==74
673 08:58:32.448269 TrainedVREFDQ_A1==75
674 08:58:32.448731 VrefDac_Margin_A0==25
675 08:58:32.449138 DeviceVref_Margin_A0==40
676 08:58:32.453801 VrefDac_Margin_A1==25
677 08:58:32.454258 DeviceVref_Margin_A1==39
678 08:58:32.454663
679 08:58:32.455062
680 08:58:32.459391 channel==1
681 08:58:32.459845 RxClkDly_Margin_A0==98 ps 10
682 08:58:32.460291 TxDqDly_Margin_A0==98 ps 10
683 08:58:32.464985 RxClkDly_Margin_A1==98 ps 10
684 08:58:32.465435 TxDqDly_Margin_A1==88 ps 9
685 08:58:32.470599 TrainedVREFDQ_A0==77
686 08:58:32.471053 TrainedVREFDQ_A1==77
687 08:58:32.471456 VrefDac_Margin_A0==22
688 08:58:32.476214 DeviceVref_Margin_A0==37
689 08:58:32.476665 VrefDac_Margin_A1==24
690 08:58:32.481783 DeviceVref_Margin_A1==37
691 08:58:32.482236
692 08:58:32.482636 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 08:58:32.487361
694 08:58:32.515323 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 08:58:32.515842 2D training succeed
696 08:58:32.521035 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 08:58:32.526582 auto size-- 65535DDR cs0 size: 2048MB
698 08:58:32.527041 DDR cs1 size: 2048MB
699 08:58:32.532183 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 08:58:32.532637 cs0 DataBus test pass
701 08:58:32.537771 cs1 DataBus test pass
702 08:58:32.538223 cs0 AddrBus test pass
703 08:58:32.538626 cs1 AddrBus test pass
704 08:58:32.539020
705 08:58:32.543354 100bdlr_step_size ps== 420
706 08:58:32.543817 result report
707 08:58:32.548939 boot times 0Enable ddr reg access
708 08:58:32.553428 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 08:58:32.567664 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 08:58:33.141553 0.0;M3 CHK:0;cm4_sp_mode 0
711 08:58:33.142167 MVN_1=0x00000000
712 08:58:33.147024 MVN_2=0x00000000
713 08:58:33.152767 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 08:58:33.153255 OPS=0x10
715 08:58:33.153654 ring efuse init
716 08:58:33.154044 chipver efuse init
717 08:58:33.158499 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 08:58:33.163967 [0.018961 Inits done]
719 08:58:33.164442 secure task start!
720 08:58:33.164832 high task start!
721 08:58:33.167883 low task start!
722 08:58:33.168338 run into bl31
723 08:58:33.175270 NOTICE: BL31: v1.3(release):4fc40b1
724 08:58:33.182869 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 08:58:33.183326 NOTICE: BL31: G12A normal boot!
726 08:58:33.208323 NOTICE: BL31: BL33 decompress pass
727 08:58:33.213303 ERROR: Error initializing runtime service opteed_fast
728 08:58:34.446923
729 08:58:34.447368
730 08:58:34.455504 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 08:58:34.456088
732 08:58:34.456531 Model: Libre Computer AML-A311D-CC Alta
733 08:58:34.663388 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 08:58:34.686572 DRAM: 2 GiB (effective 3.8 GiB)
735 08:58:34.830274 Core: 408 devices, 31 uclasses, devicetree: separate
736 08:58:34.836217 WDT: Not starting watchdog@f0d0
737 08:58:34.868414 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 08:58:34.880842 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 08:58:34.885032 ** Bad device specification mmc 0 **
740 08:58:34.896221 Card did not respond to voltage select! : -110
741 08:58:34.903338 ** Bad device specification mmc 0 **
742 08:58:34.903838 Couldn't find partition mmc 0
743 08:58:34.912212 Card did not respond to voltage select! : -110
744 08:58:34.917693 ** Bad device specification mmc 0 **
745 08:58:34.918195 Couldn't find partition mmc 0
746 08:58:34.922660 Error: could not access storage.
747 08:58:35.264100 Net: eth0: ethernet@ff3f0000
748 08:58:35.264530 starting USB...
749 08:58:35.517008 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 08:58:35.517601 Starting the controller
751 08:58:35.522987 USB XHCI 1.10
752 08:58:37.686953 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 08:58:37.687513 bl2_stage_init 0x01
754 08:58:37.687874 bl2_stage_init 0x81
755 08:58:37.692558 hw id: 0x0000 - pwm id 0x01
756 08:58:37.692941 bl2_stage_init 0xc1
757 08:58:37.693260 bl2_stage_init 0x02
758 08:58:37.693575
759 08:58:37.698101 L0:00000000
760 08:58:37.698474 L1:20000703
761 08:58:37.698791 L2:00008067
762 08:58:37.699097 L3:14000000
763 08:58:37.701082 B2:00402000
764 08:58:37.701455 B1:e0f83180
765 08:58:37.701770
766 08:58:37.702084 TE: 58124
767 08:58:37.702394
768 08:58:37.712259 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 08:58:37.712639
770 08:58:37.713007 Board ID = 1
771 08:58:37.713334 Set A53 clk to 24M
772 08:58:37.713646 Set A73 clk to 24M
773 08:58:37.717830 Set clk81 to 24M
774 08:58:37.718176 A53 clk: 1200 MHz
775 08:58:37.718514 A73 clk: 1200 MHz
776 08:58:37.721249 CLK81: 166.6M
777 08:58:37.721631 smccc: 00012a91
778 08:58:37.726642 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 08:58:37.732242 board id: 1
780 08:58:37.736784 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 08:58:37.748287 fw parse done
782 08:58:37.754320 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 08:58:37.796365 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 08:58:37.807554 PIEI prepare done
785 08:58:37.807849 fastboot data load
786 08:58:37.808118 fastboot data verify
787 08:58:37.813151 verify result: 266
788 08:58:37.818739 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 08:58:37.819092 LPDDR4 probe
790 08:58:37.819433 ddr clk to 1584MHz
791 08:58:37.826474 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 08:58:37.864033
793 08:58:37.864355 dmc_version 0001
794 08:58:37.870377 Check phy result
795 08:58:37.876489 INFO : End of CA training
796 08:58:37.876765 INFO : End of initialization
797 08:58:37.882128 INFO : Training has run successfully!
798 08:58:37.882400 Check phy result
799 08:58:37.887698 INFO : End of initialization
800 08:58:37.887960 INFO : End of read enable training
801 08:58:37.891119 INFO : End of fine write leveling
802 08:58:37.896722 INFO : End of Write leveling coarse delay
803 08:58:37.902282 INFO : Training has run successfully!
804 08:58:37.902703 Check phy result
805 08:58:37.903059 INFO : End of initialization
806 08:58:37.907855 INFO : End of read dq deskew training
807 08:58:37.911295 INFO : End of MPR read delay center optimization
808 08:58:37.916769 INFO : End of write delay center optimization
809 08:58:37.922414 INFO : End of read delay center optimization
810 08:58:37.922756 INFO : End of max read latency training
811 08:58:37.928171 INFO : Training has run successfully!
812 08:58:37.928482 1D training succeed
813 08:58:37.935318 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 08:58:37.982905 Check phy result
815 08:58:37.983292 INFO : End of initialization
816 08:58:38.005561 INFO : End of 2D read delay Voltage center optimization
817 08:58:38.025805 INFO : End of 2D read delay Voltage center optimization
818 08:58:38.078318 INFO : End of 2D write delay Voltage center optimization
819 08:58:38.128125 INFO : End of 2D write delay Voltage center optimization
820 08:58:38.133631 INFO : Training has run successfully!
821 08:58:38.134126
822 08:58:38.134513 channel==0
823 08:58:38.139203 RxClkDly_Margin_A0==78 ps 8
824 08:58:38.139557 TxDqDly_Margin_A0==98 ps 10
825 08:58:38.144778 RxClkDly_Margin_A1==78 ps 8
826 08:58:38.145126 TxDqDly_Margin_A1==98 ps 10
827 08:58:38.145400 TrainedVREFDQ_A0==74
828 08:58:38.150495 TrainedVREFDQ_A1==75
829 08:58:38.150830 VrefDac_Margin_A0==26
830 08:58:38.151035 DeviceVref_Margin_A0==40
831 08:58:38.156082 VrefDac_Margin_A1==26
832 08:58:38.156447 DeviceVref_Margin_A1==39
833 08:58:38.156674
834 08:58:38.156890
835 08:58:38.161599 channel==1
836 08:58:38.162144 RxClkDly_Margin_A0==98 ps 10
837 08:58:38.162598 TxDqDly_Margin_A0==98 ps 10
838 08:58:38.167246 RxClkDly_Margin_A1==88 ps 9
839 08:58:38.167829 TxDqDly_Margin_A1==88 ps 9
840 08:58:38.172831 TrainedVREFDQ_A0==77
841 08:58:38.173379 TrainedVREFDQ_A1==77
842 08:58:38.173851 VrefDac_Margin_A0==22
843 08:58:38.178400 DeviceVref_Margin_A0==37
844 08:58:38.178727 VrefDac_Margin_A1==24
845 08:58:38.184038 DeviceVref_Margin_A1==37
846 08:58:38.184597
847 08:58:38.185045 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 08:58:38.185482
849 08:58:38.217650 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
850 08:58:38.218289 2D training succeed
851 08:58:38.223196 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 08:58:38.228806 auto size-- 65535DDR cs0 size: 2048MB
853 08:58:38.229342 DDR cs1 size: 2048MB
854 08:58:38.234384 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 08:58:38.234885 cs0 DataBus test pass
856 08:58:38.240004 cs1 DataBus test pass
857 08:58:38.240494 cs0 AddrBus test pass
858 08:58:38.240926 cs1 AddrBus test pass
859 08:58:38.241350
860 08:58:38.245587 100bdlr_step_size ps== 420
861 08:58:38.246113 result report
862 08:58:38.251181 boot times 0Enable ddr reg access
863 08:58:38.256226 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 08:58:38.269225 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 08:58:38.843673 0.0;M3 CHK:0;cm4_sp_mode 0
866 08:58:38.844418 MVN_1=0x00000000
867 08:58:38.849293 MVN_2=0x00000000
868 08:58:38.855258 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 08:58:38.855801 OPS=0x10
870 08:58:38.856270 ring efuse init
871 08:58:38.856681 chipver efuse init
872 08:58:38.860693 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 08:58:38.866359 [0.018961 Inits done]
874 08:58:38.866865 secure task start!
875 08:58:38.867287 high task start!
876 08:58:38.870612 low task start!
877 08:58:38.871179 run into bl31
878 08:58:38.877645 NOTICE: BL31: v1.3(release):4fc40b1
879 08:58:38.884426 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 08:58:38.884997 NOTICE: BL31: G12A normal boot!
881 08:58:38.910683 NOTICE: BL31: BL33 decompress pass
882 08:58:38.915407 ERROR: Error initializing runtime service opteed_fast
883 08:58:40.149139
884 08:58:40.149513
885 08:58:40.157341 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 08:58:40.157653
887 08:58:40.157879 Model: Libre Computer AML-A311D-CC Alta
888 08:58:40.365901 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 08:58:40.389388 DRAM: 2 GiB (effective 3.8 GiB)
890 08:58:40.532417 Core: 408 devices, 31 uclasses, devicetree: separate
891 08:58:40.537289 WDT: Not starting watchdog@f0d0
892 08:58:40.570617 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 08:58:40.583013 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 08:58:40.587172 ** Bad device specification mmc 0 **
895 08:58:40.598495 Card did not respond to voltage select! : -110
896 08:58:40.605193 ** Bad device specification mmc 0 **
897 08:58:40.605694 Couldn't find partition mmc 0
898 08:58:40.614514 Card did not respond to voltage select! : -110
899 08:58:40.619823 ** Bad device specification mmc 0 **
900 08:58:40.620299 Couldn't find partition mmc 0
901 08:58:40.624864 Error: could not access storage.
902 08:58:40.968172 Net: eth0: ethernet@ff3f0000
903 08:58:40.968757 starting USB...
904 08:58:41.219128 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 08:58:41.219535 Starting the controller
906 08:58:41.226009 USB XHCI 1.10
907 08:58:42.780139 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 08:58:42.787569 scanning usb for storage devices... 0 Storage Device(s) found
910 08:58:42.838783 Hit any key to stop autoboot: 1
911 08:58:42.839568 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
912 08:58:42.839935 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
913 08:58:42.840242 Setting prompt string to ['=>']
914 08:58:42.840510 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
915 08:58:42.845155 0
916 08:58:42.845783 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 08:58:42.846088 Sending with 10 millisecond of delay
919 08:58:43.980984 => setenv autoload no
920 08:58:43.991769 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
921 08:58:43.996730 setenv autoload no
922 08:58:43.997450 Sending with 10 millisecond of delay
924 08:58:45.795355 => setenv initrd_high 0xffffffff
925 08:58:45.806106 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
926 08:58:45.806896 setenv initrd_high 0xffffffff
927 08:58:45.807517 Sending with 10 millisecond of delay
929 08:58:47.424315 => setenv fdt_high 0xffffffff
930 08:58:47.435067 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
931 08:58:47.435841 setenv fdt_high 0xffffffff
932 08:58:47.436563 Sending with 10 millisecond of delay
934 08:58:47.728579 => dhcp
935 08:58:47.739407 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
936 08:58:47.740329 dhcp
937 08:58:47.740781 Speed: 1000, full duplex
938 08:58:47.741189 BOOTP broadcast 1
939 08:58:47.987908 BOOTP broadcast 2
940 08:58:48.179560 DHCP client bound to address 192.168.6.33 (440 ms)
941 08:58:48.180509 Sending with 10 millisecond of delay
943 08:58:49.858731 => setenv serverip 192.168.6.2
944 08:58:49.870581 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
945 08:58:49.871579 setenv serverip 192.168.6.2
946 08:58:49.872382 Sending with 10 millisecond of delay
948 08:58:53.602888 => tftpboot 0x01080000 676617/tftp-deploy-fmowiw3v/kernel/uImage
949 08:58:53.613762 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
950 08:58:53.614719 tftpboot 0x01080000 676617/tftp-deploy-fmowiw3v/kernel/uImage
951 08:58:53.615216 Speed: 1000, full duplex
952 08:58:53.615676 Using ethernet@ff3f0000 device
953 08:58:53.616208 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
954 08:58:53.621684 Filename '676617/tftp-deploy-fmowiw3v/kernel/uImage'.
955 08:58:53.625625 Load address: 0x1080000
956 08:58:57.979542 Loading: *################################################## 61.5 MiB
957 08:58:57.979952 14.1 MiB/s
958 08:58:57.980208 done
959 08:58:57.983997 Bytes transferred = 64508480 (3d85240 hex)
960 08:58:57.984507 Sending with 10 millisecond of delay
962 08:59:02.674759 => tftpboot 0x08000000 676617/tftp-deploy-fmowiw3v/ramdisk/ramdisk.cpio.gz.uboot
963 08:59:02.685275 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
964 08:59:02.685708 tftpboot 0x08000000 676617/tftp-deploy-fmowiw3v/ramdisk/ramdisk.cpio.gz.uboot
965 08:59:02.685940 Speed: 1000, full duplex
966 08:59:02.686155 Using ethernet@ff3f0000 device
967 08:59:02.687707 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
968 08:59:02.696359 Filename '676617/tftp-deploy-fmowiw3v/ramdisk/ramdisk.cpio.gz.uboot'.
969 08:59:02.696635 Load address: 0x8000000
970 08:59:04.986080 Loading: *################################################# UDP wrong checksum 00000007 0000da0a
971 08:59:09.987679 T UDP wrong checksum 00000007 0000da0a
972 08:59:19.990646 T T UDP wrong checksum 00000007 0000da0a
973 08:59:39.993019 T T T UDP wrong checksum 00000007 0000da0a
974 09:00:00.000468 T T T T
975 09:00:00.001103 Retry count exceeded; starting again
977 09:00:00.002520 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
980 09:00:00.004422 end: 2.4 uboot-commands (duration 00:01:49) [common]
982 09:00:00.005793 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
984 09:00:00.006803 end: 2 uboot-action (duration 00:01:49) [common]
986 09:00:00.008296 Cleaning after the job
987 09:00:00.008835 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676617/tftp-deploy-fmowiw3v/ramdisk
988 09:00:00.010226 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676617/tftp-deploy-fmowiw3v/kernel
989 09:00:00.040943 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676617/tftp-deploy-fmowiw3v/dtb
990 09:00:00.042210 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676617/tftp-deploy-fmowiw3v/modules
991 09:00:00.052769 start: 4.1 power-off (timeout 00:00:30) [common]
992 09:00:00.053359 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
993 09:00:00.085653 >> OK - accepted request
994 09:00:00.087807 Returned 0 in 0 seconds
995 09:00:00.188959 end: 4.1 power-off (duration 00:00:00) [common]
997 09:00:00.190664 start: 4.2 read-feedback (timeout 00:10:00) [common]
998 09:00:00.191764 Listened to connection for namespace 'common' for up to 1s
999 09:00:01.192558 Finalising connection for namespace 'common'
1000 09:00:01.193273 Disconnecting from shell: Finalise
1001 09:00:01.193794 =>
1002 09:00:01.294767 end: 4.2 read-feedback (duration 00:00:01) [common]
1003 09:00:01.295439 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/676617
1004 09:00:01.603003 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/676617
1005 09:00:01.603637 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.