Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 08:07:34.620355 lava-dispatcher, installed at version: 2024.01
2 08:07:34.621242 start: 0 validate
3 08:07:34.621747 Start time: 2024-08-30 08:07:34.621716+00:00 (UTC)
4 08:07:34.622306 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:07:34.622849 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 08:07:34.661567 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:07:34.662155 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240830%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 08:07:34.692883 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:07:34.693532 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240830%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 08:07:34.725823 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:07:34.726440 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240830%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 08:07:34.768344 validate duration: 0.15
14 08:07:34.769354 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 08:07:34.769737 start: 1.1 download-retry (timeout 00:10:00) [common]
16 08:07:34.770095 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 08:07:34.770816 Not decompressing ramdisk as can be used compressed.
18 08:07:34.771343 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 08:07:34.771653 saving as /var/lib/lava/dispatcher/tmp/676320/tftp-deploy-eegha1fg/ramdisk/rootfs.cpio.gz
20 08:07:34.771972 total size: 8181887 (7 MB)
21 08:07:34.811206 progress 0 % (0 MB)
22 08:07:34.817594 progress 5 % (0 MB)
23 08:07:34.823206 progress 10 % (0 MB)
24 08:07:34.828845 progress 15 % (1 MB)
25 08:07:34.833987 progress 20 % (1 MB)
26 08:07:34.839573 progress 25 % (1 MB)
27 08:07:34.844738 progress 30 % (2 MB)
28 08:07:34.850217 progress 35 % (2 MB)
29 08:07:34.855369 progress 40 % (3 MB)
30 08:07:34.860891 progress 45 % (3 MB)
31 08:07:34.866106 progress 50 % (3 MB)
32 08:07:34.871801 progress 55 % (4 MB)
33 08:07:34.877076 progress 60 % (4 MB)
34 08:07:34.882912 progress 65 % (5 MB)
35 08:07:34.888255 progress 70 % (5 MB)
36 08:07:34.894106 progress 75 % (5 MB)
37 08:07:34.899586 progress 80 % (6 MB)
38 08:07:34.905300 progress 85 % (6 MB)
39 08:07:34.910514 progress 90 % (7 MB)
40 08:07:34.915866 progress 95 % (7 MB)
41 08:07:34.921166 progress 100 % (7 MB)
42 08:07:34.921908 7 MB downloaded in 0.15 s (52.05 MB/s)
43 08:07:34.922479 end: 1.1.1 http-download (duration 00:00:00) [common]
45 08:07:34.923372 end: 1.1 download-retry (duration 00:00:00) [common]
46 08:07:34.923668 start: 1.2 download-retry (timeout 00:10:00) [common]
47 08:07:34.923938 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 08:07:34.924457 downloading http://storage.kernelci.org/next/master/next-20240830/arm64/defconfig/gcc-12/kernel/Image
49 08:07:34.924710 saving as /var/lib/lava/dispatcher/tmp/676320/tftp-deploy-eegha1fg/kernel/Image
50 08:07:34.924917 total size: 45603328 (43 MB)
51 08:07:34.925128 No compression specified
52 08:07:34.962810 progress 0 % (0 MB)
53 08:07:34.991074 progress 5 % (2 MB)
54 08:07:35.019329 progress 10 % (4 MB)
55 08:07:35.046855 progress 15 % (6 MB)
56 08:07:35.074885 progress 20 % (8 MB)
57 08:07:35.103940 progress 25 % (10 MB)
58 08:07:35.131272 progress 30 % (13 MB)
59 08:07:35.158607 progress 35 % (15 MB)
60 08:07:35.185296 progress 40 % (17 MB)
61 08:07:35.213072 progress 45 % (19 MB)
62 08:07:35.239785 progress 50 % (21 MB)
63 08:07:35.267210 progress 55 % (23 MB)
64 08:07:35.294578 progress 60 % (26 MB)
65 08:07:35.322126 progress 65 % (28 MB)
66 08:07:35.349074 progress 70 % (30 MB)
67 08:07:35.375860 progress 75 % (32 MB)
68 08:07:35.403231 progress 80 % (34 MB)
69 08:07:35.429950 progress 85 % (36 MB)
70 08:07:35.457180 progress 90 % (39 MB)
71 08:07:35.484541 progress 95 % (41 MB)
72 08:07:35.511104 progress 100 % (43 MB)
73 08:07:35.511821 43 MB downloaded in 0.59 s (74.10 MB/s)
74 08:07:35.512330 end: 1.2.1 http-download (duration 00:00:01) [common]
76 08:07:35.513141 end: 1.2 download-retry (duration 00:00:01) [common]
77 08:07:35.513417 start: 1.3 download-retry (timeout 00:09:59) [common]
78 08:07:35.513682 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 08:07:35.514150 downloading http://storage.kernelci.org/next/master/next-20240830/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 08:07:35.514403 saving as /var/lib/lava/dispatcher/tmp/676320/tftp-deploy-eegha1fg/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 08:07:35.514613 total size: 53173 (0 MB)
82 08:07:35.514824 No compression specified
83 08:07:35.552705 progress 61 % (0 MB)
84 08:07:35.553904 progress 100 % (0 MB)
85 08:07:35.554512 0 MB downloaded in 0.04 s (1.27 MB/s)
86 08:07:35.555034 end: 1.3.1 http-download (duration 00:00:00) [common]
88 08:07:35.555960 end: 1.3 download-retry (duration 00:00:00) [common]
89 08:07:35.556309 start: 1.4 download-retry (timeout 00:09:59) [common]
90 08:07:35.556626 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 08:07:35.557130 downloading http://storage.kernelci.org/next/master/next-20240830/arm64/defconfig/gcc-12/modules.tar.xz
92 08:07:35.557419 saving as /var/lib/lava/dispatcher/tmp/676320/tftp-deploy-eegha1fg/modules/modules.tar
93 08:07:35.557645 total size: 11553240 (11 MB)
94 08:07:35.557886 Using unxz to decompress xz
95 08:07:35.597387 progress 0 % (0 MB)
96 08:07:35.668849 progress 5 % (0 MB)
97 08:07:35.747740 progress 10 % (1 MB)
98 08:07:35.830720 progress 15 % (1 MB)
99 08:07:35.913234 progress 20 % (2 MB)
100 08:07:35.996782 progress 25 % (2 MB)
101 08:07:36.072811 progress 30 % (3 MB)
102 08:07:36.152503 progress 35 % (3 MB)
103 08:07:36.232409 progress 40 % (4 MB)
104 08:07:36.305019 progress 45 % (4 MB)
105 08:07:36.383776 progress 50 % (5 MB)
106 08:07:36.456803 progress 55 % (6 MB)
107 08:07:36.542514 progress 60 % (6 MB)
108 08:07:36.629176 progress 65 % (7 MB)
109 08:07:36.708948 progress 70 % (7 MB)
110 08:07:36.806506 progress 75 % (8 MB)
111 08:07:36.903701 progress 80 % (8 MB)
112 08:07:36.980547 progress 85 % (9 MB)
113 08:07:37.056626 progress 90 % (9 MB)
114 08:07:37.130688 progress 95 % (10 MB)
115 08:07:37.207879 progress 100 % (11 MB)
116 08:07:37.220018 11 MB downloaded in 1.66 s (6.63 MB/s)
117 08:07:37.221025 end: 1.4.1 http-download (duration 00:00:02) [common]
119 08:07:37.222772 end: 1.4 download-retry (duration 00:00:02) [common]
120 08:07:37.223347 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 08:07:37.223913 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 08:07:37.224488 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 08:07:37.225037 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 08:07:37.226106 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj
125 08:07:37.227034 makedir: /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin
126 08:07:37.227727 makedir: /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/tests
127 08:07:37.228447 makedir: /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/results
128 08:07:37.229110 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-add-keys
129 08:07:37.230136 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-add-sources
130 08:07:37.231126 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-background-process-start
131 08:07:37.232182 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-background-process-stop
132 08:07:37.233259 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-common-functions
133 08:07:37.234261 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-echo-ipv4
134 08:07:37.235239 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-install-packages
135 08:07:37.236238 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-installed-packages
136 08:07:37.237334 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-os-build
137 08:07:37.238329 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-probe-channel
138 08:07:37.239298 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-probe-ip
139 08:07:37.240302 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-target-ip
140 08:07:37.241295 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-target-mac
141 08:07:37.242269 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-target-storage
142 08:07:37.243250 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-test-case
143 08:07:37.244261 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-test-event
144 08:07:37.245265 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-test-feedback
145 08:07:37.246229 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-test-raise
146 08:07:37.247211 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-test-reference
147 08:07:37.248216 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-test-runner
148 08:07:37.249144 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-test-set
149 08:07:37.250052 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-test-shell
150 08:07:37.250951 Updating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-install-packages (oe)
151 08:07:37.251921 Updating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/bin/lava-installed-packages (oe)
152 08:07:37.252790 Creating /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/environment
153 08:07:37.253515 LAVA metadata
154 08:07:37.253999 - LAVA_JOB_ID=676320
155 08:07:37.254423 - LAVA_DISPATCHER_IP=192.168.6.2
156 08:07:37.255096 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 08:07:37.256582 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 08:07:37.256939 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 08:07:37.257157 skipped lava-vland-overlay
160 08:07:37.257403 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 08:07:37.257666 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 08:07:37.257886 skipped lava-multinode-overlay
163 08:07:37.258132 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 08:07:37.258387 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 08:07:37.258643 Loading test definitions
166 08:07:37.258929 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 08:07:37.259157 Using /lava-676320 at stage 0
168 08:07:37.260457 uuid=676320_1.5.2.4.1 testdef=None
169 08:07:37.260798 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 08:07:37.261074 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 08:07:37.263005 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 08:07:37.263830 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 08:07:37.266282 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 08:07:37.267212 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:58) [common]
177 08:07:37.269615 runner path: /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/0/tests/0_dmesg test_uuid 676320_1.5.2.4.1
178 08:07:37.270322 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 08:07:37.271132 Creating lava-test-runner.conf files
181 08:07:37.271339 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/676320/lava-overlay-e673vesj/lava-676320/0 for stage 0
182 08:07:37.271715 - 0_dmesg
183 08:07:37.272133 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 08:07:37.272444 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 08:07:37.297486 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 08:07:37.297979 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 08:07:37.298299 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 08:07:37.298578 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 08:07:37.298887 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 08:07:38.221527 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 08:07:38.221998 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 08:07:38.222244 extracting modules file /var/lib/lava/dispatcher/tmp/676320/tftp-deploy-eegha1fg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/676320/extract-overlay-ramdisk-owld_1mr/ramdisk
193 08:07:39.553271 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 08:07:39.553765 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 08:07:39.554043 [common] Applying overlay /var/lib/lava/dispatcher/tmp/676320/compress-overlay-b0hed36n/overlay-1.5.2.5.tar.gz to ramdisk
196 08:07:39.554256 [common] Applying overlay /var/lib/lava/dispatcher/tmp/676320/compress-overlay-b0hed36n/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/676320/extract-overlay-ramdisk-owld_1mr/ramdisk
197 08:07:39.584630 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 08:07:39.585082 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 08:07:39.585355 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 08:07:39.585584 Converting downloaded kernel to a uImage
201 08:07:39.585894 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/676320/tftp-deploy-eegha1fg/kernel/Image /var/lib/lava/dispatcher/tmp/676320/tftp-deploy-eegha1fg/kernel/uImage
202 08:07:40.063463 output: Image Name:
203 08:07:40.063885 output: Created: Fri Aug 30 08:07:39 2024
204 08:07:40.064131 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 08:07:40.064338 output: Data Size: 45603328 Bytes = 44534.50 KiB = 43.49 MiB
206 08:07:40.064539 output: Load Address: 01080000
207 08:07:40.064739 output: Entry Point: 01080000
208 08:07:40.064936 output:
209 08:07:40.065269 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 08:07:40.065535 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 08:07:40.065806 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 08:07:40.066061 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 08:07:40.066319 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 08:07:40.066575 Building ramdisk /var/lib/lava/dispatcher/tmp/676320/extract-overlay-ramdisk-owld_1mr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/676320/extract-overlay-ramdisk-owld_1mr/ramdisk
215 08:07:42.592287 >> 180797 blocks
216 08:07:51.013332 Adding RAMdisk u-boot header.
217 08:07:51.013829 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/676320/extract-overlay-ramdisk-owld_1mr/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/676320/extract-overlay-ramdisk-owld_1mr/ramdisk.cpio.gz.uboot
218 08:07:51.295232 output: Image Name:
219 08:07:51.295655 output: Created: Fri Aug 30 08:07:51 2024
220 08:07:51.295865 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 08:07:51.296292 output: Data Size: 25968129 Bytes = 25359.50 KiB = 24.77 MiB
222 08:07:51.296744 output: Load Address: 00000000
223 08:07:51.297197 output: Entry Point: 00000000
224 08:07:51.297630 output:
225 08:07:51.299158 rename /var/lib/lava/dispatcher/tmp/676320/extract-overlay-ramdisk-owld_1mr/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/676320/tftp-deploy-eegha1fg/ramdisk/ramdisk.cpio.gz.uboot
226 08:07:51.300018 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 08:07:51.300674 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 08:07:51.301274 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 08:07:51.301801 No LXC device requested
230 08:07:51.302393 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 08:07:51.302970 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 08:07:51.303516 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 08:07:51.303966 Checking files for TFTP limit of 4294967296 bytes.
234 08:07:51.306977 end: 1 tftp-deploy (duration 00:00:17) [common]
235 08:07:51.307652 start: 2 uboot-action (timeout 00:05:00) [common]
236 08:07:51.308278 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 08:07:51.308834 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 08:07:51.309382 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 08:07:51.309966 Using kernel file from prepare-kernel: 676320/tftp-deploy-eegha1fg/kernel/uImage
240 08:07:51.310650 substitutions:
241 08:07:51.311104 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 08:07:51.311546 - {DTB_ADDR}: 0x01070000
243 08:07:51.312006 - {DTB}: 676320/tftp-deploy-eegha1fg/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 08:07:51.312456 - {INITRD}: 676320/tftp-deploy-eegha1fg/ramdisk/ramdisk.cpio.gz.uboot
245 08:07:51.312893 - {KERNEL_ADDR}: 0x01080000
246 08:07:51.313323 - {KERNEL}: 676320/tftp-deploy-eegha1fg/kernel/uImage
247 08:07:51.313755 - {LAVA_MAC}: None
248 08:07:51.314233 - {PRESEED_CONFIG}: None
249 08:07:51.314667 - {PRESEED_LOCAL}: None
250 08:07:51.315098 - {RAMDISK_ADDR}: 0x08000000
251 08:07:51.315522 - {RAMDISK}: 676320/tftp-deploy-eegha1fg/ramdisk/ramdisk.cpio.gz.uboot
252 08:07:51.315952 - {ROOT_PART}: None
253 08:07:51.316411 - {ROOT}: None
254 08:07:51.316839 - {SERVER_IP}: 192.168.6.2
255 08:07:51.317269 - {TEE_ADDR}: 0x83000000
256 08:07:51.317694 - {TEE}: None
257 08:07:51.318120 Parsed boot commands:
258 08:07:51.318539 - setenv autoload no
259 08:07:51.318967 - setenv initrd_high 0xffffffff
260 08:07:51.319391 - setenv fdt_high 0xffffffff
261 08:07:51.319813 - dhcp
262 08:07:51.320272 - setenv serverip 192.168.6.2
263 08:07:51.320705 - tftpboot 0x01080000 676320/tftp-deploy-eegha1fg/kernel/uImage
264 08:07:51.321135 - tftpboot 0x08000000 676320/tftp-deploy-eegha1fg/ramdisk/ramdisk.cpio.gz.uboot
265 08:07:51.321562 - tftpboot 0x01070000 676320/tftp-deploy-eegha1fg/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 08:07:51.321988 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 08:07:51.322421 - bootm 0x01080000 0x08000000 0x01070000
268 08:07:51.322979 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 08:07:51.324646 start: 2.3 connect-device (timeout 00:05:00) [common]
271 08:07:51.325143 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 08:07:51.341538 Setting prompt string to ['lava-test: # ']
273 08:07:51.343174 end: 2.3 connect-device (duration 00:00:00) [common]
274 08:07:51.343842 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 08:07:51.344570 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 08:07:51.345258 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 08:07:51.346639 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 08:07:51.384564 >> OK - accepted request
279 08:07:51.386878 Returned 0 in 0 seconds
280 08:07:51.488278 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 08:07:51.490152 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 08:07:51.490791 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 08:07:51.491351 Setting prompt string to ['Hit any key to stop autoboot']
285 08:07:51.491853 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 08:07:51.493611 Trying 192.168.56.21...
287 08:07:51.494142 Connected to conserv1.
288 08:07:51.494587 Escape character is '^]'.
289 08:07:51.495052
290 08:07:51.495520 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 08:07:51.496026
292 08:07:58.965101 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 08:07:58.965798 bl2_stage_init 0x01
294 08:07:58.966284 bl2_stage_init 0x81
295 08:07:58.970394 hw id: 0x0000 - pwm id 0x01
296 08:07:58.970930 bl2_stage_init 0xc1
297 08:07:58.976188 bl2_stage_init 0x02
298 08:07:58.976715
299 08:07:58.977176 L0:00000000
300 08:07:58.977634 L1:00000703
301 08:07:58.978085 L2:00008067
302 08:07:58.978524 L3:15000000
303 08:07:58.981678 S1:00000000
304 08:07:58.982179 B2:20282000
305 08:07:58.982616 B1:a0f83180
306 08:07:58.983066
307 08:07:58.983511 TE: 69438
308 08:07:58.983960
309 08:07:58.987301 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 08:07:58.987801
311 08:07:58.992973 Board ID = 1
312 08:07:58.993471 Set cpu clk to 24M
313 08:07:58.993908 Set clk81 to 24M
314 08:07:58.998691 Use GP1_pll as DSU clk.
315 08:07:58.999196 DSU clk: 1200 Mhz
316 08:07:58.999633 CPU clk: 1200 MHz
317 08:07:59.004311 Set clk81 to 166.6M
318 08:07:59.009924 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 08:07:59.010528 board id: 1
320 08:07:59.016834 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 08:07:59.027554 fw parse done
322 08:07:59.033486 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 08:07:59.076017 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 08:07:59.086888 PIEI prepare done
325 08:07:59.087377 fastboot data load
326 08:07:59.087823 fastboot data verify
327 08:07:59.092446 verify result: 266
328 08:07:59.098056 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 08:07:59.098560 LPDDR4 probe
330 08:07:59.098999 ddr clk to 1584MHz
331 08:07:59.106060 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 08:07:59.143374
333 08:07:59.143953 dmc_version 0001
334 08:07:59.149056 Check phy result
335 08:07:59.155893 INFO : End of CA training
336 08:07:59.156445 INFO : End of initialization
337 08:07:59.161502 INFO : Training has run successfully!
338 08:07:59.162074 Check phy result
339 08:07:59.167093 INFO : End of initialization
340 08:07:59.167563 INFO : End of read enable training
341 08:07:59.173169 INFO : End of fine write leveling
342 08:07:59.178335 INFO : End of Write leveling coarse delay
343 08:07:59.178858 INFO : Training has run successfully!
344 08:07:59.179296 Check phy result
345 08:07:59.183917 INFO : End of initialization
346 08:07:59.184458 INFO : End of read dq deskew training
347 08:07:59.189516 INFO : End of MPR read delay center optimization
348 08:07:59.195086 INFO : End of write delay center optimization
349 08:07:59.200695 INFO : End of read delay center optimization
350 08:07:59.201239 INFO : End of max read latency training
351 08:07:59.206295 INFO : Training has run successfully!
352 08:07:59.206815 1D training succeed
353 08:07:59.215446 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 08:07:59.263247 Check phy result
355 08:07:59.263870 INFO : End of initialization
356 08:07:59.284651 INFO : End of 2D read delay Voltage center optimization
357 08:07:59.304671 INFO : End of 2D read delay Voltage center optimization
358 08:07:59.356434 INFO : End of 2D write delay Voltage center optimization
359 08:07:59.405767 INFO : End of 2D write delay Voltage center optimization
360 08:07:59.411241 INFO : Training has run successfully!
361 08:07:59.411721
362 08:07:59.412259 channel==0
363 08:07:59.416930 RxClkDly_Margin_A0==88 ps 9
364 08:07:59.417436 TxDqDly_Margin_A0==98 ps 10
365 08:07:59.420153 RxClkDly_Margin_A1==88 ps 9
366 08:07:59.420648 TxDqDly_Margin_A1==98 ps 10
367 08:07:59.425692 TrainedVREFDQ_A0==74
368 08:07:59.426185 TrainedVREFDQ_A1==75
369 08:07:59.431230 VrefDac_Margin_A0==24
370 08:07:59.431733 DeviceVref_Margin_A0==40
371 08:07:59.432224 VrefDac_Margin_A1==23
372 08:07:59.437019 DeviceVref_Margin_A1==39
373 08:07:59.437520
374 08:07:59.437956
375 08:07:59.438390 channel==1
376 08:07:59.438818 RxClkDly_Margin_A0==88 ps 9
377 08:07:59.442451 TxDqDly_Margin_A0==98 ps 10
378 08:07:59.442927 RxClkDly_Margin_A1==78 ps 8
379 08:07:59.448175 TxDqDly_Margin_A1==78 ps 8
380 08:07:59.448786 TrainedVREFDQ_A0==78
381 08:07:59.449240 TrainedVREFDQ_A1==75
382 08:07:59.453678 VrefDac_Margin_A0==22
383 08:07:59.454192 DeviceVref_Margin_A0==36
384 08:07:59.459295 VrefDac_Margin_A1==22
385 08:07:59.459816 DeviceVref_Margin_A1==39
386 08:07:59.460288
387 08:07:59.464897 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 08:07:59.465375
389 08:07:59.493018 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 08:07:59.498489 2D training succeed
391 08:07:59.504086 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 08:07:59.504631 auto size-- 65535DDR cs0 size: 2048MB
393 08:07:59.509627 DDR cs1 size: 2048MB
394 08:07:59.510103 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 08:07:59.515254 cs0 DataBus test pass
396 08:07:59.515760 cs1 DataBus test pass
397 08:07:59.516243 cs0 AddrBus test pass
398 08:07:59.520878 cs1 AddrBus test pass
399 08:07:59.521404
400 08:07:59.521846 100bdlr_step_size ps== 478
401 08:07:59.522290 result report
402 08:07:59.526457 boot times 0Enable ddr reg access
403 08:07:59.534111 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 08:07:59.547027 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 08:08:00.203367 bl2z: ptr: 05129330, size: 00001e40
406 08:08:00.210824 0.0;M3 CHK:0;cm4_sp_mode 0
407 08:08:00.211332 MVN_1=0x00000000
408 08:08:00.211776 MVN_2=0x00000000
409 08:08:00.222280 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 08:08:00.222766 OPS=0x04
411 08:08:00.223208 ring efuse init
412 08:08:00.228022 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 08:08:00.228505 [0.017320 Inits done]
414 08:08:00.228941 secure task start!
415 08:08:00.235129 high task start!
416 08:08:00.235594 low task start!
417 08:08:00.236060 run into bl31
418 08:08:00.243761 NOTICE: BL31: v1.3(release):4fc40b1
419 08:08:00.251551 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 08:08:00.252069 NOTICE: BL31: G12A normal boot!
421 08:08:00.267056 NOTICE: BL31: BL33 decompress pass
422 08:08:00.271893 ERROR: Error initializing runtime service opteed_fast
423 08:08:01.513478 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 08:08:01.514125 bl2_stage_init 0x01
425 08:08:01.514570 bl2_stage_init 0x81
426 08:08:01.519123 hw id: 0x0000 - pwm id 0x01
427 08:08:01.519597 bl2_stage_init 0xc1
428 08:08:01.524188 bl2_stage_init 0x02
429 08:08:01.524667
430 08:08:01.525101 L0:00000000
431 08:08:01.525594 L1:00000703
432 08:08:01.526021 L2:00008067
433 08:08:01.529817 L3:15000000
434 08:08:01.530290 S1:00000000
435 08:08:01.530723 B2:20282000
436 08:08:01.531149 B1:a0f83180
437 08:08:01.531573
438 08:08:01.532032 TE: 69409
439 08:08:01.532466
440 08:08:01.535357 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 08:08:01.540961
442 08:08:01.541442 Board ID = 1
443 08:08:01.541874 Set cpu clk to 24M
444 08:08:01.542301 Set clk81 to 24M
445 08:08:01.546626 Use GP1_pll as DSU clk.
446 08:08:01.547109 DSU clk: 1200 Mhz
447 08:08:01.547540 CPU clk: 1200 MHz
448 08:08:01.552180 Set clk81 to 166.6M
449 08:08:01.557793 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 08:08:01.558270 board id: 1
451 08:08:01.565440 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 08:08:01.576140 fw parse done
453 08:08:01.582073 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 08:08:01.624634 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 08:08:01.635602 PIEI prepare done
456 08:08:01.635909 fastboot data load
457 08:08:01.636184 fastboot data verify
458 08:08:01.641202 verify result: 266
459 08:08:01.646760 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 08:08:01.647049 LPDDR4 probe
461 08:08:01.647278 ddr clk to 1584MHz
462 08:08:03.011883 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 08:08:03.012486 bl2_stage_init 0x01
464 08:08:03.012820 bl2_stage_init 0x81
465 08:08:03.017352 hw id: 0x0000 - pwm id 0x01
466 08:08:03.017754 bl2_stage_init 0xc1
467 08:08:03.023004 bl2_stage_init 0x02
468 08:08:03.023391
469 08:08:03.023710 L0:00000000
470 08:08:03.024041 L1:00000703
471 08:08:03.024346 L2:00008067
472 08:08:03.024651 L3:15000000
473 08:08:03.028560 S1:00000000
474 08:08:03.028943 B2:20282000
475 08:08:03.029252 B1:a0f83180
476 08:08:03.029565
477 08:08:03.029865 TE: 68098
478 08:08:03.030166
479 08:08:03.034288 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 08:08:03.034695
481 08:08:03.039767 Board ID = 1
482 08:08:03.040178 Set cpu clk to 24M
483 08:08:03.040505 Set clk81 to 24M
484 08:08:03.045389 Use GP1_pll as DSU clk.
485 08:08:03.045766 DSU clk: 1200 Mhz
486 08:08:03.046073 CPU clk: 1200 MHz
487 08:08:03.051010 Set clk81 to 166.6M
488 08:08:03.056544 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 08:08:03.056891 board id: 1
490 08:08:03.063241 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 08:08:03.074453 fw parse done
492 08:08:03.080438 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 08:08:03.123007 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 08:08:03.134029 PIEI prepare done
495 08:08:03.134339 fastboot data load
496 08:08:03.134593 fastboot data verify
497 08:08:03.139604 verify result: 266
498 08:08:03.145184 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 08:08:03.145491 LPDDR4 probe
500 08:08:03.145742 ddr clk to 1584MHz
501 08:08:03.153253 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 08:08:03.189917
503 08:08:03.190474 dmc_version 0001
504 08:08:03.197146 Check phy result
505 08:08:03.203044 INFO : End of CA training
506 08:08:03.203487 INFO : End of initialization
507 08:08:03.208631 INFO : Training has run successfully!
508 08:08:03.209078 Check phy result
509 08:08:03.214227 INFO : End of initialization
510 08:08:03.214670 INFO : End of read enable training
511 08:08:03.219834 INFO : End of fine write leveling
512 08:08:03.225432 INFO : End of Write leveling coarse delay
513 08:08:03.225881 INFO : Training has run successfully!
514 08:08:03.226288 Check phy result
515 08:08:03.231081 INFO : End of initialization
516 08:08:03.231527 INFO : End of read dq deskew training
517 08:08:03.236661 INFO : End of MPR read delay center optimization
518 08:08:03.242220 INFO : End of write delay center optimization
519 08:08:03.247810 INFO : End of read delay center optimization
520 08:08:03.248082 INFO : End of max read latency training
521 08:08:03.253425 INFO : Training has run successfully!
522 08:08:03.253664 1D training succeed
523 08:08:03.262604 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 08:08:03.310334 Check phy result
525 08:08:03.310823 INFO : End of initialization
526 08:08:03.332542 INFO : End of 2D read delay Voltage center optimization
527 08:08:03.351815 INFO : End of 2D read delay Voltage center optimization
528 08:08:03.403650 INFO : End of 2D write delay Voltage center optimization
529 08:08:03.452871 INFO : End of 2D write delay Voltage center optimization
530 08:08:03.458398 INFO : Training has run successfully!
531 08:08:03.458642
532 08:08:03.458851 channel==0
533 08:08:03.463966 RxClkDly_Margin_A0==78 ps 8
534 08:08:03.464233 TxDqDly_Margin_A0==88 ps 9
535 08:08:03.469529 RxClkDly_Margin_A1==88 ps 9
536 08:08:03.469771 TxDqDly_Margin_A1==88 ps 9
537 08:08:03.469976 TrainedVREFDQ_A0==74
538 08:08:03.475149 TrainedVREFDQ_A1==74
539 08:08:03.475419 VrefDac_Margin_A0==24
540 08:08:03.475629 DeviceVref_Margin_A0==40
541 08:08:03.480701 VrefDac_Margin_A1==23
542 08:08:03.480942 DeviceVref_Margin_A1==40
543 08:08:03.481146
544 08:08:03.481359
545 08:08:03.481561 channel==1
546 08:08:03.486409 RxClkDly_Margin_A0==78 ps 8
547 08:08:03.486997 TxDqDly_Margin_A0==88 ps 9
548 08:08:03.491999 RxClkDly_Margin_A1==78 ps 8
549 08:08:03.492970 TxDqDly_Margin_A1==88 ps 9
550 08:08:03.497720 TrainedVREFDQ_A0==78
551 08:08:03.498338 TrainedVREFDQ_A1==77
552 08:08:03.498828 VrefDac_Margin_A0==22
553 08:08:03.503385 DeviceVref_Margin_A0==36
554 08:08:03.503956 VrefDac_Margin_A1==22
555 08:08:03.504496 DeviceVref_Margin_A1==37
556 08:08:03.508892
557 08:08:03.509448 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 08:08:03.509918
559 08:08:03.542518 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
560 08:08:03.543137 2D training succeed
561 08:08:03.548108 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 08:08:03.553678 auto size-- 65535DDR cs0 size: 2048MB
563 08:08:03.554252 DDR cs1 size: 2048MB
564 08:08:03.559379 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 08:08:03.559951 cs0 DataBus test pass
566 08:08:03.564914 cs1 DataBus test pass
567 08:08:03.565483 cs0 AddrBus test pass
568 08:08:03.565944 cs1 AddrBus test pass
569 08:08:03.566395
570 08:08:03.570582 100bdlr_step_size ps== 478
571 08:08:03.571159 result report
572 08:08:03.576097 boot times 0Enable ddr reg access
573 08:08:03.581062 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 08:08:03.594848 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 08:08:04.250009 bl2z: ptr: 05129330, size: 00001e40
576 08:08:04.256511 0.0;M3 CHK:0;cm4_sp_mode 0
577 08:08:04.257088 MVN_1=0x00000000
578 08:08:04.257552 MVN_2=0x00000000
579 08:08:04.268044 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 08:08:04.268609 OPS=0x04
581 08:08:04.269076 ring efuse init
582 08:08:04.270968 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 08:08:04.277094 [0.017319 Inits done]
584 08:08:04.277641 secure task start!
585 08:08:04.278100 high task start!
586 08:08:04.278541 low task start!
587 08:08:04.280304 run into bl31
588 08:08:04.289776 NOTICE: BL31: v1.3(release):4fc40b1
589 08:08:04.297567 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 08:08:04.298209 NOTICE: BL31: G12A normal boot!
591 08:08:04.313036 NOTICE: BL31: BL33 decompress pass
592 08:08:04.318684 ERROR: Error initializing runtime service opteed_fast
593 08:08:05.568278 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 08:08:05.569002 bl2_stage_init 0x01
595 08:08:05.569548 bl2_stage_init 0x81
596 08:08:05.573712 hw id: 0x0000 - pwm id 0x01
597 08:08:05.574723 bl2_stage_init 0xc1
598 08:08:05.579350 bl2_stage_init 0x02
599 08:08:05.580057
600 08:08:05.580645 L0:00000000
601 08:08:05.581153 L1:00000703
602 08:08:05.581626 L2:00008067
603 08:08:05.582106 L3:15000000
604 08:08:05.585065 S1:00000000
605 08:08:05.585692 B2:20282000
606 08:08:05.586211 B1:a0f83180
607 08:08:05.586770
608 08:08:05.587376 TE: 72523
609 08:08:05.587897
610 08:08:05.590548 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 08:08:05.591102
612 08:08:05.596139 Board ID = 1
613 08:08:05.596693 Set cpu clk to 24M
614 08:08:05.597148 Set clk81 to 24M
615 08:08:05.600321 Use GP1_pll as DSU clk.
616 08:08:05.600909 DSU clk: 1200 Mhz
617 08:08:05.605204 CPU clk: 1200 MHz
618 08:08:05.605764 Set clk81 to 166.6M
619 08:08:05.610730 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 08:08:05.611311 board id: 1
621 08:08:05.619965 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 08:08:05.630814 fw parse done
623 08:08:05.636212 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 08:08:05.679964 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 08:08:05.691082 PIEI prepare done
626 08:08:05.691690 fastboot data load
627 08:08:05.692213 fastboot data verify
628 08:08:05.696658 verify result: 266
629 08:08:05.702217 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 08:08:05.702769 LPDDR4 probe
631 08:08:05.703250 ddr clk to 1584MHz
632 08:08:05.710253 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 08:08:05.748061
634 08:08:05.748672 dmc_version 0001
635 08:08:05.754932 Check phy result
636 08:08:05.760921 INFO : End of CA training
637 08:08:05.761443 INFO : End of initialization
638 08:08:05.766580 INFO : Training has run successfully!
639 08:08:05.767099 Check phy result
640 08:08:05.772164 INFO : End of initialization
641 08:08:05.772743 INFO : End of read enable training
642 08:08:05.777646 INFO : End of fine write leveling
643 08:08:05.783279 INFO : End of Write leveling coarse delay
644 08:08:05.783791 INFO : Training has run successfully!
645 08:08:05.784285 Check phy result
646 08:08:05.788814 INFO : End of initialization
647 08:08:05.789300 INFO : End of read dq deskew training
648 08:08:05.794451 INFO : End of MPR read delay center optimization
649 08:08:05.800075 INFO : End of write delay center optimization
650 08:08:05.805653 INFO : End of read delay center optimization
651 08:08:05.806197 INFO : End of max read latency training
652 08:08:05.811233 INFO : Training has run successfully!
653 08:08:05.811763 1D training succeed
654 08:08:05.820440 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 08:08:05.868799 Check phy result
656 08:08:05.869370 INFO : End of initialization
657 08:08:05.896156 INFO : End of 2D read delay Voltage center optimization
658 08:08:05.920408 INFO : End of 2D read delay Voltage center optimization
659 08:08:05.977061 INFO : End of 2D write delay Voltage center optimization
660 08:08:06.031023 INFO : End of 2D write delay Voltage center optimization
661 08:08:06.036578 INFO : Training has run successfully!
662 08:08:06.037133
663 08:08:06.037611 channel==0
664 08:08:06.042227 RxClkDly_Margin_A0==78 ps 8
665 08:08:06.042761 TxDqDly_Margin_A0==98 ps 10
666 08:08:06.047817 RxClkDly_Margin_A1==69 ps 7
667 08:08:06.048383 TxDqDly_Margin_A1==98 ps 10
668 08:08:06.048858 TrainedVREFDQ_A0==74
669 08:08:06.053364 TrainedVREFDQ_A1==75
670 08:08:06.053922 VrefDac_Margin_A0==23
671 08:08:06.054382 DeviceVref_Margin_A0==40
672 08:08:06.059155 VrefDac_Margin_A1==23
673 08:08:06.059733 DeviceVref_Margin_A1==39
674 08:08:06.060253
675 08:08:06.060734
676 08:08:06.064718 channel==1
677 08:08:06.065268 RxClkDly_Margin_A0==78 ps 8
678 08:08:06.065751 TxDqDly_Margin_A0==88 ps 9
679 08:08:06.070307 RxClkDly_Margin_A1==78 ps 8
680 08:08:06.070872 TxDqDly_Margin_A1==88 ps 9
681 08:08:06.075827 TrainedVREFDQ_A0==75
682 08:08:06.076401 TrainedVREFDQ_A1==75
683 08:08:06.076882 VrefDac_Margin_A0==22
684 08:08:06.081495 DeviceVref_Margin_A0==39
685 08:08:06.082026 VrefDac_Margin_A1==22
686 08:08:06.087049 DeviceVref_Margin_A1==39
687 08:08:06.087582
688 08:08:06.088098 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 08:08:06.088565
690 08:08:06.120559 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
691 08:08:06.121146 2D training succeed
692 08:08:06.126208 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 08:08:06.131839 auto size-- 65535DDR cs0 size: 2048MB
694 08:08:06.132410 DDR cs1 size: 2048MB
695 08:08:06.137435 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 08:08:06.137965 cs0 DataBus test pass
697 08:08:06.143032 cs1 DataBus test pass
698 08:08:06.143554 cs0 AddrBus test pass
699 08:08:06.144056 cs1 AddrBus test pass
700 08:08:06.144518
701 08:08:06.148589 100bdlr_step_size ps== 471
702 08:08:06.149115 result report
703 08:08:06.154154 boot times 0Enable ddr reg access
704 08:08:06.159429 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 08:08:06.173253 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 08:08:06.832577 bl2z: ptr: 05129330, size: 00001e40
707 08:08:06.841443 0.0;M3 CHK:0;cm4_sp_mode 0
708 08:08:06.842045 MVN_1=0x00000000
709 08:08:06.842543 MVN_2=0x00000000
710 08:08:06.852940 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 08:08:06.853525 OPS=0x04
712 08:08:06.853971 ring efuse init
713 08:08:06.858493 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 08:08:06.858992 [0.017354 Inits done]
715 08:08:06.859428 secure task start!
716 08:08:06.865739 high task start!
717 08:08:06.866219 low task start!
718 08:08:06.866654 run into bl31
719 08:08:06.874345 NOTICE: BL31: v1.3(release):4fc40b1
720 08:08:06.882195 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 08:08:06.882668 NOTICE: BL31: G12A normal boot!
722 08:08:06.897735 NOTICE: BL31: BL33 decompress pass
723 08:08:06.903423 ERROR: Error initializing runtime service opteed_fast
724 08:08:07.698934
725 08:08:07.699610
726 08:08:07.704263 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 08:08:07.704784
728 08:08:07.707770 Model: Libre Computer AML-S905D3-CC Solitude
729 08:08:07.854827 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 08:08:07.870229 DRAM: 2 GiB (effective 3.8 GiB)
731 08:08:07.971222 Core: 406 devices, 33 uclasses, devicetree: separate
732 08:08:07.976130 WDT: Not starting watchdog@f0d0
733 08:08:08.002122 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 08:08:08.014313 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 08:08:08.019277 ** Bad device specification mmc 0 **
736 08:08:08.029345 Card did not respond to voltage select! : -110
737 08:08:08.037114 ** Bad device specification mmc 0 **
738 08:08:08.037630 Couldn't find partition mmc 0
739 08:08:08.045277 Card did not respond to voltage select! : -110
740 08:08:08.050878 ** Bad device specification mmc 0 **
741 08:08:08.051377 Couldn't find partition mmc 0
742 08:08:08.055879 Error: could not access storage.
743 08:08:08.353520 Net: eth0: ethernet@ff3f0000
744 08:08:08.353911 starting USB...
745 08:08:08.598308 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 08:08:08.598929 Starting the controller
747 08:08:08.605085 USB XHCI 1.10
748 08:08:10.161168 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 08:08:10.169465 scanning usb for storage devices... 0 Storage Device(s) found
751 08:08:10.221082 Hit any key to stop autoboot: 1
752 08:08:10.222024 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 08:08:10.222674 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 08:08:10.223198 Setting prompt string to ['=>']
755 08:08:10.223723 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 08:08:10.235474 0
757 08:08:10.236488 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 08:08:10.337861 => setenv autoload no
760 08:08:10.338719 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 08:08:10.344042 setenv autoload no
763 08:08:10.445691 => setenv initrd_high 0xffffffff
764 08:08:10.446499 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 08:08:10.450783 setenv initrd_high 0xffffffff
767 08:08:10.552447 => setenv fdt_high 0xffffffff
768 08:08:10.553227 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 08:08:10.557519 setenv fdt_high 0xffffffff
771 08:08:10.659159 => dhcp
772 08:08:10.659938 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 08:08:10.663246 dhcp
774 08:08:11.870434 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete... done
775 08:08:11.871108 Speed: 1000, full duplex
776 08:08:11.871591 BOOTP broadcast 1
777 08:08:12.118723 BOOTP broadcast 2
778 08:08:12.619771 BOOTP broadcast 3
779 08:08:13.620888 BOOTP broadcast 4
780 08:08:15.621792 BOOTP broadcast 5
781 08:08:15.633959 DHCP client bound to address 192.168.6.12 (3763 ms)
783 08:08:15.735699 => setenv serverip 192.168.6.2
784 08:08:15.736568 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
785 08:08:15.741180 setenv serverip 192.168.6.2
787 08:08:15.842922 => tftpboot 0x01080000 676320/tftp-deploy-eegha1fg/kernel/uImage
788 08:08:15.844130 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
789 08:08:15.850742 tftpboot 0x01080000 676320/tftp-deploy-eegha1fg/kernel/uImage
790 08:08:15.851133 Speed: 1000, full duplex
791 08:08:15.851411 Using ethernet@ff3f0000 device
792 08:08:15.856280 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
793 08:08:15.861840 Filename '676320/tftp-deploy-eegha1fg/kernel/uImage'.
794 08:08:15.865486 Load address: 0x1080000
795 08:08:18.931598 Loading: *################################################## 43.5 MiB
796 08:08:18.932051 14.2 MiB/s
797 08:08:18.932277 done
798 08:08:18.935958 Bytes transferred = 45603392 (2b7da40 hex)
800 08:08:19.037097 => tftpboot 0x08000000 676320/tftp-deploy-eegha1fg/ramdisk/ramdisk.cpio.gz.uboot
801 08:08:19.037653 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
802 08:08:19.044708 tftpboot 0x08000000 676320/tftp-deploy-eegha1fg/ramdisk/ramdisk.cpio.gz.uboot
803 08:08:19.045029 Speed: 1000, full duplex
804 08:08:19.045249 Using ethernet@ff3f0000 device
805 08:08:19.050295 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
806 08:08:19.060057 Filename '676320/tftp-deploy-eegha1fg/ramdisk/ramdisk.cpio.gz.uboot'.
807 08:08:19.060418 Load address: 0x8000000
808 08:08:20.882067 Loading: *################################################# UDP wrong checksum 00000005 00003e81
809 08:08:25.881565 T UDP wrong checksum 00000005 00003e81
810 08:08:35.883622 T T UDP wrong checksum 00000005 00003e81
811 08:08:53.444262 T T T UDP wrong checksum 0000000f 0000a291
812 08:08:55.887566 T UDP wrong checksum 00000005 00003e81
813 08:09:09.933252 T T UDP wrong checksum 000000ff 0000cd3d
814 08:09:09.950346 UDP wrong checksum 000000ff 00006a30
815 08:09:15.892159 T
816 08:09:15.892702 Retry count exceeded; starting again
818 08:09:15.894155 end: 2.4.3 bootloader-commands (duration 00:01:06) [common]
821 08:09:15.895814 end: 2.4 uboot-commands (duration 00:01:25) [common]
823 08:09:15.897008 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
825 08:09:15.897822 end: 2 uboot-action (duration 00:01:25) [common]
827 08:09:15.898918 Cleaning after the job
828 08:09:15.899338 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676320/tftp-deploy-eegha1fg/ramdisk
829 08:09:15.900322 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676320/tftp-deploy-eegha1fg/kernel
830 08:09:15.911664 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676320/tftp-deploy-eegha1fg/dtb
831 08:09:15.912645 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/676320/tftp-deploy-eegha1fg/modules
832 08:09:15.916758 start: 4.1 power-off (timeout 00:00:30) [common]
833 08:09:15.917529 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
834 08:09:15.950940 >> OK - accepted request
835 08:09:15.952263 Returned 0 in 0 seconds
836 08:09:16.053448 end: 4.1 power-off (duration 00:00:00) [common]
838 08:09:16.055056 start: 4.2 read-feedback (timeout 00:10:00) [common]
839 08:09:16.056210 Listened to connection for namespace 'common' for up to 1s
840 08:09:17.056984 Finalising connection for namespace 'common'
841 08:09:17.057776 Disconnecting from shell: Finalise
842 08:09:17.058328 =>
843 08:09:17.159214 end: 4.2 read-feedback (duration 00:00:01) [common]
844 08:09:17.159639 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/676320
845 08:09:17.397150 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/676320
846 08:09:17.397736 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.