Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:40:46.964947 lava-dispatcher, installed at version: 2024.01
2 09:40:46.965759 start: 0 validate
3 09:40:46.966229 Start time: 2024-09-02 09:40:46.966199+00:00 (UTC)
4 09:40:46.966758 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:40:46.967288 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 09:40:47.009102 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:40:47.009680 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240902%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 09:40:47.040044 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:40:47.040668 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240902%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 09:40:48.087259 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:40:48.087746 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240902%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 09:40:48.135011 validate duration: 1.17
14 09:40:48.136539 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:40:48.137143 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:40:48.137712 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:40:48.138781 Not decompressing ramdisk as can be used compressed.
18 09:40:48.139520 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 09:40:48.140043 saving as /var/lib/lava/dispatcher/tmp/690423/tftp-deploy-cnhq0oul/ramdisk/rootfs.cpio.gz
20 09:40:48.140560 total size: 8181887 (7 MB)
21 09:40:48.176437 progress 0 % (0 MB)
22 09:40:48.187464 progress 5 % (0 MB)
23 09:40:48.197740 progress 10 % (0 MB)
24 09:40:48.208483 progress 15 % (1 MB)
25 09:40:48.213749 progress 20 % (1 MB)
26 09:40:48.219514 progress 25 % (1 MB)
27 09:40:48.224841 progress 30 % (2 MB)
28 09:40:48.232647 progress 35 % (2 MB)
29 09:40:48.237902 progress 40 % (3 MB)
30 09:40:48.243541 progress 45 % (3 MB)
31 09:40:48.248868 progress 50 % (3 MB)
32 09:40:48.254561 progress 55 % (4 MB)
33 09:40:48.259827 progress 60 % (4 MB)
34 09:40:48.265501 progress 65 % (5 MB)
35 09:40:48.270818 progress 70 % (5 MB)
36 09:40:48.276756 progress 75 % (5 MB)
37 09:40:48.282165 progress 80 % (6 MB)
38 09:40:48.287966 progress 85 % (6 MB)
39 09:40:48.293305 progress 90 % (7 MB)
40 09:40:48.299001 progress 95 % (7 MB)
41 09:40:48.303928 progress 100 % (7 MB)
42 09:40:48.304632 7 MB downloaded in 0.16 s (47.56 MB/s)
43 09:40:48.305201 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:40:48.306102 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:40:48.306400 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:40:48.306676 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:40:48.307156 downloading http://storage.kernelci.org/next/master/next-20240902/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/kernel/Image
49 09:40:48.307420 saving as /var/lib/lava/dispatcher/tmp/690423/tftp-deploy-cnhq0oul/kernel/Image
50 09:40:48.307627 total size: 45666816 (43 MB)
51 09:40:48.307837 No compression specified
52 09:40:48.346471 progress 0 % (0 MB)
53 09:40:48.375188 progress 5 % (2 MB)
54 09:40:48.404157 progress 10 % (4 MB)
55 09:40:48.433814 progress 15 % (6 MB)
56 09:40:48.462535 progress 20 % (8 MB)
57 09:40:48.491509 progress 25 % (10 MB)
58 09:40:48.521239 progress 30 % (13 MB)
59 09:40:48.549655 progress 35 % (15 MB)
60 09:40:48.579309 progress 40 % (17 MB)
61 09:40:48.608607 progress 45 % (19 MB)
62 09:40:48.637107 progress 50 % (21 MB)
63 09:40:48.666652 progress 55 % (23 MB)
64 09:40:48.695628 progress 60 % (26 MB)
65 09:40:48.725729 progress 65 % (28 MB)
66 09:40:48.755528 progress 70 % (30 MB)
67 09:40:48.786062 progress 75 % (32 MB)
68 09:40:48.816055 progress 80 % (34 MB)
69 09:40:48.845633 progress 85 % (37 MB)
70 09:40:48.876007 progress 90 % (39 MB)
71 09:40:48.905397 progress 95 % (41 MB)
72 09:40:48.934788 progress 100 % (43 MB)
73 09:40:48.935564 43 MB downloaded in 0.63 s (69.36 MB/s)
74 09:40:48.936142 end: 1.2.1 http-download (duration 00:00:01) [common]
76 09:40:48.937054 end: 1.2 download-retry (duration 00:00:01) [common]
77 09:40:48.937373 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:40:48.937673 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:40:48.938195 downloading http://storage.kernelci.org/next/master/next-20240902/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 09:40:48.938519 saving as /var/lib/lava/dispatcher/tmp/690423/tftp-deploy-cnhq0oul/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 09:40:48.938752 total size: 53173 (0 MB)
82 09:40:48.938979 No compression specified
83 09:40:48.983334 progress 61 % (0 MB)
84 09:40:48.984258 progress 100 % (0 MB)
85 09:40:48.984862 0 MB downloaded in 0.05 s (1.10 MB/s)
86 09:40:48.985405 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:40:48.986281 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:40:48.986572 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:40:48.986858 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:40:48.987358 downloading http://storage.kernelci.org/next/master/next-20240902/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/modules.tar.xz
92 09:40:48.987644 saving as /var/lib/lava/dispatcher/tmp/690423/tftp-deploy-cnhq0oul/modules/modules.tar
93 09:40:48.987871 total size: 11549280 (11 MB)
94 09:40:48.988146 Using unxz to decompress xz
95 09:40:49.027153 progress 0 % (0 MB)
96 09:40:49.093263 progress 5 % (0 MB)
97 09:40:49.177092 progress 10 % (1 MB)
98 09:40:49.258321 progress 15 % (1 MB)
99 09:40:49.346806 progress 20 % (2 MB)
100 09:40:49.425547 progress 25 % (2 MB)
101 09:40:49.500881 progress 30 % (3 MB)
102 09:40:49.577971 progress 35 % (3 MB)
103 09:40:49.653226 progress 40 % (4 MB)
104 09:40:49.735204 progress 45 % (4 MB)
105 09:40:49.814450 progress 50 % (5 MB)
106 09:40:49.895548 progress 55 % (6 MB)
107 09:40:49.973136 progress 60 % (6 MB)
108 09:40:50.056516 progress 65 % (7 MB)
109 09:40:50.130394 progress 70 % (7 MB)
110 09:40:50.213299 progress 75 % (8 MB)
111 09:40:50.302880 progress 80 % (8 MB)
112 09:40:50.401199 progress 85 % (9 MB)
113 09:40:50.475163 progress 90 % (9 MB)
114 09:40:50.548386 progress 95 % (10 MB)
115 09:40:50.623123 progress 100 % (11 MB)
116 09:40:50.635416 11 MB downloaded in 1.65 s (6.69 MB/s)
117 09:40:50.636036 end: 1.4.1 http-download (duration 00:00:02) [common]
119 09:40:50.637811 end: 1.4 download-retry (duration 00:00:02) [common]
120 09:40:50.638386 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 09:40:50.638956 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 09:40:50.639497 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:40:50.640075 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 09:40:50.641115 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi
125 09:40:50.642019 makedir: /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin
126 09:40:50.642716 makedir: /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/tests
127 09:40:50.643392 makedir: /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/results
128 09:40:50.644082 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-add-keys
129 09:40:50.645160 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-add-sources
130 09:40:50.646187 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-background-process-start
131 09:40:50.647211 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-background-process-stop
132 09:40:50.648318 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-common-functions
133 09:40:50.649392 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-echo-ipv4
134 09:40:50.650423 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-install-packages
135 09:40:50.651420 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-installed-packages
136 09:40:50.652424 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-os-build
137 09:40:50.653422 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-probe-channel
138 09:40:50.654396 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-probe-ip
139 09:40:50.655367 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-target-ip
140 09:40:50.656381 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-target-mac
141 09:40:50.657357 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-target-storage
142 09:40:50.658346 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-test-case
143 09:40:50.659360 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-test-event
144 09:40:50.660374 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-test-feedback
145 09:40:50.661388 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-test-raise
146 09:40:50.662350 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-test-reference
147 09:40:50.663315 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-test-runner
148 09:40:50.664334 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-test-set
149 09:40:50.665308 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-test-shell
150 09:40:50.666279 Updating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-install-packages (oe)
151 09:40:50.667344 Updating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/bin/lava-installed-packages (oe)
152 09:40:50.668345 Creating /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/environment
153 09:40:50.669135 LAVA metadata
154 09:40:50.669661 - LAVA_JOB_ID=690423
155 09:40:50.670128 - LAVA_DISPATCHER_IP=192.168.6.2
156 09:40:50.670998 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 09:40:50.672999 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 09:40:50.673586 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 09:40:50.673996 skipped lava-vland-overlay
160 09:40:50.674477 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 09:40:50.674978 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 09:40:50.675399 skipped lava-multinode-overlay
163 09:40:50.675872 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 09:40:50.676408 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 09:40:50.676882 Loading test definitions
166 09:40:50.677418 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 09:40:50.677860 Using /lava-690423 at stage 0
168 09:40:50.680063 uuid=690423_1.5.2.4.1 testdef=None
169 09:40:50.680387 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 09:40:50.680653 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 09:40:50.682506 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 09:40:50.683309 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 09:40:50.685570 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 09:40:50.686422 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 09:40:50.688625 runner path: /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/0/tests/0_dmesg test_uuid 690423_1.5.2.4.1
178 09:40:50.689192 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 09:40:50.689958 Creating lava-test-runner.conf files
181 09:40:50.690160 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/690423/lava-overlay-67n3svvi/lava-690423/0 for stage 0
182 09:40:50.690502 - 0_dmesg
183 09:40:50.690851 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 09:40:50.691129 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 09:40:50.714934 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 09:40:50.715333 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 09:40:50.715595 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 09:40:50.715860 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 09:40:50.716148 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 09:40:51.633012 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 09:40:51.633490 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 09:40:51.633759 extracting modules file /var/lib/lava/dispatcher/tmp/690423/tftp-deploy-cnhq0oul/modules/modules.tar to /var/lib/lava/dispatcher/tmp/690423/extract-overlay-ramdisk-ob5co14r/ramdisk
193 09:40:52.953443 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 09:40:52.953905 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 09:40:52.954198 [common] Applying overlay /var/lib/lava/dispatcher/tmp/690423/compress-overlay-30_qmwxt/overlay-1.5.2.5.tar.gz to ramdisk
196 09:40:52.954426 [common] Applying overlay /var/lib/lava/dispatcher/tmp/690423/compress-overlay-30_qmwxt/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/690423/extract-overlay-ramdisk-ob5co14r/ramdisk
197 09:40:52.985138 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 09:40:52.985556 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 09:40:52.985824 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 09:40:52.986049 Converting downloaded kernel to a uImage
201 09:40:52.986365 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/690423/tftp-deploy-cnhq0oul/kernel/Image /var/lib/lava/dispatcher/tmp/690423/tftp-deploy-cnhq0oul/kernel/uImage
202 09:40:53.479231 output: Image Name:
203 09:40:53.479631 output: Created: Mon Sep 2 09:40:52 2024
204 09:40:53.479841 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 09:40:53.480082 output: Data Size: 45666816 Bytes = 44596.50 KiB = 43.55 MiB
206 09:40:53.480287 output: Load Address: 01080000
207 09:40:53.480485 output: Entry Point: 01080000
208 09:40:53.480682 output:
209 09:40:53.481011 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 09:40:53.481276 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 09:40:53.481543 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 09:40:53.481790 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 09:40:53.482043 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 09:40:53.482294 Building ramdisk /var/lib/lava/dispatcher/tmp/690423/extract-overlay-ramdisk-ob5co14r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/690423/extract-overlay-ramdisk-ob5co14r/ramdisk
215 09:40:55.935454 >> 180826 blocks
216 09:41:04.457700 Adding RAMdisk u-boot header.
217 09:41:04.458364 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/690423/extract-overlay-ramdisk-ob5co14r/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/690423/extract-overlay-ramdisk-ob5co14r/ramdisk.cpio.gz.uboot
218 09:41:04.751920 output: Image Name:
219 09:41:04.752552 output: Created: Mon Sep 2 09:41:04 2024
220 09:41:04.752962 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 09:41:04.753365 output: Data Size: 25978415 Bytes = 25369.55 KiB = 24.77 MiB
222 09:41:04.753762 output: Load Address: 00000000
223 09:41:04.754155 output: Entry Point: 00000000
224 09:41:04.754541 output:
225 09:41:04.755594 rename /var/lib/lava/dispatcher/tmp/690423/extract-overlay-ramdisk-ob5co14r/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/690423/tftp-deploy-cnhq0oul/ramdisk/ramdisk.cpio.gz.uboot
226 09:41:04.756326 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 09:41:04.756863 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 09:41:04.757376 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 09:41:04.757824 No LXC device requested
230 09:41:04.758312 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 09:41:04.758808 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 09:41:04.759289 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 09:41:04.759696 Checking files for TFTP limit of 4294967296 bytes.
234 09:41:04.762333 end: 1 tftp-deploy (duration 00:00:17) [common]
235 09:41:04.762896 start: 2 uboot-action (timeout 00:05:00) [common]
236 09:41:04.763411 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 09:41:04.763900 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 09:41:04.764432 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 09:41:04.764956 Using kernel file from prepare-kernel: 690423/tftp-deploy-cnhq0oul/kernel/uImage
240 09:41:04.765568 substitutions:
241 09:41:04.765975 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 09:41:04.766371 - {DTB_ADDR}: 0x01070000
243 09:41:04.766761 - {DTB}: 690423/tftp-deploy-cnhq0oul/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 09:41:04.767156 - {INITRD}: 690423/tftp-deploy-cnhq0oul/ramdisk/ramdisk.cpio.gz.uboot
245 09:41:04.767546 - {KERNEL_ADDR}: 0x01080000
246 09:41:04.767932 - {KERNEL}: 690423/tftp-deploy-cnhq0oul/kernel/uImage
247 09:41:04.768356 - {LAVA_MAC}: None
248 09:41:04.768777 - {PRESEED_CONFIG}: None
249 09:41:04.769166 - {PRESEED_LOCAL}: None
250 09:41:04.769549 - {RAMDISK_ADDR}: 0x08000000
251 09:41:04.769933 - {RAMDISK}: 690423/tftp-deploy-cnhq0oul/ramdisk/ramdisk.cpio.gz.uboot
252 09:41:04.770324 - {ROOT_PART}: None
253 09:41:04.770711 - {ROOT}: None
254 09:41:04.771097 - {SERVER_IP}: 192.168.6.2
255 09:41:04.771484 - {TEE_ADDR}: 0x83000000
256 09:41:04.771868 - {TEE}: None
257 09:41:04.772278 Parsed boot commands:
258 09:41:04.772652 - setenv autoload no
259 09:41:04.773035 - setenv initrd_high 0xffffffff
260 09:41:04.773418 - setenv fdt_high 0xffffffff
261 09:41:04.773802 - dhcp
262 09:41:04.774184 - setenv serverip 192.168.6.2
263 09:41:04.774566 - tftpboot 0x01080000 690423/tftp-deploy-cnhq0oul/kernel/uImage
264 09:41:04.774950 - tftpboot 0x08000000 690423/tftp-deploy-cnhq0oul/ramdisk/ramdisk.cpio.gz.uboot
265 09:41:04.775332 - tftpboot 0x01070000 690423/tftp-deploy-cnhq0oul/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 09:41:04.775716 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 09:41:04.776121 - bootm 0x01080000 0x08000000 0x01070000
268 09:41:04.776602 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 09:41:04.778055 start: 2.3 connect-device (timeout 00:05:00) [common]
271 09:41:04.778484 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 09:41:04.792223 Setting prompt string to ['lava-test: # ']
273 09:41:04.793670 end: 2.3 connect-device (duration 00:00:00) [common]
274 09:41:04.794256 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 09:41:04.794789 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 09:41:04.795300 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 09:41:04.796472 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 09:41:04.828932 >> OK - accepted request
279 09:41:04.831014 Returned 0 in 0 seconds
280 09:41:04.932119 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 09:41:04.933691 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 09:41:04.934246 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 09:41:04.934737 Setting prompt string to ['Hit any key to stop autoboot']
285 09:41:04.935187 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 09:41:04.936787 Trying 192.168.56.21...
287 09:41:04.937269 Connected to conserv1.
288 09:41:04.937693 Escape character is '^]'.
289 09:41:04.938116
290 09:41:04.938543 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 09:41:04.938964
292 09:41:12.227248 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 09:41:12.227884 bl2_stage_init 0x01
294 09:41:12.228379 bl2_stage_init 0x81
295 09:41:12.232927 hw id: 0x0000 - pwm id 0x01
296 09:41:12.233408 bl2_stage_init 0xc1
297 09:41:12.238488 bl2_stage_init 0x02
298 09:41:12.238952
299 09:41:12.239369 L0:00000000
300 09:41:12.239778 L1:00000703
301 09:41:12.240215 L2:00008067
302 09:41:12.240616 L3:15000000
303 09:41:12.244059 S1:00000000
304 09:41:12.244514 B2:20282000
305 09:41:12.244931 B1:a0f83180
306 09:41:12.245335
307 09:41:12.245738 TE: 68055
308 09:41:12.246139
309 09:41:12.249540 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 09:41:12.249994
311 09:41:12.255163 Board ID = 1
312 09:41:12.255620 Set cpu clk to 24M
313 09:41:12.256060 Set clk81 to 24M
314 09:41:12.260752 Use GP1_pll as DSU clk.
315 09:41:12.261200 DSU clk: 1200 Mhz
316 09:41:12.261608 CPU clk: 1200 MHz
317 09:41:12.266353 Set clk81 to 166.6M
318 09:41:12.271938 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 09:41:12.272411 board id: 1
320 09:41:12.279259 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 09:41:12.289924 fw parse done
322 09:41:12.295928 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 09:41:12.338499 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 09:41:12.349502 PIEI prepare done
325 09:41:12.349967 fastboot data load
326 09:41:12.350388 fastboot data verify
327 09:41:12.354967 verify result: 266
328 09:41:12.360571 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 09:41:12.361026 LPDDR4 probe
330 09:41:12.361434 ddr clk to 1584MHz
331 09:41:12.368602 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 09:41:12.405816
333 09:41:12.406278 dmc_version 0001
334 09:41:12.412249 Check phy result
335 09:41:12.418402 INFO : End of CA training
336 09:41:12.418857 INFO : End of initialization
337 09:41:12.424084 INFO : Training has run successfully!
338 09:41:12.424541 Check phy result
339 09:41:12.429614 INFO : End of initialization
340 09:41:12.430070 INFO : End of read enable training
341 09:41:12.435183 INFO : End of fine write leveling
342 09:41:12.440785 INFO : End of Write leveling coarse delay
343 09:41:12.441238 INFO : Training has run successfully!
344 09:41:12.441645 Check phy result
345 09:41:12.446435 INFO : End of initialization
346 09:41:12.446887 INFO : End of read dq deskew training
347 09:41:12.452090 INFO : End of MPR read delay center optimization
348 09:41:12.457625 INFO : End of write delay center optimization
349 09:41:12.463193 INFO : End of read delay center optimization
350 09:41:12.463645 INFO : End of max read latency training
351 09:41:12.468792 INFO : Training has run successfully!
352 09:41:12.469245 1D training succeed
353 09:41:12.477970 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 09:41:12.525589 Check phy result
355 09:41:12.526064 INFO : End of initialization
356 09:41:12.548038 INFO : End of 2D read delay Voltage center optimization
357 09:41:12.567145 INFO : End of 2D read delay Voltage center optimization
358 09:41:12.619012 INFO : End of 2D write delay Voltage center optimization
359 09:41:12.668357 INFO : End of 2D write delay Voltage center optimization
360 09:41:12.673898 INFO : Training has run successfully!
361 09:41:12.674407
362 09:41:12.674826 channel==0
363 09:41:12.679431 RxClkDly_Margin_A0==78 ps 8
364 09:41:12.679974 TxDqDly_Margin_A0==98 ps 10
365 09:41:12.682756 RxClkDly_Margin_A1==88 ps 9
366 09:41:12.683239 TxDqDly_Margin_A1==88 ps 9
367 09:41:12.688600 TrainedVREFDQ_A0==74
368 09:41:12.689209 TrainedVREFDQ_A1==74
369 09:41:12.689863 VrefDac_Margin_A0==24
370 09:41:12.693923 DeviceVref_Margin_A0==40
371 09:41:12.694420 VrefDac_Margin_A1==22
372 09:41:12.699463 DeviceVref_Margin_A1==40
373 09:41:12.700025
374 09:41:12.700532
375 09:41:12.701025 channel==1
376 09:41:12.701509 RxClkDly_Margin_A0==78 ps 8
377 09:41:12.702957 TxDqDly_Margin_A0==98 ps 10
378 09:41:12.708576 RxClkDly_Margin_A1==88 ps 9
379 09:41:12.709039 TxDqDly_Margin_A1==78 ps 8
380 09:41:12.709452 TrainedVREFDQ_A0==78
381 09:41:12.715020 TrainedVREFDQ_A1==77
382 09:41:12.715518 VrefDac_Margin_A0==22
383 09:41:12.719776 DeviceVref_Margin_A0==36
384 09:41:12.720557 VrefDac_Margin_A1==22
385 09:41:12.721081 DeviceVref_Margin_A1==37
386 09:41:12.721576
387 09:41:12.729021 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 09:41:12.730044
389 09:41:12.754467 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000016 00000017 00000016 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000014 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
390 09:41:12.760208 2D training succeed
391 09:41:12.765708 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 09:41:12.766286 auto size-- 65535DDR cs0 size: 2048MB
393 09:41:12.771319 DDR cs1 size: 2048MB
394 09:41:12.771893 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 09:41:12.776946 cs0 DataBus test pass
396 09:41:12.777537 cs1 DataBus test pass
397 09:41:12.782533 cs0 AddrBus test pass
398 09:41:12.783117 cs1 AddrBus test pass
399 09:41:12.783537
400 09:41:12.783946 100bdlr_step_size ps== 478
401 09:41:12.788215 result report
402 09:41:12.788792 boot times 0Enable ddr reg access
403 09:41:12.796514 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 09:41:12.810439 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 09:41:13.466483 bl2z: ptr: 05129330, size: 00001e40
406 09:41:13.474330 0.0;M3 CHK:0;cm4_sp_mode 0
407 09:41:13.474814 MVN_1=0x00000000
408 09:41:13.475231 MVN_2=0x00000000
409 09:41:13.485801 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 09:41:13.486357 OPS=0x04
411 09:41:13.486835 ring efuse init
412 09:41:13.491447 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 09:41:13.491926 [0.017320 Inits done]
414 09:41:13.492463 secure task start!
415 09:41:13.499494 high task start!
416 09:41:13.499964 low task start!
417 09:41:13.500414 run into bl31
418 09:41:13.508237 NOTICE: BL31: v1.3(release):4fc40b1
419 09:41:13.515889 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 09:41:13.516386 NOTICE: BL31: G12A normal boot!
421 09:41:13.531476 NOTICE: BL31: BL33 decompress pass
422 09:41:13.537232 ERROR: Error initializing runtime service opteed_fast
423 09:41:14.778099 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 09:41:14.778736 bl2_stage_init 0x01
425 09:41:14.779186 bl2_stage_init 0x81
426 09:41:14.783693 hw id: 0x0000 - pwm id 0x01
427 09:41:14.784215 bl2_stage_init 0xc1
428 09:41:14.789330 bl2_stage_init 0x02
429 09:41:14.789815
430 09:41:14.790261 L0:00000000
431 09:41:14.790698 L1:00000703
432 09:41:14.791131 L2:00008067
433 09:41:14.791566 L3:15000000
434 09:41:14.794813 S1:00000000
435 09:41:14.795291 B2:20282000
436 09:41:14.795752 B1:a0f83180
437 09:41:14.796223
438 09:41:14.796665 TE: 68790
439 09:41:14.797098
440 09:41:14.800436 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 09:41:14.800910
442 09:41:14.806019 Board ID = 1
443 09:41:14.806499 Set cpu clk to 24M
444 09:41:14.806934 Set clk81 to 24M
445 09:41:14.811644 Use GP1_pll as DSU clk.
446 09:41:14.812148 DSU clk: 1200 Mhz
447 09:41:14.812591 CPU clk: 1200 MHz
448 09:41:14.817346 Set clk81 to 166.6M
449 09:41:14.822852 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 09:41:14.823332 board id: 1
451 09:41:14.830027 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 09:41:14.840663 fw parse done
453 09:41:14.846649 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 09:41:14.889494 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 09:41:14.900405 PIEI prepare done
456 09:41:14.900906 fastboot data load
457 09:41:14.901346 fastboot data verify
458 09:41:14.905907 verify result: 266
459 09:41:14.911092 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 09:41:14.911589 LPDDR4 probe
461 09:41:16.266954 ddr c< SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
462 09:41:16.267323 bl2_stage_init 0x01
463 09:41:16.267534 bl2_stage_init 0x81
464 09:41:16.272483 hw id: 0x0000 - pwm id 0x01
465 09:41:16.272732 bl2_stage_init 0xc1
466 09:41:16.277015 bl2_stage_init 0x02
467 09:41:16.277254
468 09:41:16.277458 L0:00000000
469 09:41:16.277656 L1:00000703
470 09:41:16.277976 L2:00008067
471 09:41:16.282586 L3:15000000
472 09:41:16.282816 S1:00000000
473 09:41:16.283016 B2:20282000
474 09:41:16.283211 B1:a0f83180
475 09:41:16.283435
476 09:41:16.283633 TE: 68000
477 09:41:16.283829
478 09:41:16.293692 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
479 09:41:16.293939
480 09:41:16.294141 Board ID = 1
481 09:41:16.294335 Set cpu clk to 24M
482 09:41:16.294528 Set clk81 to 24M
483 09:41:16.299271 Use GP1_pll as DSU clk.
484 09:41:16.299500 DSU clk: 1200 Mhz
485 09:41:16.299701 CPU clk: 1200 MHz
486 09:41:16.304853 Set clk81 to 166.6M
487 09:41:16.310596 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
488 09:41:16.310998 board id: 1
489 09:41:16.318820 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
490 09:41:16.329494 fw parse done
491 09:41:16.335544 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
492 09:41:16.378149 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
493 09:41:16.389111 PIEI prepare done
494 09:41:16.389776 fastboot data load
495 09:41:16.390050 fastboot data verify
496 09:41:16.394877 verify result: 266
497 09:41:16.400928 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
498 09:41:16.401716 LPDDR4 probe
499 09:41:16.402532 ddr clk to 1584MHz
500 09:41:16.408360 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
501 09:41:16.445567
502 09:41:16.446171 dmc_version 0001
503 09:41:16.452467 Check phy result
504 09:41:16.458120 INFO : End of CA training
505 09:41:16.458652 INFO : End of initialization
506 09:41:16.463832 INFO : Training has run successfully!
507 09:41:16.464391 Check phy result
508 09:41:16.469423 INFO : End of initialization
509 09:41:16.470004 INFO : End of read enable training
510 09:41:16.473402 INFO : End of fine write leveling
511 09:41:16.478466 INFO : End of Write leveling coarse delay
512 09:41:16.483884 INFO : Training has run successfully!
513 09:41:16.484442 Check phy result
514 09:41:16.484845 INFO : End of initialization
515 09:41:16.489499 INFO : End of read dq deskew training
516 09:41:16.492838 INFO : End of MPR read delay center optimization
517 09:41:16.498302 INFO : End of write delay center optimization
518 09:41:16.504052 INFO : End of read delay center optimization
519 09:41:16.504650 INFO : End of max read latency training
520 09:41:16.533047 INFO : Training has run successfully!
521 09:41:16.533470 1D training succeed
522 09:41:16.533963 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
523 09:41:16.564697 Check phy result
524 09:41:16.565066 INFO : End of initialization
525 09:41:16.587930 INFO : End of 2D read delay Voltage center optimization
526 09:41:16.606955 INFO : End of 2D read delay Voltage center optimization
527 09:41:16.658673 INFO : End of 2D write delay Voltage center optimization
528 09:41:16.707909 INFO : End of 2D write delay Voltage center optimization
529 09:41:16.713481 INFO : Training has run successfully!
530 09:41:16.713973
531 09:41:16.714399 channel==0
532 09:41:16.719049 RxClkDly_Margin_A0==78 ps 8
533 09:41:16.719539 TxDqDly_Margin_A0==98 ps 10
534 09:41:16.724704 RxClkDly_Margin_A1==88 ps 9
535 09:41:16.725196 TxDqDly_Margin_A1==88 ps 9
536 09:41:16.725618 TrainedVREFDQ_A0==74
537 09:41:16.730281 TrainedVREFDQ_A1==74
538 09:41:16.730783 VrefDac_Margin_A0==24
539 09:41:16.731201 DeviceVref_Margin_A0==40
540 09:41:16.735865 VrefDac_Margin_A1==23
541 09:41:16.736378 DeviceVref_Margin_A1==40
542 09:41:16.736799
543 09:41:16.737207
544 09:41:16.737617 channel==1
545 09:41:16.741639 RxClkDly_Margin_A0==78 ps 8
546 09:41:16.742124 TxDqDly_Margin_A0==98 ps 10
547 09:41:16.747086 RxClkDly_Margin_A1==88 ps 9
548 09:41:16.747572 TxDqDly_Margin_A1==78 ps 8
549 09:41:16.752739 TrainedVREFDQ_A0==78
550 09:41:16.753223 TrainedVREFDQ_A1==75
551 09:41:16.753642 VrefDac_Margin_A0==22
552 09:41:16.758297 DeviceVref_Margin_A0==36
553 09:41:16.758776 VrefDac_Margin_A1==22
554 09:41:16.763899 DeviceVref_Margin_A1==39
555 09:41:16.764426
556 09:41:16.764845 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
557 09:41:16.765245
558 09:41:16.797438 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000014 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000014 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
559 09:41:16.797966 2D training succeed
560 09:41:16.803069 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
561 09:41:16.808743 auto size-- 65535DDR cs0 size: 2048MB
562 09:41:16.809233 DDR cs1 size: 2048MB
563 09:41:16.814265 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
564 09:41:16.814752 cs0 DataBus test pass
565 09:41:16.819888 cs1 DataBus test pass
566 09:41:16.820412 cs0 AddrBus test pass
567 09:41:16.820827 cs1 AddrBus test pass
568 09:41:16.821232
569 09:41:16.825497 100bdlr_step_size ps== 478
570 09:41:16.826002 result report
571 09:41:16.831049 boot times 0Enable ddr reg access
572 09:41:16.835296 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
573 09:41:16.849382 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
574 09:41:17.504914 bl2z: ptr: 05129330, size: 00001e40
575 09:41:17.511861 0.0;M3 CHK:0;cm4_sp_mode 0
576 09:41:17.512403 MVN_1=0x00000000
577 09:41:17.512846 MVN_2=0x00000000
578 09:41:17.523227 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
579 09:41:17.523706 OPS=0x04
580 09:41:17.524156 ring efuse init
581 09:41:17.528892 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
582 09:41:17.529365 [0.017319 Inits done]
583 09:41:17.529780 secure task start!
584 09:41:17.536178 high task start!
585 09:41:17.536639 low task start!
586 09:41:17.537050 run into bl31
587 09:41:17.544783 NOTICE: BL31: v1.3(release):4fc40b1
588 09:41:17.552553 NOTICE: BL31: Built : 15:57:33, May 22 2019
589 09:41:17.553024 NOTICE: BL31: G12A normal boot!
590 09:41:17.568152 NOTICE: BL31: BL33 decompress pass
591 09:41:17.573094 ERROR: Error initializing runtime service opteed_fast
592 09:41:18.818637 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
593 09:41:18.819076 bl2_stage_init 0x01
594 09:41:18.819417 bl2_stage_init 0x81
595 09:41:18.824098 hw id: 0x0000 - pwm id 0x01
596 09:41:18.824671 bl2_stage_init 0xc1
597 09:41:18.829668 bl2_stage_init 0x02
598 09:41:18.830229
599 09:41:18.830716 L0:00000000
600 09:41:18.831192 L1:00000703
601 09:41:18.831657 L2:00008067
602 09:41:18.832154 L3:15000000
603 09:41:18.835222 S1:00000000
604 09:41:18.835728 B2:20282000
605 09:41:18.836196 B1:a0f83180
606 09:41:18.836617
607 09:41:18.837031 TE: 69102
608 09:41:18.837446
609 09:41:18.840755 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
610 09:41:18.841246
611 09:41:18.846422 Board ID = 1
612 09:41:18.846923 Set cpu clk to 24M
613 09:41:18.847349 Set clk81 to 24M
614 09:41:18.852072 Use GP1_pll as DSU clk.
615 09:41:18.852572 DSU clk: 1200 Mhz
616 09:41:18.852993 CPU clk: 1200 MHz
617 09:41:18.857491 Set clk81 to 166.6M
618 09:41:18.863212 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
619 09:41:18.863711 board id: 1
620 09:41:18.870370 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
621 09:41:18.881082 fw parse done
622 09:41:18.887072 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
623 09:41:18.929502 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
624 09:41:18.940531 PIEI prepare done
625 09:41:18.941027 fastboot data load
626 09:41:18.941457 fastboot data verify
627 09:41:18.946063 verify result: 266
628 09:41:18.951628 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
629 09:41:18.952161 LPDDR4 probe
630 09:41:18.952600 ddr clk to 1584MHz
631 09:41:18.959772 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
632 09:41:18.996918
633 09:41:18.997432 dmc_version 0001
634 09:41:19.003546 Check phy result
635 09:41:19.009496 INFO : End of CA training
636 09:41:19.009988 INFO : End of initialization
637 09:41:19.015074 INFO : Training has run successfully!
638 09:41:19.015553 Check phy result
639 09:41:19.020685 INFO : End of initialization
640 09:41:19.021179 INFO : End of read enable training
641 09:41:19.026289 INFO : End of fine write leveling
642 09:41:19.031996 INFO : End of Write leveling coarse delay
643 09:41:19.032492 INFO : Training has run successfully!
644 09:41:19.032911 Check phy result
645 09:41:19.037472 INFO : End of initialization
646 09:41:19.037963 INFO : End of read dq deskew training
647 09:41:19.043115 INFO : End of MPR read delay center optimization
648 09:41:19.048657 INFO : End of write delay center optimization
649 09:41:19.054286 INFO : End of read delay center optimization
650 09:41:19.054773 INFO : End of max read latency training
651 09:41:19.060022 INFO : Training has run successfully!
652 09:41:19.060515 1D training succeed
653 09:41:19.069046 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
654 09:41:19.116631 Check phy result
655 09:41:19.117141 INFO : End of initialization
656 09:41:19.138368 INFO : End of 2D read delay Voltage center optimization
657 09:41:19.158178 INFO : End of 2D read delay Voltage center optimization
658 09:41:19.210132 INFO : End of 2D write delay Voltage center optimization
659 09:41:19.259233 INFO : End of 2D write delay Voltage center optimization
660 09:41:19.264963 INFO : Training has run successfully!
661 09:41:19.265467
662 09:41:19.265894 channel==0
663 09:41:19.270483 RxClkDly_Margin_A0==88 ps 9
664 09:41:19.270979 TxDqDly_Margin_A0==98 ps 10
665 09:41:19.276089 RxClkDly_Margin_A1==88 ps 9
666 09:41:19.276585 TxDqDly_Margin_A1==98 ps 10
667 09:41:19.277014 TrainedVREFDQ_A0==74
668 09:41:19.281672 TrainedVREFDQ_A1==75
669 09:41:19.282157 VrefDac_Margin_A0==24
670 09:41:19.282574 DeviceVref_Margin_A0==40
671 09:41:19.287283 VrefDac_Margin_A1==23
672 09:41:19.287776 DeviceVref_Margin_A1==39
673 09:41:19.288237
674 09:41:19.288655
675 09:41:19.292913 channel==1
676 09:41:19.293403 RxClkDly_Margin_A0==78 ps 8
677 09:41:19.293818 TxDqDly_Margin_A0==98 ps 10
678 09:41:19.298455 RxClkDly_Margin_A1==88 ps 9
679 09:41:19.298945 TxDqDly_Margin_A1==78 ps 8
680 09:41:19.304084 TrainedVREFDQ_A0==78
681 09:41:19.304571 TrainedVREFDQ_A1==75
682 09:41:19.304987 VrefDac_Margin_A0==22
683 09:41:19.309716 DeviceVref_Margin_A0==36
684 09:41:19.310219 VrefDac_Margin_A1==21
685 09:41:19.315328 DeviceVref_Margin_A1==39
686 09:41:19.315831
687 09:41:19.316324 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
688 09:41:19.316772
689 09:41:19.348933 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000016 dram_vref_reg_value 0x 00000062
690 09:41:19.349498 2D training succeed
691 09:41:19.354504 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
692 09:41:19.360127 auto size-- 65535DDR cs0 size: 2048MB
693 09:41:19.360642 DDR cs1 size: 2048MB
694 09:41:19.365656 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
695 09:41:19.366166 cs0 DataBus test pass
696 09:41:19.371239 cs1 DataBus test pass
697 09:41:19.371751 cs0 AddrBus test pass
698 09:41:19.372276 cs1 AddrBus test pass
699 09:41:19.372720
700 09:41:19.377085 100bdlr_step_size ps== 478
701 09:41:19.377617 result report
702 09:41:19.382539 boot times 0Enable ddr reg access
703 09:41:19.387781 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
704 09:41:19.401584 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
705 09:41:20.056723 bl2z: ptr: 05129330, size: 00001e40
706 09:41:20.065263 0.0;M3 CHK:0;cm4_sp_mode 0
707 09:41:20.065808 MVN_1=0x00000000
708 09:41:20.066248 MVN_2=0x00000000
709 09:41:20.076598 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
710 09:41:20.077123 OPS=0x04
711 09:41:20.077632 ring efuse init
712 09:41:20.082392 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
713 09:41:20.083244 [0.017319 Inits done]
714 09:41:20.084099 secure task start!
715 09:41:20.089922 high task start!
716 09:41:20.090761 low task start!
717 09:41:20.091485 run into bl31
718 09:41:20.098594 NOTICE: BL31: v1.3(release):4fc40b1
719 09:41:20.105598 NOTICE: BL31: Built : 15:57:33, May 22 2019
720 09:41:20.106435 NOTICE: BL31: G12A normal boot!
721 09:41:20.121825 NOTICE: BL31: BL33 decompress pass
722 09:41:20.127661 ERROR: Error initializing runtime service opteed_fast
723 09:41:20.922786
724 09:41:20.923374
725 09:41:20.928336 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
726 09:41:20.928860
727 09:41:20.931712 Model: Libre Computer AML-S905D3-CC Solitude
728 09:41:21.078720 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
729 09:41:21.094134 DRAM: 2 GiB (effective 3.8 GiB)
730 09:41:21.195078 Core: 406 devices, 33 uclasses, devicetree: separate
731 09:41:21.200965 WDT: Not starting watchdog@f0d0
732 09:41:21.226001 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
733 09:41:21.238246 Loading Environment from FAT... Card did not respond to voltage select! : -110
734 09:41:21.243212 ** Bad device specification mmc 0 **
735 09:41:21.253277 Card did not respond to voltage select! : -110
736 09:41:21.260947 ** Bad device specification mmc 0 **
737 09:41:21.261452 Couldn't find partition mmc 0
738 09:41:21.269316 Card did not respond to voltage select! : -110
739 09:41:21.274854 ** Bad device specification mmc 0 **
740 09:41:21.275371 Couldn't find partition mmc 0
741 09:41:21.279900 Error: could not access storage.
742 09:41:21.577190 Net: eth0: ethernet@ff3f0000
743 09:41:21.577576 starting USB...
744 09:41:21.821921 Bus usb@ff500000: Register 3000140 NbrPorts 3
745 09:41:21.822510 Starting the controller
746 09:41:21.828900 USB XHCI 1.10
747 09:41:23.385133 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
748 09:41:23.393628 scanning usb for storage devices... 0 Storage Device(s) found
750 09:41:23.444620 Hit any key to stop autoboot: 1
751 09:41:23.445655 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
752 09:41:23.446294 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
753 09:41:23.446788 Setting prompt string to ['=>']
754 09:41:23.447265 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
755 09:41:23.459785 0
756 09:41:23.460767 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
758 09:41:23.562200 => setenv autoload no
759 09:41:23.563048 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
760 09:41:23.567954 setenv autoload no
762 09:41:23.669628 => setenv initrd_high 0xffffffff
763 09:41:23.670427 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
764 09:41:23.674811 setenv initrd_high 0xffffffff
766 09:41:23.776450 => setenv fdt_high 0xffffffff
767 09:41:23.777226 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
768 09:41:23.780803 setenv fdt_high 0xffffffff
770 09:41:23.882386 => dhcp
771 09:41:23.883137 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
772 09:41:23.887240 dhcp
773 09:41:24.442741 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
774 09:41:24.443340 Speed: 1000, full duplex
775 09:41:24.443751 BOOTP broadcast 1
776 09:41:24.690770 BOOTP broadcast 2
777 09:41:25.190664 BOOTP broadcast 3
778 09:41:26.191818 BOOTP broadcast 4
779 09:41:28.193745 BOOTP broadcast 5
780 09:41:28.205439 DHCP client bound to address 192.168.6.12 (3763 ms)
782 09:41:28.306930 => setenv serverip 192.168.6.2
783 09:41:28.307537 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
784 09:41:28.311642 setenv serverip 192.168.6.2
786 09:41:28.412881 => tftpboot 0x01080000 690423/tftp-deploy-cnhq0oul/kernel/uImage
787 09:41:28.413730 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
788 09:41:28.419946 tftpboot 0x01080000 690423/tftp-deploy-cnhq0oul/kernel/uImage
789 09:41:28.420275 Speed: 1000, full duplex
790 09:41:28.420493 Using ethernet@ff3f0000 device
791 09:41:28.425471 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
792 09:41:28.431064 Filename '690423/tftp-deploy-cnhq0oul/kernel/uImage'.
793 09:41:28.434858 Load address: 0x1080000
794 09:41:31.754879 Loading: *################################################## 43.6 MiB
795 09:41:31.756037 13.1 MiB/s
796 09:41:31.757837 done
797 09:41:31.759462 Bytes transferred = 45666880 (2b8d240 hex)
799 09:41:31.861591 => tftpboot 0x08000000 690423/tftp-deploy-cnhq0oul/ramdisk/ramdisk.cpio.gz.uboot
800 09:41:31.862483 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
801 09:41:31.869231 tftpboot 0x08000000 690423/tftp-deploy-cnhq0oul/ramdisk/ramdisk.cpio.gz.uboot
802 09:41:31.869735 Speed: 1000, full duplex
803 09:41:31.870156 Using ethernet@ff3f0000 device
804 09:41:31.874691 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
805 09:41:31.884466 Filename '690423/tftp-deploy-cnhq0oul/ramdisk/ramdisk.cpio.gz.uboot'.
806 09:41:31.884977 Load address: 0x8000000
807 09:41:33.678607 Loading: *################################################# UDP wrong checksum 00000005 00003007
808 09:41:35.033207 UDP wrong checksum 000000ff 00003058
809 09:41:35.068648 UDP wrong checksum 000000ff 0000b74a
810 09:41:38.678617 T UDP wrong checksum 00000005 00003007
811 09:41:48.680574 T T UDP wrong checksum 00000005 00003007
812 09:41:55.071253 T UDP wrong checksum 00000005 00005f97
813 09:42:08.684875 T T T UDP wrong checksum 00000005 00003007
814 09:42:14.788873 T UDP wrong checksum 000000ff 0000e6a9
815 09:42:14.823166 UDP wrong checksum 000000ff 0000769c
816 09:42:28.688774 T T
817 09:42:28.689419 Retry count exceeded; starting again
819 09:42:28.690887 end: 2.4.3 bootloader-commands (duration 00:01:05) [common]
822 09:42:28.692850 end: 2.4 uboot-commands (duration 00:01:24) [common]
824 09:42:28.694276 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
826 09:42:28.695375 end: 2 uboot-action (duration 00:01:24) [common]
828 09:42:28.696966 Cleaning after the job
829 09:42:28.697528 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/690423/tftp-deploy-cnhq0oul/ramdisk
830 09:42:28.698878 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/690423/tftp-deploy-cnhq0oul/kernel
831 09:42:28.742989 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/690423/tftp-deploy-cnhq0oul/dtb
832 09:42:28.743966 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/690423/tftp-deploy-cnhq0oul/modules
833 09:42:28.763937 start: 4.1 power-off (timeout 00:00:30) [common]
834 09:42:28.764649 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
835 09:42:28.797185 >> OK - accepted request
836 09:42:28.799197 Returned 0 in 0 seconds
837 09:42:28.899948 end: 4.1 power-off (duration 00:00:00) [common]
839 09:42:28.900987 start: 4.2 read-feedback (timeout 00:10:00) [common]
840 09:42:28.901639 Listened to connection for namespace 'common' for up to 1s
841 09:42:29.902438 Finalising connection for namespace 'common'
842 09:42:29.903193 Disconnecting from shell: Finalise
843 09:42:29.903734 =>
844 09:42:30.004820 end: 4.2 read-feedback (duration 00:00:01) [common]
845 09:42:30.005533 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/690423
846 09:42:30.322038 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/690423
847 09:42:30.322636 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.