Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:54:27.521120 lava-dispatcher, installed at version: 2024.01
2 09:54:27.521937 start: 0 validate
3 09:54:27.522400 Start time: 2024-09-02 09:54:27.522370+00:00 (UTC)
4 09:54:27.522895 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:54:27.523411 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 09:54:27.559913 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:54:27.560536 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240902%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 09:54:28.611647 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:54:28.612322 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240902%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 09:54:35.678332 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:54:35.678843 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240902%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 09:54:36.719150 validate duration: 9.20
14 09:54:36.720206 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:54:36.720558 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:54:36.720852 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:54:36.721534 Not decompressing ramdisk as can be used compressed.
18 09:54:36.722006 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 09:54:36.722244 saving as /var/lib/lava/dispatcher/tmp/690465/tftp-deploy-rznc7pzh/ramdisk/rootfs.cpio.gz
20 09:54:36.722489 total size: 8181887 (7 MB)
21 09:54:36.756106 progress 0 % (0 MB)
22 09:54:36.768309 progress 5 % (0 MB)
23 09:54:36.779870 progress 10 % (0 MB)
24 09:54:36.791418 progress 15 % (1 MB)
25 09:54:36.797154 progress 20 % (1 MB)
26 09:54:36.802898 progress 25 % (1 MB)
27 09:54:36.808256 progress 30 % (2 MB)
28 09:54:36.813916 progress 35 % (2 MB)
29 09:54:36.819233 progress 40 % (3 MB)
30 09:54:36.825143 progress 45 % (3 MB)
31 09:54:36.830508 progress 50 % (3 MB)
32 09:54:36.836449 progress 55 % (4 MB)
33 09:54:36.841851 progress 60 % (4 MB)
34 09:54:36.847693 progress 65 % (5 MB)
35 09:54:36.853083 progress 70 % (5 MB)
36 09:54:36.858966 progress 75 % (5 MB)
37 09:54:36.864428 progress 80 % (6 MB)
38 09:54:36.870125 progress 85 % (6 MB)
39 09:54:36.875356 progress 90 % (7 MB)
40 09:54:36.881027 progress 95 % (7 MB)
41 09:54:36.885952 progress 100 % (7 MB)
42 09:54:36.886608 7 MB downloaded in 0.16 s (47.55 MB/s)
43 09:54:36.887162 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:54:36.888256 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:54:36.889011 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:54:36.889602 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:54:36.890463 downloading http://storage.kernelci.org/next/master/next-20240902/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 09:54:36.890956 saving as /var/lib/lava/dispatcher/tmp/690465/tftp-deploy-rznc7pzh/kernel/Image
50 09:54:36.891411 total size: 65890816 (62 MB)
51 09:54:36.891866 No compression specified
52 09:54:36.927261 progress 0 % (0 MB)
53 09:54:36.968217 progress 5 % (3 MB)
54 09:54:37.010178 progress 10 % (6 MB)
55 09:54:37.048979 progress 15 % (9 MB)
56 09:54:37.088808 progress 20 % (12 MB)
57 09:54:37.127700 progress 25 % (15 MB)
58 09:54:37.166823 progress 30 % (18 MB)
59 09:54:37.205732 progress 35 % (22 MB)
60 09:54:37.244490 progress 40 % (25 MB)
61 09:54:37.283310 progress 45 % (28 MB)
62 09:54:37.324573 progress 50 % (31 MB)
63 09:54:37.364987 progress 55 % (34 MB)
64 09:54:37.416259 progress 60 % (37 MB)
65 09:54:37.455249 progress 65 % (40 MB)
66 09:54:37.495444 progress 70 % (44 MB)
67 09:54:37.549662 progress 75 % (47 MB)
68 09:54:37.590750 progress 80 % (50 MB)
69 09:54:37.631159 progress 85 % (53 MB)
70 09:54:37.688031 progress 90 % (56 MB)
71 09:54:37.729316 progress 95 % (59 MB)
72 09:54:37.768727 progress 100 % (62 MB)
73 09:54:37.769500 62 MB downloaded in 0.88 s (71.56 MB/s)
74 09:54:37.769996 end: 1.2.1 http-download (duration 00:00:01) [common]
76 09:54:37.770807 end: 1.2 download-retry (duration 00:00:01) [common]
77 09:54:37.771084 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:54:37.771346 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:54:37.771816 downloading http://storage.kernelci.org/next/master/next-20240902/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 09:54:37.772124 saving as /var/lib/lava/dispatcher/tmp/690465/tftp-deploy-rznc7pzh/dtb/meson-g12b-a311d-libretech-cc.dtb
81 09:54:37.772335 total size: 54667 (0 MB)
82 09:54:37.772545 No compression specified
83 09:54:37.815114 progress 59 % (0 MB)
84 09:54:37.816007 progress 100 % (0 MB)
85 09:54:37.816628 0 MB downloaded in 0.04 s (1.18 MB/s)
86 09:54:37.817172 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:54:37.818118 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:54:37.818413 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:54:37.818703 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:54:37.819232 downloading http://storage.kernelci.org/next/master/next-20240902/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 09:54:37.819517 saving as /var/lib/lava/dispatcher/tmp/690465/tftp-deploy-rznc7pzh/modules/modules.tar
93 09:54:37.819746 total size: 16208112 (15 MB)
94 09:54:37.819969 Using unxz to decompress xz
95 09:54:37.864739 progress 0 % (0 MB)
96 09:54:37.984289 progress 5 % (0 MB)
97 09:54:38.107711 progress 10 % (1 MB)
98 09:54:38.226588 progress 15 % (2 MB)
99 09:54:38.350236 progress 20 % (3 MB)
100 09:54:38.492107 progress 25 % (3 MB)
101 09:54:38.936705 progress 30 % (4 MB)
102 09:54:39.070007 progress 35 % (5 MB)
103 09:54:39.188395 progress 40 % (6 MB)
104 09:54:39.318743 progress 45 % (6 MB)
105 09:54:39.444445 progress 50 % (7 MB)
106 09:54:39.570260 progress 55 % (8 MB)
107 09:54:39.687330 progress 60 % (9 MB)
108 09:54:39.809480 progress 65 % (10 MB)
109 09:54:39.934741 progress 70 % (10 MB)
110 09:54:40.073709 progress 75 % (11 MB)
111 09:54:40.211557 progress 80 % (12 MB)
112 09:54:40.323835 progress 85 % (13 MB)
113 09:54:40.442463 progress 90 % (13 MB)
114 09:54:40.545254 progress 95 % (14 MB)
115 09:54:40.664157 progress 100 % (15 MB)
116 09:54:40.676641 15 MB downloaded in 2.86 s (5.41 MB/s)
117 09:54:40.677258 end: 1.4.1 http-download (duration 00:00:03) [common]
119 09:54:40.678077 end: 1.4 download-retry (duration 00:00:03) [common]
120 09:54:40.678346 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 09:54:40.678611 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 09:54:40.678861 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:54:40.679114 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 09:54:40.679810 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163
125 09:54:40.680576 makedir: /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin
126 09:54:40.681215 makedir: /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/tests
127 09:54:40.681821 makedir: /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/results
128 09:54:40.682428 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-add-keys
129 09:54:40.683380 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-add-sources
130 09:54:40.684354 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-background-process-start
131 09:54:40.685297 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-background-process-stop
132 09:54:40.686273 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-common-functions
133 09:54:40.687220 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-echo-ipv4
134 09:54:40.688140 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-install-packages
135 09:54:40.689031 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-installed-packages
136 09:54:40.689947 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-os-build
137 09:54:40.690837 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-probe-channel
138 09:54:40.691720 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-probe-ip
139 09:54:40.692723 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-target-ip
140 09:54:40.693763 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-target-mac
141 09:54:40.694667 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-target-storage
142 09:54:40.695609 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-test-case
143 09:54:40.696559 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-test-event
144 09:54:40.697445 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-test-feedback
145 09:54:40.698326 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-test-raise
146 09:54:40.699221 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-test-reference
147 09:54:40.700138 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-test-runner
148 09:54:40.701044 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-test-set
149 09:54:40.701931 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-test-shell
150 09:54:40.702826 Updating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-install-packages (oe)
151 09:54:40.703785 Updating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/bin/lava-installed-packages (oe)
152 09:54:40.704673 Creating /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/environment
153 09:54:40.705391 LAVA metadata
154 09:54:40.705868 - LAVA_JOB_ID=690465
155 09:54:40.706287 - LAVA_DISPATCHER_IP=192.168.6.2
156 09:54:40.706957 start: 1.5.2.1 ssh-authorize (timeout 00:09:56) [common]
157 09:54:40.708808 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 09:54:40.709409 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:56) [common]
159 09:54:40.709815 skipped lava-vland-overlay
160 09:54:40.710299 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 09:54:40.710802 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:56) [common]
162 09:54:40.711223 skipped lava-multinode-overlay
163 09:54:40.711703 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 09:54:40.712153 start: 1.5.2.4 test-definition (timeout 00:09:56) [common]
165 09:54:40.712423 Loading test definitions
166 09:54:40.712712 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:56) [common]
167 09:54:40.712939 Using /lava-690465 at stage 0
168 09:54:40.714196 uuid=690465_1.5.2.4.1 testdef=None
169 09:54:40.714515 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 09:54:40.714951 start: 1.5.2.4.2 test-overlay (timeout 00:09:56) [common]
171 09:54:40.716855 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 09:54:40.717666 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:56) [common]
174 09:54:40.719976 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 09:54:40.720878 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:56) [common]
177 09:54:40.723157 runner path: /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/0/tests/0_dmesg test_uuid 690465_1.5.2.4.1
178 09:54:40.723799 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 09:54:40.724634 Creating lava-test-runner.conf files
181 09:54:40.724840 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/690465/lava-overlay-v0gpm163/lava-690465/0 for stage 0
182 09:54:40.725253 - 0_dmesg
183 09:54:40.725647 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 09:54:40.725933 start: 1.5.2.5 compress-overlay (timeout 00:09:56) [common]
185 09:54:40.751311 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 09:54:40.751737 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:56) [common]
187 09:54:40.752034 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 09:54:40.752315 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 09:54:40.752579 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
190 09:54:41.712980 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 09:54:41.713458 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
192 09:54:41.713705 extracting modules file /var/lib/lava/dispatcher/tmp/690465/tftp-deploy-rznc7pzh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/690465/extract-overlay-ramdisk-01ydide1/ramdisk
193 09:54:43.311392 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 09:54:43.311885 start: 1.5.5 apply-overlay-tftp (timeout 00:09:53) [common]
195 09:54:43.312191 [common] Applying overlay /var/lib/lava/dispatcher/tmp/690465/compress-overlay-9k15etvr/overlay-1.5.2.5.tar.gz to ramdisk
196 09:54:43.312407 [common] Applying overlay /var/lib/lava/dispatcher/tmp/690465/compress-overlay-9k15etvr/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/690465/extract-overlay-ramdisk-01ydide1/ramdisk
197 09:54:43.343262 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 09:54:43.343708 start: 1.5.6 prepare-kernel (timeout 00:09:53) [common]
199 09:54:43.344004 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:53) [common]
200 09:54:43.344244 Converting downloaded kernel to a uImage
201 09:54:43.344566 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/690465/tftp-deploy-rznc7pzh/kernel/Image /var/lib/lava/dispatcher/tmp/690465/tftp-deploy-rznc7pzh/kernel/uImage
202 09:54:44.046210 output: Image Name:
203 09:54:44.046638 output: Created: Mon Sep 2 09:54:43 2024
204 09:54:44.046855 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 09:54:44.047063 output: Data Size: 65890816 Bytes = 64346.50 KiB = 62.84 MiB
206 09:54:44.047262 output: Load Address: 01080000
207 09:54:44.047456 output: Entry Point: 01080000
208 09:54:44.047652 output:
209 09:54:44.047977 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 09:54:44.048294 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 09:54:44.048560 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 09:54:44.048810 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 09:54:44.049062 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 09:54:44.049312 Building ramdisk /var/lib/lava/dispatcher/tmp/690465/extract-overlay-ramdisk-01ydide1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/690465/extract-overlay-ramdisk-01ydide1/ramdisk
215 09:54:47.782034 >> 255037 blocks
216 09:54:59.036232 Adding RAMdisk u-boot header.
217 09:54:59.036646 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/690465/extract-overlay-ramdisk-01ydide1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/690465/extract-overlay-ramdisk-01ydide1/ramdisk.cpio.gz.uboot
218 09:54:59.448628 output: Image Name:
219 09:54:59.449025 output: Created: Mon Sep 2 09:54:59 2024
220 09:54:59.449232 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 09:54:59.449434 output: Data Size: 33700811 Bytes = 32910.95 KiB = 32.14 MiB
222 09:54:59.449634 output: Load Address: 00000000
223 09:54:59.449829 output: Entry Point: 00000000
224 09:54:59.450023 output:
225 09:54:59.450639 rename /var/lib/lava/dispatcher/tmp/690465/extract-overlay-ramdisk-01ydide1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/690465/tftp-deploy-rznc7pzh/ramdisk/ramdisk.cpio.gz.uboot
226 09:54:59.451050 end: 1.5.8 compress-ramdisk (duration 00:00:15) [common]
227 09:54:59.451330 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
228 09:54:59.451599 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
229 09:54:59.451834 No LXC device requested
230 09:54:59.452208 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 09:54:59.452718 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
232 09:54:59.453204 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 09:54:59.453609 Checking files for TFTP limit of 4294967296 bytes.
234 09:54:59.456235 end: 1 tftp-deploy (duration 00:00:23) [common]
235 09:54:59.456800 start: 2 uboot-action (timeout 00:05:00) [common]
236 09:54:59.457313 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 09:54:59.457797 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 09:54:59.458287 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 09:54:59.458801 Using kernel file from prepare-kernel: 690465/tftp-deploy-rznc7pzh/kernel/uImage
240 09:54:59.459413 substitutions:
241 09:54:59.459820 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 09:54:59.460248 - {DTB_ADDR}: 0x01070000
243 09:54:59.460645 - {DTB}: 690465/tftp-deploy-rznc7pzh/dtb/meson-g12b-a311d-libretech-cc.dtb
244 09:54:59.461041 - {INITRD}: 690465/tftp-deploy-rznc7pzh/ramdisk/ramdisk.cpio.gz.uboot
245 09:54:59.461437 - {KERNEL_ADDR}: 0x01080000
246 09:54:59.461826 - {KERNEL}: 690465/tftp-deploy-rznc7pzh/kernel/uImage
247 09:54:59.462216 - {LAVA_MAC}: None
248 09:54:59.462639 - {PRESEED_CONFIG}: None
249 09:54:59.463029 - {PRESEED_LOCAL}: None
250 09:54:59.463413 - {RAMDISK_ADDR}: 0x08000000
251 09:54:59.463798 - {RAMDISK}: 690465/tftp-deploy-rznc7pzh/ramdisk/ramdisk.cpio.gz.uboot
252 09:54:59.464213 - {ROOT_PART}: None
253 09:54:59.464606 - {ROOT}: None
254 09:54:59.464997 - {SERVER_IP}: 192.168.6.2
255 09:54:59.465387 - {TEE_ADDR}: 0x83000000
256 09:54:59.465775 - {TEE}: None
257 09:54:59.466161 Parsed boot commands:
258 09:54:59.466537 - setenv autoload no
259 09:54:59.466921 - setenv initrd_high 0xffffffff
260 09:54:59.467304 - setenv fdt_high 0xffffffff
261 09:54:59.467686 - dhcp
262 09:54:59.468092 - setenv serverip 192.168.6.2
263 09:54:59.468479 - tftpboot 0x01080000 690465/tftp-deploy-rznc7pzh/kernel/uImage
264 09:54:59.468864 - tftpboot 0x08000000 690465/tftp-deploy-rznc7pzh/ramdisk/ramdisk.cpio.gz.uboot
265 09:54:59.469246 - tftpboot 0x01070000 690465/tftp-deploy-rznc7pzh/dtb/meson-g12b-a311d-libretech-cc.dtb
266 09:54:59.469629 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 09:54:59.470017 - bootm 0x01080000 0x08000000 0x01070000
268 09:54:59.470502 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 09:54:59.471956 start: 2.3 connect-device (timeout 00:05:00) [common]
271 09:54:59.472420 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 09:54:59.485964 Setting prompt string to ['lava-test: # ']
273 09:54:59.487421 end: 2.3 connect-device (duration 00:00:00) [common]
274 09:54:59.488040 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 09:54:59.488596 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 09:54:59.489101 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 09:54:59.490232 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 09:54:59.524201 >> OK - accepted request
279 09:54:59.526812 Returned 0 in 0 seconds
280 09:54:59.627647 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 09:54:59.629284 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 09:54:59.629848 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 09:54:59.630347 Setting prompt string to ['Hit any key to stop autoboot']
285 09:54:59.630794 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 09:54:59.632362 Trying 192.168.56.21...
287 09:54:59.632835 Connected to conserv1.
288 09:54:59.633247 Escape character is '^]'.
289 09:54:59.633663
290 09:54:59.634080 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 09:54:59.634507
292 09:55:11.566882 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 09:55:11.567380 bl2_stage_init 0x01
294 09:55:11.567630 bl2_stage_init 0x81
295 09:55:11.572583 hw id: 0x0000 - pwm id 0x01
296 09:55:11.573194 bl2_stage_init 0xc1
297 09:55:11.573659 bl2_stage_init 0x02
298 09:55:11.574102
299 09:55:11.578137 L0:00000000
300 09:55:11.578696 L1:20000703
301 09:55:11.579128 L2:00008067
302 09:55:11.579529 L3:14000000
303 09:55:11.583580 B2:00402000
304 09:55:11.584157 B1:e0f83180
305 09:55:11.584630
306 09:55:11.585061 TE: 58159
307 09:55:11.585480
308 09:55:11.589165 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 09:55:11.589675
310 09:55:11.590115 Board ID = 1
311 09:55:11.594813 Set A53 clk to 24M
312 09:55:11.595335 Set A73 clk to 24M
313 09:55:11.595772 Set clk81 to 24M
314 09:55:11.600353 A53 clk: 1200 MHz
315 09:55:11.600823 A73 clk: 1200 MHz
316 09:55:11.601212 CLK81: 166.6M
317 09:55:11.601604 smccc: 00012ab5
318 09:55:11.606002 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 09:55:11.611655 board id: 1
320 09:55:11.616440 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 09:55:11.628091 fw parse done
322 09:55:11.634154 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 09:55:11.675865 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 09:55:11.687700 PIEI prepare done
325 09:55:11.688265 fastboot data load
326 09:55:11.688667 fastboot data verify
327 09:55:11.693309 verify result: 266
328 09:55:11.699128 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 09:55:11.699707 LPDDR4 probe
330 09:55:11.700222 ddr clk to 1584MHz
331 09:55:11.707285 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 09:55:11.744046
333 09:55:11.744677 dmc_version 0001
334 09:55:11.750460 Check phy result
335 09:55:11.756863 INFO : End of CA training
336 09:55:11.757398 INFO : End of initialization
337 09:55:11.762492 INFO : Training has run successfully!
338 09:55:11.763018 Check phy result
339 09:55:11.768029 INFO : End of initialization
340 09:55:11.768564 INFO : End of read enable training
341 09:55:11.773610 INFO : End of fine write leveling
342 09:55:11.779443 INFO : End of Write leveling coarse delay
343 09:55:11.780015 INFO : Training has run successfully!
344 09:55:11.780455 Check phy result
345 09:55:11.784865 INFO : End of initialization
346 09:55:11.785397 INFO : End of read dq deskew training
347 09:55:11.790508 INFO : End of MPR read delay center optimization
348 09:55:11.796078 INFO : End of write delay center optimization
349 09:55:11.801480 INFO : End of read delay center optimization
350 09:55:11.802006 INFO : End of max read latency training
351 09:55:11.807276 INFO : Training has run successfully!
352 09:55:11.807804 1D training succeed
353 09:55:11.815320 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 09:55:11.863378 Check phy result
355 09:55:11.863767 INFO : End of initialization
356 09:55:11.885398 INFO : End of 2D read delay Voltage center optimization
357 09:55:11.905231 INFO : End of 2D read delay Voltage center optimization
358 09:55:11.956946 INFO : End of 2D write delay Voltage center optimization
359 09:55:12.007339 INFO : End of 2D write delay Voltage center optimization
360 09:55:12.012851 INFO : Training has run successfully!
361 09:55:12.013371
362 09:55:12.013794 channel==0
363 09:55:12.018273 RxClkDly_Margin_A0==88 ps 9
364 09:55:12.018858 TxDqDly_Margin_A0==98 ps 10
365 09:55:12.023886 RxClkDly_Margin_A1==88 ps 9
366 09:55:12.024432 TxDqDly_Margin_A1==98 ps 10
367 09:55:12.024857 TrainedVREFDQ_A0==74
368 09:55:12.029487 TrainedVREFDQ_A1==75
369 09:55:12.029994 VrefDac_Margin_A0==25
370 09:55:12.030411 DeviceVref_Margin_A0==40
371 09:55:12.035174 VrefDac_Margin_A1==25
372 09:55:12.035741 DeviceVref_Margin_A1==39
373 09:55:12.036377
374 09:55:12.036948
375 09:55:12.040814 channel==1
376 09:55:12.041371 RxClkDly_Margin_A0==98 ps 10
377 09:55:12.041816 TxDqDly_Margin_A0==98 ps 10
378 09:55:12.046265 RxClkDly_Margin_A1==98 ps 10
379 09:55:12.046756 TxDqDly_Margin_A1==88 ps 9
380 09:55:12.051905 TrainedVREFDQ_A0==77
381 09:55:12.052447 TrainedVREFDQ_A1==77
382 09:55:12.052881 VrefDac_Margin_A0==22
383 09:55:12.057476 DeviceVref_Margin_A0==37
384 09:55:12.057982 VrefDac_Margin_A1==22
385 09:55:12.063126 DeviceVref_Margin_A1==37
386 09:55:12.063615
387 09:55:12.064064 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 09:55:12.068668
389 09:55:12.096778 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 09:55:12.097426 2D training succeed
391 09:55:12.102323 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 09:55:12.107923 auto size-- 65535DDR cs0 size: 2048MB
393 09:55:12.108868 DDR cs1 size: 2048MB
394 09:55:12.113585 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 09:55:12.114156 cs0 DataBus test pass
396 09:55:12.119186 cs1 DataBus test pass
397 09:55:12.119717 cs0 AddrBus test pass
398 09:55:12.120215 cs1 AddrBus test pass
399 09:55:12.120636
400 09:55:12.125121 100bdlr_step_size ps== 420
401 09:55:12.125691 result report
402 09:55:12.130356 boot times 0Enable ddr reg access
403 09:55:12.135621 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 09:55:12.148466 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 09:55:12.722921 0.0;M3 CHK:0;cm4_sp_mode 0
406 09:55:12.723689 MVN_1=0x00000000
407 09:55:12.728292 MVN_2=0x00000000
408 09:55:12.734101 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 09:55:12.734613 OPS=0x10
410 09:55:12.735204 ring efuse init
411 09:55:12.735819 chipver efuse init
412 09:55:12.742355 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 09:55:12.742973 [0.018961 Inits done]
414 09:55:12.749444 secure task start!
415 09:55:12.750044 high task start!
416 09:55:12.750450 low task start!
417 09:55:12.750849 run into bl31
418 09:55:12.756567 NOTICE: BL31: v1.3(release):4fc40b1
419 09:55:12.764202 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 09:55:12.764804 NOTICE: BL31: G12A normal boot!
421 09:55:12.789667 NOTICE: BL31: BL33 decompress pass
422 09:55:12.794364 ERROR: Error initializing runtime service opteed_fast
423 09:55:14.028459
424 09:55:14.029102
425 09:55:14.036466 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 09:55:14.036988
427 09:55:14.037430 Model: Libre Computer AML-A311D-CC Alta
428 09:55:14.244318 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 09:55:14.267615 DRAM: 2 GiB (effective 3.8 GiB)
430 09:55:14.411491 Core: 408 devices, 31 uclasses, devicetree: separate
431 09:55:14.417554 WDT: Not starting watchdog@f0d0
432 09:55:14.449611 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 09:55:14.462148 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 09:55:14.466136 ** Bad device specification mmc 0 **
435 09:55:14.477444 Card did not respond to voltage select! : -110
436 09:55:14.484268 ** Bad device specification mmc 0 **
437 09:55:14.484592 Couldn't find partition mmc 0
438 09:55:14.493390 Card did not respond to voltage select! : -110
439 09:55:14.498889 ** Bad device specification mmc 0 **
440 09:55:14.499211 Couldn't find partition mmc 0
441 09:55:14.502982 Error: could not access storage.
442 09:55:15.767364 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 09:55:15.768052 bl2_stage_init 0x81
444 09:55:15.773115 hw id: 0x0000 - pwm id 0x01
445 09:55:15.773533 bl2_stage_init 0xc1
446 09:55:15.773757 bl2_stage_init 0x02
447 09:55:15.774331
448 09:55:15.778640 L0:00000000
449 09:55:15.779150 L1:20000703
450 09:55:15.779406 L2:00008067
451 09:55:15.779613 L3:14000000
452 09:55:15.779816 B2:00402000
453 09:55:15.781210 B1:e0f83180
454 09:55:15.781510
455 09:55:15.781729 TE: 58150
456 09:55:15.781932
457 09:55:15.792825 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 09:55:15.793401
459 09:55:15.793701 Board ID = 1
460 09:55:15.793926 Set A53 clk to 24M
461 09:55:15.794135 Set A73 clk to 24M
462 09:55:15.798205 Set clk81 to 24M
463 09:55:15.798589 A53 clk: 1200 MHz
464 09:55:15.798873 A73 clk: 1200 MHz
465 09:55:15.803741 CLK81: 166.6M
466 09:55:15.804078 smccc: 00012aac
467 09:55:15.809316 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 09:55:15.809639 board id: 1
469 09:55:15.817125 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 09:55:15.828710 fw parse done
471 09:55:15.833595 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 09:55:15.877173 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 09:55:15.888113 PIEI prepare done
474 09:55:15.888457 fastboot data load
475 09:55:15.888670 fastboot data verify
476 09:55:15.893744 verify result: 266
477 09:55:15.899369 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 09:55:15.899779 LPDDR4 probe
479 09:55:15.900034 ddr clk to 1584MHz
480 09:55:15.906362 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 09:55:15.943705
482 09:55:15.944151 dmc_version 0001
483 09:55:15.951267 Check phy result
484 09:55:15.957127 INFO : End of CA training
485 09:55:15.957536 INFO : End of initialization
486 09:55:15.962700 INFO : Training has run successfully!
487 09:55:15.963069 Check phy result
488 09:55:15.968338 INFO : End of initialization
489 09:55:15.968705 INFO : End of read enable training
490 09:55:15.973829 INFO : End of fine write leveling
491 09:55:15.979836 INFO : End of Write leveling coarse delay
492 09:55:15.980297 INFO : Training has run successfully!
493 09:55:15.980556 Check phy result
494 09:55:15.985410 INFO : End of initialization
495 09:55:15.985880 INFO : End of read dq deskew training
496 09:55:15.990937 INFO : End of MPR read delay center optimization
497 09:55:15.996483 INFO : End of write delay center optimization
498 09:55:16.002008 INFO : End of read delay center optimization
499 09:55:16.002636 INFO : End of max read latency training
500 09:55:16.007549 INFO : Training has run successfully!
501 09:55:16.008451 1D training succeed
502 09:55:16.015905 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 09:55:16.064356 Check phy result
504 09:55:16.065177 INFO : End of initialization
505 09:55:16.085347 INFO : End of 2D read delay Voltage center optimization
506 09:55:16.105501 INFO : End of 2D read delay Voltage center optimization
507 09:55:16.159736 INFO : End of 2D write delay Voltage center optimization
508 09:55:16.208072 INFO : End of 2D write delay Voltage center optimization
509 09:55:16.213465 INFO : Training has run successfully!
510 09:55:16.214086
511 09:55:16.214501 channel==0
512 09:55:16.218862 RxClkDly_Margin_A0==88 ps 9
513 09:55:16.219338 TxDqDly_Margin_A0==98 ps 10
514 09:55:16.224554 RxClkDly_Margin_A1==88 ps 9
515 09:55:16.225096 TxDqDly_Margin_A1==98 ps 10
516 09:55:16.225504 TrainedVREFDQ_A0==74
517 09:55:16.230149 TrainedVREFDQ_A1==74
518 09:55:16.230711 VrefDac_Margin_A0==25
519 09:55:16.231133 DeviceVref_Margin_A0==40
520 09:55:16.235796 VrefDac_Margin_A1==25
521 09:55:16.236338 DeviceVref_Margin_A1==40
522 09:55:16.236806
523 09:55:16.237223
524 09:55:16.241302 channel==1
525 09:55:16.241765 RxClkDly_Margin_A0==98 ps 10
526 09:55:16.242162 TxDqDly_Margin_A0==88 ps 9
527 09:55:16.246926 RxClkDly_Margin_A1==88 ps 9
528 09:55:16.247397 TxDqDly_Margin_A1==98 ps 10
529 09:55:16.252458 TrainedVREFDQ_A0==77
530 09:55:16.252901 TrainedVREFDQ_A1==78
531 09:55:16.253298 VrefDac_Margin_A0==22
532 09:55:16.258130 DeviceVref_Margin_A0==37
533 09:55:16.258569 VrefDac_Margin_A1==24
534 09:55:16.263805 DeviceVref_Margin_A1==36
535 09:55:16.264342
536 09:55:16.264769 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 09:55:16.265188
538 09:55:16.297465 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
539 09:55:16.298513 2D training succeed
540 09:55:16.303130 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 09:55:16.308621 auto size-- 65535DDR cs0 size: 2048MB
542 09:55:16.309425 DDR cs1 size: 2048MB
543 09:55:16.314186 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 09:55:16.314859 cs0 DataBus test pass
545 09:55:16.319941 cs1 DataBus test pass
546 09:55:16.320592 cs0 AddrBus test pass
547 09:55:16.321082 cs1 AddrBus test pass
548 09:55:16.321540
549 09:55:16.325320 100bdlr_step_size ps== 420
550 09:55:16.325962 result report
551 09:55:16.330991 boot times 0Enable ddr reg access
552 09:55:16.336371 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 09:55:16.349358 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 09:55:16.923798 0.0;M3 CHK:0;cm4_sp_mode 0
555 09:55:16.924647 MVN_1=0x00000000
556 09:55:16.929006 MVN_2=0x00000000
557 09:55:16.934761 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 09:55:16.935302 OPS=0x10
559 09:55:16.935848 ring efuse init
560 09:55:16.936346 chipver efuse init
561 09:55:16.942892 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 09:55:16.943398 [0.018961 Inits done]
563 09:55:16.950544 secure task start!
564 09:55:16.951052 high task start!
565 09:55:16.951453 low task start!
566 09:55:16.951844 run into bl31
567 09:55:16.957198 NOTICE: BL31: v1.3(release):4fc40b1
568 09:55:16.964195 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 09:55:16.964711 NOTICE: BL31: G12A normal boot!
570 09:55:16.990484 NOTICE: BL31: BL33 decompress pass
571 09:55:16.995229 ERROR: Error initializing runtime service opteed_fast
572 09:55:18.228698
573 09:55:18.229100
574 09:55:18.236189 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 09:55:18.236484
576 09:55:18.236698 Model: Libre Computer AML-A311D-CC Alta
577 09:55:18.444707 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 09:55:18.467929 DRAM: 2 GiB (effective 3.8 GiB)
579 09:55:18.611830 Core: 408 devices, 31 uclasses, devicetree: separate
580 09:55:18.616837 WDT: Not starting watchdog@f0d0
581 09:55:18.650174 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 09:55:18.662664 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 09:55:18.667212 ** Bad device specification mmc 0 **
584 09:55:18.678038 Card did not respond to voltage select! : -110
585 09:55:18.684799 ** Bad device specification mmc 0 **
586 09:55:18.685068 Couldn't find partition mmc 0
587 09:55:18.694043 Card did not respond to voltage select! : -110
588 09:55:18.699703 ** Bad device specification mmc 0 **
589 09:55:18.699965 Couldn't find partition mmc 0
590 09:55:18.703606 Error: could not access storage.
591 09:55:19.045908 Net: eth0: ethernet@ff3f0000
592 09:55:19.046536 starting USB...
593 09:55:19.298534 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 09:55:19.299146 Starting the controller
595 09:55:19.304522 USB XHCI 1.10
596 09:55:21.017376 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 09:55:21.018044 bl2_stage_init 0x01
598 09:55:21.018518 bl2_stage_init 0x81
599 09:55:21.022953 hw id: 0x0000 - pwm id 0x01
600 09:55:21.023511 bl2_stage_init 0xc1
601 09:55:21.023975 bl2_stage_init 0x02
602 09:55:21.024512
603 09:55:21.028512 L0:00000000
604 09:55:21.029049 L1:20000703
605 09:55:21.029511 L2:00008067
606 09:55:21.030004 L3:14000000
607 09:55:21.031358 B2:00402000
608 09:55:21.031858 B1:e0f83180
609 09:55:21.032354
610 09:55:21.032807 TE: 58124
611 09:55:21.033282
612 09:55:21.042601 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 09:55:21.043176
614 09:55:21.043641 Board ID = 1
615 09:55:21.044124 Set A53 clk to 24M
616 09:55:21.044588 Set A73 clk to 24M
617 09:55:21.048391 Set clk81 to 24M
618 09:55:21.048978 A53 clk: 1200 MHz
619 09:55:21.049450 A73 clk: 1200 MHz
620 09:55:21.051542 CLK81: 166.6M
621 09:55:21.052092 smccc: 00012a92
622 09:55:21.057122 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 09:55:21.062666 board id: 1
624 09:55:21.068091 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 09:55:21.078727 fw parse done
626 09:55:21.084344 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 09:55:21.127156 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 09:55:21.138187 PIEI prepare done
629 09:55:21.138684 fastboot data load
630 09:55:21.138953 fastboot data verify
631 09:55:21.143774 verify result: 266
632 09:55:21.149404 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 09:55:21.149778 LPDDR4 probe
634 09:55:21.149994 ddr clk to 1584MHz
635 09:55:21.157256 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 09:55:21.193794
637 09:55:21.194389 dmc_version 0001
638 09:55:21.201123 Check phy result
639 09:55:21.207166 INFO : End of CA training
640 09:55:21.207550 INFO : End of initialization
641 09:55:21.212777 INFO : Training has run successfully!
642 09:55:21.213309 Check phy result
643 09:55:21.218400 INFO : End of initialization
644 09:55:21.218760 INFO : End of read enable training
645 09:55:21.224020 INFO : End of fine write leveling
646 09:55:21.229589 INFO : End of Write leveling coarse delay
647 09:55:21.229968 INFO : Training has run successfully!
648 09:55:21.230187 Check phy result
649 09:55:21.235165 INFO : End of initialization
650 09:55:21.235657 INFO : End of read dq deskew training
651 09:55:21.240777 INFO : End of MPR read delay center optimization
652 09:55:21.246430 INFO : End of write delay center optimization
653 09:55:21.252047 INFO : End of read delay center optimization
654 09:55:21.252409 INFO : End of max read latency training
655 09:55:21.257624 INFO : Training has run successfully!
656 09:55:21.258110 1D training succeed
657 09:55:21.265848 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 09:55:21.314063 Check phy result
659 09:55:21.314495 INFO : End of initialization
660 09:55:21.335873 INFO : End of 2D read delay Voltage center optimization
661 09:55:21.356818 INFO : End of 2D read delay Voltage center optimization
662 09:55:21.407241 INFO : End of 2D write delay Voltage center optimization
663 09:55:21.457424 INFO : End of 2D write delay Voltage center optimization
664 09:55:21.462821 INFO : Training has run successfully!
665 09:55:21.463452
666 09:55:21.464047 channel==0
667 09:55:21.468478 RxClkDly_Margin_A0==88 ps 9
668 09:55:21.469096 TxDqDly_Margin_A0==98 ps 10
669 09:55:21.473956 RxClkDly_Margin_A1==88 ps 9
670 09:55:21.474553 TxDqDly_Margin_A1==98 ps 10
671 09:55:21.475098 TrainedVREFDQ_A0==74
672 09:55:21.479578 TrainedVREFDQ_A1==75
673 09:55:21.480218 VrefDac_Margin_A0==25
674 09:55:21.480781 DeviceVref_Margin_A0==40
675 09:55:21.485230 VrefDac_Margin_A1==25
676 09:55:21.485838 DeviceVref_Margin_A1==39
677 09:55:21.486378
678 09:55:21.486914
679 09:55:21.490772 channel==1
680 09:55:21.491378 RxClkDly_Margin_A0==98 ps 10
681 09:55:21.491923 TxDqDly_Margin_A0==98 ps 10
682 09:55:21.496447 RxClkDly_Margin_A1==98 ps 10
683 09:55:21.497075 TxDqDly_Margin_A1==88 ps 9
684 09:55:21.501977 TrainedVREFDQ_A0==77
685 09:55:21.502580 TrainedVREFDQ_A1==77
686 09:55:21.503129 VrefDac_Margin_A0==22
687 09:55:21.507631 DeviceVref_Margin_A0==37
688 09:55:21.508262 VrefDac_Margin_A1==22
689 09:55:21.513189 DeviceVref_Margin_A1==37
690 09:55:21.513800
691 09:55:21.514329 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 09:55:21.518779
693 09:55:21.546809 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
694 09:55:21.547527 2D training succeed
695 09:55:21.552532 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 09:55:21.558096 auto size-- 65535DDR cs0 size: 2048MB
697 09:55:21.558788 DDR cs1 size: 2048MB
698 09:55:21.563573 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 09:55:21.564224 cs0 DataBus test pass
700 09:55:21.569224 cs1 DataBus test pass
701 09:55:21.569822 cs0 AddrBus test pass
702 09:55:21.570363 cs1 AddrBus test pass
703 09:55:21.570896
704 09:55:21.574833 100bdlr_step_size ps== 420
705 09:55:21.575445 result report
706 09:55:21.580459 boot times 0Enable ddr reg access
707 09:55:21.584897 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 09:55:21.599153 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 09:55:22.171333 0.0;M3 CHK:0;cm4_sp_mode 0
710 09:55:22.172045 MVN_1=0x00000000
711 09:55:22.176899 MVN_2=0x00000000
712 09:55:22.182658 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 09:55:22.183213 OPS=0x10
714 09:55:22.183664 ring efuse init
715 09:55:22.184138 chipver efuse init
716 09:55:22.188264 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 09:55:22.193838 [0.018961 Inits done]
718 09:55:22.194363 secure task start!
719 09:55:22.194798 high task start!
720 09:55:22.198474 low task start!
721 09:55:22.198992 run into bl31
722 09:55:22.205043 NOTICE: BL31: v1.3(release):4fc40b1
723 09:55:22.212742 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 09:55:22.213264 NOTICE: BL31: G12A normal boot!
725 09:55:22.238768 NOTICE: BL31: BL33 decompress pass
726 09:55:22.243638 ERROR: Error initializing runtime service opteed_fast
727 09:55:23.477200
728 09:55:23.477636
729 09:55:23.484740 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 09:55:23.485029
731 09:55:23.485275 Model: Libre Computer AML-A311D-CC Alta
732 09:55:23.693359 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 09:55:23.716889 DRAM: 2 GiB (effective 3.8 GiB)
734 09:55:23.860705 Core: 408 devices, 31 uclasses, devicetree: separate
735 09:55:23.866334 WDT: Not starting watchdog@f0d0
736 09:55:23.898896 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 09:55:23.911234 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 09:55:23.916288 ** Bad device specification mmc 0 **
739 09:55:23.926506 Card did not respond to voltage select! : -110
740 09:55:23.933293 ** Bad device specification mmc 0 **
741 09:55:23.933834 Couldn't find partition mmc 0
742 09:55:23.942529 Card did not respond to voltage select! : -110
743 09:55:23.948072 ** Bad device specification mmc 0 **
744 09:55:23.948604 Couldn't find partition mmc 0
745 09:55:23.952359 Error: could not access storage.
746 09:55:24.294708 Net: eth0: ethernet@ff3f0000
747 09:55:24.295123 starting USB...
748 09:55:24.547372 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 09:55:24.547765 Starting the controller
750 09:55:24.553667 USB XHCI 1.10
751 09:55:26.647590 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 09:55:26.648312 bl2_stage_init 0x01
753 09:55:26.648788 bl2_stage_init 0x81
754 09:55:26.653149 hw id: 0x0000 - pwm id 0x01
755 09:55:26.653676 bl2_stage_init 0xc1
756 09:55:26.654141 bl2_stage_init 0x02
757 09:55:26.654589
758 09:55:26.658734 L0:00000000
759 09:55:26.659255 L1:20000703
760 09:55:26.659707 L2:00008067
761 09:55:26.660190 L3:14000000
762 09:55:26.664434 B2:00402000
763 09:55:26.664945 B1:e0f83180
764 09:55:26.665397
765 09:55:26.665849 TE: 58167
766 09:55:26.666293
767 09:55:26.670050 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 09:55:26.670570
769 09:55:26.671024 Board ID = 1
770 09:55:26.675669 Set A53 clk to 24M
771 09:55:26.676212 Set A73 clk to 24M
772 09:55:26.676670 Set clk81 to 24M
773 09:55:26.681189 A53 clk: 1200 MHz
774 09:55:26.681718 A73 clk: 1200 MHz
775 09:55:26.682172 CLK81: 166.6M
776 09:55:26.682612 smccc: 00012abe
777 09:55:26.686732 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 09:55:26.692433 board id: 1
779 09:55:26.698340 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 09:55:26.708763 fw parse done
781 09:55:26.714749 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 09:55:26.756615 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 09:55:26.768270 PIEI prepare done
784 09:55:26.768792 fastboot data load
785 09:55:26.769255 fastboot data verify
786 09:55:26.773917 verify result: 266
787 09:55:26.779465 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 09:55:26.780040 LPDDR4 probe
789 09:55:26.780498 ddr clk to 1584MHz
790 09:55:26.787505 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 09:55:26.824771
792 09:55:26.825355 dmc_version 0001
793 09:55:26.831381 Check phy result
794 09:55:26.837325 INFO : End of CA training
795 09:55:26.837865 INFO : End of initialization
796 09:55:26.842941 INFO : Training has run successfully!
797 09:55:26.843477 Check phy result
798 09:55:26.848486 INFO : End of initialization
799 09:55:26.849027 INFO : End of read enable training
800 09:55:26.854056 INFO : End of fine write leveling
801 09:55:26.859701 INFO : End of Write leveling coarse delay
802 09:55:26.860239 INFO : Training has run successfully!
803 09:55:26.860691 Check phy result
804 09:55:26.865233 INFO : End of initialization
805 09:55:26.865737 INFO : End of read dq deskew training
806 09:55:26.870849 INFO : End of MPR read delay center optimization
807 09:55:26.876445 INFO : End of write delay center optimization
808 09:55:26.882008 INFO : End of read delay center optimization
809 09:55:26.882514 INFO : End of max read latency training
810 09:55:26.887630 INFO : Training has run successfully!
811 09:55:26.888175 1D training succeed
812 09:55:26.896851 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 09:55:26.944391 Check phy result
814 09:55:26.944984 INFO : End of initialization
815 09:55:26.966087 INFO : End of 2D read delay Voltage center optimization
816 09:55:26.986311 INFO : End of 2D read delay Voltage center optimization
817 09:55:27.038384 INFO : End of 2D write delay Voltage center optimization
818 09:55:27.087782 INFO : End of 2D write delay Voltage center optimization
819 09:55:27.093370 INFO : Training has run successfully!
820 09:55:27.093912
821 09:55:27.094383 channel==0
822 09:55:27.098977 RxClkDly_Margin_A0==88 ps 9
823 09:55:27.099488 TxDqDly_Margin_A0==98 ps 10
824 09:55:27.104588 RxClkDly_Margin_A1==88 ps 9
825 09:55:27.105108 TxDqDly_Margin_A1==98 ps 10
826 09:55:27.105565 TrainedVREFDQ_A0==74
827 09:55:27.110199 TrainedVREFDQ_A1==74
828 09:55:27.110754 VrefDac_Margin_A0==25
829 09:55:27.111258 DeviceVref_Margin_A0==40
830 09:55:27.115789 VrefDac_Margin_A1==25
831 09:55:27.116363 DeviceVref_Margin_A1==40
832 09:55:27.116871
833 09:55:27.117355
834 09:55:27.121380 channel==1
835 09:55:27.121935 RxClkDly_Margin_A0==98 ps 10
836 09:55:27.122439 TxDqDly_Margin_A0==98 ps 10
837 09:55:27.126985 RxClkDly_Margin_A1==98 ps 10
838 09:55:27.127523 TxDqDly_Margin_A1==88 ps 9
839 09:55:27.132583 TrainedVREFDQ_A0==77
840 09:55:27.133114 TrainedVREFDQ_A1==77
841 09:55:27.133604 VrefDac_Margin_A0==22
842 09:55:27.138147 DeviceVref_Margin_A0==37
843 09:55:27.138677 VrefDac_Margin_A1==24
844 09:55:27.143791 DeviceVref_Margin_A1==37
845 09:55:27.144562
846 09:55:27.144914 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 09:55:27.149395
848 09:55:27.177291 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
849 09:55:27.177849 2D training succeed
850 09:55:27.183037 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 09:55:27.188593 auto size-- 65535DDR cs0 size: 2048MB
852 09:55:27.189119 DDR cs1 size: 2048MB
853 09:55:27.194165 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 09:55:27.194661 cs0 DataBus test pass
855 09:55:27.199704 cs1 DataBus test pass
856 09:55:27.200233 cs0 AddrBus test pass
857 09:55:27.200665 cs1 AddrBus test pass
858 09:55:27.201089
859 09:55:27.205342 100bdlr_step_size ps== 420
860 09:55:27.205850 result report
861 09:55:27.210992 boot times 0Enable ddr reg access
862 09:55:27.216408 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 09:55:27.230334 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 09:55:27.803302 0.0;M3 CHK:0;cm4_sp_mode 0
865 09:55:27.803691 MVN_1=0x00000000
866 09:55:27.808728 MVN_2=0x00000000
867 09:55:27.814514 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 09:55:27.814786 OPS=0x10
869 09:55:27.815030 ring efuse init
870 09:55:27.815266 chipver efuse init
871 09:55:27.820126 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 09:55:27.825741 [0.018961 Inits done]
873 09:55:27.826024 secure task start!
874 09:55:27.826363 high task start!
875 09:55:27.830326 low task start!
876 09:55:27.830586 run into bl31
877 09:55:27.836981 NOTICE: BL31: v1.3(release):4fc40b1
878 09:55:27.843909 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 09:55:27.844395 NOTICE: BL31: G12A normal boot!
880 09:55:27.870178 NOTICE: BL31: BL33 decompress pass
881 09:55:27.874930 ERROR: Error initializing runtime service opteed_fast
882 09:55:29.108907
883 09:55:29.109588
884 09:55:29.117353 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 09:55:29.117891
886 09:55:29.118346 Model: Libre Computer AML-A311D-CC Alta
887 09:55:29.325737 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 09:55:29.348196 DRAM: 2 GiB (effective 3.8 GiB)
889 09:55:29.492255 Core: 408 devices, 31 uclasses, devicetree: separate
890 09:55:29.498031 WDT: Not starting watchdog@f0d0
891 09:55:29.530303 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 09:55:29.542726 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 09:55:29.546804 ** Bad device specification mmc 0 **
894 09:55:29.558045 Card did not respond to voltage select! : -110
895 09:55:29.564765 ** Bad device specification mmc 0 **
896 09:55:29.565279 Couldn't find partition mmc 0
897 09:55:29.574072 Card did not respond to voltage select! : -110
898 09:55:29.579531 ** Bad device specification mmc 0 **
899 09:55:29.580073 Couldn't find partition mmc 0
900 09:55:29.583650 Error: could not access storage.
901 09:55:29.928298 Net: eth0: ethernet@ff3f0000
902 09:55:29.929007 starting USB...
903 09:55:30.180020 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 09:55:30.180673 Starting the controller
905 09:55:30.186174 USB XHCI 1.10
906 09:55:31.741098 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 09:55:31.749332 scanning usb for storage devices... 0 Storage Device(s) found
909 09:55:31.800968 Hit any key to stop autoboot: 1
910 09:55:31.802933 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
911 09:55:31.803293 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
912 09:55:31.803539 Setting prompt string to ['=>']
913 09:55:31.803950 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
914 09:55:31.815675 0
915 09:55:31.816611 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 09:55:31.817119 Sending with 10 millisecond of delay
918 09:55:32.952015 => setenv autoload no
919 09:55:32.962822 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
920 09:55:32.967765 setenv autoload no
921 09:55:32.968523 Sending with 10 millisecond of delay
923 09:55:34.766227 => setenv initrd_high 0xffffffff
924 09:55:34.777267 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
925 09:55:34.778156 setenv initrd_high 0xffffffff
926 09:55:34.778945 Sending with 10 millisecond of delay
928 09:55:36.396327 => setenv fdt_high 0xffffffff
929 09:55:36.407163 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
930 09:55:36.408033 setenv fdt_high 0xffffffff
931 09:55:36.408745 Sending with 10 millisecond of delay
933 09:55:36.700570 => dhcp
934 09:55:36.711330 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
935 09:55:36.712221 dhcp
936 09:55:36.712666 Speed: 1000, full duplex
937 09:55:36.713078 BOOTP broadcast 1
938 09:55:36.959515 BOOTP broadcast 2
939 09:55:37.460500 BOOTP broadcast 3
940 09:55:37.473505 DHCP client bound to address 192.168.6.33 (762 ms)
941 09:55:37.474235 Sending with 10 millisecond of delay
943 09:55:39.150854 => setenv serverip 192.168.6.2
944 09:55:39.161707 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
945 09:55:39.162646 setenv serverip 192.168.6.2
946 09:55:39.163348 Sending with 10 millisecond of delay
948 09:55:42.892823 => tftpboot 0x01080000 690465/tftp-deploy-rznc7pzh/kernel/uImage
949 09:55:42.903625 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
950 09:55:42.904544 tftpboot 0x01080000 690465/tftp-deploy-rznc7pzh/kernel/uImage
951 09:55:42.905022 Speed: 1000, full duplex
952 09:55:42.905463 Using ethernet@ff3f0000 device
953 09:55:42.906373 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
954 09:55:42.911943 Filename '690465/tftp-deploy-rznc7pzh/kernel/uImage'.
955 09:55:42.915731 Load address: 0x1080000
956 09:55:47.185948 Loading: *################################################## 62.8 MiB
957 09:55:47.186604 14.7 MiB/s
958 09:55:47.187051 done
959 09:55:47.190428 Bytes transferred = 65890880 (3ed6a40 hex)
960 09:55:47.191324 Sending with 10 millisecond of delay
962 09:55:51.881061 => tftpboot 0x08000000 690465/tftp-deploy-rznc7pzh/ramdisk/ramdisk.cpio.gz.uboot
963 09:55:51.892289 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:08)
964 09:55:51.893673 tftpboot 0x08000000 690465/tftp-deploy-rznc7pzh/ramdisk/ramdisk.cpio.gz.uboot
965 09:55:51.894378 Speed: 1000, full duplex
966 09:55:51.895105 Using ethernet@ff3f0000 device
967 09:55:51.895873 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
968 09:55:51.906854 Filename '690465/tftp-deploy-rznc7pzh/ramdisk/ramdisk.cpio.gz.uboot'.
969 09:55:51.907677 Load address: 0x8000000
970 09:55:54.131217 Loading: *################################################# UDP wrong checksum 00000007 00000389
971 09:55:59.132907 T UDP wrong checksum 00000007 00000389
972 09:56:09.134824 T T UDP wrong checksum 00000007 00000389
973 09:56:29.138664 T T T T UDP wrong checksum 00000007 00000389
974 09:56:39.341274 T T UDP wrong checksum 000000ff 0000f9a8
975 09:56:39.359873 UDP wrong checksum 000000ff 00008b9b
976 09:56:49.144086 T
977 09:56:49.144724 Retry count exceeded; starting again
979 09:56:49.146207 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
982 09:56:49.148173 end: 2.4 uboot-commands (duration 00:01:50) [common]
984 09:56:49.149914 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
986 09:56:49.151100 end: 2 uboot-action (duration 00:01:50) [common]
988 09:56:49.152800 Cleaning after the job
989 09:56:49.153413 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/690465/tftp-deploy-rznc7pzh/ramdisk
990 09:56:49.154859 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/690465/tftp-deploy-rznc7pzh/kernel
991 09:56:49.214382 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/690465/tftp-deploy-rznc7pzh/dtb
992 09:56:49.215346 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/690465/tftp-deploy-rznc7pzh/modules
993 09:56:49.244046 start: 4.1 power-off (timeout 00:00:30) [common]
994 09:56:49.244686 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
995 09:56:49.278522 >> OK - accepted request
996 09:56:49.280900 Returned 0 in 0 seconds
997 09:56:49.381864 end: 4.1 power-off (duration 00:00:00) [common]
999 09:56:49.382743 start: 4.2 read-feedback (timeout 00:10:00) [common]
1000 09:56:49.383385 Listened to connection for namespace 'common' for up to 1s
1001 09:56:50.384364 Finalising connection for namespace 'common'
1002 09:56:50.385142 Disconnecting from shell: Finalise
1003 09:56:50.385683 =>
1004 09:56:50.486743 end: 4.2 read-feedback (duration 00:00:01) [common]
1005 09:56:50.487508 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/690465
1006 09:56:50.821333 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/690465
1007 09:56:50.821923 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.