Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 16:46:58.510563 lava-dispatcher, installed at version: 2024.01
2 16:46:58.511404 start: 0 validate
3 16:46:58.511890 Start time: 2024-09-05 16:46:58.511858+00:00 (UTC)
4 16:46:58.512513 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 16:46:58.513052 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 16:46:58.556435 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 16:46:58.557040 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240905%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 16:46:58.593357 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 16:46:58.594012 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240905%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 16:46:59.647319 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 16:46:59.647810 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240905%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 16:46:59.693683 validate duration: 1.18
14 16:46:59.695164 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 16:46:59.695770 start: 1.1 download-retry (timeout 00:10:00) [common]
16 16:46:59.696380 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 16:46:59.697340 Not decompressing ramdisk as can be used compressed.
18 16:46:59.698046 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 16:46:59.698530 saving as /var/lib/lava/dispatcher/tmp/710865/tftp-deploy-lw4vwp27/ramdisk/rootfs.cpio.gz
20 16:46:59.699035 total size: 8181887 (7 MB)
21 16:46:59.740551 progress 0 % (0 MB)
22 16:46:59.752307 progress 5 % (0 MB)
23 16:46:59.763597 progress 10 % (0 MB)
24 16:46:59.775969 progress 15 % (1 MB)
25 16:46:59.783359 progress 20 % (1 MB)
26 16:46:59.789101 progress 25 % (1 MB)
27 16:46:59.794425 progress 30 % (2 MB)
28 16:46:59.800284 progress 35 % (2 MB)
29 16:46:59.805607 progress 40 % (3 MB)
30 16:46:59.811352 progress 45 % (3 MB)
31 16:46:59.816703 progress 50 % (3 MB)
32 16:46:59.822332 progress 55 % (4 MB)
33 16:46:59.827791 progress 60 % (4 MB)
34 16:46:59.833906 progress 65 % (5 MB)
35 16:46:59.839546 progress 70 % (5 MB)
36 16:46:59.845343 progress 75 % (5 MB)
37 16:46:59.850634 progress 80 % (6 MB)
38 16:46:59.856349 progress 85 % (6 MB)
39 16:46:59.861618 progress 90 % (7 MB)
40 16:46:59.867031 progress 95 % (7 MB)
41 16:46:59.871860 progress 100 % (7 MB)
42 16:46:59.872522 7 MB downloaded in 0.17 s (44.98 MB/s)
43 16:46:59.873054 end: 1.1.1 http-download (duration 00:00:00) [common]
45 16:46:59.873917 end: 1.1 download-retry (duration 00:00:00) [common]
46 16:46:59.874204 start: 1.2 download-retry (timeout 00:10:00) [common]
47 16:46:59.874470 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 16:46:59.874940 downloading http://storage.kernelci.org/next/master/next-20240905/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/kernel/Image
49 16:46:59.875180 saving as /var/lib/lava/dispatcher/tmp/710865/tftp-deploy-lw4vwp27/kernel/Image
50 16:46:59.875382 total size: 45677056 (43 MB)
51 16:46:59.875592 No compression specified
52 16:46:59.915673 progress 0 % (0 MB)
53 16:46:59.943536 progress 5 % (2 MB)
54 16:46:59.971872 progress 10 % (4 MB)
55 16:46:59.999810 progress 15 % (6 MB)
56 16:47:00.027851 progress 20 % (8 MB)
57 16:47:00.055886 progress 25 % (10 MB)
58 16:47:00.083900 progress 30 % (13 MB)
59 16:47:00.111429 progress 35 % (15 MB)
60 16:47:00.139803 progress 40 % (17 MB)
61 16:47:00.167864 progress 45 % (19 MB)
62 16:47:00.195536 progress 50 % (21 MB)
63 16:47:00.223948 progress 55 % (23 MB)
64 16:47:00.252025 progress 60 % (26 MB)
65 16:47:00.280111 progress 65 % (28 MB)
66 16:47:00.307803 progress 70 % (30 MB)
67 16:47:00.336355 progress 75 % (32 MB)
68 16:47:00.364376 progress 80 % (34 MB)
69 16:47:00.392069 progress 85 % (37 MB)
70 16:47:00.420098 progress 90 % (39 MB)
71 16:47:00.448534 progress 95 % (41 MB)
72 16:47:00.475714 progress 100 % (43 MB)
73 16:47:00.476509 43 MB downloaded in 0.60 s (72.47 MB/s)
74 16:47:00.476993 end: 1.2.1 http-download (duration 00:00:01) [common]
76 16:47:00.477802 end: 1.2 download-retry (duration 00:00:01) [common]
77 16:47:00.478075 start: 1.3 download-retry (timeout 00:09:59) [common]
78 16:47:00.478337 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 16:47:00.478802 downloading http://storage.kernelci.org/next/master/next-20240905/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 16:47:00.479075 saving as /var/lib/lava/dispatcher/tmp/710865/tftp-deploy-lw4vwp27/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 16:47:00.479282 total size: 53209 (0 MB)
82 16:47:00.479489 No compression specified
83 16:47:00.524514 progress 61 % (0 MB)
84 16:47:00.525364 progress 100 % (0 MB)
85 16:47:00.525893 0 MB downloaded in 0.05 s (1.09 MB/s)
86 16:47:00.526358 end: 1.3.1 http-download (duration 00:00:00) [common]
88 16:47:00.527158 end: 1.3 download-retry (duration 00:00:00) [common]
89 16:47:00.527414 start: 1.4 download-retry (timeout 00:09:59) [common]
90 16:47:00.527673 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 16:47:00.528165 downloading http://storage.kernelci.org/next/master/next-20240905/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/modules.tar.xz
92 16:47:00.528417 saving as /var/lib/lava/dispatcher/tmp/710865/tftp-deploy-lw4vwp27/modules/modules.tar
93 16:47:00.528622 total size: 11527284 (10 MB)
94 16:47:00.528833 Using unxz to decompress xz
95 16:47:00.562610 progress 0 % (0 MB)
96 16:47:00.628004 progress 5 % (0 MB)
97 16:47:00.710979 progress 10 % (1 MB)
98 16:47:00.790990 progress 15 % (1 MB)
99 16:47:00.876957 progress 20 % (2 MB)
100 16:47:00.950970 progress 25 % (2 MB)
101 16:47:01.028275 progress 30 % (3 MB)
102 16:47:01.105117 progress 35 % (3 MB)
103 16:47:01.180634 progress 40 % (4 MB)
104 16:47:01.262764 progress 45 % (4 MB)
105 16:47:01.337876 progress 50 % (5 MB)
106 16:47:01.422085 progress 55 % (6 MB)
107 16:47:01.500020 progress 60 % (6 MB)
108 16:47:01.580212 progress 65 % (7 MB)
109 16:47:01.660100 progress 70 % (7 MB)
110 16:47:01.738057 progress 75 % (8 MB)
111 16:47:01.832986 progress 80 % (8 MB)
112 16:47:01.932685 progress 85 % (9 MB)
113 16:47:02.003218 progress 90 % (9 MB)
114 16:47:02.081150 progress 95 % (10 MB)
115 16:47:02.156419 progress 100 % (10 MB)
116 16:47:02.170642 10 MB downloaded in 1.64 s (6.70 MB/s)
117 16:47:02.171386 end: 1.4.1 http-download (duration 00:00:02) [common]
119 16:47:02.172582 end: 1.4 download-retry (duration 00:00:02) [common]
120 16:47:02.173183 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 16:47:02.173765 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 16:47:02.174311 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 16:47:02.174866 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 16:47:02.175973 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh
125 16:47:02.177001 makedir: /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin
126 16:47:02.177913 makedir: /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/tests
127 16:47:02.178648 makedir: /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/results
128 16:47:02.179367 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-add-keys
129 16:47:02.180503 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-add-sources
130 16:47:02.181651 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-background-process-start
131 16:47:02.182787 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-background-process-stop
132 16:47:02.183961 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-common-functions
133 16:47:02.185131 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-echo-ipv4
134 16:47:02.186366 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-install-packages
135 16:47:02.187459 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-installed-packages
136 16:47:02.188576 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-os-build
137 16:47:02.189646 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-probe-channel
138 16:47:02.190715 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-probe-ip
139 16:47:02.191760 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-target-ip
140 16:47:02.192873 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-target-mac
141 16:47:02.194032 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-target-storage
142 16:47:02.195188 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-test-case
143 16:47:02.196281 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-test-event
144 16:47:02.197289 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-test-feedback
145 16:47:02.198296 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-test-raise
146 16:47:02.199296 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-test-reference
147 16:47:02.200350 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-test-runner
148 16:47:02.201378 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-test-set
149 16:47:02.202443 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-test-shell
150 16:47:02.203497 Updating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-install-packages (oe)
151 16:47:02.204637 Updating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/bin/lava-installed-packages (oe)
152 16:47:02.205571 Creating /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/environment
153 16:47:02.206361 LAVA metadata
154 16:47:02.206894 - LAVA_JOB_ID=710865
155 16:47:02.207368 - LAVA_DISPATCHER_IP=192.168.6.2
156 16:47:02.208138 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 16:47:02.210165 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 16:47:02.210830 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 16:47:02.211283 skipped lava-vland-overlay
160 16:47:02.211819 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 16:47:02.212420 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 16:47:02.212896 skipped lava-multinode-overlay
163 16:47:02.213430 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 16:47:02.213979 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 16:47:02.214507 Loading test definitions
166 16:47:02.215118 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 16:47:02.215600 Using /lava-710865 at stage 0
168 16:47:02.219655 uuid=710865_1.5.2.4.1 testdef=None
169 16:47:02.220388 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 16:47:02.220964 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 16:47:02.224948 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 16:47:02.226673 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 16:47:02.231536 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 16:47:02.233402 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 16:47:02.238036 runner path: /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/0/tests/0_dmesg test_uuid 710865_1.5.2.4.1
178 16:47:02.239150 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 16:47:02.240710 Creating lava-test-runner.conf files
181 16:47:02.241112 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/710865/lava-overlay-n694a1jh/lava-710865/0 for stage 0
182 16:47:02.241771 - 0_dmesg
183 16:47:02.242438 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 16:47:02.242973 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 16:47:02.267451 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 16:47:02.267876 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 16:47:02.268168 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 16:47:02.268440 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 16:47:02.268705 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 16:47:03.229034 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 16:47:03.229512 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 16:47:03.229758 extracting modules file /var/lib/lava/dispatcher/tmp/710865/tftp-deploy-lw4vwp27/modules/modules.tar to /var/lib/lava/dispatcher/tmp/710865/extract-overlay-ramdisk-1yzxm92b/ramdisk
193 16:47:04.619975 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 16:47:04.620475 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 16:47:04.620747 [common] Applying overlay /var/lib/lava/dispatcher/tmp/710865/compress-overlay-tiv9rsb6/overlay-1.5.2.5.tar.gz to ramdisk
196 16:47:04.620959 [common] Applying overlay /var/lib/lava/dispatcher/tmp/710865/compress-overlay-tiv9rsb6/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/710865/extract-overlay-ramdisk-1yzxm92b/ramdisk
197 16:47:04.651701 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 16:47:04.652154 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 16:47:04.652428 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 16:47:04.652656 Converting downloaded kernel to a uImage
201 16:47:04.652959 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/710865/tftp-deploy-lw4vwp27/kernel/Image /var/lib/lava/dispatcher/tmp/710865/tftp-deploy-lw4vwp27/kernel/uImage
202 16:47:05.135739 output: Image Name:
203 16:47:05.136194 output: Created: Thu Sep 5 16:47:04 2024
204 16:47:05.136409 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 16:47:05.136616 output: Data Size: 45677056 Bytes = 44606.50 KiB = 43.56 MiB
206 16:47:05.136818 output: Load Address: 01080000
207 16:47:05.137016 output: Entry Point: 01080000
208 16:47:05.137213 output:
209 16:47:05.137548 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 16:47:05.137816 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 16:47:05.138084 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 16:47:05.138337 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 16:47:05.138594 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 16:47:05.138859 Building ramdisk /var/lib/lava/dispatcher/tmp/710865/extract-overlay-ramdisk-1yzxm92b/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/710865/extract-overlay-ramdisk-1yzxm92b/ramdisk
215 16:47:07.641149 >> 180707 blocks
216 16:47:16.053432 Adding RAMdisk u-boot header.
217 16:47:16.053882 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/710865/extract-overlay-ramdisk-1yzxm92b/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/710865/extract-overlay-ramdisk-1yzxm92b/ramdisk.cpio.gz.uboot
218 16:47:16.335887 output: Image Name:
219 16:47:16.336590 output: Created: Thu Sep 5 16:47:16 2024
220 16:47:16.337062 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 16:47:16.337509 output: Data Size: 25947551 Bytes = 25339.41 KiB = 24.75 MiB
222 16:47:16.337946 output: Load Address: 00000000
223 16:47:16.338382 output: Entry Point: 00000000
224 16:47:16.338811 output:
225 16:47:16.339868 rename /var/lib/lava/dispatcher/tmp/710865/extract-overlay-ramdisk-1yzxm92b/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/710865/tftp-deploy-lw4vwp27/ramdisk/ramdisk.cpio.gz.uboot
226 16:47:16.340682 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 16:47:16.341273 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 16:47:16.341847 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 16:47:16.342339 No LXC device requested
230 16:47:16.342882 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 16:47:16.343435 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 16:47:16.343974 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 16:47:16.344463 Checking files for TFTP limit of 4294967296 bytes.
234 16:47:16.347377 end: 1 tftp-deploy (duration 00:00:17) [common]
235 16:47:16.348030 start: 2 uboot-action (timeout 00:05:00) [common]
236 16:47:16.348713 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 16:47:16.349283 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 16:47:16.349857 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 16:47:16.350439 Using kernel file from prepare-kernel: 710865/tftp-deploy-lw4vwp27/kernel/uImage
240 16:47:16.351100 substitutions:
241 16:47:16.351549 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 16:47:16.352017 - {DTB_ADDR}: 0x01070000
243 16:47:16.352464 - {DTB}: 710865/tftp-deploy-lw4vwp27/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 16:47:16.352906 - {INITRD}: 710865/tftp-deploy-lw4vwp27/ramdisk/ramdisk.cpio.gz.uboot
245 16:47:16.353340 - {KERNEL_ADDR}: 0x01080000
246 16:47:16.353775 - {KERNEL}: 710865/tftp-deploy-lw4vwp27/kernel/uImage
247 16:47:16.354210 - {LAVA_MAC}: None
248 16:47:16.354681 - {PRESEED_CONFIG}: None
249 16:47:16.355117 - {PRESEED_LOCAL}: None
250 16:47:16.355548 - {RAMDISK_ADDR}: 0x08000000
251 16:47:16.355971 - {RAMDISK}: 710865/tftp-deploy-lw4vwp27/ramdisk/ramdisk.cpio.gz.uboot
252 16:47:16.356434 - {ROOT_PART}: None
253 16:47:16.356863 - {ROOT}: None
254 16:47:16.357285 - {SERVER_IP}: 192.168.6.2
255 16:47:16.357713 - {TEE_ADDR}: 0x83000000
256 16:47:16.358140 - {TEE}: None
257 16:47:16.358566 Parsed boot commands:
258 16:47:16.358981 - setenv autoload no
259 16:47:16.359406 - setenv initrd_high 0xffffffff
260 16:47:16.359826 - setenv fdt_high 0xffffffff
261 16:47:16.360274 - dhcp
262 16:47:16.360700 - setenv serverip 192.168.6.2
263 16:47:16.361124 - tftpboot 0x01080000 710865/tftp-deploy-lw4vwp27/kernel/uImage
264 16:47:16.361547 - tftpboot 0x08000000 710865/tftp-deploy-lw4vwp27/ramdisk/ramdisk.cpio.gz.uboot
265 16:47:16.361971 - tftpboot 0x01070000 710865/tftp-deploy-lw4vwp27/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 16:47:16.362395 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 16:47:16.362826 - bootm 0x01080000 0x08000000 0x01070000
268 16:47:16.363359 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 16:47:16.365062 start: 2.3 connect-device (timeout 00:05:00) [common]
271 16:47:16.365549 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 16:47:16.381017 Setting prompt string to ['lava-test: # ']
273 16:47:16.382593 end: 2.3 connect-device (duration 00:00:00) [common]
274 16:47:16.383239 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 16:47:16.383832 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 16:47:16.384424 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 16:47:16.385881 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 16:47:16.423442 >> OK - accepted request
279 16:47:16.425580 Returned 0 in 0 seconds
280 16:47:16.526787 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 16:47:16.528603 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 16:47:16.529219 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 16:47:16.529765 Setting prompt string to ['Hit any key to stop autoboot']
285 16:47:16.530249 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 16:47:16.531971 Trying 192.168.56.21...
287 16:47:16.532532 Connected to conserv1.
288 16:47:16.532990 Escape character is '^]'.
289 16:47:16.533450
290 16:47:16.533907 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 16:47:16.534372
292 16:47:23.727643 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 16:47:23.728416 bl2_stage_init 0x01
294 16:47:23.728899 bl2_stage_init 0x81
295 16:47:23.733225 hw id: 0x0000 - pwm id 0x01
296 16:47:23.733756 bl2_stage_init 0xc1
297 16:47:23.738903 bl2_stage_init 0x02
298 16:47:23.739445
299 16:47:23.739891 L0:00000000
300 16:47:23.740381 L1:00000703
301 16:47:23.740815 L2:00008067
302 16:47:23.741246 L3:15000000
303 16:47:23.744578 S1:00000000
304 16:47:23.745098 B2:20282000
305 16:47:23.745546 B1:a0f83180
306 16:47:23.745987
307 16:47:23.746424 TE: 69119
308 16:47:23.746863
309 16:47:23.750183 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 16:47:23.750690
311 16:47:23.755763 Board ID = 1
312 16:47:23.756355 Set cpu clk to 24M
313 16:47:23.756796 Set clk81 to 24M
314 16:47:23.761399 Use GP1_pll as DSU clk.
315 16:47:23.761892 DSU clk: 1200 Mhz
316 16:47:23.762330 CPU clk: 1200 MHz
317 16:47:23.767021 Set clk81 to 166.6M
318 16:47:23.772586 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 16:47:23.773083 board id: 1
320 16:47:23.779646 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 16:47:23.790473 fw parse done
322 16:47:23.796451 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 16:47:23.839577 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 16:47:23.850689 PIEI prepare done
325 16:47:23.851222 fastboot data load
326 16:47:23.851665 fastboot data verify
327 16:47:23.856390 verify result: 266
328 16:47:23.861909 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 16:47:23.862418 LPDDR4 probe
330 16:47:23.862852 ddr clk to 1584MHz
331 16:47:23.869928 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 16:47:23.907645
333 16:47:23.908215 dmc_version 0001
334 16:47:23.914658 Check phy result
335 16:47:23.920687 INFO : End of CA training
336 16:47:23.921213 INFO : End of initialization
337 16:47:23.926260 INFO : Training has run successfully!
338 16:47:23.926764 Check phy result
339 16:47:23.931840 INFO : End of initialization
340 16:47:23.932384 INFO : End of read enable training
341 16:47:23.937502 INFO : End of fine write leveling
342 16:47:23.943061 INFO : End of Write leveling coarse delay
343 16:47:23.943563 INFO : Training has run successfully!
344 16:47:23.944036 Check phy result
345 16:47:23.948649 INFO : End of initialization
346 16:47:23.949148 INFO : End of read dq deskew training
347 16:47:23.954190 INFO : End of MPR read delay center optimization
348 16:47:23.959827 INFO : End of write delay center optimization
349 16:47:23.965446 INFO : End of read delay center optimization
350 16:47:23.965946 INFO : End of max read latency training
351 16:47:23.971053 INFO : Training has run successfully!
352 16:47:23.971558 1D training succeed
353 16:47:23.980217 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 16:47:24.027786 Check phy result
355 16:47:24.028377 INFO : End of initialization
356 16:47:24.055972 INFO : End of 2D read delay Voltage center optimization
357 16:47:24.080112 INFO : End of 2D read delay Voltage center optimization
358 16:47:24.136143 INFO : End of 2D write delay Voltage center optimization
359 16:47:24.190852 INFO : End of 2D write delay Voltage center optimization
360 16:47:24.196499 INFO : Training has run successfully!
361 16:47:24.197009
362 16:47:24.197451 channel==0
363 16:47:24.202059 RxClkDly_Margin_A0==88 ps 9
364 16:47:24.202562 TxDqDly_Margin_A0==98 ps 10
365 16:47:24.207655 RxClkDly_Margin_A1==88 ps 9
366 16:47:24.208213 TxDqDly_Margin_A1==98 ps 10
367 16:47:24.208659 TrainedVREFDQ_A0==76
368 16:47:24.213294 TrainedVREFDQ_A1==74
369 16:47:24.213798 VrefDac_Margin_A0==24
370 16:47:24.214229 DeviceVref_Margin_A0==38
371 16:47:24.218790 VrefDac_Margin_A1==23
372 16:47:24.219298 DeviceVref_Margin_A1==40
373 16:47:24.219736
374 16:47:24.220206
375 16:47:24.224495 channel==1
376 16:47:24.225007 RxClkDly_Margin_A0==88 ps 9
377 16:47:24.225443 TxDqDly_Margin_A0==88 ps 9
378 16:47:24.230032 RxClkDly_Margin_A1==78 ps 8
379 16:47:24.230547 TxDqDly_Margin_A1==78 ps 8
380 16:47:24.235580 TrainedVREFDQ_A0==75
381 16:47:24.236124 TrainedVREFDQ_A1==75
382 16:47:24.236572 VrefDac_Margin_A0==23
383 16:47:24.241220 DeviceVref_Margin_A0==39
384 16:47:24.241748 VrefDac_Margin_A1==22
385 16:47:24.246835 DeviceVref_Margin_A1==38
386 16:47:24.247346
387 16:47:24.247791 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 16:47:24.248270
389 16:47:24.280410 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000016 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
390 16:47:24.281049 2D training succeed
391 16:47:24.285997 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 16:47:24.291581 auto size-- 65535DDR cs0 size: 2048MB
393 16:47:24.292121 DDR cs1 size: 2048MB
394 16:47:24.297198 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 16:47:24.297708 cs0 DataBus test pass
396 16:47:24.302746 cs1 DataBus test pass
397 16:47:24.303250 cs0 AddrBus test pass
398 16:47:24.303683 cs1 AddrBus test pass
399 16:47:24.304150
400 16:47:24.308482 100bdlr_step_size ps== 471
401 16:47:24.309003 result report
402 16:47:24.313989 boot times 0Enable ddr reg access
403 16:47:24.319163 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 16:47:24.333046 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 16:47:24.992756 bl2z: ptr: 05129330, size: 00001e40
406 16:47:25.002481 0.0;M3 CHK:0;cm4_sp_mode 0
407 16:47:25.002785 MVN_1=0x00000000
408 16:47:25.003011 MVN_2=0x00000000
409 16:47:25.014014 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 16:47:25.014318 OPS=0x04
411 16:47:25.014539 ring efuse init
412 16:47:25.019559 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 16:47:25.019846 [0.017354 Inits done]
414 16:47:25.020101 secure task start!
415 16:47:25.027440 high task start!
416 16:47:25.027719 low task start!
417 16:47:25.027935 run into bl31
418 16:47:25.036144 NOTICE: BL31: v1.3(release):4fc40b1
419 16:47:25.043894 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 16:47:25.044203 NOTICE: BL31: G12A normal boot!
421 16:47:25.059440 NOTICE: BL31: BL33 decompress pass
422 16:47:25.065184 ERROR: Error initializing runtime service opteed_fast
423 16:47:26.279857 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 16:47:26.280671 bl2_stage_init 0x01
425 16:47:26.281142 bl2_stage_init 0x81
426 16:47:26.285491 hw id: 0x0000 - pwm id 0x01
427 16:47:26.286004 bl2_stage_init 0xc1
428 16:47:26.291056 bl2_stage_init 0x02
429 16:47:26.291567
430 16:47:26.292063 L0:00000000
431 16:47:26.292518 L1:00000703
432 16:47:26.292967 L2:00008067
433 16:47:26.293410 L3:15000000
434 16:47:26.296683 S1:00000000
435 16:47:26.297188 B2:20282000
436 16:47:26.297640 B1:a0f83180
437 16:47:26.298078
438 16:47:26.298519 TE: 71165
439 16:47:26.298956
440 16:47:26.302261 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 16:47:26.302766
442 16:47:26.307869 Board ID = 1
443 16:47:26.308412 Set cpu clk to 24M
444 16:47:26.308867 Set clk81 to 24M
445 16:47:26.313459 Use GP1_pll as DSU clk.
446 16:47:26.313959 DSU clk: 1200 Mhz
447 16:47:26.314406 CPU clk: 1200 MHz
448 16:47:26.319050 Set clk81 to 166.6M
449 16:47:26.324663 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 16:47:26.325171 board id: 1
451 16:47:26.331871 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 16:47:26.342471 fw parse done
453 16:47:26.348464 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 16:47:26.391066 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 16:47:26.402021 PIEI prepare done
456 16:47:26.402540 fastboot data load
457 16:47:26.402998 fastboot data verify
458 16:47:26.407702 verify result: 266
459 16:47:26.413230 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 16:47:26.413753 LPDDR4 probe
461 16:47:26.414205 ddr clk to 1584MHz
462 16:47:27.778585 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x000 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 16:47:27.779270 bl2_stage_init 0x01
464 16:47:27.779740 bl2_stage_init 0x81
465 16:47:27.784265 hw id: 0x0000 - pwm id 0x01
466 16:47:27.784783 bl2_stage_init 0xc1
467 16:47:27.789313 bl2_stage_init 0x02
468 16:47:27.789839
469 16:47:27.790317 L0:00000000
470 16:47:27.790760 L1:00000703
471 16:47:27.791194 L2:00008067
472 16:47:27.794894 L3:15000000
473 16:47:27.795393 S1:00000000
474 16:47:27.795823 B2:20282000
475 16:47:27.796297 B1:a0f83180
476 16:47:27.796720
477 16:47:27.797145 TE: 68913
478 16:47:27.797567
479 16:47:27.805989 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 16:47:27.806494
481 16:47:27.806923 Board ID = 1
482 16:47:27.807346 Set cpu clk to 24M
483 16:47:27.807771 Set clk81 to 24M
484 16:47:27.811635 Use GP1_pll as DSU clk.
485 16:47:27.812157 DSU clk: 1200 Mhz
486 16:47:27.812593 CPU clk: 1200 MHz
487 16:47:27.817224 Set clk81 to 166.6M
488 16:47:27.822870 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 16:47:27.823362 board id: 1
490 16:47:27.830593 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 16:47:27.841219 fw parse done
492 16:47:27.847188 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 16:47:27.889900 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 16:47:27.900893 PIEI prepare done
495 16:47:27.901373 fastboot data load
496 16:47:27.901807 fastboot data verify
497 16:47:27.906367 verify result: 266
498 16:47:27.911941 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 16:47:27.912475 LPDDR4 probe
500 16:47:27.912903 ddr clk to 1584MHz
501 16:47:27.919976 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 16:47:27.957173
503 16:47:27.957673 dmc_version 0001
504 16:47:27.963957 Check phy result
505 16:47:27.969872 INFO : End of CA training
506 16:47:27.970358 INFO : End of initialization
507 16:47:27.975459 INFO : Training has run successfully!
508 16:47:27.976018 Check phy result
509 16:47:27.981011 INFO : End of initialization
510 16:47:27.981520 INFO : End of read enable training
511 16:47:27.986637 INFO : End of fine write leveling
512 16:47:27.992268 INFO : End of Write leveling coarse delay
513 16:47:27.992805 INFO : Training has run successfully!
514 16:47:27.993275 Check phy result
515 16:47:27.997933 INFO : End of initialization
516 16:47:27.998443 INFO : End of read dq deskew training
517 16:47:28.003422 INFO : End of MPR read delay center optimization
518 16:47:28.009008 INFO : End of write delay center optimization
519 16:47:28.014672 INFO : End of read delay center optimization
520 16:47:28.015169 INFO : End of max read latency training
521 16:47:28.020214 INFO : Training has run successfully!
522 16:47:28.020729 1D training succeed
523 16:47:28.029384 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 16:47:28.077010 Check phy result
525 16:47:28.077527 INFO : End of initialization
526 16:47:28.099320 INFO : End of 2D read delay Voltage center optimization
527 16:47:28.118488 INFO : End of 2D read delay Voltage center optimization
528 16:47:28.170349 INFO : End of 2D write delay Voltage center optimization
529 16:47:28.219524 INFO : End of 2D write delay Voltage center optimization
530 16:47:28.225086 INFO : Training has run successfully!
531 16:47:28.225587
532 16:47:28.226042 channel==0
533 16:47:28.230691 RxClkDly_Margin_A0==78 ps 8
534 16:47:28.231187 TxDqDly_Margin_A0==88 ps 9
535 16:47:28.236315 RxClkDly_Margin_A1==88 ps 9
536 16:47:28.236810 TxDqDly_Margin_A1==88 ps 9
537 16:47:28.237259 TrainedVREFDQ_A0==74
538 16:47:28.241944 TrainedVREFDQ_A1==74
539 16:47:28.242443 VrefDac_Margin_A0==24
540 16:47:28.242890 DeviceVref_Margin_A0==40
541 16:47:28.247506 VrefDac_Margin_A1==23
542 16:47:28.248030 DeviceVref_Margin_A1==40
543 16:47:28.248483
544 16:47:28.248932
545 16:47:28.249372 channel==1
546 16:47:28.253387 RxClkDly_Margin_A0==88 ps 9
547 16:47:28.253888 TxDqDly_Margin_A0==98 ps 10
548 16:47:28.260022 RxClkDly_Margin_A1==88 ps 9
549 16:47:28.260521 TxDqDly_Margin_A1==88 ps 9
550 16:47:28.264335 TrainedVREFDQ_A0==78
551 16:47:28.264829 TrainedVREFDQ_A1==78
552 16:47:28.265280 VrefDac_Margin_A0==23
553 16:47:28.270032 DeviceVref_Margin_A0==36
554 16:47:28.270528 VrefDac_Margin_A1==22
555 16:47:28.270980 DeviceVref_Margin_A1==36
556 16:47:28.275486
557 16:47:28.276019 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 16:47:28.276478
559 16:47:28.309079 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
560 16:47:28.309632 2D training succeed
561 16:47:28.314727 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 16:47:28.320331 auto size-- 65535DDR cs0 size: 2048MB
563 16:47:28.320829 DDR cs1 size: 2048MB
564 16:47:28.325993 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 16:47:28.326489 cs0 DataBus test pass
566 16:47:28.331503 cs1 DataBus test pass
567 16:47:28.332036 cs0 AddrBus test pass
568 16:47:28.332490 cs1 AddrBus test pass
569 16:47:28.332937
570 16:47:28.337117 100bdlr_step_size ps== 471
571 16:47:28.337625 result report
572 16:47:28.342701 boot times 0Enable ddr reg access
573 16:47:28.347788 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 16:47:28.361602 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 16:47:29.016637 bl2z: ptr: 05129330, size: 00001e40
576 16:47:29.022600 0.0;M3 CHK:0;cm4_sp_mode 0
577 16:47:29.023118 MVN_1=0x00000000
578 16:47:29.023567 MVN_2=0x00000000
579 16:47:29.034020 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 16:47:29.034530 OPS=0x04
581 16:47:29.034981 ring efuse init
582 16:47:29.037056 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 16:47:29.043448 [0.017319 Inits done]
584 16:47:29.043947 secure task start!
585 16:47:29.044433 high task start!
586 16:47:29.044868 low task start!
587 16:47:29.047873 run into bl31
588 16:47:29.056437 NOTICE: BL31: v1.3(release):4fc40b1
589 16:47:29.064234 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 16:47:29.064742 NOTICE: BL31: G12A normal boot!
591 16:47:29.079804 NOTICE: BL31: BL33 decompress pass
592 16:47:29.085462 ERROR: Error initializing runtime service opteed_fast
593 16:47:30.407826 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 16:47:30.408496 bl2_stage_init 0x01
595 16:47:30.408966 bl2_stage_init 0x81
596 16:47:30.413371 hw id: 0x0000 - pwm id 0x01
597 16:47:30.413892 bl2_stage_init 0xc1
598 16:47:30.418448 bl2_stage_init 0x02
599 16:47:30.418951
600 16:47:30.419411 L0:00000000
601 16:47:30.419857 L1:00000703
602 16:47:30.420343 L2:00008067
603 16:47:30.424028 L3:15000000
604 16:47:30.424534 S1:00000000
605 16:47:30.424986 B2:20282000
606 16:47:30.425430 B1:a0f83180
607 16:47:30.425867
608 16:47:30.426304 TE: 69131
609 16:47:30.426739
610 16:47:30.435275 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 16:47:30.435806
612 16:47:30.436303 Board ID = 1
613 16:47:30.436746 Set cpu clk to 24M
614 16:47:30.437187 Set clk81 to 24M
615 16:47:30.440781 Use GP1_pll as DSU clk.
616 16:47:30.441282 DSU clk: 1200 Mhz
617 16:47:30.441733 CPU clk: 1200 MHz
618 16:47:30.446385 Set clk81 to 166.6M
619 16:47:30.451933 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 16:47:30.452461 board id: 1
621 16:47:30.459700 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 16:47:30.470386 fw parse done
623 16:47:30.476326 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 16:47:30.518902 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 16:47:30.529850 PIEI prepare done
626 16:47:30.530358 fastboot data load
627 16:47:30.530810 fastboot data verify
628 16:47:30.535460 verify result: 266
629 16:47:30.541061 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 16:47:30.541563 LPDDR4 probe
631 16:47:30.542014 ddr clk to 1584MHz
632 16:47:30.549087 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 16:47:30.586349
634 16:47:30.586858 dmc_version 0001
635 16:47:30.592979 Check phy result
636 16:47:30.598892 INFO : End of CA training
637 16:47:30.599394 INFO : End of initialization
638 16:47:30.604484 INFO : Training has run successfully!
639 16:47:30.604990 Check phy result
640 16:47:30.610083 INFO : End of initialization
641 16:47:30.610584 INFO : End of read enable training
642 16:47:30.615693 INFO : End of fine write leveling
643 16:47:30.621271 INFO : End of Write leveling coarse delay
644 16:47:30.621766 INFO : Training has run successfully!
645 16:47:30.622215 Check phy result
646 16:47:30.626870 INFO : End of initialization
647 16:47:30.627369 INFO : End of read dq deskew training
648 16:47:30.632458 INFO : End of MPR read delay center optimization
649 16:47:30.638073 INFO : End of write delay center optimization
650 16:47:30.643670 INFO : End of read delay center optimization
651 16:47:30.644196 INFO : End of max read latency training
652 16:47:30.649281 INFO : Training has run successfully!
653 16:47:30.649779 1D training succeed
654 16:47:30.658421 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 16:47:30.706015 Check phy result
656 16:47:30.706528 INFO : End of initialization
657 16:47:30.728424 INFO : End of 2D read delay Voltage center optimization
658 16:47:30.747584 INFO : End of 2D read delay Voltage center optimization
659 16:47:30.799475 INFO : End of 2D write delay Voltage center optimization
660 16:47:30.848597 INFO : End of 2D write delay Voltage center optimization
661 16:47:30.854302 INFO : Training has run successfully!
662 16:47:30.854802
663 16:47:30.855253 channel==0
664 16:47:30.859814 RxClkDly_Margin_A0==78 ps 8
665 16:47:30.860340 TxDqDly_Margin_A0==98 ps 10
666 16:47:30.863111 RxClkDly_Margin_A1==78 ps 8
667 16:47:30.863607 TxDqDly_Margin_A1==98 ps 10
668 16:47:30.868731 TrainedVREFDQ_A0==74
669 16:47:30.869235 TrainedVREFDQ_A1==75
670 16:47:30.869684 VrefDac_Margin_A0==24
671 16:47:30.874317 DeviceVref_Margin_A0==40
672 16:47:30.874816 VrefDac_Margin_A1==22
673 16:47:30.879935 DeviceVref_Margin_A1==39
674 16:47:30.880452
675 16:47:30.880907
676 16:47:30.881350 channel==1
677 16:47:30.881784 RxClkDly_Margin_A0==88 ps 9
678 16:47:30.885532 TxDqDly_Margin_A0==98 ps 10
679 16:47:30.886036 RxClkDly_Margin_A1==78 ps 8
680 16:47:30.891100 TxDqDly_Margin_A1==88 ps 9
681 16:47:30.891612 TrainedVREFDQ_A0==78
682 16:47:30.892094 TrainedVREFDQ_A1==78
683 16:47:30.896723 VrefDac_Margin_A0==23
684 16:47:30.897223 DeviceVref_Margin_A0==36
685 16:47:30.902325 VrefDac_Margin_A1==22
686 16:47:30.902817 DeviceVref_Margin_A1==36
687 16:47:30.903264
688 16:47:30.907906 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 16:47:30.908433
690 16:47:30.935841 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000016 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000062
691 16:47:30.941498 2D training succeed
692 16:47:30.947103 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 16:47:30.947604 auto size-- 65535DDR cs0 size: 2048MB
694 16:47:30.952703 DDR cs1 size: 2048MB
695 16:47:30.953201 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 16:47:30.958314 cs0 DataBus test pass
697 16:47:30.958812 cs1 DataBus test pass
698 16:47:30.959260 cs0 AddrBus test pass
699 16:47:30.963921 cs1 AddrBus test pass
700 16:47:30.964442
701 16:47:30.964901 100bdlr_step_size ps== 478
702 16:47:30.965356 result report
703 16:47:30.969505 boot times 0Enable ddr reg access
704 16:47:30.977052 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 16:47:30.990832 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 16:47:31.645178 bl2z: ptr: 05129330, size: 00001e40
707 16:47:31.653746 0.0;M3 CHK:0;cm4_sp_mode 0
708 16:47:31.654272 MVN_1=0x00000000
709 16:47:31.654728 MVN_2=0x00000000
710 16:47:31.665182 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 16:47:31.665694 OPS=0x04
712 16:47:31.666149 ring efuse init
713 16:47:31.670844 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 16:47:31.671356 [0.017319 Inits done]
715 16:47:31.671808 secure task start!
716 16:47:31.678111 high task start!
717 16:47:31.678607 low task start!
718 16:47:31.679055 run into bl31
719 16:47:31.686698 NOTICE: BL31: v1.3(release):4fc40b1
720 16:47:31.694528 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 16:47:31.695035 NOTICE: BL31: G12A normal boot!
722 16:47:31.710059 NOTICE: BL31: BL33 decompress pass
723 16:47:31.715324 ERROR: Error initializing runtime service opteed_fast
724 16:47:32.511047
725 16:47:32.511652
726 16:47:32.516552 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 16:47:32.517070
728 16:47:32.520036 Model: Libre Computer AML-S905D3-CC Solitude
729 16:47:32.666987 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 16:47:32.682413 DRAM: 2 GiB (effective 3.8 GiB)
731 16:47:32.783318 Core: 406 devices, 33 uclasses, devicetree: separate
732 16:47:32.789307 WDT: Not starting watchdog@f0d0
733 16:47:32.814326 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 16:47:32.826505 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 16:47:32.831625 ** Bad device specification mmc 0 **
736 16:47:32.841550 Card did not respond to voltage select! : -110
737 16:47:32.849203 ** Bad device specification mmc 0 **
738 16:47:32.849696 Couldn't find partition mmc 0
739 16:47:32.857533 Card did not respond to voltage select! : -110
740 16:47:32.863059 ** Bad device specification mmc 0 **
741 16:47:32.863551 Couldn't find partition mmc 0
742 16:47:32.868192 Error: could not access storage.
743 16:47:33.165687 Net: eth0: ethernet@ff3f0000
744 16:47:33.166268 starting USB...
745 16:47:33.410268 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 16:47:33.410843 Starting the controller
747 16:47:33.417253 USB XHCI 1.10
748 16:47:34.971569 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 16:47:34.979961 scanning usb for storage devices... 0 Storage Device(s) found
751 16:47:35.031556 Hit any key to stop autoboot: 1
752 16:47:35.032439 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 16:47:35.033137 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 16:47:35.033673 Setting prompt string to ['=>']
755 16:47:35.034207 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 16:47:35.045988 0
757 16:47:35.046935 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 16:47:35.148217 => setenv autoload no
760 16:47:35.149204 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 16:47:35.154775 setenv autoload no
763 16:47:35.256345 => setenv initrd_high 0xffffffff
764 16:47:35.257233 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 16:47:35.261496 setenv initrd_high 0xffffffff
767 16:47:35.363054 => setenv fdt_high 0xffffffff
768 16:47:35.363905 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 16:47:35.368576 setenv fdt_high 0xffffffff
771 16:47:35.470273 => dhcp
772 16:47:35.471281 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 16:47:35.475778 dhcp
774 16:47:35.981011 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
775 16:47:35.981646 Speed: 1000, full duplex
776 16:47:35.982106 BOOTP broadcast 1
777 16:47:36.229275 BOOTP broadcast 2
778 16:47:36.730164 BOOTP broadcast 3
779 16:47:37.731218 BOOTP broadcast 4
780 16:47:39.731417 BOOTP broadcast 5
781 16:47:39.749418 DHCP client bound to address 192.168.6.12 (3768 ms)
783 16:47:39.851141 => setenv serverip 192.168.6.2
784 16:47:39.851966 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
785 16:47:39.856055 setenv serverip 192.168.6.2
787 16:47:39.957708 => tftpboot 0x01080000 710865/tftp-deploy-lw4vwp27/kernel/uImage
788 16:47:39.958608 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
789 16:47:39.966280 tftpboot 0x01080000 710865/tftp-deploy-lw4vwp27/kernel/uImage
790 16:47:39.966891 Speed: 1000, full duplex
791 16:47:39.967364 Using ethernet@ff3f0000 device
792 16:47:39.971812 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
793 16:47:39.977353 Filename '710865/tftp-deploy-lw4vwp27/kernel/uImage'.
794 16:47:39.981304 Load address: 0x1080000
795 16:47:42.807189 Loading: *################################################## 43.6 MiB
796 16:47:42.807629 15.4 MiB/s
797 16:47:42.807851 done
798 16:47:42.810564 Bytes transferred = 45677120 (2b8fa40 hex)
800 16:47:42.911661 => tftpboot 0x08000000 710865/tftp-deploy-lw4vwp27/ramdisk/ramdisk.cpio.gz.uboot
801 16:47:42.912563 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
802 16:47:42.919131 tftpboot 0x08000000 710865/tftp-deploy-lw4vwp27/ramdisk/ramdisk.cpio.gz.uboot
803 16:47:42.919443 Speed: 1000, full duplex
804 16:47:42.919660 Using ethernet@ff3f0000 device
805 16:47:42.924690 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
806 16:47:42.934473 Filename '710865/tftp-deploy-lw4vwp27/ramdisk/ramdisk.cpio.gz.uboot'.
807 16:47:42.934977 Load address: 0x8000000
808 16:47:44.813188 Loading: *################################################# UDP wrong checksum 00000005 0000eedf
809 16:47:49.812330 T UDP wrong checksum 00000005 0000eedf
810 16:47:59.814336 T T UDP wrong checksum 00000005 0000eedf
811 16:48:19.819334 T T T T UDP wrong checksum 00000005 0000eedf
812 16:48:34.828124 T T T UDP wrong checksum 000000ff 000052c1
813 16:48:34.890134 UDP wrong checksum 000000ff 0000ebb3
814 16:48:39.822751
815 16:48:39.823146 Retry count exceeded; starting again
817 16:48:39.824001 end: 2.4.3 bootloader-commands (duration 00:01:05) [common]
820 16:48:39.824942 end: 2.4 uboot-commands (duration 00:01:23) [common]
822 16:48:39.825647 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
824 16:48:39.826185 end: 2 uboot-action (duration 00:01:23) [common]
826 16:48:39.826981 Cleaning after the job
827 16:48:39.827278 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/710865/tftp-deploy-lw4vwp27/ramdisk
828 16:48:39.828086 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/710865/tftp-deploy-lw4vwp27/kernel
829 16:48:39.861429 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/710865/tftp-deploy-lw4vwp27/dtb
830 16:48:39.862282 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/710865/tftp-deploy-lw4vwp27/modules
831 16:48:39.884546 start: 4.1 power-off (timeout 00:00:30) [common]
832 16:48:39.885222 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
833 16:48:39.916176 >> OK - accepted request
834 16:48:39.917753 Returned 0 in 0 seconds
835 16:48:40.018828 end: 4.1 power-off (duration 00:00:00) [common]
837 16:48:40.020121 start: 4.2 read-feedback (timeout 00:10:00) [common]
838 16:48:40.021164 Listened to connection for namespace 'common' for up to 1s
839 16:48:41.021333 Finalising connection for namespace 'common'
840 16:48:41.022311 Disconnecting from shell: Finalise
841 16:48:41.022985 =>
842 16:48:41.124207 end: 4.2 read-feedback (duration 00:00:01) [common]
843 16:48:41.125059 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/710865
844 16:48:41.469991 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/710865
845 16:48:41.470772 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.