Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 10:14:59.841764 lava-dispatcher, installed at version: 2024.01
2 10:14:59.842554 start: 0 validate
3 10:14:59.843035 Start time: 2024-09-06 10:14:59.843006+00:00 (UTC)
4 10:14:59.843591 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 10:14:59.844168 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 10:14:59.881142 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 10:14:59.881747 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240906%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 10:14:59.915344 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 10:14:59.916033 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240906%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 10:15:05.997592 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 10:15:05.998105 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240906%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 10:15:12.079843 validate duration: 12.24
14 10:15:12.080915 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:15:12.081353 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:15:12.081667 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:15:12.082559 Not decompressing ramdisk as can be used compressed.
18 10:15:12.083748 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 10:15:12.084335 saving as /var/lib/lava/dispatcher/tmp/715318/tftp-deploy-kz_2wv_v/ramdisk/rootfs.cpio.gz
20 10:15:12.084848 total size: 8181887 (7 MB)
21 10:15:12.128918 progress 0 % (0 MB)
22 10:15:12.136528 progress 5 % (0 MB)
23 10:15:12.142335 progress 10 % (0 MB)
24 10:15:12.148735 progress 15 % (1 MB)
25 10:15:12.154566 progress 20 % (1 MB)
26 10:15:12.161014 progress 25 % (1 MB)
27 10:15:12.166865 progress 30 % (2 MB)
28 10:15:12.173348 progress 35 % (2 MB)
29 10:15:12.179102 progress 40 % (3 MB)
30 10:15:12.185752 progress 45 % (3 MB)
31 10:15:12.191624 progress 50 % (3 MB)
32 10:15:12.197813 progress 55 % (4 MB)
33 10:15:12.203429 progress 60 % (4 MB)
34 10:15:12.209785 progress 65 % (5 MB)
35 10:15:12.215939 progress 70 % (5 MB)
36 10:15:12.222366 progress 75 % (5 MB)
37 10:15:12.228338 progress 80 % (6 MB)
38 10:15:12.234623 progress 85 % (6 MB)
39 10:15:12.240418 progress 90 % (7 MB)
40 10:15:12.246527 progress 95 % (7 MB)
41 10:15:12.251626 progress 100 % (7 MB)
42 10:15:12.252321 7 MB downloaded in 0.17 s (46.59 MB/s)
43 10:15:12.252887 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:15:12.253871 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:15:12.254225 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:15:12.254660 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:15:12.255369 downloading http://storage.kernelci.org/next/master/next-20240906/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/kernel/Image
49 10:15:12.255755 saving as /var/lib/lava/dispatcher/tmp/715318/tftp-deploy-kz_2wv_v/kernel/Image
50 10:15:12.256052 total size: 47288832 (45 MB)
51 10:15:12.256407 No compression specified
52 10:15:12.300212 progress 0 % (0 MB)
53 10:15:12.337366 progress 5 % (2 MB)
54 10:15:12.375069 progress 10 % (4 MB)
55 10:15:12.410228 progress 15 % (6 MB)
56 10:15:12.439772 progress 20 % (9 MB)
57 10:15:12.469762 progress 25 % (11 MB)
58 10:15:12.498354 progress 30 % (13 MB)
59 10:15:12.528126 progress 35 % (15 MB)
60 10:15:12.557732 progress 40 % (18 MB)
61 10:15:12.587922 progress 45 % (20 MB)
62 10:15:12.618415 progress 50 % (22 MB)
63 10:15:12.649173 progress 55 % (24 MB)
64 10:15:12.679476 progress 60 % (27 MB)
65 10:15:12.711523 progress 65 % (29 MB)
66 10:15:12.744940 progress 70 % (31 MB)
67 10:15:12.781390 progress 75 % (33 MB)
68 10:15:12.813450 progress 80 % (36 MB)
69 10:15:12.845720 progress 85 % (38 MB)
70 10:15:12.876810 progress 90 % (40 MB)
71 10:15:12.907682 progress 95 % (42 MB)
72 10:15:12.939479 progress 100 % (45 MB)
73 10:15:12.940232 45 MB downloaded in 0.68 s (65.92 MB/s)
74 10:15:12.940922 end: 1.2.1 http-download (duration 00:00:01) [common]
76 10:15:12.941946 end: 1.2 download-retry (duration 00:00:01) [common]
77 10:15:12.942234 start: 1.3 download-retry (timeout 00:09:59) [common]
78 10:15:12.942500 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 10:15:12.943079 downloading http://storage.kernelci.org/next/master/next-20240906/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 10:15:12.943412 saving as /var/lib/lava/dispatcher/tmp/715318/tftp-deploy-kz_2wv_v/dtb/meson-g12b-a311d-libretech-cc.dtb
81 10:15:12.943683 total size: 54703 (0 MB)
82 10:15:12.943968 No compression specified
83 10:15:12.980457 progress 59 % (0 MB)
84 10:15:12.981292 progress 100 % (0 MB)
85 10:15:12.981834 0 MB downloaded in 0.04 s (1.37 MB/s)
86 10:15:12.982312 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:15:12.983137 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:15:12.983405 start: 1.4 download-retry (timeout 00:09:59) [common]
90 10:15:12.983743 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 10:15:12.984265 downloading http://storage.kernelci.org/next/master/next-20240906/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/modules.tar.xz
92 10:15:12.984529 saving as /var/lib/lava/dispatcher/tmp/715318/tftp-deploy-kz_2wv_v/modules/modules.tar
93 10:15:12.984736 total size: 11541352 (11 MB)
94 10:15:12.984946 Using unxz to decompress xz
95 10:15:13.022208 progress 0 % (0 MB)
96 10:15:13.095904 progress 5 % (0 MB)
97 10:15:13.174635 progress 10 % (1 MB)
98 10:15:13.258341 progress 15 % (1 MB)
99 10:15:14.056706 progress 20 % (2 MB)
100 10:15:14.141259 progress 25 % (2 MB)
101 10:15:14.217502 progress 30 % (3 MB)
102 10:15:14.298696 progress 35 % (3 MB)
103 10:15:14.375290 progress 40 % (4 MB)
104 10:15:14.453404 progress 45 % (4 MB)
105 10:15:14.533331 progress 50 % (5 MB)
106 10:15:14.607264 progress 55 % (6 MB)
107 10:15:14.697465 progress 60 % (6 MB)
108 10:15:14.779423 progress 65 % (7 MB)
109 10:15:14.862596 progress 70 % (7 MB)
110 10:15:14.961029 progress 75 % (8 MB)
111 10:15:15.053463 progress 80 % (8 MB)
112 10:15:15.136535 progress 85 % (9 MB)
113 10:15:15.209465 progress 90 % (9 MB)
114 10:15:15.287676 progress 95 % (10 MB)
115 10:15:15.365256 progress 100 % (11 MB)
116 10:15:15.376065 11 MB downloaded in 2.39 s (4.60 MB/s)
117 10:15:15.377393 end: 1.4.1 http-download (duration 00:00:02) [common]
119 10:15:15.379528 end: 1.4 download-retry (duration 00:00:02) [common]
120 10:15:15.380288 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 10:15:15.381045 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 10:15:15.381783 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:15:15.382469 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 10:15:15.383744 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov
125 10:15:15.384889 makedir: /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin
126 10:15:15.385755 makedir: /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/tests
127 10:15:15.386552 makedir: /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/results
128 10:15:15.387336 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-add-keys
129 10:15:15.388616 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-add-sources
130 10:15:15.389847 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-background-process-start
131 10:15:15.391110 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-background-process-stop
132 10:15:15.392464 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-common-functions
133 10:15:15.393739 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-echo-ipv4
134 10:15:15.394940 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-install-packages
135 10:15:15.396161 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-installed-packages
136 10:15:15.397386 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-os-build
137 10:15:15.398557 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-probe-channel
138 10:15:15.399700 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-probe-ip
139 10:15:15.400964 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-target-ip
140 10:15:15.402260 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-target-mac
141 10:15:15.403426 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-target-storage
142 10:15:15.404696 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-test-case
143 10:15:15.405881 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-test-event
144 10:15:15.407018 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-test-feedback
145 10:15:15.408194 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-test-raise
146 10:15:15.409384 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-test-reference
147 10:15:15.410530 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-test-runner
148 10:15:15.411739 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-test-set
149 10:15:15.413017 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-test-shell
150 10:15:15.414236 Updating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-install-packages (oe)
151 10:15:15.415481 Updating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/bin/lava-installed-packages (oe)
152 10:15:15.416408 Creating /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/environment
153 10:15:15.416924 LAVA metadata
154 10:15:15.417279 - LAVA_JOB_ID=715318
155 10:15:15.417544 - LAVA_DISPATCHER_IP=192.168.6.2
156 10:15:15.418015 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 10:15:15.419291 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 10:15:15.419703 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 10:15:15.419962 skipped lava-vland-overlay
160 10:15:15.420295 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 10:15:15.420615 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 10:15:15.420899 skipped lava-multinode-overlay
163 10:15:15.421208 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 10:15:15.421524 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 10:15:15.421842 Loading test definitions
166 10:15:15.422193 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 10:15:15.422490 Using /lava-715318 at stage 0
168 10:15:15.424133 uuid=715318_1.5.2.4.1 testdef=None
169 10:15:15.424560 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 10:15:15.424893 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 10:15:15.427211 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 10:15:15.428266 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 10:15:15.431637 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 10:15:15.432745 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 10:15:15.435520 runner path: /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/0/tests/0_dmesg test_uuid 715318_1.5.2.4.1
178 10:15:15.436293 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 10:15:15.437265 Creating lava-test-runner.conf files
181 10:15:15.437518 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/715318/lava-overlay-ckxdq3ov/lava-715318/0 for stage 0
182 10:15:15.437947 - 0_dmesg
183 10:15:15.438390 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 10:15:15.438736 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 10:15:15.468086 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 10:15:15.468636 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 10:15:15.468964 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 10:15:15.469297 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 10:15:15.469626 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 10:15:16.436778 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 10:15:16.437255 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 10:15:16.437504 extracting modules file /var/lib/lava/dispatcher/tmp/715318/tftp-deploy-kz_2wv_v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/715318/extract-overlay-ramdisk-gan65tu9/ramdisk
193 10:15:17.800758 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 10:15:17.801251 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 10:15:17.801568 [common] Applying overlay /var/lib/lava/dispatcher/tmp/715318/compress-overlay-54zrwr19/overlay-1.5.2.5.tar.gz to ramdisk
196 10:15:17.801788 [common] Applying overlay /var/lib/lava/dispatcher/tmp/715318/compress-overlay-54zrwr19/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/715318/extract-overlay-ramdisk-gan65tu9/ramdisk
197 10:15:17.832073 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 10:15:17.832544 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 10:15:17.832818 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 10:15:17.833049 Converting downloaded kernel to a uImage
201 10:15:17.833360 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/715318/tftp-deploy-kz_2wv_v/kernel/Image /var/lib/lava/dispatcher/tmp/715318/tftp-deploy-kz_2wv_v/kernel/uImage
202 10:15:18.304456 output: Image Name:
203 10:15:18.304892 output: Created: Fri Sep 6 10:15:17 2024
204 10:15:18.305103 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 10:15:18.305312 output: Data Size: 47288832 Bytes = 46180.50 KiB = 45.10 MiB
206 10:15:18.305513 output: Load Address: 01080000
207 10:15:18.305712 output: Entry Point: 01080000
208 10:15:18.305909 output:
209 10:15:18.306251 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 10:15:18.306516 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 10:15:18.306786 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 10:15:18.307040 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 10:15:18.307296 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 10:15:18.307562 Building ramdisk /var/lib/lava/dispatcher/tmp/715318/extract-overlay-ramdisk-gan65tu9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/715318/extract-overlay-ramdisk-gan65tu9/ramdisk
215 10:15:20.842195 >> 180757 blocks
216 10:15:29.439766 Adding RAMdisk u-boot header.
217 10:15:29.440288 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/715318/extract-overlay-ramdisk-gan65tu9/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/715318/extract-overlay-ramdisk-gan65tu9/ramdisk.cpio.gz.uboot
218 10:15:29.855218 output: Image Name:
219 10:15:29.855646 output: Created: Fri Sep 6 10:15:29 2024
220 10:15:29.855855 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 10:15:29.856246 output: Data Size: 25926265 Bytes = 25318.62 KiB = 24.73 MiB
222 10:15:29.856700 output: Load Address: 00000000
223 10:15:29.857161 output: Entry Point: 00000000
224 10:15:29.857598 output:
225 10:15:29.858778 rename /var/lib/lava/dispatcher/tmp/715318/extract-overlay-ramdisk-gan65tu9/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/715318/tftp-deploy-kz_2wv_v/ramdisk/ramdisk.cpio.gz.uboot
226 10:15:29.859565 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 10:15:29.860199 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 10:15:29.860784 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
229 10:15:29.861283 No LXC device requested
230 10:15:29.861828 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 10:15:29.862381 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
232 10:15:29.862919 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 10:15:29.863365 Checking files for TFTP limit of 4294967296 bytes.
234 10:15:29.866288 end: 1 tftp-deploy (duration 00:00:18) [common]
235 10:15:29.866921 start: 2 uboot-action (timeout 00:05:00) [common]
236 10:15:29.867491 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 10:15:29.868060 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 10:15:29.868617 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 10:15:29.869196 Using kernel file from prepare-kernel: 715318/tftp-deploy-kz_2wv_v/kernel/uImage
240 10:15:29.869883 substitutions:
241 10:15:29.870336 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 10:15:29.870776 - {DTB_ADDR}: 0x01070000
243 10:15:29.871212 - {DTB}: 715318/tftp-deploy-kz_2wv_v/dtb/meson-g12b-a311d-libretech-cc.dtb
244 10:15:29.871649 - {INITRD}: 715318/tftp-deploy-kz_2wv_v/ramdisk/ramdisk.cpio.gz.uboot
245 10:15:29.872119 - {KERNEL_ADDR}: 0x01080000
246 10:15:29.872556 - {KERNEL}: 715318/tftp-deploy-kz_2wv_v/kernel/uImage
247 10:15:29.872991 - {LAVA_MAC}: None
248 10:15:29.873467 - {PRESEED_CONFIG}: None
249 10:15:29.873900 - {PRESEED_LOCAL}: None
250 10:15:29.874330 - {RAMDISK_ADDR}: 0x08000000
251 10:15:29.874759 - {RAMDISK}: 715318/tftp-deploy-kz_2wv_v/ramdisk/ramdisk.cpio.gz.uboot
252 10:15:29.875194 - {ROOT_PART}: None
253 10:15:29.875628 - {ROOT}: None
254 10:15:29.876088 - {SERVER_IP}: 192.168.6.2
255 10:15:29.876525 - {TEE_ADDR}: 0x83000000
256 10:15:29.876956 - {TEE}: None
257 10:15:29.877385 Parsed boot commands:
258 10:15:29.877801 - setenv autoload no
259 10:15:29.878229 - setenv initrd_high 0xffffffff
260 10:15:29.878656 - setenv fdt_high 0xffffffff
261 10:15:29.879080 - dhcp
262 10:15:29.879507 - setenv serverip 192.168.6.2
263 10:15:29.879935 - tftpboot 0x01080000 715318/tftp-deploy-kz_2wv_v/kernel/uImage
264 10:15:29.880392 - tftpboot 0x08000000 715318/tftp-deploy-kz_2wv_v/ramdisk/ramdisk.cpio.gz.uboot
265 10:15:29.880824 - tftpboot 0x01070000 715318/tftp-deploy-kz_2wv_v/dtb/meson-g12b-a311d-libretech-cc.dtb
266 10:15:29.881256 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 10:15:29.881695 - bootm 0x01080000 0x08000000 0x01070000
268 10:15:29.882245 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 10:15:29.883887 start: 2.3 connect-device (timeout 00:05:00) [common]
271 10:15:29.884404 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 10:15:29.898666 Setting prompt string to ['lava-test: # ']
273 10:15:29.899619 end: 2.3 connect-device (duration 00:00:00) [common]
274 10:15:29.900052 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 10:15:29.900414 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 10:15:29.900720 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 10:15:29.901372 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 10:15:29.934333 >> OK - accepted request
279 10:15:29.936322 Returned 0 in 0 seconds
280 10:15:30.037547 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 10:15:30.039352 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 10:15:30.040023 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 10:15:30.040592 Setting prompt string to ['Hit any key to stop autoboot']
285 10:15:30.041081 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 10:15:30.042786 Trying 192.168.56.21...
287 10:15:30.043302 Connected to conserv1.
288 10:15:30.043752 Escape character is '^]'.
289 10:15:30.044248
290 10:15:30.044710 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 10:15:30.045201
292 10:15:41.634208 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 10:15:41.634643 bl2_stage_init 0x01
294 10:15:41.634901 bl2_stage_init 0x81
295 10:15:41.639717 hw id: 0x0000 - pwm id 0x01
296 10:15:41.640075 bl2_stage_init 0xc1
297 10:15:41.640328 bl2_stage_init 0x02
298 10:15:41.640574
299 10:15:41.645310 L0:00000000
300 10:15:41.645608 L1:20000703
301 10:15:41.645837 L2:00008067
302 10:15:41.646062 L3:14000000
303 10:15:41.648167 B2:00402000
304 10:15:41.648435 B1:e0f83180
305 10:15:41.648666
306 10:15:41.648891 TE: 58124
307 10:15:41.649115
308 10:15:41.659435 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 10:15:41.659736
310 10:15:41.659968 Board ID = 1
311 10:15:41.660228 Set A53 clk to 24M
312 10:15:41.660452 Set A73 clk to 24M
313 10:15:41.664970 Set clk81 to 24M
314 10:15:41.665243 A53 clk: 1200 MHz
315 10:15:41.665469 A73 clk: 1200 MHz
316 10:15:41.670567 CLK81: 166.6M
317 10:15:41.670845 smccc: 00012a92
318 10:15:41.676188 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 10:15:41.676460 board id: 1
320 10:15:41.684790 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 10:15:41.695470 fw parse done
322 10:15:41.701391 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 10:15:41.744148 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 10:15:41.754964 PIEI prepare done
325 10:15:41.755254 fastboot data load
326 10:15:41.755474 fastboot data verify
327 10:15:41.760668 verify result: 266
328 10:15:41.766191 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 10:15:41.766473 LPDDR4 probe
330 10:15:41.766693 ddr clk to 1584MHz
331 10:15:41.774250 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 10:15:41.811626
333 10:15:41.812013 dmc_version 0001
334 10:15:41.818323 Check phy result
335 10:15:41.824197 INFO : End of CA training
336 10:15:41.824481 INFO : End of initialization
337 10:15:41.829671 INFO : Training has run successfully!
338 10:15:41.829946 Check phy result
339 10:15:41.835273 INFO : End of initialization
340 10:15:41.835576 INFO : End of read enable training
341 10:15:41.840983 INFO : End of fine write leveling
342 10:15:41.846460 INFO : End of Write leveling coarse delay
343 10:15:41.846748 INFO : Training has run successfully!
344 10:15:41.846975 Check phy result
345 10:15:41.852042 INFO : End of initialization
346 10:15:41.852328 INFO : End of read dq deskew training
347 10:15:41.857634 INFO : End of MPR read delay center optimization
348 10:15:41.863233 INFO : End of write delay center optimization
349 10:15:41.868873 INFO : End of read delay center optimization
350 10:15:41.869149 INFO : End of max read latency training
351 10:15:41.874470 INFO : Training has run successfully!
352 10:15:41.874750 1D training succeed
353 10:15:41.883637 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 10:15:41.931226 Check phy result
355 10:15:41.931560 INFO : End of initialization
356 10:15:41.953037 INFO : End of 2D read delay Voltage center optimization
357 10:15:41.973127 INFO : End of 2D read delay Voltage center optimization
358 10:15:42.025267 INFO : End of 2D write delay Voltage center optimization
359 10:15:42.075568 INFO : End of 2D write delay Voltage center optimization
360 10:15:42.081202 INFO : Training has run successfully!
361 10:15:42.081703
362 10:15:42.082106 channel==0
363 10:15:42.086687 RxClkDly_Margin_A0==78 ps 8
364 10:15:42.087127 TxDqDly_Margin_A0==108 ps 11
365 10:15:42.089987 RxClkDly_Margin_A1==88 ps 9
366 10:15:42.090423 TxDqDly_Margin_A1==98 ps 10
367 10:15:42.095527 TrainedVREFDQ_A0==74
368 10:15:42.095977 TrainedVREFDQ_A1==76
369 10:15:42.101108 VrefDac_Margin_A0==26
370 10:15:42.101547 DeviceVref_Margin_A0==40
371 10:15:42.101938 VrefDac_Margin_A1==25
372 10:15:42.106658 DeviceVref_Margin_A1==38
373 10:15:42.107090
374 10:15:42.107485
375 10:15:42.107876 channel==1
376 10:15:42.108302 RxClkDly_Margin_A0==88 ps 9
377 10:15:42.110129 TxDqDly_Margin_A0==98 ps 10
378 10:15:42.115681 RxClkDly_Margin_A1==88 ps 9
379 10:15:42.116138 TxDqDly_Margin_A1==88 ps 9
380 10:15:42.116540 TrainedVREFDQ_A0==77
381 10:15:42.121261 TrainedVREFDQ_A1==77
382 10:15:42.121696 VrefDac_Margin_A0==23
383 10:15:42.126853 DeviceVref_Margin_A0==37
384 10:15:42.127284 VrefDac_Margin_A1==24
385 10:15:42.127675 DeviceVref_Margin_A1==37
386 10:15:42.128088
387 10:15:42.132458 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 10:15:42.132956
389 10:15:42.166101 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 10:15:42.166644 2D training succeed
391 10:15:42.171709 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 10:15:42.177338 auto size-- 65535DDR cs0 size: 2048MB
393 10:15:42.177782 DDR cs1 size: 2048MB
394 10:15:42.182728 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 10:15:42.183167 cs0 DataBus test pass
396 10:15:42.183566 cs1 DataBus test pass
397 10:15:42.188369 cs0 AddrBus test pass
398 10:15:42.188813 cs1 AddrBus test pass
399 10:15:42.189206
400 10:15:42.193994 100bdlr_step_size ps== 420
401 10:15:42.194463 result report
402 10:15:42.194858 boot times 0Enable ddr reg access
403 10:15:42.203944 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 10:15:42.217445 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 10:15:42.791221 0.0;M3 CHK:0;cm4_sp_mode 0
406 10:15:42.791758 MVN_1=0x00000000
407 10:15:42.796828 MVN_2=0x00000000
408 10:15:42.802441 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 10:15:42.802813 OPS=0x10
410 10:15:42.803063 ring efuse init
411 10:15:42.803308 chipver efuse init
412 10:15:42.808117 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 10:15:42.813721 [0.018961 Inits done]
414 10:15:42.814096 secure task start!
415 10:15:42.814342 high task start!
416 10:15:42.818172 low task start!
417 10:15:42.818529 run into bl31
418 10:15:42.824858 NOTICE: BL31: v1.3(release):4fc40b1
419 10:15:42.832836 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 10:15:42.833260 NOTICE: BL31: G12A normal boot!
421 10:15:42.858133 NOTICE: BL31: BL33 decompress pass
422 10:15:42.863777 ERROR: Error initializing runtime service opteed_fast
423 10:15:44.096751
424 10:15:44.097711
425 10:15:44.105266 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 10:15:44.105869
427 10:15:44.106398 Model: Libre Computer AML-A311D-CC Alta
428 10:15:44.313580 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 10:15:44.337018 DRAM: 2 GiB (effective 3.8 GiB)
430 10:15:44.480070 Core: 408 devices, 31 uclasses, devicetree: separate
431 10:15:44.485804 WDT: Not starting watchdog@f0d0
432 10:15:44.518113 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 10:15:44.530608 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 10:15:44.534620 ** Bad device specification mmc 0 **
435 10:15:44.545971 Card did not respond to voltage select! : -110
436 10:15:44.552581 ** Bad device specification mmc 0 **
437 10:15:44.552897 Couldn't find partition mmc 0
438 10:15:44.561781 Card did not respond to voltage select! : -110
439 10:15:44.567328 ** Bad device specification mmc 0 **
440 10:15:44.567763 Couldn't find partition mmc 0
441 10:15:44.571446 Error: could not access storage.
442 10:15:45.833753 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 10:15:45.834186 bl2_stage_init 0x01
444 10:15:45.834411 bl2_stage_init 0x81
445 10:15:45.839183 hw id: 0x0000 - pwm id 0x01
446 10:15:45.839582 bl2_stage_init 0xc1
447 10:15:45.839886 bl2_stage_init 0x02
448 10:15:45.840240
449 10:15:45.844818 L0:00000000
450 10:15:45.845218 L1:20000703
451 10:15:45.845461 L2:00008067
452 10:15:45.845670 L3:14000000
453 10:15:45.847666 B2:00402000
454 10:15:45.847950 B1:e0f83180
455 10:15:45.848197
456 10:15:45.848415 TE: 58124
457 10:15:45.848633
458 10:15:45.858844 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 10:15:45.859200
460 10:15:45.859419 Board ID = 1
461 10:15:45.859624 Set A53 clk to 24M
462 10:15:45.859825 Set A73 clk to 24M
463 10:15:45.864466 Set clk81 to 24M
464 10:15:45.864766 A53 clk: 1200 MHz
465 10:15:45.864991 A73 clk: 1200 MHz
466 10:15:45.870105 CLK81: 166.6M
467 10:15:45.870529 smccc: 00012a92
468 10:15:45.875694 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 10:15:45.876017 board id: 1
470 10:15:45.883405 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 10:15:45.894962 fw parse done
472 10:15:45.900884 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 10:15:45.943544 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 10:15:45.954396 PIEI prepare done
475 10:15:45.954768 fastboot data load
476 10:15:45.955037 fastboot data verify
477 10:15:45.960114 verify result: 266
478 10:15:45.965608 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 10:15:45.966077 LPDDR4 probe
480 10:15:45.966359 ddr clk to 1584MHz
481 10:15:45.973655 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 10:15:46.010011
483 10:15:46.010570 dmc_version 0001
484 10:15:46.017549 Check phy result
485 10:15:46.023415 INFO : End of CA training
486 10:15:46.023752 INFO : End of initialization
487 10:15:46.029087 INFO : Training has run successfully!
488 10:15:46.029412 Check phy result
489 10:15:46.034600 INFO : End of initialization
490 10:15:46.035082 INFO : End of read enable training
491 10:15:46.037997 INFO : End of fine write leveling
492 10:15:46.043456 INFO : End of Write leveling coarse delay
493 10:15:46.049257 INFO : Training has run successfully!
494 10:15:46.049594 Check phy result
495 10:15:46.049845 INFO : End of initialization
496 10:15:46.054747 INFO : End of read dq deskew training
497 10:15:46.060259 INFO : End of MPR read delay center optimization
498 10:15:46.060596 INFO : End of write delay center optimization
499 10:15:46.065947 INFO : End of read delay center optimization
500 10:15:46.071448 INFO : End of max read latency training
501 10:15:46.071917 INFO : Training has run successfully!
502 10:15:46.077113 1D training succeed
503 10:15:46.082984 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 10:15:46.130666 Check phy result
505 10:15:46.131070 INFO : End of initialization
506 10:15:46.153251 INFO : End of 2D read delay Voltage center optimization
507 10:15:46.173454 INFO : End of 2D read delay Voltage center optimization
508 10:15:46.225509 INFO : End of 2D write delay Voltage center optimization
509 10:15:46.274878 INFO : End of 2D write delay Voltage center optimization
510 10:15:46.280415 INFO : Training has run successfully!
511 10:15:46.280749
512 10:15:46.280959 channel==0
513 10:15:46.286004 RxClkDly_Margin_A0==88 ps 9
514 10:15:46.286315 TxDqDly_Margin_A0==98 ps 10
515 10:15:46.291612 RxClkDly_Margin_A1==88 ps 9
516 10:15:46.291924 TxDqDly_Margin_A1==98 ps 10
517 10:15:46.292381 TrainedVREFDQ_A0==74
518 10:15:46.297289 TrainedVREFDQ_A1==74
519 10:15:46.297612 VrefDac_Margin_A0==25
520 10:15:46.297832 DeviceVref_Margin_A0==40
521 10:15:46.302792 VrefDac_Margin_A1==25
522 10:15:46.303128 DeviceVref_Margin_A1==40
523 10:15:46.303348
524 10:15:46.303562
525 10:15:46.308448 channel==1
526 10:15:46.308771 RxClkDly_Margin_A0==98 ps 10
527 10:15:46.308998 TxDqDly_Margin_A0==98 ps 10
528 10:15:46.314059 RxClkDly_Margin_A1==98 ps 10
529 10:15:46.314390 TxDqDly_Margin_A1==88 ps 9
530 10:15:46.319620 TrainedVREFDQ_A0==77
531 10:15:46.320116 TrainedVREFDQ_A1==77
532 10:15:46.320492 VrefDac_Margin_A0==23
533 10:15:46.325219 DeviceVref_Margin_A0==37
534 10:15:46.325542 VrefDac_Margin_A1==22
535 10:15:46.330818 DeviceVref_Margin_A1==37
536 10:15:46.331285
537 10:15:46.331658 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 10:15:46.336423
539 10:15:46.368025 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
540 10:15:46.368479 2D training succeed
541 10:15:46.370128 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 10:15:46.375840 auto size-- 65535DDR cs0 size: 2048MB
543 10:15:46.376474 DDR cs1 size: 2048MB
544 10:15:46.381427 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 10:15:46.381832 cs0 DataBus test pass
546 10:15:46.387437 cs1 DataBus test pass
547 10:15:46.387871 cs0 AddrBus test pass
548 10:15:46.388183 cs1 AddrBus test pass
549 10:15:46.388443
550 10:15:46.392556 100bdlr_step_size ps== 420
551 10:15:46.392996 result report
552 10:15:46.398129 boot times 0Enable ddr reg access
553 10:15:46.402559 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 10:15:46.416071 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 10:15:46.990621 0.0;M3 CHK:0;cm4_sp_mode 0
556 10:15:46.991058 MVN_1=0x00000000
557 10:15:46.997747 MVN_2=0x00000000
558 10:15:47.001864 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 10:15:47.002167 OPS=0x10
560 10:15:47.002384 ring efuse init
561 10:15:47.002588 chipver efuse init
562 10:15:47.010227 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 10:15:47.010561 [0.018961 Inits done]
564 10:15:47.017712 secure task start!
565 10:15:47.018024 high task start!
566 10:15:47.018234 low task start!
567 10:15:47.018436 run into bl31
568 10:15:47.026884 NOTICE: BL31: v1.3(release):4fc40b1
569 10:15:47.032109 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 10:15:47.032427 NOTICE: BL31: G12A normal boot!
571 10:15:47.057789 NOTICE: BL31: BL33 decompress pass
572 10:15:47.062370 ERROR: Error initializing runtime service opteed_fast
573 10:15:48.296278
574 10:15:48.296707
575 10:15:48.304411 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 10:15:48.304847
577 10:15:48.305224 Model: Libre Computer AML-A311D-CC Alta
578 10:15:48.514022 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 10:15:48.536412 DRAM: 2 GiB (effective 3.8 GiB)
580 10:15:48.679383 Core: 408 devices, 31 uclasses, devicetree: separate
581 10:15:48.684545 WDT: Not starting watchdog@f0d0
582 10:15:48.717452 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 10:15:48.729884 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 10:15:48.734190 ** Bad device specification mmc 0 **
585 10:15:48.745200 Card did not respond to voltage select! : -110
586 10:15:48.752463 ** Bad device specification mmc 0 **
587 10:15:48.752910 Couldn't find partition mmc 0
588 10:15:48.761243 Card did not respond to voltage select! : -110
589 10:15:48.766708 ** Bad device specification mmc 0 **
590 10:15:48.767155 Couldn't find partition mmc 0
591 10:15:48.770926 Error: could not access storage.
592 10:15:49.114036 Net: eth0: ethernet@ff3f0000
593 10:15:49.114643 starting USB...
594 10:15:49.366250 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 10:15:49.367037 Starting the controller
596 10:15:49.372359 USB XHCI 1.10
597 10:15:51.085498 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 10:15:51.086336 bl2_stage_init 0x01
599 10:15:51.086913 bl2_stage_init 0x81
600 10:15:51.091126 hw id: 0x0000 - pwm id 0x01
601 10:15:51.091775 bl2_stage_init 0xc1
602 10:15:51.092398 bl2_stage_init 0x02
603 10:15:51.092947
604 10:15:51.096598 L0:00000000
605 10:15:51.097225 L1:20000703
606 10:15:51.097768 L2:00008067
607 10:15:51.098305 L3:14000000
608 10:15:51.102514 B2:00402000
609 10:15:51.103134 B1:e0f83180
610 10:15:51.103686
611 10:15:51.104272 TE: 58124
612 10:15:51.104815
613 10:15:51.108120 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 10:15:51.108739
615 10:15:51.109278 Board ID = 1
616 10:15:51.113541 Set A53 clk to 24M
617 10:15:51.114026 Set A73 clk to 24M
618 10:15:51.114299 Set clk81 to 24M
619 10:15:51.119061 A53 clk: 1200 MHz
620 10:15:51.119714 A73 clk: 1200 MHz
621 10:15:51.120287 CLK81: 166.6M
622 10:15:51.120816 smccc: 00012a92
623 10:15:51.124637 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 10:15:51.130288 board id: 1
625 10:15:51.135758 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 10:15:51.146658 fw parse done
627 10:15:51.151773 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 10:15:51.194649 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 10:15:51.206154 PIEI prepare done
630 10:15:51.206806 fastboot data load
631 10:15:51.207353 fastboot data verify
632 10:15:51.211901 verify result: 266
633 10:15:51.217357 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 10:15:51.217985 LPDDR4 probe
635 10:15:51.218519 ddr clk to 1584MHz
636 10:15:51.225082 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 10:15:51.261693
638 10:15:51.262346 dmc_version 0001
639 10:15:51.269340 Check phy result
640 10:15:51.275115 INFO : End of CA training
641 10:15:51.275734 INFO : End of initialization
642 10:15:51.280743 INFO : Training has run successfully!
643 10:15:51.281358 Check phy result
644 10:15:51.286317 INFO : End of initialization
645 10:15:51.286924 INFO : End of read enable training
646 10:15:51.291919 INFO : End of fine write leveling
647 10:15:51.297534 INFO : End of Write leveling coarse delay
648 10:15:51.298147 INFO : Training has run successfully!
649 10:15:51.298667 Check phy result
650 10:15:51.303127 INFO : End of initialization
651 10:15:51.303731 INFO : End of read dq deskew training
652 10:15:51.308704 INFO : End of MPR read delay center optimization
653 10:15:51.314373 INFO : End of write delay center optimization
654 10:15:51.319946 INFO : End of read delay center optimization
655 10:15:51.320615 INFO : End of max read latency training
656 10:15:51.325534 INFO : Training has run successfully!
657 10:15:51.326099 1D training succeed
658 10:15:51.334441 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 10:15:51.381574 Check phy result
660 10:15:51.382210 INFO : End of initialization
661 10:15:51.403075 INFO : End of 2D read delay Voltage center optimization
662 10:15:51.423236 INFO : End of 2D read delay Voltage center optimization
663 10:15:51.475471 INFO : End of 2D write delay Voltage center optimization
664 10:15:51.525271 INFO : End of 2D write delay Voltage center optimization
665 10:15:51.530813 INFO : Training has run successfully!
666 10:15:51.531403
667 10:15:51.531951 channel==0
668 10:15:51.536374 RxClkDly_Margin_A0==88 ps 9
669 10:15:51.536939 TxDqDly_Margin_A0==98 ps 10
670 10:15:51.542002 RxClkDly_Margin_A1==88 ps 9
671 10:15:51.542565 TxDqDly_Margin_A1==98 ps 10
672 10:15:51.543103 TrainedVREFDQ_A0==74
673 10:15:51.547612 TrainedVREFDQ_A1==75
674 10:15:51.548216 VrefDac_Margin_A0==25
675 10:15:51.548757 DeviceVref_Margin_A0==40
676 10:15:51.553169 VrefDac_Margin_A1==25
677 10:15:51.553740 DeviceVref_Margin_A1==39
678 10:15:51.554262
679 10:15:51.554776
680 10:15:51.558793 channel==1
681 10:15:51.559352 RxClkDly_Margin_A0==98 ps 10
682 10:15:51.559870 TxDqDly_Margin_A0==98 ps 10
683 10:15:51.564333 RxClkDly_Margin_A1==98 ps 10
684 10:15:51.564889 TxDqDly_Margin_A1==88 ps 9
685 10:15:51.570040 TrainedVREFDQ_A0==77
686 10:15:51.570619 TrainedVREFDQ_A1==77
687 10:15:51.571143 VrefDac_Margin_A0==22
688 10:15:51.575604 DeviceVref_Margin_A0==37
689 10:15:51.576191 VrefDac_Margin_A1==22
690 10:15:51.581204 DeviceVref_Margin_A1==37
691 10:15:51.581755
692 10:15:51.582271 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 10:15:51.586780
694 10:15:51.614829 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
695 10:15:51.615510 2D training succeed
696 10:15:51.620356 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 10:15:51.626102 auto size-- 65535DDR cs0 size: 2048MB
698 10:15:51.626710 DDR cs1 size: 2048MB
699 10:15:51.631577 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 10:15:51.632180 cs0 DataBus test pass
701 10:15:51.637217 cs1 DataBus test pass
702 10:15:51.637781 cs0 AddrBus test pass
703 10:15:51.638314 cs1 AddrBus test pass
704 10:15:51.638840
705 10:15:51.642776 100bdlr_step_size ps== 420
706 10:15:51.643337 result report
707 10:15:51.648360 boot times 0Enable ddr reg access
708 10:15:51.653052 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 10:15:51.666343 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 10:15:52.239413 0.0;M3 CHK:0;cm4_sp_mode 0
711 10:15:52.240225 MVN_1=0x00000000
712 10:15:52.244848 MVN_2=0x00000000
713 10:15:52.250615 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 10:15:52.251251 OPS=0x10
715 10:15:52.251780 ring efuse init
716 10:15:52.252341 chipver efuse init
717 10:15:52.258848 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 10:15:52.259471 [0.018961 Inits done]
719 10:15:52.265427 secure task start!
720 10:15:52.266037 high task start!
721 10:15:52.266559 low task start!
722 10:15:52.267070 run into bl31
723 10:15:52.273029 NOTICE: BL31: v1.3(release):4fc40b1
724 10:15:52.280335 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 10:15:52.280943 NOTICE: BL31: G12A normal boot!
726 10:15:52.306207 NOTICE: BL31: BL33 decompress pass
727 10:15:52.311493 ERROR: Error initializing runtime service opteed_fast
728 10:15:53.544682
729 10:15:53.545185
730 10:15:53.552401 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 10:15:53.552866
732 10:15:53.553170 Model: Libre Computer AML-A311D-CC Alta
733 10:15:53.761091 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 10:15:53.784221 DRAM: 2 GiB (effective 3.8 GiB)
735 10:15:53.928050 Core: 408 devices, 31 uclasses, devicetree: separate
736 10:15:53.933751 WDT: Not starting watchdog@f0d0
737 10:15:53.966120 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 10:15:53.978577 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 10:15:53.983371 ** Bad device specification mmc 0 **
740 10:15:53.993919 Card did not respond to voltage select! : -110
741 10:15:54.001254 ** Bad device specification mmc 0 **
742 10:15:54.001667 Couldn't find partition mmc 0
743 10:15:54.009900 Card did not respond to voltage select! : -110
744 10:15:54.015372 ** Bad device specification mmc 0 **
745 10:15:54.015749 Couldn't find partition mmc 0
746 10:15:54.019691 Error: could not access storage.
747 10:15:54.362779 Net: eth0: ethernet@ff3f0000
748 10:15:54.363310 starting USB...
749 10:15:54.614811 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 10:15:54.615632 Starting the controller
751 10:15:54.620735 USB XHCI 1.10
752 10:15:56.784096 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 10:15:56.784913 bl2_stage_init 0x01
754 10:15:56.785495 bl2_stage_init 0x81
755 10:15:56.789567 hw id: 0x0000 - pwm id 0x01
756 10:15:56.790176 bl2_stage_init 0xc1
757 10:15:56.790718 bl2_stage_init 0x02
758 10:15:56.791239
759 10:15:56.795163 L0:00000000
760 10:15:56.795733 L1:20000703
761 10:15:56.796301 L2:00008067
762 10:15:56.796867 L3:14000000
763 10:15:56.798173 B2:00402000
764 10:15:56.798730 B1:e0f83180
765 10:15:56.799260
766 10:15:56.799775 TE: 58124
767 10:15:56.800332
768 10:15:56.809289 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 10:15:56.809855
770 10:15:56.810390 Board ID = 1
771 10:15:56.810907 Set A53 clk to 24M
772 10:15:56.811418 Set A73 clk to 24M
773 10:15:56.814839 Set clk81 to 24M
774 10:15:56.815403 A53 clk: 1200 MHz
775 10:15:56.815933 A73 clk: 1200 MHz
776 10:15:56.818510 CLK81: 166.6M
777 10:15:56.819044 smccc: 00012a92
778 10:15:56.823939 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 10:15:56.829548 board id: 1
780 10:15:56.833989 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 10:15:56.845123 fw parse done
782 10:15:56.850557 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 10:15:56.892920 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 10:15:56.904705 PIEI prepare done
785 10:15:56.905273 fastboot data load
786 10:15:56.905809 fastboot data verify
787 10:15:56.910307 verify result: 266
788 10:15:56.915884 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 10:15:56.916479 LPDDR4 probe
790 10:15:56.916999 ddr clk to 1584MHz
791 10:15:56.923087 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 10:15:56.960274
793 10:15:56.960894 dmc_version 0001
794 10:15:56.966925 Check phy result
795 10:15:56.973744 INFO : End of CA training
796 10:15:56.974303 INFO : End of initialization
797 10:15:56.979338 INFO : Training has run successfully!
798 10:15:56.979898 Check phy result
799 10:15:56.984958 INFO : End of initialization
800 10:15:56.985562 INFO : End of read enable training
801 10:15:56.990526 INFO : End of fine write leveling
802 10:15:56.996164 INFO : End of Write leveling coarse delay
803 10:15:56.996629 INFO : Training has run successfully!
804 10:15:56.997050 Check phy result
805 10:15:57.001792 INFO : End of initialization
806 10:15:57.002229 INFO : End of read dq deskew training
807 10:15:57.007349 INFO : End of MPR read delay center optimization
808 10:15:57.012952 INFO : End of write delay center optimization
809 10:15:57.018563 INFO : End of read delay center optimization
810 10:15:57.019033 INFO : End of max read latency training
811 10:15:57.024072 INFO : Training has run successfully!
812 10:15:57.024509 1D training succeed
813 10:15:57.032976 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 10:15:57.080114 Check phy result
815 10:15:57.080619 INFO : End of initialization
816 10:15:57.102698 INFO : End of 2D read delay Voltage center optimization
817 10:15:57.121937 INFO : End of 2D read delay Voltage center optimization
818 10:15:57.174895 INFO : End of 2D write delay Voltage center optimization
819 10:15:57.224282 INFO : End of 2D write delay Voltage center optimization
820 10:15:57.229849 INFO : Training has run successfully!
821 10:15:57.230291
822 10:15:57.230703 channel==0
823 10:15:57.235401 RxClkDly_Margin_A0==88 ps 9
824 10:15:57.235864 TxDqDly_Margin_A0==98 ps 10
825 10:15:57.238735 RxClkDly_Margin_A1==88 ps 9
826 10:15:57.239171 TxDqDly_Margin_A1==98 ps 10
827 10:15:57.244358 TrainedVREFDQ_A0==74
828 10:15:57.244798 TrainedVREFDQ_A1==74
829 10:15:57.245216 VrefDac_Margin_A0==25
830 10:15:57.249960 DeviceVref_Margin_A0==40
831 10:15:57.250426 VrefDac_Margin_A1==25
832 10:15:57.255542 DeviceVref_Margin_A1==40
833 10:15:57.256023
834 10:15:57.256439
835 10:15:57.256853 channel==1
836 10:15:57.257252 RxClkDly_Margin_A0==88 ps 9
837 10:15:57.261217 TxDqDly_Margin_A0==88 ps 9
838 10:15:57.261699 RxClkDly_Margin_A1==98 ps 10
839 10:15:57.266749 TxDqDly_Margin_A1==98 ps 10
840 10:15:57.267210 TrainedVREFDQ_A0==77
841 10:15:57.267603 TrainedVREFDQ_A1==77
842 10:15:57.272300 VrefDac_Margin_A0==22
843 10:15:57.272724 DeviceVref_Margin_A0==37
844 10:15:57.277892 VrefDac_Margin_A1==23
845 10:15:57.278329 DeviceVref_Margin_A1==37
846 10:15:57.278714
847 10:15:57.283498 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 10:15:57.283917
849 10:15:57.311510 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
850 10:15:57.317152 2D training succeed
851 10:15:57.322776 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 10:15:57.323203 auto size-- 65535DDR cs0 size: 2048MB
853 10:15:57.328403 DDR cs1 size: 2048MB
854 10:15:57.328855 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 10:15:57.333970 cs0 DataBus test pass
856 10:15:57.334392 cs1 DataBus test pass
857 10:15:57.334777 cs0 AddrBus test pass
858 10:15:57.339487 cs1 AddrBus test pass
859 10:15:57.339903
860 10:15:57.340335 100bdlr_step_size ps== 420
861 10:15:57.340727 result report
862 10:15:57.345096 boot times 0Enable ddr reg access
863 10:15:57.352349 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 10:15:57.365662 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 10:15:57.939281 0.0;M3 CHK:0;cm4_sp_mode 0
866 10:15:57.939861 MVN_1=0x00000000
867 10:15:57.944866 MVN_2=0x00000000
868 10:15:57.950551 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 10:15:57.951016 OPS=0x10
870 10:15:57.951432 ring efuse init
871 10:15:57.951832 chipver efuse init
872 10:15:57.956109 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 10:15:57.961824 [0.018961 Inits done]
874 10:15:57.962259 secure task start!
875 10:15:57.962659 high task start!
876 10:15:57.966215 low task start!
877 10:15:57.966651 run into bl31
878 10:15:57.972930 NOTICE: BL31: v1.3(release):4fc40b1
879 10:15:57.979743 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 10:15:57.980207 NOTICE: BL31: G12A normal boot!
881 10:15:58.006097 NOTICE: BL31: BL33 decompress pass
882 10:15:58.010800 ERROR: Error initializing runtime service opteed_fast
883 10:15:59.244629
884 10:15:59.245205
885 10:15:59.252234 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 10:15:59.252915
887 10:15:59.253360 Model: Libre Computer AML-A311D-CC Alta
888 10:15:59.460528 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 10:15:59.484074 DRAM: 2 GiB (effective 3.8 GiB)
890 10:15:59.627965 Core: 408 devices, 31 uclasses, devicetree: separate
891 10:15:59.633416 WDT: Not starting watchdog@f0d0
892 10:15:59.665929 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 10:15:59.678432 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 10:15:59.682376 ** Bad device specification mmc 0 **
895 10:15:59.693660 Card did not respond to voltage select! : -110
896 10:15:59.700448 ** Bad device specification mmc 0 **
897 10:15:59.701118 Couldn't find partition mmc 0
898 10:15:59.709728 Card did not respond to voltage select! : -110
899 10:15:59.715211 ** Bad device specification mmc 0 **
900 10:15:59.715870 Couldn't find partition mmc 0
901 10:15:59.719298 Error: could not access storage.
902 10:16:00.062848 Net: eth0: ethernet@ff3f0000
903 10:16:00.063642 starting USB...
904 10:16:00.315599 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 10:16:00.316409 Starting the controller
906 10:16:00.321601 USB XHCI 1.10
907 10:16:02.183915 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
908 10:16:02.184489 bl2_stage_init 0x81
909 10:16:02.189450 hw id: 0x0000 - pwm id 0x01
910 10:16:02.189825 bl2_stage_init 0xc1
911 10:16:02.190097 bl2_stage_init 0x02
912 10:16:02.190358
913 10:16:02.195101 L0:00000000
914 10:16:02.195628 L1:20000703
915 10:16:02.196080 L2:00008067
916 10:16:02.196491 L3:14000000
917 10:16:02.196887 B2:00402000
918 10:16:02.198221 B1:e0f83180
919 10:16:02.198563
920 10:16:02.198820 TE: 58150
921 10:16:02.199076
922 10:16:02.209585 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
923 10:16:02.209974
924 10:16:02.210235 Board ID = 1
925 10:16:02.210483 Set A53 clk to 24M
926 10:16:02.210729 Set A73 clk to 24M
927 10:16:02.214713 Set clk81 to 24M
928 10:16:02.215071 A53 clk: 1200 MHz
929 10:16:02.215326 A73 clk: 1200 MHz
930 10:16:02.220265 CLK81: 166.6M
931 10:16:02.221127 smccc: 00012aac
932 10:16:02.225814 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
933 10:16:02.226276 board id: 1
934 10:16:02.234150 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
935 10:16:02.245190 fw parse done
936 10:16:02.251011 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
937 10:16:02.292668 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
938 10:16:02.304555 PIEI prepare done
939 10:16:02.305012 fastboot data load
940 10:16:02.305301 fastboot data verify
941 10:16:02.310150 verify result: 266
942 10:16:02.315733 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
943 10:16:02.316199 LPDDR4 probe
944 10:16:02.316491 ddr clk to 1584MHz
945 10:16:02.322827 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
946 10:16:02.360124
947 10:16:02.360785 dmc_version 0001
948 10:16:02.367234 Check phy result
949 10:16:02.373480 INFO : End of CA training
950 10:16:02.373989 INFO : End of initialization
951 10:16:02.379076 INFO : Training has run successfully!
952 10:16:02.379575 Check phy result
953 10:16:02.384654 INFO : End of initialization
954 10:16:02.385145 INFO : End of read enable training
955 10:16:02.388395 INFO : End of fine write leveling
956 10:16:02.393688 INFO : End of Write leveling coarse delay
957 10:16:02.399276 INFO : Training has run successfully!
958 10:16:02.399800 Check phy result
959 10:16:02.400301 INFO : End of initialization
960 10:16:02.404823 INFO : End of read dq deskew training
961 10:16:02.410452 INFO : End of MPR read delay center optimization
962 10:16:02.410966 INFO : End of write delay center optimization
963 10:16:02.416069 INFO : End of read delay center optimization
964 10:16:02.421673 INFO : End of max read latency training
965 10:16:02.422185 INFO : Training has run successfully!
966 10:16:02.427260 1D training succeed
967 10:16:02.432203 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
968 10:16:02.480483 Check phy result
969 10:16:02.481006 INFO : End of initialization
970 10:16:02.501455 INFO : End of 2D read delay Voltage center optimization
971 10:16:02.521834 INFO : End of 2D read delay Voltage center optimization
972 10:16:02.573404 INFO : End of 2D write delay Voltage center optimization
973 10:16:02.623563 INFO : End of 2D write delay Voltage center optimization
974 10:16:02.629077 INFO : Training has run successfully!
975 10:16:02.629595
976 10:16:02.630065 channel==0
977 10:16:02.634692 RxClkDly_Margin_A0==88 ps 9
978 10:16:02.635199 TxDqDly_Margin_A0==98 ps 10
979 10:16:02.640294 RxClkDly_Margin_A1==88 ps 9
980 10:16:02.640801 TxDqDly_Margin_A1==98 ps 10
981 10:16:02.641260 TrainedVREFDQ_A0==74
982 10:16:02.645890 TrainedVREFDQ_A1==74
983 10:16:02.646396 VrefDac_Margin_A0==25
984 10:16:02.646854 DeviceVref_Margin_A0==40
985 10:16:02.651493 VrefDac_Margin_A1==25
986 10:16:02.652017 DeviceVref_Margin_A1==40
987 10:16:02.652478
988 10:16:02.652930
989 10:16:02.657093 channel==1
990 10:16:02.657597 RxClkDly_Margin_A0==98 ps 10
991 10:16:02.658052 TxDqDly_Margin_A0==98 ps 10
992 10:16:02.662680 RxClkDly_Margin_A1==98 ps 10
993 10:16:02.663186 TxDqDly_Margin_A1==88 ps 9
994 10:16:02.668330 TrainedVREFDQ_A0==77
995 10:16:02.668839 TrainedVREFDQ_A1==77
996 10:16:02.669294 VrefDac_Margin_A0==22
997 10:16:02.673951 DeviceVref_Margin_A0==37
998 10:16:02.674458 VrefDac_Margin_A1==22
999 10:16:02.679527 DeviceVref_Margin_A1==37
1000 10:16:02.680062
1001 10:16:02.680525 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1002 10:16:02.685106
1003 10:16:02.713106 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1004 10:16:02.713657 2D training succeed
1005 10:16:02.718692 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1006 10:16:02.724262 auto size-- 65535DDR cs0 size: 2048MB
1007 10:16:02.724768 DDR cs1 size: 2048MB
1008 10:16:02.729890 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1009 10:16:02.730388 cs0 DataBus test pass
1010 10:16:02.735496 cs1 DataBus test pass
1011 10:16:02.736034 cs0 AddrBus test pass
1012 10:16:02.736510 cs1 AddrBus test pass
1013 10:16:02.736961
1014 10:16:02.741092 100bdlr_step_size ps== 420
1015 10:16:02.741639 result report
1016 10:16:02.746804 boot times 0Enable ddr reg access
1017 10:16:02.751953 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1018 10:16:02.764619 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1019 10:16:03.337673 0.0;M3 CHK:0;cm4_sp_mode 0
1020 10:16:03.338107 MVN_1=0x00000000
1021 10:16:03.343142 MVN_2=0x00000000
1022 10:16:03.348865 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1023 10:16:03.349333 OPS=0x10
1024 10:16:03.349603 ring efuse init
1025 10:16:03.349811 chipver efuse init
1026 10:16:03.357023 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1027 10:16:03.357367 [0.018960 Inits done]
1028 10:16:03.363691 secure task start!
1029 10:16:03.364213 high task start!
1030 10:16:03.364571 low task start!
1031 10:16:03.364898 run into bl31
1032 10:16:03.371299 NOTICE: BL31: v1.3(release):4fc40b1
1033 10:16:03.379117 NOTICE: BL31: Built : 15:58:17, May 22 2019
1034 10:16:03.379456 NOTICE: BL31: G12A normal boot!
1035 10:16:03.404593 NOTICE: BL31: BL33 decompress pass
1036 10:16:03.410213 ERROR: Error initializing runtime service opteed_fast
1037 10:16:04.643101
1038 10:16:04.643763
1039 10:16:04.651482 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1040 10:16:04.652012
1041 10:16:04.652473 Model: Libre Computer AML-A311D-CC Alta
1042 10:16:04.858966 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1043 10:16:04.882314 DRAM: 2 GiB (effective 3.8 GiB)
1044 10:16:05.026277 Core: 408 devices, 31 uclasses, devicetree: separate
1045 10:16:05.031122 WDT: Not starting watchdog@f0d0
1046 10:16:05.064491 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1047 10:16:05.076852 Loading Environment from FAT... Card did not respond to voltage select! : -110
1048 10:16:05.080862 ** Bad device specification mmc 0 **
1049 10:16:05.092211 Card did not respond to voltage select! : -110
1050 10:16:05.098878 ** Bad device specification mmc 0 **
1051 10:16:05.099383 Couldn't find partition mmc 0
1052 10:16:05.108134 Card did not respond to voltage select! : -110
1053 10:16:05.113735 ** Bad device specification mmc 0 **
1054 10:16:05.114237 Couldn't find partition mmc 0
1055 10:16:05.118238 Error: could not access storage.
1056 10:16:05.461099 Net: eth0: ethernet@ff3f0000
1057 10:16:05.461490 starting USB...
1058 10:16:05.713019 Bus usb@ff500000: Register 3000140 NbrPorts 3
1059 10:16:05.713576 Starting the controller
1060 10:16:05.718991 USB XHCI 1.10
1061 10:16:07.274122 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1062 10:16:07.282472 scanning usb for storage devices... 0 Storage Device(s) found
1064 10:16:07.333609 Hit any key to stop autoboot: 1
1065 10:16:07.334428 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1066 10:16:07.334785 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1067 10:16:07.335045 Setting prompt string to ['=>']
1068 10:16:07.335298 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1069 10:16:07.339855 0
1070 10:16:07.340499 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1071 10:16:07.340781 Sending with 10 millisecond of delay
1073 10:16:08.475484 => setenv autoload no
1074 10:16:08.486390 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1075 10:16:08.491860 setenv autoload no
1076 10:16:08.492718 Sending with 10 millisecond of delay
1078 10:16:10.290202 => setenv initrd_high 0xffffffff
1079 10:16:10.301033 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1080 10:16:10.302001 setenv initrd_high 0xffffffff
1081 10:16:10.302768 Sending with 10 millisecond of delay
1083 10:16:11.919592 => setenv fdt_high 0xffffffff
1084 10:16:11.930539 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1085 10:16:11.931579 setenv fdt_high 0xffffffff
1086 10:16:11.932408 Sending with 10 millisecond of delay
1088 10:16:12.224573 => dhcp
1089 10:16:12.235412 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1090 10:16:12.236411 dhcp
1091 10:16:12.236899 Speed: 1000, full duplex
1092 10:16:12.237361 BOOTP broadcast 1
1093 10:16:12.483805 BOOTP broadcast 2
1094 10:16:12.509279 DHCP client bound to address 192.168.6.33 (274 ms)
1095 10:16:12.510176 Sending with 10 millisecond of delay
1097 10:16:14.188612 => setenv serverip 192.168.6.2
1098 10:16:14.199960 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 10:16:14.200554 setenv serverip 192.168.6.2
1100 10:16:14.201406 Sending with 10 millisecond of delay
1102 10:16:17.929718 => tftpboot 0x01080000 715318/tftp-deploy-kz_2wv_v/kernel/uImage
1103 10:16:17.940359 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 10:16:17.941380 tftpboot 0x01080000 715318/tftp-deploy-kz_2wv_v/kernel/uImage
1105 10:16:17.941832 Speed: 1000, full duplex
1106 10:16:17.942262 Using ethernet@ff3f0000 device
1107 10:16:17.943021 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1108 10:16:17.948557 Filename '715318/tftp-deploy-kz_2wv_v/kernel/uImage'.
1109 10:16:17.952410 Load address: 0x1080000
1110 10:16:21.062502 Loading: *################################################## 45.1 MiB
1111 10:16:21.063113 14.5 MiB/s
1112 10:16:21.063544 done
1113 10:16:21.066683 Bytes transferred = 47288896 (2d19240 hex)
1114 10:16:21.067431 Sending with 10 millisecond of delay
1116 10:16:25.756101 => tftpboot 0x08000000 715318/tftp-deploy-kz_2wv_v/ramdisk/ramdisk.cpio.gz.uboot
1117 10:16:25.766905 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1118 10:16:25.767773 tftpboot 0x08000000 715318/tftp-deploy-kz_2wv_v/ramdisk/ramdisk.cpio.gz.uboot
1119 10:16:25.768263 Speed: 1000, full duplex
1120 10:16:25.768666 Using ethernet@ff3f0000 device
1121 10:16:25.770310 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1122 10:16:25.778316 Filename '715318/tftp-deploy-kz_2wv_v/ramdisk/ramdisk.cpio.gz.uboot'.
1123 10:16:25.778770 Load address: 0x8000000
1124 10:16:30.937552 Loading: *####### UDP wrong checksum 000000ff 0000b7e7
1125 10:16:30.956511 UDP wrong checksum 000000ff 000046da
1126 10:16:32.868845 T ########################################## UDP wrong checksum 00000005 0000c067
1127 10:16:37.870105 T UDP wrong checksum 00000005 0000c067
1128 10:16:37.887247 UDP wrong checksum 000000ff 0000f97b
1129 10:16:37.894392 UDP wrong checksum 000000ff 00008d6e
1130 10:16:47.872211 T T UDP wrong checksum 00000005 0000c067
1131 10:16:56.323085 T UDP wrong checksum 000000ff 0000f139
1132 10:16:56.343935 UDP wrong checksum 000000ff 0000822c
1133 10:16:58.591338 T UDP wrong checksum 000000ff 000015b3
1134 10:16:58.603530 UDP wrong checksum 000000ff 0000b2a5
1135 10:17:07.875269 T T UDP wrong checksum 00000005 0000c067
1136 10:17:22.879961 T T
1137 10:17:22.880618 Retry count exceeded; starting again
1139 10:17:22.882165 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
1142 10:17:22.884265 end: 2.4 uboot-commands (duration 00:01:53) [common]
1144 10:17:22.885772 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1146 10:17:22.886930 end: 2 uboot-action (duration 00:01:53) [common]
1148 10:17:22.888615 Cleaning after the job
1149 10:17:22.889213 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/715318/tftp-deploy-kz_2wv_v/ramdisk
1150 10:17:22.891313 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/715318/tftp-deploy-kz_2wv_v/kernel
1151 10:17:22.942139 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/715318/tftp-deploy-kz_2wv_v/dtb
1152 10:17:22.942899 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/715318/tftp-deploy-kz_2wv_v/modules
1153 10:17:22.961929 start: 4.1 power-off (timeout 00:00:30) [common]
1154 10:17:22.962524 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1155 10:17:22.992869 >> OK - accepted request
1156 10:17:22.994934 Returned 0 in 0 seconds
1157 10:17:23.095605 end: 4.1 power-off (duration 00:00:00) [common]
1159 10:17:23.096524 start: 4.2 read-feedback (timeout 00:10:00) [common]
1160 10:17:23.097179 Listened to connection for namespace 'common' for up to 1s
1161 10:17:24.097247 Finalising connection for namespace 'common'
1162 10:17:24.097925 Disconnecting from shell: Finalise
1163 10:17:24.098456 =>
1164 10:17:24.199425 end: 4.2 read-feedback (duration 00:00:01) [common]
1165 10:17:24.200108 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/715318
1166 10:17:24.497396 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/715318
1167 10:17:24.498162 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.