Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 10:22:59.402436 lava-dispatcher, installed at version: 2024.01
2 10:22:59.403232 start: 0 validate
3 10:22:59.403704 Start time: 2024-09-06 10:22:59.403674+00:00 (UTC)
4 10:22:59.404267 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 10:22:59.404803 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 10:22:59.448468 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 10:22:59.449057 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240906%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-17%2Fkernel%2FImage exists
8 10:22:59.482367 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 10:22:59.483321 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240906%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-17%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 10:23:00.540178 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 10:23:00.540694 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240906%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-17%2Fmodules.tar.xz exists
12 10:23:00.589340 validate duration: 1.19
14 10:23:00.590806 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:23:00.591432 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:23:00.592035 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:23:00.593003 Not decompressing ramdisk as can be used compressed.
18 10:23:00.593744 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 10:23:00.594196 saving as /var/lib/lava/dispatcher/tmp/715592/tftp-deploy-2v9jzbfo/ramdisk/rootfs.cpio.gz
20 10:23:00.594679 total size: 8181887 (7 MB)
21 10:23:00.638275 progress 0 % (0 MB)
22 10:23:00.650610 progress 5 % (0 MB)
23 10:23:00.661983 progress 10 % (0 MB)
24 10:23:00.674168 progress 15 % (1 MB)
25 10:23:00.682328 progress 20 % (1 MB)
26 10:23:00.688077 progress 25 % (1 MB)
27 10:23:00.693362 progress 30 % (2 MB)
28 10:23:00.699104 progress 35 % (2 MB)
29 10:23:00.704409 progress 40 % (3 MB)
30 10:23:00.710119 progress 45 % (3 MB)
31 10:23:00.715585 progress 50 % (3 MB)
32 10:23:00.721241 progress 55 % (4 MB)
33 10:23:00.726520 progress 60 % (4 MB)
34 10:23:00.732232 progress 65 % (5 MB)
35 10:23:00.737488 progress 70 % (5 MB)
36 10:23:00.743103 progress 75 % (5 MB)
37 10:23:00.748351 progress 80 % (6 MB)
38 10:23:00.754015 progress 85 % (6 MB)
39 10:23:00.759250 progress 90 % (7 MB)
40 10:23:00.764682 progress 95 % (7 MB)
41 10:23:00.769857 progress 100 % (7 MB)
42 10:23:00.770520 7 MB downloaded in 0.18 s (44.38 MB/s)
43 10:23:00.771103 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:23:00.772067 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:23:00.772394 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:23:00.772687 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:23:00.773182 downloading http://storage.kernelci.org/next/master/next-20240906/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-17/kernel/Image
49 10:23:00.773446 saving as /var/lib/lava/dispatcher/tmp/715592/tftp-deploy-2v9jzbfo/kernel/Image
50 10:23:00.773663 total size: 39455232 (37 MB)
51 10:23:00.773879 No compression specified
52 10:23:00.811048 progress 0 % (0 MB)
53 10:23:00.835906 progress 5 % (1 MB)
54 10:23:00.860100 progress 10 % (3 MB)
55 10:23:00.884221 progress 15 % (5 MB)
56 10:23:00.908427 progress 20 % (7 MB)
57 10:23:00.933170 progress 25 % (9 MB)
58 10:23:00.957342 progress 30 % (11 MB)
59 10:23:00.981678 progress 35 % (13 MB)
60 10:23:01.006209 progress 40 % (15 MB)
61 10:23:01.031117 progress 45 % (16 MB)
62 10:23:01.056073 progress 50 % (18 MB)
63 10:23:01.080527 progress 55 % (20 MB)
64 10:23:01.105051 progress 60 % (22 MB)
65 10:23:01.129992 progress 65 % (24 MB)
66 10:23:01.154575 progress 70 % (26 MB)
67 10:23:01.179559 progress 75 % (28 MB)
68 10:23:01.204108 progress 80 % (30 MB)
69 10:23:01.228977 progress 85 % (32 MB)
70 10:23:01.253600 progress 90 % (33 MB)
71 10:23:01.278020 progress 95 % (35 MB)
72 10:23:01.302120 progress 100 % (37 MB)
73 10:23:01.302645 37 MB downloaded in 0.53 s (71.13 MB/s)
74 10:23:01.303180 end: 1.2.1 http-download (duration 00:00:01) [common]
76 10:23:01.304081 end: 1.2 download-retry (duration 00:00:01) [common]
77 10:23:01.304413 start: 1.3 download-retry (timeout 00:09:59) [common]
78 10:23:01.304720 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 10:23:01.305234 downloading http://storage.kernelci.org/next/master/next-20240906/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-17/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 10:23:01.305535 saving as /var/lib/lava/dispatcher/tmp/715592/tftp-deploy-2v9jzbfo/dtb/meson-g12b-a311d-libretech-cc.dtb
81 10:23:01.305770 total size: 54703 (0 MB)
82 10:23:01.306005 No compression specified
83 10:23:01.349196 progress 59 % (0 MB)
84 10:23:01.350058 progress 100 % (0 MB)
85 10:23:01.350664 0 MB downloaded in 0.04 s (1.16 MB/s)
86 10:23:01.351175 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:23:01.352102 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:23:01.352419 start: 1.4 download-retry (timeout 00:09:59) [common]
90 10:23:01.352717 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 10:23:01.353299 downloading http://storage.kernelci.org/next/master/next-20240906/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-17/modules.tar.xz
92 10:23:01.353583 saving as /var/lib/lava/dispatcher/tmp/715592/tftp-deploy-2v9jzbfo/modules/modules.tar
93 10:23:01.353815 total size: 11688868 (11 MB)
94 10:23:01.354051 Using unxz to decompress xz
95 10:23:01.393642 progress 0 % (0 MB)
96 10:23:01.464007 progress 5 % (0 MB)
97 10:23:01.543249 progress 10 % (1 MB)
98 10:23:01.631631 progress 15 % (1 MB)
99 10:23:01.714462 progress 20 % (2 MB)
100 10:23:01.798612 progress 25 % (2 MB)
101 10:23:01.880567 progress 30 % (3 MB)
102 10:23:01.956464 progress 35 % (3 MB)
103 10:23:02.036497 progress 40 % (4 MB)
104 10:23:02.114171 progress 45 % (5 MB)
105 10:23:02.194290 progress 50 % (5 MB)
106 10:23:02.272503 progress 55 % (6 MB)
107 10:23:02.358479 progress 60 % (6 MB)
108 10:23:02.441830 progress 65 % (7 MB)
109 10:23:02.527490 progress 70 % (7 MB)
110 10:23:02.622656 progress 75 % (8 MB)
111 10:23:02.718794 progress 80 % (8 MB)
112 10:23:02.800362 progress 85 % (9 MB)
113 10:23:02.877977 progress 90 % (10 MB)
114 10:23:02.953418 progress 95 % (10 MB)
115 10:23:03.031047 progress 100 % (11 MB)
116 10:23:03.043862 11 MB downloaded in 1.69 s (6.60 MB/s)
117 10:23:03.044751 end: 1.4.1 http-download (duration 00:00:02) [common]
119 10:23:03.046353 end: 1.4 download-retry (duration 00:00:02) [common]
120 10:23:03.046870 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 10:23:03.047383 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 10:23:03.048183 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:23:03.048718 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 10:23:03.049707 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx
125 10:23:03.050529 makedir: /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin
126 10:23:03.051155 makedir: /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/tests
127 10:23:03.051759 makedir: /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/results
128 10:23:03.052417 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-add-keys
129 10:23:03.053370 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-add-sources
130 10:23:03.054306 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-background-process-start
131 10:23:03.055250 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-background-process-stop
132 10:23:03.056278 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-common-functions
133 10:23:03.057256 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-echo-ipv4
134 10:23:03.058181 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-install-packages
135 10:23:03.059096 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-installed-packages
136 10:23:03.060005 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-os-build
137 10:23:03.060915 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-probe-channel
138 10:23:03.061818 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-probe-ip
139 10:23:03.062756 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-target-ip
140 10:23:03.063638 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-target-mac
141 10:23:03.064557 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-target-storage
142 10:23:03.065463 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-test-case
143 10:23:03.066345 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-test-event
144 10:23:03.067245 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-test-feedback
145 10:23:03.068180 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-test-raise
146 10:23:03.069103 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-test-reference
147 10:23:03.070029 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-test-runner
148 10:23:03.070954 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-test-set
149 10:23:03.071835 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-test-shell
150 10:23:03.072774 Updating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-install-packages (oe)
151 10:23:03.073734 Updating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/bin/lava-installed-packages (oe)
152 10:23:03.074551 Creating /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/environment
153 10:23:03.075257 LAVA metadata
154 10:23:03.075742 - LAVA_JOB_ID=715592
155 10:23:03.076207 - LAVA_DISPATCHER_IP=192.168.6.2
156 10:23:03.076874 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 10:23:03.078673 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 10:23:03.079263 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 10:23:03.079673 skipped lava-vland-overlay
160 10:23:03.080198 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 10:23:03.080706 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 10:23:03.081127 skipped lava-multinode-overlay
163 10:23:03.081607 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 10:23:03.082104 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 10:23:03.082570 Loading test definitions
166 10:23:03.083109 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 10:23:03.083545 Using /lava-715592 at stage 0
168 10:23:03.085044 uuid=715592_1.5.2.4.1 testdef=None
169 10:23:03.085380 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 10:23:03.085651 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 10:23:03.087446 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 10:23:03.088287 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 10:23:03.090564 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 10:23:03.091420 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 10:23:03.093630 runner path: /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/0/tests/0_dmesg test_uuid 715592_1.5.2.4.1
178 10:23:03.094200 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 10:23:03.094974 Creating lava-test-runner.conf files
181 10:23:03.095177 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/715592/lava-overlay-pgf6ehhx/lava-715592/0 for stage 0
182 10:23:03.095511 - 0_dmesg
183 10:23:03.095863 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 10:23:03.096183 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 10:23:03.120160 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 10:23:03.120569 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 10:23:03.120832 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 10:23:03.121097 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 10:23:03.121360 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 10:23:04.047485 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 10:23:04.047953 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 10:23:04.048480 extracting modules file /var/lib/lava/dispatcher/tmp/715592/tftp-deploy-2v9jzbfo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/715592/extract-overlay-ramdisk-p4bkd9yo/ramdisk
193 10:23:05.424335 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 10:23:05.424801 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 10:23:05.425073 [common] Applying overlay /var/lib/lava/dispatcher/tmp/715592/compress-overlay-jmvg8x86/overlay-1.5.2.5.tar.gz to ramdisk
196 10:23:05.425284 [common] Applying overlay /var/lib/lava/dispatcher/tmp/715592/compress-overlay-jmvg8x86/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/715592/extract-overlay-ramdisk-p4bkd9yo/ramdisk
197 10:23:05.455522 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 10:23:05.455916 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 10:23:05.456226 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 10:23:05.456455 Converting downloaded kernel to a uImage
201 10:23:05.456758 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/715592/tftp-deploy-2v9jzbfo/kernel/Image /var/lib/lava/dispatcher/tmp/715592/tftp-deploy-2v9jzbfo/kernel/uImage
202 10:23:05.872097 output: Image Name:
203 10:23:05.872514 output: Created: Fri Sep 6 10:23:05 2024
204 10:23:05.872720 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 10:23:05.872922 output: Data Size: 39455232 Bytes = 38530.50 KiB = 37.63 MiB
206 10:23:05.873121 output: Load Address: 01080000
207 10:23:05.873316 output: Entry Point: 01080000
208 10:23:05.873511 output:
209 10:23:05.873842 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 10:23:05.874102 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 10:23:05.874365 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 10:23:05.874610 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 10:23:05.874859 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 10:23:05.875109 Building ramdisk /var/lib/lava/dispatcher/tmp/715592/extract-overlay-ramdisk-p4bkd9yo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/715592/extract-overlay-ramdisk-p4bkd9yo/ramdisk
215 10:23:08.831772 >> 187492 blocks
216 10:23:17.288448 Adding RAMdisk u-boot header.
217 10:23:17.289116 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/715592/extract-overlay-ramdisk-p4bkd9yo/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/715592/extract-overlay-ramdisk-p4bkd9yo/ramdisk.cpio.gz.uboot
218 10:23:17.557759 output: Image Name:
219 10:23:17.558175 output: Created: Fri Sep 6 10:23:17 2024
220 10:23:17.558382 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 10:23:17.558585 output: Data Size: 26660463 Bytes = 26035.61 KiB = 25.43 MiB
222 10:23:17.558785 output: Load Address: 00000000
223 10:23:17.558981 output: Entry Point: 00000000
224 10:23:17.559177 output:
225 10:23:17.559785 rename /var/lib/lava/dispatcher/tmp/715592/extract-overlay-ramdisk-p4bkd9yo/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/715592/tftp-deploy-2v9jzbfo/ramdisk/ramdisk.cpio.gz.uboot
226 10:23:17.560352 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 10:23:17.560887 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 10:23:17.561403 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 10:23:17.561847 No LXC device requested
230 10:23:17.562335 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 10:23:17.562829 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 10:23:17.563309 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 10:23:17.563708 Checking files for TFTP limit of 4294967296 bytes.
234 10:23:17.566358 end: 1 tftp-deploy (duration 00:00:17) [common]
235 10:23:17.566925 start: 2 uboot-action (timeout 00:05:00) [common]
236 10:23:17.567440 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 10:23:17.567930 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 10:23:17.568461 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 10:23:17.568983 Using kernel file from prepare-kernel: 715592/tftp-deploy-2v9jzbfo/kernel/uImage
240 10:23:17.569598 substitutions:
241 10:23:17.570005 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 10:23:17.570404 - {DTB_ADDR}: 0x01070000
243 10:23:17.570801 - {DTB}: 715592/tftp-deploy-2v9jzbfo/dtb/meson-g12b-a311d-libretech-cc.dtb
244 10:23:17.571198 - {INITRD}: 715592/tftp-deploy-2v9jzbfo/ramdisk/ramdisk.cpio.gz.uboot
245 10:23:17.571592 - {KERNEL_ADDR}: 0x01080000
246 10:23:17.572003 - {KERNEL}: 715592/tftp-deploy-2v9jzbfo/kernel/uImage
247 10:23:17.572406 - {LAVA_MAC}: None
248 10:23:17.572832 - {PRESEED_CONFIG}: None
249 10:23:17.573222 - {PRESEED_LOCAL}: None
250 10:23:17.573608 - {RAMDISK_ADDR}: 0x08000000
251 10:23:17.573990 - {RAMDISK}: 715592/tftp-deploy-2v9jzbfo/ramdisk/ramdisk.cpio.gz.uboot
252 10:23:17.574378 - {ROOT_PART}: None
253 10:23:17.574765 - {ROOT}: None
254 10:23:17.575149 - {SERVER_IP}: 192.168.6.2
255 10:23:17.575540 - {TEE_ADDR}: 0x83000000
256 10:23:17.575926 - {TEE}: None
257 10:23:17.576346 Parsed boot commands:
258 10:23:17.576724 - setenv autoload no
259 10:23:17.577113 - setenv initrd_high 0xffffffff
260 10:23:17.577501 - setenv fdt_high 0xffffffff
261 10:23:17.577885 - dhcp
262 10:23:17.578273 - setenv serverip 192.168.6.2
263 10:23:17.578659 - tftpboot 0x01080000 715592/tftp-deploy-2v9jzbfo/kernel/uImage
264 10:23:17.579043 - tftpboot 0x08000000 715592/tftp-deploy-2v9jzbfo/ramdisk/ramdisk.cpio.gz.uboot
265 10:23:17.579430 - tftpboot 0x01070000 715592/tftp-deploy-2v9jzbfo/dtb/meson-g12b-a311d-libretech-cc.dtb
266 10:23:17.579815 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 10:23:17.580236 - bootm 0x01080000 0x08000000 0x01070000
268 10:23:17.580735 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 10:23:17.582208 start: 2.3 connect-device (timeout 00:05:00) [common]
271 10:23:17.582644 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 10:23:17.597549 Setting prompt string to ['lava-test: # ']
273 10:23:17.599037 end: 2.3 connect-device (duration 00:00:00) [common]
274 10:23:17.599613 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 10:23:17.600194 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 10:23:17.600710 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 10:23:17.601850 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 10:23:17.635727 >> OK - accepted request
279 10:23:17.637961 Returned 0 in 0 seconds
280 10:23:17.739042 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 10:23:17.740632 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 10:23:17.741189 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 10:23:17.741689 Setting prompt string to ['Hit any key to stop autoboot']
285 10:23:17.742135 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 10:23:17.743717 Trying 192.168.56.21...
287 10:23:17.744211 Connected to conserv1.
288 10:23:17.744611 Escape character is '^]'.
289 10:23:17.745023
290 10:23:17.745435 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 10:23:17.745863
292 10:23:28.577643 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 10:23:28.578298 bl2_stage_init 0x01
294 10:23:28.578777 bl2_stage_init 0x81
295 10:23:28.583239 hw id: 0x0000 - pwm id 0x01
296 10:23:28.583841 bl2_stage_init 0xc1
297 10:23:28.584388 bl2_stage_init 0x02
298 10:23:28.584879
299 10:23:28.588872 L0:00000000
300 10:23:28.589381 L1:20000703
301 10:23:28.589822 L2:00008067
302 10:23:28.590251 L3:14000000
303 10:23:28.594444 B2:00402000
304 10:23:28.594919 B1:e0f83180
305 10:23:28.595351
306 10:23:28.595785 TE: 58167
307 10:23:28.596254
308 10:23:28.599890 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 10:23:28.600383
310 10:23:28.600817 Board ID = 1
311 10:23:28.605387 Set A53 clk to 24M
312 10:23:28.605862 Set A73 clk to 24M
313 10:23:28.606288 Set clk81 to 24M
314 10:23:28.611010 A53 clk: 1200 MHz
315 10:23:28.611474 A73 clk: 1200 MHz
316 10:23:28.611901 CLK81: 166.6M
317 10:23:28.612362 smccc: 00012abd
318 10:23:28.616534 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 10:23:28.622083 board id: 1
320 10:23:28.628136 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 10:23:28.638635 fw parse done
322 10:23:28.644552 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 10:23:28.687302 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 10:23:28.698210 PIEI prepare done
325 10:23:28.698726 fastboot data load
326 10:23:28.699160 fastboot data verify
327 10:23:28.703789 verify result: 266
328 10:23:28.709429 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 10:23:28.709931 LPDDR4 probe
330 10:23:28.710359 ddr clk to 1584MHz
331 10:23:28.717349 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 10:23:28.753754
333 10:23:28.754088 dmc_version 0001
334 10:23:28.761413 Check phy result
335 10:23:28.767278 INFO : End of CA training
336 10:23:28.767614 INFO : End of initialization
337 10:23:28.773031 INFO : Training has run successfully!
338 10:23:28.773603 Check phy result
339 10:23:28.778433 INFO : End of initialization
340 10:23:28.778940 INFO : End of read enable training
341 10:23:28.784501 INFO : End of fine write leveling
342 10:23:28.789657 INFO : End of Write leveling coarse delay
343 10:23:28.790149 INFO : Training has run successfully!
344 10:23:28.790570 Check phy result
345 10:23:28.795193 INFO : End of initialization
346 10:23:28.795671 INFO : End of read dq deskew training
347 10:23:28.800803 INFO : End of MPR read delay center optimization
348 10:23:28.806326 INFO : End of write delay center optimization
349 10:23:28.812030 INFO : End of read delay center optimization
350 10:23:28.812513 INFO : End of max read latency training
351 10:23:28.817549 INFO : Training has run successfully!
352 10:23:28.818038 1D training succeed
353 10:23:28.825981 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 10:23:28.874583 Check phy result
355 10:23:28.875114 INFO : End of initialization
356 10:23:28.897090 INFO : End of 2D read delay Voltage center optimization
357 10:23:28.916625 INFO : End of 2D read delay Voltage center optimization
358 10:23:28.968639 INFO : End of 2D write delay Voltage center optimization
359 10:23:29.018246 INFO : End of 2D write delay Voltage center optimization
360 10:23:29.023457 INFO : Training has run successfully!
361 10:23:29.023927
362 10:23:29.024554 channel==0
363 10:23:29.029213 RxClkDly_Margin_A0==88 ps 9
364 10:23:29.029865 TxDqDly_Margin_A0==98 ps 10
365 10:23:29.034629 RxClkDly_Margin_A1==78 ps 8
366 10:23:29.035265 TxDqDly_Margin_A1==88 ps 9
367 10:23:29.035801 TrainedVREFDQ_A0==74
368 10:23:29.040258 TrainedVREFDQ_A1==74
369 10:23:29.040772 VrefDac_Margin_A0==25
370 10:23:29.041168 DeviceVref_Margin_A0==40
371 10:23:29.045827 VrefDac_Margin_A1==26
372 10:23:29.046260 DeviceVref_Margin_A1==40
373 10:23:29.046658
374 10:23:29.047048
375 10:23:29.047460 channel==1
376 10:23:29.051619 RxClkDly_Margin_A0==88 ps 9
377 10:23:29.052246 TxDqDly_Margin_A0==88 ps 9
378 10:23:29.057429 RxClkDly_Margin_A1==88 ps 9
379 10:23:29.057971 TxDqDly_Margin_A1==88 ps 9
380 10:23:29.062969 TrainedVREFDQ_A0==76
381 10:23:29.063669 TrainedVREFDQ_A1==77
382 10:23:29.064183 VrefDac_Margin_A0==24
383 10:23:29.069182 DeviceVref_Margin_A0==38
384 10:23:29.069720 VrefDac_Margin_A1==24
385 10:23:29.070180 DeviceVref_Margin_A1==37
386 10:23:29.074229
387 10:23:29.074696 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 10:23:29.075095
389 10:23:29.107913 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000016 00000018 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 10:23:29.108684 2D training succeed
391 10:23:29.113418 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 10:23:29.118652 auto size-- 65535DDR cs0 size: 2048MB
393 10:23:29.119291 DDR cs1 size: 2048MB
394 10:23:29.124358 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 10:23:29.124970 cs0 DataBus test pass
396 10:23:29.129947 cs1 DataBus test pass
397 10:23:29.130489 cs0 AddrBus test pass
398 10:23:29.130938 cs1 AddrBus test pass
399 10:23:29.131377
400 10:23:29.135364 100bdlr_step_size ps== 420
401 10:23:29.135858 result report
402 10:23:29.141092 boot times 0Enable ddr reg access
403 10:23:29.145182 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 10:23:29.158752 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 10:23:29.732600 0.0;M3 CHK:0;cm4_sp_mode 0
406 10:23:29.733215 MVN_1=0x00000000
407 10:23:29.738222 MVN_2=0x00000000
408 10:23:29.743976 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 10:23:29.744557 OPS=0x10
410 10:23:29.744985 ring efuse init
411 10:23:29.745392 chipver efuse init
412 10:23:29.749521 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 10:23:29.755151 [0.018961 Inits done]
414 10:23:29.755720 secure task start!
415 10:23:29.756224 high task start!
416 10:23:29.759255 low task start!
417 10:23:29.759745 run into bl31
418 10:23:29.766239 NOTICE: BL31: v1.3(release):4fc40b1
419 10:23:29.773111 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 10:23:29.773620 NOTICE: BL31: G12A normal boot!
421 10:23:29.799489 NOTICE: BL31: BL33 decompress pass
422 10:23:29.804319 ERROR: Error initializing runtime service opteed_fast
423 10:23:31.037871
424 10:23:31.038280
425 10:23:31.045428 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 10:23:31.045788
427 10:23:31.046010 Model: Libre Computer AML-A311D-CC Alta
428 10:23:31.253890 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 10:23:31.278209 DRAM: 2 GiB (effective 3.8 GiB)
430 10:23:31.421189 Core: 408 devices, 31 uclasses, devicetree: separate
431 10:23:31.426555 WDT: Not starting watchdog@f0d0
432 10:23:31.459357 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 10:23:31.471693 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 10:23:31.476181 ** Bad device specification mmc 0 **
435 10:23:31.487010 Card did not respond to voltage select! : -110
436 10:23:31.494032 ** Bad device specification mmc 0 **
437 10:23:31.494603 Couldn't find partition mmc 0
438 10:23:31.502966 Card did not respond to voltage select! : -110
439 10:23:31.508505 ** Bad device specification mmc 0 **
440 10:23:31.509040 Couldn't find partition mmc 0
441 10:23:31.513281 Error: could not access storage.
442 10:23:32.777597 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 10:23:32.778034 bl2_stage_init 0x01
444 10:23:32.778259 bl2_stage_init 0x81
445 10:23:32.783150 hw id: 0x0000 - pwm id 0x01
446 10:23:32.783450 bl2_stage_init 0xc1
447 10:23:32.783666 bl2_stage_init 0x02
448 10:23:32.783874
449 10:23:32.788755 L0:00000000
450 10:23:32.789062 L1:20000703
451 10:23:32.789277 L2:00008067
452 10:23:32.789479 L3:14000000
453 10:23:32.794478 B2:00402000
454 10:23:32.794793 B1:e0f83180
455 10:23:32.795007
456 10:23:32.795216 TE: 58167
457 10:23:32.795423
458 10:23:32.800024 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 10:23:32.800336
460 10:23:32.800551 Board ID = 1
461 10:23:32.805591 Set A53 clk to 24M
462 10:23:32.805896 Set A73 clk to 24M
463 10:23:32.806112 Set clk81 to 24M
464 10:23:32.811156 A53 clk: 1200 MHz
465 10:23:32.811457 A73 clk: 1200 MHz
466 10:23:32.811672 CLK81: 166.6M
467 10:23:32.811877 smccc: 00012abd
468 10:23:32.816777 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 10:23:32.822496 board id: 1
470 10:23:32.827327 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 10:23:32.838932 fw parse done
472 10:23:32.843887 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 10:23:32.886987 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 10:23:32.898488 PIEI prepare done
475 10:23:32.898997 fastboot data load
476 10:23:32.899449 fastboot data verify
477 10:23:32.904128 verify result: 266
478 10:23:32.909695 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 10:23:32.910231 LPDDR4 probe
480 10:23:32.910670 ddr clk to 1584MHz
481 10:23:32.917109 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 10:23:32.954376
483 10:23:32.954964 dmc_version 0001
484 10:23:32.960890 Check phy result
485 10:23:32.967560 INFO : End of CA training
486 10:23:32.968120 INFO : End of initialization
487 10:23:32.973090 INFO : Training has run successfully!
488 10:23:32.973625 Check phy result
489 10:23:32.978623 INFO : End of initialization
490 10:23:32.979095 INFO : End of read enable training
491 10:23:32.984257 INFO : End of fine write leveling
492 10:23:32.989888 INFO : End of Write leveling coarse delay
493 10:23:32.990412 INFO : Training has run successfully!
494 10:23:32.990872 Check phy result
495 10:23:32.995555 INFO : End of initialization
496 10:23:32.996113 INFO : End of read dq deskew training
497 10:23:33.001161 INFO : End of MPR read delay center optimization
498 10:23:33.006760 INFO : End of write delay center optimization
499 10:23:33.012298 INFO : End of read delay center optimization
500 10:23:33.012824 INFO : End of max read latency training
501 10:23:33.017861 INFO : Training has run successfully!
502 10:23:33.018392 1D training succeed
503 10:23:33.026333 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 10:23:33.074724 Check phy result
505 10:23:33.075288 INFO : End of initialization
506 10:23:33.095959 INFO : End of 2D read delay Voltage center optimization
507 10:23:33.116521 INFO : End of 2D read delay Voltage center optimization
508 10:23:33.168485 INFO : End of 2D write delay Voltage center optimization
509 10:23:33.218082 INFO : End of 2D write delay Voltage center optimization
510 10:23:33.223593 INFO : Training has run successfully!
511 10:23:33.224169
512 10:23:33.224624 channel==0
513 10:23:33.229218 RxClkDly_Margin_A0==88 ps 9
514 10:23:33.229710 TxDqDly_Margin_A0==98 ps 10
515 10:23:33.232551 RxClkDly_Margin_A1==88 ps 9
516 10:23:33.233014 TxDqDly_Margin_A1==98 ps 10
517 10:23:33.238243 TrainedVREFDQ_A0==74
518 10:23:33.238757 TrainedVREFDQ_A1==74
519 10:23:33.239213 VrefDac_Margin_A0==25
520 10:23:33.243831 DeviceVref_Margin_A0==40
521 10:23:33.244413 VrefDac_Margin_A1==25
522 10:23:33.249414 DeviceVref_Margin_A1==40
523 10:23:33.249803
524 10:23:33.250043
525 10:23:33.250269 channel==1
526 10:23:33.250555 RxClkDly_Margin_A0==98 ps 10
527 10:23:33.255014 TxDqDly_Margin_A0==88 ps 9
528 10:23:33.255331 RxClkDly_Margin_A1==98 ps 10
529 10:23:33.260551 TxDqDly_Margin_A1==88 ps 9
530 10:23:33.260868 TrainedVREFDQ_A0==77
531 10:23:33.261097 TrainedVREFDQ_A1==77
532 10:23:33.266160 VrefDac_Margin_A0==22
533 10:23:33.266460 DeviceVref_Margin_A0==37
534 10:23:33.271808 VrefDac_Margin_A1==24
535 10:23:33.272278 DeviceVref_Margin_A1==37
536 10:23:33.272603
537 10:23:33.277398 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 10:23:33.277763
539 10:23:33.305391 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
540 10:23:33.310988 2D training succeed
541 10:23:33.316602 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 10:23:33.317223 auto size-- 65535DDR cs0 size: 2048MB
543 10:23:33.322164 DDR cs1 size: 2048MB
544 10:23:33.322548 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 10:23:33.327949 cs0 DataBus test pass
546 10:23:33.328323 cs1 DataBus test pass
547 10:23:33.328542 cs0 AddrBus test pass
548 10:23:33.333383 cs1 AddrBus test pass
549 10:23:33.333890
550 10:23:33.334337 100bdlr_step_size ps== 420
551 10:23:33.334780 result report
552 10:23:33.338950 boot times 0Enable ddr reg access
553 10:23:33.345783 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 10:23:33.359536 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 10:23:33.933772 0.0;M3 CHK:0;cm4_sp_mode 0
556 10:23:33.934423 MVN_1=0x00000000
557 10:23:33.939259 MVN_2=0x00000000
558 10:23:33.944936 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 10:23:33.945430 OPS=0x10
560 10:23:33.945872 ring efuse init
561 10:23:33.946303 chipver efuse init
562 10:23:33.953174 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 10:23:33.953731 [0.018961 Inits done]
564 10:23:33.960197 secure task start!
565 10:23:33.960676 high task start!
566 10:23:33.961113 low task start!
567 10:23:33.961543 run into bl31
568 10:23:33.967422 NOTICE: BL31: v1.3(release):4fc40b1
569 10:23:33.974654 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 10:23:33.975132 NOTICE: BL31: G12A normal boot!
571 10:23:34.000706 NOTICE: BL31: BL33 decompress pass
572 10:23:34.005975 ERROR: Error initializing runtime service opteed_fast
573 10:23:35.239228
574 10:23:35.239634
575 10:23:35.247768 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 10:23:35.248348
577 10:23:35.248825 Model: Libre Computer AML-A311D-CC Alta
578 10:23:35.456339 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 10:23:35.479615 DRAM: 2 GiB (effective 3.8 GiB)
580 10:23:35.622503 Core: 408 devices, 31 uclasses, devicetree: separate
581 10:23:35.628288 WDT: Not starting watchdog@f0d0
582 10:23:35.660645 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 10:23:35.673290 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 10:23:35.677463 ** Bad device specification mmc 0 **
585 10:23:35.688449 Card did not respond to voltage select! : -110
586 10:23:35.696288 ** Bad device specification mmc 0 **
587 10:23:35.696825 Couldn't find partition mmc 0
588 10:23:35.704297 Card did not respond to voltage select! : -110
589 10:23:35.709830 ** Bad device specification mmc 0 **
590 10:23:35.710350 Couldn't find partition mmc 0
591 10:23:35.714906 Error: could not access storage.
592 10:23:36.058623 Net: eth0: ethernet@ff3f0000
593 10:23:36.059041 starting USB...
594 10:23:36.310257 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 10:23:36.310689 Starting the controller
596 10:23:36.317284 USB XHCI 1.10
597 10:23:38.027964 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
598 10:23:38.028437 bl2_stage_init 0x81
599 10:23:38.033531 hw id: 0x0000 - pwm id 0x01
600 10:23:38.033986 bl2_stage_init 0xc1
601 10:23:38.034338 bl2_stage_init 0x02
602 10:23:38.034683
603 10:23:38.039084 L0:00000000
604 10:23:38.039399 L1:20000703
605 10:23:38.039622 L2:00008067
606 10:23:38.039830 L3:14000000
607 10:23:38.040072 B2:00402000
608 10:23:38.041867 B1:e0f83180
609 10:23:38.042143
610 10:23:38.042360 TE: 58150
611 10:23:38.042570
612 10:23:38.052894 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 10:23:38.053387
614 10:23:38.053744 Board ID = 1
615 10:23:38.054084 Set A53 clk to 24M
616 10:23:38.054430 Set A73 clk to 24M
617 10:23:38.058597 Set clk81 to 24M
618 10:23:38.059066 A53 clk: 1200 MHz
619 10:23:38.059320 A73 clk: 1200 MHz
620 10:23:38.062100 CLK81: 166.6M
621 10:23:38.062382 smccc: 00012aac
622 10:23:38.067652 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 10:23:38.073240 board id: 1
624 10:23:38.077653 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 10:23:38.089302 fw parse done
626 10:23:38.094041 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 10:23:38.137630 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 10:23:38.148520 PIEI prepare done
629 10:23:38.148840 fastboot data load
630 10:23:38.149063 fastboot data verify
631 10:23:38.154201 verify result: 266
632 10:23:38.159699 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 10:23:38.160029 LPDDR4 probe
634 10:23:38.160259 ddr clk to 1584MHz
635 10:23:38.167152 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 10:23:38.204957
637 10:23:38.205299 dmc_version 0001
638 10:23:38.211482 Check phy result
639 10:23:38.217455 INFO : End of CA training
640 10:23:38.217727 INFO : End of initialization
641 10:23:38.223227 INFO : Training has run successfully!
642 10:23:38.223634 Check phy result
643 10:23:38.228768 INFO : End of initialization
644 10:23:38.229047 INFO : End of read enable training
645 10:23:38.231970 INFO : End of fine write leveling
646 10:23:38.237492 INFO : End of Write leveling coarse delay
647 10:23:38.243212 INFO : Training has run successfully!
648 10:23:38.243487 Check phy result
649 10:23:38.243702 INFO : End of initialization
650 10:23:38.248730 INFO : End of read dq deskew training
651 10:23:38.254318 INFO : End of MPR read delay center optimization
652 10:23:38.254602 INFO : End of write delay center optimization
653 10:23:38.259918 INFO : End of read delay center optimization
654 10:23:38.265520 INFO : End of max read latency training
655 10:23:38.265804 INFO : Training has run successfully!
656 10:23:38.271199 1D training succeed
657 10:23:38.276133 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 10:23:38.323794 Check phy result
659 10:23:38.324171 INFO : End of initialization
660 10:23:38.345404 INFO : End of 2D read delay Voltage center optimization
661 10:23:38.365588 INFO : End of 2D read delay Voltage center optimization
662 10:23:38.417528 INFO : End of 2D write delay Voltage center optimization
663 10:23:38.466731 INFO : End of 2D write delay Voltage center optimization
664 10:23:38.472248 INFO : Training has run successfully!
665 10:23:38.472535
666 10:23:38.472753 channel==0
667 10:23:38.477850 RxClkDly_Margin_A0==88 ps 9
668 10:23:38.478139 TxDqDly_Margin_A0==98 ps 10
669 10:23:38.483446 RxClkDly_Margin_A1==88 ps 9
670 10:23:38.483728 TxDqDly_Margin_A1==88 ps 9
671 10:23:38.483956 TrainedVREFDQ_A0==74
672 10:23:38.489049 TrainedVREFDQ_A1==74
673 10:23:38.489328 VrefDac_Margin_A0==25
674 10:23:38.489544 DeviceVref_Margin_A0==40
675 10:23:38.494630 VrefDac_Margin_A1==25
676 10:23:38.494910 DeviceVref_Margin_A1==40
677 10:23:38.495124
678 10:23:38.495329
679 10:23:38.495546 channel==1
680 10:23:38.500232 RxClkDly_Margin_A0==88 ps 9
681 10:23:38.500511 TxDqDly_Margin_A0==98 ps 10
682 10:23:38.505854 RxClkDly_Margin_A1==88 ps 9
683 10:23:38.506134 TxDqDly_Margin_A1==88 ps 9
684 10:23:38.511476 TrainedVREFDQ_A0==77
685 10:23:38.511753 TrainedVREFDQ_A1==77
686 10:23:38.511968 VrefDac_Margin_A0==23
687 10:23:38.517046 DeviceVref_Margin_A0==37
688 10:23:38.517317 VrefDac_Margin_A1==24
689 10:23:38.522660 DeviceVref_Margin_A1==37
690 10:23:38.522926
691 10:23:38.523142 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 10:23:38.523358
693 10:23:38.556241 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000019 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
694 10:23:38.556606 2D training succeed
695 10:23:38.561844 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 10:23:38.567435 auto size-- 65535DDR cs0 size: 2048MB
697 10:23:38.567718 DDR cs1 size: 2048MB
698 10:23:38.573031 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 10:23:38.573303 cs0 DataBus test pass
700 10:23:38.578640 cs1 DataBus test pass
701 10:23:38.579047 cs0 AddrBus test pass
702 10:23:38.579403 cs1 AddrBus test pass
703 10:23:38.579641
704 10:23:38.584232 100bdlr_step_size ps== 420
705 10:23:38.584634 result report
706 10:23:38.589857 boot times 0Enable ddr reg access
707 10:23:38.594815 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 10:23:38.608489 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 10:23:39.180616 0.0;M3 CHK:0;cm4_sp_mode 0
710 10:23:39.181016 MVN_1=0x00000000
711 10:23:39.186028 MVN_2=0x00000000
712 10:23:39.191808 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 10:23:39.192133 OPS=0x10
714 10:23:39.192351 ring efuse init
715 10:23:39.192557 chipver efuse init
716 10:23:39.197403 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 10:23:39.202995 [0.018961 Inits done]
718 10:23:39.203255 secure task start!
719 10:23:39.203464 high task start!
720 10:23:39.207566 low task start!
721 10:23:39.207824 run into bl31
722 10:23:39.214207 NOTICE: BL31: v1.3(release):4fc40b1
723 10:23:39.221214 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 10:23:39.221499 NOTICE: BL31: G12A normal boot!
725 10:23:39.247834 NOTICE: BL31: BL33 decompress pass
726 10:23:39.253194 ERROR: Error initializing runtime service opteed_fast
727 10:23:40.734905
728 10:23:40.735309
729 10:23:40.735564 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 10:23:40.735935
731 10:23:40.736185 Model: Libre Computer AML-A311D-CC Alta
732 10:23:40.736397 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 10:23:40.737043 DRAM: 2 GiB (effective 3.8 GiB)
734 10:23:40.869650 Core: 408 devices, 31 uclasses, devicetree: separate
735 10:23:40.875557 WDT: Not starting watchdog@f0d0
736 10:23:40.907751 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 10:23:40.920288 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 10:23:40.925136 ** Bad device specification mmc 0 **
739 10:23:40.935472 Card did not respond to voltage select! : -110
740 10:23:40.943141 ** Bad device specification mmc 0 **
741 10:23:40.943650 Couldn't find partition mmc 0
742 10:23:40.951504 Card did not respond to voltage select! : -110
743 10:23:40.957003 ** Bad device specification mmc 0 **
744 10:23:40.957508 Couldn't find partition mmc 0
745 10:23:40.962062 Error: could not access storage.
746 10:23:41.304721 Net: eth0: ethernet@ff3f0000
747 10:23:41.305361 starting USB...
748 10:23:41.556534 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 10:23:41.557198 Starting the controller
750 10:23:41.563331 USB XHCI 1.10
751 10:23:43.729680 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 10:23:43.730368 bl2_stage_init 0x01
753 10:23:43.730816 bl2_stage_init 0x81
754 10:23:43.735276 hw id: 0x0000 - pwm id 0x01
755 10:23:43.735860 bl2_stage_init 0xc1
756 10:23:43.736363 bl2_stage_init 0x02
757 10:23:43.736788
758 10:23:43.740957 L0:00000000
759 10:23:43.741515 L1:20000703
760 10:23:43.741937 L2:00008067
761 10:23:43.742340 L3:14000000
762 10:23:43.746532 B2:00402000
763 10:23:43.747118 B1:e0f83180
764 10:23:43.747561
765 10:23:43.748011 TE: 58124
766 10:23:43.748445
767 10:23:43.752229 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 10:23:43.752812
769 10:23:43.753245 Board ID = 1
770 10:23:43.757701 Set A53 clk to 24M
771 10:23:43.758258 Set A73 clk to 24M
772 10:23:43.758675 Set clk81 to 24M
773 10:23:43.763225 A53 clk: 1200 MHz
774 10:23:43.763785 A73 clk: 1200 MHz
775 10:23:43.764249 CLK81: 166.6M
776 10:23:43.764664 smccc: 00012a91
777 10:23:43.768909 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 10:23:43.774490 board id: 1
779 10:23:43.780510 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 10:23:43.790921 fw parse done
781 10:23:43.796882 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 10:23:43.839434 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 10:23:43.850434 PIEI prepare done
784 10:23:43.851007 fastboot data load
785 10:23:43.851436 fastboot data verify
786 10:23:43.856234 verify result: 266
787 10:23:43.861658 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 10:23:43.862226 LPDDR4 probe
789 10:23:43.862646 ddr clk to 1584MHz
790 10:23:43.868706 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 10:23:43.906887
792 10:23:43.907452 dmc_version 0001
793 10:23:43.913579 Check phy result
794 10:23:43.919534 INFO : End of CA training
795 10:23:43.920111 INFO : End of initialization
796 10:23:43.924998 INFO : Training has run successfully!
797 10:23:43.925519 Check phy result
798 10:23:43.930696 INFO : End of initialization
799 10:23:43.931236 INFO : End of read enable training
800 10:23:43.936233 INFO : End of fine write leveling
801 10:23:43.941866 INFO : End of Write leveling coarse delay
802 10:23:43.942401 INFO : Training has run successfully!
803 10:23:43.942818 Check phy result
804 10:23:43.947473 INFO : End of initialization
805 10:23:43.948043 INFO : End of read dq deskew training
806 10:23:43.953006 INFO : End of MPR read delay center optimization
807 10:23:43.958656 INFO : End of write delay center optimization
808 10:23:43.965527 INFO : End of read delay center optimization
809 10:23:43.966063 INFO : End of max read latency training
810 10:23:43.969856 INFO : Training has run successfully!
811 10:23:43.970373 1D training succeed
812 10:23:43.978924 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 10:23:44.026616 Check phy result
814 10:23:44.027171 INFO : End of initialization
815 10:23:44.048401 INFO : End of 2D read delay Voltage center optimization
816 10:23:44.068328 INFO : End of 2D read delay Voltage center optimization
817 10:23:44.120399 INFO : End of 2D write delay Voltage center optimization
818 10:23:44.169487 INFO : End of 2D write delay Voltage center optimization
819 10:23:44.175023 INFO : Training has run successfully!
820 10:23:44.175548
821 10:23:44.175973 channel==0
822 10:23:44.180705 RxClkDly_Margin_A0==88 ps 9
823 10:23:44.181224 TxDqDly_Margin_A0==98 ps 10
824 10:23:44.186357 RxClkDly_Margin_A1==88 ps 9
825 10:23:44.186935 TxDqDly_Margin_A1==98 ps 10
826 10:23:44.187359 TrainedVREFDQ_A0==74
827 10:23:44.191936 TrainedVREFDQ_A1==74
828 10:23:44.192532 VrefDac_Margin_A0==25
829 10:23:44.192926 DeviceVref_Margin_A0==40
830 10:23:44.197505 VrefDac_Margin_A1==25
831 10:23:44.198011 DeviceVref_Margin_A1==40
832 10:23:44.198402
833 10:23:44.198789
834 10:23:44.203047 channel==1
835 10:23:44.203546 RxClkDly_Margin_A0==98 ps 10
836 10:23:44.203936 TxDqDly_Margin_A0==98 ps 10
837 10:23:44.208706 RxClkDly_Margin_A1==98 ps 10
838 10:23:44.209202 TxDqDly_Margin_A1==88 ps 9
839 10:23:44.214261 TrainedVREFDQ_A0==77
840 10:23:44.214791 TrainedVREFDQ_A1==77
841 10:23:44.215187 VrefDac_Margin_A0==22
842 10:23:44.219868 DeviceVref_Margin_A0==37
843 10:23:44.220404 VrefDac_Margin_A1==22
844 10:23:44.225401 DeviceVref_Margin_A1==37
845 10:23:44.225911
846 10:23:44.226306 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 10:23:44.230980
848 10:23:44.258921 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
849 10:23:44.259512 2D training succeed
850 10:23:44.264595 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 10:23:44.270155 auto size-- 65535DDR cs0 size: 2048MB
852 10:23:44.270664 DDR cs1 size: 2048MB
853 10:23:44.275805 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 10:23:44.276351 cs0 DataBus test pass
855 10:23:44.281386 cs1 DataBus test pass
856 10:23:44.281888 cs0 AddrBus test pass
857 10:23:44.282275 cs1 AddrBus test pass
858 10:23:44.282660
859 10:23:44.286983 100bdlr_step_size ps== 420
860 10:23:44.287488 result report
861 10:23:44.292584 boot times 0Enable ddr reg access
862 10:23:44.298000 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 10:23:44.311439 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 10:23:44.883417 0.0;M3 CHK:0;cm4_sp_mode 0
865 10:23:44.884137 MVN_1=0x00000000
866 10:23:44.889006 MVN_2=0x00000000
867 10:23:44.894719 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 10:23:44.895253 OPS=0x10
869 10:23:44.895675 ring efuse init
870 10:23:44.896119 chipver efuse init
871 10:23:44.900350 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 10:23:44.905963 [0.018961 Inits done]
873 10:23:44.906489 secure task start!
874 10:23:44.906902 high task start!
875 10:23:44.910527 low task start!
876 10:23:44.911066 run into bl31
877 10:23:44.917230 NOTICE: BL31: v1.3(release):4fc40b1
878 10:23:44.925138 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 10:23:44.925694 NOTICE: BL31: G12A normal boot!
880 10:23:44.950344 NOTICE: BL31: BL33 decompress pass
881 10:23:44.956085 ERROR: Error initializing runtime service opteed_fast
882 10:23:46.188836
883 10:23:46.189468
884 10:23:46.197284 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 10:23:46.197795
886 10:23:46.198214 Model: Libre Computer AML-A311D-CC Alta
887 10:23:46.405703 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 10:23:46.429087 DRAM: 2 GiB (effective 3.8 GiB)
889 10:23:46.572124 Core: 408 devices, 31 uclasses, devicetree: separate
890 10:23:46.577900 WDT: Not starting watchdog@f0d0
891 10:23:46.610221 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 10:23:46.622609 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 10:23:46.627661 ** Bad device specification mmc 0 **
894 10:23:46.637988 Card did not respond to voltage select! : -110
895 10:23:46.645607 ** Bad device specification mmc 0 **
896 10:23:46.646096 Couldn't find partition mmc 0
897 10:23:46.653948 Card did not respond to voltage select! : -110
898 10:23:46.659458 ** Bad device specification mmc 0 **
899 10:23:46.659932 Couldn't find partition mmc 0
900 10:23:46.664554 Error: could not access storage.
901 10:23:47.008088 Net: eth0: ethernet@ff3f0000
902 10:23:47.008705 starting USB...
903 10:23:47.260254 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 10:23:47.260689 Starting the controller
905 10:23:47.266820 USB XHCI 1.10
906 10:23:48.820944 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 10:23:48.829276 scanning usb for storage devices... 0 Storage Device(s) found
909 10:23:48.880973 Hit any key to stop autoboot: 1
910 10:23:48.881867 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
911 10:23:48.882617 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
912 10:23:48.883167 Setting prompt string to ['=>']
913 10:23:48.883705 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
914 10:23:48.896728 0
915 10:23:48.897751 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 10:23:48.898270 Sending with 10 millisecond of delay
918 10:23:50.034636 => setenv autoload no
919 10:23:50.045869 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:28)
920 10:23:50.050829 setenv autoload no
921 10:23:50.051592 Sending with 10 millisecond of delay
923 10:23:51.850549 => setenv initrd_high 0xffffffff
924 10:23:51.861583 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
925 10:23:51.862806 setenv initrd_high 0xffffffff
926 10:23:51.863669 Sending with 10 millisecond of delay
928 10:23:53.481492 => setenv fdt_high 0xffffffff
929 10:23:53.492550 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
930 10:23:53.493711 setenv fdt_high 0xffffffff
931 10:23:53.494590 Sending with 10 millisecond of delay
933 10:23:53.786944 => dhcp
934 10:23:53.797729 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
935 10:23:53.798615 dhcp
936 10:23:53.799077 Speed: 1000, full duplex
937 10:23:53.799491 BOOTP broadcast 1
938 10:23:54.045457 BOOTP broadcast 2
939 10:23:54.139303 DHCP client bound to address 192.168.6.33 (341 ms)
940 10:23:54.140423 Sending with 10 millisecond of delay
942 10:23:55.818039 => setenv serverip 192.168.6.2
943 10:23:55.828742 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
944 10:23:55.829426 setenv serverip 192.168.6.2
945 10:23:55.829919 Sending with 10 millisecond of delay
947 10:23:59.553744 => tftpboot 0x01080000 715592/tftp-deploy-2v9jzbfo/kernel/uImage
948 10:23:59.564736 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
949 10:23:59.565651 tftpboot 0x01080000 715592/tftp-deploy-2v9jzbfo/kernel/uImage
950 10:23:59.566120 Speed: 1000, full duplex
951 10:23:59.566547 Using ethernet@ff3f0000 device
952 10:23:59.567580 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
953 10:23:59.573119 Filename '715592/tftp-deploy-2v9jzbfo/kernel/uImage'.
954 10:23:59.577140 Load address: 0x1080000
955 10:24:01.564751 Loading: *######################################## UDP wrong checksum 000000ff 0000ef50
956 10:24:01.575372 UDP wrong checksum 000000ff 00007343
957 10:24:02.043952 ########## 37.6 MiB
958 10:24:02.044787 15.2 MiB/s
959 10:24:02.045341 done
960 10:24:02.047259 Bytes transferred = 39455296 (25a0a40 hex)
961 10:24:02.048192 Sending with 10 millisecond of delay
963 10:24:06.736549 => tftpboot 0x08000000 715592/tftp-deploy-2v9jzbfo/ramdisk/ramdisk.cpio.gz.uboot
964 10:24:06.747329 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
965 10:24:06.748243 tftpboot 0x08000000 715592/tftp-deploy-2v9jzbfo/ramdisk/ramdisk.cpio.gz.uboot
966 10:24:06.748669 Speed: 1000, full duplex
967 10:24:06.749067 Using ethernet@ff3f0000 device
968 10:24:06.749771 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
969 10:24:06.761600 Filename '715592/tftp-deploy-2v9jzbfo/ramdisk/ramdisk.cpio.gz.uboot'.
970 10:24:06.761943 Load address: 0x8000000
971 10:24:13.884243 Loading: *##T ############################################### UDP wrong checksum 00000005 0000159d
972 10:24:18.883853 T UDP wrong checksum 00000005 0000159d
973 10:24:28.885839 T T UDP wrong checksum 00000005 0000159d
974 10:24:36.458470 T UDP wrong checksum 000000ff 00007e68
975 10:24:36.470632 UDP wrong checksum 000000ff 0000035b
976 10:24:48.888561 T T UDP wrong checksum 00000005 0000159d
977 10:24:54.108073 T T UDP wrong checksum 000000ff 00000444
978 10:24:54.127318 UDP wrong checksum 000000ff 0000a136
979 10:25:01.505605 T UDP wrong checksum 000000ff 0000703d
980 10:25:01.538345 UDP wrong checksum 000000ff 00000130
981 10:25:03.895113
982 10:25:03.895747 Retry count exceeded; starting again
984 10:25:03.897243 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
987 10:25:03.899035 end: 2.4 uboot-commands (duration 00:01:46) [common]
989 10:25:03.900419 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
991 10:25:03.901456 end: 2 uboot-action (duration 00:01:46) [common]
993 10:25:03.902973 Cleaning after the job
994 10:25:03.903533 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/715592/tftp-deploy-2v9jzbfo/ramdisk
995 10:25:03.904812 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/715592/tftp-deploy-2v9jzbfo/kernel
996 10:25:03.917874 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/715592/tftp-deploy-2v9jzbfo/dtb
997 10:25:03.919094 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/715592/tftp-deploy-2v9jzbfo/modules
998 10:25:03.928966 start: 4.1 power-off (timeout 00:00:30) [common]
999 10:25:03.930010 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1000 10:25:03.965499 >> OK - accepted request
1001 10:25:03.968059 Returned 0 in 0 seconds
1002 10:25:04.069214 end: 4.1 power-off (duration 00:00:00) [common]
1004 10:25:04.070931 start: 4.2 read-feedback (timeout 00:10:00) [common]
1005 10:25:04.072111 Listened to connection for namespace 'common' for up to 1s
1006 10:25:05.072279 Finalising connection for namespace 'common'
1007 10:25:05.073032 Disconnecting from shell: Finalise
1008 10:25:05.073575 =>
1009 10:25:05.174662 end: 4.2 read-feedback (duration 00:00:01) [common]
1010 10:25:05.175374 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/715592
1011 10:25:05.457946 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/715592
1012 10:25:05.458562 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.