Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 13:34:25.973073 lava-dispatcher, installed at version: 2024.01
2 13:34:25.973873 start: 0 validate
3 13:34:25.974340 Start time: 2024-09-18 13:34:25.974310+00:00 (UTC)
4 13:34:25.974912 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 13:34:25.975452 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 13:34:26.012255 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 13:34:26.012835 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240918%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 13:34:27.066442 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 13:34:27.067079 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240918%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 13:34:33.142245 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 13:34:33.142751 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240918%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 13:34:34.193725 validate duration: 8.22
14 13:34:34.195627 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:34:34.196579 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:34:34.197349 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:34:34.198818 Not decompressing ramdisk as can be used compressed.
18 13:34:34.199816 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 13:34:34.200486 saving as /var/lib/lava/dispatcher/tmp/739625/tftp-deploy-un6efvdh/ramdisk/rootfs.cpio.gz
20 13:34:34.201120 total size: 8181887 (7 MB)
21 13:34:34.247530 progress 0 % (0 MB)
22 13:34:34.253783 progress 5 % (0 MB)
23 13:34:34.259157 progress 10 % (0 MB)
24 13:34:34.264989 progress 15 % (1 MB)
25 13:34:34.270149 progress 20 % (1 MB)
26 13:34:34.275814 progress 25 % (1 MB)
27 13:34:34.282301 progress 30 % (2 MB)
28 13:34:34.290964 progress 35 % (2 MB)
29 13:34:34.297350 progress 40 % (3 MB)
30 13:34:34.304285 progress 45 % (3 MB)
31 13:34:34.309481 progress 50 % (3 MB)
32 13:34:34.315069 progress 55 % (4 MB)
33 13:34:34.320270 progress 60 % (4 MB)
34 13:34:34.325763 progress 65 % (5 MB)
35 13:34:34.330921 progress 70 % (5 MB)
36 13:34:34.336415 progress 75 % (5 MB)
37 13:34:34.341509 progress 80 % (6 MB)
38 13:34:34.347321 progress 85 % (6 MB)
39 13:34:34.352665 progress 90 % (7 MB)
40 13:34:34.357852 progress 95 % (7 MB)
41 13:34:34.362684 progress 100 % (7 MB)
42 13:34:34.363347 7 MB downloaded in 0.16 s (48.10 MB/s)
43 13:34:34.363907 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:34:34.364844 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:34:34.365139 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:34:34.365410 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:34:34.365867 downloading http://storage.kernelci.org/next/master/next-20240918/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/kernel/Image
49 13:34:34.366150 saving as /var/lib/lava/dispatcher/tmp/739625/tftp-deploy-un6efvdh/kernel/Image
50 13:34:34.366358 total size: 45724160 (43 MB)
51 13:34:34.366570 No compression specified
52 13:34:34.406650 progress 0 % (0 MB)
53 13:34:34.435064 progress 5 % (2 MB)
54 13:34:34.463545 progress 10 % (4 MB)
55 13:34:34.493626 progress 15 % (6 MB)
56 13:34:34.526480 progress 20 % (8 MB)
57 13:34:34.561451 progress 25 % (10 MB)
58 13:34:34.596585 progress 30 % (13 MB)
59 13:34:34.630190 progress 35 % (15 MB)
60 13:34:34.663558 progress 40 % (17 MB)
61 13:34:34.695532 progress 45 % (19 MB)
62 13:34:34.723621 progress 50 % (21 MB)
63 13:34:34.752920 progress 55 % (24 MB)
64 13:34:34.783208 progress 60 % (26 MB)
65 13:34:34.810669 progress 65 % (28 MB)
66 13:34:34.837463 progress 70 % (30 MB)
67 13:34:34.864819 progress 75 % (32 MB)
68 13:34:34.892021 progress 80 % (34 MB)
69 13:34:34.921489 progress 85 % (37 MB)
70 13:34:34.948662 progress 90 % (39 MB)
71 13:34:34.976159 progress 95 % (41 MB)
72 13:34:35.003043 progress 100 % (43 MB)
73 13:34:35.003672 43 MB downloaded in 0.64 s (68.42 MB/s)
74 13:34:35.004184 end: 1.2.1 http-download (duration 00:00:01) [common]
76 13:34:35.005008 end: 1.2 download-retry (duration 00:00:01) [common]
77 13:34:35.005282 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:34:35.005545 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:34:35.006037 downloading http://storage.kernelci.org/next/master/next-20240918/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 13:34:35.006366 saving as /var/lib/lava/dispatcher/tmp/739625/tftp-deploy-un6efvdh/dtb/meson-g12b-a311d-libretech-cc.dtb
81 13:34:35.006602 total size: 54703 (0 MB)
82 13:34:35.006829 No compression specified
83 13:34:35.049334 progress 59 % (0 MB)
84 13:34:35.050196 progress 100 % (0 MB)
85 13:34:35.050750 0 MB downloaded in 0.04 s (1.18 MB/s)
86 13:34:35.051227 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:34:35.052158 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:34:35.052441 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:34:35.052707 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:34:35.053194 downloading http://storage.kernelci.org/next/master/next-20240918/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/modules.tar.xz
92 13:34:35.053447 saving as /var/lib/lava/dispatcher/tmp/739625/tftp-deploy-un6efvdh/modules/modules.tar
93 13:34:35.053651 total size: 11606812 (11 MB)
94 13:34:35.053868 Using unxz to decompress xz
95 13:34:35.100335 progress 0 % (0 MB)
96 13:34:35.168224 progress 5 % (0 MB)
97 13:34:35.254825 progress 10 % (1 MB)
98 13:34:35.342664 progress 15 % (1 MB)
99 13:34:35.425546 progress 20 % (2 MB)
100 13:34:35.507885 progress 25 % (2 MB)
101 13:34:35.588329 progress 30 % (3 MB)
102 13:34:35.662629 progress 35 % (3 MB)
103 13:34:35.741743 progress 40 % (4 MB)
104 13:34:35.825829 progress 45 % (5 MB)
105 13:34:35.906160 progress 50 % (5 MB)
106 13:34:35.987054 progress 55 % (6 MB)
107 13:34:36.070402 progress 60 % (6 MB)
108 13:34:36.155739 progress 65 % (7 MB)
109 13:34:36.231138 progress 70 % (7 MB)
110 13:34:36.318350 progress 75 % (8 MB)
111 13:34:36.414853 progress 80 % (8 MB)
112 13:34:36.515674 progress 85 % (9 MB)
113 13:34:36.586253 progress 90 % (9 MB)
114 13:34:36.665566 progress 95 % (10 MB)
115 13:34:36.742088 progress 100 % (11 MB)
116 13:34:36.754929 11 MB downloaded in 1.70 s (6.51 MB/s)
117 13:34:36.755562 end: 1.4.1 http-download (duration 00:00:02) [common]
119 13:34:36.756840 end: 1.4 download-retry (duration 00:00:02) [common]
120 13:34:36.757369 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 13:34:36.757885 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 13:34:36.758373 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:34:36.758869 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 13:34:36.759861 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5
125 13:34:36.760840 makedir: /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin
126 13:34:36.761498 makedir: /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/tests
127 13:34:36.762105 makedir: /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/results
128 13:34:36.762713 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-add-keys
129 13:34:36.763654 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-add-sources
130 13:34:36.764628 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-background-process-start
131 13:34:36.765570 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-background-process-stop
132 13:34:36.766557 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-common-functions
133 13:34:36.767456 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-echo-ipv4
134 13:34:36.768376 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-install-packages
135 13:34:36.769271 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-installed-packages
136 13:34:36.770143 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-os-build
137 13:34:36.771051 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-probe-channel
138 13:34:36.771941 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-probe-ip
139 13:34:36.772876 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-target-ip
140 13:34:36.773762 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-target-mac
141 13:34:36.774640 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-target-storage
142 13:34:36.775562 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-test-case
143 13:34:36.776496 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-test-event
144 13:34:36.777380 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-test-feedback
145 13:34:36.778306 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-test-raise
146 13:34:36.779211 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-test-reference
147 13:34:36.780179 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-test-runner
148 13:34:36.781086 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-test-set
149 13:34:36.781976 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-test-shell
150 13:34:36.782906 Updating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-install-packages (oe)
151 13:34:36.783886 Updating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/bin/lava-installed-packages (oe)
152 13:34:36.784776 Creating /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/environment
153 13:34:36.785496 LAVA metadata
154 13:34:36.786017 - LAVA_JOB_ID=739625
155 13:34:36.786449 - LAVA_DISPATCHER_IP=192.168.6.2
156 13:34:36.787132 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 13:34:36.789013 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 13:34:36.789643 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 13:34:36.790056 skipped lava-vland-overlay
160 13:34:36.790586 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 13:34:36.791156 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 13:34:36.791623 skipped lava-multinode-overlay
163 13:34:36.792183 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 13:34:36.792704 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 13:34:36.793194 Loading test definitions
166 13:34:36.793748 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 13:34:36.794194 Using /lava-739625 at stage 0
168 13:34:36.796269 uuid=739625_1.5.2.4.1 testdef=None
169 13:34:36.796648 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 13:34:36.796985 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 13:34:36.799068 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 13:34:36.799900 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 13:34:36.802248 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 13:34:36.803084 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 13:34:36.805428 runner path: /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/0/tests/0_dmesg test_uuid 739625_1.5.2.4.1
178 13:34:36.806031 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 13:34:36.806809 Creating lava-test-runner.conf files
181 13:34:36.807014 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/739625/lava-overlay-bsietqu5/lava-739625/0 for stage 0
182 13:34:36.807362 - 0_dmesg
183 13:34:36.807723 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 13:34:36.808025 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 13:34:36.832508 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 13:34:36.832941 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 13:34:36.833206 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 13:34:36.833477 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 13:34:36.833814 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 13:34:37.804205 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 13:34:37.804675 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 13:34:37.804921 extracting modules file /var/lib/lava/dispatcher/tmp/739625/tftp-deploy-un6efvdh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/739625/extract-overlay-ramdisk-301oi000/ramdisk
193 13:34:39.235677 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 13:34:39.236230 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 13:34:39.236563 [common] Applying overlay /var/lib/lava/dispatcher/tmp/739625/compress-overlay-ckg34ce8/overlay-1.5.2.5.tar.gz to ramdisk
196 13:34:39.236811 [common] Applying overlay /var/lib/lava/dispatcher/tmp/739625/compress-overlay-ckg34ce8/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/739625/extract-overlay-ramdisk-301oi000/ramdisk
197 13:34:39.271457 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 13:34:39.271917 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 13:34:39.272227 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 13:34:39.272461 Converting downloaded kernel to a uImage
201 13:34:39.272769 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/739625/tftp-deploy-un6efvdh/kernel/Image /var/lib/lava/dispatcher/tmp/739625/tftp-deploy-un6efvdh/kernel/uImage
202 13:34:39.739046 output: Image Name:
203 13:34:39.739469 output: Created: Wed Sep 18 13:34:39 2024
204 13:34:39.739675 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 13:34:39.739881 output: Data Size: 45724160 Bytes = 44652.50 KiB = 43.61 MiB
206 13:34:39.740122 output: Load Address: 01080000
207 13:34:39.740323 output: Entry Point: 01080000
208 13:34:39.740518 output:
209 13:34:39.740846 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 13:34:39.741109 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 13:34:39.741378 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 13:34:39.741630 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 13:34:39.741884 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 13:34:39.742139 Building ramdisk /var/lib/lava/dispatcher/tmp/739625/extract-overlay-ramdisk-301oi000/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/739625/extract-overlay-ramdisk-301oi000/ramdisk
215 13:34:42.342211 >> 181654 blocks
216 13:34:50.812983 Adding RAMdisk u-boot header.
217 13:34:50.813646 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/739625/extract-overlay-ramdisk-301oi000/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/739625/extract-overlay-ramdisk-301oi000/ramdisk.cpio.gz.uboot
218 13:34:51.136088 output: Image Name:
219 13:34:51.136704 output: Created: Wed Sep 18 13:34:50 2024
220 13:34:51.137112 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 13:34:51.137512 output: Data Size: 26068047 Bytes = 25457.08 KiB = 24.86 MiB
222 13:34:51.137908 output: Load Address: 00000000
223 13:34:51.138298 output: Entry Point: 00000000
224 13:34:51.138681 output:
225 13:34:51.139612 rename /var/lib/lava/dispatcher/tmp/739625/extract-overlay-ramdisk-301oi000/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/739625/tftp-deploy-un6efvdh/ramdisk/ramdisk.cpio.gz.uboot
226 13:34:51.140332 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 13:34:51.140868 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 13:34:51.141384 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 13:34:51.141837 No LXC device requested
230 13:34:51.142326 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 13:34:51.142821 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 13:34:51.143299 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 13:34:51.143712 Checking files for TFTP limit of 4294967296 bytes.
234 13:34:51.146376 end: 1 tftp-deploy (duration 00:00:17) [common]
235 13:34:51.146934 start: 2 uboot-action (timeout 00:05:00) [common]
236 13:34:51.147445 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 13:34:51.147934 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 13:34:51.148465 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 13:34:51.148996 Using kernel file from prepare-kernel: 739625/tftp-deploy-un6efvdh/kernel/uImage
240 13:34:51.149597 substitutions:
241 13:34:51.149996 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 13:34:51.150398 - {DTB_ADDR}: 0x01070000
243 13:34:51.150803 - {DTB}: 739625/tftp-deploy-un6efvdh/dtb/meson-g12b-a311d-libretech-cc.dtb
244 13:34:51.151197 - {INITRD}: 739625/tftp-deploy-un6efvdh/ramdisk/ramdisk.cpio.gz.uboot
245 13:34:51.151589 - {KERNEL_ADDR}: 0x01080000
246 13:34:51.151976 - {KERNEL}: 739625/tftp-deploy-un6efvdh/kernel/uImage
247 13:34:51.152401 - {LAVA_MAC}: None
248 13:34:51.152830 - {PRESEED_CONFIG}: None
249 13:34:51.153218 - {PRESEED_LOCAL}: None
250 13:34:51.153604 - {RAMDISK_ADDR}: 0x08000000
251 13:34:51.153988 - {RAMDISK}: 739625/tftp-deploy-un6efvdh/ramdisk/ramdisk.cpio.gz.uboot
252 13:34:51.154374 - {ROOT_PART}: None
253 13:34:51.154754 - {ROOT}: None
254 13:34:51.155133 - {SERVER_IP}: 192.168.6.2
255 13:34:51.155521 - {TEE_ADDR}: 0x83000000
256 13:34:51.155905 - {TEE}: None
257 13:34:51.156318 Parsed boot commands:
258 13:34:51.156693 - setenv autoload no
259 13:34:51.157076 - setenv initrd_high 0xffffffff
260 13:34:51.157455 - setenv fdt_high 0xffffffff
261 13:34:51.157836 - dhcp
262 13:34:51.158218 - setenv serverip 192.168.6.2
263 13:34:51.158596 - tftpboot 0x01080000 739625/tftp-deploy-un6efvdh/kernel/uImage
264 13:34:51.158981 - tftpboot 0x08000000 739625/tftp-deploy-un6efvdh/ramdisk/ramdisk.cpio.gz.uboot
265 13:34:51.159365 - tftpboot 0x01070000 739625/tftp-deploy-un6efvdh/dtb/meson-g12b-a311d-libretech-cc.dtb
266 13:34:51.159746 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 13:34:51.160160 - bootm 0x01080000 0x08000000 0x01070000
268 13:34:51.160652 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 13:34:51.162117 start: 2.3 connect-device (timeout 00:05:00) [common]
271 13:34:51.162552 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 13:34:51.177051 Setting prompt string to ['lava-test: # ']
273 13:34:51.178562 end: 2.3 connect-device (duration 00:00:00) [common]
274 13:34:51.179149 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 13:34:51.179713 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 13:34:51.180399 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 13:34:51.181579 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 13:34:51.217767 >> OK - accepted request
279 13:34:51.220423 Returned 0 in 0 seconds
280 13:34:51.321430 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 13:34:51.323105 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 13:34:51.323656 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 13:34:51.324225 Setting prompt string to ['Hit any key to stop autoboot']
285 13:34:51.324678 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 13:34:51.326270 Trying 192.168.56.21...
287 13:34:51.326752 Connected to conserv1.
288 13:34:51.327155 Escape character is '^]'.
289 13:34:51.327556
290 13:34:51.327968 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 13:34:51.328440
292 13:35:03.324335 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 13:35:03.324979 bl2_stage_init 0x01
294 13:35:03.325410 bl2_stage_init 0x81
295 13:35:03.329915 hw id: 0x0000 - pwm id 0x01
296 13:35:03.330422 bl2_stage_init 0xc1
297 13:35:03.330837 bl2_stage_init 0x02
298 13:35:03.331272
299 13:35:03.335438 L0:00000000
300 13:35:03.335903 L1:20000703
301 13:35:03.336424 L2:00008067
302 13:35:03.336831 L3:14000000
303 13:35:03.338289 B2:00402000
304 13:35:03.338715 B1:e0f83180
305 13:35:03.339108
306 13:35:03.339493 TE: 58124
307 13:35:03.339875
308 13:35:03.349533 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 13:35:03.349966
310 13:35:03.350353 Board ID = 1
311 13:35:03.350737 Set A53 clk to 24M
312 13:35:03.351118 Set A73 clk to 24M
313 13:35:03.355188 Set clk81 to 24M
314 13:35:03.355618 A53 clk: 1200 MHz
315 13:35:03.356032 A73 clk: 1200 MHz
316 13:35:03.360713 CLK81: 166.6M
317 13:35:03.361141 smccc: 00012a91
318 13:35:03.366278 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 13:35:03.366701 board id: 1
320 13:35:03.374910 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 13:35:03.385550 fw parse done
322 13:35:03.391613 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 13:35:03.434228 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 13:35:03.445228 PIEI prepare done
325 13:35:03.445661 fastboot data load
326 13:35:03.446058 fastboot data verify
327 13:35:03.450733 verify result: 266
328 13:35:03.456306 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 13:35:03.456738 LPDDR4 probe
330 13:35:03.457147 ddr clk to 1584MHz
331 13:35:03.464277 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 13:35:03.501647
333 13:35:03.502101 dmc_version 0001
334 13:35:03.508322 Check phy result
335 13:35:03.514107 INFO : End of CA training
336 13:35:03.514554 INFO : End of initialization
337 13:35:03.519721 INFO : Training has run successfully!
338 13:35:03.520197 Check phy result
339 13:35:03.525286 INFO : End of initialization
340 13:35:03.525712 INFO : End of read enable training
341 13:35:03.530899 INFO : End of fine write leveling
342 13:35:03.536532 INFO : End of Write leveling coarse delay
343 13:35:03.537033 INFO : Training has run successfully!
344 13:35:03.537428 Check phy result
345 13:35:03.542098 INFO : End of initialization
346 13:35:03.542527 INFO : End of read dq deskew training
347 13:35:03.547703 INFO : End of MPR read delay center optimization
348 13:35:03.553276 INFO : End of write delay center optimization
349 13:35:03.558894 INFO : End of read delay center optimization
350 13:35:03.559313 INFO : End of max read latency training
351 13:35:03.564495 INFO : Training has run successfully!
352 13:35:03.564919 1D training succeed
353 13:35:03.573703 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 13:35:03.620473 Check phy result
355 13:35:03.620897 INFO : End of initialization
356 13:35:03.642984 INFO : End of 2D read delay Voltage center optimization
357 13:35:03.663352 INFO : End of 2D read delay Voltage center optimization
358 13:35:03.715218 INFO : End of 2D write delay Voltage center optimization
359 13:35:03.764598 INFO : End of 2D write delay Voltage center optimization
360 13:35:03.770269 INFO : Training has run successfully!
361 13:35:03.770704
362 13:35:03.771101 channel==0
363 13:35:03.775770 RxClkDly_Margin_A0==88 ps 9
364 13:35:03.776241 TxDqDly_Margin_A0==98 ps 10
365 13:35:03.781421 RxClkDly_Margin_A1==88 ps 9
366 13:35:03.781855 TxDqDly_Margin_A1==98 ps 10
367 13:35:03.782256 TrainedVREFDQ_A0==74
368 13:35:03.787011 TrainedVREFDQ_A1==74
369 13:35:03.787437 VrefDac_Margin_A0==25
370 13:35:03.787825 DeviceVref_Margin_A0==40
371 13:35:03.792592 VrefDac_Margin_A1==25
372 13:35:03.793020 DeviceVref_Margin_A1==40
373 13:35:03.793411
374 13:35:03.793800
375 13:35:03.798294 channel==1
376 13:35:03.798737 RxClkDly_Margin_A0==98 ps 10
377 13:35:03.799125 TxDqDly_Margin_A0==98 ps 10
378 13:35:03.803802 RxClkDly_Margin_A1==88 ps 9
379 13:35:03.804263 TxDqDly_Margin_A1==88 ps 9
380 13:35:03.809408 TrainedVREFDQ_A0==77
381 13:35:03.809838 TrainedVREFDQ_A1==77
382 13:35:03.810230 VrefDac_Margin_A0==23
383 13:35:03.815043 DeviceVref_Margin_A0==37
384 13:35:03.815467 VrefDac_Margin_A1==24
385 13:35:03.820579 DeviceVref_Margin_A1==37
386 13:35:03.821000
387 13:35:03.821396 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 13:35:03.821785
389 13:35:03.854243 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
390 13:35:03.854755 2D training succeed
391 13:35:03.859748 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 13:35:03.865357 auto size-- 65535DDR cs0 size: 2048MB
393 13:35:03.865788 DDR cs1 size: 2048MB
394 13:35:03.871032 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 13:35:03.871458 cs0 DataBus test pass
396 13:35:03.876529 cs1 DataBus test pass
397 13:35:03.876954 cs0 AddrBus test pass
398 13:35:03.877342 cs1 AddrBus test pass
399 13:35:03.877727
400 13:35:03.882258 100bdlr_step_size ps== 420
401 13:35:03.882694 result report
402 13:35:03.887781 boot times 0Enable ddr reg access
403 13:35:03.893071 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 13:35:03.906585 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 13:35:04.480378 0.0;M3 CHK:0;cm4_sp_mode 0
406 13:35:04.480935 MVN_1=0x00000000
407 13:35:04.485787 MVN_2=0x00000000
408 13:35:04.491561 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 13:35:04.492045 OPS=0x10
410 13:35:04.492526 ring efuse init
411 13:35:04.492927 chipver efuse init
412 13:35:04.497197 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 13:35:04.502756 [0.018961 Inits done]
414 13:35:04.503187 secure task start!
415 13:35:04.503579 high task start!
416 13:35:04.507379 low task start!
417 13:35:04.507808 run into bl31
418 13:35:04.513986 NOTICE: BL31: v1.3(release):4fc40b1
419 13:35:04.521792 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 13:35:04.522230 NOTICE: BL31: G12A normal boot!
421 13:35:04.547154 NOTICE: BL31: BL33 decompress pass
422 13:35:04.551843 ERROR: Error initializing runtime service opteed_fast
423 13:35:05.785763
424 13:35:05.786217
425 13:35:05.793128 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 13:35:05.793513
427 13:35:05.793741 Model: Libre Computer AML-A311D-CC Alta
428 13:35:06.002703 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 13:35:06.026133 DRAM: 2 GiB (effective 3.8 GiB)
430 13:35:06.169172 Core: 408 devices, 31 uclasses, devicetree: separate
431 13:35:06.175075 WDT: Not starting watchdog@f0d0
432 13:35:06.208131 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 13:35:06.219660 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 13:35:06.223656 ** Bad device specification mmc 0 **
435 13:35:06.234972 Card did not respond to voltage select! : -110
436 13:35:06.241749 ** Bad device specification mmc 0 **
437 13:35:06.242221 Couldn't find partition mmc 0
438 13:35:06.250913 Card did not respond to voltage select! : -110
439 13:35:06.256418 ** Bad device specification mmc 0 **
440 13:35:06.256824 Couldn't find partition mmc 0
441 13:35:06.261575 Error: could not access storage.
442 13:35:07.524896 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 13:35:07.525534 bl2_stage_init 0x01
444 13:35:07.526014 bl2_stage_init 0x81
445 13:35:07.530406 hw id: 0x0000 - pwm id 0x01
446 13:35:07.530925 bl2_stage_init 0xc1
447 13:35:07.531389 bl2_stage_init 0x02
448 13:35:07.531835
449 13:35:07.536046 L0:00000000
450 13:35:07.536571 L1:20000703
451 13:35:07.537030 L2:00008067
452 13:35:07.537470 L3:14000000
453 13:35:07.541652 B2:00402000
454 13:35:07.542163 B1:e0f83180
455 13:35:07.542613
456 13:35:07.543060 TE: 58124
457 13:35:07.543505
458 13:35:07.547205 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 13:35:07.547720
460 13:35:07.548212 Board ID = 1
461 13:35:07.552886 Set A53 clk to 24M
462 13:35:07.553395 Set A73 clk to 24M
463 13:35:07.553847 Set clk81 to 24M
464 13:35:07.558398 A53 clk: 1200 MHz
465 13:35:07.558917 A73 clk: 1200 MHz
466 13:35:07.559369 CLK81: 166.6M
467 13:35:07.559811 smccc: 00012a91
468 13:35:07.564082 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 13:35:07.569639 board id: 1
470 13:35:07.575462 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 13:35:07.586127 fw parse done
472 13:35:07.592105 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 13:35:07.634705 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 13:35:07.645632 PIEI prepare done
475 13:35:07.646145 fastboot data load
476 13:35:07.646596 fastboot data verify
477 13:35:07.651226 verify result: 266
478 13:35:07.656899 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 13:35:07.657406 LPDDR4 probe
480 13:35:07.657864 ddr clk to 1584MHz
481 13:35:07.664847 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 13:35:07.702111
483 13:35:07.702681 dmc_version 0001
484 13:35:07.708765 Check phy result
485 13:35:07.714658 INFO : End of CA training
486 13:35:07.715171 INFO : End of initialization
487 13:35:07.720254 INFO : Training has run successfully!
488 13:35:07.720768 Check phy result
489 13:35:07.725921 INFO : End of initialization
490 13:35:07.726432 INFO : End of read enable training
491 13:35:07.731414 INFO : End of fine write leveling
492 13:35:07.737049 INFO : End of Write leveling coarse delay
493 13:35:07.737565 INFO : Training has run successfully!
494 13:35:07.738020 Check phy result
495 13:35:07.742683 INFO : End of initialization
496 13:35:07.743215 INFO : End of read dq deskew training
497 13:35:07.748247 INFO : End of MPR read delay center optimization
498 13:35:07.753900 INFO : End of write delay center optimization
499 13:35:07.759451 INFO : End of read delay center optimization
500 13:35:07.759968 INFO : End of max read latency training
501 13:35:07.765083 INFO : Training has run successfully!
502 13:35:07.765590 1D training succeed
503 13:35:07.774195 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 13:35:07.821783 Check phy result
505 13:35:07.822297 INFO : End of initialization
506 13:35:07.843535 INFO : End of 2D read delay Voltage center optimization
507 13:35:07.863788 INFO : End of 2D read delay Voltage center optimization
508 13:35:07.915801 INFO : End of 2D write delay Voltage center optimization
509 13:35:07.965154 INFO : End of 2D write delay Voltage center optimization
510 13:35:07.970770 INFO : Training has run successfully!
511 13:35:07.971351
512 13:35:07.971852 channel==0
513 13:35:07.976364 RxClkDly_Margin_A0==88 ps 9
514 13:35:07.976907 TxDqDly_Margin_A0==98 ps 10
515 13:35:07.981976 RxClkDly_Margin_A1==88 ps 9
516 13:35:07.982519 TxDqDly_Margin_A1==88 ps 9
517 13:35:07.982985 TrainedVREFDQ_A0==74
518 13:35:07.987535 TrainedVREFDQ_A1==74
519 13:35:07.988093 VrefDac_Margin_A0==25
520 13:35:07.988566 DeviceVref_Margin_A0==40
521 13:35:07.993197 VrefDac_Margin_A1==25
522 13:35:07.993747 DeviceVref_Margin_A1==40
523 13:35:07.994209
524 13:35:07.994661
525 13:35:07.995102 channel==1
526 13:35:07.998773 RxClkDly_Margin_A0==98 ps 10
527 13:35:07.999311 TxDqDly_Margin_A0==88 ps 9
528 13:35:08.004426 RxClkDly_Margin_A1==88 ps 9
529 13:35:08.004954 TxDqDly_Margin_A1==88 ps 9
530 13:35:08.009965 TrainedVREFDQ_A0==76
531 13:35:08.010514 TrainedVREFDQ_A1==77
532 13:35:08.010986 VrefDac_Margin_A0==23
533 13:35:08.015554 DeviceVref_Margin_A0==38
534 13:35:08.016105 VrefDac_Margin_A1==24
535 13:35:08.021178 DeviceVref_Margin_A1==37
536 13:35:08.021708
537 13:35:08.022172 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 13:35:08.022630
539 13:35:08.054762 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
540 13:35:08.055357 2D training succeed
541 13:35:08.060420 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 13:35:08.065968 auto size-- 65535DDR cs0 size: 2048MB
543 13:35:08.066523 DDR cs1 size: 2048MB
544 13:35:08.071483 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 13:35:08.072046 cs0 DataBus test pass
546 13:35:08.077079 cs1 DataBus test pass
547 13:35:08.077611 cs0 AddrBus test pass
548 13:35:08.078081 cs1 AddrBus test pass
549 13:35:08.078701
550 13:35:08.082783 100bdlr_step_size ps== 420
551 13:35:08.083360 result report
552 13:35:08.088422 boot times 0Enable ddr reg access
553 13:35:08.093543 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 13:35:08.107021 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 13:35:08.680604 0.0;M3 CHK:0;cm4_sp_mode 0
556 13:35:08.681228 MVN_1=0x00000000
557 13:35:08.686140 MVN_2=0x00000000
558 13:35:08.691975 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 13:35:08.692553 OPS=0x10
560 13:35:08.692998 ring efuse init
561 13:35:08.693429 chipver efuse init
562 13:35:08.697480 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 13:35:08.703047 [0.018961 Inits done]
564 13:35:08.703547 secure task start!
565 13:35:08.703976 high task start!
566 13:35:08.707644 low task start!
567 13:35:08.708158 run into bl31
568 13:35:08.714273 NOTICE: BL31: v1.3(release):4fc40b1
569 13:35:08.722071 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 13:35:08.722564 NOTICE: BL31: G12A normal boot!
571 13:35:08.747515 NOTICE: BL31: BL33 decompress pass
572 13:35:08.753166 ERROR: Error initializing runtime service opteed_fast
573 13:35:09.985968
574 13:35:09.986586
575 13:35:09.993495 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 13:35:09.994019
577 13:35:09.994479 Model: Libre Computer AML-A311D-CC Alta
578 13:35:10.201985 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 13:35:10.226236 DRAM: 2 GiB (effective 3.8 GiB)
580 13:35:10.369281 Core: 408 devices, 31 uclasses, devicetree: separate
581 13:35:10.374197 WDT: Not starting watchdog@f0d0
582 13:35:10.407426 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 13:35:10.419824 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 13:35:10.423932 ** Bad device specification mmc 0 **
585 13:35:10.435153 Card did not respond to voltage select! : -110
586 13:35:10.442754 ** Bad device specification mmc 0 **
587 13:35:10.443259 Couldn't find partition mmc 0
588 13:35:10.451174 Card did not respond to voltage select! : -110
589 13:35:10.456648 ** Bad device specification mmc 0 **
590 13:35:10.457156 Couldn't find partition mmc 0
591 13:35:10.460741 Error: could not access storage.
592 13:35:10.803156 Net: eth0: ethernet@ff3f0000
593 13:35:10.803723 starting USB...
594 13:35:11.055957 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 13:35:11.056550 Starting the controller
596 13:35:11.063077 USB XHCI 1.10
597 13:35:12.774384 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 13:35:12.775006 bl2_stage_init 0x01
599 13:35:12.775467 bl2_stage_init 0x81
600 13:35:12.779288 hw id: 0x0000 - pwm id 0x01
601 13:35:12.779795 bl2_stage_init 0xc1
602 13:35:12.780298 bl2_stage_init 0x02
603 13:35:12.780742
604 13:35:12.784868 L0:00000000
605 13:35:12.785371 L1:20000703
606 13:35:12.785821 L2:00008067
607 13:35:12.786262 L3:14000000
608 13:35:12.788105 B2:00402000
609 13:35:12.788602 B1:e0f83180
610 13:35:12.789048
611 13:35:12.789494 TE: 58124
612 13:35:12.789937
613 13:35:12.799100 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 13:35:12.799612
615 13:35:12.800102 Board ID = 1
616 13:35:12.800552 Set A53 clk to 24M
617 13:35:12.800990 Set A73 clk to 24M
618 13:35:12.804680 Set clk81 to 24M
619 13:35:12.805184 A53 clk: 1200 MHz
620 13:35:12.805632 A73 clk: 1200 MHz
621 13:35:12.810209 CLK81: 166.6M
622 13:35:12.810707 smccc: 00012a92
623 13:35:12.815628 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 13:35:12.816165 board id: 1
625 13:35:12.823197 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 13:35:12.834763 fw parse done
627 13:35:12.839867 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 13:35:12.883392 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 13:35:12.894270 PIEI prepare done
630 13:35:12.894771 fastboot data load
631 13:35:12.895221 fastboot data verify
632 13:35:12.899910 verify result: 266
633 13:35:12.905571 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 13:35:12.906074 LPDDR4 probe
635 13:35:12.906523 ddr clk to 1584MHz
636 13:35:12.913297 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 13:35:12.949822
638 13:35:12.950335 dmc_version 0001
639 13:35:12.957211 Check phy result
640 13:35:12.963298 INFO : End of CA training
641 13:35:12.963825 INFO : End of initialization
642 13:35:12.968906 INFO : Training has run successfully!
643 13:35:12.969424 Check phy result
644 13:35:12.974554 INFO : End of initialization
645 13:35:12.975095 INFO : End of read enable training
646 13:35:12.977809 INFO : End of fine write leveling
647 13:35:12.983308 INFO : End of Write leveling coarse delay
648 13:35:12.988923 INFO : Training has run successfully!
649 13:35:12.989432 Check phy result
650 13:35:12.989879 INFO : End of initialization
651 13:35:12.994587 INFO : End of read dq deskew training
652 13:35:12.997918 INFO : End of MPR read delay center optimization
653 13:35:13.003525 INFO : End of write delay center optimization
654 13:35:13.009029 INFO : End of read delay center optimization
655 13:35:13.009544 INFO : End of max read latency training
656 13:35:13.014676 INFO : Training has run successfully!
657 13:35:13.015190 1D training succeed
658 13:35:13.022888 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 13:35:13.069543 Check phy result
660 13:35:13.070072 INFO : End of initialization
661 13:35:13.092940 INFO : End of 2D read delay Voltage center optimization
662 13:35:13.112140 INFO : End of 2D read delay Voltage center optimization
663 13:35:13.164058 INFO : End of 2D write delay Voltage center optimization
664 13:35:13.214238 INFO : End of 2D write delay Voltage center optimization
665 13:35:13.219766 INFO : Training has run successfully!
666 13:35:13.220369
667 13:35:13.220839 channel==0
668 13:35:13.225368 RxClkDly_Margin_A0==88 ps 9
669 13:35:13.225923 TxDqDly_Margin_A0==98 ps 10
670 13:35:13.230938 RxClkDly_Margin_A1==88 ps 9
671 13:35:13.231481 TxDqDly_Margin_A1==98 ps 10
672 13:35:13.231945 TrainedVREFDQ_A0==74
673 13:35:13.236590 TrainedVREFDQ_A1==74
674 13:35:13.237107 VrefDac_Margin_A0==24
675 13:35:13.237556 DeviceVref_Margin_A0==40
676 13:35:13.242136 VrefDac_Margin_A1==25
677 13:35:13.242652 DeviceVref_Margin_A1==40
678 13:35:13.243100
679 13:35:13.243543
680 13:35:13.247740 channel==1
681 13:35:13.248331 RxClkDly_Margin_A0==88 ps 9
682 13:35:13.248787 TxDqDly_Margin_A0==98 ps 10
683 13:35:13.253338 RxClkDly_Margin_A1==88 ps 9
684 13:35:13.253859 TxDqDly_Margin_A1==88 ps 9
685 13:35:13.258974 TrainedVREFDQ_A0==77
686 13:35:13.259507 TrainedVREFDQ_A1==77
687 13:35:13.259964 VrefDac_Margin_A0==22
688 13:35:13.264563 DeviceVref_Margin_A0==37
689 13:35:13.265088 VrefDac_Margin_A1==24
690 13:35:13.270125 DeviceVref_Margin_A1==37
691 13:35:13.270648
692 13:35:13.271098 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 13:35:13.271538
694 13:35:13.303692 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 13:35:13.304372 2D training succeed
696 13:35:13.309388 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 13:35:13.314930 auto size-- 65535DDR cs0 size: 2048MB
698 13:35:13.315468 DDR cs1 size: 2048MB
699 13:35:13.320595 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 13:35:13.321121 cs0 DataBus test pass
701 13:35:13.326135 cs1 DataBus test pass
702 13:35:13.326669 cs0 AddrBus test pass
703 13:35:13.327118 cs1 AddrBus test pass
704 13:35:13.327553
705 13:35:13.331739 100bdlr_step_size ps== 420
706 13:35:13.332325 result report
707 13:35:13.337377 boot times 0Enable ddr reg access
708 13:35:13.342700 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 13:35:13.356016 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 13:35:13.928095 0.0;M3 CHK:0;cm4_sp_mode 0
711 13:35:13.928721 MVN_1=0x00000000
712 13:35:13.933648 MVN_2=0x00000000
713 13:35:13.939266 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 13:35:13.939826 OPS=0x10
715 13:35:13.940314 ring efuse init
716 13:35:13.940758 chipver efuse init
717 13:35:13.947546 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 13:35:13.948102 [0.018961 Inits done]
719 13:35:13.948543 secure task start!
720 13:35:13.954996 high task start!
721 13:35:13.955498 low task start!
722 13:35:13.955924 run into bl31
723 13:35:13.961722 NOTICE: BL31: v1.3(release):4fc40b1
724 13:35:13.969507 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 13:35:13.970009 NOTICE: BL31: G12A normal boot!
726 13:35:13.994826 NOTICE: BL31: BL33 decompress pass
727 13:35:14.000553 ERROR: Error initializing runtime service opteed_fast
728 13:35:15.233409
729 13:35:15.234039
730 13:35:15.241848 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 13:35:15.242359
732 13:35:15.242821 Model: Libre Computer AML-A311D-CC Alta
733 13:35:15.450317 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 13:35:15.473585 DRAM: 2 GiB (effective 3.8 GiB)
735 13:35:15.616604 Core: 408 devices, 31 uclasses, devicetree: separate
736 13:35:15.622462 WDT: Not starting watchdog@f0d0
737 13:35:15.654840 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 13:35:15.667204 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 13:35:15.672187 ** Bad device specification mmc 0 **
740 13:35:15.682494 Card did not respond to voltage select! : -110
741 13:35:15.690213 ** Bad device specification mmc 0 **
742 13:35:15.690716 Couldn't find partition mmc 0
743 13:35:15.698450 Card did not respond to voltage select! : -110
744 13:35:15.704382 ** Bad device specification mmc 0 **
745 13:35:15.704885 Couldn't find partition mmc 0
746 13:35:15.709022 Error: could not access storage.
747 13:35:16.052587 Net: eth0: ethernet@ff3f0000
748 13:35:16.053166 starting USB...
749 13:35:16.304359 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 13:35:16.304922 Starting the controller
751 13:35:16.311363 USB XHCI 1.10
752 13:35:18.473746 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
753 13:35:18.474433 bl2_stage_init 0x81
754 13:35:18.479389 hw id: 0x0000 - pwm id 0x01
755 13:35:18.479906 bl2_stage_init 0xc1
756 13:35:18.480411 bl2_stage_init 0x02
757 13:35:18.480859
758 13:35:18.484980 L0:00000000
759 13:35:18.485516 L1:20000703
760 13:35:18.485974 L2:00008067
761 13:35:18.486409 L3:14000000
762 13:35:18.486844 B2:00402000
763 13:35:18.490427 B1:e0f83180
764 13:35:18.490939
765 13:35:18.491399 TE: 58150
766 13:35:18.491843
767 13:35:18.496241 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 13:35:18.496767
769 13:35:18.497230 Board ID = 1
770 13:35:18.501833 Set A53 clk to 24M
771 13:35:18.502344 Set A73 clk to 24M
772 13:35:18.502799 Set clk81 to 24M
773 13:35:18.507278 A53 clk: 1200 MHz
774 13:35:18.507776 A73 clk: 1200 MHz
775 13:35:18.508263 CLK81: 166.6M
776 13:35:18.508703 smccc: 00012aac
777 13:35:18.512866 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 13:35:18.518459 board id: 1
779 13:35:18.523311 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 13:35:18.534886 fw parse done
781 13:35:18.540870 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 13:35:18.583490 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 13:35:18.594435 PIEI prepare done
784 13:35:18.594947 fastboot data load
785 13:35:18.595402 fastboot data verify
786 13:35:18.600059 verify result: 266
787 13:35:18.605647 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 13:35:18.606153 LPDDR4 probe
789 13:35:18.606600 ddr clk to 1584MHz
790 13:35:18.613579 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 13:35:18.650959
792 13:35:18.651535 dmc_version 0001
793 13:35:18.657582 Check phy result
794 13:35:18.663424 INFO : End of CA training
795 13:35:18.663931 INFO : End of initialization
796 13:35:18.669030 INFO : Training has run successfully!
797 13:35:18.669532 Check phy result
798 13:35:18.674616 INFO : End of initialization
799 13:35:18.675112 INFO : End of read enable training
800 13:35:18.680372 INFO : End of fine write leveling
801 13:35:18.685887 INFO : End of Write leveling coarse delay
802 13:35:18.686392 INFO : Training has run successfully!
803 13:35:18.686843 Check phy result
804 13:35:18.691428 INFO : End of initialization
805 13:35:18.691926 INFO : End of read dq deskew training
806 13:35:18.697016 INFO : End of MPR read delay center optimization
807 13:35:18.702556 INFO : End of write delay center optimization
808 13:35:18.708265 INFO : End of read delay center optimization
809 13:35:18.708696 INFO : End of max read latency training
810 13:35:18.713761 INFO : Training has run successfully!
811 13:35:18.714188 1D training succeed
812 13:35:18.722936 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 13:35:18.770607 Check phy result
814 13:35:18.771123 INFO : End of initialization
815 13:35:18.793142 INFO : End of 2D read delay Voltage center optimization
816 13:35:18.813443 INFO : End of 2D read delay Voltage center optimization
817 13:35:18.865961 INFO : End of 2D write delay Voltage center optimization
818 13:35:18.914910 INFO : End of 2D write delay Voltage center optimization
819 13:35:18.920460 INFO : Training has run successfully!
820 13:35:18.920903
821 13:35:18.921304 channel==0
822 13:35:18.925999 RxClkDly_Margin_A0==88 ps 9
823 13:35:18.926448 TxDqDly_Margin_A0==98 ps 10
824 13:35:18.931954 RxClkDly_Margin_A1==88 ps 9
825 13:35:18.932445 TxDqDly_Margin_A1==88 ps 9
826 13:35:18.932842 TrainedVREFDQ_A0==74
827 13:35:18.937378 TrainedVREFDQ_A1==74
828 13:35:18.937811 VrefDac_Margin_A0==24
829 13:35:18.938201 DeviceVref_Margin_A0==40
830 13:35:18.942845 VrefDac_Margin_A1==24
831 13:35:18.943272 DeviceVref_Margin_A1==40
832 13:35:18.943658
833 13:35:18.944071
834 13:35:18.944455 channel==1
835 13:35:18.948407 RxClkDly_Margin_A0==98 ps 10
836 13:35:18.948912 TxDqDly_Margin_A0==88 ps 9
837 13:35:18.953966 RxClkDly_Margin_A1==98 ps 10
838 13:35:18.954422 TxDqDly_Margin_A1==88 ps 9
839 13:35:18.959610 TrainedVREFDQ_A0==77
840 13:35:18.960102 TrainedVREFDQ_A1==77
841 13:35:18.960497 VrefDac_Margin_A0==22
842 13:35:18.965215 DeviceVref_Margin_A0==37
843 13:35:18.965650 VrefDac_Margin_A1==22
844 13:35:18.970774 DeviceVref_Margin_A1==37
845 13:35:18.971201
846 13:35:18.971587 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 13:35:18.971970
848 13:35:19.004421 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
849 13:35:19.004911 2D training succeed
850 13:35:19.009859 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 13:35:19.015438 auto size-- 65535DDR cs0 size: 2048MB
852 13:35:19.015874 DDR cs1 size: 2048MB
853 13:35:19.021106 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 13:35:19.021545 cs0 DataBus test pass
855 13:35:19.026657 cs1 DataBus test pass
856 13:35:19.027084 cs0 AddrBus test pass
857 13:35:19.027467 cs1 AddrBus test pass
858 13:35:19.027847
859 13:35:19.032294 100bdlr_step_size ps== 420
860 13:35:19.032731 result report
861 13:35:19.037826 boot times 0Enable ddr reg access
862 13:35:19.043180 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 13:35:19.056667 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 13:35:19.630531 0.0;M3 CHK:0;cm4_sp_mode 0
865 13:35:19.631109 MVN_1=0x00000000
866 13:35:19.635832 MVN_2=0x00000000
867 13:35:19.641586 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 13:35:19.642041 OPS=0x10
869 13:35:19.642460 ring efuse init
870 13:35:19.642860 chipver efuse init
871 13:35:19.647246 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 13:35:19.652845 [0.018960 Inits done]
873 13:35:19.653403 secure task start!
874 13:35:19.653903 high task start!
875 13:35:19.656606 low task start!
876 13:35:19.657148 run into bl31
877 13:35:19.664058 NOTICE: BL31: v1.3(release):4fc40b1
878 13:35:19.671833 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 13:35:19.672339 NOTICE: BL31: G12A normal boot!
880 13:35:19.697380 NOTICE: BL31: BL33 decompress pass
881 13:35:19.703004 ERROR: Error initializing runtime service opteed_fast
882 13:35:20.935877
883 13:35:20.936504
884 13:35:20.943855 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 13:35:20.944376
886 13:35:20.944810 Model: Libre Computer AML-A311D-CC Alta
887 13:35:21.152129 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 13:35:21.175853 DRAM: 2 GiB (effective 3.8 GiB)
889 13:35:21.319028 Core: 408 devices, 31 uclasses, devicetree: separate
890 13:35:21.324608 WDT: Not starting watchdog@f0d0
891 13:35:21.357103 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 13:35:21.369601 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 13:35:21.374733 ** Bad device specification mmc 0 **
894 13:35:21.384984 Card did not respond to voltage select! : -110
895 13:35:21.392543 ** Bad device specification mmc 0 **
896 13:35:21.393078 Couldn't find partition mmc 0
897 13:35:21.400949 Card did not respond to voltage select! : -110
898 13:35:21.406494 ** Bad device specification mmc 0 **
899 13:35:21.407019 Couldn't find partition mmc 0
900 13:35:21.411361 Error: could not access storage.
901 13:35:21.753669 Net: eth0: ethernet@ff3f0000
902 13:35:21.754279 starting USB...
903 13:35:22.005761 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 13:35:22.006382 Starting the controller
905 13:35:22.012207 USB XHCI 1.10
906 13:35:23.566719 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 13:35:23.574859 scanning usb for storage devices... 0 Storage Device(s) found
909 13:35:23.626697 Hit any key to stop autoboot: 1
910 13:35:23.627574 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
911 13:35:23.628314 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
912 13:35:23.628907 Setting prompt string to ['=>']
913 13:35:23.629431 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
914 13:35:23.642560 0
915 13:35:23.643545 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 13:35:23.644148 Sending with 10 millisecond of delay
918 13:35:24.779026 => setenv autoload no
919 13:35:24.789838 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
920 13:35:24.795231 setenv autoload no
921 13:35:24.796050 Sending with 10 millisecond of delay
923 13:35:26.592887 => setenv initrd_high 0xffffffff
924 13:35:26.603664 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
925 13:35:26.604646 setenv initrd_high 0xffffffff
926 13:35:26.605425 Sending with 10 millisecond of delay
928 13:35:28.221792 => setenv fdt_high 0xffffffff
929 13:35:28.232591 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
930 13:35:28.233501 setenv fdt_high 0xffffffff
931 13:35:28.234275 Sending with 10 millisecond of delay
933 13:35:28.526164 => dhcp
934 13:35:28.536918 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
935 13:35:28.537813 dhcp
936 13:35:28.538301 Speed: 1000, full duplex
937 13:35:28.538756 BOOTP broadcast 1
938 13:35:28.655140 UDP wrong checksum 000000ff 0000bc4e
939 13:35:28.784362 BOOTP broadcast 2
940 13:35:28.796177 DHCP client bound to address 192.168.6.33 (260 ms)
941 13:35:28.796998 Sending with 10 millisecond of delay
943 13:35:30.474004 => setenv serverip 192.168.6.2
944 13:35:30.484825 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
945 13:35:30.485786 setenv serverip 192.168.6.2
946 13:35:30.486575 Sending with 10 millisecond of delay
948 13:35:34.211874 => tftpboot 0x01080000 739625/tftp-deploy-un6efvdh/kernel/uImage
949 13:35:34.222772 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
950 13:35:34.223655 tftpboot 0x01080000 739625/tftp-deploy-un6efvdh/kernel/uImage
951 13:35:34.224202 Speed: 1000, full duplex
952 13:35:34.224658 Using ethernet@ff3f0000 device
953 13:35:34.225583 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
954 13:35:34.231354 Filename '739625/tftp-deploy-un6efvdh/kernel/uImage'.
955 13:35:34.234197 Load address: 0x1080000
956 13:35:37.719226 Loading: *################################################## 43.6 MiB
957 13:35:37.719878 12.5 MiB/s
958 13:35:37.720388 done
959 13:35:37.722473 Bytes transferred = 45724224 (2b9b240 hex)
960 13:35:37.723270 Sending with 10 millisecond of delay
962 13:35:42.410246 => tftpboot 0x08000000 739625/tftp-deploy-un6efvdh/ramdisk/ramdisk.cpio.gz.uboot
963 13:35:42.420995 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
964 13:35:42.421769 tftpboot 0x08000000 739625/tftp-deploy-un6efvdh/ramdisk/ramdisk.cpio.gz.uboot
965 13:35:42.422201 Speed: 1000, full duplex
966 13:35:42.422601 Using ethernet@ff3f0000 device
967 13:35:42.423560 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
968 13:35:42.432130 Filename '739625/tftp-deploy-un6efvdh/ramdisk/ramdisk.cpio.gz.uboot'.
969 13:35:42.432577 Load address: 0x8000000
970 13:35:43.115066 Loading: *## UDP wrong checksum 000000ff 00004444
971 13:35:43.138508 UDP wrong checksum 000000ff 0000c936
972 13:35:50.376361 T ############################################### UDP wrong checksum 00000005 00008300
973 13:35:55.376770 T UDP wrong checksum 00000005 00008300
974 13:36:05.380111 T T UDP wrong checksum 00000005 00008300
975 13:36:25.384038 T T T T UDP wrong checksum 00000005 00008300
976 13:36:40.388169 T T
977 13:36:40.388817 Retry count exceeded; starting again
979 13:36:40.391046 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
982 13:36:40.393094 end: 2.4 uboot-commands (duration 00:01:49) [common]
984 13:36:40.394688 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
986 13:36:40.395800 end: 2 uboot-action (duration 00:01:49) [common]
988 13:36:40.397473 Cleaning after the job
989 13:36:40.398067 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/739625/tftp-deploy-un6efvdh/ramdisk
990 13:36:40.399301 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/739625/tftp-deploy-un6efvdh/kernel
991 13:36:40.447602 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/739625/tftp-deploy-un6efvdh/dtb
992 13:36:40.448456 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/739625/tftp-deploy-un6efvdh/modules
993 13:36:40.469182 start: 4.1 power-off (timeout 00:00:30) [common]
994 13:36:40.469816 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
995 13:36:40.507493 >> OK - accepted request
996 13:36:40.509223 Returned 0 in 0 seconds
997 13:36:40.609902 end: 4.1 power-off (duration 00:00:00) [common]
999 13:36:40.610759 start: 4.2 read-feedback (timeout 00:10:00) [common]
1000 13:36:40.611389 Listened to connection for namespace 'common' for up to 1s
1001 13:36:41.611446 Finalising connection for namespace 'common'
1002 13:36:41.612225 Disconnecting from shell: Finalise
1003 13:36:41.612778 =>
1004 13:36:41.713807 end: 4.2 read-feedback (duration 00:00:01) [common]
1005 13:36:41.714447 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/739625
1006 13:36:42.002216 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/739625
1007 13:36:42.002819 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.