Boot log: beaglebone-black
- Warnings: 3
- Kernel Warnings: 101
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 07:30:59.023771 lava-dispatcher, installed at version: 2024.01
2 07:30:59.024087 start: 0 validate
3 07:30:59.024241 Start time: 2024-09-19 07:30:59.024229+00:00 (UTC)
4 07:30:59.024406 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 07:30:59.359092 Validating that http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/clang-17/kernel/zImage exists
6 07:30:59.528031 Validating that http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/clang-17/dtbs/ti/omap/am335x-boneblack.dtb exists
7 07:30:59.694431 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 07:30:59.860475 Validating that http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/clang-17/modules.tar.xz exists
9 07:31:00.031560 validate duration: 1.01
11 07:31:00.032320 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 07:31:00.032554 start: 1.1 download-retry (timeout 00:10:00) [common]
13 07:31:00.032778 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 07:31:00.033255 Not decompressing ramdisk as can be used compressed.
15 07:31:00.033556 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 07:31:00.033731 saving as /var/lib/lava/dispatcher/tmp/742859/tftp-deploy-yq2i0syt/ramdisk/initrd.cpio.gz
17 07:31:00.033883 total size: 4775763 (4 MB)
18 07:31:00.364211 progress 0 % (0 MB)
19 07:31:00.859140 progress 5 % (0 MB)
20 07:31:01.019877 progress 10 % (0 MB)
21 07:31:01.028273 progress 15 % (0 MB)
22 07:31:01.183828 progress 20 % (0 MB)
23 07:31:01.190112 progress 25 % (1 MB)
24 07:31:01.198449 progress 30 % (1 MB)
25 07:31:01.202768 progress 35 % (1 MB)
26 07:31:01.348327 progress 40 % (1 MB)
27 07:31:01.352154 progress 45 % (2 MB)
28 07:31:01.355835 progress 50 % (2 MB)
29 07:31:01.359828 progress 55 % (2 MB)
30 07:31:01.363352 progress 60 % (2 MB)
31 07:31:01.366957 progress 65 % (2 MB)
32 07:31:01.371040 progress 70 % (3 MB)
33 07:31:01.374320 progress 75 % (3 MB)
34 07:31:01.512477 progress 80 % (3 MB)
35 07:31:01.516274 progress 85 % (3 MB)
36 07:31:01.520360 progress 90 % (4 MB)
37 07:31:01.523905 progress 95 % (4 MB)
38 07:31:01.527169 progress 100 % (4 MB)
39 07:31:01.527740 4 MB downloaded in 1.49 s (3.05 MB/s)
40 07:31:01.528142 end: 1.1.1 http-download (duration 00:00:01) [common]
42 07:31:01.528763 end: 1.1 download-retry (duration 00:00:01) [common]
43 07:31:01.528976 start: 1.2 download-retry (timeout 00:09:59) [common]
44 07:31:01.529180 start: 1.2.1 http-download (timeout 00:09:59) [common]
45 07:31:01.529590 downloading http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/clang-17/kernel/zImage
46 07:31:01.529764 saving as /var/lib/lava/dispatcher/tmp/742859/tftp-deploy-yq2i0syt/kernel/zImage
47 07:31:01.529913 total size: 12050944 (11 MB)
48 07:31:01.530066 No compression specified
49 07:31:01.696591 progress 0 % (0 MB)
50 07:31:01.705600 progress 5 % (0 MB)
51 07:31:01.714550 progress 10 % (1 MB)
52 07:31:01.724027 progress 15 % (1 MB)
53 07:31:01.732770 progress 20 % (2 MB)
54 07:31:01.739966 progress 25 % (2 MB)
55 07:31:01.871167 progress 30 % (3 MB)
56 07:31:01.880126 progress 35 % (4 MB)
57 07:31:01.890141 progress 40 % (4 MB)
58 07:31:01.898793 progress 45 % (5 MB)
59 07:31:02.028420 progress 50 % (5 MB)
60 07:31:02.037849 progress 55 % (6 MB)
61 07:31:02.054004 progress 60 % (6 MB)
62 07:31:02.063388 progress 65 % (7 MB)
63 07:31:02.072210 progress 70 % (8 MB)
64 07:31:02.191549 progress 75 % (8 MB)
65 07:31:02.200778 progress 80 % (9 MB)
66 07:31:02.219793 progress 85 % (9 MB)
67 07:31:02.228625 progress 90 % (10 MB)
68 07:31:02.237726 progress 95 % (10 MB)
69 07:31:02.363340 progress 100 % (11 MB)
70 07:31:02.364144 11 MB downloaded in 0.83 s (13.78 MB/s)
71 07:31:02.364552 end: 1.2.1 http-download (duration 00:00:01) [common]
73 07:31:02.365133 end: 1.2 download-retry (duration 00:00:01) [common]
74 07:31:02.365353 start: 1.3 download-retry (timeout 00:09:58) [common]
75 07:31:02.365552 start: 1.3.1 http-download (timeout 00:09:58) [common]
76 07:31:02.365954 downloading http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/clang-17/dtbs/ti/omap/am335x-boneblack.dtb
77 07:31:02.366123 saving as /var/lib/lava/dispatcher/tmp/742859/tftp-deploy-yq2i0syt/dtb/am335x-boneblack.dtb
78 07:31:02.366267 total size: 70568 (0 MB)
79 07:31:02.366416 No compression specified
80 07:31:02.534194 progress 46 % (0 MB)
81 07:31:02.535067 progress 92 % (0 MB)
82 07:31:02.535805 progress 100 % (0 MB)
83 07:31:02.536119 0 MB downloaded in 0.17 s (0.40 MB/s)
84 07:31:02.536513 end: 1.3.1 http-download (duration 00:00:00) [common]
86 07:31:02.537099 end: 1.3 download-retry (duration 00:00:00) [common]
87 07:31:02.537301 start: 1.4 download-retry (timeout 00:09:57) [common]
88 07:31:02.537508 start: 1.4.1 http-download (timeout 00:09:57) [common]
89 07:31:02.537938 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 07:31:02.538110 saving as /var/lib/lava/dispatcher/tmp/742859/tftp-deploy-yq2i0syt/nfsrootfs/full.rootfs.tar
91 07:31:02.538255 total size: 117747780 (112 MB)
92 07:31:02.538408 Using unxz to decompress xz
93 07:31:02.706039 progress 0 % (0 MB)
94 07:31:03.111818 progress 5 % (5 MB)
95 07:31:03.563792 progress 10 % (11 MB)
96 07:31:03.970861 progress 15 % (16 MB)
97 07:31:04.417815 progress 20 % (22 MB)
98 07:31:04.863661 progress 25 % (28 MB)
99 07:31:05.287437 progress 30 % (33 MB)
100 07:31:05.718820 progress 35 % (39 MB)
101 07:31:06.071001 progress 40 % (44 MB)
102 07:31:06.490222 progress 45 % (50 MB)
103 07:31:06.866008 progress 50 % (56 MB)
104 07:31:07.255022 progress 55 % (61 MB)
105 07:31:07.623525 progress 60 % (67 MB)
106 07:31:07.984940 progress 65 % (73 MB)
107 07:31:08.373074 progress 70 % (78 MB)
108 07:31:08.743399 progress 75 % (84 MB)
109 07:31:09.108026 progress 80 % (89 MB)
110 07:31:09.464724 progress 85 % (95 MB)
111 07:31:09.826179 progress 90 % (101 MB)
112 07:31:10.176846 progress 95 % (106 MB)
113 07:31:10.640225 progress 100 % (112 MB)
114 07:31:10.642318 112 MB downloaded in 8.10 s (13.86 MB/s)
115 07:31:10.642683 end: 1.4.1 http-download (duration 00:00:08) [common]
117 07:31:10.643224 end: 1.4 download-retry (duration 00:00:08) [common]
118 07:31:10.643427 start: 1.5 download-retry (timeout 00:09:49) [common]
119 07:31:10.643660 start: 1.5.1 http-download (timeout 00:09:49) [common]
120 07:31:10.644049 downloading http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/clang-17/modules.tar.xz
121 07:31:10.644195 saving as /var/lib/lava/dispatcher/tmp/742859/tftp-deploy-yq2i0syt/modules/modules.tar
122 07:31:10.644351 total size: 6913848 (6 MB)
123 07:31:10.644507 Using unxz to decompress xz
124 07:31:10.811718 progress 0 % (0 MB)
125 07:31:10.830648 progress 5 % (0 MB)
126 07:31:10.853207 progress 10 % (0 MB)
127 07:31:10.873723 progress 15 % (1 MB)
128 07:31:10.899228 progress 20 % (1 MB)
129 07:31:10.921163 progress 25 % (1 MB)
130 07:31:10.944882 progress 30 % (2 MB)
131 07:31:10.965969 progress 35 % (2 MB)
132 07:31:10.989500 progress 40 % (2 MB)
133 07:31:11.010641 progress 45 % (2 MB)
134 07:31:11.033976 progress 50 % (3 MB)
135 07:31:11.056532 progress 55 % (3 MB)
136 07:31:11.078254 progress 60 % (3 MB)
137 07:31:11.101437 progress 65 % (4 MB)
138 07:31:11.148704 progress 70 % (4 MB)
139 07:31:11.172105 progress 75 % (4 MB)
140 07:31:11.193966 progress 80 % (5 MB)
141 07:31:11.217980 progress 85 % (5 MB)
142 07:31:11.238949 progress 90 % (5 MB)
143 07:31:11.261868 progress 95 % (6 MB)
144 07:31:11.321649 progress 100 % (6 MB)
145 07:31:11.325100 6 MB downloaded in 0.68 s (9.69 MB/s)
146 07:31:11.325471 end: 1.5.1 http-download (duration 00:00:01) [common]
148 07:31:11.325993 end: 1.5 download-retry (duration 00:00:01) [common]
149 07:31:11.326185 start: 1.6 prepare-tftp-overlay (timeout 00:09:49) [common]
150 07:31:11.326378 start: 1.6.1 extract-nfsrootfs (timeout 00:09:49) [common]
151 07:31:16.745610 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/742859/extract-nfsrootfs-tofrx_ks
152 07:31:16.745950 end: 1.6.1 extract-nfsrootfs (duration 00:00:05) [common]
153 07:31:16.746062 start: 1.6.2 lava-overlay (timeout 00:09:43) [common]
154 07:31:16.746340 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n
155 07:31:16.746522 makedir: /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin
156 07:31:16.746647 makedir: /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/tests
157 07:31:16.746771 makedir: /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/results
158 07:31:16.746892 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-add-keys
159 07:31:16.747082 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-add-sources
160 07:31:16.747255 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-background-process-start
161 07:31:16.747424 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-background-process-stop
162 07:31:16.747636 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-common-functions
163 07:31:16.747820 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-echo-ipv4
164 07:31:16.747988 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-install-packages
165 07:31:16.748172 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-installed-packages
166 07:31:16.748339 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-os-build
167 07:31:16.748505 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-probe-channel
168 07:31:16.748678 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-probe-ip
169 07:31:16.748846 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-target-ip
170 07:31:16.749012 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-target-mac
171 07:31:16.749183 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-target-storage
172 07:31:16.749352 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-test-case
173 07:31:16.749526 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-test-event
174 07:31:16.749691 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-test-feedback
175 07:31:16.749859 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-test-raise
176 07:31:16.750045 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-test-reference
177 07:31:16.750211 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-test-runner
178 07:31:16.750385 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-test-set
179 07:31:16.750556 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-test-shell
180 07:31:16.750727 Updating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-add-keys (debian)
181 07:31:16.750982 Updating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-add-sources (debian)
182 07:31:16.751194 Updating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-install-packages (debian)
183 07:31:16.751395 Updating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-installed-packages (debian)
184 07:31:16.751609 Updating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/bin/lava-os-build (debian)
185 07:31:16.751786 Creating /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/environment
186 07:31:16.751911 LAVA metadata
187 07:31:16.751992 - LAVA_JOB_ID=742859
188 07:31:16.752065 - LAVA_DISPATCHER_IP=192.168.56.76
189 07:31:16.752215 start: 1.6.2.1 ssh-authorize (timeout 00:09:43) [common]
190 07:31:16.752562 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 07:31:16.752666 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:43) [common]
192 07:31:16.752751 skipped lava-vland-overlay
193 07:31:16.752846 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 07:31:16.752938 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:43) [common]
195 07:31:16.753006 skipped lava-multinode-overlay
196 07:31:16.753098 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 07:31:16.753196 start: 1.6.2.4 test-definition (timeout 00:09:43) [common]
198 07:31:16.753281 Loading test definitions
199 07:31:16.753379 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:43) [common]
200 07:31:16.753450 Using /lava-742859 at stage 0
201 07:31:16.753885 uuid=742859_1.6.2.4.1 testdef=None
202 07:31:16.753996 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 07:31:16.754097 start: 1.6.2.4.2 test-overlay (timeout 00:09:43) [common]
204 07:31:16.754622 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 07:31:16.754867 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:43) [common]
207 07:31:16.755792 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 07:31:16.756083 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:43) [common]
210 07:31:16.756745 runner path: /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/0/tests/0_timesync-off test_uuid 742859_1.6.2.4.1
211 07:31:16.756974 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 07:31:16.757231 start: 1.6.2.4.5 git-repo-action (timeout 00:09:43) [common]
214 07:31:16.757317 Using /lava-742859 at stage 0
215 07:31:16.757446 Fetching tests from https://github.com/kernelci/test-definitions.git
216 07:31:16.757545 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/0/tests/1_kselftest-dt'
217 07:31:18.507658 Running '/usr/bin/git checkout kernelci.org
218 07:31:18.677308 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 07:31:18.677797 uuid=742859_1.6.2.4.5 testdef=None
220 07:31:18.677922 end: 1.6.2.4.5 git-repo-action (duration 00:00:02) [common]
222 07:31:18.678145 start: 1.6.2.4.6 test-overlay (timeout 00:09:41) [common]
223 07:31:18.678991 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 07:31:18.679227 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:41) [common]
226 07:31:18.680425 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 07:31:18.680695 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:41) [common]
229 07:31:18.681828 runner path: /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/0/tests/1_kselftest-dt test_uuid 742859_1.6.2.4.5
230 07:31:18.681931 BOARD='beaglebone-black'
231 07:31:18.682003 BRANCH='next'
232 07:31:18.682076 SKIPFILE='/dev/null'
233 07:31:18.682135 SKIP_INSTALL='True'
234 07:31:18.682189 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz'
235 07:31:18.682252 TST_CASENAME=''
236 07:31:18.682315 TST_CMDFILES='dt'
237 07:31:18.682532 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 07:31:18.682748 Creating lava-test-runner.conf files
240 07:31:18.682812 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/742859/lava-overlay-tpz1w74n/lava-742859/0 for stage 0
241 07:31:18.682921 - 0_timesync-off
242 07:31:18.682988 - 1_kselftest-dt
243 07:31:18.683110 end: 1.6.2.4 test-definition (duration 00:00:02) [common]
244 07:31:18.683195 start: 1.6.2.5 compress-overlay (timeout 00:09:41) [common]
245 07:31:27.186772 end: 1.6.2.5 compress-overlay (duration 00:00:09) [common]
246 07:31:27.186944 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:33) [common]
247 07:31:27.187055 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 07:31:27.187159 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
249 07:31:27.187266 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
250 07:31:27.313788 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 07:31:27.314020 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
252 07:31:27.314119 extracting modules file /var/lib/lava/dispatcher/tmp/742859/tftp-deploy-yq2i0syt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/742859/extract-nfsrootfs-tofrx_ks
253 07:31:27.627200 extracting modules file /var/lib/lava/dispatcher/tmp/742859/tftp-deploy-yq2i0syt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/742859/extract-overlay-ramdisk-ii7_66nl/ramdisk
254 07:31:27.959053 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 07:31:27.959241 start: 1.6.5 apply-overlay-tftp (timeout 00:09:32) [common]
256 07:31:27.959331 [common] Applying overlay to NFS
257 07:31:27.959389 [common] Applying overlay /var/lib/lava/dispatcher/tmp/742859/compress-overlay-pb_5ilb9/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/742859/extract-nfsrootfs-tofrx_ks
258 07:31:29.103706 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 07:31:29.103890 start: 1.6.6 prepare-kernel (timeout 00:09:31) [common]
260 07:31:29.103974 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:31) [common]
261 07:31:29.104060 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 07:31:29.104142 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 07:31:29.104223 start: 1.6.7 configure-preseed-file (timeout 00:09:31) [common]
264 07:31:29.104308 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 07:31:29.104381 start: 1.6.8 compress-ramdisk (timeout 00:09:31) [common]
266 07:31:29.104445 Building ramdisk /var/lib/lava/dispatcher/tmp/742859/extract-overlay-ramdisk-ii7_66nl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/742859/extract-overlay-ramdisk-ii7_66nl/ramdisk
267 07:31:29.393674 >> 79000 blocks
268 07:31:31.268419 Adding RAMdisk u-boot header.
269 07:31:31.268715 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/742859/extract-overlay-ramdisk-ii7_66nl/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/742859/extract-overlay-ramdisk-ii7_66nl/ramdisk.cpio.gz.uboot
270 07:31:31.367276 output: Image Name:
271 07:31:31.367548 output: Created: Thu Sep 19 07:31:31 2024
272 07:31:31.367689 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 07:31:31.367806 output: Data Size: 15346645 Bytes = 14986.96 KiB = 14.64 MiB
274 07:31:31.367918 output: Load Address: 00000000
275 07:31:31.368029 output: Entry Point: 00000000
276 07:31:31.368141 output:
277 07:31:31.368369 rename /var/lib/lava/dispatcher/tmp/742859/extract-overlay-ramdisk-ii7_66nl/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/742859/tftp-deploy-yq2i0syt/ramdisk/ramdisk.cpio.gz.uboot
278 07:31:31.368586 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
279 07:31:31.368759 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
280 07:31:31.368922 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:29) [common]
281 07:31:31.369065 No LXC device requested
282 07:31:31.369213 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 07:31:31.369366 start: 1.8 deploy-device-env (timeout 00:09:29) [common]
284 07:31:31.369516 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 07:31:31.369668 Checking files for TFTP limit of 4294967296 bytes.
286 07:31:31.370819 end: 1 tftp-deploy (duration 00:00:31) [common]
287 07:31:31.371058 start: 2 uboot-action (timeout 00:05:00) [common]
288 07:31:31.371261 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 07:31:31.371452 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 07:31:31.371696 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 07:31:31.372001 substitutions:
292 07:31:31.372160 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 07:31:31.372308 - {DTB_ADDR}: 0x88000000
294 07:31:31.372453 - {DTB}: 742859/tftp-deploy-yq2i0syt/dtb/am335x-boneblack.dtb
295 07:31:31.372598 - {INITRD}: 742859/tftp-deploy-yq2i0syt/ramdisk/ramdisk.cpio.gz.uboot
296 07:31:31.372723 - {KERNEL_ADDR}: 0x82000000
297 07:31:31.372835 - {KERNEL}: 742859/tftp-deploy-yq2i0syt/kernel/zImage
298 07:31:31.372947 - {LAVA_MAC}: None
299 07:31:31.373077 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/742859/extract-nfsrootfs-tofrx_ks
300 07:31:31.373193 - {NFS_SERVER_IP}: 192.168.56.76
301 07:31:31.373305 - {PRESEED_CONFIG}: None
302 07:31:31.373416 - {PRESEED_LOCAL}: None
303 07:31:31.373526 - {RAMDISK_ADDR}: 0x83000000
304 07:31:31.373664 - {RAMDISK}: 742859/tftp-deploy-yq2i0syt/ramdisk/ramdisk.cpio.gz.uboot
305 07:31:31.373807 - {ROOT_PART}: None
306 07:31:31.373947 - {ROOT}: None
307 07:31:31.374087 - {SERVER_IP}: 192.168.56.76
308 07:31:31.374227 - {TEE_ADDR}: 0x83000000
309 07:31:31.374367 - {TEE}: None
310 07:31:31.374509 Parsed boot commands:
311 07:31:31.374647 - setenv autoload no
312 07:31:31.374808 - setenv initrd_high 0xffffffff
313 07:31:31.374951 - setenv fdt_high 0xffffffff
314 07:31:31.375088 - dhcp
315 07:31:31.375227 - setenv serverip 192.168.56.76
316 07:31:31.375366 - tftp 0x82000000 742859/tftp-deploy-yq2i0syt/kernel/zImage
317 07:31:31.375530 - tftp 0x83000000 742859/tftp-deploy-yq2i0syt/ramdisk/ramdisk.cpio.gz.uboot
318 07:31:31.375687 - setenv initrd_size ${filesize}
319 07:31:31.375825 - tftp 0x88000000 742859/tftp-deploy-yq2i0syt/dtb/am335x-boneblack.dtb
320 07:31:31.375965 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/742859/extract-nfsrootfs-tofrx_ks,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 07:31:31.376112 - bootz 0x82000000 0x83000000 0x88000000
322 07:31:31.376310 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 07:31:31.376802 start: 2.3 connect-device (timeout 00:05:00) [common]
325 07:31:31.376930 [common] connect-device Connecting to device using 'telnet conserv3 3000'
326 07:31:31.384997 Setting prompt string to ['lava-test: # ']
327 07:31:31.385747 end: 2.3 connect-device (duration 00:00:00) [common]
328 07:31:31.385977 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 07:31:31.386156 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 07:31:31.386376 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 07:31:31.386841 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-03'
332 07:31:31.404089 >> OK - accepted request
333 07:31:31.405526 Returned 0 in 0 seconds
334 07:31:31.506490 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
336 07:31:31.507250 end: 2.4.1 reset-device (duration 00:00:00) [common]
337 07:31:31.507454 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
338 07:31:31.507656 Setting prompt string to ['Hit any key to stop autoboot']
339 07:31:31.507815 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
340 07:31:31.508509 Trying 192.168.56.22...
341 07:31:31.508656 Connected to conserv3.
342 07:31:31.508789 Escape character is '^]'.
343 07:31:31.508949
344 07:31:31.509096 ser2net port telnet,3000 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
345 07:31:31.509250
346 07:31:39.791883
347 07:31:39.798920 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
348 07:31:39.799321 Trying to boot from MMC1
349 07:31:40.375563
350 07:31:40.375962
351 07:31:40.381088 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
352 07:31:40.381486
353 07:31:40.381651 CPU : AM335X-GP rev 2.0
354 07:31:40.386406 Model: TI AM335x BeagleBone Black
355 07:31:40.386796 DRAM: 512 MiB
356 07:31:43.848112
357 07:31:43.853856 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
358 07:31:43.854158 Trying to boot from MMC1
359 07:31:44.433597
360 07:31:44.433997
361 07:31:44.439170 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
362 07:31:44.439593
363 07:31:44.439762 CPU : AM335X-GP rev 2.0
364 07:31:44.444345 Model: TI AM335x BeagleBone Black
365 07:31:44.444735 DRAM: 512 MiB
366 07:31:46.541594
367 07:31:46.548659 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
368 07:31:46.549053 Trying to boot from MMC1
369 07:31:47.126568
370 07:31:47.126957
371 07:31:47.132210 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
372 07:31:47.132600
373 07:31:47.132765 CPU : AM335X-GP rev 2.0
374 07:31:47.137333 Model: TI AM335x BeagleBone Black
375 07:31:47.137724 DRAM: 512 MiB
376 07:31:47.220921 Core: 160 devices, 18 uclasses, devicetree: separate
377 07:31:47.235394 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
378 07:31:47.636486 NAND: 0 MiB
379 07:31:47.646711 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
380 07:31:47.721370 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
381 07:31:47.741719 <ethaddr> not set. Validating first E-fuse MAC
382 07:31:47.771583 Net: eth2: ethernet@4a100000, eth3: usb_ether
384 07:31:47.831058 Hit any key to stop autoboot: 2
385 07:31:47.831710 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
386 07:31:47.831967 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
387 07:31:47.832165 Setting prompt string to ['=>']
388 07:31:47.832368 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
389 07:31:47.840807 0
390 07:31:47.841556 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
391 07:31:47.841772 Sending with 10 millisecond of delay
393 07:31:48.986182 => setenv autoload no
394 07:31:48.996992 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
395 07:31:48.999076 setenv autoload no
396 07:31:48.999512 Sending with 10 millisecond of delay
398 07:31:50.802988 => setenv initrd_high 0xffffffff
399 07:31:50.813412 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
400 07:31:50.813834 setenv initrd_high 0xffffffff
401 07:31:50.814235 Sending with 10 millisecond of delay
403 07:31:52.436137 => setenv fdt_high 0xffffffff
404 07:31:52.446636 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
405 07:31:52.447140 setenv fdt_high 0xffffffff
406 07:31:52.447560 Sending with 10 millisecond of delay
408 07:31:52.740197 => dhcp
409 07:31:52.750704 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
410 07:31:52.751195 dhcp
411 07:31:52.753655 link up on port 0, speed 100, full duplex
412 07:31:52.753959 BOOTP broadcast 1
413 07:31:53.004788 BOOTP broadcast 2
414 07:31:53.506465 BOOTP broadcast 3
415 07:31:54.508921 BOOTP broadcast 4
416 07:31:54.538582 *** Unhandled DHCP Option in OFFER/ACK: 42
417 07:31:54.568571 *** Unhandled DHCP Option in OFFER/ACK: 42
418 07:31:54.574081 DHCP client bound to address 192.168.56.9 (1818 ms)
419 07:31:54.574612 Sending with 10 millisecond of delay
421 07:31:56.375745 => setenv serverip 192.168.56.76
422 07:31:56.386440 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
423 07:31:56.386858 setenv serverip 192.168.56.76
424 07:31:56.387214 Sending with 10 millisecond of delay
426 07:31:59.879898 => tftp 0x82000000 742859/tftp-deploy-yq2i0syt/kernel/zImage
427 07:31:59.890378 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:31)
428 07:31:59.890854 tftp 0x82000000 742859/tftp-deploy-yq2i0syt/kernel/zImage
429 07:31:59.891035 link up on port 0, speed 100, full duplex
430 07:31:59.894963 Using ethernet@4a100000 device
431 07:31:59.900562 TFTP from server 192.168.56.76; our IP address is 192.168.56.9
432 07:31:59.907041 Filename '742859/tftp-deploy-yq2i0syt/kernel/zImage'.
433 07:31:59.907184 Load address: 0x82000000
434 07:32:02.270496 Loading: *################################################## 11.5 MiB
435 07:32:02.270822 4.9 MiB/s
436 07:32:02.271000 done
437 07:32:02.274773 Bytes transferred = 12050944 (b7e200 hex)
438 07:32:02.275200 Sending with 10 millisecond of delay
440 07:32:06.734205 => tftp 0x83000000 742859/tftp-deploy-yq2i0syt/ramdisk/ramdisk.cpio.gz.uboot
441 07:32:06.744754 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
442 07:32:06.745301 tftp 0x83000000 742859/tftp-deploy-yq2i0syt/ramdisk/ramdisk.cpio.gz.uboot
443 07:32:06.745484 link up on port 0, speed 100, full duplex
444 07:32:06.749650 Using ethernet@4a100000 device
445 07:32:06.755298 TFTP from server 192.168.56.76; our IP address is 192.168.56.9
446 07:32:06.763783 Filename '742859/tftp-deploy-yq2i0syt/ramdisk/ramdisk.cpio.gz.uboot'.
447 07:32:06.764030 Load address: 0x83000000
448 07:32:09.659297 Loading: *################################################## 14.6 MiB
449 07:32:09.659605 5.1 MiB/s
450 07:32:09.659774 done
451 07:32:09.662585 Bytes transferred = 15346709 (ea2c15 hex)
452 07:32:09.663039 Sending with 10 millisecond of delay
454 07:32:11.523232 => setenv initrd_size ${filesize}
455 07:32:11.533788 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
456 07:32:11.534307 setenv initrd_size ${filesize}
457 07:32:11.534724 Sending with 10 millisecond of delay
459 07:32:15.683642 => tftp 0x88000000 742859/tftp-deploy-yq2i0syt/dtb/am335x-boneblack.dtb
460 07:32:15.694224 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
461 07:32:15.694831 tftp 0x88000000 742859/tftp-deploy-yq2i0syt/dtb/am335x-boneblack.dtb
462 07:32:15.695015 link up on port 0, speed 100, full duplex
463 07:32:15.699723 Using ethernet@4a100000 device
464 07:32:15.705056 TFTP from server 192.168.56.76; our IP address is 192.168.56.9
465 07:32:15.708088 Filename '742859/tftp-deploy-yq2i0syt/dtb/am335x-boneblack.dtb'.
466 07:32:15.723092 Load address: 0x88000000
467 07:32:15.728700 Loading: *################################################## 68.9 KiB
468 07:32:15.729006 4.2 MiB/s
469 07:32:15.729168 done
470 07:32:15.735871 Bytes transferred = 70568 (113a8 hex)
471 07:32:15.736468 Sending with 10 millisecond of delay
473 07:32:29.055822 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/742859/extract-nfsrootfs-tofrx_ks,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
474 07:32:29.066263 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
475 07:32:29.066671 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/742859/extract-nfsrootfs-tofrx_ks,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
476 07:32:29.067029 Sending with 10 millisecond of delay
478 07:32:31.406633 => bootz 0x82000000 0x83000000 0x88000000
479 07:32:31.417046 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
480 07:32:31.417420 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
481 07:32:31.417868 bootz 0x82000000 0x83000000 0x88000000
482 07:32:31.418025 Kernel image @ 0x82000000 [ 0x000000 - 0xb7e200 ]
483 07:32:31.418877 ## Loading init Ramdisk from Legacy Image at 83000000 ...
484 07:32:31.424612 Image Name:
485 07:32:31.424867 Created: 2024-09-19 7:31:31 UTC
486 07:32:31.430206 Image Type: ARM Linux RAMDisk Image (uncompressed)
487 07:32:31.435768 Data Size: 15346645 Bytes = 14.6 MiB
488 07:32:31.436012 Load Address: 00000000
489 07:32:31.441958 Entry Point: 00000000
490 07:32:31.616505 Verifying Checksum ... OK
491 07:32:31.616817 ## Flattened Device Tree blob at 88000000
492 07:32:31.623162 Booting using the fdt blob at 0x88000000
493 07:32:31.623455 Working FDT set to 88000000
494 07:32:31.628485 Using Device Tree in place at 88000000, end 880143a7
495 07:32:31.632967 Working FDT set to 88000000
496 07:32:31.646210
497 07:32:31.646453 Starting kernel ...
498 07:32:31.646636
499 07:32:31.647090 end: 2.4.3 bootloader-commands (duration 00:00:44) [common]
500 07:32:31.647319 start: 2.4.4 auto-login-action (timeout 00:04:00) [common]
501 07:32:31.647482 Setting prompt string to ['Linux version [0-9]']
502 07:32:31.647685 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
503 07:32:31.647875 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
504 07:32:32.564648 [ 0.000000] Booting Linux on physical CPU 0x0
505 07:32:32.570302 start: 2.4.4.1 login-action (timeout 00:03:59) [common]
506 07:32:32.570547 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
507 07:32:32.570735 Setting prompt string to []
508 07:32:32.570934 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
509 07:32:32.571082 Using line separator: #'\n'#
510 07:32:32.571154 No login prompt set.
511 07:32:32.571231 Parsing kernel messages
512 07:32:32.571300 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
513 07:32:32.571431 [login-action] Waiting for messages, (timeout 00:03:59)
514 07:32:32.571531 Waiting using forced prompt support (timeout 00:01:59)
515 07:32:32.590344 [ 0.000000] Linux version 6.11.0-next-20240919 (KernelCI@build-j314370-arm-clang-17-multi-v7-defconfig-d2kdg) (Debian clang version 17.0.6 (++20231208085813+6009708b4367-1~exp1~20231208085906.81), Debian LLD 17.0.6) #1 SMP Thu Sep 19 06:54:09 UTC 2024
516 07:32:32.596049 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
517 07:32:32.604861 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
518 07:32:32.610709 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
519 07:32:32.616446 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
520 07:32:32.622179 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
521 07:32:32.628823 [ 0.000000] Memory policy: Data cache writeback
522 07:32:32.629022 [ 0.000000] efi: UEFI not found.
523 07:32:32.637785 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
524 07:32:32.643440 [ 0.000000] Zone ranges:
525 07:32:32.649161 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
526 07:32:32.649358 [ 0.000000] Normal empty
527 07:32:32.654885 [ 0.000000] HighMem empty
528 07:32:32.660636 [ 0.000000] Movable zone start for each node
529 07:32:32.660831 [ 0.000000] Early memory node ranges
530 07:32:32.666284 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
531 07:32:32.675766 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
532 07:32:32.693377 [ 0.000000] CPU: All CPU(s) started in SVC mode.
533 07:32:32.699276 [ 0.000000] AM335X ES2.0 (sgx neon)
534 07:32:32.710931 [ 0.000000] percpu: Embedded 17 pages/cpu s40780 r8192 d20660 u69632
535 07:32:32.728606 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/742859/extract-nfsrootfs-tofrx_ks,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
536 07:32:32.740162 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
537 07:32:32.745929 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
538 07:32:32.751653 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
539 07:32:32.761830 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
540 07:32:32.791300 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
541 07:32:32.797183 <6>[ 0.000000] trace event string verifier disabled
542 07:32:32.797390 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
543 07:32:32.802864 <6>[ 0.000000] rcu: RCU event tracing is enabled.
544 07:32:32.814343 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
545 07:32:32.820086 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
546 07:32:32.827477 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
547 07:32:32.842563 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
548 07:32:32.860636 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
549 07:32:32.867392 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
550 07:32:32.970828 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
551 07:32:32.982316 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
552 07:32:32.989045 <6>[ 0.008339] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
553 07:32:33.002099 <6>[ 0.019227] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
554 07:32:33.009879 <6>[ 0.034456] Console: colour dummy device 80x30
555 07:32:33.015827 Matched prompt #6: WARNING:
556 07:32:33.016030 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
557 07:32:33.021402 <3>[ 0.039355] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
558 07:32:33.027146 <3>[ 0.046433] This ensures that you still see kernel messages. Please
559 07:32:33.030400 <3>[ 0.053163] update your kernel commandline.
560 07:32:33.070616 <6>[ 0.057776] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
561 07:32:33.076432 <6>[ 0.096236] CPU: Testing write buffer coherency: ok
562 07:32:33.082378 <6>[ 0.101604] CPU0: Spectre v2: using BPIALL workaround
563 07:32:33.082493 <6>[ 0.107070] pid_max: default: 32768 minimum: 301
564 07:32:33.093960 <6>[ 0.112266] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
565 07:32:33.100876 <6>[ 0.120088] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
566 07:32:33.107920 <6>[ 0.129559] CPU0: thread -1, cpu 0, socket -1, mpidr 0
567 07:32:33.115440 <6>[ 0.136504] Setting up static identity map for 0x80300000 - 0x803000ac
568 07:32:33.121858 <6>[ 0.146264] rcu: Hierarchical SRCU implementation.
569 07:32:33.128981 <6>[ 0.151552] rcu: Max phase no-delay instances is 1000.
570 07:32:33.138989 <6>[ 0.163138] EFI services will not be available.
571 07:32:33.144738 <6>[ 0.168428] smp: Bringing up secondary CPUs ...
572 07:32:33.150481 <6>[ 0.173487] smp: Brought up 1 node, 1 CPU
573 07:32:33.156379 <6>[ 0.177891] SMP: Total of 1 processors activated (996.14 BogoMIPS).
574 07:32:33.162215 <6>[ 0.184664] CPU: All CPU(s) started in SVC mode.
575 07:32:33.181639 <6>[ 0.189866] Memory: 404428K/522240K available (17408K kernel code, 2544K rwdata, 6696K rodata, 2048K init, 435K bss, 50620K reserved, 65536K cma-reserved, 0K highmem)
576 07:32:33.181865 <6>[ 0.206173] devtmpfs: initialized
577 07:32:33.205452 <6>[ 0.223864] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
578 07:32:33.216942 <6>[ 0.232477] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
579 07:32:33.222174 <6>[ 0.242943] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
580 07:32:33.233866 <6>[ 0.255286] pinctrl core: initialized pinctrl subsystem
581 07:32:33.243467 <6>[ 0.266318] DMI not present or invalid.
582 07:32:33.250769 <6>[ 0.272238] NET: Registered PF_NETLINK/PF_ROUTE protocol family
583 07:32:33.260687 <6>[ 0.281211] DMA: preallocated 256 KiB pool for atomic coherent allocations
584 07:32:33.276668 <6>[ 0.292922] thermal_sys: Registered thermal governor 'step_wise'
585 07:32:33.276883 <6>[ 0.293117] cpuidle: using governor menu
586 07:32:33.299390 <6>[ 0.323947] No ATAGs?
587 07:32:33.305566 <6>[ 0.326592] hw-breakpoint: debug architecture 0x4 unsupported.
588 07:32:33.315147 <6>[ 0.338878] Serial: AMBA PL011 UART driver
589 07:32:33.351300 <6>[ 0.375687] iommu: Default domain type: Translated
590 07:32:33.359572 <6>[ 0.381042] iommu: DMA domain TLB invalidation policy: strict mode
591 07:32:33.387184 <5>[ 0.410947] SCSI subsystem initialized
592 07:32:33.393048 <6>[ 0.415886] usbcore: registered new interface driver usbfs
593 07:32:33.398772 <6>[ 0.421964] usbcore: registered new interface driver hub
594 07:32:33.405682 <6>[ 0.427746] usbcore: registered new device driver usb
595 07:32:33.411650 <6>[ 0.434344] pps_core: LinuxPPS API ver. 1 registered
596 07:32:33.422950 <6>[ 0.439781] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
597 07:32:33.429262 <6>[ 0.449466] PTP clock support registered
598 07:32:33.429465 <6>[ 0.453954] EDAC MC: Ver: 3.0.0
599 07:32:33.481997 <6>[ 0.504973] scmi_core: SCMI protocol bus registered
600 07:32:33.498561 <6>[ 0.522156] vgaarb: loaded
601 07:32:33.504493 <6>[ 0.525956] clocksource: Switched to clocksource dmtimer
602 07:32:33.540977 <6>[ 0.565141] NET: Registered PF_INET protocol family
603 07:32:33.553715 <6>[ 0.570856] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
604 07:32:33.560764 <6>[ 0.579880] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
605 07:32:33.572178 <6>[ 0.588817] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
606 07:32:33.574991 <6>[ 0.597082] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
607 07:32:33.586507 <6>[ 0.605350] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
608 07:32:33.592413 <6>[ 0.613074] TCP: Hash tables configured (established 4096 bind 4096)
609 07:32:33.598212 <6>[ 0.619998] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
610 07:32:33.609790 <6>[ 0.627040] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
611 07:32:33.612861 <6>[ 0.634625] NET: Registered PF_UNIX/PF_LOCAL protocol family
612 07:32:33.695203 <6>[ 0.713942] RPC: Registered named UNIX socket transport module.
613 07:32:33.695431 <6>[ 0.720398] RPC: Registered udp transport module.
614 07:32:33.700866 <6>[ 0.725505] RPC: Registered tcp transport module.
615 07:32:33.706624 <6>[ 0.730627] RPC: Registered tcp-with-tls transport module.
616 07:32:33.719665 <6>[ 0.736553] RPC: Registered tcp NFSv4.1 backchannel transport module.
617 07:32:33.719880 <6>[ 0.743460] PCI: CLS 0 bytes, default 64
618 07:32:33.726090 <5>[ 0.749317] Initialise system trusted keyrings
619 07:32:33.747969 <6>[ 0.770392] Trying to unpack rootfs image as initramfs...
620 07:32:33.818982 <6>[ 0.837268] workingset: timestamp_bits=30 max_order=17 bucket_order=0
621 07:32:33.822865 <6>[ 0.844787] squashfs: version 4.0 (2009/01/31) Phillip Lougher
622 07:32:33.861938 <5>[ 0.886440] NFS: Registering the id_resolver key type
623 07:32:33.867800 <5>[ 0.892031] Key type id_resolver registered
624 07:32:33.873555 <5>[ 0.896713] Key type id_legacy registered
625 07:32:33.879721 <6>[ 0.901154] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
626 07:32:33.887980 <6>[ 0.908358] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
627 07:32:33.965332 <5>[ 0.989867] Key type asymmetric registered
628 07:32:33.971260 <5>[ 0.994395] Asymmetric key parser 'x509' registered
629 07:32:33.979600 <6>[ 0.999887] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
630 07:32:33.985328 <6>[ 1.007810] io scheduler mq-deadline registered
631 07:32:33.994116 <6>[ 1.012743] io scheduler kyber registered
632 07:32:33.994332 <6>[ 1.017224] io scheduler bfq registered
633 07:32:34.106844 <6>[ 1.128280] ledtrig-cpu: registered to indicate activity on CPUs
634 07:32:34.418639 <6>[ 1.439240] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
635 07:32:34.455879 <6>[ 1.480253] msm_serial: driver initialized
636 07:32:34.462015 <6>[ 1.485037] SuperH (H)SCI(F) driver initialized
637 07:32:34.468023 <6>[ 1.490395] STMicroelectronics ASC driver initialized
638 07:32:34.473201 <6>[ 1.496099] STM32 USART driver initialized
639 07:32:34.584653 <6>[ 1.608484] brd: module loaded
640 07:32:34.630115 <6>[ 1.653962] loop: module loaded
641 07:32:34.680371 <6>[ 1.703813] CAN device driver interface
642 07:32:34.686965 <6>[ 1.709145] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
643 07:32:34.692746 <6>[ 1.716254] e1000e: Intel(R) PRO/1000 Network Driver
644 07:32:34.698800 <6>[ 1.721640] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
645 07:32:34.704339 <6>[ 1.728108] igb: Intel(R) Gigabit Ethernet Network Driver
646 07:32:34.712683 <6>[ 1.733933] igb: Copyright (c) 2007-2014 Intel Corporation.
647 07:32:34.724569 <6>[ 1.743250] pegasus: Pegasus/Pegasus II USB Ethernet driver
648 07:32:34.730238 <6>[ 1.749415] usbcore: registered new interface driver pegasus
649 07:32:34.736031 <6>[ 1.755545] usbcore: registered new interface driver asix
650 07:32:34.741796 <6>[ 1.761428] usbcore: registered new interface driver ax88179_178a
651 07:32:34.747592 <6>[ 1.768024] usbcore: registered new interface driver cdc_ether
652 07:32:34.753388 <6>[ 1.774321] usbcore: registered new interface driver smsc75xx
653 07:32:34.759272 <6>[ 1.780561] usbcore: registered new interface driver smsc95xx
654 07:32:34.764963 <6>[ 1.786814] usbcore: registered new interface driver net1080
655 07:32:34.770695 <6>[ 1.792946] usbcore: registered new interface driver cdc_subset
656 07:32:34.776577 <6>[ 1.799363] usbcore: registered new interface driver zaurus
657 07:32:34.784149 <6>[ 1.805406] usbcore: registered new interface driver cdc_ncm
658 07:32:34.793236 <6>[ 1.815032] usbcore: registered new interface driver usb-storage
659 07:32:35.079445 <6>[ 2.102118] i2c_dev: i2c /dev entries driver
660 07:32:35.122221 <5>[ 2.143283] cpuidle: enable-method property 'ti,am3352' found operations
661 07:32:35.136248 <6>[ 2.153036] sdhci: Secure Digital Host Controller Interface driver
662 07:32:35.136526 <6>[ 2.159821] sdhci: Copyright(c) Pierre Ossman
663 07:32:35.149153 <6>[ 2.166524] Synopsys Designware Multimedia Card Interface Driver
664 07:32:35.153165 <6>[ 2.174465] sdhci-pltfm: SDHCI platform and OF driver helper
665 07:32:35.280072 <6>[ 2.297166] usbcore: registered new interface driver usbhid
666 07:32:35.280341 <6>[ 2.303211] usbhid: USB HID core driver
667 07:32:35.340933 <6>[ 2.362863] NET: Registered PF_INET6 protocol family
668 07:32:35.369075 <6>[ 2.393517] Segment Routing with IPv6
669 07:32:35.374912 <6>[ 2.397795] In-situ OAM (IOAM) with IPv6
670 07:32:35.381659 <6>[ 2.402208] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
671 07:32:35.387381 <6>[ 2.409570] NET: Registered PF_PACKET protocol family
672 07:32:35.393315 <6>[ 2.415058] can: controller area network core
673 07:32:35.399070 <6>[ 2.419965] NET: Registered PF_CAN protocol family
674 07:32:35.399310 <6>[ 2.425171] can: raw protocol
675 07:32:35.404814 <6>[ 2.428528] can: broadcast manager protocol
676 07:32:35.411345 <6>[ 2.433108] can: netlink gateway - max_hops=1
677 07:32:35.417419 <5>[ 2.438635] Key type dns_resolver registered
678 07:32:35.423804 <6>[ 2.443624] ThumbEE CPU extension supported.
679 07:32:35.424090 <5>[ 2.448442] Registering SWP/SWPB emulation handler
680 07:32:35.433606 <3>[ 2.454101] omap_voltage_late_init: Voltage driver support not added
681 07:32:35.630627 <5>[ 2.653676] Loading compiled-in X.509 certificates
682 07:32:35.763972 <6>[ 2.775487] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
683 07:32:35.771157 <6>[ 2.792261] pinctrl-single 44e10800.pinmux: 142 pins, size 568
684 07:32:35.798341 <3>[ 2.816854] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
685 07:32:36.000695 <3>[ 3.019111] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
686 07:32:36.194068 <6>[ 3.216902] OMAP GPIO hardware version 0.1
687 07:32:36.215555 <6>[ 3.236233] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
688 07:32:36.307155 <4>[ 3.327681] at24 2-0054: supply vcc not found, using dummy regulator
689 07:32:36.341216 <4>[ 3.361757] at24 2-0055: supply vcc not found, using dummy regulator
690 07:32:36.378554 <4>[ 3.399693] at24 2-0056: supply vcc not found, using dummy regulator
691 07:32:36.421170 <4>[ 3.441745] at24 2-0057: supply vcc not found, using dummy regulator
692 07:32:36.457959 <6>[ 3.479300] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
693 07:32:36.516011 <3>[ 3.533318] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
694 07:32:36.540916 <6>[ 3.554582] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
695 07:32:36.562542 <4>[ 3.581850] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
696 07:32:36.576720 <4>[ 3.597002] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
697 07:32:36.665579 <6>[ 3.686344] omap_rng 48310000.rng: Random Number Generator ver. 20
698 07:32:36.689909 <5>[ 3.713377] random: crng init done
699 07:32:36.718211 <6>[ 3.740973] Freeing initrd memory: 14988K
700 07:32:36.736774 <6>[ 3.755969] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
701 07:32:36.790063 <6>[ 3.808396] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
702 07:32:36.795915 <4>[ 3.818729] ------------[ cut here ]------------
703 07:32:36.803885 <4>[ 3.823765] WARNING: CPU: 0 PID: 38 at drivers/base/regmap/regmap.c:1208 devm_regmap_field_alloc+0x9c/0xa0
704 07:32:36.809804 <4>[ 3.834069] invalid empty mask defined
705 07:32:36.815362 <4>[ 3.838213] Modules linked in:
706 07:32:36.821126 <4>[ 3.841636] CPU: 0 UID: 0 PID: 38 Comm: kworker/u4:4 Not tainted 6.11.0-next-20240919 #1
707 07:32:36.826883 <4>[ 3.850234] Hardware name: Generic AM33XX (Flattened Device Tree)
708 07:32:36.832651 <4>[ 3.856773] Workqueue: events_unbound deferred_probe_work_func
709 07:32:36.838350 <4>[ 3.863059] Call trace:
710 07:32:36.844105 <4>[ 3.863079] unwind_backtrace from show_stack+0x10/0x14
711 07:32:36.849902 <4>[ 3.871609] show_stack from dump_stack_lvl+0x34/0x70
712 07:32:36.855706 <4>[ 3.877090] dump_stack_lvl from __warn+0xd8/0x20c
713 07:32:36.861335 <4>[ 3.882304] __warn from warn_slowpath_fmt+0xb4/0x168
714 07:32:36.867085 <4>[ 3.887777] warn_slowpath_fmt from devm_regmap_field_alloc+0x9c/0xa0
715 07:32:36.872938 <4>[ 3.894682] devm_regmap_field_alloc from cpsw_ale_create+0x1f4/0x408
716 07:32:36.878624 <4>[ 3.901588] cpsw_ale_create from cpsw_init_common+0x204/0x374
717 07:32:36.884328 <4>[ 3.907861] cpsw_init_common from cpsw_probe+0x558/0x940
718 07:32:36.890028 <4>[ 3.913694] cpsw_probe from platform_probe+0x98/0xc0
719 07:32:36.895893 <4>[ 3.919170] platform_probe from really_probe+0xd4/0x30c
720 07:32:36.901642 <4>[ 3.924911] really_probe from __driver_probe_device+0x90/0x188
721 07:32:36.912987 <4>[ 3.931277] __driver_probe_device from driver_probe_device+0x3c/0x198
722 07:32:36.918749 <4>[ 3.938268] driver_probe_device from __device_attach_driver+0x11c/0x12c
723 07:32:36.924448 <4>[ 3.945436] __device_attach_driver from bus_for_each_drv+0x118/0x164
724 07:32:36.930418 <4>[ 3.952338] bus_for_each_drv from __device_attach+0xc8/0x184
725 07:32:36.936004 <4>[ 3.958522] __device_attach from bus_probe_device+0xac/0x100
726 07:32:36.941735 <4>[ 3.964705] bus_probe_device from device_add+0x290/0x48c
727 07:32:36.947439 <4>[ 3.970544] device_add from of_platform_device_create_pdata+0xc4/0xf4
728 07:32:36.958934 <4>[ 3.977542] of_platform_device_create_pdata from of_platform_bus_create+0x16c/0x360
729 07:32:36.964677 <4>[ 3.985781] of_platform_bus_create from of_platform_populate+0x7c/0xc0
730 07:32:36.970538 <4>[ 3.992857] of_platform_populate from sysc_probe+0xb34/0xc8c
731 07:32:36.976105 <4>[ 3.999050] sysc_probe from platform_probe+0x98/0xc0
732 07:32:36.981901 <4>[ 4.004522] platform_probe from really_probe+0xd4/0x30c
733 07:32:36.987654 <4>[ 4.010263] really_probe from __driver_probe_device+0x90/0x188
734 07:32:36.993344 <4>[ 4.016628] __driver_probe_device from driver_probe_device+0x3c/0x198
735 07:32:37.004987 <4>[ 4.023615] driver_probe_device from __device_attach_driver+0x11c/0x12c
736 07:32:37.010479 <4>[ 4.030782] __device_attach_driver from bus_for_each_drv+0x118/0x164
737 07:32:37.016240 <4>[ 4.037682] bus_for_each_drv from __device_attach+0xc8/0x184
738 07:32:37.022005 <4>[ 4.043868] __device_attach from bus_probe_device+0xac/0x100
739 07:32:37.027772 <4>[ 4.050053] bus_probe_device from device_add+0x290/0x48c
740 07:32:37.033487 <4>[ 4.055883] device_add from of_platform_device_create_pdata+0xc4/0xf4
741 07:32:37.044894 <4>[ 4.062874] of_platform_device_create_pdata from of_platform_bus_create+0x16c/0x360
742 07:32:37.050630 <4>[ 4.071117] of_platform_bus_create from of_platform_populate+0x7c/0xc0
743 07:32:37.056370 <4>[ 4.078194] of_platform_populate from simple_pm_bus_probe+0xac/0xfc
744 07:32:37.062140 <4>[ 4.085007] simple_pm_bus_probe from platform_probe+0x98/0xc0
745 07:32:37.067891 <4>[ 4.091285] platform_probe from really_probe+0xd4/0x30c
746 07:32:37.073587 <4>[ 4.097025] really_probe from __driver_probe_device+0x90/0x188
747 07:32:37.085070 <4>[ 4.103388] __driver_probe_device from driver_probe_device+0x3c/0x198
748 07:32:37.090880 <4>[ 4.110380] driver_probe_device from __device_attach_driver+0x11c/0x12c
749 07:32:37.096576 <4>[ 4.117548] __device_attach_driver from bus_for_each_drv+0x118/0x164
750 07:32:37.102272 <4>[ 4.124449] bus_for_each_drv from __device_attach+0xc8/0x184
751 07:32:37.108050 <4>[ 4.130633] __device_attach from bus_probe_device+0xac/0x100
752 07:32:37.113779 <4>[ 4.136817] bus_probe_device from device_add+0x290/0x48c
753 07:32:37.119466 <4>[ 4.142648] device_add from of_platform_device_create_pdata+0xc4/0xf4
754 07:32:37.130997 <4>[ 4.149637] of_platform_device_create_pdata from of_platform_bus_create+0x16c/0x360
755 07:32:37.136737 <4>[ 4.157876] of_platform_bus_create from of_platform_populate+0x7c/0xc0
756 07:32:37.142840 <4>[ 4.164952] of_platform_populate from simple_pm_bus_probe+0xac/0xfc
757 07:32:37.148208 <4>[ 4.171762] simple_pm_bus_probe from platform_probe+0x98/0xc0
758 07:32:37.153852 <4>[ 4.178039] platform_probe from really_probe+0xd4/0x30c
759 07:32:37.159674 <4>[ 4.183779] really_probe from __driver_probe_device+0x90/0x188
760 07:32:37.171074 <4>[ 4.190142] __driver_probe_device from driver_probe_device+0x3c/0x198
761 07:32:37.176893 <4>[ 4.197129] driver_probe_device from __device_attach_driver+0x11c/0x12c
762 07:32:37.182549 <4>[ 4.204299] __device_attach_driver from bus_for_each_drv+0x118/0x164
763 07:32:37.188242 <4>[ 4.211196] bus_for_each_drv from __device_attach+0xc8/0x184
764 07:32:37.194029 <4>[ 4.217380] __device_attach from bus_probe_device+0xac/0x100
765 07:32:37.199908 <4>[ 4.223563] bus_probe_device from device_add+0x290/0x48c
766 07:32:37.211189 <4>[ 4.229391] device_add from of_platform_device_create_pdata+0xc4/0xf4
767 07:32:37.216960 <4>[ 4.236382] of_platform_device_create_pdata from of_platform_bus_create+0x16c/0x360
768 07:32:37.222841 <4>[ 4.244623] of_platform_bus_create from of_platform_populate+0x7c/0xc0
769 07:32:37.228430 <4>[ 4.251700] of_platform_populate from simple_pm_bus_probe+0xac/0xfc
770 07:32:37.239912 <4>[ 4.258511] simple_pm_bus_probe from platform_probe+0x98/0xc0
771 07:32:37.245625 <4>[ 4.264788] platform_probe from really_probe+0xd4/0x30c
772 07:32:37.251335 <4>[ 4.270527] really_probe from __driver_probe_device+0x90/0x188
773 07:32:37.257378 <4>[ 4.276892] __driver_probe_device from driver_probe_device+0x3c/0x198
774 07:32:37.262867 <4>[ 4.283880] driver_probe_device from __device_attach_driver+0x11c/0x12c
775 07:32:37.268593 <4>[ 4.291047] __device_attach_driver from bus_for_each_drv+0x118/0x164
776 07:32:37.274331 <4>[ 4.297948] bus_for_each_drv from __device_attach+0xc8/0x184
777 07:32:37.280148 <4>[ 4.304133] __device_attach from bus_probe_device+0xac/0x100
778 07:32:37.291596 <4>[ 4.310316] bus_probe_device from deferred_probe_work_func+0x7c/0xa8
779 07:32:37.297303 <4>[ 4.317216] deferred_probe_work_func from process_scheduled_works+0x25c/0x430
780 07:32:37.303057 <4>[ 4.324935] process_scheduled_works from worker_thread+0x340/0x438
781 07:32:37.308788 <4>[ 4.331659] worker_thread from kthread+0x11c/0x13c
782 07:32:37.314589 <4>[ 4.336958] kthread from ret_from_fork+0x14/0x28
783 07:32:37.320262 <4>[ 4.342072] Exception stack(0xe0131fb0 to 0xe0131ff8)
784 07:32:37.326034 <4>[ 4.347537] 1fa0: 00000000 00000000 00000000 00000000
785 07:32:37.337421 <4>[ 4.356219] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
786 07:32:37.343303 <4>[ 4.364900] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000
787 07:32:37.349190 <4>[ 4.372097] ---[ end trace 0000000000000000 ]---
788 07:32:37.349742 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
789 07:32:37.349907 login-action: kernel 'warning'
790 07:32:37.350053 [login-action] Waiting for messages, (timeout 00:03:54)
791 07:32:37.350176 Waiting using forced prompt support (timeout 00:01:57)
792 07:32:37.355055 <6>[ 4.377222] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
793 07:32:37.366756 <6>[ 4.384483] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
794 07:32:37.372619 <6>[ 4.392098] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
795 07:32:37.384175 <6>[ 4.400244] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
796 07:32:37.391743 <6>[ 4.411883] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5c:d5:d8
797 07:32:37.404168 <5>[ 4.421040] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
798 07:32:37.432803 <3>[ 4.451631] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
799 07:32:37.438648 <6>[ 4.460222] edma 49000000.dma: TI EDMA DMA engine driver
800 07:32:37.512052 <3>[ 4.530145] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
801 07:32:37.526899 <6>[ 4.544743] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
802 07:32:37.540085 <3>[ 4.562095] l3-aon-clkctrl:0000:0: failed to disable
803 07:32:37.596036 <6>[ 4.614797] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
804 07:32:37.601771 <6>[ 4.624310] printk: legacy console [ttyS0] enabled
805 07:32:37.604442 <6>[ 4.624310] printk: legacy console [ttyS0] enabled
806 07:32:37.610158 <6>[ 4.634647] printk: legacy bootconsole [omap8250] disabled
807 07:32:37.618904 <6>[ 4.634647] printk: legacy bootconsole [omap8250] disabled
808 07:32:37.649019 <4>[ 4.666803] tps65217-pmic: Failed to locate of_node [id: -1]
809 07:32:37.652643 <4>[ 4.674234] tps65217-bl: Failed to locate of_node [id: -1]
810 07:32:37.669803 <6>[ 4.694496] tps65217 0-0024: TPS65217 ID 0xe version 1.2
811 07:32:37.688268 <6>[ 4.701519] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
812 07:32:37.700077 <6>[ 4.715221] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
813 07:32:37.705750 <6>[ 4.727166] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
814 07:32:37.728797 <6>[ 4.747733] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
815 07:32:37.734626 <6>[ 4.756970] sdhci-omap 48060000.mmc: Got CD GPIO
816 07:32:37.742630 <4>[ 4.762103] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
817 07:32:37.757736 <4>[ 4.776052] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
818 07:32:37.765441 <4>[ 4.784650] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
819 07:32:37.800124 <4>[ 4.819537] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
820 07:32:37.848375 <6>[ 4.868582] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
821 07:32:37.910208 <6>[ 4.929519] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
822 07:32:37.930843 <6>[ 4.949225] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
823 07:32:37.937525 <6>[ 4.958164] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
824 07:32:37.980411 <6>[ 4.995024] mmc0: new high speed SDHC card at address 0001
825 07:32:37.980670 <6>[ 5.003124] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
826 07:32:37.987568 <6>[ 5.012062] mmcblk0: p1
827 07:32:38.020718 <6>[ 5.037227] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
828 07:32:38.041687 <6>[ 5.057117] mmc1: new high speed MMC card at address 0001
829 07:32:38.041978 <6>[ 5.064354] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
830 07:32:38.050110 <6>[ 5.074158] mmcblk1:
831 07:32:38.058167 <6>[ 5.077463] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
832 07:32:38.063776 <6>[ 5.085072] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
833 07:32:38.071682 <6>[ 5.092611] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
834 07:32:40.138135 <6>[ 7.157037] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
835 07:32:48.451428 <5>[ 7.185971] Sending DHCP requests ..., OK
836 07:32:48.462882 <6>[ 15.480779] IP-Config: Got DHCP answer from 192.168.56.254, my address is 192.168.56.9
837 07:32:48.463162 <6>[ 15.489230] IP-Config: Complete:
838 07:32:48.474142 <6>[ 15.492767] device=eth0, hwaddr=90:59:af:5c:d5:d8, ipaddr=192.168.56.9, mask=255.255.255.0, gw=192.168.56.254
839 07:32:48.485318 <6>[ 15.503554] host=192.168.56.9, domain=mayfield.sirena.org.uk, nis-domain=(none)
840 07:32:48.491027 <6>[ 15.511685] bootserver=192.168.56.254, rootserver=192.168.56.76, rootpath=
841 07:32:48.496741 <6>[ 15.511723] nameserver0=192.168.56.254
842 07:32:48.503534 <6>[ 15.523904] ntpserver0=50.205.244.22, ntpserver1=85.199.214.99
843 07:32:48.509541 <6>[ 15.531672] clk: Disabling unused clocks
844 07:32:48.514127 <6>[ 15.536421] PM: genpd: Disabling unused power domains
845 07:32:48.532303 <6>[ 15.553703] Freeing unused kernel image (initmem) memory: 2048K
846 07:32:48.539907 <6>[ 15.563667] Run /init as init process
847 07:32:48.563946 Loading, please wait...
848 07:32:48.641007 Starting systemd-udevd version 252.22-1~deb12u1
849 07:32:51.892662 <4>[ 18.911108] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
850 07:32:52.078085 <4>[ 19.096793] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
851 07:32:52.169615 <6>[ 19.193932] tda998x 0-0070: found TDA19988
852 07:32:52.225311 <6>[ 19.250587] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
853 07:32:52.235232 <6>[ 19.256406] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
854 07:32:52.539377 <6>[ 19.563327] hub 1-0:1.0: USB hub found
855 07:32:52.584654 <6>[ 19.608187] hub 1-0:1.0: 1 port detected
856 07:32:55.268169 Begin: Loading essential drivers ... done.
857 07:32:55.273674 Begin: Running /scripts/init-premount ... done.
858 07:32:55.279402 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
859 07:32:55.286989 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
860 07:32:55.293121 Device /sys/class/net/eth0 found
861 07:32:55.293413 done.
862 07:32:55.388777 Begin: Waiting up to 180 secs for any network device to become available ... done.
863 07:32:55.473826 IP-Config: eth0 hardware address 90:59:af:5c:d5:d8 mtu 1500 DHCP
864 07:32:55.551410 IP-Config: eth0 complete (dhcp from 192.168.56.254):
865 07:32:55.562576 address: 192.168.56.9 broadcast: 192.168.56.255 netmask: 255.255.255.0
866 07:32:55.565948 gateway: 192.168.56.254 dns0 : 192.168.56.254 dns1 : 0.0.0.0
867 07:32:55.579571 domain : mayfield.sirena.org.uk
868 07:32:55.579775 rootserver: 192.168.56.254 rootpath:
869 07:32:55.579859 filename :
870 07:32:55.676784 done.
871 07:32:55.693620 Begin: Running /scripts/nfs-bottom ... done.
872 07:32:55.760742 Begin: Running /scripts/init-bottom ... done.
873 07:32:57.222801 <30>[ 24.243696] systemd[1]: System time before build time, advancing clock.
874 07:32:57.406290 <30>[ 24.401065] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
875 07:32:57.414991 <30>[ 24.437830] systemd[1]: Detected architecture arm.
876 07:32:57.427024
877 07:32:57.427265 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
878 07:32:57.427399
879 07:32:57.455771 <30>[ 24.477200] systemd[1]: Hostname set to <debian-bookworm-armhf>.
880 07:32:59.661041 <30>[ 26.681557] systemd[1]: Queued start job for default target graphical.target.
881 07:32:59.677934 <30>[ 26.696668] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
882 07:32:59.685424 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
883 07:32:59.710801 <30>[ 26.729456] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
884 07:32:59.719200 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
885 07:32:59.740319 <30>[ 26.759064] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
886 07:32:59.748573 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
887 07:32:59.769172 <30>[ 26.787970] systemd[1]: Created slice user.slice - User and Session Slice.
888 07:32:59.775716 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
889 07:32:59.804058 <30>[ 26.817343] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
890 07:32:59.810200 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
891 07:32:59.828103 <30>[ 26.847110] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
892 07:32:59.839201 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
893 07:32:59.868863 <30>[ 26.876987] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
894 07:32:59.875218 <30>[ 26.897452] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
895 07:32:59.883772 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
896 07:32:59.907084 <30>[ 26.926439] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
897 07:32:59.915313 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
898 07:32:59.937791 <30>[ 26.956778] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
899 07:32:59.946213 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
900 07:32:59.967527 <30>[ 26.986820] systemd[1]: Reached target paths.target - Path Units.
901 07:32:59.972625 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
902 07:32:59.997307 <30>[ 27.016601] systemd[1]: Reached target remote-fs.target - Remote File Systems.
903 07:33:00.004669 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
904 07:33:00.027218 <30>[ 27.046536] systemd[1]: Reached target slices.target - Slice Units.
905 07:33:00.032641 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
906 07:33:00.057468 <30>[ 27.076771] systemd[1]: Reached target swap.target - Swaps.
907 07:33:00.061496 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
908 07:33:00.087868 <30>[ 27.106769] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
909 07:33:00.096665 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
910 07:33:00.118636 <30>[ 27.137576] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
911 07:33:00.126398 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
912 07:33:00.217165 <30>[ 27.231329] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
913 07:33:00.230300 <30>[ 27.249149] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
914 07:33:00.238411 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
915 07:33:00.259213 <30>[ 27.277808] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
916 07:33:00.265595 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
917 07:33:00.292138 <30>[ 27.309338] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
918 07:33:00.301428 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
919 07:33:00.334395 <30>[ 27.354041] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
920 07:33:00.348004 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
921 07:33:00.369254 <30>[ 27.387994] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
922 07:33:00.377723 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
923 07:33:00.405006 <30>[ 27.417786] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
924 07:33:00.421648 <30>[ 27.434505] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
925 07:33:00.472248 <30>[ 27.492143] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
926 07:33:00.498840 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
927 07:33:00.549453 <30>[ 27.569247] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
928 07:33:00.565406 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
929 07:33:00.630513 <30>[ 27.649353] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
930 07:33:00.649089 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
931 07:33:00.698124 <30>[ 27.717902] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
932 07:33:00.721054 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
933 07:33:00.778123 <30>[ 27.797904] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
934 07:33:00.797218 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
935 07:33:00.819625 <30>[ 27.840266] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
936 07:33:00.844061 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
937 07:33:00.890577 <30>[ 27.909679] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
938 07:33:00.908385 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
939 07:33:00.967286 <30>[ 27.987276] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
940 07:33:00.983588 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
941 07:33:01.047415 <30>[ 28.067127] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
942 07:33:01.066505 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
943 07:33:01.094121 <28>[ 28.108436] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
944 07:33:01.106635 <28>[ 28.125571] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
945 07:33:01.149408 <30>[ 28.169559] systemd[1]: Starting systemd-journald.service - Journal Service...
946 07:33:01.166321 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
947 07:33:01.237621 <30>[ 28.257343] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
948 07:33:01.256648 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
949 07:33:01.309691 <30>[ 28.329383] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
950 07:33:01.353044 Starting [0;1;39msystemd-network-g… units from Kernel command line...
951 07:33:01.413509 <30>[ 28.431968] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
952 07:33:01.476382 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
953 07:33:01.544269 <30>[ 28.564616] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
954 07:33:01.610540 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
955 07:33:01.701273 <30>[ 28.692404] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
956 07:33:01.709759 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
957 07:33:01.716034 <30>[ 28.738171] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
958 07:33:01.757412 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
959 07:33:01.779666 <30>[ 28.798740] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
960 07:33:01.809909 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
961 07:33:01.997603 <30>[ 29.018574] systemd[1]: modprobe@configfs.service: Deactivated successfully.
962 07:33:02.028177 <30>[ 29.047938] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
963 07:33:02.057547 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
964 07:33:02.078680 <30>[ 29.097769] systemd[1]: Started systemd-journald.service - Journal Service.
965 07:33:02.085209 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
966 07:33:02.113697 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
967 07:33:02.137546 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
968 07:33:02.168784 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
969 07:33:02.192281 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
970 07:33:02.228553 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
971 07:33:02.257525 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
972 07:33:02.279582 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
973 07:33:02.300568 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
974 07:33:02.331535 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
975 07:33:02.400702 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
976 07:33:02.437988 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
977 07:33:02.510741 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
978 07:33:02.597745 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
979 07:33:02.658823 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
980 07:33:02.808213 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
981 07:33:02.845178 <46>[ 29.865308] systemd-journald[163]: Received client request to flush runtime journal.
982 07:33:02.955427 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
983 07:33:03.375036 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
984 07:33:04.202536 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
985 07:33:04.289442 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
986 07:33:04.610938 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
987 07:33:04.870487 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
988 07:33:04.898511 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
989 07:33:04.917132 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
990 07:33:04.997874 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
991 07:33:05.044554 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
992 07:33:06.048687 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
993 07:33:06.114130 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
994 07:33:06.260189 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
995 07:33:06.347422 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
996 07:33:06.391555 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
997 07:33:07.239972 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
998 07:33:08.569440 <5>[ 35.589931] cfg80211: Loading compiled-in X.509 certificates for regulatory database
999 07:33:09.368632 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1000 07:33:09.966278 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
1001 07:33:10.318359 <5>[ 37.340874] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1002 07:33:10.451250 <5>[ 37.472195] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1003 07:33:10.464068 <4>[ 37.484252] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1004 07:33:10.469946 <6>[ 37.493390] cfg80211: failed to load regulatory.db
1005 07:33:11.007051 <46>[ 38.018345] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1006 07:33:11.035073 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1007 07:33:11.152379 <46>[ 38.166888] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
1008 07:33:11.482929 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1009 07:33:20.710404 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1010 07:33:20.742898 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1011 07:33:20.769105 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1012 07:33:20.789333 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1013 07:33:20.847146 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1014 07:33:20.899293 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1015 07:33:20.960596 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1016 07:33:20.998240 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1017 07:33:21.055638 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1018 07:33:21.082447 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1019 07:33:21.111964 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1020 07:33:21.152995 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1021 07:33:21.180671 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1022 07:33:21.239731 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1023 07:33:21.296598 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1024 07:33:21.318515 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1025 07:33:21.347316 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1026 07:33:21.376710 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1027 07:33:21.404400 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1028 07:33:21.427370 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1029 07:33:21.458554 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1030 07:33:21.476541 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1031 07:33:21.500034 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1032 07:33:21.577427 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1033 07:33:21.623375 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1034 07:33:21.732200 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1035 07:33:21.820108 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1036 07:33:21.906579 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1037 07:33:21.921771 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1038 07:33:21.954592 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1039 07:33:22.197425 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1040 07:33:22.247242 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1041 07:33:22.298107 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1042 07:33:22.316166 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1043 07:33:22.346698 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1044 07:33:22.523560 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
1045 07:33:22.696996 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1046 07:33:23.133851 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
1047 07:33:23.391288 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1048 07:33:23.443695 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1049 07:33:23.470650 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1050 07:33:23.562571 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1051 07:33:23.736382 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1052 07:33:23.885347
1053 07:33:23.887688 Debian GNU/Linux 12 worm-armhf login: root (automatic login)
1054 07:33:23.887876
1055 07:33:24.191251 Linux debian-bookworm-armhf 6.11.0-next-20240919 #1 SMP Thu Sep 19 06:54:09 UTC 2024 armv7l
1056 07:33:24.191505
1057 07:33:24.196680 The programs included with the Debian GNU/Linux system are free software;
1058 07:33:24.202298 the exact distribution terms for each program are described in the
1059 07:33:24.207895 individual files in /usr/share/doc/*/copyright.
1060 07:33:24.208096
1061 07:33:24.213510 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1062 07:33:24.216840 permitted by applicable law.
1063 07:33:28.896175 Matched prompt #10: / #
1065 07:33:28.897133 Kernel warnings or errors detected.
1066 07:33:28.897263 Setting prompt string to ['/ #']
1067 07:33:28.897439 end: 2.4.4.1 login-action (duration 00:00:56) [common]
1069 07:33:28.898194 end: 2.4.4 auto-login-action (duration 00:00:57) [common]
1070 07:33:28.898386 start: 2.4.5 expect-shell-connection (timeout 00:03:02) [common]
1071 07:33:28.898533 Setting prompt string to ['/ #']
1072 07:33:28.898660 Forcing a shell prompt, looking for ['/ #']
1074 07:33:28.949049 / #
1075 07:33:28.949381 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1076 07:33:28.949537 Waiting using forced prompt support (timeout 00:02:30)
1077 07:33:28.953673
1078 07:33:28.964456 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1079 07:33:28.964681 start: 2.4.6 export-device-env (timeout 00:03:02) [common]
1080 07:33:28.964836 Sending with 10 millisecond of delay
1082 07:33:33.952993 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/742859/extract-nfsrootfs-tofrx_ks'
1083 07:33:33.963503 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/742859/extract-nfsrootfs-tofrx_ks'
1084 07:33:33.964909 Sending with 10 millisecond of delay
1086 07:33:36.182882 / # export NFS_SERVER_IP='192.168.56.76'
1087 07:33:36.193346 export NFS_SERVER_IP='192.168.56.76'
1088 07:33:36.201439 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1089 07:33:36.201690 end: 2.4 uboot-commands (duration 00:02:05) [common]
1090 07:33:36.201890 end: 2 uboot-action (duration 00:02:05) [common]
1091 07:33:36.202069 start: 3 lava-test-retry (timeout 00:07:24) [common]
1092 07:33:36.202254 start: 3.1 lava-test-shell (timeout 00:07:24) [common]
1093 07:33:36.202402 Using namespace: common
1095 07:33:36.302932 / # #
1096 07:33:36.303306 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1097 07:33:36.308327 #
1098 07:33:36.315374 Using /lava-742859
1100 07:33:36.416005 / # export SHELL=/bin/bash
1101 07:33:36.421393 export SHELL=/bin/bash
1103 07:33:36.528262 / # . /lava-742859/environment
1104 07:33:36.533448 . /lava-742859/environment
1106 07:33:36.646588 / # /lava-742859/bin/lava-test-runner /lava-742859/0
1107 07:33:36.646923 Test shell timeout: 10s (minimum of the action and connection timeout)
1108 07:33:36.651637 /lava-742859/bin/lava-test-runner /lava-742859/0
1109 07:33:37.073973 + export TESTRUN_ID=0_timesync-off
1110 07:33:37.081788 + TESTRUN_ID=0_timesync-off
1111 07:33:37.081980 + cd /lava-742859/0/tests/0_timesync-off
1112 07:33:37.082131 ++ cat uuid
1113 07:33:37.098406 + UUID=742859_1.6.2.4.1
1114 07:33:37.098593 + set +x
1115 07:33:37.106866 <LAVA_SIGNAL_STARTRUN 0_timesync-off 742859_1.6.2.4.1>
1116 07:33:37.107047 + systemctl stop systemd-timesyncd
1117 07:33:37.107421 Received signal: <STARTRUN> 0_timesync-off 742859_1.6.2.4.1
1118 07:33:37.107587 Starting test lava.0_timesync-off (742859_1.6.2.4.1)
1119 07:33:37.107770 Skipping test definition patterns.
1120 07:33:37.444564 + set +x
1121 07:33:37.444808 <LAVA_SIGNAL_ENDRUN 0_timesync-off 742859_1.6.2.4.1>
1122 07:33:37.445144 Received signal: <ENDRUN> 0_timesync-off 742859_1.6.2.4.1
1123 07:33:37.445301 Ending use of test pattern.
1124 07:33:37.445424 Ending test lava.0_timesync-off (742859_1.6.2.4.1), duration 0.34
1126 07:33:37.588828 + export TESTRUN_ID=1_kselftest-dt
1127 07:33:37.596778 + TESTRUN_ID=1_kselftest-dt
1128 07:33:37.596975 + cd /lava-742859/0/tests/1_kselftest-dt
1129 07:33:37.597114 ++ cat uuid
1130 07:33:37.613611 + UUID=742859_1.6.2.4.5
1131 07:33:37.613808 + set +x
1132 07:33:37.618968 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 742859_1.6.2.4.5>
1133 07:33:37.619161 + cd ./automated/linux/kselftest/
1134 07:33:37.619521 Received signal: <STARTRUN> 1_kselftest-dt 742859_1.6.2.4.5
1135 07:33:37.619665 Starting test lava.1_kselftest-dt (742859_1.6.2.4.5)
1136 07:33:37.619820 Skipping test definition patterns.
1137 07:33:37.645511 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1138 07:33:37.787934 INFO: install_deps skipped
1139 07:33:38.391827 --2024-09-19 07:33:38-- http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz
1140 07:33:38.412716 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1141 07:33:38.572336 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1142 07:33:38.731399 HTTP request sent, awaiting response... 200 OK
1143 07:33:38.731718 Length: 2744336 (2.6M) [application/octet-stream]
1144 07:33:38.736941 Saving to: 'kselftest_armhf.tar.gz'
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1148 07:33:40.565979 2024-09-19 07:33:40 (1.80 MB/s) - 'kselftest_armhf.tar.gz' saved [2744336/2744336]
1149 07:33:40.566228
1150 07:33:57.322467 skiplist:
1151 07:33:57.322748 ========================================
1152 07:33:57.327286 ========================================
1153 07:33:57.432556 dt:test_unprobed_devices.sh
1154 07:33:57.462340 ============== Tests to run ===============
1155 07:33:57.470002 dt:test_unprobed_devices.sh
1156 07:33:57.474025 ===========End Tests to run ===============
1157 07:33:57.483849 shardfile-dt pass
1158 07:33:57.728061 <12>[ 84.753775] kselftest: Running tests in dt
1159 07:33:57.756138 TAP version 13
1160 07:33:57.783043 1..1
1161 07:33:57.837061 # timeout set to 45
1162 07:33:57.837346 # selftests: dt: test_unprobed_devices.sh
1163 07:33:58.628424 # TAP version 13
1164 07:34:24.236121 # 1..257
1165 07:34:24.427718 # ok 1 / # SKIP
1166 07:34:24.451876 # ok 2 /clk_mcasp0
1167 07:34:24.535295 # ok 3 /clk_mcasp0_fixed # SKIP
1168 07:34:24.606227 # ok 4 /cpus/cpu@0 # SKIP
1169 07:34:24.687173 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1170 07:34:24.713275 # ok 6 /fixedregulator0
1171 07:34:24.731190 # ok 7 /leds
1172 07:34:24.757206 # ok 8 /ocp
1173 07:34:24.780113 # ok 9 /ocp/interconnect@44c00000
1174 07:34:24.806638 # ok 10 /ocp/interconnect@44c00000/segment@0
1175 07:34:24.831935 # ok 11 /ocp/interconnect@44c00000/segment@100000
1176 07:34:24.861717 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1177 07:34:24.937375 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1178 07:34:24.959356 # ok 14 /ocp/interconnect@44c00000/segment@200000
1179 07:34:24.985704 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1180 07:34:25.112585 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1181 07:34:25.198566 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1182 07:34:25.279978 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1183 07:34:25.359817 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1184 07:34:25.440793 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1185 07:34:25.518349 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1186 07:34:25.598169 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1187 07:34:25.676182 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1188 07:34:25.759574 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1189 07:34:25.839982 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1190 07:34:25.915316 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1191 07:34:25.995856 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1192 07:34:26.074580 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1193 07:34:26.153206 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1194 07:34:26.231903 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1195 07:34:26.311296 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1196 07:34:26.390401 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1197 07:34:26.473013 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1198 07:34:26.549758 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1199 07:34:26.628420 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1200 07:34:26.701606 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1201 07:34:26.783528 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1202 07:34:26.864142 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1203 07:34:26.944908 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1204 07:34:27.042435 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1205 07:34:27.124772 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1206 07:34:27.200654 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1207 07:34:27.279734 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1208 07:34:27.358526 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1209 07:34:27.436567 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1210 07:34:27.516904 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1211 07:34:27.600317 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1212 07:34:27.683154 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1213 07:34:27.763180 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1214 07:34:27.842410 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1215 07:34:27.922099 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1216 07:34:28.001417 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1217 07:34:28.081108 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1218 07:34:28.161978 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1219 07:34:28.242214 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1220 07:34:28.332013 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1221 07:34:28.406668 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1222 07:34:28.484496 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1223 07:34:28.563281 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1224 07:34:28.642450 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1225 07:34:28.729191 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1226 07:34:28.805836 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1227 07:34:28.884694 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1228 07:34:28.963540 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1229 07:34:29.044249 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1230 07:34:29.123779 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1231 07:34:29.210892 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1232 07:34:29.285916 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1233 07:34:29.368866 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1234 07:34:29.444367 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1235 07:34:29.527394 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1236 07:34:29.610828 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1237 07:34:29.686430 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1238 07:34:29.765022 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1239 07:34:29.845172 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1240 07:34:29.924080 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1241 07:34:30.005291 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1242 07:34:30.084605 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1243 07:34:30.169922 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1244 07:34:30.253922 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1245 07:34:30.332667 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1246 07:34:30.412754 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1247 07:34:30.487398 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1248 07:34:30.571914 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1249 07:34:30.651886 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1250 07:34:30.731585 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1251 07:34:30.811806 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1252 07:34:30.903096 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1253 07:34:30.985709 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1254 07:34:31.063855 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1255 07:34:31.140985 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1256 07:34:31.224332 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1257 07:34:31.312826 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1258 07:34:31.394516 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1259 07:34:31.416009 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1260 07:34:31.441974 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1261 07:34:31.467752 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1262 07:34:31.493353 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1263 07:34:31.522876 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1264 07:34:31.544725 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1265 07:34:31.570455 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1266 07:34:31.594774 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1267 07:34:31.716726 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1268 07:34:31.753339 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1269 07:34:31.774823 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1270 07:34:31.800895 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1271 07:34:31.925876 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1272 07:34:32.009653 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1273 07:34:32.089872 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1274 07:34:32.169522 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1275 07:34:32.250035 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1276 07:34:32.333731 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1277 07:34:32.414627 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1278 07:34:32.496529 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1279 07:34:32.581164 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1280 07:34:32.669247 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1281 07:34:32.747632 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1282 07:34:32.827780 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1283 07:34:32.906806 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1284 07:34:32.989705 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1285 07:34:33.070550 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1286 07:34:33.175548 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1287 07:34:33.202287 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1288 07:34:33.280880 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1289 07:34:33.357617 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1290 07:34:33.438541 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1291 07:34:33.464065 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1292 07:34:33.542577 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1293 07:34:33.566164 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1294 07:34:33.650230 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1295 07:34:33.670608 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1296 07:34:33.696453 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1297 07:34:33.719663 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1298 07:34:33.752311 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1299 07:34:33.775834 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1300 07:34:33.797952 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1301 07:34:33.824935 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1302 07:34:33.914892 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1303 07:34:33.933047 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1304 07:34:33.955619 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1305 07:34:34.031318 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1306 07:34:34.104964 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1307 07:34:34.124350 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1308 07:34:34.226309 # not ok 144 /ocp/interconnect@47c00000
1309 07:34:34.298825 # not ok 145 /ocp/interconnect@47c00000/segment@0
1310 07:34:34.319438 # ok 146 /ocp/interconnect@48000000
1311 07:34:34.347872 # ok 147 /ocp/interconnect@48000000/segment@0
1312 07:34:34.371400 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1313 07:34:34.393212 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1314 07:34:34.416387 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1315 07:34:34.440910 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1316 07:34:34.468431 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1317 07:34:34.491796 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1318 07:34:34.511949 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1319 07:34:34.585970 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1320 07:34:34.661501 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1321 07:34:34.688814 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1322 07:34:34.711869 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1323 07:34:34.737171 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1324 07:34:34.761882 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1325 07:34:34.781854 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1326 07:34:34.805843 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1327 07:34:34.828571 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1328 07:34:34.853756 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1329 07:34:34.880916 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1330 07:34:34.909879 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1331 07:34:34.925204 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1332 07:34:34.950647 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1333 07:34:34.974233 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1334 07:34:35.001457 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1335 07:34:35.026777 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1336 07:34:35.047935 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1337 07:34:35.070935 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1338 07:34:35.100294 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1339 07:34:35.119746 # ok 175 /ocp/interconnect@48000000/segment@100000
1340 07:34:35.147905 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1341 07:34:35.171930 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1342 07:34:35.245151 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1343 07:34:35.320123 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1344 07:34:35.392481 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1345 07:34:35.468748 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1346 07:34:35.539858 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1347 07:34:35.616315 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1348 07:34:35.687246 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1349 07:34:35.763509 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1350 07:34:35.784103 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1351 07:34:35.808214 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1352 07:34:35.832143 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1353 07:34:35.856089 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1354 07:34:35.879507 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1355 07:34:35.904143 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1356 07:34:35.926975 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1357 07:34:35.956152 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1358 07:34:35.974850 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1359 07:34:35.999328 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1360 07:34:36.027751 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1361 07:34:36.051811 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1362 07:34:36.069268 # ok 198 /ocp/interconnect@48000000/segment@200000
1363 07:34:36.098602 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1364 07:34:36.172216 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1365 07:34:36.192501 # ok 201 /ocp/interconnect@48000000/segment@300000
1366 07:34:36.219034 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1367 07:34:36.241249 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1368 07:34:36.265224 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1369 07:34:36.288021 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1370 07:34:36.311980 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1371 07:34:36.339926 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1372 07:34:36.412238 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1373 07:34:36.427984 # ok 209 /ocp/interconnect@4a000000
1374 07:34:36.455973 # ok 210 /ocp/interconnect@4a000000/segment@0
1375 07:34:36.480899 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1376 07:34:36.509199 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1377 07:34:36.527642 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1378 07:34:36.553237 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1379 07:34:36.625180 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1380 07:34:36.734348 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1381 07:34:36.809081 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1382 07:34:36.915719 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1383 07:34:36.992827 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1384 07:34:37.065129 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1385 07:34:37.167780 # not ok 221 /ocp/interconnect@4b140000
1386 07:34:37.245762 # not ok 222 /ocp/interconnect@4b140000/segment@0
1387 07:34:37.319504 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1388 07:34:37.336269 # ok 224 /ocp/target-module@40300000
1389 07:34:37.360481 # ok 225 /ocp/target-module@40300000/sram@0
1390 07:34:37.440548 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1391 07:34:37.511244 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1392 07:34:37.535102 # ok 228 /ocp/target-module@47400000
1393 07:34:37.554586 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1394 07:34:37.579586 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1395 07:34:37.601868 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1396 07:34:37.628513 # ok 232 /ocp/target-module@47400000/usb@1400
1397 07:34:37.649128 # ok 233 /ocp/target-module@47400000/usb@1800
1398 07:34:37.669837 # ok 234 /ocp/target-module@47810000
1399 07:34:37.696107 # ok 235 /ocp/target-module@49000000
1400 07:34:37.719018 # ok 236 /ocp/target-module@49000000/dma@0
1401 07:34:37.737425 # ok 237 /ocp/target-module@49800000
1402 07:34:37.762069 # ok 238 /ocp/target-module@49800000/dma@0
1403 07:34:37.784000 # ok 239 /ocp/target-module@49900000
1404 07:34:37.808866 # ok 240 /ocp/target-module@49900000/dma@0
1405 07:34:37.833915 # ok 241 /ocp/target-module@49a00000
1406 07:34:37.852113 # ok 242 /ocp/target-module@49a00000/dma@0
1407 07:34:37.878297 # ok 243 /ocp/target-module@4c000000
1408 07:34:37.947559 # not ok 244 /ocp/target-module@4c000000/emif@0
1409 07:34:37.974275 # ok 245 /ocp/target-module@50000000
1410 07:34:37.997891 # ok 246 /ocp/target-module@53100000
1411 07:34:38.068443 # not ok 247 /ocp/target-module@53100000/sham@0
1412 07:34:38.094877 # ok 248 /ocp/target-module@53500000
1413 07:34:38.168608 # not ok 249 /ocp/target-module@53500000/aes@0
1414 07:34:38.186256 # ok 250 /ocp/target-module@56000000
1415 07:34:38.299691 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1416 07:34:38.365907 # ok 252 /opp-table # SKIP
1417 07:34:38.444360 # ok 253 /soc # SKIP
1418 07:34:38.461345 # ok 254 /sound
1419 07:34:38.486241 # ok 255 /target-module@4b000000
1420 07:34:38.515094 # ok 256 /target-module@4b000000/target-module@140000
1421 07:34:38.533085 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1422 07:34:38.540469 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1423 07:34:38.549431 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1424 07:34:40.737800 dt_test_unprobed_devices_sh_ skip
1425 07:34:40.743620 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1426 07:34:40.749065 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1427 07:34:40.749314 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1428 07:34:40.754766 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1429 07:34:40.760127 dt_test_unprobed_devices_sh_fixedregulator0 pass
1430 07:34:40.765942 dt_test_unprobed_devices_sh_leds pass
1431 07:34:40.766160 dt_test_unprobed_devices_sh_ocp pass
1432 07:34:40.771642 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1433 07:34:40.777048 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1434 07:34:40.782696 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1435 07:34:40.793762 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1436 07:34:40.799566 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1437 07:34:40.804971 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1438 07:34:40.816230 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1439 07:34:40.821798 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1440 07:34:40.833123 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1441 07:34:40.844319 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1442 07:34:40.855663 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1443 07:34:40.861010 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1444 07:34:40.872343 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1445 07:34:40.883665 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1446 07:34:40.894818 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1447 07:34:40.905991 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1448 07:34:40.911610 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1449 07:34:40.922813 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1450 07:34:40.934016 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1451 07:34:40.945026 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1452 07:34:40.956274 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1453 07:34:40.961817 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1454 07:34:40.973131 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1455 07:34:40.984203 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1456 07:34:40.995421 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1457 07:34:41.001155 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1458 07:34:41.012220 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1459 07:34:41.023380 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1460 07:34:41.034586 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1461 07:34:41.045770 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1462 07:34:41.051377 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1463 07:34:41.062614 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1464 07:34:41.073822 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1465 07:34:41.085240 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1466 07:34:41.096199 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1467 07:34:41.107414 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1468 07:34:41.118648 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1469 07:34:41.129890 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1470 07:34:41.141101 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1471 07:34:41.152311 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1472 07:34:41.163535 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1473 07:34:41.174741 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1474 07:34:41.186074 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1475 07:34:41.197289 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1476 07:34:41.208296 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1477 07:34:41.219547 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1478 07:34:41.230805 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1479 07:34:41.242018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1480 07:34:41.253083 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1481 07:34:41.264318 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1482 07:34:41.275619 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1483 07:34:41.286797 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1484 07:34:41.297990 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1485 07:34:41.309187 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1486 07:34:41.320471 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1487 07:34:41.331568 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1488 07:34:41.337197 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1489 07:34:41.348363 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1490 07:34:41.359589 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1491 07:34:41.370755 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1492 07:34:41.381922 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1493 07:34:41.393023 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1494 07:34:41.404304 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1495 07:34:41.415693 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1496 07:34:41.426761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1497 07:34:41.437942 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1498 07:34:41.449014 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1499 07:34:41.460183 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1500 07:34:41.471553 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1501 07:34:41.482620 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1502 07:34:41.493919 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1503 07:34:41.505044 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1504 07:34:41.516298 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1505 07:34:41.527547 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1506 07:34:41.533011 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1507 07:34:41.544148 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1508 07:34:41.555556 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1509 07:34:41.566683 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1510 07:34:41.577748 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1511 07:34:41.583504 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1512 07:34:41.600100 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1513 07:34:41.611504 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1514 07:34:41.617073 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1515 07:34:41.633862 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1516 07:34:41.645114 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1517 07:34:41.656118 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1518 07:34:41.661688 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1519 07:34:41.673187 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1520 07:34:41.684226 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1521 07:34:41.689777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1522 07:34:41.700824 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1523 07:34:41.712152 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1524 07:34:41.717644 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1525 07:34:41.728824 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1526 07:34:41.734446 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1527 07:34:41.745736 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1528 07:34:41.756777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1529 07:34:41.768211 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1530 07:34:41.779354 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1531 07:34:41.790381 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1532 07:34:41.801710 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1533 07:34:41.812768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1534 07:34:41.823957 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1535 07:34:41.835296 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1536 07:34:41.846351 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1537 07:34:41.857665 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1538 07:34:41.868747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1539 07:34:41.885607 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1540 07:34:41.896802 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1541 07:34:41.907966 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1542 07:34:41.919299 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1543 07:34:41.930321 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1544 07:34:41.947281 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1545 07:34:41.958306 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1546 07:34:41.969554 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1547 07:34:41.980846 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1548 07:34:41.986388 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1549 07:34:41.997619 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1550 07:34:42.009004 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1551 07:34:42.014566 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1552 07:34:42.025836 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1553 07:34:42.031398 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1554 07:34:42.042472 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1555 07:34:42.048252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1556 07:34:42.059405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1557 07:34:42.064879 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1558 07:34:42.076126 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1559 07:34:42.081965 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1560 07:34:42.093047 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1561 07:34:42.104270 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1562 07:34:42.115316 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1563 07:34:42.126504 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1564 07:34:42.137652 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1565 07:34:42.143234 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1566 07:34:42.154494 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1567 07:34:42.160105 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1568 07:34:42.165619 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1569 07:34:42.171207 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1570 07:34:42.176816 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1571 07:34:42.182434 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1572 07:34:42.193672 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1573 07:34:42.199283 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1574 07:34:42.204851 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1575 07:34:42.216038 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1576 07:34:42.221683 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1577 07:34:42.232801 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1578 07:34:42.238460 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1579 07:34:42.249670 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1580 07:34:42.255687 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1581 07:34:42.266420 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1582 07:34:42.272006 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1583 07:34:42.283189 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1584 07:34:42.288765 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1585 07:34:42.299983 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1586 07:34:42.305604 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1587 07:34:42.316800 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1588 07:34:42.322402 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1589 07:34:42.327978 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1590 07:34:42.339193 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1591 07:34:42.345286 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1592 07:34:42.356139 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1593 07:34:42.361979 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1594 07:34:42.372763 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1595 07:34:42.378344 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1596 07:34:42.389758 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1597 07:34:42.396247 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1598 07:34:42.401847 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1599 07:34:42.412718 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1600 07:34:42.417628 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1601 07:34:42.429011 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1602 07:34:42.439977 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1603 07:34:42.451103 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1604 07:34:42.462332 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1605 07:34:42.473504 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1606 07:34:42.484713 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1607 07:34:42.495893 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1608 07:34:42.507215 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1609 07:34:42.512694 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1610 07:34:42.523906 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1611 07:34:42.529493 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1612 07:34:42.540930 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1613 07:34:42.546270 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1614 07:34:42.557461 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1615 07:34:42.563513 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1616 07:34:42.574290 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1617 07:34:42.579816 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1618 07:34:42.590990 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1619 07:34:42.596630 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1620 07:34:42.607879 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1621 07:34:42.613407 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1622 07:34:42.624598 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1623 07:34:42.630372 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1624 07:34:42.635802 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1625 07:34:42.646966 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1626 07:34:42.652614 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1627 07:34:42.663863 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1628 07:34:42.669473 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1629 07:34:42.680501 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1630 07:34:42.686265 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1631 07:34:42.697529 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1632 07:34:42.702896 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1633 07:34:42.708485 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1634 07:34:42.714070 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1635 07:34:42.725246 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1636 07:34:42.736483 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1637 07:34:42.742110 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1638 07:34:42.747837 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1639 07:34:42.758900 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1640 07:34:42.770087 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1641 07:34:42.781219 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1642 07:34:42.792450 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1643 07:34:42.798023 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1644 07:34:42.803699 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1645 07:34:42.809311 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1646 07:34:42.815100 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1647 07:34:42.820519 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1648 07:34:42.826433 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1649 07:34:42.837389 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1650 07:34:42.843140 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1651 07:34:42.848629 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1652 07:34:42.854230 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1653 07:34:42.859873 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1654 07:34:42.871035 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1655 07:34:42.876652 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1656 07:34:42.882220 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1657 07:34:42.887854 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1658 07:34:42.893457 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1659 07:34:42.899040 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1660 07:34:42.904677 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1661 07:34:42.910226 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1662 07:34:42.915810 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1663 07:34:42.921407 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1664 07:34:42.927038 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1665 07:34:42.932622 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1666 07:34:42.938395 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1667 07:34:42.943825 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1668 07:34:42.949697 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1669 07:34:42.955003 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1670 07:34:42.960683 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1671 07:34:42.966274 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1672 07:34:42.971907 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1673 07:34:42.977510 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1674 07:34:42.983050 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1675 07:34:42.983320 dt_test_unprobed_devices_sh_opp-table skip
1676 07:34:42.988712 dt_test_unprobed_devices_sh_soc skip
1677 07:34:42.994331 dt_test_unprobed_devices_sh_sound pass
1678 07:34:42.999887 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1679 07:34:43.005543 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1680 07:34:43.011155 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1681 07:34:43.016737 dt_test_unprobed_devices_sh fail
1682 07:34:43.016983 + ../../utils/send-to-lava.sh ./output/result.txt
1683 07:34:43.024050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1684 07:34:43.024638 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1686 07:34:43.039036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1687 07:34:43.039555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1689 07:34:43.137021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1690 07:34:43.137533 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1692 07:34:43.230430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1693 07:34:43.230950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1695 07:34:43.324281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1696 07:34:43.324803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1698 07:34:43.421070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1699 07:34:43.421585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1701 07:34:43.516600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1702 07:34:43.517139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1704 07:34:43.616004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1705 07:34:43.616570 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1707 07:34:43.708295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1708 07:34:43.708825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1710 07:34:43.804339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1711 07:34:43.804828 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1713 07:34:43.901536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1714 07:34:43.902052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1716 07:34:43.994713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1717 07:34:43.995221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1719 07:34:44.093080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1720 07:34:44.093591 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1722 07:34:44.189153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1723 07:34:44.189646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1725 07:34:44.282458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1726 07:34:44.282972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1728 07:34:44.378616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1729 07:34:44.379126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1731 07:34:44.475046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1732 07:34:44.475562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1734 07:34:44.604477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1735 07:34:44.604996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1737 07:34:44.704316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1738 07:34:44.704827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1740 07:34:44.799951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1741 07:34:44.800462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1743 07:34:44.895377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1744 07:34:44.895908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1746 07:34:44.992104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1747 07:34:44.992611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1749 07:34:45.087404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1750 07:34:45.088008 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1752 07:34:45.190290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1753 07:34:45.190811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1755 07:34:45.286258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1756 07:34:45.286768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1758 07:34:45.383175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1759 07:34:45.383701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1761 07:34:45.476489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1762 07:34:45.477035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1764 07:34:45.578684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1765 07:34:45.579207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1767 07:34:45.673836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1768 07:34:45.674360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1770 07:34:45.771461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1771 07:34:45.771987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1773 07:34:45.866482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1774 07:34:45.866987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1776 07:34:45.966323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1777 07:34:45.966837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1779 07:34:46.061933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1780 07:34:46.062439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1782 07:34:46.153149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1783 07:34:46.153651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1785 07:34:46.246452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1786 07:34:46.246955 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1788 07:34:46.335889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1789 07:34:46.336390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1791 07:34:46.424935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1792 07:34:46.425456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1794 07:34:46.520291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1795 07:34:46.520819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1797 07:34:46.616720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1798 07:34:46.617224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1800 07:34:46.714583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1801 07:34:46.715079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1803 07:34:46.809133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1804 07:34:46.809636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1806 07:34:46.906525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1807 07:34:46.907027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1809 07:34:47.012689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1810 07:34:47.013215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1812 07:34:47.130435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1813 07:34:47.130939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1815 07:34:47.227397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1816 07:34:47.227926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1818 07:34:47.322029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1819 07:34:47.322528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1821 07:34:47.421465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1822 07:34:47.421964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1824 07:34:47.520363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1825 07:34:47.520859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1827 07:34:47.617845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1828 07:34:47.618332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1830 07:34:47.713578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1831 07:34:47.714075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1833 07:34:47.811005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1834 07:34:47.811556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1836 07:34:47.922364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1837 07:34:47.922889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1839 07:34:48.034790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1840 07:34:48.035360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1842 07:34:48.146663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1843 07:34:48.147262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1845 07:34:48.266393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1846 07:34:48.266924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1848 07:34:48.386023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1849 07:34:48.386548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1851 07:34:48.502464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1852 07:34:48.502984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1854 07:34:48.613158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1855 07:34:48.613695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1857 07:34:48.730105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1858 07:34:48.730631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1860 07:34:48.846733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1861 07:34:48.847252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1863 07:34:48.968925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1864 07:34:48.969482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1866 07:34:49.093616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1867 07:34:49.094149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1869 07:34:49.210556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1870 07:34:49.211152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1872 07:34:49.326364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1873 07:34:49.326882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1875 07:34:49.461788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1876 07:34:49.462313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1878 07:34:49.585922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1879 07:34:49.586443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1881 07:34:49.704916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1882 07:34:49.705536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1884 07:34:49.815567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1885 07:34:49.816200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1887 07:34:49.937054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1888 07:34:49.937648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1890 07:34:50.056530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1891 07:34:50.057079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1893 07:34:50.156467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1894 07:34:50.157012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1896 07:34:50.256391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1897 07:34:50.256939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1899 07:34:50.352175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1900 07:34:50.352715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1902 07:34:50.447269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1903 07:34:50.447832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1905 07:34:50.547353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1906 07:34:50.547920 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1908 07:34:50.645040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1909 07:34:50.645580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1911 07:34:50.748482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1912 07:34:50.749024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1914 07:34:50.847000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1915 07:34:50.847545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1917 07:34:50.945594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1918 07:34:50.946133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1920 07:34:51.041133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1921 07:34:51.041657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1923 07:34:51.137771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1924 07:34:51.138297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1926 07:34:51.235099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1927 07:34:51.235635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1929 07:34:51.332258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1930 07:34:51.332798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1932 07:34:51.428243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1933 07:34:51.428784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1935 07:34:51.525943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1936 07:34:51.526478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1938 07:34:51.622350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1939 07:34:51.622852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1941 07:34:51.717176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1942 07:34:51.717705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1944 07:34:51.813995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1945 07:34:51.814514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1947 07:34:51.909891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1948 07:34:51.910384 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1950 07:34:52.008813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1951 07:34:52.009321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1953 07:34:52.104278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1954 07:34:52.104771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1956 07:34:52.196082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1957 07:34:52.196594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1959 07:34:52.297388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1960 07:34:52.297898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1962 07:34:52.393585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1963 07:34:52.394088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1965 07:34:52.490815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1966 07:34:52.491318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1968 07:34:52.583150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1969 07:34:52.583677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1971 07:34:52.675007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1972 07:34:52.675569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1974 07:34:52.769107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1975 07:34:52.769608 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1977 07:34:52.863321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1978 07:34:52.863863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1980 07:34:52.958967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1981 07:34:52.959470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1983 07:34:53.054648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1984 07:34:53.055190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1986 07:34:53.151320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1987 07:34:53.151899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1989 07:34:53.246007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1990 07:34:53.246527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1992 07:34:53.342757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1993 07:34:53.343289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1995 07:34:53.439324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1996 07:34:53.439891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1998 07:34:53.535647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1999 07:34:53.536176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
2001 07:34:53.625200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
2002 07:34:53.625757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
2004 07:34:53.720918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
2005 07:34:53.721479 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
2007 07:34:53.818424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
2008 07:34:53.818977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
2010 07:34:53.915209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
2011 07:34:53.915755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
2013 07:34:54.011007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
2014 07:34:54.011554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
2016 07:34:54.107553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
2017 07:34:54.108075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
2019 07:34:54.202360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
2020 07:34:54.202865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
2022 07:34:54.298391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
2023 07:34:54.298896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
2025 07:34:54.393651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
2026 07:34:54.394173 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
2028 07:34:54.488711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
2029 07:34:54.489217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
2031 07:34:54.614320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
2032 07:34:54.614854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
2034 07:34:54.711034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
2035 07:34:54.711555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
2037 07:34:54.807512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
2038 07:34:54.808030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
2040 07:34:54.903373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
2041 07:34:54.903922 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
2043 07:34:54.998624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
2045 07:34:55.001795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
2046 07:34:55.095720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
2048 07:34:55.098795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2049 07:34:55.193412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2051 07:34:55.196498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2052 07:34:55.290395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2053 07:34:55.290927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2055 07:34:55.387722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2056 07:34:55.388272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2058 07:34:55.478860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2059 07:34:55.479369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2061 07:34:55.574467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2062 07:34:55.574973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2064 07:34:55.669983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2065 07:34:55.670491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2067 07:34:55.766349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2068 07:34:55.766866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2070 07:34:55.862970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2071 07:34:55.863475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2073 07:34:55.959367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2074 07:34:55.959896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2076 07:34:56.057256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2077 07:34:56.057755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2079 07:34:56.151781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2080 07:34:56.152299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2082 07:34:56.241878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2083 07:34:56.242386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2085 07:34:56.336335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2086 07:34:56.336869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2088 07:34:56.433562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2089 07:34:56.434114 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2091 07:34:56.529763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2092 07:34:56.530303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2094 07:34:56.626261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2095 07:34:56.626790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2097 07:34:56.724914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2098 07:34:56.725443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2100 07:34:56.816788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2101 07:34:56.817333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2103 07:34:56.912600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2104 07:34:56.913123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2106 07:34:57.006751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2107 07:34:57.007286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2109 07:34:57.103212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2110 07:34:57.103763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2112 07:34:57.195904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2113 07:34:57.196418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2115 07:34:57.290410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2116 07:34:57.290916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2118 07:34:57.385556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2119 07:34:57.386064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2121 07:34:57.480525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2122 07:34:57.481049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2124 07:34:57.577896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2125 07:34:57.578399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2127 07:34:57.675539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2128 07:34:57.676058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2130 07:34:57.771761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2131 07:34:57.772272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2133 07:34:57.867195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2134 07:34:57.867727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2136 07:34:57.963004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2137 07:34:57.963536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2139 07:34:58.053573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2140 07:34:58.054086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2142 07:34:58.151191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2143 07:34:58.151694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2145 07:34:58.244614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2146 07:34:58.245151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2148 07:34:58.342154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2149 07:34:58.342662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2151 07:34:58.436227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2152 07:34:58.436753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2154 07:34:58.530759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2155 07:34:58.531272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2157 07:34:58.620928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2158 07:34:58.621450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2160 07:34:58.714448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2161 07:34:58.714967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2163 07:34:58.811115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2164 07:34:58.811650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2166 07:34:58.906909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2167 07:34:58.907417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2169 07:34:59.002726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2170 07:34:59.003257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2172 07:34:59.097106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2173 07:34:59.097628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2175 07:34:59.194216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2176 07:34:59.194768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2178 07:34:59.287752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2179 07:34:59.288255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2181 07:34:59.384517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2182 07:34:59.385062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2184 07:34:59.473777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2185 07:34:59.474286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2187 07:34:59.573090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2188 07:34:59.573585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2190 07:34:59.668594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2191 07:34:59.669033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2193 07:34:59.763855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2194 07:34:59.764358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2196 07:34:59.861335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2197 07:34:59.861826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2199 07:34:59.955862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2200 07:34:59.956374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2202 07:35:00.050294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2203 07:35:00.050800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2205 07:35:00.144366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2206 07:35:00.144864 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2208 07:35:00.238397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2209 07:35:00.238906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2211 07:35:00.328860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2212 07:35:00.329357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2214 07:35:00.425516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2215 07:35:00.426027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2217 07:35:00.523047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2218 07:35:00.523569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2220 07:35:00.621035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2221 07:35:00.621561 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2223 07:35:00.738214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2224 07:35:00.738748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2226 07:35:00.835567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2227 07:35:00.836100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2229 07:35:00.930285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2230 07:35:00.930782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2232 07:35:01.027919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2233 07:35:01.028428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2235 07:35:01.123038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2236 07:35:01.123574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2238 07:35:01.221570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2239 07:35:01.222077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2241 07:35:01.314050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2242 07:35:01.314533 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2244 07:35:01.410331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2245 07:35:01.410859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2247 07:35:01.501395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2248 07:35:01.501900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2250 07:35:01.597793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2251 07:35:01.598296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2253 07:35:01.693761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2254 07:35:01.694261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2256 07:35:01.786646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2257 07:35:01.787141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2259 07:35:01.881113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2260 07:35:01.881607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2262 07:35:01.974320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2263 07:35:01.974812 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2265 07:35:02.070182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2266 07:35:02.070670 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2268 07:35:02.162533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2269 07:35:02.163022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2271 07:35:02.262126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2272 07:35:02.262606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2274 07:35:02.358929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2275 07:35:02.359427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2277 07:35:02.456433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2278 07:35:02.456927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2280 07:35:02.563915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2281 07:35:02.564511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2283 07:35:02.679204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2284 07:35:02.679832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2286 07:35:02.785879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2287 07:35:02.786409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2289 07:35:02.892418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2290 07:35:02.892945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2292 07:35:02.998226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2293 07:35:02.998841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2295 07:35:03.098445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2296 07:35:03.099056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2298 07:35:03.222214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2299 07:35:03.222801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2301 07:35:03.337991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2302 07:35:03.338515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2304 07:35:03.447944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2305 07:35:03.448473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2307 07:35:03.566040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2308 07:35:03.566562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2310 07:35:03.680434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2311 07:35:03.680954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2313 07:35:03.794456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2314 07:35:03.794953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2316 07:35:03.909484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2317 07:35:03.910007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2319 07:35:04.017751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2320 07:35:04.018365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2322 07:35:04.132895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2323 07:35:04.133422 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2325 07:35:04.240751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2326 07:35:04.241280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2328 07:35:04.363072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2329 07:35:04.363565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2331 07:35:04.474655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2332 07:35:04.475249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2334 07:35:04.589380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2335 07:35:04.589903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2337 07:35:04.697457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2338 07:35:04.697997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2340 07:35:04.804947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2341 07:35:04.805477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2343 07:35:04.909374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2344 07:35:04.909925 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2346 07:35:05.007055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2347 07:35:05.007576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2349 07:35:05.125828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2350 07:35:05.126354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2352 07:35:05.249803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2353 07:35:05.250324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2355 07:35:05.362604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2356 07:35:05.363125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2358 07:35:05.466316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2359 07:35:05.466839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2361 07:35:05.576976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2362 07:35:05.577502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2364 07:35:05.685195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2366 07:35:05.688166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2367 07:35:05.791255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2368 07:35:05.791830 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2370 07:35:05.901075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2371 07:35:05.901602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2373 07:35:06.027019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2374 07:35:06.027581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2376 07:35:06.143546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2377 07:35:06.144072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2379 07:35:06.263102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2380 07:35:06.263623 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2382 07:35:06.374477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2383 07:35:06.375004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2385 07:35:06.478611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2386 07:35:06.479139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2388 07:35:06.587157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2389 07:35:06.587664 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2391 07:35:06.694844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2392 07:35:06.695368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2394 07:35:06.815044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2395 07:35:06.815645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2397 07:35:06.932143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2398 07:35:06.932673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2400 07:35:07.040738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2401 07:35:07.041265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2403 07:35:07.154754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2404 07:35:07.155284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2406 07:35:07.285657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2407 07:35:07.286194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2409 07:35:07.404923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2410 07:35:07.405428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2412 07:35:07.497878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2413 07:35:07.498382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2415 07:35:07.592368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2416 07:35:07.592874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2418 07:35:07.901951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2419 07:35:07.902497 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2421 07:35:07.903126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2422 07:35:07.903539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2424 07:35:07.905452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2425 07:35:07.905893 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2427 07:35:07.967579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2428 07:35:07.968068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2430 07:35:08.061774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2431 07:35:08.062291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2433 07:35:08.150645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2434 07:35:08.151150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2436 07:35:08.241648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2437 07:35:08.242162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2439 07:35:08.336565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2440 07:35:08.337074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2442 07:35:08.432092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2443 07:35:08.432603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2445 07:35:08.528985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2446 07:35:08.529485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2448 07:35:08.624816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2449 07:35:08.625321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2451 07:35:08.722709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2452 07:35:08.723212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2454 07:35:08.818231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2455 07:35:08.818739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2457 07:35:08.909286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2458 07:35:08.909593 + set +x
2459 07:35:08.910035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2461 07:35:08.913530 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 742859_1.6.2.4.5>
2462 07:35:08.913978 Received signal: <ENDRUN> 1_kselftest-dt 742859_1.6.2.4.5
2463 07:35:08.914181 Ending use of test pattern.
2464 07:35:08.914387 Ending test lava.1_kselftest-dt (742859_1.6.2.4.5), duration 91.29
2466 07:35:08.919628 <LAVA_TEST_RUNNER EXIT>
2467 07:35:08.920071 ok: lava_test_shell seems to have completed
2468 07:35:08.924090 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2469 07:35:08.924941 end: 3.1 lava-test-shell (duration 00:01:33) [common]
2470 07:35:08.925198 end: 3 lava-test-retry (duration 00:01:33) [common]
2471 07:35:08.925461 start: 4 finalize (timeout 00:05:51) [common]
2472 07:35:08.925736 start: 4.1 power-off (timeout 00:00:30) [common]
2473 07:35:08.926174 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-03'
2474 07:35:08.945172 >> OK - accepted request
2475 07:35:08.946122 Returned 0 in 0 seconds
2476 07:35:09.046800 end: 4.1 power-off (duration 00:00:00) [common]
2478 07:35:09.047622 start: 4.2 read-feedback (timeout 00:05:51) [common]
2479 07:35:09.048248 Listened to connection for namespace 'common' for up to 1s
2480 07:35:09.048758 Listened to connection for namespace 'common' for up to 1s
2481 07:35:10.048544 Finalising connection for namespace 'common'
2482 07:35:10.048900 Disconnecting from shell: Finalise
2483 07:35:10.049113 / #
2484 07:35:10.149669 end: 4.2 read-feedback (duration 00:00:01) [common]
2485 07:35:10.150035 end: 4 finalize (duration 00:00:01) [common]
2486 07:35:10.150310 Cleaning after the job
2487 07:35:10.150567 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742859/tftp-deploy-yq2i0syt/ramdisk
2488 07:35:10.158788 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742859/tftp-deploy-yq2i0syt/kernel
2489 07:35:10.160621 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742859/tftp-deploy-yq2i0syt/dtb
2490 07:35:10.161069 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742859/tftp-deploy-yq2i0syt/nfsrootfs
2491 07:35:10.218108 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742859/tftp-deploy-yq2i0syt/modules
2492 07:35:10.224519 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/742859
2493 07:35:11.070077 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/742859
2494 07:35:11.070307 Job finished correctly