Boot log: beaglebone-black
- Warnings: 3
- Kernel Warnings: 101
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 08:03:14.482312 lava-dispatcher, installed at version: 2024.01
2 08:03:14.482630 start: 0 validate
3 08:03:14.482774 Start time: 2024-09-19 08:03:14.482768+00:00 (UTC)
4 08:03:14.482935 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 08:03:14.809460 Validating that http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
6 08:03:14.972655 Validating that http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
7 08:03:15.134829 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 08:03:15.297284 Validating that http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
9 08:03:15.461865 validate duration: 0.98
11 08:03:15.462486 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 08:03:15.462746 start: 1.1 download-retry (timeout 00:10:00) [common]
13 08:03:15.462989 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 08:03:15.463499 Not decompressing ramdisk as can be used compressed.
15 08:03:15.463837 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 08:03:15.464034 saving as /var/lib/lava/dispatcher/tmp/743034/tftp-deploy-7mwwifo5/ramdisk/initrd.cpio.gz
17 08:03:15.464209 total size: 4775763 (4 MB)
18 08:03:15.785858 progress 0 % (0 MB)
19 08:03:16.270512 progress 5 % (0 MB)
20 08:03:16.610119 progress 10 % (0 MB)
21 08:03:16.631917 progress 15 % (0 MB)
22 08:03:16.763833 progress 20 % (0 MB)
23 08:03:16.978608 progress 25 % (1 MB)
24 08:03:17.090864 progress 30 % (1 MB)
25 08:03:17.248912 progress 35 % (1 MB)
26 08:03:17.412066 progress 40 % (1 MB)
27 08:03:17.562677 progress 45 % (2 MB)
28 08:03:17.626638 progress 50 % (2 MB)
29 08:03:17.868640 progress 55 % (2 MB)
30 08:03:17.942574 progress 60 % (2 MB)
31 08:03:18.087750 progress 65 % (2 MB)
32 08:03:18.243542 progress 70 % (3 MB)
33 08:03:18.393514 progress 75 % (3 MB)
34 08:03:18.546410 progress 80 % (3 MB)
35 08:03:18.704928 progress 85 % (3 MB)
36 08:03:18.866260 progress 90 % (4 MB)
37 08:03:19.107922 progress 95 % (4 MB)
38 08:03:19.111271 progress 100 % (4 MB)
39 08:03:19.111934 4 MB downloaded in 3.65 s (1.25 MB/s)
40 08:03:19.112364 end: 1.1.1 http-download (duration 00:00:04) [common]
42 08:03:19.113020 end: 1.1 download-retry (duration 00:00:04) [common]
43 08:03:19.113237 start: 1.2 download-retry (timeout 00:09:56) [common]
44 08:03:19.113433 start: 1.2.1 http-download (timeout 00:09:56) [common]
45 08:03:19.113891 downloading http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/kernel/zImage
46 08:03:19.114067 saving as /var/lib/lava/dispatcher/tmp/743034/tftp-deploy-7mwwifo5/kernel/zImage
47 08:03:19.114207 total size: 11457024 (10 MB)
48 08:03:19.114352 No compression specified
49 08:03:19.285769 progress 0 % (0 MB)
50 08:03:19.942206 progress 5 % (0 MB)
51 08:03:20.456962 progress 10 % (1 MB)
52 08:03:21.100942 progress 15 % (1 MB)
53 08:03:21.604644 progress 20 % (2 MB)
54 08:03:22.208185 progress 25 % (2 MB)
55 08:03:22.723642 progress 30 % (3 MB)
56 08:03:23.378800 progress 35 % (3 MB)
57 08:03:23.946310 progress 40 % (4 MB)
58 08:03:24.622815 progress 45 % (4 MB)
59 08:03:25.287173 progress 50 % (5 MB)
60 08:03:25.928737 progress 55 % (6 MB)
61 08:03:26.492473 progress 60 % (6 MB)
62 08:03:27.064325 progress 65 % (7 MB)
63 08:03:27.624813 progress 70 % (7 MB)
64 08:03:28.182000 progress 75 % (8 MB)
65 08:03:28.697225 progress 80 % (8 MB)
66 08:03:29.278735 progress 85 % (9 MB)
67 08:03:29.805435 progress 90 % (9 MB)
68 08:03:30.318601 progress 95 % (10 MB)
69 08:03:30.907271 progress 100 % (10 MB)
70 08:03:30.907771 10 MB downloaded in 11.79 s (0.93 MB/s)
71 08:03:30.908051 end: 1.2.1 http-download (duration 00:00:12) [common]
73 08:03:30.908492 end: 1.2 download-retry (duration 00:00:12) [common]
74 08:03:30.908651 start: 1.3 download-retry (timeout 00:09:45) [common]
75 08:03:30.908798 start: 1.3.1 http-download (timeout 00:09:45) [common]
76 08:03:30.909035 downloading http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
77 08:03:30.909094 saving as /var/lib/lava/dispatcher/tmp/743034/tftp-deploy-7mwwifo5/dtb/am335x-boneblack.dtb
78 08:03:30.909144 total size: 70568 (0 MB)
79 08:03:30.909194 No compression specified
80 08:03:31.076741 progress 46 % (0 MB)
81 08:03:31.079560 progress 92 % (0 MB)
82 08:03:31.080148 progress 100 % (0 MB)
83 08:03:31.080433 0 MB downloaded in 0.17 s (0.39 MB/s)
84 08:03:31.080750 end: 1.3.1 http-download (duration 00:00:00) [common]
86 08:03:31.081233 end: 1.3 download-retry (duration 00:00:00) [common]
87 08:03:31.081390 start: 1.4 download-retry (timeout 00:09:44) [common]
88 08:03:31.081541 start: 1.4.1 http-download (timeout 00:09:44) [common]
89 08:03:31.081894 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 08:03:31.082043 saving as /var/lib/lava/dispatcher/tmp/743034/tftp-deploy-7mwwifo5/nfsrootfs/full.rootfs.tar
91 08:03:31.082165 total size: 117747780 (112 MB)
92 08:03:31.082297 Using unxz to decompress xz
93 08:03:31.246316 progress 0 % (0 MB)
94 08:03:35.429853 progress 5 % (5 MB)
95 08:03:39.367791 progress 10 % (11 MB)
96 08:03:43.714838 progress 15 % (16 MB)
97 08:03:49.234479 progress 20 % (22 MB)
98 08:03:54.736115 progress 25 % (28 MB)
99 08:04:01.525006 progress 30 % (33 MB)
100 08:04:10.235469 progress 35 % (39 MB)
101 08:04:16.202494 progress 40 % (44 MB)
102 08:04:23.981387 progress 45 % (50 MB)
103 08:04:29.896210 progress 50 % (56 MB)
104 08:04:32.569548 progress 55 % (61 MB)
105 08:04:34.191190 progress 60 % (67 MB)
106 08:04:35.350765 progress 65 % (73 MB)
107 08:04:36.316769 progress 70 % (78 MB)
108 08:04:37.134757 progress 75 % (84 MB)
109 08:04:37.848476 progress 80 % (89 MB)
110 08:04:38.531850 progress 85 % (95 MB)
111 08:04:39.239029 progress 90 % (101 MB)
112 08:04:39.944284 progress 95 % (106 MB)
113 08:04:40.646131 progress 100 % (112 MB)
114 08:04:40.648624 112 MB downloaded in 69.57 s (1.61 MB/s)
115 08:04:40.648875 end: 1.4.1 http-download (duration 00:01:10) [common]
117 08:04:40.649088 end: 1.4 download-retry (duration 00:01:10) [common]
118 08:04:40.649160 start: 1.5 download-retry (timeout 00:08:35) [common]
119 08:04:40.649229 start: 1.5.1 http-download (timeout 00:08:35) [common]
120 08:04:40.649408 downloading http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
121 08:04:40.649468 saving as /var/lib/lava/dispatcher/tmp/743034/tftp-deploy-7mwwifo5/modules/modules.tar
122 08:04:40.649516 total size: 6615688 (6 MB)
123 08:04:40.649584 Using unxz to decompress xz
124 08:04:40.815612 progress 0 % (0 MB)
125 08:04:41.007748 progress 5 % (0 MB)
126 08:04:41.164520 progress 10 % (0 MB)
127 08:04:41.297708 progress 15 % (0 MB)
128 08:04:41.329378 progress 20 % (1 MB)
129 08:04:41.350428 progress 25 % (1 MB)
130 08:04:41.467128 progress 30 % (1 MB)
131 08:04:41.503286 progress 35 % (2 MB)
132 08:04:41.780101 progress 40 % (2 MB)
133 08:04:41.813062 progress 45 % (2 MB)
134 08:04:41.834071 progress 50 % (3 MB)
135 08:04:41.856725 progress 55 % (3 MB)
136 08:04:41.878605 progress 60 % (3 MB)
137 08:04:41.965448 progress 65 % (4 MB)
138 08:04:42.001174 progress 70 % (4 MB)
139 08:04:42.113160 progress 75 % (4 MB)
140 08:04:42.150356 progress 80 % (5 MB)
141 08:04:42.263862 progress 85 % (5 MB)
142 08:04:42.301588 progress 90 % (5 MB)
143 08:04:42.338199 progress 95 % (6 MB)
144 08:04:42.470058 progress 100 % (6 MB)
145 08:04:42.478514 6 MB downloaded in 1.83 s (3.45 MB/s)
146 08:04:42.478965 end: 1.5.1 http-download (duration 00:00:02) [common]
148 08:04:42.479476 end: 1.5 download-retry (duration 00:00:02) [common]
149 08:04:42.479635 start: 1.6 prepare-tftp-overlay (timeout 00:08:33) [common]
150 08:04:42.479785 start: 1.6.1 extract-nfsrootfs (timeout 00:08:33) [common]
151 08:04:47.707409 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/743034/extract-nfsrootfs-j23pg8dq
152 08:04:47.707680 end: 1.6.1 extract-nfsrootfs (duration 00:00:05) [common]
153 08:04:47.707766 start: 1.6.2 lava-overlay (timeout 00:08:28) [common]
154 08:04:47.708029 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt
155 08:04:47.708169 makedir: /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin
156 08:04:47.708277 makedir: /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/tests
157 08:04:47.708373 makedir: /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/results
158 08:04:47.708476 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-add-keys
159 08:04:47.708632 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-add-sources
160 08:04:47.708766 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-background-process-start
161 08:04:47.708899 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-background-process-stop
162 08:04:47.709041 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-common-functions
163 08:04:47.709174 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-echo-ipv4
164 08:04:47.709308 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-install-packages
165 08:04:47.709438 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-installed-packages
166 08:04:47.709589 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-os-build
167 08:04:47.709726 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-probe-channel
168 08:04:47.709857 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-probe-ip
169 08:04:47.709985 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-target-ip
170 08:04:47.710120 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-target-mac
171 08:04:47.710250 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-target-storage
172 08:04:47.710382 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-test-case
173 08:04:47.710510 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-test-event
174 08:04:47.710640 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-test-feedback
175 08:04:47.710770 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-test-raise
176 08:04:47.710900 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-test-reference
177 08:04:47.711031 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-test-runner
178 08:04:47.711160 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-test-set
179 08:04:47.711292 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-test-shell
180 08:04:47.711427 Updating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-add-keys (debian)
181 08:04:47.711600 Updating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-add-sources (debian)
182 08:04:47.711749 Updating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-install-packages (debian)
183 08:04:47.711896 Updating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-installed-packages (debian)
184 08:04:47.712051 Updating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/bin/lava-os-build (debian)
185 08:04:47.712180 Creating /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/environment
186 08:04:47.712282 LAVA metadata
187 08:04:47.712349 - LAVA_JOB_ID=743034
188 08:04:47.712402 - LAVA_DISPATCHER_IP=192.168.56.193
189 08:04:47.712515 start: 1.6.2.1 ssh-authorize (timeout 00:08:28) [common]
190 08:04:47.712832 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 08:04:47.712918 start: 1.6.2.2 lava-vland-overlay (timeout 00:08:28) [common]
192 08:04:47.712976 skipped lava-vland-overlay
193 08:04:47.713039 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 08:04:47.713104 start: 1.6.2.3 lava-multinode-overlay (timeout 00:08:28) [common]
195 08:04:47.713156 skipped lava-multinode-overlay
196 08:04:47.713216 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 08:04:47.713281 start: 1.6.2.4 test-definition (timeout 00:08:28) [common]
198 08:04:47.713344 Loading test definitions
199 08:04:47.713413 start: 1.6.2.4.1 inline-repo-action (timeout 00:08:28) [common]
200 08:04:47.713470 Using /lava-743034 at stage 0
201 08:04:47.713866 uuid=743034_1.6.2.4.1 testdef=None
202 08:04:47.713949 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 08:04:47.714018 start: 1.6.2.4.2 test-overlay (timeout 00:08:28) [common]
204 08:04:47.714469 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 08:04:47.714665 start: 1.6.2.4.3 test-install-overlay (timeout 00:08:28) [common]
207 08:04:47.720052 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 08:04:47.720373 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:08:28) [common]
210 08:04:47.720967 runner path: /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/0/tests/0_timesync-off test_uuid 743034_1.6.2.4.1
211 08:04:47.721163 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 08:04:47.721370 start: 1.6.2.4.5 git-repo-action (timeout 00:08:28) [common]
214 08:04:47.721430 Using /lava-743034 at stage 0
215 08:04:47.721527 Fetching tests from https://github.com/kernelci/test-definitions.git
216 08:04:47.721628 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/0/tests/1_kselftest-dt'
217 08:04:53.690820 Running '/usr/bin/git checkout kernelci.org
218 08:04:53.865742 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 08:04:53.866551 uuid=743034_1.6.2.4.5 testdef=None
220 08:04:53.866755 end: 1.6.2.4.5 git-repo-action (duration 00:00:06) [common]
222 08:04:53.867100 start: 1.6.2.4.6 test-overlay (timeout 00:08:22) [common]
223 08:04:53.867861 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 08:04:53.868065 start: 1.6.2.4.7 test-install-overlay (timeout 00:08:22) [common]
226 08:04:53.869064 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 08:04:53.869281 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:08:22) [common]
229 08:04:53.870257 runner path: /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/0/tests/1_kselftest-dt test_uuid 743034_1.6.2.4.5
230 08:04:53.870340 BOARD='beaglebone-black'
231 08:04:53.870394 BRANCH='next'
232 08:04:53.870442 SKIPFILE='/dev/null'
233 08:04:53.870489 SKIP_INSTALL='True'
234 08:04:53.870536 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
235 08:04:53.870585 TST_CASENAME=''
236 08:04:53.870632 TST_CMDFILES='dt'
237 08:04:53.870794 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 08:04:53.870985 Creating lava-test-runner.conf files
240 08:04:53.871041 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/743034/lava-overlay-dtmesglt/lava-743034/0 for stage 0
241 08:04:53.871131 - 0_timesync-off
242 08:04:53.871189 - 1_kselftest-dt
243 08:04:53.871277 end: 1.6.2.4 test-definition (duration 00:00:06) [common]
244 08:04:53.871352 start: 1.6.2.5 compress-overlay (timeout 00:08:22) [common]
245 08:05:02.047859 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 08:05:02.048026 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:13) [common]
247 08:05:02.048101 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 08:05:02.048180 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
249 08:05:02.048251 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:13) [common]
250 08:05:02.174977 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 08:05:02.175263 start: 1.6.4 extract-modules (timeout 00:08:13) [common]
252 08:05:02.175415 extracting modules file /var/lib/lava/dispatcher/tmp/743034/tftp-deploy-7mwwifo5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/743034/extract-nfsrootfs-j23pg8dq
253 08:05:02.467978 extracting modules file /var/lib/lava/dispatcher/tmp/743034/tftp-deploy-7mwwifo5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/743034/extract-overlay-ramdisk-5ynx4e_2/ramdisk
254 08:05:02.762987 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 08:05:02.763164 start: 1.6.5 apply-overlay-tftp (timeout 00:08:13) [common]
256 08:05:02.763250 [common] Applying overlay to NFS
257 08:05:02.763304 [common] Applying overlay /var/lib/lava/dispatcher/tmp/743034/compress-overlay-5iah6xm0/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/743034/extract-nfsrootfs-j23pg8dq
258 08:05:03.768639 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 08:05:03.768811 start: 1.6.6 prepare-kernel (timeout 00:08:12) [common]
260 08:05:03.768891 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:12) [common]
261 08:05:03.768968 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 08:05:03.769035 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 08:05:03.769102 start: 1.6.7 configure-preseed-file (timeout 00:08:12) [common]
264 08:05:03.769167 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 08:05:03.769233 start: 1.6.8 compress-ramdisk (timeout 00:08:12) [common]
266 08:05:03.769292 Building ramdisk /var/lib/lava/dispatcher/tmp/743034/extract-overlay-ramdisk-5ynx4e_2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/743034/extract-overlay-ramdisk-5ynx4e_2/ramdisk
267 08:05:04.068202 >> 74933 blocks
268 08:05:05.789588 Adding RAMdisk u-boot header.
269 08:05:05.789888 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/743034/extract-overlay-ramdisk-5ynx4e_2/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/743034/extract-overlay-ramdisk-5ynx4e_2/ramdisk.cpio.gz.uboot
270 08:05:05.892044 output: Image Name:
271 08:05:05.892289 output: Created: Thu Sep 19 08:05:05 2024
272 08:05:05.892419 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 08:05:05.892560 output: Data Size: 14798828 Bytes = 14451.98 KiB = 14.11 MiB
274 08:05:05.892676 output: Load Address: 00000000
275 08:05:05.892786 output: Entry Point: 00000000
276 08:05:05.892891 output:
277 08:05:05.893141 rename /var/lib/lava/dispatcher/tmp/743034/extract-overlay-ramdisk-5ynx4e_2/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/743034/tftp-deploy-7mwwifo5/ramdisk/ramdisk.cpio.gz.uboot
278 08:05:05.893365 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
279 08:05:05.893542 end: 1.6 prepare-tftp-overlay (duration 00:00:23) [common]
280 08:05:05.893739 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:10) [common]
281 08:05:05.893881 No LXC device requested
282 08:05:05.894026 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 08:05:05.894213 start: 1.8 deploy-device-env (timeout 00:08:10) [common]
284 08:05:05.894359 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 08:05:05.894478 Checking files for TFTP limit of 4294967296 bytes.
286 08:05:05.895510 end: 1 tftp-deploy (duration 00:01:50) [common]
287 08:05:05.895744 start: 2 uboot-action (timeout 00:05:00) [common]
288 08:05:05.895975 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 08:05:05.896165 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 08:05:05.896350 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 08:05:05.896647 substitutions:
292 08:05:05.896797 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 08:05:05.896935 - {DTB_ADDR}: 0x88000000
294 08:05:05.897070 - {DTB}: 743034/tftp-deploy-7mwwifo5/dtb/am335x-boneblack.dtb
295 08:05:05.897205 - {INITRD}: 743034/tftp-deploy-7mwwifo5/ramdisk/ramdisk.cpio.gz.uboot
296 08:05:05.897339 - {KERNEL_ADDR}: 0x82000000
297 08:05:05.897473 - {KERNEL}: 743034/tftp-deploy-7mwwifo5/kernel/zImage
298 08:05:05.897636 - {LAVA_MAC}: None
299 08:05:05.897800 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/743034/extract-nfsrootfs-j23pg8dq
300 08:05:05.897938 - {NFS_SERVER_IP}: 192.168.56.193
301 08:05:05.898072 - {PRESEED_CONFIG}: None
302 08:05:05.898204 - {PRESEED_LOCAL}: None
303 08:05:05.898335 - {RAMDISK_ADDR}: 0x83000000
304 08:05:05.898469 - {RAMDISK}: 743034/tftp-deploy-7mwwifo5/ramdisk/ramdisk.cpio.gz.uboot
305 08:05:05.898602 - {ROOT_PART}: None
306 08:05:05.898734 - {ROOT}: None
307 08:05:05.898867 - {SERVER_IP}: 192.168.56.193
308 08:05:05.898999 - {TEE_ADDR}: 0x83000000
309 08:05:05.899130 - {TEE}: None
310 08:05:05.899262 Parsed boot commands:
311 08:05:05.899390 - setenv autoload no
312 08:05:05.899522 - setenv initrd_high 0xffffffff
313 08:05:05.899651 - setenv fdt_high 0xffffffff
314 08:05:05.899780 - dhcp
315 08:05:05.899909 - setenv serverip 192.168.56.193
316 08:05:05.900038 - tftp 0x82000000 743034/tftp-deploy-7mwwifo5/kernel/zImage
317 08:05:05.900168 - tftp 0x83000000 743034/tftp-deploy-7mwwifo5/ramdisk/ramdisk.cpio.gz.uboot
318 08:05:05.900299 - setenv initrd_size ${filesize}
319 08:05:05.900429 - tftp 0x88000000 743034/tftp-deploy-7mwwifo5/dtb/am335x-boneblack.dtb
320 08:05:05.900560 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/743034/extract-nfsrootfs-j23pg8dq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 08:05:05.900734 - bootz 0x82000000 0x83000000 0x88000000
322 08:05:05.900931 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 08:05:05.901486 start: 2.3 connect-device (timeout 00:05:00) [common]
325 08:05:05.901666 [common] connect-device Connecting to device using 'telnet conserv3 3002'
326 08:05:05.910915 Setting prompt string to ['lava-test: # ']
327 08:05:05.911673 end: 2.3 connect-device (duration 00:00:00) [common]
328 08:05:05.911896 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 08:05:05.912075 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 08:05:05.912274 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 08:05:05.912688 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
332 08:05:05.932692 >> OK - accepted request
333 08:05:05.934461 Returned 0 in 0 seconds
334 08:05:06.034825 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
336 08:05:06.035179 end: 2.4.1 reset-device (duration 00:00:00) [common]
337 08:05:06.035267 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
338 08:05:06.035357 Setting prompt string to ['Hit any key to stop autoboot']
339 08:05:06.035510 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
340 08:05:06.036331 Trying 192.168.56.22...
341 08:05:06.036527 Connected to conserv3.
342 08:05:06.036708 Escape character is '^]'.
343 08:05:06.036887
344 08:05:06.037039 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
345 08:05:06.037193
346 08:05:13.719296
347 08:05:13.726594 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
348 08:05:13.727003 Trying to boot from MMC1
349 08:05:17.774811
350 08:05:17.781891 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
351 08:05:17.782116 Trying to boot from MMC1
352 08:05:20.465426
353 08:05:20.471775 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
354 08:05:20.472016 Trying to boot from MMC1
355 08:05:21.056379
356 08:05:21.056629
357 08:05:21.061876 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
358 08:05:21.062046
359 08:05:21.062180 CPU : AM335X-GP rev 2.0
360 08:05:21.067084 Model: TI AM335x BeagleBone Black
361 08:05:21.067252 DRAM: 512 MiB
362 08:05:21.146781 Core: 160 devices, 18 uclasses, devicetree: separate
363 08:05:21.160971 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
364 08:05:21.561487 NAND: 0 MiB
365 08:05:21.572013 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
366 08:05:21.688039 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
367 08:05:21.710379 <ethaddr> not set. Validating first E-fuse MAC
368 08:05:21.740620 Net: eth2: ethernet@4a100000, eth3: usb_ether
370 08:05:21.798880 Hit any key to stop autoboot: 2
371 08:05:21.799319 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
372 08:05:21.799525 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
373 08:05:21.799688 Setting prompt string to ['=>']
374 08:05:21.799827 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
375 08:05:21.809049 0
376 08:05:21.809481 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
377 08:05:21.809654 Sending with 10 millisecond of delay
379 08:05:22.944041 => setenv autoload no
380 08:05:22.954562 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
381 08:05:22.956471 setenv autoload no
382 08:05:22.956869 Sending with 10 millisecond of delay
384 08:05:24.766316 => setenv initrd_high 0xffffffff
385 08:05:24.777121 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
386 08:05:24.777740 setenv initrd_high 0xffffffff
387 08:05:24.778141 Sending with 10 millisecond of delay
389 08:05:26.405374 => setenv fdt_high 0xffffffff
390 08:05:26.416121 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
391 08:05:26.416643 setenv fdt_high 0xffffffff
392 08:05:26.417032 Sending with 10 millisecond of delay
394 08:05:26.710609 => dhcp
395 08:05:26.721366 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
396 08:05:26.721881 dhcp
397 08:05:26.723474 link up on port 0, speed 100, full duplex
398 08:05:26.723775 BOOTP broadcast 1
399 08:05:26.976188 BOOTP broadcast 2
400 08:05:27.478241 BOOTP broadcast 3
401 08:05:28.480189 BOOTP broadcast 4
402 08:05:28.505054 *** Unhandled DHCP Option in OFFER/ACK: 42
403 08:05:28.534770 *** Unhandled DHCP Option in OFFER/ACK: 42
404 08:05:28.541505 DHCP client bound to address 192.168.56.11 (1814 ms)
405 08:05:28.542048 Sending with 10 millisecond of delay
407 08:05:30.413245 => setenv serverip 192.168.56.193
408 08:05:30.423815 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
409 08:05:30.424365 setenv serverip 192.168.56.193
410 08:05:30.424780 Sending with 10 millisecond of delay
412 08:05:33.932248 => tftp 0x82000000 743034/tftp-deploy-7mwwifo5/kernel/zImage
413 08:05:33.943119 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
414 08:05:33.943609 tftp 0x82000000 743034/tftp-deploy-7mwwifo5/kernel/zImage
415 08:05:33.943783 link up on port 0, speed 100, full duplex
416 08:05:33.947864 Using ethernet@4a100000 device
417 08:05:33.953661 TFTP from server 192.168.56.193; our IP address is 192.168.56.11
418 08:05:33.960187 Filename '743034/tftp-deploy-7mwwifo5/kernel/zImage'.
419 08:05:33.960484 Load address: 0x82000000
420 08:05:37.071070 Loading: *################################################## 10.9 MiB
421 08:05:37.071347 3.5 MiB/s
422 08:05:37.071503 done
423 08:05:37.075833 Bytes transferred = 11457024 (aed200 hex)
424 08:05:37.076426 Sending with 10 millisecond of delay
426 08:05:41.526830 => tftp 0x83000000 743034/tftp-deploy-7mwwifo5/ramdisk/ramdisk.cpio.gz.uboot
427 08:05:41.537270 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
428 08:05:41.537750 tftp 0x83000000 743034/tftp-deploy-7mwwifo5/ramdisk/ramdisk.cpio.gz.uboot
429 08:05:41.537935 link up on port 0, speed 100, full duplex
430 08:05:41.542235 Using ethernet@4a100000 device
431 08:05:41.547723 TFTP from server 192.168.56.193; our IP address is 192.168.56.11
432 08:05:41.551035 Filename '743034/tftp-deploy-7mwwifo5/ramdisk/ramdisk.cpio.gz.uboot'.
433 08:05:41.556382 Load address: 0x83000000
434 08:05:45.721364 Loading: *################################################## 14.1 MiB
435 08:05:45.721741 3.4 MiB/s
436 08:05:45.721900 done
437 08:05:45.725731 Bytes transferred = 14798892 (e1d02c hex)
438 08:05:45.726274 Sending with 10 millisecond of delay
440 08:05:47.594421 => setenv initrd_size ${filesize}
441 08:05:47.604992 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
442 08:05:47.605426 setenv initrd_size ${filesize}
443 08:05:47.605821 Sending with 10 millisecond of delay
445 08:05:51.758268 => tftp 0x88000000 743034/tftp-deploy-7mwwifo5/dtb/am335x-boneblack.dtb
446 08:05:51.769047 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
447 08:05:51.769705 tftp 0x88000000 743034/tftp-deploy-7mwwifo5/dtb/am335x-boneblack.dtb
448 08:05:51.769912 link up on port 0, speed 100, full duplex
449 08:05:51.774327 Using ethernet@4a100000 device
450 08:05:51.779799 TFTP from server 192.168.56.193; our IP address is 192.168.56.11
451 08:05:51.793805 Filename '743034/tftp-deploy-7mwwifo5/dtb/am335x-boneblack.dtb'.
452 08:05:51.794063 Load address: 0x88000000
453 08:05:51.810034 Loading: *################################################## 68.9 KiB
454 08:05:51.810277 2.8 MiB/s
455 08:05:51.819171 done
456 08:05:51.819475 Bytes transferred = 70568 (113a8 hex)
457 08:05:51.819908 Sending with 10 millisecond of delay
459 08:06:05.200257 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/743034/extract-nfsrootfs-j23pg8dq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
460 08:06:05.210680 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
461 08:06:05.211328 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/743034/extract-nfsrootfs-j23pg8dq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
462 08:06:05.211714 Sending with 10 millisecond of delay
464 08:06:07.551881 => bootz 0x82000000 0x83000000 0x88000000
465 08:06:07.562319 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
466 08:06:07.562591 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
467 08:06:07.562997 bootz 0x82000000 0x83000000 0x88000000
468 08:06:07.563161 Kernel image @ 0x82000000 [ 0x000000 - 0xaed200 ]
469 08:06:07.564186 ## Loading init Ramdisk from Legacy Image at 83000000 ...
470 08:06:07.569820 Image Name:
471 08:06:07.570057 Created: 2024-09-19 8:05:05 UTC
472 08:06:07.573270 Image Type: ARM Linux RAMDisk Image (uncompressed)
473 08:06:07.578687 Data Size: 14798828 Bytes = 14.1 MiB
474 08:06:07.586317 Load Address: 00000000
475 08:06:07.586561 Entry Point: 00000000
476 08:06:07.755423 Verifying Checksum ... OK
477 08:06:07.755695 ## Flattened Device Tree blob at 88000000
478 08:06:07.762287 Booting using the fdt blob at 0x88000000
479 08:06:07.762527 Working FDT set to 88000000
480 08:06:07.767794 Using Device Tree in place at 88000000, end 880143a7
481 08:06:07.772666 Working FDT set to 88000000
482 08:06:07.784932
483 08:06:07.785186 Starting kernel ...
484 08:06:07.785345
485 08:06:07.785787 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
486 08:06:07.786009 start: 2.4.4 auto-login-action (timeout 00:03:58) [common]
487 08:06:07.786188 Setting prompt string to ['Linux version [0-9]']
488 08:06:07.786351 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
489 08:06:07.786513 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
490 08:06:08.629694 [ 0.000000] Booting Linux on physical CPU 0x0
491 08:06:08.635713 start: 2.4.4.1 login-action (timeout 00:03:57) [common]
492 08:06:08.636046 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
493 08:06:08.636282 Setting prompt string to []
494 08:06:08.636543 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
495 08:06:08.636791 Using line separator: #'\n'#
496 08:06:08.637000 No login prompt set.
497 08:06:08.637198 Parsing kernel messages
498 08:06:08.637373 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
499 08:06:08.637767 [login-action] Waiting for messages, (timeout 00:03:57)
500 08:06:08.637970 Waiting using forced prompt support (timeout 00:01:59)
501 08:06:08.653002 [ 0.000000] Linux version 6.11.0-next-20240919 (KernelCI@build-j314455-arm-gcc-12-multi-v7-defconfig-6hr6q) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Thu Sep 19 07:22:06 UTC 2024
502 08:06:08.658507 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
503 08:06:08.669479 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
504 08:06:08.676314 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
505 08:06:08.683467 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
506 08:06:08.687949 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
507 08:06:08.693394 [ 0.000000] Memory policy: Data cache writeback
508 08:06:08.693681 [ 0.000000] efi: UEFI not found.
509 08:06:08.699285 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
510 08:06:08.705750 [ 0.000000] Zone ranges:
511 08:06:08.711179 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
512 08:06:08.716882 [ 0.000000] Normal empty
513 08:06:08.717106 [ 0.000000] HighMem empty
514 08:06:08.722623 [ 0.000000] Movable zone start for each node
515 08:06:08.722898 [ 0.000000] Early memory node ranges
516 08:06:08.734392 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
517 08:06:08.738754 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
518 08:06:08.764830 [ 0.000000] CPU: All CPU(s) started in SVC mode.
519 08:06:08.770315 [ 0.000000] AM335X ES2.0 (sgx neon)
520 08:06:08.782452 [ 0.000000] percpu: Embedded 17 pages/cpu s40908 r8192 d20532 u69632
521 08:06:08.799939 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/743034/extract-nfsrootfs-j23pg8dq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
522 08:06:08.811239 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
523 08:06:08.817114 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
524 08:06:08.822719 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
525 08:06:08.832675 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
526 08:06:08.862182 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
527 08:06:08.868139 <6>[ 0.000000] trace event string verifier disabled
528 08:06:08.868389 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
529 08:06:08.873855 <6>[ 0.000000] rcu: RCU event tracing is enabled.
530 08:06:08.885155 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
531 08:06:08.890932 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
532 08:06:08.898257 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
533 08:06:08.912534 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
534 08:06:08.930249 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
535 08:06:08.936698 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
536 08:06:09.029177 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
537 08:06:09.040174 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
538 08:06:09.046830 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
539 08:06:09.059814 <6>[ 0.019151] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
540 08:06:09.067376 <6>[ 0.033931] Console: colour dummy device 80x30
541 08:06:09.073430 Matched prompt #6: WARNING:
542 08:06:09.073718 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
543 08:06:09.078720 <3>[ 0.038835] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
544 08:06:09.084550 <3>[ 0.045909] This ensures that you still see kernel messages. Please
545 08:06:09.086820 <3>[ 0.052634] update your kernel commandline.
546 08:06:09.128516 <6>[ 0.057245] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
547 08:06:09.134183 <6>[ 0.096155] CPU: Testing write buffer coherency: ok
548 08:06:09.140521 <6>[ 0.101524] CPU0: Spectre v2: using BPIALL workaround
549 08:06:09.140744 <6>[ 0.106988] pid_max: default: 32768 minimum: 301
550 08:06:09.151547 <6>[ 0.112181] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
551 08:06:09.158604 <6>[ 0.120011] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
552 08:06:09.165830 <6>[ 0.129376] CPU0: thread -1, cpu 0, socket -1, mpidr 0
553 08:06:09.173993 <6>[ 0.136389] Setting up static identity map for 0x80300000 - 0x803000ac
554 08:06:09.179963 <6>[ 0.146026] rcu: Hierarchical SRCU implementation.
555 08:06:09.186609 <6>[ 0.151310] rcu: Max phase no-delay instances is 1000.
556 08:06:09.195997 <6>[ 0.162440] EFI services will not be available.
557 08:06:09.201816 <6>[ 0.167725] smp: Bringing up secondary CPUs ...
558 08:06:09.207724 <6>[ 0.172773] smp: Brought up 1 node, 1 CPU
559 08:06:09.213365 <6>[ 0.177175] SMP: Total of 1 processors activated (996.14 BogoMIPS).
560 08:06:09.219855 <6>[ 0.183945] CPU: All CPU(s) started in SVC mode.
561 08:06:09.239171 <6>[ 0.189126] Memory: 405980K/522240K available (16384K kernel code, 2548K rwdata, 6788K rodata, 2048K init, 433K bss, 49068K reserved, 65536K cma-reserved, 0K highmem)
562 08:06:09.239429 <6>[ 0.205401] devtmpfs: initialized
563 08:06:09.261897 <6>[ 0.222617] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
564 08:06:09.270207 <6>[ 0.231201] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
565 08:06:09.279391 <6>[ 0.241661] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
566 08:06:09.289325 <6>[ 0.253975] pinctrl core: initialized pinctrl subsystem
567 08:06:09.299506 <6>[ 0.264646] DMI not present or invalid.
568 08:06:09.307862 <6>[ 0.270508] NET: Registered PF_NETLINK/PF_ROUTE protocol family
569 08:06:09.316759 <6>[ 0.279399] DMA: preallocated 256 KiB pool for atomic coherent allocations
570 08:06:09.331454 <6>[ 0.290968] thermal_sys: Registered thermal governor 'step_wise'
571 08:06:09.331706 <6>[ 0.291136] cpuidle: using governor menu
572 08:06:09.360125 <6>[ 0.326779] No ATAGs?
573 08:06:09.365427 <6>[ 0.329519] hw-breakpoint: debug architecture 0x4 unsupported.
574 08:06:09.375996 <6>[ 0.341518] Serial: AMBA PL011 UART driver
575 08:06:09.409202 <6>[ 0.375331] iommu: Default domain type: Translated
576 08:06:09.417166 <6>[ 0.380681] iommu: DMA domain TLB invalidation policy: strict mode
577 08:06:09.444594 <5>[ 0.410374] SCSI subsystem initialized
578 08:06:09.450266 <6>[ 0.415264] usbcore: registered new interface driver usbfs
579 08:06:09.456075 <6>[ 0.421321] usbcore: registered new interface driver hub
580 08:06:09.462763 <6>[ 0.427101] usbcore: registered new device driver usb
581 08:06:09.468485 <6>[ 0.433628] pps_core: LinuxPPS API ver. 1 registered
582 08:06:09.480019 <6>[ 0.439017] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
583 08:06:09.487310 <6>[ 0.448741] PTP clock support registered
584 08:06:09.487519 <6>[ 0.453205] EDAC MC: Ver: 3.0.0
585 08:06:09.535871 <6>[ 0.500840] scmi_core: SCMI protocol bus registered
586 08:06:09.552281 <6>[ 0.518202] vgaarb: loaded
587 08:06:09.558105 <6>[ 0.522056] clocksource: Switched to clocksource dmtimer
588 08:06:09.592455 <6>[ 0.558800] NET: Registered PF_INET protocol family
589 08:06:09.605137 <6>[ 0.564508] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
590 08:06:09.612252 <6>[ 0.573365] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
591 08:06:09.623670 <6>[ 0.582293] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
592 08:06:09.629591 <6>[ 0.590536] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
593 08:06:09.635479 <6>[ 0.598824] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
594 08:06:09.641103 <6>[ 0.606544] TCP: Hash tables configured (established 4096 bind 4096)
595 08:06:09.652546 <6>[ 0.613459] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
596 08:06:09.658497 <6>[ 0.620466] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
597 08:06:09.663697 <6>[ 0.628080] NET: Registered PF_UNIX/PF_LOCAL protocol family
598 08:06:09.750651 <6>[ 0.711691] RPC: Registered named UNIX socket transport module.
599 08:06:09.750923 <6>[ 0.718126] RPC: Registered udp transport module.
600 08:06:09.756508 <6>[ 0.723250] RPC: Registered tcp transport module.
601 08:06:09.764991 <6>[ 0.728355] RPC: Registered tcp-with-tls transport module.
602 08:06:09.770757 <6>[ 0.734282] RPC: Registered tcp NFSv4.1 backchannel transport module.
603 08:06:09.778031 <6>[ 0.741189] PCI: CLS 0 bytes, default 64
604 08:06:09.780222 <5>[ 0.747005] Initialise system trusted keyrings
605 08:06:09.802504 <6>[ 0.767127] Trying to unpack rootfs image as initramfs...
606 08:06:09.882366 <6>[ 0.842715] workingset: timestamp_bits=30 max_order=17 bucket_order=0
607 08:06:09.886140 <6>[ 0.850207] squashfs: version 4.0 (2009/01/31) Phillip Lougher
608 08:06:09.926598 <5>[ 0.893138] NFS: Registering the id_resolver key type
609 08:06:09.932345 <5>[ 0.898744] Key type id_resolver registered
610 08:06:09.939131 <5>[ 0.903411] Key type id_legacy registered
611 08:06:09.945005 <6>[ 0.907855] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
612 08:06:09.956413 <6>[ 0.915057] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
613 08:06:10.026034 <5>[ 0.992741] Key type asymmetric registered
614 08:06:10.032002 <5>[ 0.997268] Asymmetric key parser 'x509' registered
615 08:06:10.043506 <6>[ 1.002802] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
616 08:06:10.043785 <6>[ 1.010690] io scheduler mq-deadline registered
617 08:06:10.049501 <6>[ 1.015675] io scheduler kyber registered
618 08:06:10.054323 <6>[ 1.020129] io scheduler bfq registered
619 08:06:10.182036 <6>[ 1.145262] ledtrig-cpu: registered to indicate activity on CPUs
620 08:06:10.521467 <6>[ 1.484680] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
621 08:06:10.550499 <6>[ 1.517038] msm_serial: driver initialized
622 08:06:10.556722 <6>[ 1.521829] SuperH (H)SCI(F) driver initialized
623 08:06:10.562597 <6>[ 1.527174] STMicroelectronics ASC driver initialized
624 08:06:10.567026 <6>[ 1.532863] STM32 USART driver initialized
625 08:06:10.699390 <6>[ 1.666417] brd: module loaded
626 08:06:10.748232 <6>[ 1.714434] loop: module loaded
627 08:06:10.784091 <6>[ 1.749873] CAN device driver interface
628 08:06:10.790920 <6>[ 1.755141] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
629 08:06:10.796573 <6>[ 1.762176] e1000e: Intel(R) PRO/1000 Network Driver
630 08:06:10.802404 <6>[ 1.767562] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
631 08:06:10.808063 <6>[ 1.774009] igb: Intel(R) Gigabit Ethernet Network Driver
632 08:06:10.815766 <6>[ 1.779830] igb: Copyright (c) 2007-2014 Intel Corporation.
633 08:06:10.828146 <6>[ 1.789155] pegasus: Pegasus/Pegasus II USB Ethernet driver
634 08:06:10.834221 <6>[ 1.795309] usbcore: registered new interface driver pegasus
635 08:06:10.839757 <6>[ 1.801433] usbcore: registered new interface driver asix
636 08:06:10.845657 <6>[ 1.807317] usbcore: registered new interface driver ax88179_178a
637 08:06:10.851294 <6>[ 1.813906] usbcore: registered new interface driver cdc_ether
638 08:06:10.857174 <6>[ 1.820201] usbcore: registered new interface driver smsc75xx
639 08:06:10.862901 <6>[ 1.826439] usbcore: registered new interface driver smsc95xx
640 08:06:10.868764 <6>[ 1.832672] usbcore: registered new interface driver net1080
641 08:06:10.874589 <6>[ 1.838800] usbcore: registered new interface driver cdc_subset
642 08:06:10.880192 <6>[ 1.845206] usbcore: registered new interface driver zaurus
643 08:06:10.886889 <6>[ 1.851254] usbcore: registered new interface driver cdc_ncm
644 08:06:10.897943 <6>[ 1.860716] usbcore: registered new interface driver usb-storage
645 08:06:11.178497 <6>[ 2.144207] i2c_dev: i2c /dev entries driver
646 08:06:11.239659 <5>[ 2.198326] cpuidle: enable-method property 'ti,am3352' found operations
647 08:06:11.246107 <6>[ 2.207899] sdhci: Secure Digital Host Controller Interface driver
648 08:06:11.252924 <6>[ 2.214665] sdhci: Copyright(c) Pierre Ossman
649 08:06:11.260319 <6>[ 2.221059] Synopsys Designware Multimedia Card Interface Driver
650 08:06:11.265709 <6>[ 2.229025] sdhci-pltfm: SDHCI platform and OF driver helper
651 08:06:11.377516 <6>[ 2.337387] usbcore: registered new interface driver usbhid
652 08:06:11.377826 <6>[ 2.343550] usbhid: USB HID core driver
653 08:06:11.403880 <6>[ 2.368458] NET: Registered PF_INET6 protocol family
654 08:06:11.456640 <6>[ 2.423285] Segment Routing with IPv6
655 08:06:11.462353 <6>[ 2.427436] In-situ OAM (IOAM) with IPv6
656 08:06:11.469132 <6>[ 2.431839] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
657 08:06:11.474967 <6>[ 2.439211] NET: Registered PF_PACKET protocol family
658 08:06:11.480807 <6>[ 2.444788] can: controller area network core
659 08:06:11.486571 <6>[ 2.449611] NET: Registered PF_CAN protocol family
660 08:06:11.486794 <6>[ 2.454861] can: raw protocol
661 08:06:11.492721 <6>[ 2.458189] can: broadcast manager protocol
662 08:06:11.498907 <6>[ 2.462804] can: netlink gateway - max_hops=1
663 08:06:11.504971 <5>[ 2.468297] Key type dns_resolver registered
664 08:06:11.511365 <6>[ 2.473379] ThumbEE CPU extension supported.
665 08:06:11.511591 <5>[ 2.478069] Registering SWP/SWPB emulation handler
666 08:06:11.520988 <3>[ 2.483760] omap_voltage_late_init: Voltage driver support not added
667 08:06:11.717810 <5>[ 2.682969] Loading compiled-in X.509 certificates
668 08:06:11.852146 <6>[ 2.805865] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
669 08:06:11.858756 <6>[ 2.822586] pinctrl-single 44e10800.pinmux: 142 pins, size 568
670 08:06:11.884799 <3>[ 2.846247] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
671 08:06:12.090152 <3>[ 3.051750] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
672 08:06:12.286986 <6>[ 3.252829] OMAP GPIO hardware version 0.1
673 08:06:12.309097 <6>[ 3.271385] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
674 08:06:12.400938 <4>[ 3.363725] at24 2-0054: supply vcc not found, using dummy regulator
675 08:06:12.433969 <4>[ 3.396994] at24 2-0055: supply vcc not found, using dummy regulator
676 08:06:12.472063 <4>[ 3.435614] at24 2-0056: supply vcc not found, using dummy regulator
677 08:06:12.514818 <4>[ 3.477863] at24 2-0057: supply vcc not found, using dummy regulator
678 08:06:12.555077 <6>[ 3.519135] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
679 08:06:12.604742 <3>[ 3.565016] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
680 08:06:12.629208 <6>[ 3.585867] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
681 08:06:12.652039 <4>[ 3.612630] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
682 08:06:12.659161 <4>[ 3.621238] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
683 08:06:12.749586 <6>[ 3.712588] omap_rng 48310000.rng: Random Number Generator ver. 20
684 08:06:12.775185 <5>[ 3.739003] random: crng init done
685 08:06:12.835388 <6>[ 3.801929] Freeing initrd memory: 14456K
686 08:06:12.844352 <6>[ 3.806647] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
687 08:06:12.894108 <6>[ 3.854529] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
688 08:06:12.899868 <4>[ 3.864865] ------------[ cut here ]------------
689 08:06:12.911462 <4>[ 3.869902] WARNING: CPU: 0 PID: 38 at drivers/base/regmap/regmap.c:1208 devm_regmap_field_alloc+0xb8/0xc4
690 08:06:12.917123 <4>[ 3.880241] invalid empty mask defined
691 08:06:12.917323 <4>[ 3.884400] Modules linked in:
692 08:06:12.928545 <4>[ 3.887824] CPU: 0 UID: 0 PID: 38 Comm: kworker/u4:4 Not tainted 6.11.0-next-20240919 #1
693 08:06:12.934399 <4>[ 3.896421] Hardware name: Generic AM33XX (Flattened Device Tree)
694 08:06:12.940635 <4>[ 3.902959] Workqueue: events_unbound deferred_probe_work_func
695 08:06:12.940852 <4>[ 3.909240] Call trace:
696 08:06:12.945875 <4>[ 3.909258] unwind_backtrace from show_stack+0x10/0x14
697 08:06:12.951597 <4>[ 3.917786] show_stack from dump_stack_lvl+0x68/0x74
698 08:06:12.959016 <4>[ 3.923267] dump_stack_lvl from __warn+0x7c/0x12c
699 08:06:12.963089 <4>[ 3.928480] __warn from warn_slowpath_fmt+0x124/0x190
700 08:06:12.968834 <4>[ 3.934046] warn_slowpath_fmt from devm_regmap_field_alloc+0xb8/0xc4
701 08:06:12.980297 <4>[ 3.940954] devm_regmap_field_alloc from cpsw_ale_create+0x124/0x368
702 08:06:12.986176 <4>[ 3.947876] cpsw_ale_create from cpsw_init_common+0x238/0x37c
703 08:06:12.992028 <4>[ 3.954156] cpsw_init_common from cpsw_probe+0x530/0xc60
704 08:06:12.997534 <4>[ 3.959989] cpsw_probe from platform_probe+0x5c/0xb0
705 08:06:13.003301 <4>[ 3.965470] platform_probe from really_probe+0xc8/0x2c8
706 08:06:13.009017 <4>[ 3.971212] really_probe from __driver_probe_device+0x88/0x19c
707 08:06:13.014774 <4>[ 3.977578] __driver_probe_device from driver_probe_device+0x30/0x104
708 08:06:13.020612 <4>[ 3.984569] driver_probe_device from __device_attach_driver+0x94/0x108
709 08:06:13.026255 <4>[ 3.991651] __device_attach_driver from bus_for_each_drv+0x90/0xe4
710 08:06:13.032565 <4>[ 3.998373] bus_for_each_drv from __device_attach+0xa8/0x1a4
711 08:06:13.043454 <4>[ 4.004559] __device_attach from bus_probe_device+0x88/0x8c
712 08:06:13.050148 <4>[ 4.010656] bus_probe_device from device_add+0x5b8/0x78c
713 08:06:13.055025 <4>[ 4.016485] device_add from of_platform_device_create_pdata+0x90/0xbc
714 08:06:13.060935 <4>[ 4.023485] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
715 08:06:13.066461 <4>[ 4.031730] of_platform_bus_create from of_platform_populate+0x70/0xd4
716 08:06:13.077970 <4>[ 4.038815] of_platform_populate from sysc_probe+0x100c/0x1418
717 08:06:13.083872 <4>[ 4.045189] sysc_probe from platform_probe+0x5c/0xb0
718 08:06:13.089637 <4>[ 4.050662] platform_probe from really_probe+0xc8/0x2c8
719 08:06:13.095218 <4>[ 4.056405] really_probe from __driver_probe_device+0x88/0x19c
720 08:06:13.100873 <4>[ 4.062771] __driver_probe_device from driver_probe_device+0x30/0x104
721 08:06:13.106687 <4>[ 4.069759] driver_probe_device from __device_attach_driver+0x94/0x108
722 08:06:13.112434 <4>[ 4.076839] __device_attach_driver from bus_for_each_drv+0x90/0xe4
723 08:06:13.118167 <4>[ 4.083562] bus_for_each_drv from __device_attach+0xa8/0x1a4
724 08:06:13.125311 <4>[ 4.089748] __device_attach from bus_probe_device+0x88/0x8c
725 08:06:13.129966 <4>[ 4.095843] bus_probe_device from device_add+0x5b8/0x78c
726 08:06:13.142038 <4>[ 4.101671] device_add from of_platform_device_create_pdata+0x90/0xbc
727 08:06:13.146835 <4>[ 4.108662] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
728 08:06:13.152536 <4>[ 4.116905] of_platform_bus_create from of_platform_populate+0x70/0xd4
729 08:06:13.158269 <4>[ 4.123990] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
730 08:06:13.169800 <4>[ 4.130802] simple_pm_bus_probe from platform_probe+0x5c/0xb0
731 08:06:13.175616 <4>[ 4.137078] platform_probe from really_probe+0xc8/0x2c8
732 08:06:13.181368 <4>[ 4.142819] really_probe from __driver_probe_device+0x88/0x19c
733 08:06:13.186903 <4>[ 4.149185] __driver_probe_device from driver_probe_device+0x30/0x104
734 08:06:13.192821 <4>[ 4.156174] driver_probe_device from __device_attach_driver+0x94/0x108
735 08:06:13.198479 <4>[ 4.163253] __device_attach_driver from bus_for_each_drv+0x90/0xe4
736 08:06:13.204392 <4>[ 4.169975] bus_for_each_drv from __device_attach+0xa8/0x1a4
737 08:06:13.209900 <4>[ 4.176161] __device_attach from bus_probe_device+0x88/0x8c
738 08:06:13.215976 <4>[ 4.182258] bus_probe_device from device_add+0x5b8/0x78c
739 08:06:13.227119 <4>[ 4.188085] device_add from of_platform_device_create_pdata+0x90/0xbc
740 08:06:13.233745 <4>[ 4.195075] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
741 08:06:13.238616 <4>[ 4.203321] of_platform_bus_create from of_platform_populate+0x70/0xd4
742 08:06:13.250084 <4>[ 4.210404] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
743 08:06:13.256072 <4>[ 4.217217] simple_pm_bus_probe from platform_probe+0x5c/0xb0
744 08:06:13.261619 <4>[ 4.223494] platform_probe from really_probe+0xc8/0x2c8
745 08:06:13.267232 <4>[ 4.229237] really_probe from __driver_probe_device+0x88/0x19c
746 08:06:13.273065 <4>[ 4.235600] __driver_probe_device from driver_probe_device+0x30/0x104
747 08:06:13.278891 <4>[ 4.242592] driver_probe_device from __device_attach_driver+0x94/0x108
748 08:06:13.284556 <4>[ 4.249673] __device_attach_driver from bus_for_each_drv+0x90/0xe4
749 08:06:13.290206 <4>[ 4.256394] bus_for_each_drv from __device_attach+0xa8/0x1a4
750 08:06:13.301889 <4>[ 4.262579] __device_attach from bus_probe_device+0x88/0x8c
751 08:06:13.307462 <4>[ 4.268677] bus_probe_device from device_add+0x5b8/0x78c
752 08:06:13.313304 <4>[ 4.274502] device_add from of_platform_device_create_pdata+0x90/0xbc
753 08:06:13.318858 <4>[ 4.281489] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
754 08:06:13.324637 <4>[ 4.289732] of_platform_bus_create from of_platform_populate+0x70/0xd4
755 08:06:13.336066 <4>[ 4.296814] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
756 08:06:13.341892 <4>[ 4.303626] simple_pm_bus_probe from platform_probe+0x5c/0xb0
757 08:06:13.347553 <4>[ 4.309903] platform_probe from really_probe+0xc8/0x2c8
758 08:06:13.353419 <4>[ 4.315645] really_probe from __driver_probe_device+0x88/0x19c
759 08:06:13.359058 <4>[ 4.322012] __driver_probe_device from driver_probe_device+0x30/0x104
760 08:06:13.364993 <4>[ 4.329003] driver_probe_device from __device_attach_driver+0x94/0x108
761 08:06:13.370525 <4>[ 4.336083] __device_attach_driver from bus_for_each_drv+0x90/0xe4
762 08:06:13.382020 <4>[ 4.342804] bus_for_each_drv from __device_attach+0xa8/0x1a4
763 08:06:13.387870 <4>[ 4.348992] __device_attach from bus_probe_device+0x88/0x8c
764 08:06:13.393715 <4>[ 4.355088] bus_probe_device from deferred_probe_work_func+0x78/0xa4
765 08:06:13.399250 <4>[ 4.361985] deferred_probe_work_func from process_one_work+0x178/0x3c0
766 08:06:13.405536 <4>[ 4.369081] process_one_work from worker_thread+0x264/0x42c
767 08:06:13.410838 <4>[ 4.375183] worker_thread from kthread+0xe0/0xfc
768 08:06:13.416661 <4>[ 4.380311] kthread from ret_from_fork+0x14/0x28
769 08:06:13.422189 <4>[ 4.385428] Exception stack(0xe0131fb0 to 0xe0131ff8)
770 08:06:13.427867 <4>[ 4.390893] 1fa0: 00000000 00000000 00000000 00000000
771 08:06:13.439431 <4>[ 4.399574] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
772 08:06:13.445219 <4>[ 4.408255] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000
773 08:06:13.451118 <4>[ 4.415432] ---[ end trace 0000000000000000 ]---
774 08:06:13.451663 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
775 08:06:13.451871 login-action: kernel 'warning'
776 08:06:13.452098 [login-action] Waiting for messages, (timeout 00:03:52)
777 08:06:13.452288 Waiting using forced prompt support (timeout 00:01:56)
778 08:06:13.456856 <6>[ 4.420531] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
779 08:06:13.463135 <6>[ 4.427822] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
780 08:06:13.476246 <6>[ 4.435414] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
781 08:06:13.486124 <6>[ 4.443559] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
782 08:06:13.493832 <6>[ 4.455190] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
783 08:06:13.504950 <5>[ 4.464219] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
784 08:06:13.533028 <3>[ 4.493891] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
785 08:06:13.537744 <6>[ 4.502431] edma 49000000.dma: TI EDMA DMA engine driver
786 08:06:13.608544 <3>[ 4.569662] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
787 08:06:13.623235 <6>[ 4.584135] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
788 08:06:13.636211 <3>[ 4.601232] l3-aon-clkctrl:0000:0: failed to disable
789 08:06:13.682283 <6>[ 4.643206] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
790 08:06:13.687876 <6>[ 4.652665] printk: legacy console [ttyS0] enabled
791 08:06:13.693758 <6>[ 4.652665] printk: legacy console [ttyS0] enabled
792 08:06:13.699169 <6>[ 4.662990] printk: legacy bootconsole [omap8250] disabled
793 08:06:13.704189 <6>[ 4.662990] printk: legacy bootconsole [omap8250] disabled
794 08:06:13.743395 <4>[ 4.702862] tps65217-pmic: Failed to locate of_node [id: -1]
795 08:06:13.747871 <4>[ 4.710259] tps65217-bl: Failed to locate of_node [id: -1]
796 08:06:13.763016 <6>[ 4.729885] tps65217 0-0024: TPS65217 ID 0xe version 1.2
797 08:06:13.781721 <6>[ 4.736829] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
798 08:06:13.793101 <6>[ 4.750535] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
799 08:06:13.797978 <6>[ 4.762484] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
800 08:06:13.821197 <6>[ 4.782492] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
801 08:06:13.826942 <6>[ 4.791548] sdhci-omap 48060000.mmc: Got CD GPIO
802 08:06:13.834435 <4>[ 4.796733] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
803 08:06:13.850164 <4>[ 4.810253] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
804 08:06:13.856065 <4>[ 4.818937] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
805 08:06:13.865071 <4>[ 4.827619] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
806 08:06:13.989039 <6>[ 4.952229] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
807 08:06:14.038481 <6>[ 4.998418] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
808 08:06:14.044900 <6>[ 5.007742] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
809 08:06:14.053229 <6>[ 5.016704] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
810 08:06:14.115731 <6>[ 5.080313] mmc1: new high speed MMC card at address 0001
811 08:06:14.123562 <6>[ 5.089178] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
812 08:06:14.137390 <6>[ 5.102596] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
813 08:06:14.144985 <6>[ 5.110630] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
814 08:06:14.158141 <6>[ 5.117200] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
815 08:06:14.165826 <6>[ 5.129822] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
816 08:06:14.223365 <6>[ 5.181632] mmc0: new high speed SDHC card at address aaaa
817 08:06:14.223632 <6>[ 5.189290] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
818 08:06:14.247679 <6>[ 5.213428] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
819 08:06:16.281686 <6>[ 7.243136] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
820 08:06:23.165357 <5>[ 7.282150] Sending DHCP requests ..., OK
821 08:06:23.176842 <6>[ 14.136716] IP-Config: Got DHCP answer from 192.168.56.254, my address is 192.168.56.11
822 08:06:23.177162 <6>[ 14.145247] IP-Config: Complete:
823 08:06:23.188038 <6>[ 14.148788] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.56.11, mask=255.255.255.0, gw=192.168.56.254
824 08:06:23.199393 <6>[ 14.159652] host=192.168.56.11, domain=mayfield.sirena.org.uk, nis-domain=(none)
825 08:06:23.205109 <6>[ 14.167865] bootserver=192.168.56.254, rootserver=192.168.56.193, rootpath=
826 08:06:23.211195 <6>[ 14.167900] nameserver0=192.168.56.254
827 08:06:23.217383 <6>[ 14.180165] ntpserver0=50.205.244.22, ntpserver1=85.199.214.99
828 08:06:23.223574 <6>[ 14.187817] clk: Disabling unused clocks
829 08:06:23.227191 <6>[ 14.192583] PM: genpd: Disabling unused power domains
830 08:06:23.248483 <6>[ 14.211864] Freeing unused kernel image (initmem) memory: 2048K
831 08:06:23.255923 <6>[ 14.221661] Run /init as init process
832 08:06:23.278582 Loading, please wait...
833 08:06:23.353994 Starting systemd-udevd version 252.22-1~deb12u1
834 08:06:26.299143 <4>[ 17.258864] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
835 08:06:26.456236 <4>[ 17.415848] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
836 08:06:26.645450 <6>[ 17.612332] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
837 08:06:26.656117 <6>[ 17.618005] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
838 08:06:26.860148 <6>[ 17.826604] hub 1-0:1.0: USB hub found
839 08:06:26.935822 <6>[ 17.902243] hub 1-0:1.0: 1 port detected
840 08:06:26.980256 <6>[ 17.946448] tda998x 0-0070: found TDA19988
841 08:06:30.099888 Begin: Loading essential drivers ... done.
842 08:06:30.115892 Begin: Running /scripts/init-premount ... done.
843 08:06:30.125976 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
844 08:06:30.141404 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
845 08:06:30.141817 Device /sys/class/net/eth0 found
846 08:06:30.141971 done.
847 08:06:30.201769 Begin: Waiting up to 180 secs for any network device to become available ... done.
848 08:06:30.298296 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
849 08:06:30.369682 IP-Config: eth0 complete (dhcp from 192.168.56.254):
850 08:06:30.380094 address: 192.168.56.11 broadcast: 192.168.56.255 netmask: 255.255.255.0
851 08:06:30.385812 gateway: 192.168.56.254 dns0 : 192.168.56.254 dns1 : 0.0.0.0
852 08:06:30.391826 domain : mayfield.sirena.org.uk
853 08:06:30.397321 rootserver: 192.168.56.254 rootpath:
854 08:06:30.397745 filename :
855 08:06:30.500462 done.
856 08:06:30.512499 Begin: Running /scripts/nfs-bottom ... done.
857 08:06:30.584267 Begin: Running /scripts/init-bottom ... done.
858 08:06:32.298289 <30>[ 23.258998] systemd[1]: System time before build time, advancing clock.
859 08:06:32.509439 <30>[ 23.444008] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
860 08:06:32.516926 <30>[ 23.481671] systemd[1]: Detected architecture arm.
861 08:06:32.537837
862 08:06:32.538163 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
863 08:06:32.538358
864 08:06:32.558471 <30>[ 23.522654] systemd[1]: Hostname set to <debian-bookworm-armhf>.
865 08:06:35.075826 <30>[ 26.038094] systemd[1]: Queued start job for default target graphical.target.
866 08:06:35.093218 <30>[ 26.053355] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
867 08:06:35.101244 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
868 08:06:35.124870 <30>[ 26.085097] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
869 08:06:35.132304 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
870 08:06:35.160556 <30>[ 26.115449] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
871 08:06:35.164151 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
872 08:06:35.184272 <30>[ 26.144126] systemd[1]: Created slice user.slice - User and Session Slice.
873 08:06:35.190698 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
874 08:06:35.219055 <30>[ 26.173438] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
875 08:06:35.223963 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
876 08:06:35.243938 <30>[ 26.203215] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
877 08:06:35.252324 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
878 08:06:35.283449 <30>[ 26.233198] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
879 08:06:35.289938 <30>[ 26.253891] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
880 08:06:35.298468 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
881 08:06:35.324469 <30>[ 26.282733] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
882 08:06:35.333303 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
883 08:06:35.355530 <30>[ 26.312996] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
884 08:06:35.363936 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
885 08:06:35.380998 <30>[ 26.344437] systemd[1]: Reached target paths.target - Path Units.
886 08:06:35.390981 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
887 08:06:35.413631 <30>[ 26.372707] systemd[1]: Reached target remote-fs.target - Remote File Systems.
888 08:06:35.418367 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
889 08:06:35.441539 <30>[ 26.402586] systemd[1]: Reached target slices.target - Slice Units.
890 08:06:35.446954 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
891 08:06:35.473475 <30>[ 26.433930] systemd[1]: Reached target swap.target - Swaps.
892 08:06:35.478620 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
893 08:06:35.505516 <30>[ 26.462822] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
894 08:06:35.509961 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
895 08:06:35.534997 <30>[ 26.493735] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
896 08:06:35.541503 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
897 08:06:35.636873 <30>[ 26.592415] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
898 08:06:35.650407 <30>[ 26.610359] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
899 08:06:35.661368 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
900 08:06:35.685810 <30>[ 26.644535] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
901 08:06:35.691353 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
902 08:06:35.721212 <30>[ 26.681586] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
903 08:06:35.729303 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
904 08:06:35.762265 <30>[ 26.724589] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
905 08:06:35.776040 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
906 08:06:35.803258 <30>[ 26.763829] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
907 08:06:35.810895 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
908 08:06:35.841514 <30>[ 26.793869] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
909 08:06:35.856393 <30>[ 26.810524] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
910 08:06:35.906074 <30>[ 26.867798] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
911 08:06:35.922225 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
912 08:06:35.982336 <30>[ 26.942997] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
913 08:06:35.999014 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
914 08:06:36.066639 <30>[ 27.026368] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
915 08:06:36.101487 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
916 08:06:36.166887 <30>[ 27.126152] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
917 08:06:36.175794 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
918 08:06:36.232598 <30>[ 27.194175] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
919 08:06:36.257620 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
920 08:06:36.279453 <30>[ 27.241161] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
921 08:06:36.297443 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
922 08:06:36.366464 <30>[ 27.323238] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
923 08:06:36.380835 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
924 08:06:36.444011 <30>[ 27.405965] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
925 08:06:36.468629 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
926 08:06:36.522286 <30>[ 27.483945] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
927 08:06:36.550866 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
928 08:06:36.563732 <28>[ 27.514590] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
929 08:06:36.578212 <28>[ 27.539182] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
930 08:06:36.622492 <30>[ 27.583459] systemd[1]: Starting systemd-journald.service - Journal Service...
931 08:06:36.630478 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
932 08:06:36.716606 <30>[ 27.675102] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
933 08:06:36.727587 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
934 08:06:36.795732 <30>[ 27.755324] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
935 08:06:36.806701 Starting [0;1;39msystemd-network-g… units from Kernel command line...
936 08:06:36.870130 <30>[ 27.826938] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
937 08:06:36.890057 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
938 08:06:36.949946 <30>[ 27.905150] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
939 08:06:36.955328 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
940 08:06:37.046882 <30>[ 28.007078] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
941 08:06:37.092401 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
942 08:06:37.124109 <30>[ 28.085819] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
943 08:06:37.166278 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
944 08:06:37.212709 <30>[ 28.172715] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
945 08:06:37.256647 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
946 08:06:37.542292 <30>[ 28.498821] systemd[1]: modprobe@configfs.service: Deactivated successfully.
947 08:06:37.581489 <30>[ 28.542908] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
948 08:06:37.624810 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
949 08:06:37.631696 <30>[ 28.593754] systemd[1]: Started systemd-journald.service - Journal Service.
950 08:06:37.662888 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
951 08:06:37.693679 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
952 08:06:37.718527 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
953 08:06:37.745147 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
954 08:06:37.767670 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
955 08:06:37.805013 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
956 08:06:37.843808 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
957 08:06:37.871652 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
958 08:06:37.892254 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
959 08:06:37.921641 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
960 08:06:37.986324 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
961 08:06:38.024824 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
962 08:06:38.098570 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
963 08:06:38.257743 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
964 08:06:38.366857 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
965 08:06:38.485108 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
966 08:06:38.875567 <46>[ 29.824519] systemd-journald[164]: Received client request to flush runtime journal.
967 08:06:38.890858 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
968 08:06:39.091314 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
969 08:06:40.215612 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
970 08:06:41.697232 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
971 08:06:41.745022 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
972 08:06:43.108130 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
973 08:06:43.298592 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
974 08:06:43.323261 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
975 08:06:43.345090 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
976 08:06:43.460107 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
977 08:06:43.504033 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
978 08:06:44.262458 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
979 08:06:44.373042 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
980 08:06:44.744563 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
981 08:06:44.920776 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
982 08:06:45.027518 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
983 08:06:46.933068 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
984 08:06:47.432189 <5>[ 38.395062] cfg80211: Loading compiled-in X.509 certificates for regulatory database
985 08:06:47.630026 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
986 08:06:49.309301 <5>[ 40.274542] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
987 08:06:49.457636 <5>[ 40.412555] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
988 08:06:49.479929 <4>[ 40.431413] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
989 08:06:49.485819 <6>[ 40.440551] cfg80211: failed to load regulatory.db
990 08:06:49.735073 [[0m[0;31m* [0m] (1 of 2) Job systemd-timesyncd.service/start running (14s / 1min 39s)
991 08:06:50.162615 <46>[ 41.115342] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
992 08:06:50.186530 M
[K[[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
993 08:06:50.289401 [K<46>[ 41.245551] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
994 08:06:50.448553 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
995 08:06:58.651806 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
996 08:06:58.671973 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
997 08:06:58.694264 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
998 08:06:58.717851 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
999 08:06:58.787018 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1000 08:06:58.855072 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1001 08:06:58.933312 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1002 08:06:58.988624 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1003 08:06:59.062388 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1004 08:06:59.087866 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1005 08:06:59.116317 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1006 08:06:59.159961 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1007 08:06:59.181325 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1008 08:06:59.220959 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1009 08:06:59.267841 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1010 08:06:59.286048 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1011 08:06:59.320019 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1012 08:06:59.361622 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1013 08:06:59.383066 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1014 08:06:59.402099 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1015 08:06:59.432087 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1016 08:06:59.452260 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1017 08:06:59.478567 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1018 08:06:59.564517 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1019 08:06:59.650674 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1020 08:06:59.789495 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1021 08:06:59.864590 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1022 08:06:59.943175 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1023 08:06:59.978670 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1024 08:07:00.018091 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1025 08:07:00.198701 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1026 08:07:00.267548 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1027 08:07:00.331342 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1028 08:07:00.352132 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1029 08:07:00.416701 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1030 08:07:00.622613 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
1031 08:07:00.716654 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1032 08:07:01.186206 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
1033 08:07:01.432051 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1034 08:07:01.490472 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1035 08:07:01.516336 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1036 08:07:01.595146 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1037 08:07:01.776100 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1038 08:07:01.939319
1039 08:07:01.943146 Debian GNU/Linux 12 dworm-armhf login: root (automatic login)
1040 08:07:01.943507
1041 08:07:02.352904 Linux debian-bookworm-armhf 6.11.0-next-20240919 #1 SMP Thu Sep 19 07:22:06 UTC 2024 armv7l
1042 08:07:02.353192
1043 08:07:02.358707 The programs included with the Debian GNU/Linux system are free software;
1044 08:07:02.367586 the exact distribution terms for each program are described in the
1045 08:07:02.367831 individual files in /usr/share/doc/*/copyright.
1046 08:07:02.367999
1047 08:07:02.373320 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1048 08:07:02.378585 permitted by applicable law.
1049 08:07:07.778246 Matched prompt #10: / #
1051 08:07:07.779151 Kernel warnings or errors detected.
1052 08:07:07.779277 Setting prompt string to ['/ #']
1053 08:07:07.779445 end: 2.4.4.1 login-action (duration 00:00:59) [common]
1055 08:07:07.780186 end: 2.4.4 auto-login-action (duration 00:01:00) [common]
1056 08:07:07.780357 start: 2.4.5 expect-shell-connection (timeout 00:02:58) [common]
1057 08:07:07.780495 Setting prompt string to ['/ #']
1058 08:07:07.780612 Forcing a shell prompt, looking for ['/ #']
1060 08:07:07.830981 / #
1061 08:07:07.831372 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1062 08:07:07.831559 Waiting using forced prompt support (timeout 00:02:30)
1063 08:07:07.835664
1064 08:07:07.842361 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1065 08:07:07.842528 start: 2.4.6 export-device-env (timeout 00:02:58) [common]
1066 08:07:07.842608 Sending with 10 millisecond of delay
1068 08:07:12.829986 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/743034/extract-nfsrootfs-j23pg8dq'
1069 08:07:12.840623 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/743034/extract-nfsrootfs-j23pg8dq'
1070 08:07:12.841068 Sending with 10 millisecond of delay
1072 08:07:15.119353 / # export NFS_SERVER_IP='192.168.56.193'
1073 08:07:15.129778 export NFS_SERVER_IP='192.168.56.193'
1074 08:07:15.130532 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1075 08:07:15.130770 end: 2.4 uboot-commands (duration 00:02:09) [common]
1076 08:07:15.130992 end: 2 uboot-action (duration 00:02:09) [common]
1077 08:07:15.131187 start: 3 lava-test-retry (timeout 00:06:00) [common]
1078 08:07:15.131390 start: 3.1 lava-test-shell (timeout 00:06:00) [common]
1079 08:07:15.131550 Using namespace: common
1081 08:07:15.232055 / # #
1082 08:07:15.232364 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1083 08:07:15.236958 #
1084 08:07:15.240565 Using /lava-743034
1086 08:07:15.341111 / # export SHELL=/bin/bash
1087 08:07:15.346019 export SHELL=/bin/bash
1089 08:07:15.452654 / # . /lava-743034/environment
1090 08:07:15.457592 . /lava-743034/environment
1092 08:07:15.570192 / # /lava-743034/bin/lava-test-runner /lava-743034/0
1093 08:07:15.570475 Test shell timeout: 10s (minimum of the action and connection timeout)
1094 08:07:15.575090 /lava-743034/bin/lava-test-runner /lava-743034/0
1095 08:07:15.975726 + export TESTRUN_ID=0_timesync-off
1096 08:07:15.982516 + TESTRUN_ID=0_timesync-off
1097 08:07:15.982694 + cd /lava-743034/0/tests/0_timesync-off
1098 08:07:15.982856 ++ cat uuid
1099 08:07:15.999716 + UUID=743034_1.6.2.4.1
1100 08:07:15.999911 + set +x
1101 08:07:16.008215 <LAVA_SIGNAL_STARTRUN 0_timesync-off 743034_1.6.2.4.1>
1102 08:07:16.008388 + systemctl stop systemd-timesyncd
1103 08:07:16.008761 Received signal: <STARTRUN> 0_timesync-off 743034_1.6.2.4.1
1104 08:07:16.008908 Starting test lava.0_timesync-off (743034_1.6.2.4.1)
1105 08:07:16.009110 Skipping test definition patterns.
1106 08:07:16.300373 + set +x
1107 08:07:16.300668 <LAVA_SIGNAL_ENDRUN 0_timesync-off 743034_1.6.2.4.1>
1108 08:07:16.301046 Received signal: <ENDRUN> 0_timesync-off 743034_1.6.2.4.1
1109 08:07:16.301233 Ending use of test pattern.
1110 08:07:16.301365 Ending test lava.0_timesync-off (743034_1.6.2.4.1), duration 0.29
1112 08:07:16.465522 + export TESTRUN_ID=1_kselftest-dt
1113 08:07:16.472679 + TESTRUN_ID=1_kselftest-dt
1114 08:07:16.472927 + cd /lava-743034/0/tests/1_kselftest-dt
1115 08:07:16.473094 ++ cat uuid
1116 08:07:16.489926 + UUID=743034_1.6.2.4.5
1117 08:07:16.490167 + set +x
1118 08:07:16.495647 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 743034_1.6.2.4.5>
1119 08:07:16.495880 + cd ./automated/linux/kselftest/
1120 08:07:16.496249 Received signal: <STARTRUN> 1_kselftest-dt 743034_1.6.2.4.5
1121 08:07:16.496389 Starting test lava.1_kselftest-dt (743034_1.6.2.4.5)
1122 08:07:16.496574 Skipping test definition patterns.
1123 08:07:16.521699 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1124 08:07:16.648141 INFO: install_deps skipped
1125 08:07:17.238235 --2024-09-19 08:07:17-- http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1126 08:07:17.272176 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1127 08:07:17.436342 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1128 08:07:17.599343 HTTP request sent, awaiting response... 200 OK
1129 08:07:17.599735 Length: 4112144 (3.9M) [application/octet-stream]
1130 08:07:17.604797 Saving to: 'kselftest_armhf.tar.gz'
1131 08:07:17.605188
1132 08:07:19.464708
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 155KB/s
kselftest_armhf.tar 4%[ ] 194.76K 300KB/s
kselftest_armhf.tar 18%[==> ] 747.85K 765KB/s
kselftest_armhf.tar 26%[====> ] 1.02M 881KB/s
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1133 08:07:19.465016
1134 08:07:20.177197 2024-09-19 08:07:19 (2.11 MB/s) - 'kselftest_armhf.tar.gz' saved [4112144/4112144]
1135 08:07:20.177460
1136 08:07:39.885661 skiplist:
1137 08:07:39.885962 ========================================
1138 08:07:39.891364 ========================================
1139 08:07:39.997902 dt:test_unprobed_devices.sh
1140 08:07:40.033668 ============== Tests to run ===============
1141 08:07:40.043740 dt:test_unprobed_devices.sh
1142 08:07:40.047651 ===========End Tests to run ===============
1143 08:07:40.058411 shardfile-dt pass
1144 08:07:40.320574 <12>[ 91.283822] kselftest: Running tests in dt
1145 08:07:40.347367 TAP version 13
1146 08:07:40.370902 1..1
1147 08:07:40.425950 # timeout set to 45
1148 08:07:40.426248 # selftests: dt: test_unprobed_devices.sh
1149 08:07:41.331587 # TAP version 13
1150 08:08:08.698199 # 1..257
1151 08:08:08.888642 # ok 1 / # SKIP
1152 08:08:08.914045 # ok 2 /clk_mcasp0
1153 08:08:08.991142 # ok 3 /clk_mcasp0_fixed # SKIP
1154 08:08:09.063822 # ok 4 /cpus/cpu@0 # SKIP
1155 08:08:09.158157 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1156 08:08:09.183075 # ok 6 /fixedregulator0
1157 08:08:09.208105 # ok 7 /leds
1158 08:08:09.224839 # ok 8 /ocp
1159 08:08:09.251894 # ok 9 /ocp/interconnect@44c00000
1160 08:08:09.280641 # ok 10 /ocp/interconnect@44c00000/segment@0
1161 08:08:09.299757 # ok 11 /ocp/interconnect@44c00000/segment@100000
1162 08:08:09.326828 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1163 08:08:09.404578 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1164 08:08:09.425166 # ok 14 /ocp/interconnect@44c00000/segment@200000
1165 08:08:09.449434 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1166 08:08:09.564122 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1167 08:08:09.648682 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1168 08:08:09.735170 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1169 08:08:09.817100 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1170 08:08:09.897909 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1171 08:08:09.979302 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1172 08:08:10.054328 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1173 08:08:10.141539 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1174 08:08:10.218921 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1175 08:08:10.305981 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1176 08:08:10.387380 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1177 08:08:10.469476 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1178 08:08:10.546096 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1179 08:08:10.634938 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1180 08:08:10.711078 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1181 08:08:10.798395 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1182 08:08:10.875703 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1183 08:08:10.964036 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1184 08:08:11.047150 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1185 08:08:11.133266 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1186 08:08:11.217881 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1187 08:08:11.293877 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1188 08:08:11.379189 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1189 08:08:11.456590 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1190 08:08:11.536357 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1191 08:08:11.620179 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1192 08:08:11.707825 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1193 08:08:11.789029 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1194 08:08:11.868238 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1195 08:08:11.938511 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1196 08:08:12.027747 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1197 08:08:12.110464 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1198 08:08:12.186523 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1199 08:08:12.270514 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1200 08:08:12.347882 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1201 08:08:12.435187 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1202 08:08:12.520125 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1203 08:08:12.592586 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1204 08:08:12.676804 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1205 08:08:12.755187 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1206 08:08:12.840580 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1207 08:08:12.925125 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1208 08:08:13.003034 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1209 08:08:13.087558 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1210 08:08:13.172746 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1211 08:08:13.268546 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1212 08:08:13.356131 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1213 08:08:13.448705 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1214 08:08:13.545022 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1215 08:08:13.625637 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1216 08:08:13.730129 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1217 08:08:13.823881 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1218 08:08:13.913031 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1219 08:08:14.003254 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1220 08:08:14.098079 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1221 08:08:14.198828 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1222 08:08:14.280520 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1223 08:08:14.377543 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1224 08:08:14.472550 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1225 08:08:14.571052 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1226 08:08:14.695914 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1227 08:08:14.788578 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1228 08:08:14.890378 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1229 08:08:14.994021 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1230 08:08:15.072460 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1231 08:08:15.184107 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1232 08:08:15.275694 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1233 08:08:15.380171 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1234 08:08:15.493891 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1235 08:08:15.589944 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1236 08:08:15.708399 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1237 08:08:15.836184 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1238 08:08:15.929794 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1239 08:08:16.071086 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1240 08:08:16.171650 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1241 08:08:16.277938 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1242 08:08:16.413164 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1243 08:08:16.571567 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1244 08:08:16.673468 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1245 08:08:16.727383 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1246 08:08:16.752633 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1247 08:08:16.788205 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1248 08:08:16.843436 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1249 08:08:16.914545 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1250 08:08:16.946522 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1251 08:08:16.973731 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1252 08:08:17.017465 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1253 08:08:17.270750 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1254 08:08:17.319169 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1255 08:08:17.368165 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1256 08:08:17.431450 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1257 08:08:18.005320 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1258 08:08:18.251250 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1259 08:08:18.336880 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1260 08:08:18.455947 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1261 08:08:18.553459 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1262 08:08:18.651135 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1263 08:08:18.757793 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1264 08:08:18.853837 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1265 08:08:18.960539 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1266 08:08:19.050310 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1267 08:08:19.169461 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1268 08:08:19.258193 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1269 08:08:19.375503 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1270 08:08:19.478952 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1271 08:08:19.587511 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1272 08:08:19.736196 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1273 08:08:19.770396 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1274 08:08:19.901129 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1275 08:08:20.033935 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1276 08:08:20.167921 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1277 08:08:20.217415 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1278 08:08:20.329783 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1279 08:08:20.363742 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1280 08:08:20.492738 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1281 08:08:20.531276 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1282 08:08:20.580470 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1283 08:08:20.642857 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1284 08:08:20.688907 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1285 08:08:20.735599 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1286 08:08:20.789928 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1287 08:08:20.848758 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1288 08:08:21.049068 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1289 08:08:21.108350 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1290 08:08:21.175595 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1291 08:08:21.399272 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1292 08:08:21.592316 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1293 08:08:21.625928 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1294 08:08:21.877882 # not ok 144 /ocp/interconnect@47c00000
1295 08:08:22.183609 # not ok 145 /ocp/interconnect@47c00000/segment@0
1296 08:08:22.285993 # ok 146 /ocp/interconnect@48000000
1297 08:08:22.368656 # ok 147 /ocp/interconnect@48000000/segment@0
1298 08:08:22.460031 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1299 08:08:22.562921 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1300 08:08:22.671485 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1301 08:08:22.787049 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1302 08:08:22.905310 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1303 08:08:23.032905 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1304 08:08:23.149910 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1305 08:08:23.317071 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1306 08:08:23.419172 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1307 08:08:23.450999 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1308 08:08:23.481589 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1309 08:08:23.512687 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1310 08:08:23.542650 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1311 08:08:23.575278 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1312 08:08:23.611211 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1313 08:08:23.645262 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1314 08:08:23.680917 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1315 08:08:23.705913 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1316 08:08:23.734951 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1317 08:08:23.766264 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1318 08:08:23.804468 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1319 08:08:23.847107 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1320 08:08:23.877495 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1321 08:08:23.897037 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1322 08:08:23.928513 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1323 08:08:23.963782 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1324 08:08:24.047229 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1325 08:08:24.066598 # ok 175 /ocp/interconnect@48000000/segment@100000
1326 08:08:24.094499 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1327 08:08:24.124298 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1328 08:08:24.289008 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1329 08:08:24.470400 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1330 08:08:24.610118 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1331 08:08:24.708177 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1332 08:08:24.843798 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1333 08:08:24.988208 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1334 08:08:25.099844 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1335 08:08:25.178868 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1336 08:08:25.200909 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1337 08:08:25.224940 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1338 08:08:25.250540 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1339 08:08:25.495811 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1340 08:08:25.511034 #
1341 08:08:25.514910 not ok 1 selftests: dt: test_unprobed_devices.sh # TIMEOUT 45 seconds
1342 08:08:28.019703 dt_test_unprobed_devices_sh_ skip
1343 08:08:28.030544 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1344 08:08:28.036649 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1345 08:08:28.036938 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1346 08:08:28.039902 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1347 08:08:28.040163 dt_test_unprobed_devices_sh_fixedregulator0 pass
1348 08:08:28.051060 dt_test_unprobed_devices_sh_leds pass
1349 08:08:28.057216 dt_test_unprobed_devices_sh_ocp pass
1350 08:08:28.057440 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1351 08:08:28.063509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1352 08:08:28.065771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1353 08:08:28.074815 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1354 08:08:28.080872 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1355 08:08:28.093813 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1356 08:08:28.097282 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1357 08:08:28.108422 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1358 08:08:28.114121 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1359 08:08:28.126474 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1360 08:08:28.136352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1361 08:08:28.147879 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1362 08:08:28.153172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1363 08:08:28.168226 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1364 08:08:28.180383 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1365 08:08:28.186884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1366 08:08:28.198478 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1367 08:08:28.203660 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1368 08:08:28.221104 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1369 08:08:28.226085 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1370 08:08:28.239794 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1371 08:08:28.244610 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1372 08:08:28.253972 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1373 08:08:28.265205 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1374 08:08:28.276388 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1375 08:08:28.281997 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1376 08:08:28.293099 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1377 08:08:28.304311 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1378 08:08:28.315555 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1379 08:08:28.329896 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1380 08:08:28.337989 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1381 08:08:28.343647 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1382 08:08:28.359433 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1383 08:08:28.368337 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1384 08:08:28.377250 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1385 08:08:28.388205 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1386 08:08:28.403584 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1387 08:08:28.411319 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1388 08:08:28.422090 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1389 08:08:28.437229 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1390 08:08:28.444259 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1391 08:08:28.455389 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1392 08:08:28.466559 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1393 08:08:28.479406 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1394 08:08:28.489067 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1395 08:08:28.500345 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1396 08:08:28.511790 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1397 08:08:28.523143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1398 08:08:28.534263 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1399 08:08:28.545610 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1400 08:08:28.556222 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1401 08:08:28.567496 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1402 08:08:28.578607 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1403 08:08:28.591147 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1404 08:08:28.603809 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1405 08:08:28.614735 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1406 08:08:28.617927 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1407 08:08:28.631305 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1408 08:08:28.640336 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1409 08:08:28.651595 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1410 08:08:28.663962 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1411 08:08:28.674339 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1412 08:08:28.685812 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1413 08:08:28.696753 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1414 08:08:28.708426 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1415 08:08:28.718880 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1416 08:08:28.730064 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1417 08:08:28.741261 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1418 08:08:28.754803 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1419 08:08:28.768328 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1420 08:08:28.775766 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1421 08:08:28.788646 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1422 08:08:28.798059 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1423 08:08:28.809017 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1424 08:08:28.820094 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1425 08:08:28.825127 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1426 08:08:28.836229 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1427 08:08:28.847536 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1428 08:08:28.858660 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1429 08:08:28.870827 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1430 08:08:28.883266 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1431 08:08:28.892987 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1432 08:08:28.903807 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1433 08:08:28.914641 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1434 08:08:28.925842 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1435 08:08:28.937782 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1436 08:08:28.951081 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1437 08:08:28.955935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1438 08:08:28.965895 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1439 08:08:28.977460 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1440 08:08:28.981950 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1441 08:08:28.993170 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1442 08:08:29.004339 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1443 08:08:29.009771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1444 08:08:29.021095 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1445 08:08:29.026576 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1446 08:08:29.038148 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1447 08:08:29.049163 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1448 08:08:29.060172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1449 08:08:29.072745 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1450 08:08:29.082503 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1451 08:08:29.093787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1452 08:08:29.104938 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1453 08:08:29.116053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1454 08:08:29.127319 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1455 08:08:29.138475 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1456 08:08:29.161636 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1457 08:08:29.186866 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1458 08:08:29.187185 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1459 08:08:29.188900 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1460 08:08:29.200450 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1461 08:08:29.217235 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1462 08:08:29.228065 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1463 08:08:29.239208 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1464 08:08:29.250917 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1465 08:08:29.262076 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1466 08:08:29.273273 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1467 08:08:29.278891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1468 08:08:29.290087 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1469 08:08:29.295677 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1470 08:08:29.307080 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1471 08:08:29.312011 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1472 08:08:29.324035 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1473 08:08:29.329221 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1474 08:08:29.339945 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1475 08:08:29.345795 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1476 08:08:29.358976 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1477 08:08:29.364251 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1478 08:08:29.374471 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1479 08:08:29.384789 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1480 08:08:29.396610 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1481 08:08:29.407205 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1482 08:08:29.418251 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1483 08:08:29.424168 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1484 08:08:29.435403 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1485 08:08:29.440794 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1486 08:08:29.446215 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1487 08:08:29.451900 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1488 08:08:29.457967 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1489 08:08:29.463661 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1490 08:08:29.474996 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1491 08:08:29.480270 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1492 08:08:29.491386 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1493 08:08:29.497137 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1494 08:08:29.508276 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1495 08:08:29.517826 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1496 08:08:29.518986 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1497 08:08:29.530693 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1498 08:08:29.536296 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1499 08:08:29.547176 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1500 08:08:29.552775 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1501 08:08:29.565354 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1502 08:08:29.569407 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1503 08:08:29.580631 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1504 08:08:29.586144 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1505 08:08:29.598026 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1506 08:08:29.603087 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1507 08:08:29.614590 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1508 08:08:29.620928 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1509 08:08:29.631310 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1510 08:08:29.637122 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1511 08:08:29.642389 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1512 08:08:29.653785 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1513 08:08:29.659058 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1514 08:08:29.670100 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1515 08:08:29.675870 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1516 08:08:29.687250 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1517 08:08:29.692904 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1518 08:08:29.703823 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1519 08:08:29.709776 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1520 08:08:29.721162 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1521 08:08:29.732938 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1522 08:08:29.744687 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1523 08:08:29.754287 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1524 08:08:29.765286 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1525 08:08:29.776476 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1526 08:08:29.787749 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1527 08:08:29.799189 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1528 08:08:29.804905 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1529 08:08:29.815889 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1530 08:08:29.821718 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1531 08:08:29.829310 dt_test_unprobed_devices_sh fail
1532 08:08:29.829631 + ../../utils/send-to-lava.sh ./output/result.txt
1533 08:08:29.920965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1534 08:08:29.921556 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1536 08:08:30.084882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1537 08:08:30.085362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1539 08:08:30.236008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1540 08:08:30.236350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1542 08:08:30.339019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1543 08:08:30.339453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1545 08:08:30.497306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1546 08:08:30.497908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1548 08:08:30.643074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1549 08:08:30.643576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1551 08:08:30.759391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1552 08:08:30.759967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1554 08:08:30.899855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1555 08:08:30.900363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1557 08:08:31.037375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1558 08:08:31.037959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1560 08:08:31.165431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1561 08:08:31.166039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1563 08:08:31.297395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1564 08:08:31.298014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1566 08:08:31.433175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1567 08:08:31.433583 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1569 08:08:31.647161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1570 08:08:31.647534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1572 08:08:31.751194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1573 08:08:31.751574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1575 08:08:31.854208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1576 08:08:31.854573 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1578 08:08:31.955607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1579 08:08:31.955977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1581 08:08:32.055393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1582 08:08:32.055755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1584 08:08:32.148491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1585 08:08:32.148868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1587 08:08:32.242722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1588 08:08:32.243101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1590 08:08:32.336243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1591 08:08:32.336621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1593 08:08:32.433669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1594 08:08:32.434048 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1596 08:08:32.528821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1597 08:08:32.529190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1599 08:08:32.625804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1600 08:08:32.626182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1602 08:08:32.724494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1603 08:08:32.724871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1605 08:08:32.819086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1606 08:08:32.819471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1608 08:08:32.915631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1609 08:08:32.916034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1611 08:08:33.012188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1612 08:08:33.012565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1614 08:08:33.109015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1615 08:08:33.109391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1617 08:08:33.204624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1618 08:08:33.205003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1620 08:08:33.300087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1621 08:08:33.300464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1623 08:08:33.392597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1624 08:08:33.393037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1626 08:08:33.491319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1627 08:08:33.491781 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1629 08:08:33.588049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1630 08:08:33.588487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1632 08:08:33.685629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1633 08:08:33.686121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1635 08:08:33.781893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1636 08:08:33.782272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1638 08:08:33.878098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1639 08:08:33.878483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1641 08:08:33.976063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1642 08:08:33.976458 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1644 08:08:34.072601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1645 08:08:34.072988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1647 08:08:34.167157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1648 08:08:34.167540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1650 08:08:34.265718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1651 08:08:34.266199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1653 08:08:34.365659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1654 08:08:34.366139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1656 08:08:34.461120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1657 08:08:34.461607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1659 08:08:34.553727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1660 08:08:34.554153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1662 08:08:34.650135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1663 08:08:34.650543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1665 08:08:34.745980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1666 08:08:34.746366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1668 08:08:34.843261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1669 08:08:34.843641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1671 08:08:34.939913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1672 08:08:34.940299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1674 08:08:35.032921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1675 08:08:35.033336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1677 08:08:35.130213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1678 08:08:35.130610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1680 08:08:35.227628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1681 08:08:35.228004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1683 08:08:35.319881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1684 08:08:35.320316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1686 08:08:35.418302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1687 08:08:35.418797 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1689 08:08:35.514365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1690 08:08:35.514748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1692 08:08:35.613803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1693 08:08:35.614200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1695 08:08:35.710863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1696 08:08:35.711244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1698 08:08:35.802412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1699 08:08:35.802817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1701 08:08:35.897980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1702 08:08:35.898363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1704 08:08:35.993459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1705 08:08:35.993892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1707 08:08:36.091602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1708 08:08:36.092006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1710 08:08:36.187271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1711 08:08:36.187705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1713 08:08:36.283019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1714 08:08:36.283466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1716 08:08:36.389212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1717 08:08:36.389625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1719 08:08:36.484771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1720 08:08:36.485216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1722 08:08:36.579961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1723 08:08:36.580345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1725 08:08:36.672262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1726 08:08:36.672663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1728 08:08:36.785478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1729 08:08:36.785910 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1731 08:08:36.894680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1732 08:08:36.895130 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1734 08:08:37.011140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1735 08:08:37.011527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1737 08:08:37.157531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1738 08:08:37.157991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1740 08:08:37.257772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1741 08:08:37.258163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1743 08:08:37.411257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1744 08:08:37.411624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1746 08:08:37.544617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1747 08:08:37.544947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1749 08:08:37.639787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1750 08:08:37.640140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1752 08:08:37.788060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1753 08:08:37.788394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1755 08:08:37.893818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1756 08:08:37.894183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1758 08:08:38.019297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1759 08:08:38.019667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1761 08:08:38.136694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1762 08:08:38.137021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1764 08:08:38.231704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1765 08:08:38.232127 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1767 08:08:38.319898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1768 08:08:38.320312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1770 08:08:38.471193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1771 08:08:38.471609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1773 08:08:38.599245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1774 08:08:38.599671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1776 08:08:38.695724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1777 08:08:38.696148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1779 08:08:38.831085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1780 08:08:38.831516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1782 08:08:38.922723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1783 08:08:38.923145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1785 08:08:39.049046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1786 08:08:39.049467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1788 08:08:39.144948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1789 08:08:39.145359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1791 08:08:39.268547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1792 08:08:39.268970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1794 08:08:39.391045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1795 08:08:39.391463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1797 08:08:39.487973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1798 08:08:39.488340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1800 08:08:39.616679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1801 08:08:39.617030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1803 08:08:39.709934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1804 08:08:39.710289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1806 08:08:39.838064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1807 08:08:39.838454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1809 08:08:39.945226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1810 08:08:39.945622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1812 08:08:40.067619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1813 08:08:40.068061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1815 08:08:40.188345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1816 08:08:40.188805 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1818 08:08:40.283040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1819 08:08:40.283546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1821 08:08:40.405856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1822 08:08:40.406437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1824 08:08:40.519544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1825 08:08:40.520284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1827 08:08:40.646496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1828 08:08:40.647045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1830 08:08:40.762823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1831 08:08:40.763343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1833 08:08:40.876994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1834 08:08:40.877588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1836 08:08:41.004920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1837 08:08:41.005422 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1839 08:08:41.110862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1840 08:08:41.111453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1842 08:08:41.228916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1843 08:08:41.229539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1845 08:08:41.357269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1846 08:08:41.357929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1848 08:08:41.457703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1849 08:08:41.458075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1851 08:08:41.575004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1852 08:08:41.575542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1854 08:08:41.696234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1855 08:08:41.696764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1857 08:08:41.812270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1858 08:08:41.812780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1860 08:08:41.927348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1861 08:08:41.927844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1863 08:08:42.036008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1864 08:08:42.036703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1866 08:08:42.157550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1867 08:08:42.158211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1869 08:08:42.280454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1870 08:08:42.280946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1872 08:08:42.401880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1873 08:08:42.402509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1875 08:08:42.527741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1876 08:08:42.528276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1878 08:08:42.653913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1879 08:08:42.654403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1881 08:08:42.768930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1882 08:08:42.769474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1884 08:08:42.902004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1885 08:08:42.902547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1887 08:08:43.039686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1888 08:08:43.040177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1890 08:08:43.152657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1891 08:08:43.153368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1893 08:08:43.283599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1895 08:08:43.286629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1896 08:08:43.412333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1898 08:08:43.416453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1899 08:08:43.523189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1901 08:08:43.526937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1902 08:08:43.684726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1903 08:08:43.685454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1905 08:08:43.845684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1906 08:08:43.846358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1908 08:08:43.971100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1909 08:08:43.971830 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1911 08:08:44.101028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1912 08:08:44.101629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1914 08:08:44.228622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1915 08:08:44.229224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1917 08:08:44.347199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1918 08:08:44.347693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1920 08:08:44.460893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1921 08:08:44.461419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1923 08:08:44.587533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1924 08:08:44.588057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1926 08:08:44.720855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1927 08:08:44.721349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1929 08:08:44.845847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1930 08:08:44.846415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1932 08:08:44.980467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1933 08:08:44.980965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1935 08:08:45.107016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1936 08:08:45.107515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1938 08:08:45.225438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1939 08:08:45.226023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1941 08:08:45.365876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1942 08:08:45.366422 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1944 08:08:45.506766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1945 08:08:45.507267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1947 08:08:45.640464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
1948 08:08:45.640954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
1950 08:08:45.760400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1951 08:08:45.760951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
1953 08:08:45.879588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
1954 08:08:45.880131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
1956 08:08:45.999513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
1957 08:08:46.000007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
1959 08:08:46.123518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
1960 08:08:46.124055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
1962 08:08:46.259794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
1963 08:08:46.260333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
1965 08:08:46.385322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
1966 08:08:46.385899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
1968 08:08:46.520026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
1969 08:08:46.520551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
1971 08:08:46.658073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
1972 08:08:46.658573 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
1974 08:08:46.795839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
1975 08:08:46.796357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
1977 08:08:46.921123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
1978 08:08:46.921703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
1980 08:08:47.066782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
1981 08:08:47.067327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
1983 08:08:47.207786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
1984 08:08:47.208373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
1986 08:08:47.344650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
1987 08:08:47.345181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
1989 08:08:47.463243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
1990 08:08:47.463735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
1992 08:08:47.621980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
1993 08:08:47.622480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
1995 08:08:47.770840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
1996 08:08:47.771333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
1998 08:08:47.914666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
1999 08:08:47.915160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2001 08:08:48.054138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2002 08:08:48.054624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2004 08:08:48.191386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2005 08:08:48.191884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2007 08:08:48.384078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2008 08:08:48.384558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2010 08:08:48.570677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2011 08:08:48.571173 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2013 08:08:48.970271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2014 08:08:48.970766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2016 08:08:49.455562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2017 08:08:49.456077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2019 08:08:50.084428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2020 08:08:50.084849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2022 08:08:50.182870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2023 08:08:50.183226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2025 08:08:50.279472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2026 08:08:50.279938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2028 08:08:50.384040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2029 08:08:50.384472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2031 08:08:50.491705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2032 08:08:50.492181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2034 08:08:50.606157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2035 08:08:50.606583 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2037 08:08:50.718008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2038 08:08:50.718432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2040 08:08:50.817170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2041 08:08:50.817609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2043 08:08:50.928570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2044 08:08:50.929000 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2046 08:08:51.036830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2047 08:08:51.037261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2049 08:08:51.162274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2050 08:08:51.162702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2052 08:08:51.330252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2053 08:08:51.330743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2055 08:08:51.438439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2056 08:08:51.438871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2058 08:08:51.552525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2059 08:08:51.552959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2061 08:08:51.671762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2062 08:08:51.672181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2064 08:08:51.787161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2065 08:08:51.787585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2067 08:08:51.901476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2068 08:08:51.901920 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2070 08:08:52.014880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2071 08:08:52.015301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2073 08:08:52.111132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2074 08:08:52.111546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2076 08:08:52.207795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2077 08:08:52.208278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2079 08:08:52.298381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2080 08:08:52.298806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2082 08:08:52.417725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2083 08:08:52.418154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2085 08:08:52.712700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2086 08:08:52.713122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2088 08:08:52.832840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2089 08:08:52.833265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2091 08:08:52.932860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2092 08:08:52.933288 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2094 08:08:53.055575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2095 08:08:53.055997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2097 08:08:53.187848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2098 08:08:53.188269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2100 08:08:53.291025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2101 08:08:53.291504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2103 08:08:53.409439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2104 08:08:53.409689 + set +x
2105 08:08:53.410016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2107 08:08:53.418331 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 743034_1.6.2.4.5>
2108 08:08:53.418521 <LAVA_TEST_RUNNER EXIT>
2109 08:08:53.418843 Received signal: <ENDRUN> 1_kselftest-dt 743034_1.6.2.4.5
2110 08:08:53.418984 Ending use of test pattern.
2111 08:08:53.419092 Ending test lava.1_kselftest-dt (743034_1.6.2.4.5), duration 96.92
2113 08:08:53.419512 ok: lava_test_shell seems to have completed
2114 08:08:53.421955 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
shardfile-dt: pass
2115 08:08:53.422498 end: 3.1 lava-test-shell (duration 00:01:38) [common]
2116 08:08:53.422652 end: 3 lava-test-retry (duration 00:01:38) [common]
2117 08:08:53.422819 start: 4 finalize (timeout 00:04:22) [common]
2118 08:08:53.422988 start: 4.1 power-off (timeout 00:00:30) [common]
2119 08:08:53.423274 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2120 08:08:53.441972 >> OK - accepted request
2121 08:08:53.442967 Returned 0 in 0 seconds
2122 08:08:53.543557 end: 4.1 power-off (duration 00:00:00) [common]
2124 08:08:53.544170 start: 4.2 read-feedback (timeout 00:04:22) [common]
2125 08:08:53.544617 Listened to connection for namespace 'common' for up to 1s
2126 08:08:53.544994 Listened to connection for namespace 'common' for up to 1s
2127 08:08:54.545491 Finalising connection for namespace 'common'
2128 08:08:54.545799 Disconnecting from shell: Finalise
2129 08:08:54.545965 / #
2130 08:08:54.646438 end: 4.2 read-feedback (duration 00:00:01) [common]
2131 08:08:54.646816 end: 4 finalize (duration 00:00:01) [common]
2132 08:08:54.647045 Cleaning after the job
2133 08:08:54.647257 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/743034/tftp-deploy-7mwwifo5/ramdisk
2134 08:08:54.653536 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/743034/tftp-deploy-7mwwifo5/kernel
2135 08:08:54.658282 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/743034/tftp-deploy-7mwwifo5/dtb
2136 08:08:54.658660 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/743034/tftp-deploy-7mwwifo5/nfsrootfs
2137 08:08:54.765302 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/743034/tftp-deploy-7mwwifo5/modules
2138 08:08:54.771298 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/743034
2139 08:08:55.715702 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/743034
2140 08:08:55.715925 Job finished correctly