Boot log: beaglebone-black
- Warnings: 3
- Kernel Warnings: 101
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 15:46:40.091928 lava-dispatcher, installed at version: 2023.08
2 15:46:40.092272 start: 0 validate
3 15:46:40.092458 Start time: 2024-09-19 15:46:40.092446+00:00 (UTC)
4 15:46:40.092688 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 15:46:41.022373 Validating that http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
6 15:46:41.136801 Validating that http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
7 15:46:41.250841 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 15:46:41.364882 Validating that http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
9 15:46:41.483654 validate duration: 1.39
11 15:46:41.484462 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 15:46:41.484796 start: 1.1 download-retry (timeout 00:10:00) [common]
13 15:46:41.485109 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 15:46:41.485570 Not decompressing ramdisk as can be used compressed.
15 15:46:41.485868 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 15:46:41.486109 saving as /var/lib/lava/dispatcher/tmp/1193677/tftp-deploy-x7mixwxv/ramdisk/initrd.cpio.gz
17 15:46:41.486355 total size: 4775763 (4 MB)
18 15:46:41.716863 progress 0 % (0 MB)
19 15:46:42.054107 progress 5 % (0 MB)
20 15:46:42.275633 progress 10 % (0 MB)
21 15:46:42.301582 progress 15 % (0 MB)
22 15:46:42.392186 progress 20 % (0 MB)
23 15:46:42.408625 progress 25 % (1 MB)
24 15:46:42.511655 progress 30 % (1 MB)
25 15:46:42.618931 progress 35 % (1 MB)
26 15:46:42.721415 progress 40 % (1 MB)
27 15:46:42.743487 progress 45 % (2 MB)
28 15:46:42.844329 progress 50 % (2 MB)
29 15:46:42.949043 progress 55 % (2 MB)
30 15:46:42.973573 progress 60 % (2 MB)
31 15:46:43.071259 progress 65 % (2 MB)
32 15:46:43.175370 progress 70 % (3 MB)
33 15:46:43.198884 progress 75 % (3 MB)
34 15:46:43.295801 progress 80 % (3 MB)
35 15:46:43.394542 progress 85 % (3 MB)
36 15:46:43.422635 progress 90 % (4 MB)
37 15:46:43.519096 progress 95 % (4 MB)
38 15:46:43.615599 progress 100 % (4 MB)
39 15:46:43.616525 4 MB downloaded in 2.13 s (2.14 MB/s)
40 15:46:43.617023 end: 1.1.1 http-download (duration 00:00:02) [common]
42 15:46:43.617909 end: 1.1 download-retry (duration 00:00:02) [common]
43 15:46:43.618210 start: 1.2 download-retry (timeout 00:09:58) [common]
44 15:46:43.618500 start: 1.2.1 http-download (timeout 00:09:58) [common]
45 15:46:43.618922 downloading http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/kernel/zImage
46 15:46:43.619151 saving as /var/lib/lava/dispatcher/tmp/1193677/tftp-deploy-x7mixwxv/kernel/zImage
47 15:46:43.619371 total size: 11457024 (10 MB)
48 15:46:43.619594 No compression specified
49 15:46:43.738657 progress 0 % (0 MB)
50 15:46:44.077036 progress 5 % (0 MB)
51 15:46:44.302370 progress 10 % (1 MB)
52 15:46:44.529784 progress 15 % (1 MB)
53 15:46:44.753008 progress 20 % (2 MB)
54 15:46:44.978052 progress 25 % (2 MB)
55 15:46:45.197877 progress 30 % (3 MB)
56 15:46:45.420220 progress 35 % (3 MB)
57 15:46:45.638605 progress 40 % (4 MB)
58 15:46:45.858746 progress 45 % (4 MB)
59 15:46:46.032253 progress 50 % (5 MB)
60 15:46:46.227892 progress 55 % (6 MB)
61 15:46:46.431629 progress 60 % (6 MB)
62 15:46:46.650729 progress 65 % (7 MB)
63 15:46:46.864486 progress 70 % (7 MB)
64 15:46:47.080976 progress 75 % (8 MB)
65 15:46:47.236887 progress 80 % (8 MB)
66 15:46:47.437443 progress 85 % (9 MB)
67 15:46:47.650190 progress 90 % (9 MB)
68 15:46:47.868596 progress 95 % (10 MB)
69 15:46:48.025491 progress 100 % (10 MB)
70 15:46:48.026205 10 MB downloaded in 4.41 s (2.48 MB/s)
71 15:46:48.026660 end: 1.2.1 http-download (duration 00:00:04) [common]
73 15:46:48.027489 end: 1.2 download-retry (duration 00:00:04) [common]
74 15:46:48.027790 start: 1.3 download-retry (timeout 00:09:53) [common]
75 15:46:48.028080 start: 1.3.1 http-download (timeout 00:09:53) [common]
76 15:46:48.028515 downloading http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
77 15:46:48.028749 saving as /var/lib/lava/dispatcher/tmp/1193677/tftp-deploy-x7mixwxv/dtb/am335x-boneblack.dtb
78 15:46:48.028969 total size: 70568 (0 MB)
79 15:46:48.029192 No compression specified
80 15:46:48.159412 progress 46 % (0 MB)
81 15:46:48.162225 progress 92 % (0 MB)
82 15:46:48.163218 progress 100 % (0 MB)
83 15:46:48.163615 0 MB downloaded in 0.13 s (0.50 MB/s)
84 15:46:48.164023 end: 1.3.1 http-download (duration 00:00:00) [common]
86 15:46:48.164853 end: 1.3 download-retry (duration 00:00:00) [common]
87 15:46:48.165140 start: 1.4 download-retry (timeout 00:09:53) [common]
88 15:46:48.165429 start: 1.4.1 http-download (timeout 00:09:53) [common]
89 15:46:48.165790 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 15:46:48.166020 saving as /var/lib/lava/dispatcher/tmp/1193677/tftp-deploy-x7mixwxv/nfsrootfs/full.rootfs.tar
91 15:46:48.166239 total size: 117747780 (112 MB)
92 15:46:48.166467 Using unxz to decompress xz
93 15:46:48.287385 progress 0 % (0 MB)
94 15:46:50.849956 progress 5 % (5 MB)
95 15:46:52.886288 progress 10 % (11 MB)
96 15:46:54.976308 progress 15 % (16 MB)
97 15:46:56.990980 progress 20 % (22 MB)
98 15:46:58.813051 progress 25 % (28 MB)
99 15:47:00.387713 progress 30 % (33 MB)
100 15:47:01.716485 progress 35 % (39 MB)
101 15:47:02.753705 progress 40 % (44 MB)
102 15:47:03.767999 progress 45 % (50 MB)
103 15:47:04.870503 progress 50 % (56 MB)
104 15:47:05.861242 progress 55 % (61 MB)
105 15:47:06.778924 progress 60 % (67 MB)
106 15:47:07.825585 progress 65 % (73 MB)
107 15:47:09.002583 progress 70 % (78 MB)
108 15:47:10.068302 progress 75 % (84 MB)
109 15:47:11.138035 progress 80 % (89 MB)
110 15:47:12.164921 progress 85 % (95 MB)
111 15:47:13.195789 progress 90 % (101 MB)
112 15:47:14.266081 progress 95 % (106 MB)
113 15:47:15.292818 progress 100 % (112 MB)
114 15:47:15.296644 112 MB downloaded in 27.13 s (4.14 MB/s)
115 15:47:15.297046 end: 1.4.1 http-download (duration 00:00:27) [common]
117 15:47:15.297785 end: 1.4 download-retry (duration 00:00:27) [common]
118 15:47:15.298043 start: 1.5 download-retry (timeout 00:09:26) [common]
119 15:47:15.298296 start: 1.5.1 http-download (timeout 00:09:26) [common]
120 15:47:15.298659 downloading http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
121 15:47:15.298860 saving as /var/lib/lava/dispatcher/tmp/1193677/tftp-deploy-x7mixwxv/modules/modules.tar
122 15:47:15.299053 total size: 6615688 (6 MB)
123 15:47:15.299249 Using unxz to decompress xz
124 15:47:15.417603 progress 0 % (0 MB)
125 15:47:15.653425 progress 5 % (0 MB)
126 15:47:15.767469 progress 10 % (0 MB)
127 15:47:15.891929 progress 15 % (0 MB)
128 15:47:15.917431 progress 20 % (1 MB)
129 15:47:16.007879 progress 25 % (1 MB)
130 15:47:16.120344 progress 30 % (1 MB)
131 15:47:16.275807 progress 35 % (2 MB)
132 15:47:16.343145 progress 40 % (2 MB)
133 15:47:16.454356 progress 45 % (2 MB)
134 15:47:16.564130 progress 50 % (3 MB)
135 15:47:16.721271 progress 55 % (3 MB)
136 15:47:16.789406 progress 60 % (3 MB)
137 15:47:16.899213 progress 65 % (4 MB)
138 15:47:17.011395 progress 70 % (4 MB)
139 15:47:17.121190 progress 75 % (4 MB)
140 15:47:17.230078 progress 80 % (5 MB)
141 15:47:17.336336 progress 85 % (5 MB)
142 15:47:17.444067 progress 90 % (5 MB)
143 15:47:17.550338 progress 95 % (6 MB)
144 15:47:17.657006 progress 100 % (6 MB)
145 15:47:17.662981 6 MB downloaded in 2.36 s (2.67 MB/s)
146 15:47:17.663401 end: 1.5.1 http-download (duration 00:00:02) [common]
148 15:47:17.664173 end: 1.5 download-retry (duration 00:00:02) [common]
149 15:47:17.664488 start: 1.6 prepare-tftp-overlay (timeout 00:09:24) [common]
150 15:47:17.664760 start: 1.6.1 extract-nfsrootfs (timeout 00:09:24) [common]
151 15:47:23.201081 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1193677/extract-nfsrootfs-k2t1kv2k
152 15:47:23.201369 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
153 15:47:23.201501 start: 1.6.2 lava-overlay (timeout 00:09:18) [common]
154 15:47:23.201770 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot
155 15:47:23.201940 makedir: /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin
156 15:47:23.202072 makedir: /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/tests
157 15:47:23.202202 makedir: /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/results
158 15:47:23.202343 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-add-keys
159 15:47:23.202545 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-add-sources
160 15:47:23.202716 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-background-process-start
161 15:47:23.202886 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-background-process-stop
162 15:47:23.203069 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-common-functions
163 15:47:23.203239 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-echo-ipv4
164 15:47:23.203407 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-install-packages
165 15:47:23.203572 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-installed-packages
166 15:47:23.203735 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-os-build
167 15:47:23.203898 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-probe-channel
168 15:47:23.204062 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-probe-ip
169 15:47:23.204276 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-target-ip
170 15:47:23.204441 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-target-mac
171 15:47:23.204604 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-target-storage
172 15:47:23.204772 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-test-case
173 15:47:23.204938 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-test-event
174 15:47:23.205100 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-test-feedback
175 15:47:23.205261 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-test-raise
176 15:47:23.205424 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-test-reference
177 15:47:23.205593 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-test-runner
178 15:47:23.205755 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-test-set
179 15:47:23.205917 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-test-shell
180 15:47:23.206083 Updating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-add-keys (debian)
181 15:47:23.206301 Updating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-add-sources (debian)
182 15:47:23.206488 Updating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-install-packages (debian)
183 15:47:23.206673 Updating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-installed-packages (debian)
184 15:47:23.206858 Updating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/bin/lava-os-build (debian)
185 15:47:23.207020 Creating /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/environment
186 15:47:23.207145 LAVA metadata
187 15:47:23.207241 - LAVA_JOB_ID=1193677
188 15:47:23.207334 - LAVA_DISPATCHER_IP=192.168.11.5
189 15:47:23.207473 start: 1.6.2.1 ssh-authorize (timeout 00:09:18) [common]
190 15:47:23.207791 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 15:47:23.207910 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:18) [common]
192 15:47:23.208008 skipped lava-vland-overlay
193 15:47:23.208135 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 15:47:23.208266 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:18) [common]
195 15:47:23.208359 skipped lava-multinode-overlay
196 15:47:23.208468 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 15:47:23.208581 start: 1.6.2.4 test-definition (timeout 00:09:18) [common]
198 15:47:23.208679 Loading test definitions
199 15:47:23.208797 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:18) [common]
200 15:47:23.208895 Using /lava-1193677 at stage 0
201 15:47:23.209283 uuid=1193677_1.6.2.4.1 testdef=None
202 15:47:23.209403 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 15:47:23.209519 start: 1.6.2.4.2 test-overlay (timeout 00:09:18) [common]
204 15:47:23.210113 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 15:47:23.210440 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:18) [common]
207 15:47:23.211239 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 15:47:23.211570 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:18) [common]
210 15:47:23.212370 runner path: /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/0/tests/0_timesync-off test_uuid 1193677_1.6.2.4.1
211 15:47:23.212560 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 15:47:23.212890 start: 1.6.2.4.5 git-repo-action (timeout 00:09:18) [common]
214 15:47:23.212988 Using /lava-1193677 at stage 0
215 15:47:23.213122 Fetching tests from https://github.com/kernelci/test-definitions.git
216 15:47:23.213222 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/0/tests/1_kselftest-dt'
217 15:47:27.832047 Running '/usr/bin/git checkout kernelci.org
218 15:47:28.052717 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 15:47:28.053611 uuid=1193677_1.6.2.4.5 testdef=None
220 15:47:28.053839 end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
222 15:47:28.054350 start: 1.6.2.4.6 test-overlay (timeout 00:09:13) [common]
223 15:47:28.056027 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 15:47:28.056576 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:13) [common]
226 15:47:28.058950 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 15:47:28.059505 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:13) [common]
229 15:47:28.061771 runner path: /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/0/tests/1_kselftest-dt test_uuid 1193677_1.6.2.4.5
230 15:47:28.061953 BOARD='beaglebone-black'
231 15:47:28.062099 BRANCH='next'
232 15:47:28.062240 SKIPFILE='/dev/null'
233 15:47:28.062378 SKIP_INSTALL='True'
234 15:47:28.062514 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
235 15:47:28.062655 TST_CASENAME=''
236 15:47:28.062792 TST_CMDFILES='dt'
237 15:47:28.063092 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 15:47:28.063581 Creating lava-test-runner.conf files
240 15:47:28.063721 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1193677/lava-overlay-jaj22oot/lava-1193677/0 for stage 0
241 15:47:28.063918 - 0_timesync-off
242 15:47:28.064065 - 1_kselftest-dt
243 15:47:28.064290 end: 1.6.2.4 test-definition (duration 00:00:05) [common]
244 15:47:28.064409 start: 1.6.2.5 compress-overlay (timeout 00:09:13) [common]
245 15:47:36.540689 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 15:47:36.540900 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:05) [common]
247 15:47:36.541047 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 15:47:36.541208 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
249 15:47:36.541355 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:05) [common]
250 15:47:36.664379 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 15:47:36.664675 start: 1.6.4 extract-modules (timeout 00:09:05) [common]
252 15:47:36.664840 extracting modules file /var/lib/lava/dispatcher/tmp/1193677/tftp-deploy-x7mixwxv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1193677/extract-nfsrootfs-k2t1kv2k
253 15:47:36.971677 extracting modules file /var/lib/lava/dispatcher/tmp/1193677/tftp-deploy-x7mixwxv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1193677/extract-overlay-ramdisk-ea57uoy6/ramdisk
254 15:47:37.280148 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 15:47:37.280453 start: 1.6.5 apply-overlay-tftp (timeout 00:09:04) [common]
256 15:47:37.280590 [common] Applying overlay to NFS
257 15:47:37.280698 [common] Applying overlay /var/lib/lava/dispatcher/tmp/1193677/compress-overlay-sx2g51a1/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1193677/extract-nfsrootfs-k2t1kv2k
258 15:47:38.472234 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 15:47:38.472452 start: 1.6.6 prepare-kernel (timeout 00:09:03) [common]
260 15:47:38.472600 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:03) [common]
261 15:47:38.472749 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 15:47:38.472887 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 15:47:38.473026 start: 1.6.7 configure-preseed-file (timeout 00:09:03) [common]
264 15:47:38.473160 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 15:47:38.473296 start: 1.6.8 compress-ramdisk (timeout 00:09:03) [common]
266 15:47:38.473401 Building ramdisk /var/lib/lava/dispatcher/tmp/1193677/extract-overlay-ramdisk-ea57uoy6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1193677/extract-overlay-ramdisk-ea57uoy6/ramdisk
267 15:47:38.784751 >> 74933 blocks
268 15:47:40.726894 Adding RAMdisk u-boot header.
269 15:47:40.727184 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1193677/extract-overlay-ramdisk-ea57uoy6/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1193677/extract-overlay-ramdisk-ea57uoy6/ramdisk.cpio.gz.uboot
270 15:47:40.879816 output: Image Name:
271 15:47:40.880187 output: Created: Thu Sep 19 15:47:40 2024
272 15:47:40.880416 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 15:47:40.880620 output: Data Size: 14792362 Bytes = 14445.67 KiB = 14.11 MiB
274 15:47:40.880817 output: Load Address: 00000000
275 15:47:40.881008 output: Entry Point: 00000000
276 15:47:40.881200 output:
277 15:47:40.881509 rename /var/lib/lava/dispatcher/tmp/1193677/extract-overlay-ramdisk-ea57uoy6/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1193677/tftp-deploy-x7mixwxv/ramdisk/ramdisk.cpio.gz.uboot
278 15:47:40.881863 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
279 15:47:40.882162 end: 1.6 prepare-tftp-overlay (duration 00:00:23) [common]
280 15:47:40.882456 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:01) [common]
281 15:47:40.882674 No LXC device requested
282 15:47:40.882919 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 15:47:40.883174 start: 1.8 deploy-device-env (timeout 00:09:01) [common]
284 15:47:40.883421 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 15:47:40.883619 Checking files for TFTP limit of 4294967296 bytes.
286 15:47:40.884873 end: 1 tftp-deploy (duration 00:00:59) [common]
287 15:47:40.885157 start: 2 uboot-action (timeout 00:05:00) [common]
288 15:47:40.885433 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 15:47:40.885697 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 15:47:40.885988 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 15:47:40.886380 substitutions:
292 15:47:40.886591 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 15:47:40.886805 - {DTB_ADDR}: 0x88000000
294 15:47:40.887014 - {DTB}: 1193677/tftp-deploy-x7mixwxv/dtb/am335x-boneblack.dtb
295 15:47:40.887225 - {INITRD}: 1193677/tftp-deploy-x7mixwxv/ramdisk/ramdisk.cpio.gz.uboot
296 15:47:40.887431 - {KERNEL_ADDR}: 0x82000000
297 15:47:40.887638 - {KERNEL}: 1193677/tftp-deploy-x7mixwxv/kernel/zImage
298 15:47:40.887843 - {LAVA_MAC}: None
299 15:47:40.888061 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1193677/extract-nfsrootfs-k2t1kv2k
300 15:47:40.888284 - {NFS_SERVER_IP}: 192.168.11.5
301 15:47:40.888480 - {PRESEED_CONFIG}: None
302 15:47:40.888673 - {PRESEED_LOCAL}: None
303 15:47:40.888868 - {RAMDISK_ADDR}: 0x83000000
304 15:47:40.889060 - {RAMDISK}: 1193677/tftp-deploy-x7mixwxv/ramdisk/ramdisk.cpio.gz.uboot
305 15:47:40.889255 - {ROOT_PART}: None
306 15:47:40.889446 - {ROOT}: None
307 15:47:40.889637 - {SERVER_IP}: 192.168.11.5
308 15:47:40.889826 - {TEE_ADDR}: 0x83000000
309 15:47:40.890016 - {TEE}: None
310 15:47:40.890206 Parsed boot commands:
311 15:47:40.890393 - setenv autoload no
312 15:47:40.890584 - setenv initrd_high 0xffffffff
313 15:47:40.890775 - setenv fdt_high 0xffffffff
314 15:47:40.890962 - dhcp
315 15:47:40.891152 - setenv serverip 192.168.11.5
316 15:47:40.891340 - tftp 0x82000000 1193677/tftp-deploy-x7mixwxv/kernel/zImage
317 15:47:40.891532 - tftp 0x83000000 1193677/tftp-deploy-x7mixwxv/ramdisk/ramdisk.cpio.gz.uboot
318 15:47:40.891723 - setenv initrd_size ${filesize}
319 15:47:40.891912 - tftp 0x88000000 1193677/tftp-deploy-x7mixwxv/dtb/am335x-boneblack.dtb
320 15:47:40.892104 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1193677/extract-nfsrootfs-k2t1kv2k,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 15:47:40.892332 - bootz 0x82000000 0x83000000 0x88000000
322 15:47:40.892447 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 15:47:40.892771 start: 2.3 connect-device (timeout 00:05:00) [common]
325 15:47:40.892866 [common] connect-device Connecting to device using 'telnet 127.0.0.1 63003'
326 15:47:41.251400 Setting prompt string to ['lava-test: # ']
327 15:47:41.251792 end: 2.3 connect-device (duration 00:00:00) [common]
328 15:47:41.251965 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 15:47:41.252133 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 15:47:41.252317 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 15:47:41.252636 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/reset'
332 15:47:41.616337 Returned 0 in 0 seconds
333 15:47:41.717248 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
335 15:47:41.718155 end: 2.4.1 reset-device (duration 00:00:00) [common]
336 15:47:41.718472 start: 2.4.2 bootloader-interrupt (timeout 00:04:59) [common]
337 15:47:41.718752 Setting prompt string to ['Press SPACE to abort autoboot in 2 seconds']
338 15:47:41.719006 bootloader-interrupt: Wait for prompt ['Press SPACE to abort autoboot in 2 seconds'] (timeout 00:05:00)
339 15:47:41.719770 Trying 127.0.0.1...
340 15:47:41.720006 Connected to 127.0.0.1.
341 15:47:41.720249 Escape character is '^]'.
342 15:47:46.530928
343 15:47:46.534616 U-Boot SPL 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500)
344 15:47:46.591308 Trying to boot from MMC2
345 15:47:46.639523 Loading Environment from EXT4... Card did not respond to voltage select!
346 15:47:46.706607
347 15:47:46.706878
348 15:47:46.712220 U-Boot 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500), Build: jenkins-github_Bootloader-Builder-131
349 15:47:46.712507
350 15:47:46.717246 CPU : AM335X-GP rev 2.1
351 15:47:46.771044 I2C: ready
352 15:47:46.771322 DRAM: 512 MiB
353 15:47:46.825339 No match for driver 'omap_hsmmc'
354 15:47:46.830945 No match for driver 'omap_hsmmc'
355 15:47:46.831228 Some drivers were not found
356 15:47:46.837479 Reset Source: Power-on reset has occurred.
357 15:47:46.837871 RTC 32KCLK Source: External.
358 15:47:46.840123 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
359 15:47:46.858008 Loading Environment from EXT4... Card did not respond to voltage select!
360 15:47:46.922583 Board: BeagleBone Black
361 15:47:46.926496 <ethaddr> not set. Validating first E-fuse MAC
362 15:47:46.983095 BeagleBone Black:
363 15:47:46.983363 BeagleBone: cape eeprom: i2c_probe: 0x54:
364 15:47:46.988704 BeagleBone: cape eeprom: i2c_probe: 0x55:
365 15:47:46.994703 BeagleBone: cape eeprom: i2c_probe: 0x56:
366 15:47:46.994971 BeagleBone: cape eeprom: i2c_probe: 0x57:
367 15:47:46.999707 Net: eth0: MII MODE
368 15:47:47.009025 cpsw, usb_ether
369 15:47:47.009293 Press SPACE to abort autoboot in 2 seconds
370 15:47:47.060101 end: 2.4.2 bootloader-interrupt (duration 00:00:05) [common]
371 15:47:47.060461 start: 2.4.3 bootloader-commands (timeout 00:04:54) [common]
372 15:47:47.060730 Setting prompt string to ['=> ']
373 15:47:47.060986 bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:54)
374 15:47:47.064269 Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
375 15:47:47.064572 Sending with 10 millisecond of delay
377 15:47:48.199180 => setenv autoload no
378 15:47:48.209690 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:53)
379 15:47:48.212055 setenv autoload no
380 15:47:48.212566 Sending with 10 millisecond of delay
382 15:47:50.009600 => setenv initrd_high 0xffffffff
383 15:47:50.020096 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:51)
384 15:47:50.020588 setenv initrd_high 0xffffffff
385 15:47:50.021039 Sending with 10 millisecond of delay
387 15:47:51.637437 => setenv fdt_high 0xffffffff
388 15:47:51.647980 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
389 15:47:51.648458 setenv fdt_high 0xffffffff
390 15:47:51.648903 Sending with 10 millisecond of delay
392 15:47:51.940372 => dhcp
393 15:47:51.950873 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
394 15:47:51.951350 dhcp
395 15:47:51.951578 link up on port 0, speed 100, full duplex
396 15:47:51.951794 BOOTP broadcast 1
397 15:47:51.959361 DHCP client bound to address 192.168.11.7 (3 ms)
398 15:47:51.959843 Sending with 10 millisecond of delay
400 15:47:53.696623 => setenv serverip 192.168.11.5
401 15:47:53.707149 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:47)
402 15:47:53.707642 setenv serverip 192.168.11.5
403 15:47:53.708095 Sending with 10 millisecond of delay
405 15:47:57.251217 => tftp 0x82000000 1193677/tftp-deploy-x7mixwxv/kernel/zImage
406 15:47:57.261707 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:44)
407 15:47:57.262175 tftp 0x82000000 1193677/tftp-deploy-x7mixwxv/kernel/zImage
408 15:47:57.262420 link up on port 0, speed 100, full duplex
409 15:47:57.262637 Using cpsw device
410 15:47:57.265971 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
411 15:47:57.271611 Filename '1193677/tftp-deploy-x7mixwxv/kernel/zImage'.
412 15:47:57.278419 Load address: 0x82000000
413 15:47:57.472498 Loading: *#################################################################
414 15:47:57.632748 #################################################################
415 15:47:57.827052 #################################################################
416 15:47:58.000807 #################################################################
417 15:47:58.176046 #################################################################
418 15:47:58.349143 #################################################################
419 15:47:58.523283 #################################################################
420 15:47:58.697396 #################################################################
421 15:47:58.872004 #################################################################
422 15:47:59.046764 #################################################################
423 15:47:59.242742 #################################################################
424 15:47:59.406089 #################################################################
425 15:47:59.406374 #
426 15:47:59.406606 5.1 MiB/s
427 15:47:59.406829 done
428 15:47:59.409810 Bytes transferred = 11457024 (aed200 hex)
429 15:47:59.410289 Sending with 10 millisecond of delay
431 15:48:03.917207 => tftp 0x83000000 1193677/tftp-deploy-x7mixwxv/ramdisk/ramdisk.cpio.gz.uboot
432 15:48:03.927717 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
433 15:48:03.928186 tftp 0x83000000 1193677/tftp-deploy-x7mixwxv/ramdisk/ramdisk.cpio.gz.uboot
434 15:48:03.928435 link up on port 0, speed 100, full duplex
435 15:48:03.928650 Using cpsw device
436 15:48:03.932150 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
437 15:48:03.975483 Filename '1193677/tftp-deploy-x7mixwxv/ramdisk/ramdisk.cpio.gz.uboot'.
438 15:48:03.975762 Load address: 0x83000000
439 15:48:04.121970 Loading: *#################################################################
440 15:48:04.312568 #################################################################
441 15:48:04.486180 #################################################################
442 15:48:04.657454 #################################################################
443 15:48:04.831161 #################################################################
444 15:48:05.014924 #################################################################
445 15:48:05.189586 #################################################################
446 15:48:05.364266 #################################################################
447 15:48:05.559653 #################################################################
448 15:48:05.735355 #################################################################
449 15:48:05.912111 #################################################################
450 15:48:06.088003 #################################################################
451 15:48:06.260227 #################################################################
452 15:48:06.436419 #################################################################
453 15:48:06.611935 #################################################################
454 15:48:06.702464 #################################
455 15:48:06.702824 5.1 MiB/s
456 15:48:06.703052 done
457 15:48:06.705127 Bytes transferred = 14792426 (e1b6ea hex)
458 15:48:06.705670 Sending with 10 millisecond of delay
460 15:48:08.562880 => setenv initrd_size ${filesize}
461 15:48:08.573372 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
462 15:48:08.573839 setenv initrd_size ${filesize}
463 15:48:08.574288 Sending with 10 millisecond of delay
465 15:48:12.780070 => tftp 0x88000000 1193677/tftp-deploy-x7mixwxv/dtb/am335x-boneblack.dtb
466 15:48:12.790615 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:28)
467 15:48:12.791159 tftp 0x88000000 1193677/tftp-deploy-x7mixwxv/dtb/am335x-boneblack.dtb
468 15:48:12.791466 link up on port 0, speed 100, full duplex
469 15:48:12.791683 Using cpsw device
470 15:48:12.794843 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
471 15:48:12.819923 Filename '1193677/tftp-deploy-x7mixwxv/dtb/am335x-boneblack.dtb'.
472 15:48:12.820178 Load address: 0x88000000
473 15:48:12.820427 Loading: *#####
474 15:48:12.820645 4.5 MiB/s
475 15:48:12.826623 done
476 15:48:12.826850 Bytes transferred = 70568 (113a8 hex)
477 15:48:12.827273 Sending with 10 millisecond of delay
479 15:48:26.126378 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1193677/extract-nfsrootfs-k2t1kv2k,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 15:48:26.136897 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
481 15:48:26.137356 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1193677/extract-nfsrootfs-k2t1kv2k,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
482 15:48:26.137812 Sending with 10 millisecond of delay
484 15:48:28.476892 => bootz 0x82000000 0x83000000 0x88000000
485 15:48:28.487383 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
486 15:48:28.487726 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:12)
487 15:48:28.488342 bootz 0x82000000 0x83000000 0x88000000
488 15:48:28.488607 ## Loading init Ramdisk from Legacy Image at 83000000 ...
489 15:48:28.489091 Image Name:
490 15:48:28.489330 Created: 2024-09-19 15:47:40 UTC
491 15:48:28.494501 Image Type: ARM Linux RAMDisk Image (uncompressed)
492 15:48:28.500144 Data Size: 14792362 Bytes = 14.1 MiB
493 15:48:28.500406 Load Address: 00000000
494 15:48:28.507357 Entry Point: 00000000
495 15:48:28.644757 Verifying Checksum ... OK
496 15:48:28.645035 ## Flattened Device Tree blob at 88000000
497 15:48:28.651203 Booting using the fdt blob at 0x88000000
498 15:48:28.656138 Using Device Tree in place at 88000000, end 880143a7
499 15:48:28.663696
500 15:48:28.663977 Starting kernel ...
501 15:48:28.664218
502 15:48:28.664761 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
503 15:48:28.665064 start: 2.4.4 auto-login-action (timeout 00:04:12) [common]
504 15:48:28.665318 Setting prompt string to ['Linux version [0-9]']
505 15:48:28.665560 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
506 15:48:28.665809 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
507 15:48:29.506851 [ 0.000000] Booting Linux on physical CPU 0x0
508 15:48:29.512763 start: 2.4.4.1 login-action (timeout 00:04:11) [common]
509 15:48:29.513061 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
510 15:48:29.513335 Setting prompt string to []
511 15:48:29.513610 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
512 15:48:29.513888 Using line separator: #'\n'#
513 15:48:29.514131 No login prompt set.
514 15:48:29.514382 Parsing kernel messages
515 15:48:29.514613 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
516 15:48:29.515036 [login-action] Waiting for messages, (timeout 00:04:11)
517 15:48:29.529521 [ 0.000000] Linux version 6.11.0-next-20240919 (KernelCI@build-j314455-arm-gcc-12-multi-v7-defconfig-6hr6q) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Thu Sep 19 07:22:06 UTC 2024
518 15:48:29.535233 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 15:48:29.546698 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 15:48:29.552349 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 15:48:29.558204 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 15:48:29.563856 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 15:48:29.570627 [ 0.000000] Memory policy: Data cache writeback
524 15:48:29.570892 [ 0.000000] efi: UEFI not found.
525 15:48:29.576914 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 15:48:29.582746 [ 0.000000] Zone ranges:
527 15:48:29.588414 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 15:48:29.594127 [ 0.000000] Normal empty
529 15:48:29.594391 [ 0.000000] HighMem empty
530 15:48:29.599875 [ 0.000000] Movable zone start for each node
531 15:48:29.600170 [ 0.000000] Early memory node ranges
532 15:48:29.611231 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 15:48:29.616570 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 15:48:29.641971 [ 0.000000] CPU: All CPU(s) started in SVC mode.
535 15:48:29.647584 [ 0.000000] AM335X ES2.1 (sgx neon)
536 15:48:29.659289 [ 0.000000] percpu: Embedded 17 pages/cpu s40908 r8192 d20532 u69632
537 15:48:29.676921 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1193677/extract-nfsrootfs-k2t1kv2k,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
538 15:48:29.688572 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
539 15:48:29.694286 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
540 15:48:29.700020 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
541 15:48:29.710191 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
542 15:48:29.739209 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
543 15:48:29.745276 <6>[ 0.000000] trace event string verifier disabled
544 15:48:29.745667 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
545 15:48:29.750917 <6>[ 0.000000] rcu: RCU event tracing is enabled.
546 15:48:29.762414 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
547 15:48:29.768028 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
548 15:48:29.775314 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
549 15:48:29.790356 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
550 15:48:29.807352 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
551 15:48:29.814269 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
552 15:48:29.905732 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
553 15:48:29.917090 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
554 15:48:29.923863 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
555 15:48:29.936889 <6>[ 0.019146] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
556 15:48:29.944273 <6>[ 0.033930] Console: colour dummy device 80x30
557 15:48:29.950314 Matched prompt #6: WARNING:
558 15:48:29.950623 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
559 15:48:29.955745 <3>[ 0.038834] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
560 15:48:29.961466 <3>[ 0.045906] This ensures that you still see kernel messages. Please
561 15:48:29.964879 <3>[ 0.052635] update your kernel commandline.
562 15:48:30.005570 <6>[ 0.057249] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
563 15:48:30.011334 <6>[ 0.096154] CPU: Testing write buffer coherency: ok
564 15:48:30.017142 <6>[ 0.101517] CPU0: Spectre v2: using BPIALL workaround
565 15:48:30.017424 <6>[ 0.106984] pid_max: default: 32768 minimum: 301
566 15:48:30.028764 <6>[ 0.112175] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 15:48:30.035641 <6>[ 0.120003] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 15:48:30.042759 <6>[ 0.129357] CPU0: thread -1, cpu 0, socket -1, mpidr 0
569 15:48:30.051161 <6>[ 0.136371] Setting up static identity map for 0x80300000 - 0x803000ac
570 15:48:30.056936 <6>[ 0.146021] rcu: Hierarchical SRCU implementation.
571 15:48:30.064583 <6>[ 0.151309] rcu: Max phase no-delay instances is 1000.
572 15:48:30.073171 <6>[ 0.162437] EFI services will not be available.
573 15:48:30.078894 <6>[ 0.167726] smp: Bringing up secondary CPUs ...
574 15:48:30.084768 <6>[ 0.172773] smp: Brought up 1 node, 1 CPU
575 15:48:30.090508 <6>[ 0.177173] SMP: Total of 1 processors activated (996.14 BogoMIPS).
576 15:48:30.096397 <6>[ 0.183946] CPU: All CPU(s) started in SVC mode.
577 15:48:30.116930 <6>[ 0.189126] Memory: 405988K/522240K available (16384K kernel code, 2548K rwdata, 6788K rodata, 2048K init, 433K bss, 49060K reserved, 65536K cma-reserved, 0K highmem)
578 15:48:30.117225 <6>[ 0.205422] devtmpfs: initialized
579 15:48:30.139025 <6>[ 0.222628] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
580 15:48:30.150630 <6>[ 0.231202] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
581 15:48:30.156438 <6>[ 0.241657] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
582 15:48:30.167185 <6>[ 0.253988] pinctrl core: initialized pinctrl subsystem
583 15:48:30.176661 <6>[ 0.264644] DMI not present or invalid.
584 15:48:30.184944 <6>[ 0.270500] NET: Registered PF_NETLINK/PF_ROUTE protocol family
585 15:48:30.194476 <6>[ 0.279391] DMA: preallocated 256 KiB pool for atomic coherent allocations
586 15:48:30.209404 <6>[ 0.290951] thermal_sys: Registered thermal governor 'step_wise'
587 15:48:30.209686 <6>[ 0.291120] cpuidle: using governor menu
588 15:48:30.237131 <6>[ 0.326762] No ATAGs?
589 15:48:30.243257 <6>[ 0.329499] hw-breakpoint: debug architecture 0x4 unsupported.
590 15:48:30.253559 <6>[ 0.341472] Serial: AMBA PL011 UART driver
591 15:48:30.285879 <6>[ 0.375451] iommu: Default domain type: Translated
592 15:48:30.295069 <6>[ 0.380797] iommu: DMA domain TLB invalidation policy: strict mode
593 15:48:30.322168 <5>[ 0.411004] SCSI subsystem initialized
594 15:48:30.327885 <6>[ 0.415918] usbcore: registered new interface driver usbfs
595 15:48:30.333720 <6>[ 0.421975] usbcore: registered new interface driver hub
596 15:48:30.340487 <6>[ 0.427758] usbcore: registered new device driver usb
597 15:48:30.346196 <6>[ 0.434283] pps_core: LinuxPPS API ver. 1 registered
598 15:48:30.357682 <6>[ 0.439723] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
599 15:48:30.364868 <6>[ 0.449431] PTP clock support registered
600 15:48:30.365104 <6>[ 0.453877] EDAC MC: Ver: 3.0.0
601 15:48:30.413707 <6>[ 0.500791] scmi_core: SCMI protocol bus registered
602 15:48:30.428814 <6>[ 0.518138] vgaarb: loaded
603 15:48:30.441375 <6>[ 0.531150] clocksource: Switched to clocksource dmtimer
604 15:48:30.478498 <6>[ 0.567865] NET: Registered PF_INET protocol family
605 15:48:30.491063 <6>[ 0.573566] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
606 15:48:30.496962 <6>[ 0.582425] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
607 15:48:30.508319 <6>[ 0.591349] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
608 15:48:30.514211 <6>[ 0.599591] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
609 15:48:30.525712 <6>[ 0.607877] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
610 15:48:30.531588 <6>[ 0.615603] TCP: Hash tables configured (established 4096 bind 4096)
611 15:48:30.537308 <6>[ 0.622523] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
612 15:48:30.543227 <6>[ 0.629533] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
613 15:48:30.550736 <6>[ 0.637148] NET: Registered PF_UNIX/PF_LOCAL protocol family
614 15:48:30.641997 <6>[ 0.725914] RPC: Registered named UNIX socket transport module.
615 15:48:30.642282 <6>[ 0.732352] RPC: Registered udp transport module.
616 15:48:30.647750 <6>[ 0.737457] RPC: Registered tcp transport module.
617 15:48:30.653455 <6>[ 0.742578] RPC: Registered tcp-with-tls transport module.
618 15:48:30.666582 <6>[ 0.748485] RPC: Registered tcp NFSv4.1 backchannel transport module.
619 15:48:30.666860 <6>[ 0.755406] PCI: CLS 0 bytes, default 64
620 15:48:30.673758 <5>[ 0.761311] Initialise system trusted keyrings
621 15:48:30.693324 <6>[ 0.779861] Trying to unpack rootfs image as initramfs...
622 15:48:30.777849 <6>[ 0.861281] workingset: timestamp_bits=30 max_order=17 bucket_order=0
623 15:48:30.782504 <6>[ 0.868767] squashfs: version 4.0 (2009/01/31) Phillip Lougher
624 15:48:30.812292 <5>[ 0.901905] NFS: Registering the id_resolver key type
625 15:48:30.818101 <5>[ 0.907496] Key type id_resolver registered
626 15:48:30.823865 <5>[ 0.912182] Key type id_legacy registered
627 15:48:30.829737 <6>[ 0.916626] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
628 15:48:30.839300 <6>[ 0.923824] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
629 15:48:30.912148 <5>[ 1.001858] Key type asymmetric registered
630 15:48:30.918057 <5>[ 1.006384] Asymmetric key parser 'x509' registered
631 15:48:30.929731 <6>[ 1.011911] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
632 15:48:30.930015 <6>[ 1.019794] io scheduler mq-deadline registered
633 15:48:30.935377 <6>[ 1.024773] io scheduler kyber registered
634 15:48:30.941030 <6>[ 1.029226] io scheduler bfq registered
635 15:48:31.076834 <6>[ 1.162657] ledtrig-cpu: registered to indicate activity on CPUs
636 15:48:31.397832 <6>[ 1.483490] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 15:48:31.426735 <6>[ 1.516116] msm_serial: driver initialized
638 15:48:31.432719 <6>[ 1.520893] SuperH (H)SCI(F) driver initialized
639 15:48:31.438704 <6>[ 1.526201] STMicroelectronics ASC driver initialized
640 15:48:31.443921 <6>[ 1.531858] STM32 USART driver initialized
641 15:48:31.565403 <6>[ 1.654440] brd: module loaded
642 15:48:31.615034 <6>[ 1.703952] loop: module loaded
643 15:48:31.650226 <6>[ 1.738922] CAN device driver interface
644 15:48:31.656843 <6>[ 1.744202] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 15:48:31.662696 <6>[ 1.751243] e1000e: Intel(R) PRO/1000 Network Driver
646 15:48:31.668446 <6>[ 1.756630] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 15:48:31.674194 <6>[ 1.763071] igb: Intel(R) Gigabit Ethernet Network Driver
648 15:48:31.682391 <6>[ 1.768895] igb: Copyright (c) 2007-2014 Intel Corporation.
649 15:48:31.694322 <6>[ 1.778277] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 15:48:31.700138 <6>[ 1.784435] usbcore: registered new interface driver pegasus
651 15:48:31.705954 <6>[ 1.790563] usbcore: registered new interface driver asix
652 15:48:31.711702 <6>[ 1.796466] usbcore: registered new interface driver ax88179_178a
653 15:48:31.717453 <6>[ 1.803061] usbcore: registered new interface driver cdc_ether
654 15:48:31.723326 <6>[ 1.809358] usbcore: registered new interface driver smsc75xx
655 15:48:31.729077 <6>[ 1.815587] usbcore: registered new interface driver smsc95xx
656 15:48:31.734868 <6>[ 1.821817] usbcore: registered new interface driver net1080
657 15:48:31.740705 <6>[ 1.827942] usbcore: registered new interface driver cdc_subset
658 15:48:31.746410 <6>[ 1.834358] usbcore: registered new interface driver zaurus
659 15:48:31.754092 <6>[ 1.840406] usbcore: registered new interface driver cdc_ncm
660 15:48:31.764021 <6>[ 1.850008] usbcore: registered new interface driver usb-storage
661 15:48:32.055884 <6>[ 2.143449] i2c_dev: i2c /dev entries driver
662 15:48:32.116686 <5>[ 2.198253] cpuidle: enable-method property 'ti,am3352' found operations
663 15:48:32.122681 <6>[ 2.207918] sdhci: Secure Digital Host Controller Interface driver
664 15:48:32.130179 <6>[ 2.214703] sdhci: Copyright(c) Pierre Ossman
665 15:48:32.137429 <6>[ 2.221344] Synopsys Designware Multimedia Card Interface Driver
666 15:48:32.142852 <6>[ 2.229282] sdhci-pltfm: SDHCI platform and OF driver helper
667 15:48:32.250425 <6>[ 2.332739] usbcore: registered new interface driver usbhid
668 15:48:32.250694 <6>[ 2.338781] usbhid: USB HID core driver
669 15:48:32.300646 <6>[ 2.387672] NET: Registered PF_INET6 protocol family
670 15:48:32.343415 <6>[ 2.433169] Segment Routing with IPv6
671 15:48:32.349367 <6>[ 2.437318] In-situ OAM (IOAM) with IPv6
672 15:48:32.355984 <6>[ 2.441822] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
673 15:48:32.361899 <6>[ 2.449099] NET: Registered PF_PACKET protocol family
674 15:48:32.367646 <6>[ 2.454670] can: controller area network core
675 15:48:32.373507 <6>[ 2.459495] NET: Registered PF_CAN protocol family
676 15:48:32.373759 <6>[ 2.464747] can: raw protocol
677 15:48:32.379252 <6>[ 2.468078] can: broadcast manager protocol
678 15:48:32.385785 <6>[ 2.472679] can: netlink gateway - max_hops=1
679 15:48:32.391919 <5>[ 2.478166] Key type dns_resolver registered
680 15:48:32.398129 <6>[ 2.483250] ThumbEE CPU extension supported.
681 15:48:32.398409 <5>[ 2.487937] Registering SWP/SWPB emulation handler
682 15:48:32.407998 <3>[ 2.493631] omap_voltage_late_init: Voltage driver support not added
683 15:48:32.608136 <5>[ 2.695448] Loading compiled-in X.509 certificates
684 15:48:32.743505 <6>[ 2.820252] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
685 15:48:32.750708 <6>[ 2.836918] pinctrl-single 44e10800.pinmux: 142 pins, size 568
686 15:48:32.776828 <3>[ 2.860490] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
687 15:48:32.977332 <3>[ 3.060943] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
688 15:48:33.163914 <6>[ 3.251818] OMAP GPIO hardware version 0.1
689 15:48:33.184462 <6>[ 3.270369] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
690 15:48:33.277718 <4>[ 3.363417] at24 2-0054: supply vcc not found, using dummy regulator
691 15:48:33.310662 <4>[ 3.396460] at24 2-0055: supply vcc not found, using dummy regulator
692 15:48:33.350203 <4>[ 3.435933] at24 2-0056: supply vcc not found, using dummy regulator
693 15:48:33.388554 <4>[ 3.474250] at24 2-0057: supply vcc not found, using dummy regulator
694 15:48:33.428094 <6>[ 3.514538] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
695 15:48:33.505470 <3>[ 3.587912] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
696 15:48:33.529830 <6>[ 3.608612] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
697 15:48:33.550859 <4>[ 3.635284] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
698 15:48:33.567809 <4>[ 3.652308] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
699 15:48:33.655650 <6>[ 3.741496] omap_rng 48310000.rng: Random Number Generator ver. 20
700 15:48:33.678944 <5>[ 3.767681] random: crng init done
701 15:48:33.711408 <6>[ 3.799409] Freeing initrd memory: 14448K
702 15:48:33.726795 <6>[ 3.811232] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
703 15:48:33.780163 <6>[ 3.863585] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
704 15:48:33.785877 <4>[ 3.873908] ------------[ cut here ]------------
705 15:48:33.797355 <4>[ 3.878946] WARNING: CPU: 0 PID: 38 at drivers/base/regmap/regmap.c:1208 devm_regmap_field_alloc+0xb8/0xc4
706 15:48:33.803106 <4>[ 3.889258] invalid empty mask defined
707 15:48:33.803341 <4>[ 3.893403] Modules linked in:
708 15:48:33.814622 <4>[ 3.896828] CPU: 0 UID: 0 PID: 38 Comm: kworker/u4:4 Not tainted 6.11.0-next-20240919 #1
709 15:48:33.820375 <4>[ 3.905425] Hardware name: Generic AM33XX (Flattened Device Tree)
710 15:48:33.826139 <4>[ 3.911965] Workqueue: events_unbound deferred_probe_work_func
711 15:48:33.826386 <4>[ 3.918250] Call trace:
712 15:48:33.831826 <4>[ 3.918269] unwind_backtrace from show_stack+0x10/0x14
713 15:48:33.837574 <4>[ 3.926800] show_stack from dump_stack_lvl+0x68/0x74
714 15:48:33.843326 <4>[ 3.932282] dump_stack_lvl from __warn+0x7c/0x12c
715 15:48:33.849127 <4>[ 3.937494] __warn from warn_slowpath_fmt+0x124/0x190
716 15:48:33.854825 <4>[ 3.943059] warn_slowpath_fmt from devm_regmap_field_alloc+0xb8/0xc4
717 15:48:33.866347 <4>[ 3.949966] devm_regmap_field_alloc from cpsw_ale_create+0x124/0x368
718 15:48:33.872095 <4>[ 3.956889] cpsw_ale_create from cpsw_init_common+0x238/0x37c
719 15:48:33.877850 <4>[ 3.963170] cpsw_init_common from cpsw_probe+0x530/0xc60
720 15:48:33.883599 <4>[ 3.969004] cpsw_probe from platform_probe+0x5c/0xb0
721 15:48:33.889324 <4>[ 3.974482] platform_probe from really_probe+0xc8/0x2c8
722 15:48:33.895080 <4>[ 3.980224] really_probe from __driver_probe_device+0x88/0x19c
723 15:48:33.900822 <4>[ 3.986589] __driver_probe_device from driver_probe_device+0x30/0x104
724 15:48:33.906597 <4>[ 3.993579] driver_probe_device from __device_attach_driver+0x94/0x108
725 15:48:33.912213 <4>[ 4.000659] __device_attach_driver from bus_for_each_drv+0x90/0xe4
726 15:48:33.917944 <4>[ 4.007379] bus_for_each_drv from __device_attach+0xa8/0x1a4
727 15:48:33.929472 <4>[ 4.013566] __device_attach from bus_probe_device+0x88/0x8c
728 15:48:33.935263 <4>[ 4.019662] bus_probe_device from device_add+0x5b8/0x78c
729 15:48:33.940984 <4>[ 4.025490] device_add from of_platform_device_create_pdata+0x90/0xbc
730 15:48:33.946700 <4>[ 4.032490] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
731 15:48:33.952507 <4>[ 4.040734] of_platform_bus_create from of_platform_populate+0x70/0xd4
732 15:48:33.963815 <4>[ 4.047817] of_platform_populate from sysc_probe+0x100c/0x1418
733 15:48:33.969694 <4>[ 4.054192] sysc_probe from platform_probe+0x5c/0xb0
734 15:48:33.975359 <4>[ 4.059664] platform_probe from really_probe+0xc8/0x2c8
735 15:48:33.981074 <4>[ 4.065406] really_probe from __driver_probe_device+0x88/0x19c
736 15:48:33.986837 <4>[ 4.071771] __driver_probe_device from driver_probe_device+0x30/0x104
737 15:48:33.992600 <4>[ 4.078762] driver_probe_device from __device_attach_driver+0x94/0x108
738 15:48:33.998317 <4>[ 4.085843] __device_attach_driver from bus_for_each_drv+0x90/0xe4
739 15:48:34.004065 <4>[ 4.092565] bus_for_each_drv from __device_attach+0xa8/0x1a4
740 15:48:34.009816 <4>[ 4.098751] __device_attach from bus_probe_device+0x88/0x8c
741 15:48:34.015568 <4>[ 4.104847] bus_probe_device from device_add+0x5b8/0x78c
742 15:48:34.027059 <4>[ 4.110673] device_add from of_platform_device_create_pdata+0x90/0xbc
743 15:48:34.032695 <4>[ 4.117662] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
744 15:48:34.038564 <4>[ 4.125904] of_platform_bus_create from of_platform_populate+0x70/0xd4
745 15:48:34.044264 <4>[ 4.132985] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
746 15:48:34.055687 <4>[ 4.139800] simple_pm_bus_probe from platform_probe+0x5c/0xb0
747 15:48:34.061439 <4>[ 4.146076] platform_probe from really_probe+0xc8/0x2c8
748 15:48:34.067188 <4>[ 4.151817] really_probe from __driver_probe_device+0x88/0x19c
749 15:48:34.072948 <4>[ 4.158185] __driver_probe_device from driver_probe_device+0x30/0x104
750 15:48:34.078718 <4>[ 4.165177] driver_probe_device from __device_attach_driver+0x94/0x108
751 15:48:34.084347 <4>[ 4.172257] __device_attach_driver from bus_for_each_drv+0x90/0xe4
752 15:48:34.090065 <4>[ 4.178979] bus_for_each_drv from __device_attach+0xa8/0x1a4
753 15:48:34.095817 <4>[ 4.185161] __device_attach from bus_probe_device+0x88/0x8c
754 15:48:34.101625 <4>[ 4.191257] bus_probe_device from device_add+0x5b8/0x78c
755 15:48:34.113062 <4>[ 4.197080] device_add from of_platform_device_create_pdata+0x90/0xbc
756 15:48:34.118819 <4>[ 4.204071] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
757 15:48:34.124608 <4>[ 4.212315] of_platform_bus_create from of_platform_populate+0x70/0xd4
758 15:48:34.135938 <4>[ 4.219396] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
759 15:48:34.141707 <4>[ 4.226209] simple_pm_bus_probe from platform_probe+0x5c/0xb0
760 15:48:34.147624 <4>[ 4.232488] platform_probe from really_probe+0xc8/0x2c8
761 15:48:34.153215 <4>[ 4.238231] really_probe from __driver_probe_device+0x88/0x19c
762 15:48:34.158935 <4>[ 4.244598] __driver_probe_device from driver_probe_device+0x30/0x104
763 15:48:34.164686 <4>[ 4.251585] driver_probe_device from __device_attach_driver+0x94/0x108
764 15:48:34.170459 <4>[ 4.258667] __device_attach_driver from bus_for_each_drv+0x90/0xe4
765 15:48:34.176225 <4>[ 4.265387] bus_for_each_drv from __device_attach+0xa8/0x1a4
766 15:48:34.187740 <4>[ 4.271573] __device_attach from bus_probe_device+0x88/0x8c
767 15:48:34.193370 <4>[ 4.277670] bus_probe_device from device_add+0x5b8/0x78c
768 15:48:34.199086 <4>[ 4.283497] device_add from of_platform_device_create_pdata+0x90/0xbc
769 15:48:34.204855 <4>[ 4.290487] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
770 15:48:34.210556 <4>[ 4.298732] of_platform_bus_create from of_platform_populate+0x70/0xd4
771 15:48:34.222052 <4>[ 4.305816] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
772 15:48:34.227809 <4>[ 4.312625] simple_pm_bus_probe from platform_probe+0x5c/0xb0
773 15:48:34.233561 <4>[ 4.318902] platform_probe from really_probe+0xc8/0x2c8
774 15:48:34.239311 <4>[ 4.324643] really_probe from __driver_probe_device+0x88/0x19c
775 15:48:34.245120 <4>[ 4.331008] __driver_probe_device from driver_probe_device+0x30/0x104
776 15:48:34.250743 <4>[ 4.338000] driver_probe_device from __device_attach_driver+0x94/0x108
777 15:48:34.256619 <4>[ 4.345081] __device_attach_driver from bus_for_each_drv+0x90/0xe4
778 15:48:34.267987 <4>[ 4.351802] bus_for_each_drv from __device_attach+0xa8/0x1a4
779 15:48:34.273767 <4>[ 4.357987] __device_attach from bus_probe_device+0x88/0x8c
780 15:48:34.279460 <4>[ 4.364084] bus_probe_device from deferred_probe_work_func+0x78/0xa4
781 15:48:34.285184 <4>[ 4.370985] deferred_probe_work_func from process_one_work+0x178/0x3c0
782 15:48:34.290960 <4>[ 4.378079] process_one_work from worker_thread+0x264/0x42c
783 15:48:34.296681 <4>[ 4.384182] worker_thread from kthread+0xe0/0xfc
784 15:48:34.302429 <4>[ 4.389311] kthread from ret_from_fork+0x14/0x28
785 15:48:34.308179 <4>[ 4.394425] Exception stack(0xe0131fb0 to 0xe0131ff8)
786 15:48:34.313822 <4>[ 4.399891] 1fa0: 00000000 00000000 00000000 00000000
787 15:48:34.325358 <4>[ 4.408570] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
788 15:48:34.331207 <4>[ 4.417250] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000
789 15:48:34.336930 <4>[ 4.424423] ---[ end trace 0000000000000000 ]---
790 15:48:34.337553 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
791 15:48:34.337837 login-action: kernel 'warning'
792 15:48:34.338100 [login-action] Waiting for messages, (timeout 00:04:07)
793 15:48:34.342685 <6>[ 4.429518] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
794 15:48:34.348931 <6>[ 4.436808] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
795 15:48:34.360423 <6>[ 4.444386] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
796 15:48:34.371917 <6>[ 4.452535] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
797 15:48:34.379333 <6>[ 4.464174] cpsw-switch 4a100000.switch: Detected MACID = 64:cf:d9:3f:a0:d5
798 15:48:34.391099 <5>[ 4.473204] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
799 15:48:34.418877 <3>[ 4.502891] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
800 15:48:34.424696 <6>[ 4.511424] edma 49000000.dma: TI EDMA DMA engine driver
801 15:48:34.495351 <3>[ 4.578596] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
802 15:48:34.510167 <6>[ 4.593088] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
803 15:48:34.523071 <3>[ 4.610186] l3-aon-clkctrl:0000:0: failed to disable
804 15:48:34.568396 <6>[ 4.652361] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
805 15:48:34.574036 <6>[ 4.661821] printk: legacy console [ttyS0] enabled
806 15:48:34.579786 <6>[ 4.661821] printk: legacy console [ttyS0] enabled
807 15:48:34.585410 <6>[ 4.672146] printk: legacy bootconsole [omap8250] disabled
808 15:48:34.591211 <6>[ 4.672146] printk: legacy bootconsole [omap8250] disabled
809 15:48:34.629054 <4>[ 4.711918] tps65217-pmic: Failed to locate of_node [id: -1]
810 15:48:34.632604 <4>[ 4.719315] tps65217-bl: Failed to locate of_node [id: -1]
811 15:48:34.649050 <6>[ 4.739008] tps65217 0-0024: TPS65217 ID 0xe version 1.2
812 15:48:34.667542 <6>[ 4.745959] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
813 15:48:34.679299 <6>[ 4.759656] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
814 15:48:34.684959 <6>[ 4.771582] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
815 15:48:34.707159 <6>[ 4.791538] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
816 15:48:34.713032 <6>[ 4.800594] sdhci-omap 48060000.mmc: Got CD GPIO
817 15:48:34.721123 <4>[ 4.805759] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
818 15:48:34.735534 <4>[ 4.819117] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
819 15:48:34.741907 <4>[ 4.827777] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
820 15:48:34.751832 <4>[ 4.836460] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
821 15:48:34.875859 <6>[ 4.961217] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
822 15:48:34.924411 <6>[ 5.007530] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
823 15:48:34.930899 <6>[ 5.016847] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
824 15:48:34.940080 <6>[ 5.025806] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
825 15:48:34.996588 <6>[ 5.083324] mmc1: new high speed MMC card at address 0001
826 15:48:35.004230 <6>[ 5.091992] mmcblk1: mmc1:0001 M62704 3.56 GiB
827 15:48:35.014668 <6>[ 5.103248] mmcblk1: p1
828 15:48:35.020071 <6>[ 5.107431] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
829 15:48:35.027629 <6>[ 5.115895] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
830 15:48:35.040919 <6>[ 5.122595] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
831 15:48:35.056176 <6>[ 5.142236] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
832 15:48:38.198016 <6>[ 8.282183] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
833 15:48:38.271503 <5>[ 8.321238] Sending DHCP requests ., OK
834 15:48:38.282842 <6>[ 8.365672] IP-Config: Got DHCP answer from 192.168.11.1, my address is 192.168.11.7
835 15:48:38.283111 <6>[ 8.373921] IP-Config: Complete:
836 15:48:38.294218 <6>[ 8.377462] device=eth0, hwaddr=64:cf:d9:3f:a0:d5, ipaddr=192.168.11.7, mask=255.255.255.0, gw=192.168.11.1
837 15:48:38.299841 <6>[ 8.388103] host=192.168.11.7, domain=usen.ad.jp, nis-domain=(none)
838 15:48:38.312229 <6>[ 8.395191] bootserver=0.0.0.0, rootserver=192.168.11.5, rootpath=
839 15:48:38.312528 <6>[ 8.395227] nameserver0=192.168.11.1
840 15:48:38.318341 <6>[ 8.407498] clk: Disabling unused clocks
841 15:48:38.324892 <6>[ 8.412264] PM: genpd: Disabling unused power domains
842 15:48:38.345036 <6>[ 8.431455] Freeing unused kernel image (initmem) memory: 2048K
843 15:48:38.352177 <6>[ 8.440982] Run /init as init process
844 15:48:38.374983 Loading, please wait...
845 15:48:38.450941 Starting systemd-udevd version 252.22-1~deb12u1
846 15:48:41.446919 <4>[ 11.529661] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
847 15:48:41.629751 <4>[ 11.712641] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
848 15:48:41.750515 <6>[ 11.840753] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
849 15:48:41.761399 <6>[ 11.846597] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
850 15:48:41.980384 <6>[ 12.069068] hub 1-0:1.0: USB hub found
851 15:48:42.026773 <6>[ 12.115453] hub 1-0:1.0: 1 port detected
852 15:48:42.175909 <6>[ 12.264279] tda998x 0-0070: found TDA19988
853 15:48:45.296487 Begin: Loading essential drivers ... done.
854 15:48:45.302009 Begin: Running /scripts/init-premount ... done.
855 15:48:45.307632 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
856 15:48:45.317794 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
857 15:48:45.325422 Device /sys/class/net/eth0 found
858 15:48:45.325655 done.
859 15:48:45.405990 Begin: Waiting up to 180 secs for any network device to become available ... done.
860 15:48:45.496735 IP-Config: eth0 hardware address 64:cf:d9:3f:a0:d5 mtu 1500 DHCP
861 15:48:45.497016 IP-Config: eth0 guessed broadcast address 192.168.11.255
862 15:48:45.502352 IP-Config: eth0 complete (dhcp from 192.168.11.1):
863 15:48:45.513476 address: 192.168.11.7 broadcast: 192.168.11.255 netmask: 255.255.255.0
864 15:48:45.519227 gateway: 192.168.11.1 dns0 : 192.168.11.1 dns1 : 0.0.0.0
865 15:48:45.524726 domain : usen.ad.jp
866 15:48:45.529679 rootserver: 192.168.11.1 rootpath:
867 15:48:45.529906 filename :
868 15:48:45.595072 done.
869 15:48:45.609112 Begin: Running /scripts/nfs-bottom ... done.
870 15:48:45.675587 Begin: Running /scripts/init-bottom ... done.
871 15:48:47.128840 <30>[ 17.214977] systemd[1]: System time before build time, advancing clock.
872 15:48:47.282299 <30>[ 17.342215] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
873 15:48:47.290986 <30>[ 17.378846] systemd[1]: Detected architecture arm.
874 15:48:47.304853
875 15:48:47.305129 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
876 15:48:47.305358
877 15:48:47.334958 <30>[ 17.421710] systemd[1]: Hostname set to <debian-bookworm-armhf>.
878 15:48:49.535069 <30>[ 19.620639] systemd[1]: Queued start job for default target graphical.target.
879 15:48:49.552044 <30>[ 19.635592] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
880 15:48:49.559635 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
881 15:48:49.580053 <30>[ 19.663996] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
882 15:48:49.588487 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
883 15:48:49.610818 <30>[ 19.694556] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
884 15:48:49.619106 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
885 15:48:49.639208 <30>[ 19.723187] systemd[1]: Created slice user.slice - User and Session Slice.
886 15:48:49.645865 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
887 15:48:49.674315 <30>[ 19.752598] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
888 15:48:49.680417 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
889 15:48:49.698329 <30>[ 19.782382] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
890 15:48:49.707225 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
891 15:48:49.739051 <30>[ 19.812162] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
892 15:48:49.745463 <30>[ 19.832659] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
893 15:48:49.753986 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
894 15:48:49.777311 <30>[ 19.861646] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
895 15:48:49.785489 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
896 15:48:49.808061 <30>[ 19.892030] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
897 15:48:49.816472 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
898 15:48:49.837809 <30>[ 19.922155] systemd[1]: Reached target paths.target - Path Units.
899 15:48:49.842984 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
900 15:48:49.867556 <30>[ 19.951853] systemd[1]: Reached target remote-fs.target - Remote File Systems.
901 15:48:49.874855 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
902 15:48:49.897430 <30>[ 19.981692] systemd[1]: Reached target slices.target - Slice Units.
903 15:48:49.902897 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
904 15:48:49.927678 <30>[ 20.011967] systemd[1]: Reached target swap.target - Swaps.
905 15:48:49.931758 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
906 15:48:49.958181 <30>[ 20.042215] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
907 15:48:49.967127 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
908 15:48:49.988848 <30>[ 20.072751] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
909 15:48:49.997180 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
910 15:48:50.076118 <30>[ 20.155289] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
911 15:48:50.089173 <30>[ 20.173052] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
912 15:48:50.097405 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
913 15:48:50.120719 <30>[ 20.203895] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
914 15:48:50.128153 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
915 15:48:50.150329 <30>[ 20.234351] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
916 15:48:50.158510 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
917 15:48:50.183317 <30>[ 20.266245] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
918 15:48:50.188928 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
919 15:48:50.219987 <30>[ 20.304794] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
920 15:48:50.233020 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
921 15:48:50.264471 <30>[ 20.342610] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
922 15:48:50.282745 <30>[ 20.360767] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
923 15:48:50.331502 <30>[ 20.416460] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
924 15:48:50.358115 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
925 15:48:50.387539 <30>[ 20.471803] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
926 15:48:50.395234 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
927 15:48:50.472085 <30>[ 20.555990] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
928 15:48:50.491123 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
929 15:48:50.557853 <30>[ 20.642277] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
930 15:48:50.585656 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
931 15:48:50.637705 <30>[ 20.722565] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
932 15:48:50.659847 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
933 15:48:50.718060 <30>[ 20.802420] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
934 15:48:50.725079 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
935 15:48:50.758705 <30>[ 20.842858] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
936 15:48:50.796254 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
937 15:48:50.848837 <30>[ 20.933968] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
938 15:48:50.874095 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
939 15:48:50.927839 <30>[ 21.013062] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
940 15:48:50.947102 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
941 15:48:50.974697 <28>[ 21.054685] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
942 15:48:50.986739 <28>[ 21.070987] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
943 15:48:51.036979 <30>[ 21.122542] systemd[1]: Starting systemd-journald.service - Journal Service...
944 15:48:51.055826 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
945 15:48:51.129970 <30>[ 21.214900] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
946 15:48:51.155595 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
947 15:48:51.207595 <30>[ 21.292784] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
948 15:48:51.246256 Starting [0;1;39msystemd-network-g… units from Kernel command line...
949 15:48:51.313981 <30>[ 21.397576] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
950 15:48:51.377099 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
951 15:48:51.440265 <30>[ 21.524689] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
952 15:48:51.486250 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
953 15:48:51.549434 <30>[ 21.634757] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
954 15:48:51.588558 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
955 15:48:51.618173 <30>[ 21.703180] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
956 15:48:51.657274 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
957 15:48:51.682098 <30>[ 21.765997] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
958 15:48:51.710616 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
959 15:48:51.870718 <30>[ 21.956537] systemd[1]: modprobe@configfs.service: Deactivated successfully.
960 15:48:51.908111 <30>[ 21.992815] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
961 15:48:51.937213 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
962 15:48:51.958406 <30>[ 22.042836] systemd[1]: Started systemd-journald.service - Journal Service.
963 15:48:51.965242 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
964 15:48:51.993334 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
965 15:48:52.024131 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
966 15:48:52.058726 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
967 15:48:52.091868 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
968 15:48:52.128482 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
969 15:48:52.157334 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
970 15:48:52.187497 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
971 15:48:52.209831 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
972 15:48:52.237471 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
973 15:48:52.297068 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
974 15:48:52.337074 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
975 15:48:52.399113 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
976 15:48:52.472853 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
977 15:48:52.563653 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
978 15:48:52.699692 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
979 15:48:52.745953 <46>[ 22.831031] systemd-journald[162]: Received client request to flush runtime journal.
980 15:48:52.831598 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
981 15:48:52.972931 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
982 15:48:53.727443 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
983 15:48:53.780781 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
984 15:48:54.572699 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
985 15:48:54.727669 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
986 15:48:54.757284 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
987 15:48:54.777161 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
988 15:48:54.869802 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
989 15:48:54.909294 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
990 15:48:55.831346 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
991 15:48:55.898256 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
992 15:48:56.037333 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
993 15:48:56.137068 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
994 15:48:56.179939 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
995 15:48:58.047553 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
996 15:48:58.757275 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
997 15:48:58.928753 <5>[ 29.014197] cfg80211: Loading compiled-in X.509 certificates for regulatory database
998 15:48:59.729863 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
999 15:49:00.459308 <5>[ 30.546941] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1000 15:49:00.530465 <5>[ 30.616553] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1001 15:49:00.546255 <4>[ 30.631693] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1002 15:49:00.552052 <6>[ 30.640671] cfg80211: failed to load regulatory.db
1003 15:49:00.833533 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1004 15:49:01.170915 <46>[ 31.246325] systemd-journald[162]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1005 15:49:01.325347 <46>[ 31.403884] systemd-journald[162]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
1006 15:49:01.460571 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1007 15:49:10.124253 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1008 15:49:10.147219 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1009 15:49:10.171446 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1010 15:49:10.199233 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1011 15:49:10.257220 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1012 15:49:10.305565 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1013 15:49:10.359021 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1014 15:49:10.442259 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1015 15:49:10.492991 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1016 15:49:10.521979 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1017 15:49:10.564242 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1018 15:49:10.591166 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1019 15:49:10.631261 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1020 15:49:10.683604 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1021 15:49:10.717124 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1022 15:49:10.741036 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1023 15:49:10.779394 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1024 15:49:10.814957 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1025 15:49:10.838513 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1026 15:49:10.857383 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1027 15:49:10.887529 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1028 15:49:10.907531 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1029 15:49:10.933756 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1030 15:49:11.007283 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1031 15:49:11.056832 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1032 15:49:11.163845 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1033 15:49:11.232889 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1034 15:49:11.318622 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1035 15:49:11.353041 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1036 15:49:11.386320 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1037 15:49:11.568272 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1038 15:49:11.616940 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1039 15:49:11.688315 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1040 15:49:11.706027 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1041 15:49:11.736239 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1042 15:49:11.952097 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1043 15:49:12.307074 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1044 15:49:12.334452 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1045 15:49:12.361457 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1046 15:49:12.447204 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1047 15:49:12.616131 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1048 15:49:12.756378
1049 15:49:12.756650 Debian GNU/Linux 1worm-armhf login: root (automatic login)
1050 15:49:12.759536
1051 15:49:13.074474 Linux debian-bookworm-armhf 6.11.0-next-20240919 #1 SMP Thu Sep 19 07:22:06 UTC 2024 armv7l
1052 15:49:13.074909
1053 15:49:13.080071 The programs included with the Debian GNU/Linux system are free software;
1054 15:49:13.085718 the exact distribution terms for each program are described in the
1055 15:49:13.091317 individual files in /usr/share/doc/*/copyright.
1056 15:49:13.091596
1057 15:49:13.096825 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1058 15:49:13.100141 permitted by applicable law.
1059 15:49:17.733823 Matched prompt #10: / #
1061 15:49:17.735237 Kernel warnings or errors detected.
1062 15:49:17.735478 Setting prompt string to ['/ #']
1063 15:49:17.735790 end: 2.4.4.1 login-action (duration 00:00:48) [common]
1065 15:49:17.737097 end: 2.4.4 auto-login-action (duration 00:00:49) [common]
1066 15:49:17.737403 start: 2.4.5 expect-shell-connection (timeout 00:03:23) [common]
1067 15:49:17.737658 Setting prompt string to ['/ #']
1068 15:49:17.737876 Forcing a shell prompt, looking for ['/ #']
1070 15:49:17.788424 / #
1071 15:49:17.788804 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1072 15:49:17.789067 Waiting using forced prompt support (timeout 00:02:30)
1073 15:49:17.793310
1074 15:49:17.802329 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1075 15:49:17.802677 start: 2.4.6 export-device-env (timeout 00:03:23) [common]
1076 15:49:17.802945 Sending with 10 millisecond of delay
1078 15:49:22.851771 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1193677/extract-nfsrootfs-k2t1kv2k'
1079 15:49:22.862391 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1193677/extract-nfsrootfs-k2t1kv2k'
1080 15:49:22.863094 Sending with 10 millisecond of delay
1082 15:49:25.021474 / # export NFS_SERVER_IP='192.168.11.5'
1083 15:49:25.032052 export NFS_SERVER_IP='192.168.11.5'
1084 15:49:25.032857 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1085 15:49:25.033174 end: 2.4 uboot-commands (duration 00:01:44) [common]
1086 15:49:25.033490 end: 2 uboot-action (duration 00:01:44) [common]
1087 15:49:25.033817 start: 3 lava-test-retry (timeout 00:07:16) [common]
1088 15:49:25.034136 start: 3.1 lava-test-shell (timeout 00:07:16) [common]
1089 15:49:25.034398 Using namespace: common
1091 15:49:25.135095 / # #
1092 15:49:25.135474 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1093 15:49:25.139911 #
1094 15:49:25.145703 Using /lava-1193677
1096 15:49:25.246520 / # export SHELL=/bin/bash
1097 15:49:25.251480 export SHELL=/bin/bash
1099 15:49:25.358031 / # . /lava-1193677/environment
1100 15:49:25.362840 . /lava-1193677/environment
1102 15:49:25.475608 / # /lava-1193677/bin/lava-test-runner /lava-1193677/0
1103 15:49:25.475991 Test shell timeout: 10s (minimum of the action and connection timeout)
1104 15:49:25.480453 /lava-1193677/bin/lava-test-runner /lava-1193677/0
1105 15:49:25.867042 + export TESTRUN_ID=0_timesync-off
1106 15:49:25.875083 + TESTRUN_ID=0_timesync-off
1107 15:49:25.875366 + cd /lava-1193677/0/tests/0_timesync-off
1108 15:49:25.875598 ++ cat uuid
1109 15:49:25.890910 + UUID=1193677_1.6.2.4.1
1110 15:49:25.891194 + set +x
1111 15:49:25.896419 <LAVA_SIGNAL_STARTRUN 0_timesync-off 1193677_1.6.2.4.1>
1112 15:49:25.896925 Received signal: <STARTRUN> 0_timesync-off 1193677_1.6.2.4.1
1113 15:49:25.897174 Starting test lava.0_timesync-off (1193677_1.6.2.4.1)
1114 15:49:25.897459 Skipping test definition patterns.
1115 15:49:25.899583 + systemctl stop systemd-timesyncd
1116 15:49:26.198196 + set +x
1117 15:49:26.198768 Received signal: <ENDRUN> 0_timesync-off 1193677_1.6.2.4.1
1118 15:49:26.199049 Ending use of test pattern.
1119 15:49:26.199275 Ending test lava.0_timesync-off (1193677_1.6.2.4.1), duration 0.30
1121 15:49:26.201256 <LAVA_SIGNAL_ENDRUN 0_timesync-off 1193677_1.6.2.4.1>
1122 15:49:26.431063 + export TESTRUN_ID=1_kselftest-dt
1123 15:49:26.439046 + TESTRUN_ID=1_kselftest-dt
1124 15:49:26.439301 + cd /lava-1193677/0/tests/1_kselftest-dt
1125 15:49:26.439534 ++ cat uuid
1126 15:49:26.454507 + UUID=1193677_1.6.2.4.5
1127 15:49:26.454817 + set +x
1128 15:49:26.460152 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1193677_1.6.2.4.5>
1129 15:49:26.460467 + cd ./automated/linux/kselftest/
1130 15:49:26.460915 Received signal: <STARTRUN> 1_kselftest-dt 1193677_1.6.2.4.5
1131 15:49:26.461149 Starting test lava.1_kselftest-dt (1193677_1.6.2.4.5)
1132 15:49:26.461424 Skipping test definition patterns.
1133 15:49:26.486585 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1134 15:49:26.593375 INFO: install_deps skipped
1135 15:49:27.170484 --2024-09-19 15:49:27-- http://storage.kernelci.org/next/master/next-20240919/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1136 15:49:27.197844 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1137 15:49:27.312311 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1138 15:49:27.426462 HTTP request sent, awaiting response... 200 OK
1139 15:49:27.426741 Length: 4112144 (3.9M) [application/octet-stream]
1140 15:49:27.432066 Saving to: 'kselftest_armhf.tar.gz'
1141 15:49:27.432401
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1143 15:49:29.402910
1144 15:49:30.046982 2024-09-19 15:49:29 (1.99 MB/s) - 'kselftest_armhf.tar.gz' saved [4112144/4112144]
1145 15:49:30.047336
1146 15:49:51.878838 skiplist:
1147 15:49:51.879232 ========================================
1148 15:49:51.884487 ========================================
1149 15:49:51.994754 dt:test_unprobed_devices.sh
1150 15:49:52.027096 ============== Tests to run ===============
1151 15:49:52.037031 dt:test_unprobed_devices.sh
1152 15:49:52.041051 ===========End Tests to run ===============
1153 15:49:52.051220 shardfile-dt pass
1154 15:49:52.280624 <12>[ 82.371713] kselftest: Running tests in dt
1155 15:49:52.310484 TAP version 13
1156 15:49:52.332802 1..1
1157 15:49:52.387711 # timeout set to 45
1158 15:49:52.388072 # selftests: dt: test_unprobed_devices.sh
1159 15:49:53.230736 # TAP version 13
1160 15:50:18.235798 # 1..257
1161 15:50:18.404578 # ok 1 / # SKIP
1162 15:50:18.426709 # ok 2 /clk_mcasp0
1163 15:50:18.499265 # ok 3 /clk_mcasp0_fixed # SKIP
1164 15:50:18.575265 # ok 4 /cpus/cpu@0 # SKIP
1165 15:50:18.648332 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1166 15:50:18.666970 # ok 6 /fixedregulator0
1167 15:50:18.684763 # ok 7 /leds
1168 15:50:18.711030 # ok 8 /ocp
1169 15:50:18.730252 # ok 9 /ocp/interconnect@44c00000
1170 15:50:18.758954 # ok 10 /ocp/interconnect@44c00000/segment@0
1171 15:50:18.780719 # ok 11 /ocp/interconnect@44c00000/segment@100000
1172 15:50:18.806600 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1173 15:50:18.878810 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1174 15:50:18.898970 # ok 14 /ocp/interconnect@44c00000/segment@200000
1175 15:50:18.924620 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1176 15:50:19.031578 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1177 15:50:19.101002 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1178 15:50:19.182686 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1179 15:50:19.253247 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1180 15:50:19.322598 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1181 15:50:19.399961 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1182 15:50:19.469701 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1183 15:50:19.542577 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1184 15:50:19.615687 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1185 15:50:19.688732 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1186 15:50:19.760385 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1187 15:50:19.838715 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1188 15:50:19.907924 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1189 15:50:19.980274 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1190 15:50:20.053984 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1191 15:50:20.125258 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1192 15:50:20.197958 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1193 15:50:20.271113 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1194 15:50:20.343553 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1195 15:50:20.417350 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1196 15:50:20.489278 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1197 15:50:20.562823 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1198 15:50:20.640274 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1199 15:50:20.709701 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1200 15:50:20.782482 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1201 15:50:20.854937 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1202 15:50:20.928921 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1203 15:50:21.001516 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1204 15:50:21.079937 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1205 15:50:21.148715 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1206 15:50:21.221348 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1207 15:50:21.295669 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1208 15:50:21.366673 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1209 15:50:21.440941 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1210 15:50:21.517703 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1211 15:50:21.592047 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1212 15:50:21.664194 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1213 15:50:21.738839 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1214 15:50:21.809102 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1215 15:50:21.881100 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1216 15:50:21.957356 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1217 15:50:22.032838 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1218 15:50:22.103523 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1219 15:50:22.179148 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1220 15:50:22.248092 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1221 15:50:22.320880 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1222 15:50:22.401834 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1223 15:50:22.472258 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1224 15:50:22.543735 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1225 15:50:22.618482 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1226 15:50:22.687600 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1227 15:50:22.761207 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1228 15:50:22.834828 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1229 15:50:22.909440 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1230 15:50:22.983307 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1231 15:50:23.060323 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1232 15:50:23.132817 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1233 15:50:23.204069 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1234 15:50:23.273314 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1235 15:50:23.349684 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1236 15:50:23.423080 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1237 15:50:23.494192 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1238 15:50:23.567570 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1239 15:50:23.640292 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1240 15:50:23.713881 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1241 15:50:23.791618 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1242 15:50:23.863756 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1243 15:50:23.938444 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1244 15:50:24.007773 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1245 15:50:24.079403 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1246 15:50:24.152176 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1247 15:50:24.229425 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1248 15:50:24.302441 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1249 15:50:24.374667 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1250 15:50:24.448571 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1251 15:50:24.515818 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1252 15:50:24.589901 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1253 15:50:24.661659 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1254 15:50:24.734897 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1255 15:50:24.755565 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1256 15:50:24.779764 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1257 15:50:24.804016 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1258 15:50:24.827399 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1259 15:50:24.852765 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1260 15:50:24.874541 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1261 15:50:24.898836 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1262 15:50:24.921647 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1263 15:50:25.027084 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1264 15:50:25.051650 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1265 15:50:25.076150 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1266 15:50:25.099230 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1267 15:50:25.205348 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1268 15:50:25.281390 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1269 15:50:25.354228 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1270 15:50:25.426540 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1271 15:50:25.498986 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1272 15:50:25.571228 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1273 15:50:25.643872 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1274 15:50:25.720863 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1275 15:50:25.794582 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1276 15:50:25.863986 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1277 15:50:25.941089 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1278 15:50:26.014000 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1279 15:50:26.084339 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1280 15:50:26.163982 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1281 15:50:26.231672 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1282 15:50:26.305164 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1283 15:50:26.326912 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1284 15:50:26.398304 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1285 15:50:26.468424 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1286 15:50:26.545293 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1287 15:50:26.565157 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1288 15:50:26.638703 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1289 15:50:26.661489 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1290 15:50:26.734178 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1291 15:50:26.756236 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1292 15:50:26.780423 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1293 15:50:26.807966 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1294 15:50:26.831317 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1295 15:50:26.851476 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1296 15:50:26.875968 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1297 15:50:26.901710 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1298 15:50:26.981313 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1299 15:50:26.999322 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1300 15:50:27.027823 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1301 15:50:27.101337 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1302 15:50:27.173061 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1303 15:50:27.195587 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1304 15:50:27.291952 # not ok 144 /ocp/interconnect@47c00000
1305 15:50:27.363957 # not ok 145 /ocp/interconnect@47c00000/segment@0
1306 15:50:27.384714 # ok 146 /ocp/interconnect@48000000
1307 15:50:27.414591 # ok 147 /ocp/interconnect@48000000/segment@0
1308 15:50:27.433278 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1309 15:50:27.457143 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1310 15:50:27.484278 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1311 15:50:27.508168 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1312 15:50:27.530206 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1313 15:50:27.556231 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1314 15:50:27.578323 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1315 15:50:27.650409 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1316 15:50:27.721398 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1317 15:50:27.742425 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1318 15:50:27.766226 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1319 15:50:27.788562 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1320 15:50:27.813101 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1321 15:50:27.835332 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1322 15:50:27.859662 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1323 15:50:27.887023 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1324 15:50:27.910911 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1325 15:50:27.935299 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1326 15:50:27.955267 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1327 15:50:27.980056 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1328 15:50:28.001530 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1329 15:50:28.030267 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1330 15:50:28.054965 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1331 15:50:28.072990 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1332 15:50:28.098464 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1333 15:50:28.121112 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1334 15:50:28.150234 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1335 15:50:28.168989 # ok 175 /ocp/interconnect@48000000/segment@100000
1336 15:50:28.192692 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1337 15:50:28.216936 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1338 15:50:28.290310 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1339 15:50:28.370715 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1340 15:50:28.436694 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1341 15:50:28.511207 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1342 15:50:28.581797 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1343 15:50:28.655698 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1344 15:50:28.727313 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1345 15:50:28.802295 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1346 15:50:28.822461 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1347 15:50:28.850065 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1348 15:50:28.870687 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1349 15:50:28.893440 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1350 15:50:28.920570 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1351 15:50:28.949481 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1352 15:50:28.964659 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1353 15:50:28.990060 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1354 15:50:29.013674 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1355 15:50:29.040559 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1356 15:50:29.068537 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1357 15:50:29.085295 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1358 15:50:29.106784 # ok 198 /ocp/interconnect@48000000/segment@200000
1359 15:50:29.136338 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1360 15:50:29.210195 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1361 15:50:29.228686 # ok 201 /ocp/interconnect@48000000/segment@300000
1362 15:50:29.255186 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1363 15:50:29.274832 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1364 15:50:29.299176 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1365 15:50:29.322450 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1366 15:50:29.345950 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1367 15:50:29.369179 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1368 15:50:29.442278 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1369 15:50:29.461121 # ok 209 /ocp/interconnect@4a000000
1370 15:50:29.488302 # ok 210 /ocp/interconnect@4a000000/segment@0
1371 15:50:29.517972 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1372 15:50:29.535165 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1373 15:50:29.566040 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1374 15:50:29.587502 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1375 15:50:29.659907 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1376 15:50:29.763112 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1377 15:50:29.842002 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1378 15:50:29.947251 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1379 15:50:30.018589 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1380 15:50:30.090474 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1381 15:50:30.187967 # not ok 221 /ocp/interconnect@4b140000
1382 15:50:30.260398 # not ok 222 /ocp/interconnect@4b140000/segment@0
1383 15:50:30.337086 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1384 15:50:30.357462 # ok 224 /ocp/target-module@40300000
1385 15:50:30.381959 # ok 225 /ocp/target-module@40300000/sram@0
1386 15:50:30.457369 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1387 15:50:30.530232 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1388 15:50:30.547467 # ok 228 /ocp/target-module@47400000
1389 15:50:30.571615 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1390 15:50:30.593554 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1391 15:50:30.618607 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1392 15:50:30.643858 # ok 232 /ocp/target-module@47400000/usb@1400
1393 15:50:30.667234 # ok 233 /ocp/target-module@47400000/usb@1800
1394 15:50:30.684573 # ok 234 /ocp/target-module@47810000
1395 15:50:30.712410 # ok 235 /ocp/target-module@49000000
1396 15:50:30.730070 # ok 236 /ocp/target-module@49000000/dma@0
1397 15:50:30.752920 # ok 237 /ocp/target-module@49800000
1398 15:50:30.778178 # ok 238 /ocp/target-module@49800000/dma@0
1399 15:50:30.802936 # ok 239 /ocp/target-module@49900000
1400 15:50:30.822345 # ok 240 /ocp/target-module@49900000/dma@0
1401 15:50:30.847626 # ok 241 /ocp/target-module@49a00000
1402 15:50:30.867477 # ok 242 /ocp/target-module@49a00000/dma@0
1403 15:50:30.889606 # ok 243 /ocp/target-module@4c000000
1404 15:50:30.961399 # not ok 244 /ocp/target-module@4c000000/emif@0
1405 15:50:30.982716 # ok 245 /ocp/target-module@50000000
1406 15:50:31.007690 # ok 246 /ocp/target-module@53100000
1407 15:50:31.082846 # not ok 247 /ocp/target-module@53100000/sham@0
1408 15:50:31.104634 # ok 248 /ocp/target-module@53500000
1409 15:50:31.176831 # not ok 249 /ocp/target-module@53500000/aes@0
1410 15:50:31.193941 # ok 250 /ocp/target-module@56000000
1411 15:50:31.300388 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1412 15:50:31.374222 # ok 252 /opp-table # SKIP
1413 15:50:31.444293 # ok 253 /soc # SKIP
1414 15:50:31.459948 # ok 254 /sound
1415 15:50:31.484236 # ok 255 /target-module@4b000000
1416 15:50:31.513694 # ok 256 /target-module@4b000000/target-module@140000
1417 15:50:31.529090 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1418 15:50:31.537394 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1419 15:50:31.547796 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1420 15:50:33.770839 dt_test_unprobed_devices_sh_ skip
1421 15:50:33.776384 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1422 15:50:33.782031 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1423 15:50:33.782317 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1424 15:50:33.787632 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1425 15:50:33.793254 dt_test_unprobed_devices_sh_fixedregulator0 pass
1426 15:50:33.798887 dt_test_unprobed_devices_sh_leds pass
1427 15:50:33.799145 dt_test_unprobed_devices_sh_ocp pass
1428 15:50:33.804528 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1429 15:50:33.810136 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1430 15:50:33.815634 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1431 15:50:33.826875 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1432 15:50:33.832503 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1433 15:50:33.838151 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1434 15:50:33.849277 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1435 15:50:33.854902 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1436 15:50:33.866139 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1437 15:50:33.877386 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1438 15:50:33.888637 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1439 15:50:33.894137 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1440 15:50:33.905465 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1441 15:50:33.916688 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1442 15:50:33.927755 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1443 15:50:33.938998 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1444 15:50:33.944643 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1445 15:50:33.955773 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1446 15:50:33.967001 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1447 15:50:33.978141 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1448 15:50:33.989400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1449 15:50:33.995002 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1450 15:50:34.006127 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1451 15:50:34.017394 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1452 15:50:34.028683 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1453 15:50:34.034142 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1454 15:50:34.045398 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1455 15:50:34.056647 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1456 15:50:34.067835 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1457 15:50:34.078892 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1458 15:50:34.084503 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1459 15:50:34.095747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1460 15:50:34.106870 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1461 15:50:34.118116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1462 15:50:34.129244 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1463 15:50:34.140492 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1464 15:50:34.151616 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1465 15:50:34.162868 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1466 15:50:34.173991 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1467 15:50:34.185243 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1468 15:50:34.196374 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1469 15:50:34.207591 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1470 15:50:34.218689 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1471 15:50:34.229933 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1472 15:50:34.241072 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1473 15:50:34.252318 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1474 15:50:34.263563 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1475 15:50:34.274685 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1476 15:50:34.285818 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1477 15:50:34.297062 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1478 15:50:34.308182 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1479 15:50:34.319430 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1480 15:50:34.330713 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1481 15:50:34.341808 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1482 15:50:34.353060 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1483 15:50:34.364183 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1484 15:50:34.369807 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1485 15:50:34.381062 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1486 15:50:34.392176 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1487 15:50:34.403452 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1488 15:50:34.414559 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1489 15:50:34.425811 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1490 15:50:34.436932 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1491 15:50:34.448183 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1492 15:50:34.459303 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1493 15:50:34.470566 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1494 15:50:34.481679 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1495 15:50:34.492929 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1496 15:50:34.504163 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1497 15:50:34.515317 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1498 15:50:34.526605 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1499 15:50:34.537756 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1500 15:50:34.548873 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1501 15:50:34.560121 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1502 15:50:34.565732 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1503 15:50:34.576855 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1504 15:50:34.588103 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1505 15:50:34.599257 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1506 15:50:34.610478 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1507 15:50:34.616101 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1508 15:50:34.632851 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1509 15:50:34.643972 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1510 15:50:34.649607 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1511 15:50:34.666348 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1512 15:50:34.677599 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1513 15:50:34.688846 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1514 15:50:34.694348 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1515 15:50:34.705599 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1516 15:50:34.716721 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1517 15:50:34.722350 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1518 15:50:34.733597 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1519 15:50:34.744719 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1520 15:50:34.750349 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1521 15:50:34.761595 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1522 15:50:34.767117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1523 15:50:34.778345 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1524 15:50:34.789610 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1525 15:50:34.800764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1526 15:50:34.811917 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1527 15:50:34.823157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1528 15:50:34.834287 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1529 15:50:34.845532 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1530 15:50:34.856645 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1531 15:50:34.867905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1532 15:50:34.879031 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1533 15:50:34.890281 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1534 15:50:34.901408 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1535 15:50:34.918280 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1536 15:50:34.929401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1537 15:50:34.940656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1538 15:50:34.951776 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1539 15:50:34.963027 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1540 15:50:34.979777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1541 15:50:34.991031 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1542 15:50:35.002153 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1543 15:50:35.013408 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1544 15:50:35.019024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1545 15:50:35.030155 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1546 15:50:35.041404 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1547 15:50:35.046902 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1548 15:50:35.058149 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1549 15:50:35.063777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1550 15:50:35.074897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1551 15:50:35.080530 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1552 15:50:35.091773 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1553 15:50:35.097278 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1554 15:50:35.108527 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1555 15:50:35.114153 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1556 15:50:35.125273 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1557 15:50:35.136529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1558 15:50:35.147648 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1559 15:50:35.158899 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1560 15:50:35.170023 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1561 15:50:35.175572 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1562 15:50:35.186792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1563 15:50:35.192313 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1564 15:50:35.197987 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1565 15:50:35.203715 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1566 15:50:35.209391 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1567 15:50:35.214711 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1568 15:50:35.225903 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1569 15:50:35.231553 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1570 15:50:35.237123 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1571 15:50:35.248311 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1572 15:50:35.253933 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1573 15:50:35.265086 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1574 15:50:35.270693 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1575 15:50:35.281902 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1576 15:50:35.287556 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1577 15:50:35.298717 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1578 15:50:35.304309 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1579 15:50:35.315548 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1580 15:50:35.321022 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1581 15:50:35.332140 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1582 15:50:35.337766 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1583 15:50:35.349085 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1584 15:50:35.354705 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1585 15:50:35.360175 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1586 15:50:35.371443 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1587 15:50:35.377048 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1588 15:50:35.388169 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1589 15:50:35.393819 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1590 15:50:35.404976 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1591 15:50:35.410584 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1592 15:50:35.421827 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1593 15:50:35.427324 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1594 15:50:35.432971 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1595 15:50:35.444220 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1596 15:50:35.449701 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1597 15:50:35.460955 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1598 15:50:35.472075 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1599 15:50:35.483349 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1600 15:50:35.494578 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1601 15:50:35.505829 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1602 15:50:35.516945 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1603 15:50:35.528097 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1604 15:50:35.539324 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1605 15:50:35.544844 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1606 15:50:35.556067 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1607 15:50:35.561719 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1608 15:50:35.572853 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1609 15:50:35.578573 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1610 15:50:35.589682 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1611 15:50:35.595182 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1612 15:50:35.606416 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1613 15:50:35.612014 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1614 15:50:35.623128 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1615 15:50:35.628818 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1616 15:50:35.639883 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1617 15:50:35.645537 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1618 15:50:35.656814 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1619 15:50:35.662280 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1620 15:50:35.667881 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1621 15:50:35.679193 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1622 15:50:35.684690 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1623 15:50:35.695909 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1624 15:50:35.701566 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1625 15:50:35.712660 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1626 15:50:35.718316 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1627 15:50:35.729583 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1628 15:50:35.735062 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1629 15:50:35.740658 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1630 15:50:35.746294 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1631 15:50:35.757560 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1632 15:50:35.768634 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1633 15:50:35.774258 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1634 15:50:35.779880 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1635 15:50:35.791059 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1636 15:50:35.802277 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1637 15:50:35.813559 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1638 15:50:35.824690 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1639 15:50:35.830285 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1640 15:50:35.835910 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1641 15:50:35.841572 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1642 15:50:35.847186 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1643 15:50:35.852936 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1644 15:50:35.858533 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1645 15:50:35.869664 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1646 15:50:35.875310 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1647 15:50:35.880910 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1648 15:50:35.886526 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1649 15:50:35.892065 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1650 15:50:35.903308 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1651 15:50:35.908911 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1652 15:50:35.914509 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1653 15:50:35.920001 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1654 15:50:35.925628 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1655 15:50:35.931246 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1656 15:50:35.936877 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1657 15:50:35.942616 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1658 15:50:35.948057 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1659 15:50:35.953673 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1660 15:50:35.959280 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1661 15:50:35.964933 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1662 15:50:35.970557 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1663 15:50:35.976055 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1664 15:50:35.981696 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1665 15:50:35.987306 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1666 15:50:35.992938 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1667 15:50:35.998538 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1668 15:50:36.004056 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1669 15:50:36.009673 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1670 15:50:36.015305 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1671 15:50:36.015553 dt_test_unprobed_devices_sh_opp-table skip
1672 15:50:36.020935 dt_test_unprobed_devices_sh_soc skip
1673 15:50:36.026556 dt_test_unprobed_devices_sh_sound pass
1674 15:50:36.032167 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1675 15:50:36.037805 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1676 15:50:36.043433 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1677 15:50:36.048953 dt_test_unprobed_devices_sh fail
1678 15:50:36.049197 + ../../utils/send-to-lava.sh ./output/result.txt
1679 15:50:36.054543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1680 15:50:36.055100 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1682 15:50:36.063707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1683 15:50:36.064131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1685 15:50:36.158624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1686 15:50:36.159100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1688 15:50:36.256620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1689 15:50:36.257166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1691 15:50:36.355598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1692 15:50:36.356072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1694 15:50:36.453923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1695 15:50:36.454404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1697 15:50:36.551450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1698 15:50:36.552012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1700 15:50:36.647139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1701 15:50:36.647642 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1703 15:50:36.741034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1704 15:50:36.741521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1706 15:50:36.841645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1707 15:50:36.842134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1709 15:50:36.938889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1710 15:50:36.939379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1712 15:50:37.033656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1713 15:50:37.034145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1715 15:50:37.133272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1716 15:50:37.133763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1718 15:50:37.231008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1719 15:50:37.231584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1721 15:50:37.326248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1722 15:50:37.326740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1724 15:50:37.426310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1725 15:50:37.426804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1727 15:50:37.524816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1728 15:50:37.525429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1730 15:50:37.628022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1731 15:50:37.628556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1733 15:50:37.726682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1734 15:50:37.727170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1736 15:50:37.824700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1737 15:50:37.825185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1739 15:50:37.923016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1740 15:50:37.923504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1742 15:50:38.021915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1743 15:50:38.022409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1745 15:50:38.119726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1746 15:50:38.120217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1748 15:50:38.217218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1749 15:50:38.217847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1751 15:50:38.316342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1752 15:50:38.316838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1754 15:50:38.418878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1755 15:50:38.419374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1757 15:50:38.515461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1758 15:50:38.516112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1760 15:50:38.612136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1761 15:50:38.612695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1763 15:50:38.710509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1764 15:50:38.711000 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1766 15:50:38.808918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1767 15:50:38.809418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1769 15:50:38.906650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1770 15:50:38.907160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1772 15:50:39.001482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1773 15:50:39.001988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1775 15:50:39.094136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1776 15:50:39.094622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1778 15:50:39.193167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1779 15:50:39.193726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1781 15:50:39.292283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1782 15:50:39.292852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1784 15:50:39.391078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1785 15:50:39.391575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1787 15:50:39.488751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1788 15:50:39.489253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1790 15:50:39.588379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1791 15:50:39.588988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1793 15:50:39.680708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1794 15:50:39.681169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1796 15:50:39.777594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1797 15:50:39.778081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1799 15:50:39.877514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1800 15:50:39.878013 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1802 15:50:39.976877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1803 15:50:39.977370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1805 15:50:40.075999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1806 15:50:40.076522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1808 15:50:40.174490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1809 15:50:40.174997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1811 15:50:40.273126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1812 15:50:40.273705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1814 15:50:40.372611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1815 15:50:40.373124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1817 15:50:40.472713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1818 15:50:40.473204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1820 15:50:40.571462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1821 15:50:40.572025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1823 15:50:40.667203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1824 15:50:40.667694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1826 15:50:40.768832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1827 15:50:40.769344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1829 15:50:40.868986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1830 15:50:40.869493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1832 15:50:40.966739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1833 15:50:40.967249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1835 15:50:41.068265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1836 15:50:41.068757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1838 15:50:41.170072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1839 15:50:41.170565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1841 15:50:41.268586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1842 15:50:41.269148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1844 15:50:41.363617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1845 15:50:41.364097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1847 15:50:41.455275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1848 15:50:41.455754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1850 15:50:41.550571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1851 15:50:41.551148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1853 15:50:41.641863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1854 15:50:41.642354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1856 15:50:41.736421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1857 15:50:41.736900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1859 15:50:41.827860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1860 15:50:41.828361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1862 15:50:41.920875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1863 15:50:41.921365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1865 15:50:42.016130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1866 15:50:42.016625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1868 15:50:42.109390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1869 15:50:42.109875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1871 15:50:42.205030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1872 15:50:42.205534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1874 15:50:42.298155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1875 15:50:42.298727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1877 15:50:42.391689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1878 15:50:42.392169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1880 15:50:42.489741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1881 15:50:42.490231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1883 15:50:42.582488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1884 15:50:42.583046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1886 15:50:42.676060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1887 15:50:42.676618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1889 15:50:42.770814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1890 15:50:42.771352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1892 15:50:42.864330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1893 15:50:42.864872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1895 15:50:42.960421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1896 15:50:42.960911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1898 15:50:43.053871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1899 15:50:43.054409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1901 15:50:43.147900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1902 15:50:43.148455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1904 15:50:43.244155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1905 15:50:43.244761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1907 15:50:43.339697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1908 15:50:43.340171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1910 15:50:43.437697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1911 15:50:43.438185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1913 15:50:43.532912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1914 15:50:43.533473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1916 15:50:43.630917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1917 15:50:43.631480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1919 15:50:43.729388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1920 15:50:43.729894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1922 15:50:43.827520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1923 15:50:43.827937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1925 15:50:43.926071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1926 15:50:43.926584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1928 15:50:44.023852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1929 15:50:44.024335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1931 15:50:44.118864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1932 15:50:44.119365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1934 15:50:44.218694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1935 15:50:44.219174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1937 15:50:44.317262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1938 15:50:44.317804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1940 15:50:44.414600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1941 15:50:44.415108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1943 15:50:44.508866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1944 15:50:44.509373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1946 15:50:44.610488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1947 15:50:44.611081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1949 15:50:44.710823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1950 15:50:44.711323 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1952 15:50:44.808476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1953 15:50:44.808976 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1955 15:50:44.911434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1956 15:50:44.911914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1958 15:50:45.006381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1959 15:50:45.006871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1961 15:50:45.103875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1962 15:50:45.104366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1964 15:50:45.196372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1965 15:50:45.196868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1967 15:50:45.291087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1968 15:50:45.291661 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1970 15:50:45.387957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1971 15:50:45.388460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1973 15:50:45.481947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1974 15:50:45.482443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1976 15:50:45.578262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1977 15:50:45.578823 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1979 15:50:45.671591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1980 15:50:45.672071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1982 15:50:45.763522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1983 15:50:45.764006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1985 15:50:45.853617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1986 15:50:45.854097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1988 15:50:45.947152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1989 15:50:45.947654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1991 15:50:46.040774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1992 15:50:46.041278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1994 15:50:46.135540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1995 15:50:46.136028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1997 15:50:46.229167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1998 15:50:46.229669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
2000 15:50:46.321772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
2001 15:50:46.322359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
2003 15:50:46.417889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
2004 15:50:46.418382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
2006 15:50:46.511671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
2007 15:50:46.512161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
2009 15:50:46.606388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
2010 15:50:46.606972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
2012 15:50:46.701510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
2013 15:50:46.702010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
2015 15:50:46.796013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
2016 15:50:46.796542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
2018 15:50:46.889873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
2019 15:50:46.890362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
2021 15:50:46.982755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
2022 15:50:46.983252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
2024 15:50:47.077269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
2025 15:50:47.077773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
2027 15:50:47.169871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
2028 15:50:47.170361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
2030 15:50:47.265880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
2031 15:50:47.266457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
2033 15:50:47.362317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
2034 15:50:47.362775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
2036 15:50:47.458205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
2037 15:50:47.458677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
2039 15:50:47.558448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
2041 15:50:47.561405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
2042 15:50:47.657160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
2044 15:50:47.660272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2045 15:50:47.754511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2047 15:50:47.757612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2048 15:50:47.853506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2049 15:50:47.854020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2051 15:50:47.950611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2052 15:50:47.951101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2054 15:50:48.041608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2055 15:50:48.042101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2057 15:50:48.139109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2058 15:50:48.139636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2060 15:50:48.237278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2061 15:50:48.237805 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2063 15:50:48.336897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2064 15:50:48.337474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2066 15:50:48.434348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2067 15:50:48.434837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2069 15:50:48.530015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2070 15:50:48.530512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2072 15:50:48.626815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2073 15:50:48.627363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2075 15:50:48.720717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2076 15:50:48.721209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2078 15:50:48.816217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2079 15:50:48.816696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2081 15:50:48.909194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2082 15:50:48.909686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2084 15:50:49.001341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2085 15:50:49.001820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2087 15:50:49.093008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2088 15:50:49.093482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2090 15:50:49.189442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2091 15:50:49.189926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2093 15:50:49.283166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2094 15:50:49.283723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2096 15:50:49.377143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2097 15:50:49.377622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2099 15:50:49.470725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2100 15:50:49.471204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2102 15:50:49.568810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2103 15:50:49.569393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2105 15:50:49.662514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2106 15:50:49.663001 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2108 15:50:49.752275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2109 15:50:49.752768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2111 15:50:49.843823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2112 15:50:49.844313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2114 15:50:49.937531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2115 15:50:49.938023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2117 15:50:50.034121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2118 15:50:50.034618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2120 15:50:50.126918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2121 15:50:50.127450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2123 15:50:50.222156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2124 15:50:50.222646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2126 15:50:50.313663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2127 15:50:50.314233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2129 15:50:50.407152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2130 15:50:50.407639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2132 15:50:50.499392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2133 15:50:50.499881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2135 15:50:50.593051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2136 15:50:50.593620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2138 15:50:50.688143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2139 15:50:50.688643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2141 15:50:50.781649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2142 15:50:50.782133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2144 15:50:50.872471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2145 15:50:50.872960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2147 15:50:50.970641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2148 15:50:50.971126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2150 15:50:51.061512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2151 15:50:51.061999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2153 15:50:51.157269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2154 15:50:51.157755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2156 15:50:51.252793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2157 15:50:51.253288 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2159 15:50:51.348983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2160 15:50:51.349569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2162 15:50:51.445119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2163 15:50:51.445610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2165 15:50:51.539490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2166 15:50:51.539987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2168 15:50:51.635744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2169 15:50:51.636333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2171 15:50:51.731050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2172 15:50:51.731537 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2174 15:50:51.822150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2175 15:50:51.822647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2177 15:50:51.920519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2178 15:50:51.921059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2180 15:50:52.016147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2181 15:50:52.016658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2183 15:50:52.115890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2184 15:50:52.116384 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2186 15:50:52.212512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2187 15:50:52.213003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2189 15:50:52.315173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2190 15:50:52.315744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2192 15:50:52.421250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2193 15:50:52.421739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2195 15:50:52.519122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2196 15:50:52.519609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2198 15:50:52.612636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2199 15:50:52.613207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2201 15:50:52.711739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2202 15:50:52.712244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2204 15:50:52.805493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2205 15:50:52.805985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2207 15:50:52.902939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2208 15:50:52.903427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2210 15:50:52.997842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2211 15:50:52.998336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2213 15:50:53.097851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2214 15:50:53.098347 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2216 15:50:53.196418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2217 15:50:53.196918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2219 15:50:53.294266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2220 15:50:53.294874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2222 15:50:53.393272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2223 15:50:53.393765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2225 15:50:53.482995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2226 15:50:53.483474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2228 15:50:53.580496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2229 15:50:53.581120 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2231 15:50:53.673920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2232 15:50:53.674411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2234 15:50:53.770203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2235 15:50:53.770713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2237 15:50:53.863460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2238 15:50:53.863950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2240 15:50:53.959486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2241 15:50:53.959977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2243 15:50:54.057665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2244 15:50:54.058154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2246 15:50:54.158162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2247 15:50:54.158644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2249 15:50:54.256908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2250 15:50:54.257391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2252 15:50:54.353297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2253 15:50:54.353861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2255 15:50:54.446658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2256 15:50:54.447149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2258 15:50:54.540180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2259 15:50:54.540695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2261 15:50:54.633787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2262 15:50:54.634367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2264 15:50:54.729665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2265 15:50:54.730158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2267 15:50:54.826201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2268 15:50:54.826693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2270 15:50:54.920016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2271 15:50:54.920525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2273 15:50:55.013744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2274 15:50:55.014236 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2276 15:50:55.106377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2277 15:50:55.106871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2279 15:50:55.202094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2280 15:50:55.202583 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2282 15:50:55.292750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2283 15:50:55.293331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2285 15:50:55.390146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2286 15:50:55.390635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2288 15:50:55.483747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2289 15:50:55.484254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2291 15:50:55.581333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2292 15:50:55.581952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2294 15:50:55.676063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2295 15:50:55.676649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2297 15:50:55.773990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2298 15:50:55.774475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2300 15:50:55.868247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2301 15:50:55.868746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2303 15:50:55.960613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2304 15:50:55.961113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2306 15:50:56.051090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2307 15:50:56.051574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2309 15:50:56.147963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2310 15:50:56.148475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2312 15:50:56.245142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2313 15:50:56.245633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2315 15:50:56.340435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2316 15:50:56.341026 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2318 15:50:56.434813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2319 15:50:56.435325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2321 15:50:56.530276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2322 15:50:56.530767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2324 15:50:56.626974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2325 15:50:56.627544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2327 15:50:56.722490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2328 15:50:56.722971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2330 15:50:56.819751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2331 15:50:56.820249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2333 15:50:56.910624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2334 15:50:56.911106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2336 15:50:57.004230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2337 15:50:57.004721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2339 15:50:57.099229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2340 15:50:57.099709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2342 15:50:57.190188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2343 15:50:57.190679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2345 15:50:57.295551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2346 15:50:57.296126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2348 15:50:57.389672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2349 15:50:57.390166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2351 15:50:57.481898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2352 15:50:57.482390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2354 15:50:57.575527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2355 15:50:57.576021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2357 15:50:57.670600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2358 15:50:57.671151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2360 15:50:57.759989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2362 15:50:57.763012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2363 15:50:57.857530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2364 15:50:57.858019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2366 15:50:57.954432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2367 15:50:57.954924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2369 15:50:58.050600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2370 15:50:58.051080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2372 15:50:58.149458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2373 15:50:58.149946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2375 15:50:58.245856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2376 15:50:58.246334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2378 15:50:58.342360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2379 15:50:58.342919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2381 15:50:58.436883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2382 15:50:58.437371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2384 15:50:58.531701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2385 15:50:58.532189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2387 15:50:58.628393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2388 15:50:58.628971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2390 15:50:58.724297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2391 15:50:58.724783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2393 15:50:58.824981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2394 15:50:58.825460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2396 15:50:58.923980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2397 15:50:58.924500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2399 15:50:59.022986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2400 15:50:59.023477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2402 15:50:59.119900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2403 15:50:59.120394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2405 15:50:59.216371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2406 15:50:59.216866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2408 15:50:59.313220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2409 15:50:59.313784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2411 15:50:59.410301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2412 15:50:59.410804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2414 15:50:59.505473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2415 15:50:59.505956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2417 15:50:59.602914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2418 15:50:59.603530 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2420 15:50:59.700087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2421 15:50:59.700602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2423 15:50:59.796771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2424 15:50:59.797253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2426 15:50:59.892823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2427 15:50:59.893301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2429 15:50:59.988816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2430 15:50:59.989292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2432 15:51:00.081948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2433 15:51:00.082487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2435 15:51:00.174114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2436 15:51:00.174590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2438 15:51:00.269803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2439 15:51:00.270278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2441 15:51:00.368998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2442 15:51:00.369567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2444 15:51:00.467459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2445 15:51:00.467945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2447 15:51:00.566423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2448 15:51:00.566899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2450 15:51:00.663649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2451 15:51:00.664192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2453 15:51:00.755908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2454 15:51:00.756248 + set +x
2455 15:51:00.756715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2457 15:51:00.760181 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1193677_1.6.2.4.5>
2458 15:51:00.760632 Received signal: <ENDRUN> 1_kselftest-dt 1193677_1.6.2.4.5
2459 15:51:00.760886 Ending use of test pattern.
2460 15:51:00.761130 Ending test lava.1_kselftest-dt (1193677_1.6.2.4.5), duration 94.30
2462 15:51:00.766208 <LAVA_TEST_RUNNER EXIT>
2463 15:51:00.766648 ok: lava_test_shell seems to have completed
2464 15:51:00.772526 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2465 15:51:00.773582 end: 3.1 lava-test-shell (duration 00:01:36) [common]
2466 15:51:00.773884 end: 3 lava-test-retry (duration 00:01:36) [common]
2467 15:51:00.774183 start: 4 finalize (timeout 00:05:41) [common]
2468 15:51:00.774479 start: 4.1 power-off (timeout 00:00:30) [common]
2469 15:51:00.774866 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/off'
2470 15:51:01.142660 Returned 0 in 0 seconds
2471 15:51:01.243525 end: 4.1 power-off (duration 00:00:00) [common]
2473 15:51:01.244454 start: 4.2 read-feedback (timeout 00:05:40) [common]
2474 15:51:01.245076 Listened to connection for namespace 'common' for up to 1s
2475 15:51:01.245627 Listened to connection for namespace 'common' for up to 1s
2476 15:51:02.245951 Finalising connection for namespace 'common'
2477 15:51:02.246373 Disconnecting from shell: Finalise
2478 15:51:02.246652 / #
2479 15:51:02.347257 end: 4.2 read-feedback (duration 00:00:01) [common]
2480 15:51:02.347704 end: 4 finalize (duration 00:00:02) [common]
2481 15:51:02.348061 Cleaning after the job
2482 15:51:02.348417 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1193677/tftp-deploy-x7mixwxv/ramdisk
2483 15:51:02.352120 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1193677/tftp-deploy-x7mixwxv/kernel
2484 15:51:02.355045 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1193677/tftp-deploy-x7mixwxv/dtb
2485 15:51:02.355511 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1193677/tftp-deploy-x7mixwxv/nfsrootfs
2486 15:51:02.409240 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1193677/tftp-deploy-x7mixwxv/modules
2487 15:51:02.412797 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1193677
2488 15:51:03.056437 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1193677
2489 15:51:03.056711 Job finished correctly