Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:20:07.279605 lava-dispatcher, installed at version: 2024.01
2 07:20:07.280521 start: 0 validate
3 07:20:07.281041 Start time: 2024-09-19 07:20:07.281008+00:00 (UTC)
4 07:20:07.281647 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:20:07.282217 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64be%2Frootfs.cpio.gz exists
6 07:20:07.346608 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:20:07.347245 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2BCONFIG_CPU_BIG_ENDIAN%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 07:20:08.398797 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:20:08.399469 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2BCONFIG_CPU_BIG_ENDIAN%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 07:20:13.465015 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:20:13.465488 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2BCONFIG_CPU_BIG_ENDIAN%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 07:20:14.534922 validate duration: 7.25
14 07:20:14.536584 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 07:20:14.537256 start: 1.1 download-retry (timeout 00:10:00) [common]
16 07:20:14.537887 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 07:20:14.538955 Not decompressing ramdisk as can be used compressed.
18 07:20:14.539716 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64be/rootfs.cpio.gz
19 07:20:14.540301 saving as /var/lib/lava/dispatcher/tmp/742905/tftp-deploy-dthn09wv/ramdisk/rootfs.cpio.gz
20 07:20:14.540863 total size: 8083589 (7 MB)
21 07:20:14.584755 progress 0 % (0 MB)
22 07:20:14.595711 progress 5 % (0 MB)
23 07:20:14.606231 progress 10 % (0 MB)
24 07:20:14.617407 progress 15 % (1 MB)
25 07:20:14.625967 progress 20 % (1 MB)
26 07:20:14.631371 progress 25 % (1 MB)
27 07:20:14.637141 progress 30 % (2 MB)
28 07:20:14.642417 progress 35 % (2 MB)
29 07:20:14.647871 progress 40 % (3 MB)
30 07:20:14.653702 progress 45 % (3 MB)
31 07:20:14.658989 progress 50 % (3 MB)
32 07:20:14.664364 progress 55 % (4 MB)
33 07:20:14.670025 progress 60 % (4 MB)
34 07:20:14.675417 progress 65 % (5 MB)
35 07:20:14.680840 progress 70 % (5 MB)
36 07:20:14.686623 progress 75 % (5 MB)
37 07:20:14.691925 progress 80 % (6 MB)
38 07:20:14.697236 progress 85 % (6 MB)
39 07:20:14.702883 progress 90 % (6 MB)
40 07:20:14.708188 progress 95 % (7 MB)
41 07:20:14.713067 progress 100 % (7 MB)
42 07:20:14.713707 7 MB downloaded in 0.17 s (44.60 MB/s)
43 07:20:14.714259 end: 1.1.1 http-download (duration 00:00:00) [common]
45 07:20:14.715170 end: 1.1 download-retry (duration 00:00:00) [common]
46 07:20:14.715482 start: 1.2 download-retry (timeout 00:10:00) [common]
47 07:20:14.715770 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 07:20:14.716272 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig+CONFIG_CPU_BIG_ENDIAN=y/gcc-12/kernel/Image
49 07:20:14.716534 saving as /var/lib/lava/dispatcher/tmp/742905/tftp-deploy-dthn09wv/kernel/Image
50 07:20:14.716758 total size: 44148744 (42 MB)
51 07:20:14.716981 No compression specified
52 07:20:14.754965 progress 0 % (0 MB)
53 07:20:14.782227 progress 5 % (2 MB)
54 07:20:14.809030 progress 10 % (4 MB)
55 07:20:14.836277 progress 15 % (6 MB)
56 07:20:14.862821 progress 20 % (8 MB)
57 07:20:14.889698 progress 25 % (10 MB)
58 07:20:14.916623 progress 30 % (12 MB)
59 07:20:14.943104 progress 35 % (14 MB)
60 07:20:14.969821 progress 40 % (16 MB)
61 07:20:14.996868 progress 45 % (18 MB)
62 07:20:15.023666 progress 50 % (21 MB)
63 07:20:15.050803 progress 55 % (23 MB)
64 07:20:15.077606 progress 60 % (25 MB)
65 07:20:15.104468 progress 65 % (27 MB)
66 07:20:15.131606 progress 70 % (29 MB)
67 07:20:15.158330 progress 75 % (31 MB)
68 07:20:15.185067 progress 80 % (33 MB)
69 07:20:15.212005 progress 85 % (35 MB)
70 07:20:15.238792 progress 90 % (37 MB)
71 07:20:15.265336 progress 95 % (40 MB)
72 07:20:15.292070 progress 100 % (42 MB)
73 07:20:15.292654 42 MB downloaded in 0.58 s (73.11 MB/s)
74 07:20:15.293133 end: 1.2.1 http-download (duration 00:00:01) [common]
76 07:20:15.293947 end: 1.2 download-retry (duration 00:00:01) [common]
77 07:20:15.294222 start: 1.3 download-retry (timeout 00:09:59) [common]
78 07:20:15.294485 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 07:20:15.294951 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig+CONFIG_CPU_BIG_ENDIAN=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 07:20:15.295219 saving as /var/lib/lava/dispatcher/tmp/742905/tftp-deploy-dthn09wv/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 07:20:15.295428 total size: 53209 (0 MB)
82 07:20:15.295638 No compression specified
83 07:20:15.334830 progress 61 % (0 MB)
84 07:20:15.335666 progress 100 % (0 MB)
85 07:20:15.336227 0 MB downloaded in 0.04 s (1.24 MB/s)
86 07:20:15.336695 end: 1.3.1 http-download (duration 00:00:00) [common]
88 07:20:15.337495 end: 1.3 download-retry (duration 00:00:00) [common]
89 07:20:15.337756 start: 1.4 download-retry (timeout 00:09:59) [common]
90 07:20:15.338019 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 07:20:15.338479 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig+CONFIG_CPU_BIG_ENDIAN=y/gcc-12/modules.tar.xz
92 07:20:15.338718 saving as /var/lib/lava/dispatcher/tmp/742905/tftp-deploy-dthn09wv/modules/modules.tar
93 07:20:15.338922 total size: 11465312 (10 MB)
94 07:20:15.339131 Using unxz to decompress xz
95 07:20:15.379558 progress 0 % (0 MB)
96 07:20:15.451935 progress 5 % (0 MB)
97 07:20:15.527354 progress 10 % (1 MB)
98 07:20:15.618743 progress 15 % (1 MB)
99 07:20:15.696221 progress 20 % (2 MB)
100 07:20:15.780665 progress 25 % (2 MB)
101 07:20:15.857047 progress 30 % (3 MB)
102 07:20:15.939108 progress 35 % (3 MB)
103 07:20:16.014299 progress 40 % (4 MB)
104 07:20:16.095524 progress 45 % (4 MB)
105 07:20:16.177013 progress 50 % (5 MB)
106 07:20:16.261942 progress 55 % (6 MB)
107 07:20:16.429337 progress 60 % (6 MB)
108 07:20:16.528986 progress 65 % (7 MB)
109 07:20:16.616466 progress 70 % (7 MB)
110 07:20:16.725148 progress 75 % (8 MB)
111 07:20:16.824312 progress 80 % (8 MB)
112 07:20:16.913933 progress 85 % (9 MB)
113 07:20:16.992922 progress 90 % (9 MB)
114 07:20:17.077723 progress 95 % (10 MB)
115 07:20:17.157639 progress 100 % (10 MB)
116 07:20:17.173923 10 MB downloaded in 1.83 s (5.96 MB/s)
117 07:20:17.174856 end: 1.4.1 http-download (duration 00:00:02) [common]
119 07:20:17.176695 end: 1.4 download-retry (duration 00:00:02) [common]
120 07:20:17.177273 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 07:20:17.177841 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 07:20:17.178380 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 07:20:17.178933 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 07:20:17.179971 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938
125 07:20:17.180969 makedir: /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin
126 07:20:17.181669 makedir: /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/tests
127 07:20:17.182333 makedir: /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/results
128 07:20:17.182997 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-add-keys
129 07:20:17.184041 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-add-sources
130 07:20:17.185094 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-background-process-start
131 07:20:17.186158 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-background-process-stop
132 07:20:17.187216 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-common-functions
133 07:20:17.188233 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-echo-ipv4
134 07:20:17.189206 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-install-packages
135 07:20:17.190164 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-installed-packages
136 07:20:17.191124 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-os-build
137 07:20:17.192115 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-probe-channel
138 07:20:17.193097 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-probe-ip
139 07:20:17.194059 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-target-ip
140 07:20:17.195117 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-target-mac
141 07:20:17.196134 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-target-storage
142 07:20:17.197132 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-test-case
143 07:20:17.198098 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-test-event
144 07:20:17.199072 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-test-feedback
145 07:20:17.200108 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-test-raise
146 07:20:17.201085 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-test-reference
147 07:20:17.202051 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-test-runner
148 07:20:17.203012 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-test-set
149 07:20:17.203966 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-test-shell
150 07:20:17.204990 Updating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-install-packages (oe)
151 07:20:17.206040 Updating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/bin/lava-installed-packages (oe)
152 07:20:17.206919 Creating /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/environment
153 07:20:17.207672 LAVA metadata
154 07:20:17.208228 - LAVA_JOB_ID=742905
155 07:20:17.208701 - LAVA_DISPATCHER_IP=192.168.6.2
156 07:20:17.209413 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 07:20:17.211330 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 07:20:17.211954 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 07:20:17.212448 skipped lava-vland-overlay
160 07:20:17.212937 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 07:20:17.213448 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 07:20:17.213870 skipped lava-multinode-overlay
163 07:20:17.214351 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 07:20:17.214843 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 07:20:17.215311 Loading test definitions
166 07:20:17.215851 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 07:20:17.216322 Using /lava-742905 at stage 0
168 07:20:17.218518 uuid=742905_1.5.2.4.1 testdef=None
169 07:20:17.219076 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 07:20:17.219590 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 07:20:17.221636 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 07:20:17.222439 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 07:20:17.224782 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 07:20:17.225606 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 07:20:17.227756 runner path: /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/0/tests/0_dmesg test_uuid 742905_1.5.2.4.1
178 07:20:17.228324 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 07:20:17.229095 Creating lava-test-runner.conf files
181 07:20:17.229298 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/742905/lava-overlay-n7hjy938/lava-742905/0 for stage 0
182 07:20:17.229634 - 0_dmesg
183 07:20:17.229972 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 07:20:17.230250 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 07:20:17.253787 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 07:20:17.254177 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 07:20:17.254438 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 07:20:17.254701 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 07:20:17.254961 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 07:20:18.192055 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 07:20:18.192524 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 07:20:18.192773 extracting modules file /var/lib/lava/dispatcher/tmp/742905/tftp-deploy-dthn09wv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/742905/extract-overlay-ramdisk-cjc5nqvq/ramdisk
193 07:20:19.501660 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 07:20:19.502101 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 07:20:19.502375 [common] Applying overlay /var/lib/lava/dispatcher/tmp/742905/compress-overlay-1o5rdsrd/overlay-1.5.2.5.tar.gz to ramdisk
196 07:20:19.502590 [common] Applying overlay /var/lib/lava/dispatcher/tmp/742905/compress-overlay-1o5rdsrd/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/742905/extract-overlay-ramdisk-cjc5nqvq/ramdisk
197 07:20:19.532587 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 07:20:19.532972 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 07:20:19.533239 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 07:20:19.533463 Converting downloaded kernel to a uImage
201 07:20:19.533765 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/742905/tftp-deploy-dthn09wv/kernel/Image /var/lib/lava/dispatcher/tmp/742905/tftp-deploy-dthn09wv/kernel/uImage
202 07:20:19.986679 output: Image Name:
203 07:20:19.987089 output: Created: Thu Sep 19 07:20:19 2024
204 07:20:19.987298 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 07:20:19.987505 output: Data Size: 44148744 Bytes = 43114.01 KiB = 42.10 MiB
206 07:20:19.987708 output: Load Address: 01080000
207 07:20:19.987907 output: Entry Point: 01080000
208 07:20:19.988150 output:
209 07:20:19.988487 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 07:20:19.988754 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 07:20:19.989026 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 07:20:19.989280 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 07:20:19.989537 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 07:20:19.989789 Building ramdisk /var/lib/lava/dispatcher/tmp/742905/extract-overlay-ramdisk-cjc5nqvq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/742905/extract-overlay-ramdisk-cjc5nqvq/ramdisk
215 07:20:22.330451 >> 179659 blocks
216 07:20:32.920951 Adding RAMdisk u-boot header.
217 07:20:32.921666 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/742905/extract-overlay-ramdisk-cjc5nqvq/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/742905/extract-overlay-ramdisk-cjc5nqvq/ramdisk.cpio.gz.uboot
218 07:20:33.246856 output: Image Name:
219 07:20:33.247284 output: Created: Thu Sep 19 07:20:32 2024
220 07:20:33.247709 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 07:20:33.248178 output: Data Size: 26126741 Bytes = 25514.40 KiB = 24.92 MiB
222 07:20:33.248589 output: Load Address: 00000000
223 07:20:33.248992 output: Entry Point: 00000000
224 07:20:33.249389 output:
225 07:20:33.250384 rename /var/lib/lava/dispatcher/tmp/742905/extract-overlay-ramdisk-cjc5nqvq/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/742905/tftp-deploy-dthn09wv/ramdisk/ramdisk.cpio.gz.uboot
226 07:20:33.251096 end: 1.5.8 compress-ramdisk (duration 00:00:13) [common]
227 07:20:33.251648 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
228 07:20:33.252215 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
229 07:20:33.252678 No LXC device requested
230 07:20:33.253190 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 07:20:33.253712 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
232 07:20:33.254211 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 07:20:33.254627 Checking files for TFTP limit of 4294967296 bytes.
234 07:20:33.257358 end: 1 tftp-deploy (duration 00:00:19) [common]
235 07:20:33.257949 start: 2 uboot-action (timeout 00:05:00) [common]
236 07:20:33.258484 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 07:20:33.258992 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 07:20:33.259519 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 07:20:33.260083 Using kernel file from prepare-kernel: 742905/tftp-deploy-dthn09wv/kernel/uImage
240 07:20:33.260702 substitutions:
241 07:20:33.261118 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 07:20:33.261526 - {DTB_ADDR}: 0x01070000
243 07:20:33.261926 - {DTB}: 742905/tftp-deploy-dthn09wv/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 07:20:33.262328 - {INITRD}: 742905/tftp-deploy-dthn09wv/ramdisk/ramdisk.cpio.gz.uboot
245 07:20:33.262729 - {KERNEL_ADDR}: 0x01080000
246 07:20:33.263125 - {KERNEL}: 742905/tftp-deploy-dthn09wv/kernel/uImage
247 07:20:33.263523 - {LAVA_MAC}: None
248 07:20:33.263960 - {PRESEED_CONFIG}: None
249 07:20:33.264398 - {PRESEED_LOCAL}: None
250 07:20:33.264795 - {RAMDISK_ADDR}: 0x08000000
251 07:20:33.265184 - {RAMDISK}: 742905/tftp-deploy-dthn09wv/ramdisk/ramdisk.cpio.gz.uboot
252 07:20:33.265579 - {ROOT_PART}: None
253 07:20:33.265972 - {ROOT}: None
254 07:20:33.266364 - {SERVER_IP}: 192.168.6.2
255 07:20:33.266757 - {TEE_ADDR}: 0x83000000
256 07:20:33.267143 - {TEE}: None
257 07:20:33.267530 Parsed boot commands:
258 07:20:33.267908 - setenv autoload no
259 07:20:33.268381 - setenv initrd_high 0xffffffff
260 07:20:33.268778 - setenv fdt_high 0xffffffff
261 07:20:33.269169 - dhcp
262 07:20:33.269555 - setenv serverip 192.168.6.2
263 07:20:33.269941 - tftpboot 0x01080000 742905/tftp-deploy-dthn09wv/kernel/uImage
264 07:20:33.270328 - tftpboot 0x08000000 742905/tftp-deploy-dthn09wv/ramdisk/ramdisk.cpio.gz.uboot
265 07:20:33.270713 - tftpboot 0x01070000 742905/tftp-deploy-dthn09wv/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 07:20:33.271100 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 07:20:33.271498 - bootm 0x01080000 0x08000000 0x01070000
268 07:20:33.272028 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 07:20:33.273543 start: 2.3 connect-device (timeout 00:05:00) [common]
271 07:20:33.273998 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 07:20:33.289105 Setting prompt string to ['lava-test: # ']
273 07:20:33.290632 end: 2.3 connect-device (duration 00:00:00) [common]
274 07:20:33.291251 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 07:20:33.292077 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 07:20:33.292669 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 07:20:33.293779 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 07:20:33.334022 >> OK - accepted request
279 07:20:33.336178 Returned 0 in 0 seconds
280 07:20:33.437368 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 07:20:33.439015 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 07:20:33.439568 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 07:20:33.440113 Setting prompt string to ['Hit any key to stop autoboot']
285 07:20:33.440564 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 07:20:33.442115 Trying 192.168.56.21...
287 07:20:33.442584 Connected to conserv1.
288 07:20:33.442993 Escape character is '^]'.
289 07:20:33.443397
290 07:20:33.443818 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 07:20:33.444271
292 07:20:41.501315 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 07:20:41.501738 bl2_stage_init 0x01
294 07:20:41.501972 bl2_stage_init 0x81
295 07:20:41.506895 hw id: 0x0000 - pwm id 0x01
296 07:20:41.507242 bl2_stage_init 0xc1
297 07:20:41.507469 bl2_stage_init 0x02
298 07:20:41.507694
299 07:20:41.512380 L0:00000000
300 07:20:41.512742 L1:00000703
301 07:20:41.512967 L2:00008067
302 07:20:41.513175 L3:15000000
303 07:20:41.513391 S1:00000000
304 07:20:41.517977 B2:20282000
305 07:20:41.518287 B1:a0f83180
306 07:20:41.518497
307 07:20:41.518706 TE: 71026
308 07:20:41.518911
309 07:20:41.523594 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 07:20:41.523898
311 07:20:41.529179 Board ID = 1
312 07:20:41.529471 Set cpu clk to 24M
313 07:20:41.529684 Set clk81 to 24M
314 07:20:41.537949 Use GP1_pll as DSU clk.
315 07:20:41.538275 DSU clk: 1200 Mhz
316 07:20:41.538488 CPU clk: 1200 MHz
317 07:20:41.538696 Set clk81 to 166.6M
318 07:20:41.545992 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 07:20:41.546324 board id: 1
320 07:20:41.552392 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 07:20:41.563243 fw parse done
322 07:20:41.568238 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 07:20:41.611892 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 07:20:41.622796 PIEI prepare done
325 07:20:41.623398 fastboot data load
326 07:20:41.623871 fastboot data verify
327 07:20:41.628434 verify result: 266
328 07:20:41.634040 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 07:20:41.634628 LPDDR4 probe
330 07:20:41.635102 ddr clk to 1584MHz
331 07:20:41.641571 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 07:20:41.679159
333 07:20:41.679587 dmc_version 0001
334 07:20:41.684878 Check phy result
335 07:20:41.691703 INFO : End of CA training
336 07:20:41.692067 INFO : End of initialization
337 07:20:41.697248 INFO : Training has run successfully!
338 07:20:41.697589 Check phy result
339 07:20:41.702866 INFO : End of initialization
340 07:20:41.703194 INFO : End of read enable training
341 07:20:41.706119 INFO : End of fine write leveling
342 07:20:41.711667 INFO : End of Write leveling coarse delay
343 07:20:41.717329 INFO : Training has run successfully!
344 07:20:41.717662 Check phy result
345 07:20:41.717890 INFO : End of initialization
346 07:20:41.723032 INFO : End of read dq deskew training
347 07:20:41.726245 INFO : End of MPR read delay center optimization
348 07:20:41.731845 INFO : End of write delay center optimization
349 07:20:41.737445 INFO : End of read delay center optimization
350 07:20:41.737783 INFO : End of max read latency training
351 07:20:41.743074 INFO : Training has run successfully!
352 07:20:41.743404 1D training succeed
353 07:20:41.750655 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 07:20:41.797984 Check phy result
355 07:20:41.798362 INFO : End of initialization
356 07:20:41.820334 INFO : End of 2D read delay Voltage center optimization
357 07:20:41.839652 INFO : End of 2D read delay Voltage center optimization
358 07:20:41.891695 INFO : End of 2D write delay Voltage center optimization
359 07:20:41.941674 INFO : End of 2D write delay Voltage center optimization
360 07:20:41.947216 INFO : Training has run successfully!
361 07:20:41.947669
362 07:20:41.948117 channel==0
363 07:20:41.952675 RxClkDly_Margin_A0==88 ps 9
364 07:20:41.953115 TxDqDly_Margin_A0==98 ps 10
365 07:20:41.958228 RxClkDly_Margin_A1==88 ps 9
366 07:20:41.958661 TxDqDly_Margin_A1==88 ps 9
367 07:20:41.959058 TrainedVREFDQ_A0==74
368 07:20:41.963885 TrainedVREFDQ_A1==74
369 07:20:41.964366 VrefDac_Margin_A0==23
370 07:20:41.964761 DeviceVref_Margin_A0==40
371 07:20:41.969600 VrefDac_Margin_A1==23
372 07:20:41.970031 DeviceVref_Margin_A1==40
373 07:20:41.970426
374 07:20:41.970816
375 07:20:41.971204 channel==1
376 07:20:41.975026 RxClkDly_Margin_A0==78 ps 8
377 07:20:41.975459 TxDqDly_Margin_A0==98 ps 10
378 07:20:41.980606 RxClkDly_Margin_A1==78 ps 8
379 07:20:41.981072 TxDqDly_Margin_A1==88 ps 9
380 07:20:41.986281 TrainedVREFDQ_A0==78
381 07:20:41.986723 TrainedVREFDQ_A1==75
382 07:20:41.987120 VrefDac_Margin_A0==23
383 07:20:41.991886 DeviceVref_Margin_A0==36
384 07:20:41.992369 VrefDac_Margin_A1==20
385 07:20:41.997449 DeviceVref_Margin_A1==39
386 07:20:41.997876
387 07:20:41.998274 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 07:20:41.998661
389 07:20:42.031140 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000019 00000018 00000018 00000015 00000018 00000014 00000016 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
390 07:20:42.031691 2D training succeed
391 07:20:42.036705 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 07:20:42.042301 auto size-- 65535DDR cs0 size: 2048MB
393 07:20:42.042733 DDR cs1 size: 2048MB
394 07:20:42.047851 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 07:20:42.048322 cs0 DataBus test pass
396 07:20:42.053451 cs1 DataBus test pass
397 07:20:42.053881 cs0 AddrBus test pass
398 07:20:42.054269 cs1 AddrBus test pass
399 07:20:42.054653
400 07:20:42.059080 100bdlr_step_size ps== 478
401 07:20:42.059518 result report
402 07:20:42.064638 boot times 0Enable ddr reg access
403 07:20:42.069771 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 07:20:42.083589 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 07:20:42.738666 bl2z: ptr: 05129330, size: 00001e40
406 07:20:42.745188 0.0;M3 CHK:0;cm4_sp_mode 0
407 07:20:42.745809 MVN_1=0x00000000
408 07:20:42.746266 MVN_2=0x00000000
409 07:20:42.756706 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 07:20:42.757329 OPS=0x04
411 07:20:42.757784 ring efuse init
412 07:20:42.762369 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 07:20:42.763353 [0.017310 Inits done]
414 07:20:42.764239 secure task start!
415 07:20:42.769921 high task start!
416 07:20:42.771153 low task start!
417 07:20:42.772073 run into bl31
418 07:20:42.778564 NOTICE: BL31: v1.3(release):4fc40b1
419 07:20:42.786316 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 07:20:42.786958 NOTICE: BL31: G12A normal boot!
421 07:20:42.801981 NOTICE: BL31: BL33 decompress pass
422 07:20:42.807661 ERROR: Error initializing runtime service opteed_fast
423 07:20:44.048729 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 07:20:44.049146 bl2_stage_init 0x01
425 07:20:44.049370 bl2_stage_init 0x81
426 07:20:44.054346 hw id: 0x0000 - pwm id 0x01
427 07:20:44.054647 bl2_stage_init 0xc1
428 07:20:44.059707 bl2_stage_init 0x02
429 07:20:44.060052
430 07:20:44.060282 L0:00000000
431 07:20:44.060494 L1:00000703
432 07:20:44.060697 L2:00008067
433 07:20:44.060901 L3:15000000
434 07:20:44.065270 S1:00000000
435 07:20:44.065558 B2:20282000
436 07:20:44.065777 B1:a0f83180
437 07:20:44.065987
438 07:20:44.066199 TE: 70304
439 07:20:44.066411
440 07:20:44.070854 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 07:20:44.071142
442 07:20:44.076440 Board ID = 1
443 07:20:44.076727 Set cpu clk to 24M
444 07:20:44.076945 Set clk81 to 24M
445 07:20:44.079791 Use GP1_pll as DSU clk.
446 07:20:44.080080 DSU clk: 1200 Mhz
447 07:20:44.085300 CPU clk: 1200 MHz
448 07:20:44.085582 Set clk81 to 166.6M
449 07:20:44.090941 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 07:20:44.091227 board id: 1
451 07:20:44.099752 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 07:20:44.111608 fw parse done
453 07:20:44.117047 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 07:20:44.159865 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 07:20:44.171896 PIEI prepare done
456 07:20:44.172254 fastboot data load
457 07:20:44.172476 fastboot data verify
458 07:20:44.177412 verify result: 266
459 07:20:44.183057 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 07:20:44.183345 LPDDR4 probe
461 07:20:44.183553 ddr clk to 1584MHz
462 07:20:45.550155 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 07:20:45.550810 bl2_stage_init 0x01
464 07:20:45.551258 bl2_stage_init 0x81
465 07:20:45.555608 hw id: 0x0000 - pwm id 0x01
466 07:20:45.556165 bl2_stage_init 0xc1
467 07:20:45.561134 bl2_stage_init 0x02
468 07:20:45.561627
469 07:20:45.562042 L0:00000000
470 07:20:45.562471 L1:00000703
471 07:20:45.562902 L2:00008067
472 07:20:45.563322 L3:15000000
473 07:20:45.567056 S1:00000000
474 07:20:45.567572 B2:20282000
475 07:20:45.568043 B1:a0f83180
476 07:20:45.568481
477 07:20:45.568901 TE: 71869
478 07:20:45.569310
479 07:20:45.572651 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 07:20:45.573130
481 07:20:45.578245 Board ID = 1
482 07:20:45.578708 Set cpu clk to 24M
483 07:20:45.579119 Set clk81 to 24M
484 07:20:45.581621 Use GP1_pll as DSU clk.
485 07:20:45.582194 DSU clk: 1200 Mhz
486 07:20:45.587173 CPU clk: 1200 MHz
487 07:20:45.587749 Set clk81 to 166.6M
488 07:20:45.592764 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 07:20:45.593263 board id: 1
490 07:20:45.601000 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 07:20:45.612574 fw parse done
492 07:20:45.617556 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 07:20:45.660350 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 07:20:45.672244 PIEI prepare done
495 07:20:45.672808 fastboot data load
496 07:20:45.673424 fastboot data verify
497 07:20:45.677704 verify result: 266
498 07:20:45.683372 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 07:20:45.683883 LPDDR4 probe
500 07:20:45.684463 ddr clk to 1584MHz
501 07:20:45.690393 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 07:20:45.727840
503 07:20:45.728421 dmc_version 0001
504 07:20:45.734476 Check phy result
505 07:20:45.741183 INFO : End of CA training
506 07:20:45.741702 INFO : End of initialization
507 07:20:45.746786 INFO : Training has run successfully!
508 07:20:45.747279 Check phy result
509 07:20:45.752344 INFO : End of initialization
510 07:20:45.752855 INFO : End of read enable training
511 07:20:45.757965 INFO : End of fine write leveling
512 07:20:45.763588 INFO : End of Write leveling coarse delay
513 07:20:45.764152 INFO : Training has run successfully!
514 07:20:45.764587 Check phy result
515 07:20:45.769190 INFO : End of initialization
516 07:20:45.769649 INFO : End of read dq deskew training
517 07:20:45.774792 INFO : End of MPR read delay center optimization
518 07:20:45.780396 INFO : End of write delay center optimization
519 07:20:45.785976 INFO : End of read delay center optimization
520 07:20:45.786467 INFO : End of max read latency training
521 07:20:45.791644 INFO : Training has run successfully!
522 07:20:45.792152 1D training succeed
523 07:20:45.799765 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 07:20:45.847540 Check phy result
525 07:20:45.848120 INFO : End of initialization
526 07:20:45.869748 INFO : End of 2D read delay Voltage center optimization
527 07:20:45.888916 INFO : End of 2D read delay Voltage center optimization
528 07:20:45.940822 INFO : End of 2D write delay Voltage center optimization
529 07:20:45.990892 INFO : End of 2D write delay Voltage center optimization
530 07:20:45.996430 INFO : Training has run successfully!
531 07:20:45.996884
532 07:20:45.997288 channel==0
533 07:20:46.002053 RxClkDly_Margin_A0==78 ps 8
534 07:20:46.002507 TxDqDly_Margin_A0==98 ps 10
535 07:20:46.007588 RxClkDly_Margin_A1==88 ps 9
536 07:20:46.008062 TxDqDly_Margin_A1==88 ps 9
537 07:20:46.008474 TrainedVREFDQ_A0==76
538 07:20:46.013196 TrainedVREFDQ_A1==74
539 07:20:46.013629 VrefDac_Margin_A0==23
540 07:20:46.014027 DeviceVref_Margin_A0==38
541 07:20:46.018853 VrefDac_Margin_A1==22
542 07:20:46.019286 DeviceVref_Margin_A1==40
543 07:20:46.019685
544 07:20:46.020115
545 07:20:46.020517 channel==1
546 07:20:46.024435 RxClkDly_Margin_A0==78 ps 8
547 07:20:46.024911 TxDqDly_Margin_A0==98 ps 10
548 07:20:46.030053 RxClkDly_Margin_A1==78 ps 8
549 07:20:46.030526 TxDqDly_Margin_A1==88 ps 9
550 07:20:46.035676 TrainedVREFDQ_A0==78
551 07:20:46.036196 TrainedVREFDQ_A1==75
552 07:20:46.036605 VrefDac_Margin_A0==22
553 07:20:46.041214 DeviceVref_Margin_A0==36
554 07:20:46.041687 VrefDac_Margin_A1==20
555 07:20:46.046826 DeviceVref_Margin_A1==39
556 07:20:46.047279
557 07:20:46.047682 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 07:20:46.048107
559 07:20:46.080435 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000019 00000017 00000019 00000015 00000018 00000015 00000015 00000017 00000019 0000001a 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
560 07:20:46.080971 2D training succeed
561 07:20:46.086082 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 07:20:46.091658 auto size-- 65535DDR cs0 size: 2048MB
563 07:20:46.092158 DDR cs1 size: 2048MB
564 07:20:46.097241 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 07:20:46.097707 cs0 DataBus test pass
566 07:20:46.102818 cs1 DataBus test pass
567 07:20:46.103397 cs0 AddrBus test pass
568 07:20:46.103817 cs1 AddrBus test pass
569 07:20:46.104400
570 07:20:46.108414 100bdlr_step_size ps== 478
571 07:20:46.108921 result report
572 07:20:46.114038 boot times 0Enable ddr reg access
573 07:20:46.118351 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 07:20:46.132120 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 07:20:46.788125 bl2z: ptr: 05129330, size: 00001e40
576 07:20:46.795819 0.0;M3 CHK:0;cm4_sp_mode 0
577 07:20:46.796664 MVN_1=0x00000000
578 07:20:46.797327 MVN_2=0x00000000
579 07:20:46.807276 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 07:20:46.807765 OPS=0x04
581 07:20:46.808207 ring efuse init
582 07:20:46.812900 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 07:20:46.813362 [0.017310 Inits done]
584 07:20:46.813761 secure task start!
585 07:20:46.820266 high task start!
586 07:20:46.821096 low task start!
587 07:20:46.821735 run into bl31
588 07:20:46.828883 NOTICE: BL31: v1.3(release):4fc40b1
589 07:20:46.836804 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 07:20:46.837559 NOTICE: BL31: G12A normal boot!
591 07:20:46.852275 NOTICE: BL31: BL33 decompress pass
592 07:20:46.857847 ERROR: Error initializing runtime service opteed_fast
593 07:20:48.103215 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 07:20:48.103813 bl2_stage_init 0x01
595 07:20:48.104271 bl2_stage_init 0x81
596 07:20:48.108786 hw id: 0x0000 - pwm id 0x01
597 07:20:48.109225 bl2_stage_init 0xc1
598 07:20:48.109625 bl2_stage_init 0x02
599 07:20:48.110017
600 07:20:48.114389 L0:00000000
601 07:20:48.114933 L1:00000703
602 07:20:48.115341 L2:00008067
603 07:20:48.115730 L3:15000000
604 07:20:48.116177 S1:00000000
605 07:20:48.120084 B2:20282000
606 07:20:48.120608 B1:a0f83180
607 07:20:48.121040
608 07:20:48.121437 TE: 72761
609 07:20:48.121826
610 07:20:48.125567 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 07:20:48.126053
612 07:20:48.131147 Board ID = 1
613 07:20:48.131616 Set cpu clk to 24M
614 07:20:48.132046 Set clk81 to 24M
615 07:20:48.136805 Use GP1_pll as DSU clk.
616 07:20:48.137282 DSU clk: 1200 Mhz
617 07:20:48.139025 CPU clk: 1200 MHz
618 07:20:48.139789 Set clk81 to 166.6M
619 07:20:48.148127 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 07:20:48.148905 board id: 1
621 07:20:48.154407 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 07:20:48.165080 fw parse done
623 07:20:48.170989 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 07:20:48.213857 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 07:20:48.224585 PIEI prepare done
626 07:20:48.225081 fastboot data load
627 07:20:48.225488 fastboot data verify
628 07:20:48.230228 verify result: 266
629 07:20:48.235885 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 07:20:48.236383 LPDDR4 probe
631 07:20:48.236784 ddr clk to 1584MHz
632 07:20:48.243794 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 07:20:48.281085
634 07:20:48.281628 dmc_version 0001
635 07:20:48.287719 Check phy result
636 07:20:48.293631 INFO : End of CA training
637 07:20:48.294098 INFO : End of initialization
638 07:20:48.299222 INFO : Training has run successfully!
639 07:20:48.299697 Check phy result
640 07:20:48.304981 INFO : End of initialization
641 07:20:48.305445 INFO : End of read enable training
642 07:20:48.310425 INFO : End of fine write leveling
643 07:20:48.316082 INFO : End of Write leveling coarse delay
644 07:20:48.316534 INFO : Training has run successfully!
645 07:20:48.316930 Check phy result
646 07:20:48.321647 INFO : End of initialization
647 07:20:48.322107 INFO : End of read dq deskew training
648 07:20:48.327284 INFO : End of MPR read delay center optimization
649 07:20:48.332946 INFO : End of write delay center optimization
650 07:20:48.338430 INFO : End of read delay center optimization
651 07:20:48.338895 INFO : End of max read latency training
652 07:20:48.344078 INFO : Training has run successfully!
653 07:20:48.344531 1D training succeed
654 07:20:48.353324 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 07:20:48.400933 Check phy result
656 07:20:48.401567 INFO : End of initialization
657 07:20:48.423364 INFO : End of 2D read delay Voltage center optimization
658 07:20:48.442399 INFO : End of 2D read delay Voltage center optimization
659 07:20:48.494436 INFO : End of 2D write delay Voltage center optimization
660 07:20:48.543489 INFO : End of 2D write delay Voltage center optimization
661 07:20:48.549034 INFO : Training has run successfully!
662 07:20:48.549531
663 07:20:48.549956 channel==0
664 07:20:48.554607 RxClkDly_Margin_A0==78 ps 8
665 07:20:48.555061 TxDqDly_Margin_A0==98 ps 10
666 07:20:48.560264 RxClkDly_Margin_A1==88 ps 9
667 07:20:48.560725 TxDqDly_Margin_A1==98 ps 10
668 07:20:48.561125 TrainedVREFDQ_A0==74
669 07:20:48.565808 TrainedVREFDQ_A1==75
670 07:20:48.566276 VrefDac_Margin_A0==22
671 07:20:48.566679 DeviceVref_Margin_A0==40
672 07:20:48.571514 VrefDac_Margin_A1==23
673 07:20:48.572003 DeviceVref_Margin_A1==39
674 07:20:48.572412
675 07:20:48.572831
676 07:20:48.577017 channel==1
677 07:20:48.577481 RxClkDly_Margin_A0==88 ps 9
678 07:20:48.577881 TxDqDly_Margin_A0==98 ps 10
679 07:20:48.582644 RxClkDly_Margin_A1==88 ps 9
680 07:20:48.583133 TxDqDly_Margin_A1==78 ps 8
681 07:20:48.588222 TrainedVREFDQ_A0==78
682 07:20:48.588696 TrainedVREFDQ_A1==75
683 07:20:48.589091 VrefDac_Margin_A0==22
684 07:20:48.593773 DeviceVref_Margin_A0==36
685 07:20:48.594240 VrefDac_Margin_A1==21
686 07:20:48.599378 DeviceVref_Margin_A1==39
687 07:20:48.599840
688 07:20:48.600294 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 07:20:48.600707
690 07:20:48.633043 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000062
691 07:20:48.633585 2D training succeed
692 07:20:48.638622 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 07:20:48.644206 auto size-- 65535DDR cs0 size: 2048MB
694 07:20:48.644673 DDR cs1 size: 2048MB
695 07:20:48.650243 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 07:20:48.651372 cs0 DataBus test pass
697 07:20:48.655387 cs1 DataBus test pass
698 07:20:48.655875 cs0 AddrBus test pass
699 07:20:48.656331 cs1 AddrBus test pass
700 07:20:48.656750
701 07:20:48.661000 100bdlr_step_size ps== 478
702 07:20:48.661480 result report
703 07:20:48.666556 boot times 0Enable ddr reg access
704 07:20:48.671824 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 07:20:48.685648 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 07:20:49.342203 bl2z: ptr: 05129330, size: 00001e40
707 07:20:49.349227 0.0;M3 CHK:0;cm4_sp_mode 0
708 07:20:49.349690 MVN_1=0x00000000
709 07:20:49.350085 MVN_2=0x00000000
710 07:20:49.360736 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 07:20:49.361218 OPS=0x04
712 07:20:49.361615 ring efuse init
713 07:20:49.366363 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 07:20:49.366821 [0.017310 Inits done]
715 07:20:49.367210 secure task start!
716 07:20:49.373797 high task start!
717 07:20:49.374259 low task start!
718 07:20:49.374645 run into bl31
719 07:20:49.382421 NOTICE: BL31: v1.3(release):4fc40b1
720 07:20:49.390208 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 07:20:49.390665 NOTICE: BL31: G12A normal boot!
722 07:20:49.405661 NOTICE: BL31: BL33 decompress pass
723 07:20:49.411365 ERROR: Error initializing runtime service opteed_fast
724 07:20:50.207015
725 07:20:50.207625
726 07:20:50.212239 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 07:20:50.212707
728 07:20:50.215701 Model: Libre Computer AML-S905D3-CC Solitude
729 07:20:50.362845 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 07:20:50.378316 DRAM: 2 GiB (effective 3.8 GiB)
731 07:20:50.479204 Core: 406 devices, 33 uclasses, devicetree: separate
732 07:20:50.484997 WDT: Not starting watchdog@f0d0
733 07:20:50.510120 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 07:20:50.522378 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 07:20:50.527378 ** Bad device specification mmc 0 **
736 07:20:50.537300 Card did not respond to voltage select! : -110
737 07:20:50.545157 ** Bad device specification mmc 0 **
738 07:20:50.545766 Couldn't find partition mmc 0
739 07:20:50.553288 Card did not respond to voltage select! : -110
740 07:20:50.558754 ** Bad device specification mmc 0 **
741 07:20:50.559263 Couldn't find partition mmc 0
742 07:20:50.563788 Error: could not access storage.
743 07:20:50.860324 Net: eth0: ethernet@ff3f0000
744 07:20:50.860920 starting USB...
745 07:20:51.104921 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 07:20:51.105322 Starting the controller
747 07:20:51.112010 USB XHCI 1.10
748 07:20:52.668459 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 07:20:52.676815 scanning usb for storage devices... 0 Storage Device(s) found
751 07:20:52.728491 Hit any key to stop autoboot: 1
752 07:20:52.729508 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 07:20:52.730249 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 07:20:52.730770 Setting prompt string to ['=>']
755 07:20:52.731253 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 07:20:52.742825 0
757 07:20:52.743884 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 07:20:52.845289 => setenv autoload no
760 07:20:52.846088 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
761 07:20:52.850867 setenv autoload no
763 07:20:52.952357 => setenv initrd_high 0xffffffff
764 07:20:52.953118 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
765 07:20:52.957809 setenv initrd_high 0xffffffff
767 07:20:53.059311 => setenv fdt_high 0xffffffff
768 07:20:53.060174 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
769 07:20:53.064924 setenv fdt_high 0xffffffff
771 07:20:53.166529 => dhcp
772 07:20:53.167344 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
773 07:20:53.171880 dhcp
774 07:20:53.777081 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
775 07:20:53.777703 Speed: 1000, full duplex
776 07:20:53.778110 BOOTP broadcast 1
777 07:20:54.025672 BOOTP broadcast 2
778 07:20:54.526864 BOOTP broadcast 3
779 07:20:55.527543 BOOTP broadcast 4
780 07:20:57.527547 BOOTP broadcast 5
781 07:20:57.539340 DHCP client bound to address 192.168.6.12 (3762 ms)
783 07:20:57.640812 => setenv serverip 192.168.6.2
784 07:20:57.641749 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
785 07:20:57.645980 setenv serverip 192.168.6.2
787 07:20:57.747425 => tftpboot 0x01080000 742905/tftp-deploy-dthn09wv/kernel/uImage
788 07:20:57.748350 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
789 07:20:57.754698 tftpboot 0x01080000 742905/tftp-deploy-dthn09wv/kernel/uImage
790 07:20:57.755172 Speed: 1000, full duplex
791 07:20:57.755585 Using ethernet@ff3f0000 device
792 07:20:57.760230 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
793 07:20:57.765725 Filename '742905/tftp-deploy-dthn09wv/kernel/uImage'.
794 07:20:57.769644 Load address: 0x1080000
795 07:21:01.613529 Loading: *################################################## 42.1 MiB
796 07:21:01.614154 10.9 MiB/s
797 07:21:01.614588 done
798 07:21:01.617863 Bytes transferred = 44148808 (2a1a848 hex)
800 07:21:01.719393 => tftpboot 0x08000000 742905/tftp-deploy-dthn09wv/ramdisk/ramdisk.cpio.gz.uboot
801 07:21:01.719943 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
802 07:21:01.726725 tftpboot 0x08000000 742905/tftp-deploy-dthn09wv/ramdisk/ramdisk.cpio.gz.uboot
803 07:21:01.727254 Speed: 1000, full duplex
804 07:21:01.727680 Using ethernet@ff3f0000 device
805 07:21:01.732280 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
806 07:21:01.741051 Filename '742905/tftp-deploy-dthn09wv/ramdisk/ramdisk.cpio.gz.uboot'.
807 07:21:01.741387 Load address: 0x8000000
808 07:21:04.639897 Loading: *########################### UDP wrong checksum 000000ff 0000279d
809 07:21:04.642913 UDP wrong checksum 000000ff 0000ab8f
810 07:21:09.120883 T ###################### UDP wrong checksum 00000005 000095bb
811 07:21:14.121798 T UDP wrong checksum 00000005 000095bb
812 07:21:24.123633 T T UDP wrong checksum 00000005 000095bb
813 07:21:36.415533 T T UDP wrong checksum 000000ff 00006b5c
814 07:21:36.445501 UDP wrong checksum 000000ff 0000f24e
815 07:21:44.127896 T T UDP wrong checksum 00000005 000095bb
816 07:21:59.131504 T T
817 07:21:59.131904 Retry count exceeded; starting again
819 07:21:59.132819 end: 2.4.3 bootloader-commands (duration 00:01:06) [common]
822 07:21:59.133764 end: 2.4 uboot-commands (duration 00:01:26) [common]
824 07:21:59.134513 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
826 07:21:59.135081 end: 2 uboot-action (duration 00:01:26) [common]
828 07:21:59.135912 Cleaning after the job
829 07:21:59.136248 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742905/tftp-deploy-dthn09wv/ramdisk
830 07:21:59.137079 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742905/tftp-deploy-dthn09wv/kernel
831 07:21:59.142365 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742905/tftp-deploy-dthn09wv/dtb
832 07:21:59.143055 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742905/tftp-deploy-dthn09wv/modules
833 07:21:59.146225 start: 4.1 power-off (timeout 00:00:30) [common]
834 07:21:59.146786 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
835 07:21:59.184169 >> OK - accepted request
836 07:21:59.186260 Returned 0 in 0 seconds
837 07:21:59.287004 end: 4.1 power-off (duration 00:00:00) [common]
839 07:21:59.288060 start: 4.2 read-feedback (timeout 00:10:00) [common]
840 07:21:59.288765 Listened to connection for namespace 'common' for up to 1s
841 07:22:00.289741 Finalising connection for namespace 'common'
842 07:22:00.290458 Disconnecting from shell: Finalise
843 07:22:00.290977 =>
844 07:22:00.391890 end: 4.2 read-feedback (duration 00:00:01) [common]
845 07:22:00.392531 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/742905
846 07:22:00.663660 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/742905
847 07:22:00.664627 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.