Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:12:27.214471 lava-dispatcher, installed at version: 2024.01
2 07:12:27.215290 start: 0 validate
3 07:12:27.215769 Start time: 2024-09-19 07:12:27.215740+00:00 (UTC)
4 07:12:27.216344 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:12:27.216916 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 07:12:27.254235 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:12:27.254808 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 07:12:27.288131 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:12:27.288772 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 07:12:27.319436 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:12:27.319949 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 07:12:27.353779 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 07:12:27.354265 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
14 07:12:27.395191 validate duration: 0.18
16 07:12:27.396106 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 07:12:27.396457 start: 1.1 download-retry (timeout 00:10:00) [common]
18 07:12:27.396792 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 07:12:27.397480 Not decompressing ramdisk as can be used compressed.
20 07:12:27.397974 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 07:12:27.398269 saving as /var/lib/lava/dispatcher/tmp/742687/tftp-deploy-ut2njev1/ramdisk/initrd.cpio.gz
22 07:12:27.398554 total size: 5628182 (5 MB)
23 07:12:27.438326 progress 0 % (0 MB)
24 07:12:27.442542 progress 5 % (0 MB)
25 07:12:27.447002 progress 10 % (0 MB)
26 07:12:27.450924 progress 15 % (0 MB)
27 07:12:27.455238 progress 20 % (1 MB)
28 07:12:27.459105 progress 25 % (1 MB)
29 07:12:27.463433 progress 30 % (1 MB)
30 07:12:27.467762 progress 35 % (1 MB)
31 07:12:27.471637 progress 40 % (2 MB)
32 07:12:27.477914 progress 45 % (2 MB)
33 07:12:27.481797 progress 50 % (2 MB)
34 07:12:27.485997 progress 55 % (2 MB)
35 07:12:27.490190 progress 60 % (3 MB)
36 07:12:27.493946 progress 65 % (3 MB)
37 07:12:27.498111 progress 70 % (3 MB)
38 07:12:27.501812 progress 75 % (4 MB)
39 07:12:27.505955 progress 80 % (4 MB)
40 07:12:27.509832 progress 85 % (4 MB)
41 07:12:27.514044 progress 90 % (4 MB)
42 07:12:27.518166 progress 95 % (5 MB)
43 07:12:27.521563 progress 100 % (5 MB)
44 07:12:27.522262 5 MB downloaded in 0.12 s (43.39 MB/s)
45 07:12:27.522836 end: 1.1.1 http-download (duration 00:00:00) [common]
47 07:12:27.523739 end: 1.1 download-retry (duration 00:00:00) [common]
48 07:12:27.524078 start: 1.2 download-retry (timeout 00:10:00) [common]
49 07:12:27.524370 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 07:12:27.524869 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/kernel/Image
51 07:12:27.525150 saving as /var/lib/lava/dispatcher/tmp/742687/tftp-deploy-ut2njev1/kernel/Image
52 07:12:27.525364 total size: 45724160 (43 MB)
53 07:12:27.525577 No compression specified
54 07:12:27.563858 progress 0 % (0 MB)
55 07:12:27.594564 progress 5 % (2 MB)
56 07:12:27.625042 progress 10 % (4 MB)
57 07:12:27.655376 progress 15 % (6 MB)
58 07:12:27.686035 progress 20 % (8 MB)
59 07:12:27.715322 progress 25 % (10 MB)
60 07:12:27.744601 progress 30 % (13 MB)
61 07:12:27.773516 progress 35 % (15 MB)
62 07:12:27.802511 progress 40 % (17 MB)
63 07:12:27.831086 progress 45 % (19 MB)
64 07:12:27.860471 progress 50 % (21 MB)
65 07:12:27.890505 progress 55 % (24 MB)
66 07:12:27.920945 progress 60 % (26 MB)
67 07:12:27.949420 progress 65 % (28 MB)
68 07:12:27.977464 progress 70 % (30 MB)
69 07:12:28.006205 progress 75 % (32 MB)
70 07:12:28.034673 progress 80 % (34 MB)
71 07:12:28.062917 progress 85 % (37 MB)
72 07:12:28.091296 progress 90 % (39 MB)
73 07:12:28.119828 progress 95 % (41 MB)
74 07:12:28.147731 progress 100 % (43 MB)
75 07:12:28.148383 43 MB downloaded in 0.62 s (69.99 MB/s)
76 07:12:28.148889 end: 1.2.1 http-download (duration 00:00:01) [common]
78 07:12:28.149755 end: 1.2 download-retry (duration 00:00:01) [common]
79 07:12:28.150057 start: 1.3 download-retry (timeout 00:09:59) [common]
80 07:12:28.150345 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 07:12:28.151011 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 07:12:28.151319 saving as /var/lib/lava/dispatcher/tmp/742687/tftp-deploy-ut2njev1/dtb/meson-g12b-a311d-libretech-cc.dtb
83 07:12:28.151544 total size: 54703 (0 MB)
84 07:12:28.151767 No compression specified
85 07:12:28.194250 progress 59 % (0 MB)
86 07:12:28.195103 progress 100 % (0 MB)
87 07:12:28.195675 0 MB downloaded in 0.04 s (1.18 MB/s)
88 07:12:28.196203 end: 1.3.1 http-download (duration 00:00:00) [common]
90 07:12:28.197076 end: 1.3 download-retry (duration 00:00:00) [common]
91 07:12:28.197361 start: 1.4 download-retry (timeout 00:09:59) [common]
92 07:12:28.197644 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 07:12:28.198128 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 07:12:28.198388 saving as /var/lib/lava/dispatcher/tmp/742687/tftp-deploy-ut2njev1/nfsrootfs/full.rootfs.tar
95 07:12:28.198607 total size: 107552908 (102 MB)
96 07:12:28.198830 Using unxz to decompress xz
97 07:12:28.236974 progress 0 % (0 MB)
98 07:12:28.886711 progress 5 % (5 MB)
99 07:12:29.614359 progress 10 % (10 MB)
100 07:12:30.338686 progress 15 % (15 MB)
101 07:12:31.096728 progress 20 % (20 MB)
102 07:12:31.667438 progress 25 % (25 MB)
103 07:12:32.291959 progress 30 % (30 MB)
104 07:12:33.032341 progress 35 % (35 MB)
105 07:12:33.383778 progress 40 % (41 MB)
106 07:12:33.813564 progress 45 % (46 MB)
107 07:12:34.507426 progress 50 % (51 MB)
108 07:12:35.199223 progress 55 % (56 MB)
109 07:12:35.959330 progress 60 % (61 MB)
110 07:12:36.719009 progress 65 % (66 MB)
111 07:12:37.449436 progress 70 % (71 MB)
112 07:12:38.217539 progress 75 % (76 MB)
113 07:12:38.896854 progress 80 % (82 MB)
114 07:12:39.607994 progress 85 % (87 MB)
115 07:12:40.348191 progress 90 % (92 MB)
116 07:12:41.072943 progress 95 % (97 MB)
117 07:12:41.821714 progress 100 % (102 MB)
118 07:12:41.834625 102 MB downloaded in 13.64 s (7.52 MB/s)
119 07:12:41.835332 end: 1.4.1 http-download (duration 00:00:14) [common]
121 07:12:41.837072 end: 1.4 download-retry (duration 00:00:14) [common]
122 07:12:41.837610 start: 1.5 download-retry (timeout 00:09:46) [common]
123 07:12:41.838137 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 07:12:41.838937 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/modules.tar.xz
125 07:12:41.839396 saving as /var/lib/lava/dispatcher/tmp/742687/tftp-deploy-ut2njev1/modules/modules.tar
126 07:12:41.839812 total size: 11617756 (11 MB)
127 07:12:41.840276 Using unxz to decompress xz
128 07:12:41.884907 progress 0 % (0 MB)
129 07:12:41.957151 progress 5 % (0 MB)
130 07:12:42.037549 progress 10 % (1 MB)
131 07:12:42.125635 progress 15 % (1 MB)
132 07:12:42.202303 progress 20 % (2 MB)
133 07:12:42.285297 progress 25 % (2 MB)
134 07:12:42.365236 progress 30 % (3 MB)
135 07:12:42.445048 progress 35 % (3 MB)
136 07:12:42.518847 progress 40 % (4 MB)
137 07:12:42.595489 progress 45 % (5 MB)
138 07:12:42.672865 progress 50 % (5 MB)
139 07:12:42.748475 progress 55 % (6 MB)
140 07:12:42.828532 progress 60 % (6 MB)
141 07:12:42.914213 progress 65 % (7 MB)
142 07:12:42.996074 progress 70 % (7 MB)
143 07:12:43.087757 progress 75 % (8 MB)
144 07:12:43.182799 progress 80 % (8 MB)
145 07:12:43.263711 progress 85 % (9 MB)
146 07:12:43.339862 progress 90 % (10 MB)
147 07:12:43.412204 progress 95 % (10 MB)
148 07:12:43.488041 progress 100 % (11 MB)
149 07:12:43.501545 11 MB downloaded in 1.66 s (6.67 MB/s)
150 07:12:43.502432 end: 1.5.1 http-download (duration 00:00:02) [common]
152 07:12:43.504118 end: 1.5 download-retry (duration 00:00:02) [common]
153 07:12:43.504688 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 07:12:43.505236 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 07:12:53.436018 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/742687/extract-nfsrootfs-mowu3ssu
156 07:12:53.436621 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 07:12:53.436917 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 07:12:53.437549 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a
159 07:12:53.438039 makedir: /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin
160 07:12:53.438400 makedir: /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/tests
161 07:12:53.438728 makedir: /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/results
162 07:12:53.439066 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-add-keys
163 07:12:53.439603 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-add-sources
164 07:12:53.440148 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-background-process-start
165 07:12:53.440745 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-background-process-stop
166 07:12:53.441301 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-common-functions
167 07:12:53.441845 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-echo-ipv4
168 07:12:53.442354 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-install-packages
169 07:12:53.442858 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-installed-packages
170 07:12:53.443357 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-os-build
171 07:12:53.443886 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-probe-channel
172 07:12:53.444432 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-probe-ip
173 07:12:53.444933 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-target-ip
174 07:12:53.445454 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-target-mac
175 07:12:53.446037 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-target-storage
176 07:12:53.446545 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-test-case
177 07:12:53.447105 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-test-event
178 07:12:53.447604 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-test-feedback
179 07:12:53.448119 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-test-raise
180 07:12:53.448621 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-test-reference
181 07:12:53.449138 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-test-runner
182 07:12:53.449640 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-test-set
183 07:12:53.450144 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-test-shell
184 07:12:53.450734 Updating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-install-packages (oe)
185 07:12:53.451288 Updating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/bin/lava-installed-packages (oe)
186 07:12:53.451740 Creating /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/environment
187 07:12:53.452144 LAVA metadata
188 07:12:53.452415 - LAVA_JOB_ID=742687
189 07:12:53.452633 - LAVA_DISPATCHER_IP=192.168.6.2
190 07:12:53.452995 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 07:12:53.453966 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 07:12:53.454280 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 07:12:53.454494 skipped lava-vland-overlay
194 07:12:53.454738 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 07:12:53.454998 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 07:12:53.455221 skipped lava-multinode-overlay
197 07:12:53.455467 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 07:12:53.455726 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 07:12:53.455976 Loading test definitions
200 07:12:53.456292 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 07:12:53.456520 Using /lava-742687 at stage 0
202 07:12:53.457783 uuid=742687_1.6.2.4.1 testdef=None
203 07:12:53.458092 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 07:12:53.458359 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 07:12:53.460275 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 07:12:53.461074 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 07:12:53.463360 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 07:12:53.464217 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 07:12:53.466421 runner path: /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/0/tests/0_dmesg test_uuid 742687_1.6.2.4.1
212 07:12:53.466978 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 07:12:53.467745 Creating lava-test-runner.conf files
215 07:12:53.467948 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/742687/lava-overlay-yqml9_1a/lava-742687/0 for stage 0
216 07:12:53.468378 - 0_dmesg
217 07:12:53.468732 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 07:12:53.469009 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 07:12:53.490742 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 07:12:53.491126 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 07:12:53.491389 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 07:12:53.491660 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 07:12:53.491925 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 07:12:54.156021 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 07:12:54.156491 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 07:12:54.156764 extracting modules file /var/lib/lava/dispatcher/tmp/742687/tftp-deploy-ut2njev1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/742687/extract-nfsrootfs-mowu3ssu
227 07:12:55.553954 extracting modules file /var/lib/lava/dispatcher/tmp/742687/tftp-deploy-ut2njev1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/742687/extract-overlay-ramdisk-vc0h52hx/ramdisk
228 07:12:57.130406 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 07:12:57.130896 start: 1.6.5 apply-overlay-tftp (timeout 00:09:30) [common]
230 07:12:57.131187 [common] Applying overlay to NFS
231 07:12:57.131407 [common] Applying overlay /var/lib/lava/dispatcher/tmp/742687/compress-overlay-ze1_9tbs/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/742687/extract-nfsrootfs-mowu3ssu
232 07:12:57.170959 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 07:12:57.171418 start: 1.6.6 prepare-kernel (timeout 00:09:30) [common]
234 07:12:57.171698 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:30) [common]
235 07:12:57.171933 Converting downloaded kernel to a uImage
236 07:12:57.172293 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/742687/tftp-deploy-ut2njev1/kernel/Image /var/lib/lava/dispatcher/tmp/742687/tftp-deploy-ut2njev1/kernel/uImage
237 07:12:57.643129 output: Image Name:
238 07:12:57.643554 output: Created: Thu Sep 19 07:12:57 2024
239 07:12:57.643767 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 07:12:57.643971 output: Data Size: 45724160 Bytes = 44652.50 KiB = 43.61 MiB
241 07:12:57.644213 output: Load Address: 01080000
242 07:12:57.644415 output: Entry Point: 01080000
243 07:12:57.644614 output:
244 07:12:57.644949 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 07:12:57.645219 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 07:12:57.645493 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 07:12:57.645749 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 07:12:57.646011 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 07:12:57.646270 Building ramdisk /var/lib/lava/dispatcher/tmp/742687/extract-overlay-ramdisk-vc0h52hx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/742687/extract-overlay-ramdisk-vc0h52hx/ramdisk
250 07:12:59.873276 >> 166871 blocks
251 07:13:07.593737 Adding RAMdisk u-boot header.
252 07:13:07.594183 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/742687/extract-overlay-ramdisk-vc0h52hx/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/742687/extract-overlay-ramdisk-vc0h52hx/ramdisk.cpio.gz.uboot
253 07:13:07.844137 output: Image Name:
254 07:13:07.844561 output: Created: Thu Sep 19 07:13:07 2024
255 07:13:07.844777 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 07:13:07.844982 output: Data Size: 23436625 Bytes = 22887.33 KiB = 22.35 MiB
257 07:13:07.845185 output: Load Address: 00000000
258 07:13:07.845384 output: Entry Point: 00000000
259 07:13:07.845583 output:
260 07:13:07.846239 rename /var/lib/lava/dispatcher/tmp/742687/extract-overlay-ramdisk-vc0h52hx/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/742687/tftp-deploy-ut2njev1/ramdisk/ramdisk.cpio.gz.uboot
261 07:13:07.846662 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 07:13:07.846949 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
263 07:13:07.847223 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
264 07:13:07.847465 No LXC device requested
265 07:13:07.847746 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 07:13:07.848051 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
267 07:13:07.848618 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 07:13:07.849075 Checking files for TFTP limit of 4294967296 bytes.
269 07:13:07.852039 end: 1 tftp-deploy (duration 00:00:40) [common]
270 07:13:07.852670 start: 2 uboot-action (timeout 00:05:00) [common]
271 07:13:07.853250 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 07:13:07.853799 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 07:13:07.854352 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 07:13:07.854924 Using kernel file from prepare-kernel: 742687/tftp-deploy-ut2njev1/kernel/uImage
275 07:13:07.855612 substitutions:
276 07:13:07.856095 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 07:13:07.856549 - {DTB_ADDR}: 0x01070000
278 07:13:07.856989 - {DTB}: 742687/tftp-deploy-ut2njev1/dtb/meson-g12b-a311d-libretech-cc.dtb
279 07:13:07.857428 - {INITRD}: 742687/tftp-deploy-ut2njev1/ramdisk/ramdisk.cpio.gz.uboot
280 07:13:07.857869 - {KERNEL_ADDR}: 0x01080000
281 07:13:07.858307 - {KERNEL}: 742687/tftp-deploy-ut2njev1/kernel/uImage
282 07:13:07.858742 - {LAVA_MAC}: None
283 07:13:07.859217 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/742687/extract-nfsrootfs-mowu3ssu
284 07:13:07.859657 - {NFS_SERVER_IP}: 192.168.6.2
285 07:13:07.860119 - {PRESEED_CONFIG}: None
286 07:13:07.860553 - {PRESEED_LOCAL}: None
287 07:13:07.860985 - {RAMDISK_ADDR}: 0x08000000
288 07:13:07.861410 - {RAMDISK}: 742687/tftp-deploy-ut2njev1/ramdisk/ramdisk.cpio.gz.uboot
289 07:13:07.861838 - {ROOT_PART}: None
290 07:13:07.862270 - {ROOT}: None
291 07:13:07.862702 - {SERVER_IP}: 192.168.6.2
292 07:13:07.863131 - {TEE_ADDR}: 0x83000000
293 07:13:07.863559 - {TEE}: None
294 07:13:07.864010 Parsed boot commands:
295 07:13:07.864441 - setenv autoload no
296 07:13:07.864871 - setenv initrd_high 0xffffffff
297 07:13:07.865299 - setenv fdt_high 0xffffffff
298 07:13:07.865719 - dhcp
299 07:13:07.866146 - setenv serverip 192.168.6.2
300 07:13:07.866569 - tftpboot 0x01080000 742687/tftp-deploy-ut2njev1/kernel/uImage
301 07:13:07.866996 - tftpboot 0x08000000 742687/tftp-deploy-ut2njev1/ramdisk/ramdisk.cpio.gz.uboot
302 07:13:07.867423 - tftpboot 0x01070000 742687/tftp-deploy-ut2njev1/dtb/meson-g12b-a311d-libretech-cc.dtb
303 07:13:07.867852 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/742687/extract-nfsrootfs-mowu3ssu,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 07:13:07.868331 - bootm 0x01080000 0x08000000 0x01070000
305 07:13:07.868881 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 07:13:07.870522 start: 2.3 connect-device (timeout 00:05:00) [common]
308 07:13:07.870980 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 07:13:07.887434 Setting prompt string to ['lava-test: # ']
310 07:13:07.889170 end: 2.3 connect-device (duration 00:00:00) [common]
311 07:13:07.889930 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 07:13:07.890618 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 07:13:07.891194 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 07:13:07.892702 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 07:13:07.930353 >> OK - accepted request
316 07:13:07.932287 Returned 0 in 0 seconds
317 07:13:08.033475 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 07:13:08.035211 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 07:13:08.035850 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 07:13:08.036472 Setting prompt string to ['Hit any key to stop autoboot']
322 07:13:08.036983 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 07:13:08.038688 Trying 192.168.56.21...
324 07:13:08.039221 Connected to conserv1.
325 07:13:08.039679 Escape character is '^]'.
326 07:13:08.040177
327 07:13:08.040648 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 07:13:08.041120
329 07:13:18.899858 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 07:13:18.900561 bl2_stage_init 0x01
331 07:13:18.901018 bl2_stage_init 0x81
332 07:13:18.905514 hw id: 0x0000 - pwm id 0x01
333 07:13:18.906026 bl2_stage_init 0xc1
334 07:13:18.906482 bl2_stage_init 0x02
335 07:13:18.906916
336 07:13:18.911029 L0:00000000
337 07:13:18.911530 L1:20000703
338 07:13:18.912009 L2:00008067
339 07:13:18.912458 L3:14000000
340 07:13:18.913919 B2:00402000
341 07:13:18.914422 B1:e0f83180
342 07:13:18.914873
343 07:13:18.915305 TE: 58167
344 07:13:18.915741
345 07:13:18.925093 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 07:13:18.925610
347 07:13:18.926053 Board ID = 1
348 07:13:18.926482 Set A53 clk to 24M
349 07:13:18.926909 Set A73 clk to 24M
350 07:13:18.930708 Set clk81 to 24M
351 07:13:18.931194 A53 clk: 1200 MHz
352 07:13:18.931627 A73 clk: 1200 MHz
353 07:13:18.936207 CLK81: 166.6M
354 07:13:18.936691 smccc: 00012abe
355 07:13:18.941863 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 07:13:18.942352 board id: 1
357 07:13:18.947477 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 07:13:18.961141 fw parse done
359 07:13:18.966151 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 07:13:19.008881 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 07:13:19.020713 PIEI prepare done
362 07:13:19.021197 fastboot data load
363 07:13:19.021634 fastboot data verify
364 07:13:19.026350 verify result: 266
365 07:13:19.031878 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 07:13:19.032411 LPDDR4 probe
367 07:13:19.032842 ddr clk to 1584MHz
368 07:13:19.038932 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 07:13:19.076214
370 07:13:19.076735 dmc_version 0001
371 07:13:19.083815 Check phy result
372 07:13:19.089743 INFO : End of CA training
373 07:13:19.090225 INFO : End of initialization
374 07:13:19.095217 INFO : Training has run successfully!
375 07:13:19.095696 Check phy result
376 07:13:19.100902 INFO : End of initialization
377 07:13:19.101379 INFO : End of read enable training
378 07:13:19.106468 INFO : End of fine write leveling
379 07:13:19.112056 INFO : End of Write leveling coarse delay
380 07:13:19.112540 INFO : Training has run successfully!
381 07:13:19.112975 Check phy result
382 07:13:19.117726 INFO : End of initialization
383 07:13:19.118222 INFO : End of read dq deskew training
384 07:13:19.123288 INFO : End of MPR read delay center optimization
385 07:13:19.128852 INFO : End of write delay center optimization
386 07:13:19.134526 INFO : End of read delay center optimization
387 07:13:19.135007 INFO : End of max read latency training
388 07:13:19.140050 INFO : Training has run successfully!
389 07:13:19.140548 1D training succeed
390 07:13:19.148254 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 07:13:19.195908 Check phy result
392 07:13:19.196461 INFO : End of initialization
393 07:13:19.217543 INFO : End of 2D read delay Voltage center optimization
394 07:13:19.237074 INFO : End of 2D read delay Voltage center optimization
395 07:13:19.288998 INFO : End of 2D write delay Voltage center optimization
396 07:13:19.339349 INFO : End of 2D write delay Voltage center optimization
397 07:13:19.344863 INFO : Training has run successfully!
398 07:13:19.345354
399 07:13:19.345803 channel==0
400 07:13:19.350580 RxClkDly_Margin_A0==88 ps 9
401 07:13:19.351114 TxDqDly_Margin_A0==98 ps 10
402 07:13:19.353833 RxClkDly_Margin_A1==88 ps 9
403 07:13:19.354321 TxDqDly_Margin_A1==98 ps 10
404 07:13:19.359400 TrainedVREFDQ_A0==74
405 07:13:19.359892 TrainedVREFDQ_A1==74
406 07:13:19.360386 VrefDac_Margin_A0==25
407 07:13:19.365043 DeviceVref_Margin_A0==40
408 07:13:19.365533 VrefDac_Margin_A1==25
409 07:13:19.370657 DeviceVref_Margin_A1==40
410 07:13:19.371149
411 07:13:19.371592
412 07:13:19.372063 channel==1
413 07:13:19.372507 RxClkDly_Margin_A0==98 ps 10
414 07:13:19.373976 TxDqDly_Margin_A0==98 ps 10
415 07:13:19.379579 RxClkDly_Margin_A1==88 ps 9
416 07:13:19.380093 TxDqDly_Margin_A1==88 ps 9
417 07:13:19.380541 TrainedVREFDQ_A0==77
418 07:13:19.385114 TrainedVREFDQ_A1==77
419 07:13:19.385619 VrefDac_Margin_A0==23
420 07:13:19.390782 DeviceVref_Margin_A0==37
421 07:13:19.391273 VrefDac_Margin_A1==24
422 07:13:19.391725 DeviceVref_Margin_A1==37
423 07:13:19.392208
424 07:13:19.399655 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 07:13:19.400209
426 07:13:19.427650 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 07:13:19.428296 2D training succeed
428 07:13:19.438847 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 07:13:19.439341 auto size-- 65535DDR cs0 size: 2048MB
430 07:13:19.439780 DDR cs1 size: 2048MB
431 07:13:19.444450 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 07:13:19.444937 cs0 DataBus test pass
433 07:13:19.450046 cs1 DataBus test pass
434 07:13:19.450526 cs0 AddrBus test pass
435 07:13:19.455631 cs1 AddrBus test pass
436 07:13:19.456135
437 07:13:19.456576 100bdlr_step_size ps== 420
438 07:13:19.457016 result report
439 07:13:19.461255 boot times 0Enable ddr reg access
440 07:13:19.466944 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 07:13:19.480325 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 07:13:20.055344 0.0;M3 CHK:0;cm4_sp_mode 0
443 07:13:20.056041 MVN_1=0x00000000
444 07:13:20.060525 MVN_2=0x00000000
445 07:13:20.066313 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 07:13:20.066815 OPS=0x10
447 07:13:20.067266 ring efuse init
448 07:13:20.067708 chipver efuse init
449 07:13:20.071861 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 07:13:20.077483 [0.018960 Inits done]
451 07:13:20.077983 secure task start!
452 07:13:20.078429 high task start!
453 07:13:20.081122 low task start!
454 07:13:20.081610 run into bl31
455 07:13:20.088705 NOTICE: BL31: v1.3(release):4fc40b1
456 07:13:20.095563 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 07:13:20.096096 NOTICE: BL31: G12A normal boot!
458 07:13:20.121965 NOTICE: BL31: BL33 decompress pass
459 07:13:20.126636 ERROR: Error initializing runtime service opteed_fast
460 07:13:21.360549
461 07:13:21.361228
462 07:13:21.368942 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 07:13:21.369477
464 07:13:21.369954 Model: Libre Computer AML-A311D-CC Alta
465 07:13:21.577330 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 07:13:21.600688 DRAM: 2 GiB (effective 3.8 GiB)
467 07:13:21.743733 Core: 408 devices, 31 uclasses, devicetree: separate
468 07:13:21.749586 WDT: Not starting watchdog@f0d0
469 07:13:21.781864 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 07:13:21.794260 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 07:13:21.799206 ** Bad device specification mmc 0 **
472 07:13:21.809567 Card did not respond to voltage select! : -110
473 07:13:21.817185 ** Bad device specification mmc 0 **
474 07:13:21.817686 Couldn't find partition mmc 0
475 07:13:21.825558 Card did not respond to voltage select! : -110
476 07:13:21.831037 ** Bad device specification mmc 0 **
477 07:13:21.831532 Couldn't find partition mmc 0
478 07:13:21.836141 Error: could not access storage.
479 07:13:23.100420 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 07:13:23.100846 bl2_stage_init 0x01
481 07:13:23.101072 bl2_stage_init 0x81
482 07:13:23.106025 hw id: 0x0000 - pwm id 0x01
483 07:13:23.106446 bl2_stage_init 0xc1
484 07:13:23.106776 bl2_stage_init 0x02
485 07:13:23.107087
486 07:13:23.111568 L0:00000000
487 07:13:23.111950 L1:20000703
488 07:13:23.112220 L2:00008067
489 07:13:23.112429 L3:14000000
490 07:13:23.114430 B2:00402000
491 07:13:23.114790 B1:e0f83180
492 07:13:23.115110
493 07:13:23.115421 TE: 58167
494 07:13:23.115722
495 07:13:23.125664 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 07:13:23.126174
497 07:13:23.126609 Board ID = 1
498 07:13:23.127021 Set A53 clk to 24M
499 07:13:23.127428 Set A73 clk to 24M
500 07:13:23.131265 Set clk81 to 24M
501 07:13:23.131707 A53 clk: 1200 MHz
502 07:13:23.132151 A73 clk: 1200 MHz
503 07:13:23.136851 CLK81: 166.6M
504 07:13:23.137287 smccc: 00012abd
505 07:13:23.142440 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 07:13:23.142871 board id: 1
507 07:13:23.151118 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 07:13:23.161743 fw parse done
509 07:13:23.167687 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 07:13:23.210325 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 07:13:23.221237 PIEI prepare done
512 07:13:23.221694 fastboot data load
513 07:13:23.222115 fastboot data verify
514 07:13:23.226877 verify result: 266
515 07:13:23.232443 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 07:13:23.232887 LPDDR4 probe
517 07:13:23.233297 ddr clk to 1584MHz
518 07:13:23.240432 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 07:13:23.277728
520 07:13:23.278207 dmc_version 0001
521 07:13:23.284365 Check phy result
522 07:13:23.290266 INFO : End of CA training
523 07:13:23.290721 INFO : End of initialization
524 07:13:23.295809 INFO : Training has run successfully!
525 07:13:23.296309 Check phy result
526 07:13:23.301405 INFO : End of initialization
527 07:13:23.301845 INFO : End of read enable training
528 07:13:23.307029 INFO : End of fine write leveling
529 07:13:23.312632 INFO : End of Write leveling coarse delay
530 07:13:23.313078 INFO : Training has run successfully!
531 07:13:23.313495 Check phy result
532 07:13:23.318260 INFO : End of initialization
533 07:13:23.318712 INFO : End of read dq deskew training
534 07:13:23.323809 INFO : End of MPR read delay center optimization
535 07:13:23.329412 INFO : End of write delay center optimization
536 07:13:23.335018 INFO : End of read delay center optimization
537 07:13:23.335457 INFO : End of max read latency training
538 07:13:23.340645 INFO : Training has run successfully!
539 07:13:23.341084 1D training succeed
540 07:13:23.349024 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 07:13:23.397508 Check phy result
542 07:13:23.397977 INFO : End of initialization
543 07:13:23.419272 INFO : End of 2D read delay Voltage center optimization
544 07:13:23.439511 INFO : End of 2D read delay Voltage center optimization
545 07:13:23.491575 INFO : End of 2D write delay Voltage center optimization
546 07:13:23.540835 INFO : End of 2D write delay Voltage center optimization
547 07:13:23.546525 INFO : Training has run successfully!
548 07:13:23.546983
549 07:13:23.547406 channel==0
550 07:13:23.552065 RxClkDly_Margin_A0==88 ps 9
551 07:13:23.552538 TxDqDly_Margin_A0==98 ps 10
552 07:13:23.557675 RxClkDly_Margin_A1==88 ps 9
553 07:13:23.558122 TxDqDly_Margin_A1==88 ps 9
554 07:13:23.558539 TrainedVREFDQ_A0==74
555 07:13:23.563276 TrainedVREFDQ_A1==74
556 07:13:23.563722 VrefDac_Margin_A0==25
557 07:13:23.564165 DeviceVref_Margin_A0==40
558 07:13:23.568921 VrefDac_Margin_A1==25
559 07:13:23.569371 DeviceVref_Margin_A1==40
560 07:13:23.569782
561 07:13:23.570184
562 07:13:23.570585 channel==1
563 07:13:23.574483 RxClkDly_Margin_A0==98 ps 10
564 07:13:23.574924 TxDqDly_Margin_A0==88 ps 9
565 07:13:23.580039 RxClkDly_Margin_A1==88 ps 9
566 07:13:23.580488 TxDqDly_Margin_A1==88 ps 9
567 07:13:23.585609 TrainedVREFDQ_A0==77
568 07:13:23.586074 TrainedVREFDQ_A1==77
569 07:13:23.586494 VrefDac_Margin_A0==22
570 07:13:23.591240 DeviceVref_Margin_A0==37
571 07:13:23.591710 VrefDac_Margin_A1==24
572 07:13:23.596895 DeviceVref_Margin_A1==37
573 07:13:23.597340
574 07:13:23.597754 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 07:13:23.598159
576 07:13:23.630469 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
577 07:13:23.630944 2D training succeed
578 07:13:23.636102 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 07:13:23.641659 auto size-- 65535DDR cs0 size: 2048MB
580 07:13:23.642113 DDR cs1 size: 2048MB
581 07:13:23.647298 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 07:13:23.647745 cs0 DataBus test pass
583 07:13:23.652774 cs1 DataBus test pass
584 07:13:23.653233 cs0 AddrBus test pass
585 07:13:23.653645 cs1 AddrBus test pass
586 07:13:23.654051
587 07:13:23.658403 100bdlr_step_size ps== 420
588 07:13:23.658867 result report
589 07:13:23.663957 boot times 0Enable ddr reg access
590 07:13:23.669128 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 07:13:23.682648 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 07:13:24.256405 0.0;M3 CHK:0;cm4_sp_mode 0
593 07:13:24.257069 MVN_1=0x00000000
594 07:13:24.261825 MVN_2=0x00000000
595 07:13:24.267562 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 07:13:24.268193 OPS=0x10
597 07:13:24.268673 ring efuse init
598 07:13:24.269142 chipver efuse init
599 07:13:24.273125 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 07:13:24.278703 [0.018961 Inits done]
601 07:13:24.279191 secure task start!
602 07:13:24.279594 high task start!
603 07:13:24.283292 low task start!
604 07:13:24.283739 run into bl31
605 07:13:24.290019 NOTICE: BL31: v1.3(release):4fc40b1
606 07:13:24.297742 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 07:13:24.298221 NOTICE: BL31: G12A normal boot!
608 07:13:24.323709 NOTICE: BL31: BL33 decompress pass
609 07:13:24.329491 ERROR: Error initializing runtime service opteed_fast
610 07:13:25.562362
611 07:13:25.562963
612 07:13:25.570806 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 07:13:25.571282
614 07:13:25.571710 Model: Libre Computer AML-A311D-CC Alta
615 07:13:25.779234 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 07:13:25.802551 DRAM: 2 GiB (effective 3.8 GiB)
617 07:13:25.945524 Core: 408 devices, 31 uclasses, devicetree: separate
618 07:13:25.951421 WDT: Not starting watchdog@f0d0
619 07:13:25.983754 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 07:13:25.996116 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 07:13:26.001083 ** Bad device specification mmc 0 **
622 07:13:26.011438 Card did not respond to voltage select! : -110
623 07:13:26.019071 ** Bad device specification mmc 0 **
624 07:13:26.019536 Couldn't find partition mmc 0
625 07:13:26.027393 Card did not respond to voltage select! : -110
626 07:13:26.032922 ** Bad device specification mmc 0 **
627 07:13:26.033423 Couldn't find partition mmc 0
628 07:13:26.037992 Error: could not access storage.
629 07:13:26.380521 Net: eth0: ethernet@ff3f0000
630 07:13:26.381142 starting USB...
631 07:13:26.632330 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 07:13:26.632915 Starting the controller
633 07:13:26.639241 USB XHCI 1.10
634 07:13:28.350507 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 07:13:28.350937 bl2_stage_init 0x01
636 07:13:28.351160 bl2_stage_init 0x81
637 07:13:28.356226 hw id: 0x0000 - pwm id 0x01
638 07:13:28.356712 bl2_stage_init 0xc1
639 07:13:28.357075 bl2_stage_init 0x02
640 07:13:28.357411
641 07:13:28.361646 L0:00000000
642 07:13:28.362124 L1:20000703
643 07:13:28.362385 L2:00008067
644 07:13:28.362604 L3:14000000
645 07:13:28.367218 B2:00402000
646 07:13:28.367702 B1:e0f83180
647 07:13:28.368078
648 07:13:28.368419 TE: 58167
649 07:13:28.368663
650 07:13:28.372935 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 07:13:28.373287
652 07:13:28.373508 Board ID = 1
653 07:13:28.378565 Set A53 clk to 24M
654 07:13:28.379135 Set A73 clk to 24M
655 07:13:28.379572 Set clk81 to 24M
656 07:13:28.384207 A53 clk: 1200 MHz
657 07:13:28.384729 A73 clk: 1200 MHz
658 07:13:28.385167 CLK81: 166.6M
659 07:13:28.385595 smccc: 00012abd
660 07:13:28.389716 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 07:13:28.395283 board id: 1
662 07:13:28.401456 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 07:13:28.411861 fw parse done
664 07:13:28.417767 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 07:13:28.460399 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 07:13:28.471339 PIEI prepare done
667 07:13:28.471907 fastboot data load
668 07:13:28.472386 fastboot data verify
669 07:13:28.476957 verify result: 266
670 07:13:28.482500 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 07:13:28.482973 LPDDR4 probe
672 07:13:28.483398 ddr clk to 1584MHz
673 07:13:28.490429 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 07:13:28.527801
675 07:13:28.528332 dmc_version 0001
676 07:13:28.538734 Check phy result
677 07:13:28.539208 INFO : End of CA training
678 07:13:28.544340 INFO : End of initialization
679 07:13:28.544800 INFO : Training has run successfully!
680 07:13:28.549907 Check phy result
681 07:13:28.550365 INFO : End of initialization
682 07:13:28.555505 INFO : End of read enable training
683 07:13:28.555967 INFO : End of fine write leveling
684 07:13:28.561133 INFO : End of Write leveling coarse delay
685 07:13:28.561617 INFO : Training has run successfully!
686 07:13:28.566771 Check phy result
687 07:13:28.567233 INFO : End of initialization
688 07:13:28.572323 INFO : End of read dq deskew training
689 07:13:28.577869 INFO : End of MPR read delay center optimization
690 07:13:28.578325 INFO : End of write delay center optimization
691 07:13:28.583527 INFO : End of read delay center optimization
692 07:13:28.589116 INFO : End of max read latency training
693 07:13:28.589584 INFO : Training has run successfully!
694 07:13:28.594713 1D training succeed
695 07:13:28.599892 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 07:13:28.647607 Check phy result
697 07:13:28.648162 INFO : End of initialization
698 07:13:28.669457 INFO : End of 2D read delay Voltage center optimization
699 07:13:28.688914 INFO : End of 2D read delay Voltage center optimization
700 07:13:28.740901 INFO : End of 2D write delay Voltage center optimization
701 07:13:28.790232 INFO : End of 2D write delay Voltage center optimization
702 07:13:28.795700 INFO : Training has run successfully!
703 07:13:28.796218
704 07:13:28.796651 channel==0
705 07:13:28.801233 RxClkDly_Margin_A0==88 ps 9
706 07:13:28.801713 TxDqDly_Margin_A0==98 ps 10
707 07:13:28.804724 RxClkDly_Margin_A1==88 ps 9
708 07:13:28.805188 TxDqDly_Margin_A1==88 ps 9
709 07:13:28.810209 TrainedVREFDQ_A0==74
710 07:13:28.810673 TrainedVREFDQ_A1==74
711 07:13:28.811088 VrefDac_Margin_A0==24
712 07:13:28.815973 DeviceVref_Margin_A0==40
713 07:13:28.816556 VrefDac_Margin_A1==25
714 07:13:28.821548 DeviceVref_Margin_A1==40
715 07:13:28.822006
716 07:13:28.822421
717 07:13:28.822825 channel==1
718 07:13:28.823249 RxClkDly_Margin_A0==88 ps 9
719 07:13:28.825144 TxDqDly_Margin_A0==98 ps 10
720 07:13:28.830542 RxClkDly_Margin_A1==88 ps 9
721 07:13:28.831018 TxDqDly_Margin_A1==88 ps 9
722 07:13:28.831420 TrainedVREFDQ_A0==77
723 07:13:28.836212 TrainedVREFDQ_A1==77
724 07:13:28.836676 VrefDac_Margin_A0==22
725 07:13:28.841706 DeviceVref_Margin_A0==37
726 07:13:28.842154 VrefDac_Margin_A1==24
727 07:13:28.842551 DeviceVref_Margin_A1==37
728 07:13:28.842942
729 07:13:28.847242 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 07:13:28.847683
731 07:13:28.880875 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000019 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
732 07:13:28.881388 2D training succeed
733 07:13:28.886518 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 07:13:28.891977 auto size-- 65535DDR cs0 size: 2048MB
735 07:13:28.892449 DDR cs1 size: 2048MB
736 07:13:28.897578 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 07:13:28.898015 cs0 DataBus test pass
738 07:13:28.898409 cs1 DataBus test pass
739 07:13:28.903129 cs0 AddrBus test pass
740 07:13:28.903564 cs1 AddrBus test pass
741 07:13:28.903958
742 07:13:28.908769 100bdlr_step_size ps== 420
743 07:13:28.909222 result report
744 07:13:28.909615 boot times 0Enable ddr reg access
745 07:13:28.918424 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 07:13:28.931897 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 07:13:29.505488 0.0;M3 CHK:0;cm4_sp_mode 0
748 07:13:29.505930 MVN_1=0x00000000
749 07:13:29.511035 MVN_2=0x00000000
750 07:13:29.516790 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 07:13:29.517128 OPS=0x10
752 07:13:29.517358 ring efuse init
753 07:13:29.517571 chipver efuse init
754 07:13:29.522307 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 07:13:29.528118 [0.018961 Inits done]
756 07:13:29.528865 secure task start!
757 07:13:29.529401 high task start!
758 07:13:29.532530 low task start!
759 07:13:29.533023 run into bl31
760 07:13:29.539167 NOTICE: BL31: v1.3(release):4fc40b1
761 07:13:29.547061 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 07:13:29.547564 NOTICE: BL31: G12A normal boot!
763 07:13:29.572403 NOTICE: BL31: BL33 decompress pass
764 07:13:29.578116 ERROR: Error initializing runtime service opteed_fast
765 07:13:30.811080
766 07:13:30.811891
767 07:13:30.819496 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 07:13:30.820170
769 07:13:30.820731 Model: Libre Computer AML-A311D-CC Alta
770 07:13:31.027891 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 07:13:31.051255 DRAM: 2 GiB (effective 3.8 GiB)
772 07:13:31.194171 Core: 408 devices, 31 uclasses, devicetree: separate
773 07:13:31.200045 WDT: Not starting watchdog@f0d0
774 07:13:31.240981 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 07:13:31.249770 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 07:13:31.250189 ** Bad device specification mmc 0 **
777 07:13:31.260167 Card did not respond to voltage select! : -110
778 07:13:31.267714 ** Bad device specification mmc 0 **
779 07:13:31.268123 Couldn't find partition mmc 0
780 07:13:31.276193 Card did not respond to voltage select! : -110
781 07:13:31.281584 ** Bad device specification mmc 0 **
782 07:13:31.281975 Couldn't find partition mmc 0
783 07:13:31.286650 Error: could not access storage.
784 07:13:31.629240 Net: eth0: ethernet@ff3f0000
785 07:13:31.629835 starting USB...
786 07:13:31.880974 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 07:13:31.881420 Starting the controller
788 07:13:31.887930 USB XHCI 1.10
789 07:13:34.030531 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 07:13:34.031094 bl2_stage_init 0x01
791 07:13:34.031353 bl2_stage_init 0x81
792 07:13:34.036093 hw id: 0x0000 - pwm id 0x01
793 07:13:34.036426 bl2_stage_init 0xc1
794 07:13:34.036652 bl2_stage_init 0x02
795 07:13:34.036859
796 07:13:34.041728 L0:00000000
797 07:13:34.042045 L1:20000703
798 07:13:34.042262 L2:00008067
799 07:13:34.042468 L3:14000000
800 07:13:34.047275 B2:00402000
801 07:13:34.047606 B1:e0f83180
802 07:13:34.047831
803 07:13:34.048058 TE: 58124
804 07:13:34.048273
805 07:13:34.052857 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 07:13:34.053180
807 07:13:34.053403 Board ID = 1
808 07:13:34.058495 Set A53 clk to 24M
809 07:13:34.058829 Set A73 clk to 24M
810 07:13:34.059047 Set clk81 to 24M
811 07:13:34.064129 A53 clk: 1200 MHz
812 07:13:34.064618 A73 clk: 1200 MHz
813 07:13:34.065025 CLK81: 166.6M
814 07:13:34.065433 smccc: 00012a92
815 07:13:34.069955 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 07:13:34.075354 board id: 1
817 07:13:34.081357 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 07:13:34.092120 fw parse done
819 07:13:34.097893 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 07:13:34.139540 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 07:13:34.151437 PIEI prepare done
822 07:13:34.152064 fastboot data load
823 07:13:34.152552 fastboot data verify
824 07:13:34.157132 verify result: 266
825 07:13:34.162681 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 07:13:34.163263 LPDDR4 probe
827 07:13:34.163731 ddr clk to 1584MHz
828 07:13:34.169775 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 07:13:34.207540
830 07:13:34.207931 dmc_version 0001
831 07:13:34.213718 Check phy result
832 07:13:34.220666 INFO : End of CA training
833 07:13:34.221228 INFO : End of initialization
834 07:13:34.226028 INFO : Training has run successfully!
835 07:13:34.226521 Check phy result
836 07:13:34.231632 INFO : End of initialization
837 07:13:34.232189 INFO : End of read enable training
838 07:13:34.235250 INFO : End of fine write leveling
839 07:13:34.240809 INFO : End of Write leveling coarse delay
840 07:13:34.245973 INFO : Training has run successfully!
841 07:13:34.246481 Check phy result
842 07:13:34.246909 INFO : End of initialization
843 07:13:34.251694 INFO : End of read dq deskew training
844 07:13:34.255061 INFO : End of MPR read delay center optimization
845 07:13:34.260699 INFO : End of write delay center optimization
846 07:13:34.266103 INFO : End of read delay center optimization
847 07:13:34.266579 INFO : End of max read latency training
848 07:13:34.271883 INFO : Training has run successfully!
849 07:13:34.272414 1D training succeed
850 07:13:34.280127 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 07:13:34.326703 Check phy result
852 07:13:34.327268 INFO : End of initialization
853 07:13:34.348250 INFO : End of 2D read delay Voltage center optimization
854 07:13:34.369368 INFO : End of 2D read delay Voltage center optimization
855 07:13:34.420387 INFO : End of 2D write delay Voltage center optimization
856 07:13:34.470513 INFO : End of 2D write delay Voltage center optimization
857 07:13:34.475971 INFO : Training has run successfully!
858 07:13:34.476530
859 07:13:34.476963 channel==0
860 07:13:34.481585 RxClkDly_Margin_A0==88 ps 9
861 07:13:34.482104 TxDqDly_Margin_A0==98 ps 10
862 07:13:34.487224 RxClkDly_Margin_A1==88 ps 9
863 07:13:34.487729 TxDqDly_Margin_A1==98 ps 10
864 07:13:34.488201 TrainedVREFDQ_A0==74
865 07:13:34.492869 TrainedVREFDQ_A1==74
866 07:13:34.493387 VrefDac_Margin_A0==25
867 07:13:34.493809 DeviceVref_Margin_A0==40
868 07:13:34.498442 VrefDac_Margin_A1==25
869 07:13:34.498944 DeviceVref_Margin_A1==40
870 07:13:34.499358
871 07:13:34.499762
872 07:13:34.504046 channel==1
873 07:13:34.504547 RxClkDly_Margin_A0==98 ps 10
874 07:13:34.504965 TxDqDly_Margin_A0==98 ps 10
875 07:13:34.509640 RxClkDly_Margin_A1==88 ps 9
876 07:13:34.510157 TxDqDly_Margin_A1==88 ps 9
877 07:13:34.515293 TrainedVREFDQ_A0==77
878 07:13:34.515835 TrainedVREFDQ_A1==77
879 07:13:34.516290 VrefDac_Margin_A0==22
880 07:13:34.520905 DeviceVref_Margin_A0==37
881 07:13:34.521484 VrefDac_Margin_A1==24
882 07:13:34.526450 DeviceVref_Margin_A1==37
883 07:13:34.527034
884 07:13:34.527491 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 07:13:34.527889
886 07:13:34.560046 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
887 07:13:34.560722 2D training succeed
888 07:13:34.565547 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 07:13:34.571119 auto size-- 65535DDR cs0 size: 2048MB
890 07:13:34.571643 DDR cs1 size: 2048MB
891 07:13:34.576704 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 07:13:34.577190 cs0 DataBus test pass
893 07:13:34.582294 cs1 DataBus test pass
894 07:13:34.582754 cs0 AddrBus test pass
895 07:13:34.583146 cs1 AddrBus test pass
896 07:13:34.583536
897 07:13:34.587976 100bdlr_step_size ps== 420
898 07:13:34.588574 result report
899 07:13:34.593539 boot times 0Enable ddr reg access
900 07:13:34.598934 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 07:13:34.611363 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 07:13:35.184330 0.0;M3 CHK:0;cm4_sp_mode 0
903 07:13:35.184772 MVN_1=0x00000000
904 07:13:35.189917 MVN_2=0x00000000
905 07:13:35.195574 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 07:13:35.195906 OPS=0x10
907 07:13:35.196169 ring efuse init
908 07:13:35.196399 chipver efuse init
909 07:13:35.201208 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 07:13:35.206802 [0.018961 Inits done]
911 07:13:35.207258 secure task start!
912 07:13:35.207532 high task start!
913 07:13:35.211342 low task start!
914 07:13:35.211655 run into bl31
915 07:13:35.218025 NOTICE: BL31: v1.3(release):4fc40b1
916 07:13:35.225852 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 07:13:35.226219 NOTICE: BL31: G12A normal boot!
918 07:13:35.251714 NOTICE: BL31: BL33 decompress pass
919 07:13:35.257372 ERROR: Error initializing runtime service opteed_fast
920 07:13:36.490304
921 07:13:36.490746
922 07:13:36.497983 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 07:13:36.498381
924 07:13:36.498616 Model: Libre Computer AML-A311D-CC Alta
925 07:13:36.707078 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 07:13:36.730537 DRAM: 2 GiB (effective 3.8 GiB)
927 07:13:36.873568 Core: 408 devices, 31 uclasses, devicetree: separate
928 07:13:36.879445 WDT: Not starting watchdog@f0d0
929 07:13:36.912192 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 07:13:36.924238 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 07:13:36.929065 ** Bad device specification mmc 0 **
932 07:13:36.939456 Card did not respond to voltage select! : -110
933 07:13:36.947185 ** Bad device specification mmc 0 **
934 07:13:36.947654 Couldn't find partition mmc 0
935 07:13:36.955683 Card did not respond to voltage select! : -110
936 07:13:36.961050 ** Bad device specification mmc 0 **
937 07:13:36.961643 Couldn't find partition mmc 0
938 07:13:36.966015 Error: could not access storage.
939 07:13:37.309478 Net: eth0: ethernet@ff3f0000
940 07:13:37.310081 starting USB...
941 07:13:37.561401 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 07:13:37.561989 Starting the controller
943 07:13:37.567325 USB XHCI 1.10
944 07:13:39.430786 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 07:13:39.431385 bl2_stage_init 0x01
946 07:13:39.431818 bl2_stage_init 0x81
947 07:13:39.435917 hw id: 0x0000 - pwm id 0x01
948 07:13:39.436393 bl2_stage_init 0xc1
949 07:13:39.436807 bl2_stage_init 0x02
950 07:13:39.437212
951 07:13:39.441543 L0:00000000
952 07:13:39.441995 L1:20000703
953 07:13:39.442403 L2:00008067
954 07:13:39.442804 L3:14000000
955 07:13:39.444497 B2:00402000
956 07:13:39.444930 B1:e0f83180
957 07:13:39.445336
958 07:13:39.445740 TE: 58124
959 07:13:39.446142
960 07:13:39.455607 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 07:13:39.456103
962 07:13:39.456527 Board ID = 1
963 07:13:39.456929 Set A53 clk to 24M
964 07:13:39.457328 Set A73 clk to 24M
965 07:13:39.461225 Set clk81 to 24M
966 07:13:39.461670 A53 clk: 1200 MHz
967 07:13:39.462074 A73 clk: 1200 MHz
968 07:13:39.466831 CLK81: 166.6M
969 07:13:39.467269 smccc: 00012a92
970 07:13:39.472472 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 07:13:39.472926 board id: 1
972 07:13:39.481050 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 07:13:39.491796 fw parse done
974 07:13:39.497637 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 07:13:39.540321 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 07:13:39.551295 PIEI prepare done
977 07:13:39.551820 fastboot data load
978 07:13:39.552262 fastboot data verify
979 07:13:39.556881 verify result: 266
980 07:13:39.562561 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 07:13:39.562999 LPDDR4 probe
982 07:13:39.563391 ddr clk to 1584MHz
983 07:13:39.570454 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 07:13:39.607774
985 07:13:39.608306 dmc_version 0001
986 07:13:39.614367 Check phy result
987 07:13:39.620195 INFO : End of CA training
988 07:13:39.620622 INFO : End of initialization
989 07:13:39.625823 INFO : Training has run successfully!
990 07:13:39.626315 Check phy result
991 07:13:39.631403 INFO : End of initialization
992 07:13:39.631838 INFO : End of read enable training
993 07:13:39.636984 INFO : End of fine write leveling
994 07:13:39.642613 INFO : End of Write leveling coarse delay
995 07:13:39.643039 INFO : Training has run successfully!
996 07:13:39.643429 Check phy result
997 07:13:39.648199 INFO : End of initialization
998 07:13:39.648632 INFO : End of read dq deskew training
999 07:13:39.653825 INFO : End of MPR read delay center optimization
1000 07:13:39.659594 INFO : End of write delay center optimization
1001 07:13:39.665044 INFO : End of read delay center optimization
1002 07:13:39.665477 INFO : End of max read latency training
1003 07:13:39.670590 INFO : Training has run successfully!
1004 07:13:39.671017 1D training succeed
1005 07:13:39.679755 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 07:13:39.727565 Check phy result
1007 07:13:39.728124 INFO : End of initialization
1008 07:13:39.749172 INFO : End of 2D read delay Voltage center optimization
1009 07:13:39.769485 INFO : End of 2D read delay Voltage center optimization
1010 07:13:39.821454 INFO : End of 2D write delay Voltage center optimization
1011 07:13:39.870861 INFO : End of 2D write delay Voltage center optimization
1012 07:13:39.876327 INFO : Training has run successfully!
1013 07:13:39.876785
1014 07:13:39.877196 channel==0
1015 07:13:39.881948 RxClkDly_Margin_A0==88 ps 9
1016 07:13:39.882400 TxDqDly_Margin_A0==98 ps 10
1017 07:13:39.887599 RxClkDly_Margin_A1==88 ps 9
1018 07:13:39.888097 TxDqDly_Margin_A1==98 ps 10
1019 07:13:39.888518 TrainedVREFDQ_A0==74
1020 07:13:39.893133 TrainedVREFDQ_A1==74
1021 07:13:39.893601 VrefDac_Margin_A0==25
1022 07:13:39.894010 DeviceVref_Margin_A0==40
1023 07:13:39.900030 VrefDac_Margin_A1==25
1024 07:13:39.900480 DeviceVref_Margin_A1==40
1025 07:13:39.900883
1026 07:13:39.901281
1027 07:13:39.904333 channel==1
1028 07:13:39.904776 RxClkDly_Margin_A0==98 ps 10
1029 07:13:39.905176 TxDqDly_Margin_A0==98 ps 10
1030 07:13:39.909897 RxClkDly_Margin_A1==88 ps 9
1031 07:13:39.910333 TxDqDly_Margin_A1==98 ps 10
1032 07:13:39.915577 TrainedVREFDQ_A0==77
1033 07:13:39.916034 TrainedVREFDQ_A1==78
1034 07:13:39.916447 VrefDac_Margin_A0==22
1035 07:13:39.921126 DeviceVref_Margin_A0==37
1036 07:13:39.921558 VrefDac_Margin_A1==24
1037 07:13:39.926970 DeviceVref_Margin_A1==36
1038 07:13:39.927472
1039 07:13:39.927884 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 07:13:39.932474
1041 07:13:39.960389 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1042 07:13:39.960989 2D training succeed
1043 07:13:39.966102 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 07:13:39.971705 auto size-- 65535DDR cs0 size: 2048MB
1045 07:13:39.972205 DDR cs1 size: 2048MB
1046 07:13:39.977212 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 07:13:39.977906 cs0 DataBus test pass
1048 07:13:39.982891 cs1 DataBus test pass
1049 07:13:39.983526 cs0 AddrBus test pass
1050 07:13:39.984118 cs1 AddrBus test pass
1051 07:13:39.984671
1052 07:13:39.988445 100bdlr_step_size ps== 420
1053 07:13:39.989076 result report
1054 07:13:39.994085 boot times 0Enable ddr reg access
1055 07:13:39.999232 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 07:13:40.012975 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 07:13:40.586121 0.0;M3 CHK:0;cm4_sp_mode 0
1058 07:13:40.586886 MVN_1=0x00000000
1059 07:13:40.591430 MVN_2=0x00000000
1060 07:13:40.597188 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 07:13:40.597794 OPS=0x10
1062 07:13:40.598343 ring efuse init
1063 07:13:40.598868 chipver efuse init
1064 07:13:40.602828 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 07:13:40.608429 [0.018961 Inits done]
1066 07:13:40.609052 secure task start!
1067 07:13:40.609591 high task start!
1068 07:13:40.613022 low task start!
1069 07:13:40.613657 run into bl31
1070 07:13:40.619681 NOTICE: BL31: v1.3(release):4fc40b1
1071 07:13:40.627437 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 07:13:40.628072 NOTICE: BL31: G12A normal boot!
1073 07:13:40.652943 NOTICE: BL31: BL33 decompress pass
1074 07:13:40.658506 ERROR: Error initializing runtime service opteed_fast
1075 07:13:41.891352
1076 07:13:41.892234
1077 07:13:41.899771 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 07:13:41.900488
1079 07:13:41.901039 Model: Libre Computer AML-A311D-CC Alta
1080 07:13:42.108308 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 07:13:42.131875 DRAM: 2 GiB (effective 3.8 GiB)
1082 07:13:42.274735 Core: 408 devices, 31 uclasses, devicetree: separate
1083 07:13:42.280380 WDT: Not starting watchdog@f0d0
1084 07:13:42.312783 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 07:13:42.325143 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 07:13:42.330228 ** Bad device specification mmc 0 **
1087 07:13:42.340498 Card did not respond to voltage select! : -110
1088 07:13:42.348204 ** Bad device specification mmc 0 **
1089 07:13:42.348775 Couldn't find partition mmc 0
1090 07:13:42.356539 Card did not respond to voltage select! : -110
1091 07:13:42.362018 ** Bad device specification mmc 0 **
1092 07:13:42.362585 Couldn't find partition mmc 0
1093 07:13:42.367064 Error: could not access storage.
1094 07:13:42.709627 Net: eth0: ethernet@ff3f0000
1095 07:13:42.710261 starting USB...
1096 07:13:42.961263 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 07:13:42.961693 Starting the controller
1098 07:13:42.968290 USB XHCI 1.10
1099 07:13:44.522562 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 07:13:44.530105 scanning usb for storage devices... 0 Storage Device(s) found
1102 07:13:44.581790 Hit any key to stop autoboot: 1
1103 07:13:44.582781 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 07:13:44.583477 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 07:13:44.584332 Setting prompt string to ['=>']
1106 07:13:44.584898 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 07:13:44.597681 0
1108 07:13:44.598711 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 07:13:44.599249 Sending with 10 millisecond of delay
1111 07:13:45.734549 => setenv autoload no
1112 07:13:45.745388 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 07:13:45.750783 setenv autoload no
1114 07:13:45.751594 Sending with 10 millisecond of delay
1116 07:13:47.550623 => setenv initrd_high 0xffffffff
1117 07:13:47.561770 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 07:13:47.562353 setenv initrd_high 0xffffffff
1119 07:13:47.562828 Sending with 10 millisecond of delay
1121 07:13:49.179374 => setenv fdt_high 0xffffffff
1122 07:13:49.190081 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1123 07:13:49.190662 setenv fdt_high 0xffffffff
1124 07:13:49.191192 Sending with 10 millisecond of delay
1126 07:13:49.483642 => dhcp
1127 07:13:49.494865 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 07:13:49.496220 dhcp
1129 07:13:49.496968 Speed: 1000, full duplex
1130 07:13:49.497576 BOOTP broadcast 1
1131 07:13:49.742528 BOOTP broadcast 2
1132 07:13:49.841329 DHCP client bound to address 192.168.6.33 (346 ms)
1133 07:13:49.842165 Sending with 10 millisecond of delay
1135 07:13:51.519049 => setenv serverip 192.168.6.2
1136 07:13:51.529617 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1137 07:13:51.530191 setenv serverip 192.168.6.2
1138 07:13:51.530670 Sending with 10 millisecond of delay
1140 07:13:55.257121 => tftpboot 0x01080000 742687/tftp-deploy-ut2njev1/kernel/uImage
1141 07:13:55.267719 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1142 07:13:55.268315 tftpboot 0x01080000 742687/tftp-deploy-ut2njev1/kernel/uImage
1143 07:13:55.268564 Speed: 1000, full duplex
1144 07:13:55.268780 Using ethernet@ff3f0000 device
1145 07:13:55.270528 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1146 07:13:55.276171 Filename '742687/tftp-deploy-ut2njev1/kernel/uImage'.
1147 07:13:55.280081 Load address: 0x1080000
1148 07:13:59.833866 Loading: *################################################## 43.6 MiB
1149 07:13:59.834319 9.6 MiB/s
1150 07:13:59.834559 done
1151 07:13:59.837830 Bytes transferred = 45724224 (2b9b240 hex)
1152 07:13:59.838523 Sending with 10 millisecond of delay
1154 07:14:04.532550 => tftpboot 0x08000000 742687/tftp-deploy-ut2njev1/ramdisk/ramdisk.cpio.gz.uboot
1155 07:14:04.543335 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
1156 07:14:04.544180 tftpboot 0x08000000 742687/tftp-deploy-ut2njev1/ramdisk/ramdisk.cpio.gz.uboot
1157 07:14:04.544627 Speed: 1000, full duplex
1158 07:14:04.545027 Using ethernet@ff3f0000 device
1159 07:14:04.546348 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1160 07:14:04.558143 Filename '742687/tftp-deploy-ut2njev1/ramdisk/ramdisk.cpio.gz.uboot'.
1161 07:14:04.558676 Load address: 0x8000000
1162 07:14:06.322246 Loading: *################################################# UDP wrong checksum 00000005 0000cf3f
1163 07:14:11.322249 T UDP wrong checksum 00000005 0000cf3f
1164 07:14:21.324547 T T UDP wrong checksum 00000005 0000cf3f
1165 07:14:41.328246 T T T T UDP wrong checksum 00000005 0000cf3f
1166 07:15:01.333709 T T T
1167 07:15:01.334156 Retry count exceeded; starting again
1169 07:15:01.335031 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
1172 07:15:01.336030 end: 2.4 uboot-commands (duration 00:01:53) [common]
1174 07:15:01.336787 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1176 07:15:01.337354 end: 2 uboot-action (duration 00:01:53) [common]
1178 07:15:01.338179 Cleaning after the job
1179 07:15:01.338510 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742687/tftp-deploy-ut2njev1/ramdisk
1180 07:15:01.339478 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742687/tftp-deploy-ut2njev1/kernel
1181 07:15:01.349109 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742687/tftp-deploy-ut2njev1/dtb
1182 07:15:01.350035 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742687/tftp-deploy-ut2njev1/nfsrootfs
1183 07:15:01.375328 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742687/tftp-deploy-ut2njev1/modules
1184 07:15:01.382031 start: 4.1 power-off (timeout 00:00:30) [common]
1185 07:15:01.382680 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1186 07:15:01.432524 >> OK - accepted request
1187 07:15:01.434631 Returned 0 in 0 seconds
1188 07:15:01.535426 end: 4.1 power-off (duration 00:00:00) [common]
1190 07:15:01.536509 start: 4.2 read-feedback (timeout 00:10:00) [common]
1191 07:15:01.537205 Listened to connection for namespace 'common' for up to 1s
1192 07:15:02.537744 Finalising connection for namespace 'common'
1193 07:15:02.538580 Disconnecting from shell: Finalise
1194 07:15:02.539164 =>
1195 07:15:02.640292 end: 4.2 read-feedback (duration 00:00:01) [common]
1196 07:15:02.640996 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/742687
1197 07:15:04.559172 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/742687
1198 07:15:04.559830 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.