Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:25:07.473393 lava-dispatcher, installed at version: 2024.01
2 07:25:07.474177 start: 0 validate
3 07:25:07.474656 Start time: 2024-09-19 07:25:07.474626+00:00 (UTC)
4 07:25:07.475205 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:25:07.475926 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 07:25:07.511708 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:25:07.512284 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 07:25:07.540813 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:25:07.541423 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 07:25:07.575270 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:25:07.575784 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 07:25:07.608160 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 07:25:07.608629 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 07:25:07.647032 validate duration: 0.17
16 07:25:07.647888 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 07:25:07.648241 start: 1.1 download-retry (timeout 00:10:00) [common]
18 07:25:07.648559 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 07:25:07.649138 Not decompressing ramdisk as can be used compressed.
20 07:25:07.649591 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 07:25:07.649871 saving as /var/lib/lava/dispatcher/tmp/742849/tftp-deploy-06b6wwzt/ramdisk/initrd.cpio.gz
22 07:25:07.650145 total size: 5628182 (5 MB)
23 07:25:07.688289 progress 0 % (0 MB)
24 07:25:07.692360 progress 5 % (0 MB)
25 07:25:07.696649 progress 10 % (0 MB)
26 07:25:07.700400 progress 15 % (0 MB)
27 07:25:07.704577 progress 20 % (1 MB)
28 07:25:07.708333 progress 25 % (1 MB)
29 07:25:07.712509 progress 30 % (1 MB)
30 07:25:07.716759 progress 35 % (1 MB)
31 07:25:07.720497 progress 40 % (2 MB)
32 07:25:07.724579 progress 45 % (2 MB)
33 07:25:07.728292 progress 50 % (2 MB)
34 07:25:07.732758 progress 55 % (2 MB)
35 07:25:07.736894 progress 60 % (3 MB)
36 07:25:07.740679 progress 65 % (3 MB)
37 07:25:07.744821 progress 70 % (3 MB)
38 07:25:07.748529 progress 75 % (4 MB)
39 07:25:07.752647 progress 80 % (4 MB)
40 07:25:07.756412 progress 85 % (4 MB)
41 07:25:07.760488 progress 90 % (4 MB)
42 07:25:07.764282 progress 95 % (5 MB)
43 07:25:07.767627 progress 100 % (5 MB)
44 07:25:07.768307 5 MB downloaded in 0.12 s (45.43 MB/s)
45 07:25:07.768874 end: 1.1.1 http-download (duration 00:00:00) [common]
47 07:25:07.769749 end: 1.1 download-retry (duration 00:00:00) [common]
48 07:25:07.770034 start: 1.2 download-retry (timeout 00:10:00) [common]
49 07:25:07.770299 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 07:25:07.770758 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig/gcc-12/kernel/Image
51 07:25:07.770994 saving as /var/lib/lava/dispatcher/tmp/742849/tftp-deploy-06b6wwzt/kernel/Image
52 07:25:07.771202 total size: 45724160 (43 MB)
53 07:25:07.771409 No compression specified
54 07:25:07.805313 progress 0 % (0 MB)
55 07:25:07.837861 progress 5 % (2 MB)
56 07:25:07.870841 progress 10 % (4 MB)
57 07:25:07.903914 progress 15 % (6 MB)
58 07:25:07.936846 progress 20 % (8 MB)
59 07:25:07.969223 progress 25 % (10 MB)
60 07:25:08.001534 progress 30 % (13 MB)
61 07:25:08.033742 progress 35 % (15 MB)
62 07:25:08.066576 progress 40 % (17 MB)
63 07:25:08.098530 progress 45 % (19 MB)
64 07:25:08.130663 progress 50 % (21 MB)
65 07:25:08.163156 progress 55 % (24 MB)
66 07:25:08.195589 progress 60 % (26 MB)
67 07:25:08.228028 progress 65 % (28 MB)
68 07:25:08.259764 progress 70 % (30 MB)
69 07:25:08.292178 progress 75 % (32 MB)
70 07:25:08.325060 progress 80 % (34 MB)
71 07:25:08.358407 progress 85 % (37 MB)
72 07:25:08.390289 progress 90 % (39 MB)
73 07:25:08.422307 progress 95 % (41 MB)
74 07:25:08.453859 progress 100 % (43 MB)
75 07:25:08.454522 43 MB downloaded in 0.68 s (63.82 MB/s)
76 07:25:08.455075 end: 1.2.1 http-download (duration 00:00:01) [common]
78 07:25:08.456070 end: 1.2 download-retry (duration 00:00:01) [common]
79 07:25:08.456405 start: 1.3 download-retry (timeout 00:09:59) [common]
80 07:25:08.456715 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 07:25:08.457223 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 07:25:08.457511 saving as /var/lib/lava/dispatcher/tmp/742849/tftp-deploy-06b6wwzt/dtb/meson-g12b-a311d-libretech-cc.dtb
83 07:25:08.457759 total size: 54703 (0 MB)
84 07:25:08.458007 No compression specified
85 07:25:08.498675 progress 59 % (0 MB)
86 07:25:08.499654 progress 100 % (0 MB)
87 07:25:08.500389 0 MB downloaded in 0.04 s (1.22 MB/s)
88 07:25:08.500973 end: 1.3.1 http-download (duration 00:00:00) [common]
90 07:25:08.501962 end: 1.3 download-retry (duration 00:00:00) [common]
91 07:25:08.502339 start: 1.4 download-retry (timeout 00:09:59) [common]
92 07:25:08.502678 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 07:25:08.503242 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 07:25:08.503552 saving as /var/lib/lava/dispatcher/tmp/742849/tftp-deploy-06b6wwzt/nfsrootfs/full.rootfs.tar
95 07:25:08.503821 total size: 107552908 (102 MB)
96 07:25:08.504063 Using unxz to decompress xz
97 07:25:08.542122 progress 0 % (0 MB)
98 07:25:09.191104 progress 5 % (5 MB)
99 07:25:09.911923 progress 10 % (10 MB)
100 07:25:10.660118 progress 15 % (15 MB)
101 07:25:11.433629 progress 20 % (20 MB)
102 07:25:12.002716 progress 25 % (25 MB)
103 07:25:12.627332 progress 30 % (30 MB)
104 07:25:13.368439 progress 35 % (35 MB)
105 07:25:13.726007 progress 40 % (41 MB)
106 07:25:14.151081 progress 45 % (46 MB)
107 07:25:14.850350 progress 50 % (51 MB)
108 07:25:15.548962 progress 55 % (56 MB)
109 07:25:16.310559 progress 60 % (61 MB)
110 07:25:17.067599 progress 65 % (66 MB)
111 07:25:17.809693 progress 70 % (71 MB)
112 07:25:18.589303 progress 75 % (76 MB)
113 07:25:19.312206 progress 80 % (82 MB)
114 07:25:20.061670 progress 85 % (87 MB)
115 07:25:20.808886 progress 90 % (92 MB)
116 07:25:21.523719 progress 95 % (97 MB)
117 07:25:22.269150 progress 100 % (102 MB)
118 07:25:22.282203 102 MB downloaded in 13.78 s (7.44 MB/s)
119 07:25:22.283094 end: 1.4.1 http-download (duration 00:00:14) [common]
121 07:25:22.284757 end: 1.4 download-retry (duration 00:00:14) [common]
122 07:25:22.285281 start: 1.5 download-retry (timeout 00:09:45) [common]
123 07:25:22.285793 start: 1.5.1 http-download (timeout 00:09:45) [common]
124 07:25:22.286619 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig/gcc-12/modules.tar.xz
125 07:25:22.287087 saving as /var/lib/lava/dispatcher/tmp/742849/tftp-deploy-06b6wwzt/modules/modules.tar
126 07:25:22.287490 total size: 11604668 (11 MB)
127 07:25:22.287907 Using unxz to decompress xz
128 07:25:22.325962 progress 0 % (0 MB)
129 07:25:22.392739 progress 5 % (0 MB)
130 07:25:22.478994 progress 10 % (1 MB)
131 07:25:22.567099 progress 15 % (1 MB)
132 07:25:22.648809 progress 20 % (2 MB)
133 07:25:22.728119 progress 25 % (2 MB)
134 07:25:22.812640 progress 30 % (3 MB)
135 07:25:22.885619 progress 35 % (3 MB)
136 07:25:22.965264 progress 40 % (4 MB)
137 07:25:23.047872 progress 45 % (5 MB)
138 07:25:23.128902 progress 50 % (5 MB)
139 07:25:23.209890 progress 55 % (6 MB)
140 07:25:23.288865 progress 60 % (6 MB)
141 07:25:23.374365 progress 65 % (7 MB)
142 07:25:23.449887 progress 70 % (7 MB)
143 07:25:23.533518 progress 75 % (8 MB)
144 07:25:23.629095 progress 80 % (8 MB)
145 07:25:23.727556 progress 85 % (9 MB)
146 07:25:23.797585 progress 90 % (9 MB)
147 07:25:23.877450 progress 95 % (10 MB)
148 07:25:23.953727 progress 100 % (11 MB)
149 07:25:23.966231 11 MB downloaded in 1.68 s (6.59 MB/s)
150 07:25:23.967130 end: 1.5.1 http-download (duration 00:00:02) [common]
152 07:25:23.968779 end: 1.5 download-retry (duration 00:00:02) [common]
153 07:25:23.969303 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 07:25:23.969821 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 07:25:34.454298 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/742849/extract-nfsrootfs-d9kh4kts
156 07:25:34.454910 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 07:25:34.455246 start: 1.6.2 lava-overlay (timeout 00:09:33) [common]
158 07:25:34.456077 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd
159 07:25:34.456570 makedir: /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin
160 07:25:34.456930 makedir: /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/tests
161 07:25:34.457316 makedir: /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/results
162 07:25:34.457676 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-add-keys
163 07:25:34.458230 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-add-sources
164 07:25:34.458783 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-background-process-start
165 07:25:34.460027 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-background-process-stop
166 07:25:34.460653 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-common-functions
167 07:25:34.461178 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-echo-ipv4
168 07:25:34.461690 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-install-packages
169 07:25:34.462260 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-installed-packages
170 07:25:34.462832 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-os-build
171 07:25:34.463335 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-probe-channel
172 07:25:34.463890 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-probe-ip
173 07:25:34.464495 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-target-ip
174 07:25:34.465025 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-target-mac
175 07:25:34.465566 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-target-storage
176 07:25:34.466123 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-test-case
177 07:25:34.466668 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-test-event
178 07:25:34.467381 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-test-feedback
179 07:25:34.468009 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-test-raise
180 07:25:34.468614 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-test-reference
181 07:25:34.469206 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-test-runner
182 07:25:34.469783 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-test-set
183 07:25:34.470375 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-test-shell
184 07:25:34.470994 Updating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-install-packages (oe)
185 07:25:34.471665 Updating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/bin/lava-installed-packages (oe)
186 07:25:34.472235 Creating /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/environment
187 07:25:34.472689 LAVA metadata
188 07:25:34.473000 - LAVA_JOB_ID=742849
189 07:25:34.473255 - LAVA_DISPATCHER_IP=192.168.6.2
190 07:25:34.473703 start: 1.6.2.1 ssh-authorize (timeout 00:09:33) [common]
191 07:25:34.474946 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 07:25:34.475329 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:33) [common]
193 07:25:34.475590 skipped lava-vland-overlay
194 07:25:34.475891 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 07:25:34.476238 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:33) [common]
196 07:25:34.476499 skipped lava-multinode-overlay
197 07:25:34.476796 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 07:25:34.477111 start: 1.6.2.4 test-definition (timeout 00:09:33) [common]
199 07:25:34.477410 Loading test definitions
200 07:25:34.477735 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:33) [common]
201 07:25:34.477985 Using /lava-742849 at stage 0
202 07:25:34.479313 uuid=742849_1.6.2.4.1 testdef=None
203 07:25:34.479666 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 07:25:34.479964 start: 1.6.2.4.2 test-overlay (timeout 00:09:33) [common]
205 07:25:34.482035 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 07:25:34.482887 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:33) [common]
208 07:25:34.485463 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 07:25:34.486372 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:33) [common]
211 07:25:34.488911 runner path: /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/0/tests/0_dmesg test_uuid 742849_1.6.2.4.1
212 07:25:34.489573 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 07:25:34.490388 Creating lava-test-runner.conf files
215 07:25:34.490611 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/742849/lava-overlay-tcycrxmd/lava-742849/0 for stage 0
216 07:25:34.491009 - 0_dmesg
217 07:25:34.491416 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 07:25:34.491729 start: 1.6.2.5 compress-overlay (timeout 00:09:33) [common]
219 07:25:34.513755 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 07:25:34.514198 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:33) [common]
221 07:25:34.514464 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 07:25:34.514738 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 07:25:34.515002 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
224 07:25:35.219357 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 07:25:35.219805 start: 1.6.4 extract-modules (timeout 00:09:32) [common]
226 07:25:35.220122 extracting modules file /var/lib/lava/dispatcher/tmp/742849/tftp-deploy-06b6wwzt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/742849/extract-nfsrootfs-d9kh4kts
227 07:25:36.715525 extracting modules file /var/lib/lava/dispatcher/tmp/742849/tftp-deploy-06b6wwzt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/742849/extract-overlay-ramdisk-8ees8ksj/ramdisk
228 07:25:38.301626 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 07:25:38.302119 start: 1.6.5 apply-overlay-tftp (timeout 00:09:29) [common]
230 07:25:38.302404 [common] Applying overlay to NFS
231 07:25:38.302628 [common] Applying overlay /var/lib/lava/dispatcher/tmp/742849/compress-overlay-7_zpneba/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/742849/extract-nfsrootfs-d9kh4kts
232 07:25:38.337829 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 07:25:38.338290 start: 1.6.6 prepare-kernel (timeout 00:09:29) [common]
234 07:25:38.338603 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:29) [common]
235 07:25:38.338879 Converting downloaded kernel to a uImage
236 07:25:38.339223 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/742849/tftp-deploy-06b6wwzt/kernel/Image /var/lib/lava/dispatcher/tmp/742849/tftp-deploy-06b6wwzt/kernel/uImage
237 07:25:38.887301 output: Image Name:
238 07:25:38.887753 output: Created: Thu Sep 19 07:25:38 2024
239 07:25:38.887972 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 07:25:38.888232 output: Data Size: 45724160 Bytes = 44652.50 KiB = 43.61 MiB
241 07:25:38.888443 output: Load Address: 01080000
242 07:25:38.888649 output: Entry Point: 01080000
243 07:25:38.888856 output:
244 07:25:38.889233 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 07:25:38.889514 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 07:25:38.889791 start: 1.6.7 configure-preseed-file (timeout 00:09:29) [common]
247 07:25:38.890052 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 07:25:38.890318 start: 1.6.8 compress-ramdisk (timeout 00:09:29) [common]
249 07:25:38.890581 Building ramdisk /var/lib/lava/dispatcher/tmp/742849/extract-overlay-ramdisk-8ees8ksj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/742849/extract-overlay-ramdisk-8ees8ksj/ramdisk
250 07:25:41.108869 >> 166871 blocks
251 07:25:49.359255 Adding RAMdisk u-boot header.
252 07:25:49.359708 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/742849/extract-overlay-ramdisk-8ees8ksj/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/742849/extract-overlay-ramdisk-8ees8ksj/ramdisk.cpio.gz.uboot
253 07:25:49.609219 output: Image Name:
254 07:25:49.609641 output: Created: Thu Sep 19 07:25:49 2024
255 07:25:49.609857 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 07:25:49.610065 output: Data Size: 23440791 Bytes = 22891.40 KiB = 22.35 MiB
257 07:25:49.610268 output: Load Address: 00000000
258 07:25:49.610469 output: Entry Point: 00000000
259 07:25:49.610665 output:
260 07:25:49.611268 rename /var/lib/lava/dispatcher/tmp/742849/extract-overlay-ramdisk-8ees8ksj/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/742849/tftp-deploy-06b6wwzt/ramdisk/ramdisk.cpio.gz.uboot
261 07:25:49.611702 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 07:25:49.612036 end: 1.6 prepare-tftp-overlay (duration 00:00:26) [common]
263 07:25:49.612605 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
264 07:25:49.613068 No LXC device requested
265 07:25:49.613570 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 07:25:49.614081 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
267 07:25:49.614575 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 07:25:49.614987 Checking files for TFTP limit of 4294967296 bytes.
269 07:25:49.617758 end: 1 tftp-deploy (duration 00:00:42) [common]
270 07:25:49.618368 start: 2 uboot-action (timeout 00:05:00) [common]
271 07:25:49.618899 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 07:25:49.619397 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 07:25:49.619901 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 07:25:49.620470 Using kernel file from prepare-kernel: 742849/tftp-deploy-06b6wwzt/kernel/uImage
275 07:25:49.621104 substitutions:
276 07:25:49.621508 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 07:25:49.621914 - {DTB_ADDR}: 0x01070000
278 07:25:49.622311 - {DTB}: 742849/tftp-deploy-06b6wwzt/dtb/meson-g12b-a311d-libretech-cc.dtb
279 07:25:49.622707 - {INITRD}: 742849/tftp-deploy-06b6wwzt/ramdisk/ramdisk.cpio.gz.uboot
280 07:25:49.623106 - {KERNEL_ADDR}: 0x01080000
281 07:25:49.623499 - {KERNEL}: 742849/tftp-deploy-06b6wwzt/kernel/uImage
282 07:25:49.623889 - {LAVA_MAC}: None
283 07:25:49.624366 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/742849/extract-nfsrootfs-d9kh4kts
284 07:25:49.624772 - {NFS_SERVER_IP}: 192.168.6.2
285 07:25:49.625161 - {PRESEED_CONFIG}: None
286 07:25:49.625548 - {PRESEED_LOCAL}: None
287 07:25:49.625933 - {RAMDISK_ADDR}: 0x08000000
288 07:25:49.626317 - {RAMDISK}: 742849/tftp-deploy-06b6wwzt/ramdisk/ramdisk.cpio.gz.uboot
289 07:25:49.626701 - {ROOT_PART}: None
290 07:25:49.627088 - {ROOT}: None
291 07:25:49.627478 - {SERVER_IP}: 192.168.6.2
292 07:25:49.627867 - {TEE_ADDR}: 0x83000000
293 07:25:49.628287 - {TEE}: None
294 07:25:49.628682 Parsed boot commands:
295 07:25:49.629064 - setenv autoload no
296 07:25:49.629450 - setenv initrd_high 0xffffffff
297 07:25:49.629836 - setenv fdt_high 0xffffffff
298 07:25:49.630218 - dhcp
299 07:25:49.630597 - setenv serverip 192.168.6.2
300 07:25:49.630979 - tftpboot 0x01080000 742849/tftp-deploy-06b6wwzt/kernel/uImage
301 07:25:49.631365 - tftpboot 0x08000000 742849/tftp-deploy-06b6wwzt/ramdisk/ramdisk.cpio.gz.uboot
302 07:25:49.631751 - tftpboot 0x01070000 742849/tftp-deploy-06b6wwzt/dtb/meson-g12b-a311d-libretech-cc.dtb
303 07:25:49.632164 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/742849/extract-nfsrootfs-d9kh4kts,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 07:25:49.632567 - bootm 0x01080000 0x08000000 0x01070000
305 07:25:49.633081 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 07:25:49.634569 start: 2.3 connect-device (timeout 00:05:00) [common]
308 07:25:49.634986 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 07:25:49.651575 Setting prompt string to ['lava-test: # ']
310 07:25:49.653120 end: 2.3 connect-device (duration 00:00:00) [common]
311 07:25:49.653719 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 07:25:49.654303 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 07:25:49.654846 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 07:25:49.656258 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 07:25:49.690567 >> OK - accepted request
316 07:25:49.692561 Returned 0 in 0 seconds
317 07:25:49.793710 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 07:25:49.794702 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 07:25:49.795024 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 07:25:49.795313 Setting prompt string to ['Hit any key to stop autoboot']
322 07:25:49.795561 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 07:25:49.796560 Trying 192.168.56.21...
324 07:25:49.796846 Connected to conserv1.
325 07:25:49.797066 Escape character is '^]'.
326 07:25:49.797285
327 07:25:49.797505 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 07:25:49.797720
329 07:26:01.486404 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 07:26:01.486842 bl2_stage_init 0x01
331 07:26:01.487070 bl2_stage_init 0x81
332 07:26:01.491928 hw id: 0x0000 - pwm id 0x01
333 07:26:01.492256 bl2_stage_init 0xc1
334 07:26:01.492472 bl2_stage_init 0x02
335 07:26:01.492679
336 07:26:01.497406 L0:00000000
337 07:26:01.497697 L1:20000703
338 07:26:01.497919 L2:00008067
339 07:26:01.498134 L3:14000000
340 07:26:01.500324 B2:00402000
341 07:26:01.500594 B1:e0f83180
342 07:26:01.500818
343 07:26:01.501029 TE: 58159
344 07:26:01.501236
345 07:26:01.511352 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 07:26:01.511661
347 07:26:01.511876 Board ID = 1
348 07:26:01.512119 Set A53 clk to 24M
349 07:26:01.512331 Set A73 clk to 24M
350 07:26:01.517059 Set clk81 to 24M
351 07:26:01.517349 A53 clk: 1200 MHz
352 07:26:01.517562 A73 clk: 1200 MHz
353 07:26:01.522567 CLK81: 166.6M
354 07:26:01.522851 smccc: 00012ab4
355 07:26:01.528206 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 07:26:01.528496 board id: 1
357 07:26:01.536903 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 07:26:01.547430 fw parse done
359 07:26:01.553380 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 07:26:01.596062 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 07:26:01.606948 PIEI prepare done
362 07:26:01.607263 fastboot data load
363 07:26:01.607484 fastboot data verify
364 07:26:01.612666 verify result: 266
365 07:26:01.618206 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 07:26:01.618517 LPDDR4 probe
367 07:26:01.618735 ddr clk to 1584MHz
368 07:26:01.626178 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 07:26:01.663440
370 07:26:01.663823 dmc_version 0001
371 07:26:01.670092 Check phy result
372 07:26:01.675976 INFO : End of CA training
373 07:26:01.676305 INFO : End of initialization
374 07:26:01.681645 INFO : Training has run successfully!
375 07:26:01.681937 Check phy result
376 07:26:01.687132 INFO : End of initialization
377 07:26:01.687425 INFO : End of read enable training
378 07:26:01.692894 INFO : End of fine write leveling
379 07:26:01.698329 INFO : End of Write leveling coarse delay
380 07:26:01.698624 INFO : Training has run successfully!
381 07:26:01.698841 Check phy result
382 07:26:01.703967 INFO : End of initialization
383 07:26:01.704294 INFO : End of read dq deskew training
384 07:26:01.709649 INFO : End of MPR read delay center optimization
385 07:26:01.715159 INFO : End of write delay center optimization
386 07:26:01.720887 INFO : End of read delay center optimization
387 07:26:01.721218 INFO : End of max read latency training
388 07:26:01.726334 INFO : Training has run successfully!
389 07:26:01.726640 1D training succeed
390 07:26:01.735593 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 07:26:01.783181 Check phy result
392 07:26:01.783575 INFO : End of initialization
393 07:26:01.805363 INFO : End of 2D read delay Voltage center optimization
394 07:26:01.825828 INFO : End of 2D read delay Voltage center optimization
395 07:26:01.877765 INFO : End of 2D write delay Voltage center optimization
396 07:26:01.926968 INFO : End of 2D write delay Voltage center optimization
397 07:26:01.932462 INFO : Training has run successfully!
398 07:26:01.932813
399 07:26:01.933043 channel==0
400 07:26:01.937986 RxClkDly_Margin_A0==88 ps 9
401 07:26:01.938339 TxDqDly_Margin_A0==98 ps 10
402 07:26:01.941341 RxClkDly_Margin_A1==88 ps 9
403 07:26:01.941668 TxDqDly_Margin_A1==98 ps 10
404 07:26:01.946959 TrainedVREFDQ_A0==74
405 07:26:01.947303 TrainedVREFDQ_A1==74
406 07:26:01.952463 VrefDac_Margin_A0==25
407 07:26:01.952801 DeviceVref_Margin_A0==40
408 07:26:01.953021 VrefDac_Margin_A1==24
409 07:26:01.958090 DeviceVref_Margin_A1==40
410 07:26:01.958438
411 07:26:01.958669
412 07:26:01.958884 channel==1
413 07:26:01.959093 RxClkDly_Margin_A0==98 ps 10
414 07:26:01.963729 TxDqDly_Margin_A0==98 ps 10
415 07:26:01.964089 RxClkDly_Margin_A1==98 ps 10
416 07:26:01.969288 TxDqDly_Margin_A1==88 ps 9
417 07:26:01.969625 TrainedVREFDQ_A0==77
418 07:26:01.969843 TrainedVREFDQ_A1==77
419 07:26:01.974953 VrefDac_Margin_A0==22
420 07:26:01.975288 DeviceVref_Margin_A0==37
421 07:26:01.980375 VrefDac_Margin_A1==22
422 07:26:01.980702 DeviceVref_Margin_A1==37
423 07:26:01.980919
424 07:26:01.986081 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 07:26:01.986418
426 07:26:02.014033 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000018 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
427 07:26:02.019782 2D training succeed
428 07:26:02.025112 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 07:26:02.025459 auto size-- 65535DDR cs0 size: 2048MB
430 07:26:02.030816 DDR cs1 size: 2048MB
431 07:26:02.031139 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 07:26:02.036321 cs0 DataBus test pass
433 07:26:02.036649 cs1 DataBus test pass
434 07:26:02.036873 cs0 AddrBus test pass
435 07:26:02.041946 cs1 AddrBus test pass
436 07:26:02.042249
437 07:26:02.042471 100bdlr_step_size ps== 420
438 07:26:02.042685 result report
439 07:26:02.047587 boot times 0Enable ddr reg access
440 07:26:02.055399 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 07:26:02.068905 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 07:26:02.640762 0.0;M3 CHK:0;cm4_sp_mode 0
443 07:26:02.641189 MVN_1=0x00000000
444 07:26:02.646295 MVN_2=0x00000000
445 07:26:02.652119 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 07:26:02.652502 OPS=0x10
447 07:26:02.652711 ring efuse init
448 07:26:02.652927 chipver efuse init
449 07:26:02.657610 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 07:26:02.663269 [0.018961 Inits done]
451 07:26:02.663637 secure task start!
452 07:26:02.663861 high task start!
453 07:26:02.666867 low task start!
454 07:26:02.667193 run into bl31
455 07:26:02.674476 NOTICE: BL31: v1.3(release):4fc40b1
456 07:26:02.682288 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 07:26:02.682685 NOTICE: BL31: G12A normal boot!
458 07:26:02.707691 NOTICE: BL31: BL33 decompress pass
459 07:26:02.712317 ERROR: Error initializing runtime service opteed_fast
460 07:26:03.946244
461 07:26:03.946731
462 07:26:03.954722 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 07:26:03.955377
464 07:26:03.955775 Model: Libre Computer AML-A311D-CC Alta
465 07:26:04.163026 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 07:26:04.186616 DRAM: 2 GiB (effective 3.8 GiB)
467 07:26:04.329494 Core: 408 devices, 31 uclasses, devicetree: separate
468 07:26:04.335258 WDT: Not starting watchdog@f0d0
469 07:26:04.367515 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 07:26:04.379942 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 07:26:04.384958 ** Bad device specification mmc 0 **
472 07:26:04.395312 Card did not respond to voltage select! : -110
473 07:26:04.402937 ** Bad device specification mmc 0 **
474 07:26:04.403322 Couldn't find partition mmc 0
475 07:26:04.411282 Card did not respond to voltage select! : -110
476 07:26:04.416836 ** Bad device specification mmc 0 **
477 07:26:04.417423 Couldn't find partition mmc 0
478 07:26:04.421848 Error: could not access storage.
479 07:26:05.686968 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 07:26:05.687440 bl2_stage_init 0x01
481 07:26:05.688076 bl2_stage_init 0x81
482 07:26:05.692330 hw id: 0x0000 - pwm id 0x01
483 07:26:05.692846 bl2_stage_init 0xc1
484 07:26:05.693311 bl2_stage_init 0x02
485 07:26:05.693765
486 07:26:05.697731 L0:00000000
487 07:26:05.698219 L1:20000703
488 07:26:05.698675 L2:00008067
489 07:26:05.699123 L3:14000000
490 07:26:05.703349 B2:00402000
491 07:26:05.703836 B1:e0f83180
492 07:26:05.704326
493 07:26:05.704778 TE: 58167
494 07:26:05.705226
495 07:26:05.708910 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 07:26:05.709427
497 07:26:05.709884 Board ID = 1
498 07:26:05.714521 Set A53 clk to 24M
499 07:26:05.715013 Set A73 clk to 24M
500 07:26:05.715468 Set clk81 to 24M
501 07:26:05.720299 A53 clk: 1200 MHz
502 07:26:05.720815 A73 clk: 1200 MHz
503 07:26:05.721282 CLK81: 166.6M
504 07:26:05.721738 smccc: 00012abe
505 07:26:05.725735 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 07:26:05.731311 board id: 1
507 07:26:05.737324 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 07:26:05.747869 fw parse done
509 07:26:05.753795 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 07:26:05.796465 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 07:26:05.807483 PIEI prepare done
512 07:26:05.808116 fastboot data load
513 07:26:05.808616 fastboot data verify
514 07:26:05.813133 verify result: 266
515 07:26:05.818635 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 07:26:05.819154 LPDDR4 probe
517 07:26:05.819618 ddr clk to 1584MHz
518 07:26:05.826616 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 07:26:05.863931
520 07:26:05.864621 dmc_version 0001
521 07:26:05.870538 Check phy result
522 07:26:05.876361 INFO : End of CA training
523 07:26:05.876874 INFO : End of initialization
524 07:26:05.881927 INFO : Training has run successfully!
525 07:26:05.882417 Check phy result
526 07:26:05.887621 INFO : End of initialization
527 07:26:05.888256 INFO : End of read enable training
528 07:26:05.893146 INFO : End of fine write leveling
529 07:26:05.898752 INFO : End of Write leveling coarse delay
530 07:26:05.899247 INFO : Training has run successfully!
531 07:26:05.899707 Check phy result
532 07:26:05.904366 INFO : End of initialization
533 07:26:05.904862 INFO : End of read dq deskew training
534 07:26:05.909969 INFO : End of MPR read delay center optimization
535 07:26:05.915559 INFO : End of write delay center optimization
536 07:26:05.921196 INFO : End of read delay center optimization
537 07:26:05.921696 INFO : End of max read latency training
538 07:26:05.926768 INFO : Training has run successfully!
539 07:26:05.927265 1D training succeed
540 07:26:05.935972 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 07:26:05.983610 Check phy result
542 07:26:05.984226 INFO : End of initialization
543 07:26:06.006068 INFO : End of 2D read delay Voltage center optimization
544 07:26:06.026142 INFO : End of 2D read delay Voltage center optimization
545 07:26:06.078096 INFO : End of 2D write delay Voltage center optimization
546 07:26:06.127350 INFO : End of 2D write delay Voltage center optimization
547 07:26:06.132823 INFO : Training has run successfully!
548 07:26:06.133337
549 07:26:06.133816 channel==0
550 07:26:06.138405 RxClkDly_Margin_A0==88 ps 9
551 07:26:06.138969 TxDqDly_Margin_A0==98 ps 10
552 07:26:06.144046 RxClkDly_Margin_A1==88 ps 9
553 07:26:06.144557 TxDqDly_Margin_A1==88 ps 9
554 07:26:06.145017 TrainedVREFDQ_A0==74
555 07:26:06.149618 TrainedVREFDQ_A1==74
556 07:26:06.150130 VrefDac_Margin_A0==25
557 07:26:06.150581 DeviceVref_Margin_A0==40
558 07:26:06.155174 VrefDac_Margin_A1==24
559 07:26:06.155668 DeviceVref_Margin_A1==40
560 07:26:06.156160
561 07:26:06.156613
562 07:26:06.157057 channel==1
563 07:26:06.160828 RxClkDly_Margin_A0==98 ps 10
564 07:26:06.161322 TxDqDly_Margin_A0==98 ps 10
565 07:26:06.166392 RxClkDly_Margin_A1==98 ps 10
566 07:26:06.166896 TxDqDly_Margin_A1==88 ps 9
567 07:26:06.172005 TrainedVREFDQ_A0==77
568 07:26:06.172504 TrainedVREFDQ_A1==77
569 07:26:06.172953 VrefDac_Margin_A0==22
570 07:26:06.177588 DeviceVref_Margin_A0==37
571 07:26:06.178073 VrefDac_Margin_A1==22
572 07:26:06.183186 DeviceVref_Margin_A1==37
573 07:26:06.183733
574 07:26:06.184244 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 07:26:06.184703
576 07:26:06.216787 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
577 07:26:06.217422 2D training succeed
578 07:26:06.222409 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 07:26:06.228029 auto size-- 65535DDR cs0 size: 2048MB
580 07:26:06.228601 DDR cs1 size: 2048MB
581 07:26:06.233588 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 07:26:06.234088 cs0 DataBus test pass
583 07:26:06.239173 cs1 DataBus test pass
584 07:26:06.239671 cs0 AddrBus test pass
585 07:26:06.240159 cs1 AddrBus test pass
586 07:26:06.240611
587 07:26:06.244768 100bdlr_step_size ps== 420
588 07:26:06.245289 result report
589 07:26:06.250435 boot times 0Enable ddr reg access
590 07:26:06.255734 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 07:26:06.269182 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 07:26:06.841212 0.0;M3 CHK:0;cm4_sp_mode 0
593 07:26:06.841890 MVN_1=0x00000000
594 07:26:06.846711 MVN_2=0x00000000
595 07:26:06.852515 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 07:26:06.853082 OPS=0x10
597 07:26:06.853569 ring efuse init
598 07:26:06.854063 chipver efuse init
599 07:26:06.860784 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 07:26:06.861361 [0.018960 Inits done]
601 07:26:06.861803 secure task start!
602 07:26:06.868240 high task start!
603 07:26:06.868721 low task start!
604 07:26:06.869155 run into bl31
605 07:26:06.874913 NOTICE: BL31: v1.3(release):4fc40b1
606 07:26:06.882710 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 07:26:06.883199 NOTICE: BL31: G12A normal boot!
608 07:26:06.908179 NOTICE: BL31: BL33 decompress pass
609 07:26:06.913742 ERROR: Error initializing runtime service opteed_fast
610 07:26:08.146789
611 07:26:08.147183
612 07:26:08.155081 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 07:26:08.155517
614 07:26:08.155846 Model: Libre Computer AML-A311D-CC Alta
615 07:26:08.363576 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 07:26:08.386963 DRAM: 2 GiB (effective 3.8 GiB)
617 07:26:08.529986 Core: 408 devices, 31 uclasses, devicetree: separate
618 07:26:08.535882 WDT: Not starting watchdog@f0d0
619 07:26:08.568325 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 07:26:08.580538 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 07:26:08.585498 ** Bad device specification mmc 0 **
622 07:26:08.595872 Card did not respond to voltage select! : -110
623 07:26:08.602745 ** Bad device specification mmc 0 **
624 07:26:08.603081 Couldn't find partition mmc 0
625 07:26:08.611868 Card did not respond to voltage select! : -110
626 07:26:08.617480 ** Bad device specification mmc 0 **
627 07:26:08.617783 Couldn't find partition mmc 0
628 07:26:08.621453 Error: could not access storage.
629 07:26:08.964185 Net: eth0: ethernet@ff3f0000
630 07:26:08.964743 starting USB...
631 07:26:09.216995 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 07:26:09.217418 Starting the controller
633 07:26:09.223931 USB XHCI 1.10
634 07:26:10.935195 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 07:26:10.935775 bl2_stage_init 0x01
636 07:26:10.936100 bl2_stage_init 0x81
637 07:26:10.940770 hw id: 0x0000 - pwm id 0x01
638 07:26:10.941298 bl2_stage_init 0xc1
639 07:26:10.941546 bl2_stage_init 0x02
640 07:26:10.941781
641 07:26:10.946305 L0:00000000
642 07:26:10.946810 L1:20000703
643 07:26:10.947189 L2:00008067
644 07:26:10.947448 L3:14000000
645 07:26:10.949180 B2:00402000
646 07:26:10.949615 B1:e0f83180
647 07:26:10.949928
648 07:26:10.950251 TE: 58124
649 07:26:10.950489
650 07:26:10.960322 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 07:26:10.960695
652 07:26:10.960914 Board ID = 1
653 07:26:10.961121 Set A53 clk to 24M
654 07:26:10.961325 Set A73 clk to 24M
655 07:26:10.966063 Set clk81 to 24M
656 07:26:10.966578 A53 clk: 1200 MHz
657 07:26:10.966927 A73 clk: 1200 MHz
658 07:26:10.969306 CLK81: 166.6M
659 07:26:10.969775 smccc: 00012a92
660 07:26:10.974894 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 07:26:10.980400 board id: 1
662 07:26:10.984830 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 07:26:10.996460 fw parse done
664 07:26:11.002412 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 07:26:11.045071 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 07:26:11.056156 PIEI prepare done
667 07:26:11.056471 fastboot data load
668 07:26:11.056689 fastboot data verify
669 07:26:11.061459 verify result: 266
670 07:26:11.067030 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 07:26:11.067436 LPDDR4 probe
672 07:26:11.067781 ddr clk to 1584MHz
673 07:26:11.075218 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 07:26:11.112644
675 07:26:11.113071 dmc_version 0001
676 07:26:11.119137 Check phy result
677 07:26:11.124843 INFO : End of CA training
678 07:26:11.125278 INFO : End of initialization
679 07:26:11.130421 INFO : Training has run successfully!
680 07:26:11.130738 Check phy result
681 07:26:11.136149 INFO : End of initialization
682 07:26:11.136466 INFO : End of read enable training
683 07:26:11.141661 INFO : End of fine write leveling
684 07:26:11.147330 INFO : End of Write leveling coarse delay
685 07:26:11.147779 INFO : Training has run successfully!
686 07:26:11.148048 Check phy result
687 07:26:11.152911 INFO : End of initialization
688 07:26:11.153233 INFO : End of read dq deskew training
689 07:26:11.158426 INFO : End of MPR read delay center optimization
690 07:26:11.164186 INFO : End of write delay center optimization
691 07:26:11.169667 INFO : End of read delay center optimization
692 07:26:11.170136 INFO : End of max read latency training
693 07:26:11.175352 INFO : Training has run successfully!
694 07:26:11.175675 1D training succeed
695 07:26:11.184500 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 07:26:11.232257 Check phy result
697 07:26:11.232841 INFO : End of initialization
698 07:26:11.253827 INFO : End of 2D read delay Voltage center optimization
699 07:26:11.273226 INFO : End of 2D read delay Voltage center optimization
700 07:26:11.325303 INFO : End of 2D write delay Voltage center optimization
701 07:26:11.374643 INFO : End of 2D write delay Voltage center optimization
702 07:26:11.380159 INFO : Training has run successfully!
703 07:26:11.380682
704 07:26:11.381154 channel==0
705 07:26:11.385760 RxClkDly_Margin_A0==88 ps 9
706 07:26:11.386286 TxDqDly_Margin_A0==98 ps 10
707 07:26:11.389079 RxClkDly_Margin_A1==88 ps 9
708 07:26:11.389588 TxDqDly_Margin_A1==98 ps 10
709 07:26:11.394630 TrainedVREFDQ_A0==74
710 07:26:11.395129 TrainedVREFDQ_A1==74
711 07:26:11.395591 VrefDac_Margin_A0==25
712 07:26:11.400234 DeviceVref_Margin_A0==40
713 07:26:11.400741 VrefDac_Margin_A1==25
714 07:26:11.405879 DeviceVref_Margin_A1==40
715 07:26:11.406367
716 07:26:11.406831
717 07:26:11.407282 channel==1
718 07:26:11.407724 RxClkDly_Margin_A0==88 ps 9
719 07:26:11.411426 TxDqDly_Margin_A0==98 ps 10
720 07:26:11.411929 RxClkDly_Margin_A1==88 ps 9
721 07:26:11.417071 TxDqDly_Margin_A1==98 ps 10
722 07:26:11.417568 TrainedVREFDQ_A0==77
723 07:26:11.418027 TrainedVREFDQ_A1==78
724 07:26:11.422640 VrefDac_Margin_A0==23
725 07:26:11.423143 DeviceVref_Margin_A0==37
726 07:26:11.428283 VrefDac_Margin_A1==24
727 07:26:11.428775 DeviceVref_Margin_A1==36
728 07:26:11.429226
729 07:26:11.433877 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 07:26:11.434382
731 07:26:11.461869 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
732 07:26:11.467518 2D training succeed
733 07:26:11.473074 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 07:26:11.473578 auto size-- 65535DDR cs0 size: 2048MB
735 07:26:11.478643 DDR cs1 size: 2048MB
736 07:26:11.479141 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 07:26:11.484250 cs0 DataBus test pass
738 07:26:11.484742 cs1 DataBus test pass
739 07:26:11.485188 cs0 AddrBus test pass
740 07:26:11.489883 cs1 AddrBus test pass
741 07:26:11.490378
742 07:26:11.490841 100bdlr_step_size ps== 420
743 07:26:11.491299 result report
744 07:26:11.495450 boot times 0Enable ddr reg access
745 07:26:11.503168 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 07:26:11.516638 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 07:26:12.090398 0.0;M3 CHK:0;cm4_sp_mode 0
748 07:26:12.091057 MVN_1=0x00000000
749 07:26:12.095828 MVN_2=0x00000000
750 07:26:12.101564 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 07:26:12.102109 OPS=0x10
752 07:26:12.102550 ring efuse init
753 07:26:12.102982 chipver efuse init
754 07:26:12.107162 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 07:26:12.112751 [0.018960 Inits done]
756 07:26:12.113247 secure task start!
757 07:26:12.113678 high task start!
758 07:26:12.116386 low task start!
759 07:26:12.116859 run into bl31
760 07:26:12.124005 NOTICE: BL31: v1.3(release):4fc40b1
761 07:26:12.131761 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 07:26:12.132292 NOTICE: BL31: G12A normal boot!
763 07:26:12.157205 NOTICE: BL31: BL33 decompress pass
764 07:26:12.162974 ERROR: Error initializing runtime service opteed_fast
765 07:26:13.395754
766 07:26:13.396473
767 07:26:13.404161 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 07:26:13.404682
769 07:26:13.405141 Model: Libre Computer AML-A311D-CC Alta
770 07:26:13.612598 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 07:26:13.636232 DRAM: 2 GiB (effective 3.8 GiB)
772 07:26:13.778961 Core: 408 devices, 31 uclasses, devicetree: separate
773 07:26:13.784777 WDT: Not starting watchdog@f0d0
774 07:26:13.817345 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 07:26:13.829655 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 07:26:13.833819 ** Bad device specification mmc 0 **
777 07:26:13.844974 Card did not respond to voltage select! : -110
778 07:26:13.851749 ** Bad device specification mmc 0 **
779 07:26:13.852135 Couldn't find partition mmc 0
780 07:26:13.861611 Card did not respond to voltage select! : -110
781 07:26:13.866897 ** Bad device specification mmc 0 **
782 07:26:13.867473 Couldn't find partition mmc 0
783 07:26:13.870990 Error: could not access storage.
784 07:26:14.215075 Net: eth0: ethernet@ff3f0000
785 07:26:14.215744 starting USB...
786 07:26:14.466843 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 07:26:14.467495 Starting the controller
788 07:26:14.472801 USB XHCI 1.10
789 07:26:16.635486 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 07:26:16.636260 bl2_stage_init 0x01
791 07:26:16.636736 bl2_stage_init 0x81
792 07:26:16.640988 hw id: 0x0000 - pwm id 0x01
793 07:26:16.641527 bl2_stage_init 0xc1
794 07:26:16.642002 bl2_stage_init 0x02
795 07:26:16.642450
796 07:26:16.646622 L0:00000000
797 07:26:16.647146 L1:20000703
798 07:26:16.647603 L2:00008067
799 07:26:16.648080 L3:14000000
800 07:26:16.652200 B2:00402000
801 07:26:16.652726 B1:e0f83180
802 07:26:16.653357
803 07:26:16.653874 TE: 58159
804 07:26:16.654344
805 07:26:16.657813 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 07:26:16.658298
807 07:26:16.658750 Board ID = 1
808 07:26:16.663410 Set A53 clk to 24M
809 07:26:16.663916 Set A73 clk to 24M
810 07:26:16.664419 Set clk81 to 24M
811 07:26:16.668999 A53 clk: 1200 MHz
812 07:26:16.669526 A73 clk: 1200 MHz
813 07:26:16.669975 CLK81: 166.6M
814 07:26:16.670412 smccc: 00012ab5
815 07:26:16.674574 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 07:26:16.680195 board id: 1
817 07:26:16.686062 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 07:26:16.696829 fw parse done
819 07:26:16.702712 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 07:26:16.745344 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 07:26:16.756252 PIEI prepare done
822 07:26:16.756806 fastboot data load
823 07:26:16.757265 fastboot data verify
824 07:26:16.761934 verify result: 266
825 07:26:16.767486 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 07:26:16.768099 LPDDR4 probe
827 07:26:16.768591 ddr clk to 1584MHz
828 07:26:16.774520 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 07:26:16.812805
830 07:26:16.813444 dmc_version 0001
831 07:26:16.819404 Check phy result
832 07:26:16.825267 INFO : End of CA training
833 07:26:16.825803 INFO : End of initialization
834 07:26:16.830905 INFO : Training has run successfully!
835 07:26:16.831435 Check phy result
836 07:26:16.836473 INFO : End of initialization
837 07:26:16.837003 INFO : End of read enable training
838 07:26:16.842039 INFO : End of fine write leveling
839 07:26:16.847649 INFO : End of Write leveling coarse delay
840 07:26:16.848231 INFO : Training has run successfully!
841 07:26:16.848693 Check phy result
842 07:26:16.853237 INFO : End of initialization
843 07:26:16.853758 INFO : End of read dq deskew training
844 07:26:16.858902 INFO : End of MPR read delay center optimization
845 07:26:16.864480 INFO : End of write delay center optimization
846 07:26:16.870070 INFO : End of read delay center optimization
847 07:26:16.870586 INFO : End of max read latency training
848 07:26:16.875679 INFO : Training has run successfully!
849 07:26:16.876285 1D training succeed
850 07:26:16.884983 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 07:26:16.932471 Check phy result
852 07:26:16.933109 INFO : End of initialization
853 07:26:16.953210 INFO : End of 2D read delay Voltage center optimization
854 07:26:16.973315 INFO : End of 2D read delay Voltage center optimization
855 07:26:17.025256 INFO : End of 2D write delay Voltage center optimization
856 07:26:17.074554 INFO : End of 2D write delay Voltage center optimization
857 07:26:17.080067 INFO : Training has run successfully!
858 07:26:17.080634
859 07:26:17.081100 channel==0
860 07:26:17.085593 RxClkDly_Margin_A0==88 ps 9
861 07:26:17.086120 TxDqDly_Margin_A0==98 ps 10
862 07:26:17.091237 RxClkDly_Margin_A1==88 ps 9
863 07:26:17.091746 TxDqDly_Margin_A1==88 ps 9
864 07:26:17.092317 TrainedVREFDQ_A0==74
865 07:26:17.097015 TrainedVREFDQ_A1==74
866 07:26:17.097602 VrefDac_Margin_A0==25
867 07:26:17.098044 DeviceVref_Margin_A0==40
868 07:26:17.102442 VrefDac_Margin_A1==25
869 07:26:17.103022 DeviceVref_Margin_A1==40
870 07:26:17.103485
871 07:26:17.103949
872 07:26:17.104506 channel==1
873 07:26:17.108085 RxClkDly_Margin_A0==88 ps 9
874 07:26:17.108663 TxDqDly_Margin_A0==98 ps 10
875 07:26:17.113620 RxClkDly_Margin_A1==88 ps 9
876 07:26:17.114124 TxDqDly_Margin_A1==108 ps 11
877 07:26:17.119218 TrainedVREFDQ_A0==77
878 07:26:17.119808 TrainedVREFDQ_A1==77
879 07:26:17.120290 VrefDac_Margin_A0==23
880 07:26:17.124766 DeviceVref_Margin_A0==37
881 07:26:17.125280 VrefDac_Margin_A1==24
882 07:26:17.130367 DeviceVref_Margin_A1==37
883 07:26:17.130920
884 07:26:17.131362 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 07:26:17.131834
886 07:26:17.163972 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
887 07:26:17.164630 2D training succeed
888 07:26:17.169571 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 07:26:17.175168 auto size-- 65535DDR cs0 size: 2048MB
890 07:26:17.175663 DDR cs1 size: 2048MB
891 07:26:17.180791 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 07:26:17.181468 cs0 DataBus test pass
893 07:26:17.186425 cs1 DataBus test pass
894 07:26:17.186905 cs0 AddrBus test pass
895 07:26:17.187338 cs1 AddrBus test pass
896 07:26:17.187764
897 07:26:17.192057 100bdlr_step_size ps== 420
898 07:26:17.192599 result report
899 07:26:17.197596 boot times 0Enable ddr reg access
900 07:26:17.203042 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 07:26:17.216413 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 07:26:17.788411 0.0;M3 CHK:0;cm4_sp_mode 0
903 07:26:17.789074 MVN_1=0x00000000
904 07:26:17.793967 MVN_2=0x00000000
905 07:26:17.799641 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 07:26:17.800224 OPS=0x10
907 07:26:17.800694 ring efuse init
908 07:26:17.801144 chipver efuse init
909 07:26:17.805246 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 07:26:17.810897 [0.018961 Inits done]
911 07:26:17.811430 secure task start!
912 07:26:17.811898 high task start!
913 07:26:17.815409 low task start!
914 07:26:17.815892 run into bl31
915 07:26:17.822057 NOTICE: BL31: v1.3(release):4fc40b1
916 07:26:17.829874 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 07:26:17.830422 NOTICE: BL31: G12A normal boot!
918 07:26:17.855332 NOTICE: BL31: BL33 decompress pass
919 07:26:17.861056 ERROR: Error initializing runtime service opteed_fast
920 07:26:19.093908
921 07:26:19.094580
922 07:26:19.102680 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 07:26:19.103188
924 07:26:19.103659 Model: Libre Computer AML-A311D-CC Alta
925 07:26:19.310903 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 07:26:19.334266 DRAM: 2 GiB (effective 3.8 GiB)
927 07:26:19.477134 Core: 408 devices, 31 uclasses, devicetree: separate
928 07:26:19.482316 WDT: Not starting watchdog@f0d0
929 07:26:19.515354 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 07:26:19.527660 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 07:26:19.532703 ** Bad device specification mmc 0 **
932 07:26:19.543069 Card did not respond to voltage select! : -110
933 07:26:19.550642 ** Bad device specification mmc 0 **
934 07:26:19.551183 Couldn't find partition mmc 0
935 07:26:19.558952 Card did not respond to voltage select! : -110
936 07:26:19.564547 ** Bad device specification mmc 0 **
937 07:26:19.565041 Couldn't find partition mmc 0
938 07:26:19.569539 Error: could not access storage.
939 07:26:19.912339 Net: eth0: ethernet@ff3f0000
940 07:26:19.913012 starting USB...
941 07:26:20.164966 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 07:26:20.165608 Starting the controller
943 07:26:20.171912 USB XHCI 1.10
944 07:26:21.726139 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
945 07:26:21.734555 scanning usb for storage devices... 0 Storage Device(s) found
947 07:26:21.786214 Hit any key to stop autoboot: 1
948 07:26:21.787112 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
949 07:26:21.787755 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
950 07:26:21.788424 Setting prompt string to ['=>']
951 07:26:21.789100 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
952 07:26:21.802109 0
953 07:26:21.803134 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
954 07:26:21.803678 Sending with 10 millisecond of delay
956 07:26:22.939360 => setenv autoload no
957 07:26:22.950362 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
958 07:26:22.955922 setenv autoload no
959 07:26:22.956785 Sending with 10 millisecond of delay
961 07:26:24.755062 => setenv initrd_high 0xffffffff
962 07:26:24.765910 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
963 07:26:24.766888 setenv initrd_high 0xffffffff
964 07:26:24.767658 Sending with 10 millisecond of delay
966 07:26:26.385143 => setenv fdt_high 0xffffffff
967 07:26:26.395755 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
968 07:26:26.396928 setenv fdt_high 0xffffffff
969 07:26:26.397723 Sending with 10 millisecond of delay
971 07:26:26.689817 => dhcp
972 07:26:26.700632 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
973 07:26:26.701502 dhcp
974 07:26:26.701969 Speed: 1000, full duplex
975 07:26:26.702413 BOOTP broadcast 1
976 07:26:26.948431 BOOTP broadcast 2
977 07:26:27.025690 DHCP client bound to address 192.168.6.33 (325 ms)
978 07:26:27.026322 Sending with 10 millisecond of delay
980 07:26:28.711196 => setenv serverip 192.168.6.2
981 07:26:28.722001 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
982 07:26:28.722991 setenv serverip 192.168.6.2
983 07:26:28.723735 Sending with 10 millisecond of delay
985 07:26:32.461413 => tftpboot 0x01080000 742849/tftp-deploy-06b6wwzt/kernel/uImage
986 07:26:32.472272 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
987 07:26:32.473221 tftpboot 0x01080000 742849/tftp-deploy-06b6wwzt/kernel/uImage
988 07:26:32.473708 Speed: 1000, full duplex
989 07:26:32.474165 Using ethernet@ff3f0000 device
990 07:26:32.475061 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
991 07:26:32.480385 Filename '742849/tftp-deploy-06b6wwzt/kernel/uImage'.
992 07:26:32.484216 Load address: 0x1080000
993 07:26:35.966781 Loading: *################################################## 43.6 MiB
994 07:26:35.967214 12.5 MiB/s
995 07:26:35.967434 done
996 07:26:35.971141 Bytes transferred = 45724224 (2b9b240 hex)
997 07:26:35.971655 Sending with 10 millisecond of delay
999 07:26:40.660126 => tftpboot 0x08000000 742849/tftp-deploy-06b6wwzt/ramdisk/ramdisk.cpio.gz.uboot
1000 07:26:40.670986 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
1001 07:26:40.672045 tftpboot 0x08000000 742849/tftp-deploy-06b6wwzt/ramdisk/ramdisk.cpio.gz.uboot
1002 07:26:40.672604 Speed: 1000, full duplex
1003 07:26:40.673101 Using ethernet@ff3f0000 device
1004 07:26:40.674013 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1005 07:26:40.682462 Filename '742849/tftp-deploy-06b6wwzt/ramdisk/ramdisk.cpio.gz.uboot'.
1006 07:26:40.683102 Load address: 0x8000000
1007 07:26:42.543236 Loading: *################################################# UDP wrong checksum 00000005 00001a09
1008 07:26:44.485549 UDP wrong checksum 000000ff 000006b2
1009 07:26:44.493575 UDP wrong checksum 000000ff 00009da4
1010 07:26:47.546047 T UDP wrong checksum 00000005 00001a09
1011 07:26:57.547134 T T UDP wrong checksum 00000005 00001a09
1012 07:27:00.590879 UDP wrong checksum 000000ff 0000366e
1013 07:27:00.602124 UDP wrong checksum 000000ff 0000ba60
1014 07:27:17.551796 T T T T UDP wrong checksum 00000005 00001a09
1015 07:27:37.556967 T T T
1016 07:27:37.557405 Retry count exceeded; starting again
1018 07:27:37.558268 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
1021 07:27:37.559194 end: 2.4 uboot-commands (duration 00:01:48) [common]
1023 07:27:37.559901 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1025 07:27:37.560497 end: 2 uboot-action (duration 00:01:48) [common]
1027 07:27:37.561295 Cleaning after the job
1028 07:27:37.561612 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742849/tftp-deploy-06b6wwzt/ramdisk
1029 07:27:37.562567 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742849/tftp-deploy-06b6wwzt/kernel
1030 07:27:37.578268 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742849/tftp-deploy-06b6wwzt/dtb
1031 07:27:37.579105 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742849/tftp-deploy-06b6wwzt/nfsrootfs
1032 07:27:37.602878 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742849/tftp-deploy-06b6wwzt/modules
1033 07:27:37.609481 start: 4.1 power-off (timeout 00:00:30) [common]
1034 07:27:37.610094 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1035 07:27:37.643524 >> OK - accepted request
1036 07:27:37.645394 Returned 0 in 0 seconds
1037 07:27:37.746166 end: 4.1 power-off (duration 00:00:00) [common]
1039 07:27:37.747193 start: 4.2 read-feedback (timeout 00:10:00) [common]
1040 07:27:37.747853 Listened to connection for namespace 'common' for up to 1s
1041 07:27:38.748773 Finalising connection for namespace 'common'
1042 07:27:38.749244 Disconnecting from shell: Finalise
1043 07:27:38.749532 =>
1044 07:27:38.850178 end: 4.2 read-feedback (duration 00:00:01) [common]
1045 07:27:38.850616 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/742849
1046 07:27:40.575563 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/742849
1047 07:27:40.576375 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.